diff --git a/libraries/STM32F0xx_CPAL_Driver/inc/stm32f0xx_i2c_cpal.h b/libraries/STM32F0xx_CPAL_Driver/inc/stm32f0xx_i2c_cpal.h deleted file mode 100644 --- a/libraries/STM32F0xx_CPAL_Driver/inc/stm32f0xx_i2c_cpal.h +++ /dev/null @@ -1,552 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_i2c_cpal.h - * @author MCD Application Team - * @version V1.2.0 - * @date 24-July-2014 - * @brief This file contains all the functions prototypes for the I2C firmware - * layer. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -/*========= CPAL library files includes =========*/ -#include "stm32f0xx_i2c_cpal_hal.h" -#include "stm32f0xx_i2c_cpal_conf.h" - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0XX_I2C_CPAL_H -#define __STM32F0XX_I2C_CPAL_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/*========= CPAL_Dev_TypeDef =========*/ -/* CPAL devices enumeration contains the device instances */ - -typedef enum -{ - CPAL_I2C1 = 0x00, /*!< Use I2C1 device */ - - CPAL_I2C2 = 0x01 /*!< Use I2C2 device */ - -}CPAL_DevTypeDef; - - -/*========= CPAL_Direction_TypeDef =========*/ -/* CPAL transfer directions enumeration is used to configure DMA channels - (TX and RX) if CPAL_PROGMODEL_DMA is selected or TX/RX interrupts - if CPAL_PROGMODEL_INTERRUPT is selected: - - If CPAL_DIRECTION_TX is selected only TX DMA Channel or TX Interrupt is configured - - If CPAL_DIRECTION_RX is selected only RX DMA Channel or RX Interrupt is configured - - If CPAL_DIRECTION_TXRX is selected both TX and Rx DMA Channels or Interrupts are configured.*/ - -typedef enum -{ - CPAL_DIRECTION_TX = 0x01, /*!pI2C_Struct->I2C_Speed = 100000; - CPAL_I2C_Init(&I2C1_DevStructure); */ -}CPAL_InitTypeDef; - - -/*========= Table containing all I2C device structures =========*/ -extern CPAL_InitTypeDef* I2C_DevStructures[]; - - -/*========= CPAL_Global_Device_Structures =========*/ -/* CPAL Global Device Structures are the Global default structures which - are used to handle devices configuration and status.*/ - -#ifdef CPAL_USE_I2C1 -extern CPAL_InitTypeDef I2C1_DevStructure; -#endif /* CPAL_USE_I2C1 */ - -#ifdef CPAL_USE_I2C2 -extern CPAL_InitTypeDef I2C2_DevStructure; -#endif /* CPAL_USE_I2C2 */ - -/* Exported constants --------------------------------------------------------*/ - -/*========= CPAL_Options_TypeDef =========*/ -/* CPAL Options defines contains configuration options which can be affected - to wCPAL_Options which is a bit-field argument so any combination of these - parameters can be selected. If one option is not selected then the relative - feature is disabled. - There are common options and device specific options.*/ - -#define CPAL_OPT_I2C_DUALADDR ((uint32_t)0x00000001) /*!
© COPYRIGHT 2014 STMicroelectronics
- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0XX_I2C_CPAL_CONF_H -#define __STM32F0XX_I2C_CPAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/*======================================================================================================================================= - User NOTES -========================================================================================================================================= - -------------------------------- -1. How To use the CPAL Library: -------------------------------- - -------- Refer to the user manual of the library and (eventually) the example to check if - this firmware is appropriate for your hardware (device and (eventually) evaluation board) - - - Section 1 : Select the Device instances to be used and the total number of devices - - - Section 2 : Configure Transfer Options - - - Section 3 : Select and configure transfer and error user Callbacks - - - Section 4 : Configure Timeout mechanism and TimeoutCallback - - - Section 5 : Configure Interrupt Priority Offset - - - Section 6 : Configure CPAL_LOG Macro - ------- After configuring CPAL firmware functionality , You should proceed by configuring hardware used with CPAL - (please refer to stm32f0xx_i2c_cpal_hal.h file). - ------- After configuring CPAL Firmware Library, you should follow these steps to use the Firmware correctly : - - -1- STRUCTURE INITIALIZATION - Start by initializing the Device. To perform this action, the global variable PPPx_DevStructure declared - in CPAL Firmware as CPAL_InitTypeDef (I2C1_DevStructure for I2C1, I2C2_DevStructure for I2C2 ...) must be used. - There are two ways to proceed : - - ** Call the function CPAL_PPP_StructInit() using as parameter PPPx_DevStructure (where PPP = device type (ie. I2C...) - and where x could be 1 for PPP1, 2 for PPP2 ...). This function sets the default values for all fields of this structure. - - Default values for I2C devices are : - I2Cx_DevStructure.CPAL_Direction = CPAL_DIRECTION_TXRX - I2Cx_DevStructure.CPAL_Mode = CPAL_MODE_MASTER - I2Cx_DevStructure.CPAL_ProgModel = CPAL_PROGMODEL_DMA - I2Cx_DevStructure.pCPAL_TransferTx = pNULL - I2Cx_DevStructure.pCPAL_TransferRx = pNULL - I2Cx_DevStructure.CPAL_State = CPAL_STATE_DISABLED - I2Cx_DevStructure.wCPAL_DevError = CPAL_I2C_ERR_NONE - I2Cx_DevStructure.wCPAL_Options = 0 (all options disabled) - I2Cx_DevStructure.wCPAL_Timeout = CPAL_TIMEOUT_DEFAULT - I2Cx_DevStructure.pCPAL_I2C_Struct->I2C_Mode = I2C_Mode_I2C - I2Cx_DevStructure.pCPAL_I2C_Struct->I2C_AnalogFilter = I2C_AnalogFilter_Enable - I2Cx_DevStructure.pCPAL_I2C_Struct->I2C_DigitalFilter = 0x00 - I2Cx_DevStructure.pCPAL_I2C_Struct->I2C_OwnAddress1 = 0 - I2Cx_DevStructure.pCPAL_I2C_Struct->I2C_Ack = I2C_Ack_Enable - I2Cx_DevStructure.pCPAL_I2C_Struct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit - - - pCPAL_TransferTx and pCPAL_TransferRx fields have to be updated in order to point to valid structures - (these structures should be local/global variables in the user application). - - ** Another way of configuration is without calling CPAL_PPP_StructInit() function. - Declare the following structures: - - A PPP_InitTypeDef structure for the device configuration (ie. I2C_InitTypeDef structure) - - One or two CPAL_TransferTypeDef variables (one for Tx and one for Rx). - - Use the extern structure provided by the CPAL library: PPPx_InitStructure (ie. I2C1_DevStructure). - Fill in all the fields for these structures (one by one). - Use the pointers to these structures to fill in the fields pCPAL_PPP_Struct and pCPAL_TransferTx and/or - pCPAL_TransferRx of the PPPx_DevStructure. - After that CPAL_State must be set to CPAL_STATE_DISABLED. - Finally, call the CPAL_PPP_Init() with pointer to the PPPx_DevStructure as argument. - - Example: - // Declare local structures - I2C_InitTypeDef I2C1_InitStructure; - CPAL_TransferTypeDef TX_Transfer, RX_Transfer; - // Fill in all the fields of to these structures - I2Cx_InitStructure.I2C_Timing = 0X50321312; - I2Cx_InitStructure.I2C_Mode = I2C_Mode_I2C; - I2Cx_InitStructure.I2C_AnalogFilter = I2C_AnalogFilter_Disable; - ..... - TX_Transfer.pbBuffer = 0; - TX_Transfer.wNumData = 0; - ..... - RX_Transfer.pbBuffer = 0; - RX_Transfer.wNumData = 0; - ..... - // Use these structures and fill all fields of I2C1_DevStructure. - I2C1_DevStructure.CPAL_Dev = CPAL_I2C1; - I2C1_DevStructure.CPAL_Direction = CPAL_DIRECTION_TXRX; - I2C1_DevStructure.CPAL_Mode = CPAL_MODE_SLAVE; - I2C1_DevStructure.wCPAL_Options = CPAL_OPT_DMATX_TCIT | CPAL_OPT_DMATX_HTIT ; - ..... - I2C1_DevStructure.pCPAL_TransferTx = &TX_Transfer; - I2C1_DevStructure.pCPAL_TransferRx = &RX_Transfer; - I2C1_DevStructure.pCPAL_I2C_Struct = &I2C1_InitStructure; - ... - I2C1_DevStructure.wCPAL_State = CPAL_STATE_DISABLED; - .... - CPAL_I2C_Init(&I2C1_DevStructure); - - -2- DEVICE CONFIGURATION - Call the function CPAL_PPP_Init() to configure the selected device with the selected configuration by calling - CPAL_PPP_Init(). This function also enables device clock and initialize all related peripherals ( GPIO, DMA , IT and NVIC ). - This function tests on CPAL_State, if it is equal to CPAL_STATE_BUSY it exit, otherwise device initialization is - performed and CPAL_State is set to CPAL_STATE_READY. - This function returns CPAL_PASS state when the operation is correctly performed, or CPAL_FAIL when the current state of the - device doesn't allow configuration (ie. state different from READY, DISABLED or ERROR). - After calling this function, you may check on the new state of device, when it is equal to CPAL_STATE_READY, Transfer operations - can be started, otherwise you can call CPAL_PPP_DeInit() to deinitialize device and call CPAL_PPP_Init() once again. - - -3- READ / WRITE OPERATIONS - Call the function CPAL_PPP_Write() or CPAL_PPP_Read() to perform transfer operations. - These functions handle communication events using device event interrupts (independently of programming model used: DMA, - Interrupt). These functions start preparing communication (send start condition, send salve address in case of - master mode ...) if connection is established between devices CPAL_State is set CPAL_STATE_BUSY_XX and data transfer starts. - By default, Error interrupts are enabled to manage device errors (Error interrupts can be disabled by affecting - CPAL_OPT_I2C_ERRIT_DISABLE to wCPAL_Options). When transfer is completed successfully, CPAL_State is set to CPAL_STATE_READY - and another operation can be started. - These functions return CPAL_PASS if the current state of the device allows starting a new operation and the operation is correctly - started (but not finished). It returns CPAL_FAIL when the state of the device doesn't allow starting a new communication (ie. - BUSY, DISABLED, ERROR) or when an error occurs during operation start. - Once operation is started, user application may perform other tasks while CPAL is sending/receiving data on device through interrupt - or DMA. - - -4- DEVICE DEINITIALIZATION - When transfer operations are finished, you may call CPAL_PPP_DeInit() to disable PPPx device and related resources - ( GPIO, DMA , IT and NVIC). CPAL_State is then set to CPAL_STATE_DISABLED by this function. - - - ------- Callbacks are routines that let you insert your own code in different stages of communication and for handling - device errors. Their prototypes are declared by the CPAL library (if the relative define in this stm32f0xx_i2c_cpal_conf.h is enabled) - but their body is not implemented by CPAL library. It may be done by user when needed. - There are three types of Callbacks: Transfer User Callbacks, Error User Callbacks and Timeout User Callbacks: - - -a- Transfer User Callbacks : - - ** CPAL_I2C_TX_UserCallback(CPAL_InitTypeDef* pDevInitStruct) - This function is called before sending data when Interrupt Programming Model is selected. - - ** CPAL_I2C_RX_UserCallback(CPAL_InitTypeDef* pDevInitStruct) - This function is called after receiving data when Interrupt Programming Model is selected. - - ** CPAL_I2C_TXTC_UserCallback(CPAL_InitTypeDef* pDevInitStruct) - ** CPAL_I2C_RXTC_UserCallback(CPAL_InitTypeDef* pDevInitStruct) - These functions are called when a transfer is complete when using Interrupt programming model or DMA - programming model. - - ** CPAL_I2C_DMATXTC_UserCallback(CPAL_InitTypeDef* pDevInitStruct) - ** CPAL_I2C_DMATXTC_UserCallback(CPAL_InitTypeDef* pDevInitStruct) - These functions are called when Transfer complete Interrupt occurred in transmission/reception operation - if DMA Programming Model is selected - - ** CPAL_I2C_DMATXHT_UserCallback(CPAL_InitTypeDef* pDevInitStruct) - ** CPAL_I2C_DMARXHT_UserCallback(CPAL_InitTypeDef* pDevInitStruct) - These functions are called when Half transfer Interrupt occurred in transmission/reception operation - if DMA Programming Model is selected. - - ** CPAL_I2C_DMATXTE_UserCallback(CPAL_InitTypeDef* pDevInitStruct) - ** CPAL_I2C_DMARXTE_UserCallback(CPAL_InitTypeDef* pDevInitStruct) - These functions are called when a transfer error Interrupt occurred in transmission/reception operation - if DMA Programming Model is selected. - - ** CPAL_I2C_GENCALL_UserCallback(CPAL_InitTypeDef* pDevInitStruct) - This function is called when an Address Event interrupt occurred and General Call Address Flag is set - (available in Slave mode only and when the option CPAL_OPT_I2C_GENCALL is enabled). - - ** CPAL_I2C_DUALF_UserCallback(CPAL_InitTypeDef* pDevInitStruct) - This function is called when an Address Event interrupt occurred and Dual Address Flag is set - (available in Slave mode only and when the option CPAL_OPT_I2C_DUALADDR is enabled). - - - -b- Error User Callbacks : - - ** CPAL_I2C_ERR_UserCallback(CPAL_DevTypeDef pDevInstance, uint32_t Device_Error) - This function is called either when an Error Interrupt occurred (If Error Interrupts enabled) or after - a read or write operations to handle device errors (If Error Interrupts disabled). This callback - can be used to handle all device errors. It is available only when the define USE_SINGLE_ERROR_CALLBACK - is enabled (Section 5). - - ** CPAL_I2C_BERR_UserCallback(CPAL_DevTypeDef pDevInstance) - This function is called either when a Bus Error Interrupt occurred (If Error Interrupts enabled) or - after a read or write operations to handle this error (If Error Interrupts disabled). This callback is - available only when USE_MULTIPLE_ERROR_CALLBACK is enabled (Section 5). - - ** CPAL_I2C_ARLO_UserCallback(CPAL_DevTypeDef pDevInstance) - This function is called either when an Arbitration Lost Interrupt occurred (If Error Interrupts - enabled) or after a read or write operations to handle this error (If Error Interrupts disabled). - - ** CPAL_I2C_OVR_UserCallback(CPAL_DevTypeDef pDevInstance) - This function is called either when an Overrun Interrupt occurred (If Error Interrupts enabled) or - after a read or write operations to handle this error (If Error Interrupts disabled). This callback is - available only when USE_MULTIPLE_ERROR_CALLBACK is enabled (Section 5). - - ** CPAL_I2C_AF_UserCallback(CPAL_DevTypeDef pDevInstance) - This function is called either when an Acknowledge Failure Interrupt occurred (If Error Interrupts - enabled) or after a read or write operations to handle this error (If Error Interrupts disabled). - This callback is available only when USE_MULTIPLE_ERROR_CALLBACK is enabled (Section 5). - - - -c- Timeout User Callbacks : - ** CPAL_TIMEOUT_UserCallback(void) - This function is called when a Timeout occurred in communication. - - ** CPAL_TIMEOUT_INIT() - This function allows to configure and enable the counting peripheral/function (ie. SysTick Timer) - It is called into all CPAL_PPP_Init() functions. - - ** CPAL_TIMEOUT_DEINIT() - This function allow to free the resources of counting peripheral/function and stop the count. - (ie. disable the SysTick timer and its interrupt). - - ** CPAL_PPP_TIMEOUT_Manager() - WARNING: DO NOT IMPLEMENT THIS FUNCTION (already implemented in CPAL drivers) - This function is already implemented in the CPAL drivers (stm32f0xx_i2c_cpal.c file). It should be called periodically - (using the count mechanism interrupt for example). This function checks all PPP devices and - manages timeout conditions. In case of timeout occurring, this function calls the - CPAL_TIMEOUT_UserCallback() function that may be implemented by user to manage the cases of - timeout errors (ie. reset the device/microcontroller...). - In order to facilitate implementation, this function (instead to be called periodically by user - application), may be mapped directly to a periodic event/interrupt: - Example: - #define CPAL_I2C_TIMEOUT_Manager SysTick_Handler - - ** Note ** : when mapping CPAL_I2C_TIMEOUT_Manager to a periodic event/interrupt, the prototype - of this event/interrupt should be added. Here below an example when SysTick_Handler - is used to handle timeout mechanism : - #ifndef CPAL_I2C_TIMEOUT_Manager - void CPAL_I2C_TIMEOUT_Manager(void); - #else - void SysTick_Handler(void); - #endif - - To implement Transfer and Error Callbacks, you should comment relative defines in Section 4 and implement Callback function (body) into - your application (their prototypes are declared in stm32f0xx_i2c_cpal.h file). - - Example: How to implement CPAL_I2C_TX_UserCallback() callback: - - -1- Comment the relative define in this file : - //#define CPAL_I2C_TX_UserCallback (void) - - -2- Add CPAL_I2C_TX_UserCallback code source in application file ( example : main.c ) - void CPAL_I2C_TX_UserCallback (CPAL_InitTypeDef* pDevInitStruct) - { - // - // user code - // - } - - There are two types of Error Callbacks : - -1- Single Error Callback : Only one Callback is used to manage all device errors. - -2- Multiple Error Callback : Each device error is managed by its own separate Callback. - - Example of using CPAL_I2C_BERR_UserCallback : - - -1- Select Multiple Error Callback type : - //#define USE_SINGLE_ERROR_CALLBACK - #define USE_MULTIPLE_ERROR_CALLBACK - - -2- Comment define relative to CPAL_I2C_BERR_UserCallback in stm32f0xx_i2c_cpal_conf.h.h file: - //#define CPAL_I2C_BERR_UserCallback (void) - - -3- Add CPAL_I2C_BERR_UserCallback code source in application file ( example: main.c ) - void CPAL_I2C_BERR_UserCallback (CPAL_DevTypeDef pDevInstance) - { - // - // user code - // - } - ------- The driver API functions Prototypes are in stm32f0xx_i2c_cpal.h file. - -*********END OF User Notes***************************************************************************************************************/ - - - - -/*======================================================================================================================================= - CPAL Firmware Functionality Configuration -=========================================================================================================================================*/ - -/*-----------------------------------------------------------------------------------------------------------------------*/ -/*-----------------------------------------------------------------------------------------------------------------------*/ - -/* -- Section 1 : **** I2Cx Device Selection **** - - Description: This section provide an easy way to select I2Cx devices in user application. - Choosing device allows to save memory resources. - If you need I2C1 device, uncomment relative define: #define CPAL_USE_I2C1. - All available I2Cx device can be used at the same time. - At least one I2C device should be selected.*/ - -#define CPAL_USE_I2C1 /*CTRL = 0 /*Libraries->Small printf - // set to 'Yes') calls __io_putchar() - #define PUTCHAR_PROTOTYPE int __io_putchar(int ch) - #else - #define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f) - #endif - - WARNING Be aware that enabling this feature may slow down the communication process, increase the code size - significantly, and may in some cases cause communication errors (when print/display mechanism is too slow)*/ - - -/* To Enable CPAL_DEBUG Option Uncomment the define below */ -//#define CPAL_DEBUG - -#ifdef CPAL_DEBUG -#define CPAL_LOG(Str) printf(Str) -#include /* This header file must be included when using CPAL_DEBUG option */ -#else -#define CPAL_LOG(Str) ((void)0) -#endif /* CPAL_DEBUG */ - - -/*-----------------------------------------------------------------------------------------------------------------------*/ -/*-----------------------------------------------------------------------------------------------------------------------*/ - -/*********END OF CPAL Firmware Functionality Configuration****************************************************************/ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0XX_I2C_CPAL_CONF_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_CPAL_Driver/inc/stm32f0xx_i2c_cpal_hal.h b/libraries/STM32F0xx_CPAL_Driver/inc/stm32f0xx_i2c_cpal_hal.h deleted file mode 100644 --- a/libraries/STM32F0xx_CPAL_Driver/inc/stm32f0xx_i2c_cpal_hal.h +++ /dev/null @@ -1,631 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_i2c_cpal_hal.h - * @author MCD Application Team - * @version V1.2.0 - * @date 24-July-2014 - * @brief This file contains all the functions prototypes for the CPAL_I2C_HAL - * firmware layer. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef ___STM32F0XX_I2C_CPAL_HAL_H -#define ___STM32F0XX_I2C_CPAL_HAL_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -/*========= STM32 Standard library files includes =========*/ -#include "stm32f0xx.h" -#include "stm32f0xx_i2c.h" -#include "stm32f0xx_dma.h" -#include "stm32f0xx_gpio.h" -#include "stm32f0xx_rcc.h" -#include "stm32f0xx_misc.h" - -/*========= CPAL library files includes =========*/ -#include "stm32f0xx_i2c_cpal.h" - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/*====================================================================================================================================== - CPAL Hardware Configuration -========================================================================================================================================*/ - -/* ------ Configure the communication device and all related peripherals ( GPIO Pin, DMA Channels, - NVIC Priority) with this file, by referring to configuration Sections: - - - Section 1 : Select the pins to be used for each device instance. - - - Section 2 : Select TX and RX DMA Channels (if DMA mode will be used). - - - Section 3 : Set device's Events, Errors and DMA Interrupts Priorities. */ - - -/*-----------------------------------------------------------------------------------------------------------------------*/ -/*-----------------------------------------------------------------------------------------------------------------------*/ - -/* -- Section 1 : **** Device IO Pins Selection **** - - Description: This section allows user to choose IO Pins for each device if possible (in accordance with - used product: some products have only one possibility for the IO pins). - Each device instance (I2C1, I2C2 ..) has its specific defines: one for each Pin. - For each device instance, you will change existing defines with adequate IO Pins and Port - ( Refer to Product Pin mapping in related datasheet).*/ - -/* To configure SCL and SDA Pin change these defines with adequate value : - -#define CPAL_I2C1_SCL_GPIO_PORT GPIOX (X : Name of the GPIO PORT (A,B,C,....)) -#define CPAL_I2C1_SCL_GPIO_CLK RCC_APB2Periph_GPIOX (X : Name of the GPIO PORT (A,B,C,....)) -#define CPAL_I2C1_SCL_GPIO_PIN GPIO_Pin_X (X : Pin number (1,2,3,....)) -#define CPAL_I2C1_SCL_GPIO_PINSOURCE GPIO_PinSourceX (X : Pin number (1,2,3,....)) - -#define CPAL_I2C1_SDA_GPIO_PORT GPIOX (X : Name of the GPIO PORT (A,B,C,....)) -#define CPAL_I2C1_SDA_GPIO_CLK RCC_APB2Periph_GPIOX (X : Name of the GPIO PORT (A,B,C,....)) -#define CPAL_I2C1_SDA_GPIO_PIN GPIO_Pin_X (X : Pin number (1,2,3,....)) -#define CPAL_I2C1_SDA_GPIO_PINSOURCE GPIO_PinSourceX (X : Pin number (1,2,3,....)) */ - -/* IO Pins selection possibilities - -|--------|---------|--------------|-----------|------------------|-------------------------| -| Device | I2C PIN | GPIO_PIN | GPIO_PORT | GPIO_PinSource | GPIO_CLK | -|--------|---------|--------------|-----------|------------------|-------------------------| -| | | GPIO_Pin_6 | GPIOB | GPIO_PinSource6 | RCC_AHBPeriph_GPIOB | -| | SCL |--------------|-----------|------------------|-------------------------| -| | | GPIO_Pin_8 | GPIOB | GPIO_PinSource8 | RCC_AHBPeriph_GPIOB | -| I2C1 |---------|--------------|-----------|------------------|-------------------------| -| | | GPIO_Pin_7 | GPIOB | GPIO_PinSource7 | RCC_AHBPeriph_GPIOB | -| | SDA |--------------|-----------|------------------|-------------------------| -| | | GPIO_Pin_9 | GPIOB | GPIO_PinSource9 | RCC_AHBPeriph_GPIOB | -|--------|---------|--------------|-----------|------------------|-------------------------| -| | | GPIO_Pin_10 | GPIOB | GPIO_PinSource10 | RCC_AHBPeriph_GPIOB | -| | SCL |--------------|-----------|------------------|-------------------------| -| | | GPIO_Pin_6 | GPIOF | GPIO_PinSource6 | RCC_AHBPeriph_GPIOF | -| I2C2 |---------|--------------|-----------|------------------|-------------------------| -| | | GPIO_Pin_11 | GPIOB | GPIO_PinSource11 | RCC_AHBPeriph_GPIOB | -| | SDA |--------------|-----------|------------------|-------------------------| -| | | GPIO_Pin_7 | GPIOF | GPIO_PinSource9 | RCC_AHBPeriph_GPIOF | -|--------|---------|--------------|-----------|------------------|-------------------------| - - */ - - -/*----------- I2C1 Device -----------*/ - -#define CPAL_I2C1_SCL_GPIO_PORT GPIOB -#define CPAL_I2C1_SCL_GPIO_CLK RCC_AHBPeriph_GPIOB -#define CPAL_I2C1_SCL_GPIO_PIN GPIO_Pin_6 -#define CPAL_I2C1_SCL_GPIO_PINSOURCE GPIO_PinSource6 - -#define CPAL_I2C1_SDA_GPIO_PORT GPIOB -#define CPAL_I2C1_SDA_GPIO_CLK RCC_AHBPeriph_GPIOB -#define CPAL_I2C1_SDA_GPIO_PIN GPIO_Pin_7 -#define CPAL_I2C1_SDA_GPIO_PINSOURCE GPIO_PinSource7 - -/*-----------I2C2 Device -----------*/ - -#define CPAL_I2C2_SCL_GPIO_PORT GPIOB -#define CPAL_I2C2_SCL_GPIO_CLK RCC_AHBPeriph_GPIOB -#define CPAL_I2C2_SCL_GPIO_PIN GPIO_Pin_10 -#define CPAL_I2C2_SCL_GPIO_PINSOURCE GPIO_PinSource10 - -#define CPAL_I2C2_SDA_GPIO_PORT GPIOB -#define CPAL_I2C2_SDA_GPIO_CLK RCC_AHBPeriph_GPIOB -#define CPAL_I2C2_SDA_GPIO_PIN GPIO_Pin_11 -#define CPAL_I2C2_SDA_GPIO_PINSOURCE GPIO_PinSource11 - -/*-----------------------------------------------------------------------------------------------------------------------*/ -/*-----------------------------------------------------------------------------------------------------------------------*/ - -/* -- Section 2 : **** Device TX and RX DMA Channels Selection **** - - Description: This section allows user to choose TX and RX DMA Channels if possible (in accordance with - used product) for each device. - Each device instance (I2C1, I2C2 ..) has its specific defines: one for DMA TX Channel and - another one for DMA RX Channel. - For each device instance, you find all TX an RX DMA Channel possibilities ( Refer to Product - Reference Manual).*/ - -/* DMA Channel selection possibilities - -|--------|---------|----------------| -| Device | Channel | DMA Channel | -|--------|---------|----------------| -| | TX | DMA1_Channel2 | -| I2C1 |---------|----------------| -| | RX | DMA1_Channel3 | -|--------|---------|----------------| -| | TX | DMA1_Channel4 | -| I2C2 |---------|----------------| -| | RX | DMA1_Channel5 | -|--------|---------|----------------|*/ - -/* I2Cx TX and RX DMA channels for STM32F0XX family are fixed */ - -/*----------- I2C1 Device -----------*/ -#define CPAL_I2C1_DMA_TX_Channel DMA1_Channel2 -#define CPAL_I2C1_DMA_RX_Channel DMA1_Channel3 - -/*----------- I2C2 Device -----------*/ -#define CPAL_I2C2_DMA_TX_Channel DMA1_Channel4 -#define CPAL_I2C2_DMA_RX_Channel DMA1_Channel5 - -/*-----------------------------------------------------------------------------------------------------------------------*/ -/*-----------------------------------------------------------------------------------------------------------------------*/ - -/* -- Section 3 : **** I2C and DMA Interrupts Priority Selection **** - - Description: This section allows user to select Interrupt Priority of I2C Event Interrupts and DMA Interrupts. - - Make sure that the following rules are always respected: - - I2C event and error interrupts should be interruptible (mainly, the timeout interrupt should - be able to interrupt all device ISR) - - I2C Error interrupt priority should be higher than Event interrupt - - The timeout mechanism interrupt priority should be the highest one and it should be able to - interrupt any other ISR. - - It is advised that DMA interrupts have higher priority than the device event interrupts.*/ - - -/*----------- I2Cx Interrupt Priority -------------*/ - -/*----------- I2C1 Device -----------*/ -#define I2C1_IT_PRIO I2C1_IT_OFFSET_PREPRIO + 2 /* I2C1 IT PRIORITY */ -#define I2C1_IT_DMA_PRIO I2C1_IT_OFFSET_PREPRIO + 0 /* I2C1 DMA PRIORITY */ - -/*----------- I2C2 Device -----------*/ -#define I2C2_IT_PRIO I2C2_IT_OFFSET_PREPRIO + 2 /* I2C2 IT PRIORITY */ -#define I2C2_IT_DMA_PRIO I2C2_IT_OFFSET_PREPRIO + 0 /* I2C2 DMA PRIORITY */ - - -/*-----------------------------------------------------------------------------------------------------------------------*/ -/*-----------------------------------------------------------------------------------------------------------------------*/ - -/*****END OF CPAL Hardware Configuration***************************************************************************************************/ - - /* !WARNING!: - --------- - The following code should not be modified by user. - Any modification may cause Library dysfunction. - */ - -/*========= Common Defines =========*/ - -/* This define set the number of I2C devices that can be used with this product family */ -#define CPAL_I2C_DEV_NUM 2 - -/* This define is used to enable DMA Channel */ -#define CPAL_DMA_CCR_EN DMA_CCR_EN - -/* This define is used to check if DMA interrupt option are enabled */ -#define CPAL_OPT_DMA_IT_MASK ((uint32_t)0x00003F00) - -/* This define is used to check I2C errors (BERR, ARLO and OVR) */ -#define CPAL_I2C_STATUS_ERR_MASK ((uint32_t)0x00000700) /*!< I2C errors Mask */ - -/* This define is used to check I2C events (TXIS, RXNE, ADDR, NACKF, STOPF, TC and TCR) */ -#define CPAL_I2C_STATUS_EVT_MASK ((uint16_t)0x0000000FE) /*!< I2C event Mask for Status Register 1 */ - -/* This define is used to check if DMA TX interrupt are selected */ -#define CPAL_OPT_I2C_DMA_TX_IT_MASK ((uint32_t)0x00000700) - -/* This define is used to check if DMA RX interrupt are selected */ -#define CPAL_OPT_I2C_DMA_RX_IT_MASK ((uint32_t)0x00003800) - - /* I2C Event Defines */ -#define CPAL_I2C_EVT_ADDR I2C_ISR_ADDR /*!
CCR |= CPAL_DMA_CCR_EN - -#define __CPAL_I2C_HAL_DISABLE_DMATX(device) CPAL_I2C_DMA_TX_Channel[(device)]->CCR &= ~CPAL_DMA_CCR_EN - -#define __CPAL_I2C_HAL_ENABLE_DMARX(device) CPAL_I2C_DMA_RX_Channel[(device)]->CCR |= CPAL_DMA_CCR_EN - -#define __CPAL_I2C_HAL_DISABLE_DMARX(device) CPAL_I2C_DMA_RX_Channel[(device)]->CCR &= ~CPAL_DMA_CCR_EN - -/* DMA interrupts enable/disable */ - -#define __I2C_HAL_ENABLE_DMATX_TCIT(device) CPAL_I2C_DMA_TX_Channel[(device)]->CCR |= DMA_IT_TC - -#define __I2C_HAL_ENABLE_DMATX_HTIT(device) CPAL_I2C_DMA_TX_Channel[(device)]->CCR |= DMA_IT_HT - -#define __I2C_HAL_ENABLE_DMATX_TEIT(device) CPAL_I2C_DMA_TX_Channel[(device)]->CCR |= DMA_IT_TE - -#define __I2C_HAL_ENABLE_DMARX_TCIT(device) CPAL_I2C_DMA_RX_Channel[(device)]->CCR |= DMA_IT_TC - -#define __I2C_HAL_ENABLE_DMARX_HTIT(device) CPAL_I2C_DMA_RX_Channel[(device)]->CCR |= DMA_IT_HT - -#define __I2C_HAL_ENABLE_DMARX_TEIT(device) CPAL_I2C_DMA_RX_Channel[(device)]->CCR |= DMA_IT_TE - -/* DMA interrupts flag management */ - -#define __CPAL_I2C_HAL_GET_DMATX_IT(device) (uint32_t)(CPAL_I2C_DMA[(device)]->ISR & (CPAL_I2C_DMA_TX_TC_FLAG[(device)] \ - | CPAL_I2C_DMA_TX_HT_FLAG[(device)] | CPAL_I2C_DMA_TX_TE_FLAG[(device)])) - -#define __CPAL_I2C_HAL_GET_DMATX_TCIT(device) (uint32_t)(CPAL_I2C_DMA[(device)]->ISR & CPAL_I2C_DMA_TX_TC_FLAG [(device)]) - -#define __CPAL_I2C_HAL_GET_DMATX_HTIT(device) (uint32_t)(CPAL_I2C_DMA[(device)]->ISR & CPAL_I2C_DMA_TX_HT_FLAG [(device)]) - -#define __CPAL_I2C_HAL_GET_DMATX_TEIT(device) (uint32_t)(CPAL_I2C_DMA[(device)]->ISR & CPAL_I2C_DMA_TX_TE_FLAG [(device)]) - -#define __CPAL_I2C_HAL_GET_DMARX_IT(device) (uint32_t)(CPAL_I2C_DMA[(device)]->ISR & (CPAL_I2C_DMA_RX_TC_FLAG[(device)] \ - | CPAL_I2C_DMA_RX_HT_FLAG[(device)] | CPAL_I2C_DMA_RX_TE_FLAG[(device)])) - -#define __CPAL_I2C_HAL_GET_DMARX_TCIT(device) (uint32_t)(CPAL_I2C_DMA[(device)]->ISR & CPAL_I2C_DMA_RX_TC_FLAG [(device)]) - -#define __CPAL_I2C_HAL_GET_DMARX_HTIT(device) (uint32_t)(CPAL_I2C_DMA[(device)]->ISR & CPAL_I2C_DMA_RX_HT_FLAG [(device)]) - -#define __CPAL_I2C_HAL_GET_DMARX_TEIT(device) (uint32_t)(CPAL_I2C_DMA[(device)]->ISR & CPAL_I2C_DMA_RX_TE_FLAG [(device)]) - -#define __CPAL_I2C_HAL_CLEAR_DMATX_IT(device) CPAL_I2C_DMA[(device)]->IFCR = (CPAL_I2C_DMA_TX_TC_FLAG[(device)] \ - | CPAL_I2C_DMA_TX_HT_FLAG[(device)] | CPAL_I2C_DMA_TX_TE_FLAG[(device)]) - -#define __CPAL_I2C_HAL_CLEAR_DMARX_IT(device) CPAL_I2C_DMA[(device)]->IFCR = (CPAL_I2C_DMA_RX_TC_FLAG[(device)] \ - | CPAL_I2C_DMA_RX_HT_FLAG[(device)] | CPAL_I2C_DMA_RX_TE_FLAG[(device)]) - -/* Get DMA data counter */ - -#define __CPAL_I2C_HAL_DMATX_GET_CNDT(device) (uint32_t)(CPAL_I2C_DMA_TX_Channel[(device)]->CNDTR) - -#define __CPAL_I2C_HAL_DMARX_GET_CNDT(device) (uint32_t)(CPAL_I2C_DMA_RX_Channel[(device)]->CNDTR) - - -/*========= I2C =========*/ - -/* I2C enable/disable */ - -#define __CPAL_I2C_HAL_ENABLE_DEV(device) CPAL_I2C_DEVICE[(device)]->CR1 |= I2C_CR1_PE - -#define __CPAL_I2C_HAL_DISABLE_DEV(device) CPAL_I2C_DEVICE[(device)]->CR1 &= ~I2C_CR1_PE - -/* I2C software reset */ - -#define __CPAL_I2C_HAL_SWRST(device) CPAL_I2C_DEVICE[(device)]->CR1 |= I2C_CR1_SWRST; \ - CPAL_I2C_DEVICE[(device)]->CR1 &= ~I2C_CR1_SWRST - -/* I2C Wakeup option */ - -#define __CPAL_I2C_HAL_ENABLE_WAKEUP(device) CPAL_I2C_DEVICE[(device)]->CR1 |= I2C_CR1_WUPEN - -#define __CPAL_I2C_HAL_DISABLE_WAKEUP(device) CPAL_I2C_DEVICE[(device)]->CR1 &= ~I2C_CR1_WUPEN - -/* I2C interrupts enable/disable */ - -#define __CPAL_I2C_HAL_DISABLE_ALLIT(device) CPAL_I2C_DEVICE[(device)]->CR1 &= ~(I2C_CR1_TXIE | I2C_CR1_RXIE | I2C_CR1_ADDRIE | \ - I2C_CR1_STOPIE | I2C_CR1_TCIE | I2C_CR1_ERRIE | I2C_CR1_NACKIE) - -#define __CPAL_I2C_HAL_ENABLE_ERRIT(device) CPAL_I2C_DEVICE[(device)]->CR1 |= (I2C_CR1_ERRIE | I2C_CR1_NACKIE) - -#define __CPAL_I2C_HAL_DISABLE_ERRIT(device) CPAL_I2C_DEVICE[(device)]->CR1 &= ~(I2C_CR1_ERRIE | I2C_CR1_NACKIE) - - -#define __CPAL_I2C_HAL_ENABLE_MASTER_IT(device) CPAL_I2C_DEVICE[(device)]->CR1 |= (I2C_CR1_TCIE | I2C_CR1_STOPIE) - -#define __CPAL_I2C_HAL_DISABLE_MASTER_IT(device) CPAL_I2C_DEVICE[(device)]->CR1 &= ~(I2C_CR1_TCIE | I2C_CR1_STOPIE) - -#define __CPAL_I2C_HAL_ENABLE_MASTER_TXIT(device) CPAL_I2C_DEVICE[(device)]->CR1 |= (I2C_CR1_TCIE | I2C_CR1_STOPIE | I2C_CR1_TXIE) - -#define __CPAL_I2C_HAL_ENABLE_MASTER_RXIT(device) CPAL_I2C_DEVICE[(device)]->CR1 |= (I2C_CR1_TCIE | I2C_CR1_STOPIE | I2C_CR1_RXIE) - - -#define __CPAL_I2C_HAL_ENABLE_SLAVE_IT(device) CPAL_I2C_DEVICE[(device)]->CR1 |= (I2C_CR1_ADDRIE | I2C_CR1_STOPIE) - -#define __CPAL_I2C_HAL_DISABLE_SLAVE_IT(device) CPAL_I2C_DEVICE[(device)]->CR1 &= ~(I2C_CR1_ADDRIE | I2C_CR1_STOPIE) - -#define __CPAL_I2C_HAL_ENABLE_SLAVE_TXIT(device) CPAL_I2C_DEVICE[(device)]->CR1 |= (I2C_CR1_ADDRIE | I2C_CR1_STOPIE | I2C_CR1_TXIE) - -#define __CPAL_I2C_HAL_ENABLE_SLAVE_RXIT(device) CPAL_I2C_DEVICE[(device)]->CR1 |= (I2C_CR1_ADDRIE | I2C_CR1_STOPIE | I2C_CR1_RXIE) - - -#define __CPAL_I2C_HAL_ENABLE_STOPIE_IT(device) CPAL_I2C_DEVICE[(device)]->CR1 |= I2C_CR1_STOPIE - -#define __CPAL_I2C_HAL_DISABLE_STOPIE_IT(device) CPAL_I2C_DEVICE[(device)]->CR1 &= ~I2C_CR1_STOPIE - -#define __CPAL_I2C_HAL_ENABLE_ADDRIE_IT(device) CPAL_I2C_DEVICE[(device)]->CR1 |= I2C_CR1_ADDRIE - -#define __CPAL_I2C_HAL_DISABLE_ADDRIE_IT(device) CPAL_I2C_DEVICE[(device)]->CR1 &= ~I2C_CR1_ADDRIE - -#define __CPAL_I2C_HAL_ENABLE_TCIE_IT(device) CPAL_I2C_DEVICE[(device)]->CR1 |= I2C_CR1_TCIE - -#define __CPAL_I2C_HAL_DISABLE_TCIE_IT(device) CPAL_I2C_DEVICE[(device)]->CR1 &= ~I2C_CR1_TCIE - -#define __CPAL_I2C_HAL_ENABLE_TXIE_IT(device) CPAL_I2C_DEVICE[(device)]->CR1 |= I2C_CR1_TXIE - -#define __CPAL_I2C_HAL_DISABLE_TXIE_IT(device) CPAL_I2C_DEVICE[(device)]->CR1 &= ~I2C_CR1_TXIE - -#define __CPAL_I2C_HAL_ENABLE_RXIE_IT(device) CPAL_I2C_DEVICE[(device)]->CR1 |= I2C_CR1_RXIE - -#define __CPAL_I2C_HAL_DISABLE_RXIE_IT(device) CPAL_I2C_DEVICE[(device)]->CR1 &= ~I2C_CR1_RXIE - - -/* I2C Addressing configuration */ - -#define __CPAL_I2C_HAL_SADD_CONF(device,value) CPAL_I2C_DEVICE[(device)]->CR2 &= ~I2C_CR2_SADD; \ - CPAL_I2C_DEVICE[(device)]->CR2 |= (uint32_t)((value) & 0x000003FF) - -#define __CPAL_I2C_HAL_OA2_CONF(device,value) CPAL_I2C_DEVICE[(device)]->OAR2 &= ~I2C_OAR2_OA2; \ - CPAL_I2C_DEVICE[(device)]->OAR2 |= (uint32_t)((value) & 0x000000FE) - -#define __CPAL_I2C_HAL_OA2_MASK_CONF(device,value) CPAL_I2C_DEVICE[(device)]->OAR2 &= ~I2C_OAR2_OA2MSK; \ - CPAL_I2C_DEVICE[(device)]->OAR2 |= (uint32_t)((value) << 8) - -#define __CPAL_I2C_HAL_ENABLE_OA2(device) CPAL_I2C_DEVICE[(device)]->OAR2 |= I2C_OAR2_OA2EN - -#define __CPAL_I2C_HAL_ENABLE_ADD10(device) CPAL_I2C_DEVICE[(device)]->CR2 |= I2C_CR2_ADD10 - -#define __CPAL_I2C_HAL_DISABLE_ADD10(device) CPAL_I2C_DEVICE[(device)]->CR2 &= ~I2C_CR2_ADD10 - -#define __CPAL_I2C_HAL_ENABLE_COMPLETE_HEAD10R(device) CPAL_I2C_DEVICE[(device)]->CR2 &= ~I2C_CR2_HEAD10R - -#define __CPAL_I2C_HAL_DISABLE_COMPLETE_HEAD10R(device) CPAL_I2C_DEVICE[(device)]->CR2 |= I2C_CR2_HEAD10R - -#define __CPAL_I2C_HAL_ENABLE_GENCALL(device) CPAL_I2C_DEVICE[(device)]->CR1 |= I2C_CR1_GCEN - -#define __CPAL_I2C_HAL_REQ_WRITE_TRANSFER(device) CPAL_I2C_DEVICE[(device)]->CR2 &= ~I2C_CR2_RD_WRN - -#define __CPAL_I2C_HAL_REQ_READ_TRANSFER(device) CPAL_I2C_DEVICE[(device)]->CR2 |= I2C_CR2_RD_WRN - -#define __CPAL_I2C_HAL_GET_OA1(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_OAR1_OA1) - -#define __CPAL_I2C_HAL_GET_OA2(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_OAR2_OA2) - -#define __CPAL_I2C_HAL_GET_OA2_MASK(device) (uint32_t)((CPAL_I2C_DEVICE[(device)]->ISR & I2C_OAR2_OA2MSK) >> 8) - -#define __CPAL_I2C_HAL_GET_ADDCODE(device) (uint32_t)((CPAL_I2C_DEVICE[(device)]->ISR & I2C_ISR_ADDCODE) >> 17) - -#define __CPAL_I2C_HAL_GET_DIR(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_ISR_DIR) - -/* I2C misc configuration */ - -#define __CPAL_I2C_HAL_CR2_UPDATE(device,value) CPAL_I2C_DEVICE[(device)]->CR2 = value - -#define __CPAL_I2C_HAL_ENABLE_TXDMAREQ(device) CPAL_I2C_DEVICE[(device)]->CR1 |= I2C_CR1_TXDMAEN - -#define __CPAL_I2C_HAL_DISABLE_TXDMAREQ(device) CPAL_I2C_DEVICE[(device)]->CR1 &= ~I2C_CR1_TXDMAEN - -#define __CPAL_I2C_HAL_ENABLE_RXDMAREQ(device) CPAL_I2C_DEVICE[(device)]->CR1 |= I2C_CR1_RXDMAEN - -#define __CPAL_I2C_HAL_DISABLE_RXDMAREQ(device) CPAL_I2C_DEVICE[(device)]->CR1 &= ~I2C_CR1_RXDMAEN - -#define __CPAL_I2C_HAL_ENABLE_NACK(device) CPAL_I2C_DEVICE[(device)]->CR2 |= I2C_CR2_NACK - -#define __CPAL_I2C_HAL_DISABLE_NACK(device) CPAL_I2C_DEVICE[(device)]->CR2 &= ~I2C_CR2_NACK - -#define __CPAL_I2C_HAL_ENABLE_AUTOEND(device) CPAL_I2C_DEVICE[(device)]->CR2 |= I2C_CR2_AUTOEND - -#define __CPAL_I2C_HAL_DISABLE_AUTOEND(device) CPAL_I2C_DEVICE[(device)]->CR2 &= ~I2C_CR2_AUTOEND - -#define __CPAL_I2C_HAL_ENABLE_RELOAD(device) CPAL_I2C_DEVICE[(device)]->CR2 |= I2C_CR2_RELOAD - -#define __CPAL_I2C_HAL_DISABLE_RELOAD(device) CPAL_I2C_DEVICE[(device)]->CR2 &= ~I2C_CR2_RELOAD - -#define __CPAL_I2C_HAL_ENABLE_NOSTRETCH(device) CPAL_I2C_DEVICE[(device)]->CR1 |= I2C_CR1_NOSTRETCH - -#define __CPAL_I2C_HAL_DISABLE_NOSTRETCH(device) CPAL_I2C_DEVICE[(device)]->CR1 &= ~I2C_CR1_NOSTRETCH - -#define __CPAL_I2C_HAL_START(device) CPAL_I2C_DEVICE[(device)]->CR2 |= I2C_CR2_START - -#define __CPAL_I2C_HAL_STOP(device) CPAL_I2C_DEVICE[(device)]->CR2 |= I2C_CR2_STOP - -/* I2C data management */ - -#define __CPAL_I2C_HAL_RECEIVE(device) (uint8_t)(CPAL_I2C_DEVICE[(device)]->RXDR) - -#define __CPAL_I2C_HAL_SEND(device,value) CPAL_I2C_DEVICE[(device)]->TXDR = (uint8_t)((value)) - -#define __CPAL_I2C_HAL_SET_NBYTES(device,value) CPAL_I2C_DEVICE[(device)]->CR2 &= ~I2C_CR2_NBYTES; \ - CPAL_I2C_DEVICE[(device)]->CR2 |= (uint32_t)((uint32_t)(value) << 16) - -#define __CPAL_I2C_HAL_GET_NBYTES(device,value) (uint32_t)((CPAL_I2C_DEVICE[(device)]->CR2 & I2C_CR2_NBYTES) >> 16) - -#define __CPAL_I2C_HAL_CLEAR_NBYTES(device) CPAL_I2C_DEVICE[(device)]->CR2 &= ~I2C_CR2_NBYTES - -/* I2C flags management */ - -#define __CPAL_I2C_HAL_GET_EVENT(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & CPAL_I2C_STATUS_EVT_MASK) - -#define __CPAL_I2C_HAL_GET_ERROR(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & CPAL_I2C_STATUS_ERR_MASK) - -#define __CPAL_I2C_HAL_GET_TXE(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_ISR_TXE) - -#define __CPAL_I2C_HAL_GET_TXIS(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_ISR_TXIS) - -#define __CPAL_I2C_HAL_GET_RXNE(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_ISR_RXNE) - -#define __CPAL_I2C_HAL_GET_ADDR(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_ISR_ADDR) - -#define __CPAL_I2C_HAL_GET_NACK(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_ISR_NACKF) - -#define __CPAL_I2C_HAL_GET_STOP(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_ISR_STOPF) - -#define __CPAL_I2C_HAL_GET_TC(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_ISR_TC) - -#define __CPAL_I2C_HAL_GET_TCR(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_ISR_TCR) - -#define __CPAL_I2C_HAL_GET_BERR(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_ISR_BERR) - -#define __CPAL_I2C_HAL_GET_ARLO(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_ISR_ARLO) - -#define __CPAL_I2C_HAL_GET_OVR(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_ISR_OVR) - -#define __CPAL_I2C_HAL_GET_BUSY(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_ISR_BUSY) - -#define __CPAL_I2C_HAL_CLEAR_ADDR(device) CPAL_I2C_DEVICE[(device)]->ICR = I2C_ICR_ADDRCF - -#define __CPAL_I2C_HAL_CLEAR_NACK(device) CPAL_I2C_DEVICE[(device)]->ICR = I2C_ICR_NACKCF - -#define __CPAL_I2C_HAL_CLEAR_STOP(device) CPAL_I2C_DEVICE[(device)]->ICR = I2C_ICR_STOPCF - -#define __CPAL_I2C_HAL_CLEAR_BERR(device) CPAL_I2C_DEVICE[(device)]->ICR = I2C_ICR_BERRCF - -#define __CPAL_I2C_HAL_CLEAR_ARLO(device) CPAL_I2C_DEVICE[(device)]->ICR = I2C_ICR_ARLOCF - -#define __CPAL_I2C_HAL_CLEAR_OVR(device) CPAL_I2C_DEVICE[(device)]->ICR = I2C_ICR_OVRCF - -/* Exported functions --------------------------------------------------------*/ - -/*========= I2CX IRQHandler =========*/ - -#ifdef CPAL_USE_I2C1 - uint32_t I2C1_IRQHandler(void); /*
© COPYRIGHT 2014 STMicroelectronics
- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_i2c_cpal.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private defines -----------------------------------------------------------*/ - -/* Private macro -------------------------------------------------------------*/ - - -/* This macro allows to test on a flag status and to start Timeout procedure if the - waiting time exceeds the allowed timeout period. - @note This macro has not been implemented as a function because the entered parameter - 'cmd' itself can be a macro (if it was implemented as a function, the check on the - flag would be done only once, while the required behavior is to check the flag - continuously).*/ - -#define __CPAL_I2C_TIMEOUT_DETECT ((pDevInitStruct->wCPAL_Timeout == CPAL_I2C_TIMEOUT_MIN) ||\ - (pDevInitStruct->wCPAL_Timeout == CPAL_I2C_TIMEOUT_DEFAULT)) - -#define __CPAL_I2C_TIMEOUT(cmd, timeout) pDevInitStruct->wCPAL_Timeout = CPAL_I2C_TIMEOUT_MIN + (timeout);\ - while (((cmd) == 0) && (!__CPAL_I2C_TIMEOUT_DETECT));\ - if (__CPAL_I2C_TIMEOUT_DETECT)\ - {\ - return CPAL_I2C_Timeout (pDevInitStruct); \ - }\ - pDevInitStruct->wCPAL_Timeout = CPAL_I2C_TIMEOUT_DEFAULT - - -/* Private variables ---------------------------------------------------------*/ - -/*========= Table Exported from HAL =========*/ - -extern I2C_TypeDef* CPAL_I2C_DEVICE[]; - -#ifdef CPAL_I2C_DMA_PROGMODEL -extern DMA_TypeDef* CPAL_I2C_DMA[]; - -extern DMA_Channel_TypeDef* CPAL_I2C_DMA_TX_Channel[]; -extern DMA_Channel_TypeDef* CPAL_I2C_DMA_RX_Channel[]; - -extern const uint32_t CPAL_I2C_DMA_TX_TC_FLAG[]; -extern const uint32_t CPAL_I2C_DMA_RX_TC_FLAG[]; - -extern const uint32_t CPAL_I2C_DMA_TX_HT_FLAG[]; -extern const uint32_t CPAL_I2C_DMA_RX_HT_FLAG[]; - -extern const uint32_t CPAL_I2C_DMA_TX_TE_FLAG[]; -extern const uint32_t CPAL_I2C_DMA_RX_TE_FLAG[]; -#endif /* CPAL_I2C_DMA_PROGMODEL */ - -/*========= Local structures used in CPAL_I2C_StructInit() function ==========*/ - -I2C_InitTypeDef I2C_InitStructure; - -__IO uint32_t Num_Data = 0; -uint32_t CR2_tmp = 0; - -/* Private function prototypes -----------------------------------------------*/ - -/*========= Local Master events handlers =========*/ - -#ifdef CPAL_I2C_MASTER_MODE - static uint32_t I2C_MASTER_TCR_Handle(CPAL_InitTypeDef* pDevInitStruct); /* Handle Master TCR Interrupt event */ - static uint32_t I2C_MASTER_TC_Handle(CPAL_InitTypeDef* pDevInitStruct); /* Handle Master TC Interrupt event */ - static uint32_t I2C_MASTER_STOP_Handle(CPAL_InitTypeDef* pDevInitStruct); /* Handle Master STOP Interrupt event */ - static uint32_t I2C_MASTER_NACK_Handle(CPAL_InitTypeDef* pDevInitStruct); /* Handle Master NACK Interrupt event */ - #ifdef CPAL_I2C_IT_PROGMODEL - static uint32_t I2C_MASTER_TXIS_Handle(CPAL_InitTypeDef* pDevInitStruct); /* Handle Master TXIS Interrupt event */ - static uint32_t I2C_MASTER_RXNE_Handle(CPAL_InitTypeDef* pDevInitStruct); /* Handle Master RXNE Interrupt event */ - #endif /* CPAL_I2C_IT_PROGMODEL */ -#endif /* CPAL_I2C_MASTER_MODE */ - -/*========= Local Slave events handlers =========*/ - -#ifdef CPAL_I2C_SLAVE_MODE - static uint32_t I2C_SLAVE_ADDR_Handle(CPAL_InitTypeDef* pDevInitStruct); /* Handle Slave ADDR Interrupt event */ - static uint32_t I2C_SLAVE_STOP_Handle(CPAL_InitTypeDef* pDevInitStruct); /* Handle Slave STOPF Interrupt event */ - static uint32_t I2C_SLAVE_NACK_Handle(CPAL_InitTypeDef* pDevInitStruct); /* Handle Slave NACK Interrupt event */ - #ifdef CPAL_I2C_IT_PROGMODEL - static uint32_t I2C_SLAVE_TXIS_Handle(CPAL_InitTypeDef* pDevInitStruct); /* Handle Slave TXIS Interrupt event */ - static uint32_t I2C_SLAVE_RXNE_Handle(CPAL_InitTypeDef* pDevInitStruct); /* Handle Slave RXNE Interrupt event */ - #endif /* CPAL_I2C_IT_PROGMODEL */ -#endif /* CPAL_I2C_SLAVE_MODE */ - - -#ifdef CPAL_I2C_DMA_PROGMODEL -/*========= Local DMA Manager =========*/ -static uint32_t I2C_Enable_DMA (CPAL_InitTypeDef* pDevInitStruct, CPAL_DirectionTypeDef Direction); -#endif /* CPAL_I2C_DMA_PROGMODEL */ - -/*========= CPAL Timeout handler =========*/ -static uint32_t CPAL_I2C_Timeout (CPAL_InitTypeDef* pDevInitStruct); - - -/* Private functions ---------------------------------------------------------*/ - -/*================== USER CPAL Functions ==================*/ - - -/** - * @brief Initialize the peripheral and all related clocks, GPIOs, DMA and - * Interrupts according to the specified parameters in the - * CPAL_InitTypeDef structure. - * @param pDevInitStruct : Pointer to the peripheral configuration structure. - * @retval CPAL_PASS or CPAL_FAIL - */ -uint32_t CPAL_I2C_Init(CPAL_InitTypeDef* pDevInitStruct) -{ - CPAL_LOG("\n\r\n\rLOG : I2C Device Init"); - - /* If CPAL_State is not BUSY */ - if ((pDevInitStruct->CPAL_State == CPAL_STATE_READY) - || (pDevInitStruct->CPAL_State == CPAL_STATE_ERROR) - || (pDevInitStruct->CPAL_State == CPAL_STATE_DISABLED)) - { - /* - - If CPAL_State is CPAL_STATE_ERROR (an Error occurred in transaction): - Perform the initialization routines (device will be deinitialized during initialization). - - If CPAL_State is CPAL_STATE_READY: - Perform the initialization routines - - If CPAL_State is CPAL_STATE_DISABLED: - Perform the Initialization routines */ - -#ifndef CPAL_I2C_DMA_PROGMODEL - if (pDevInitStruct->CPAL_ProgModel == CPAL_PROGMODEL_DMA) - { - /* Update CPAL_State to CPAL_STATE_ERROR */ - pDevInitStruct->CPAL_State = CPAL_STATE_ERROR; - - /* Exit Init function */ - return CPAL_FAIL; - } -#endif /* CPAL_I2C_DMA_PROGMODEL */ - -#ifndef CPAL_I2C_IT_PROGMODEL - if (pDevInitStruct->CPAL_ProgModel == CPAL_PROGMODEL_INTERRUPT) - { - /* Update CPAL_State to CPAL_STATE_ERROR */ - pDevInitStruct->CPAL_State = CPAL_STATE_ERROR; - - /* Exit Init function */ - return CPAL_FAIL; - } -#endif /* CPAL_I2C_IT_PROGMODEL */ - - /* Disable I2Cx device */ - __CPAL_I2C_HAL_DISABLE_DEV(pDevInitStruct->CPAL_Dev); - - CPAL_LOG("\n\rLOG : I2C Device Disabled"); - - /* Deinitialize I2Cx GPIO */ - CPAL_I2C_HAL_GPIODeInit(pDevInitStruct->CPAL_Dev); - - CPAL_LOG("\n\rLOG : I2C Device IOs Deinit"); - - /* Deinitialize I2Cx clock */ - CPAL_I2C_HAL_CLKDeInit(pDevInitStruct->CPAL_Dev); - - CPAL_LOG("\n\rLOG : I2C Device Clock Deinit"); - -#ifdef CPAL_I2C_DMA_PROGMODEL - /* Deinitialize DMA Channels */ - if (pDevInitStruct->CPAL_ProgModel == CPAL_PROGMODEL_DMA) - { - CPAL_I2C_HAL_DMADeInit(pDevInitStruct->CPAL_Dev, pDevInitStruct->CPAL_Direction); - - CPAL_LOG("\n\rLOG : I2C Device DMA Deinit"); - } -#endif /* CPAL_I2C_DMA_PROGMODEL */ - - /*-------------------------------------------------------------------------- - GPIO pins configuration - ---------------------------------------------------------------------------*/ - /* Initialize I2Cx GPIO */ - CPAL_I2C_HAL_GPIOInit(pDevInitStruct->CPAL_Dev); - - CPAL_LOG("\n\rLOG : I2C Device IOs Init"); - - /*-------------------------------------------------------------------------- - Peripheral Clock Initialization - ---------------------------------------------------------------------------*/ - /* Initialize I2Cx clock */ - CPAL_I2C_HAL_CLKInit(pDevInitStruct->CPAL_Dev); - - CPAL_LOG("\n\rLOG : I2C Device Clock Init"); - - /*-------------------------------------------------------------------------- - Peripheral Initialization - ---------------------------------------------------------------------------*/ - - /* Initialize I2Cx device with parameters stored in pCPAL_I2C_Struct */ - I2C_Init(CPAL_I2C_DEVICE[pDevInitStruct->CPAL_Dev], pDevInitStruct->pCPAL_I2C_Struct); - - CPAL_LOG("\n\rLOG : I2C Device Config"); - - /* If General Call mode option bit selected */ - if ((pDevInitStruct->wCPAL_Options & CPAL_OPT_I2C_GENCALL) != 0) - { - /* Enable GENERAL CALL address mode */ - __CPAL_I2C_HAL_ENABLE_GENCALL(pDevInitStruct->CPAL_Dev); - - CPAL_LOG("\n\rLOG : I2C Device GENCALL Mode Enabled"); - } - - /* If OA2 Address mode option bit selected */ - if ((pDevInitStruct->wCPAL_Options & CPAL_OPT_I2C_DUALADDR) != 0) - { - /* Configure OA2 */ - __CPAL_I2C_HAL_OA2_CONF(pDevInitStruct->CPAL_Dev, (uint32_t)(pDevInitStruct->wCPAL_Options & 0x000000FE)); - - /* Configure OA2 masks */ - __CPAL_I2C_HAL_OA2_MASK_CONF(pDevInitStruct->CPAL_Dev, (uint32_t)((pDevInitStruct->wCPAL_Options & CPAL_OPT_I2C_OA2_MASK) >> 25)); - - /* Enable OA2 address mode */ - __CPAL_I2C_HAL_ENABLE_OA2(pDevInitStruct->CPAL_Dev); - - CPAL_LOG("\n\rLOG : I2C Device OA2 ADDR Mode Enabled"); - } - - /* If WakeUp from STOP option bit selected */ - if ((pDevInitStruct->wCPAL_Options & CPAL_OPT_I2C_WAKEUP_STOP) != 0) - { - /* Enable WakeUp from STOP mode */ - __CPAL_I2C_HAL_ENABLE_WAKEUP(pDevInitStruct->CPAL_Dev); - - CPAL_LOG("\n\rLOG : I2C Device WakeUp from Stop Mode Enabled"); - } - else - { - /* Disable WakeUp from STOP mode */ - __CPAL_I2C_HAL_DISABLE_WAKEUP(pDevInitStruct->CPAL_Dev); - } - - /* If NACK Slave Own Address option bit selected */ - if ((pDevInitStruct->wCPAL_Options & CPAL_OPT_I2C_NACK_ADD) != 0) - { - /* Disable Acknowledgement of own Address */ - __CPAL_I2C_HAL_DISABLE_DEV(pDevInitStruct->CPAL_Dev); - - CPAL_LOG("\n\rLOG : I2C Device NACK Own Address Mode Enabled"); - } - -#ifdef CPAL_I2C_DMA_PROGMODEL - /*---------------------------------------------------------------------------- - DMA Initialization : - ---------------------------------------------------------------------------*/ - /* If DMA Programming model is selected*/ - if (pDevInitStruct->CPAL_ProgModel == CPAL_PROGMODEL_DMA) - { - /* Initialize I2Cx DMA channels */ - CPAL_I2C_HAL_DMAInit(pDevInitStruct->CPAL_Dev, pDevInitStruct->CPAL_Direction, pDevInitStruct->wCPAL_Options); - - CPAL_LOG("\n\rLOG : I2C Device DMA Init"); - } -#endif /* CPAL_I2C_DMA_PROGMODEL */ - - /*---------------------------------------------------------------------------- - Peripheral and DMA interrupts Initialization - ---------------------------------------------------------------------------*/ - /* Initialize I2Cx interrupts */ - CPAL_I2C_HAL_ITInit(pDevInitStruct->CPAL_Dev, pDevInitStruct->wCPAL_Options); - - CPAL_LOG("\n\rLOG : I2C Device IT Init"); - - /* Update CPAL_State to CPAL_STATE_READY */ - pDevInitStruct->CPAL_State = CPAL_STATE_READY; - - CPAL_LOG("\n\rLOG : I2C Device Ready"); - - /* Initialize Timeout procedure */ - _CPAL_TIMEOUT_INIT(); - - return CPAL_PASS; - } - /* If CPAL_State is BUSY (a transaction is still on going) exit Init function */ - else - { - CPAL_LOG("\n\rERROR : I2C Device Busy"); - - return CPAL_FAIL; - } -} - - -/** - * @brief Deinitialize the peripheral and all related clocks, GPIOs, DMA and NVIC - * to their reset values. - * @param pDevInitStruct: Pointer to the peripheral configuration structure. - * @retval CPAL_PASS or CPAL_FAIL - * @note The Peripheral clock is disabled but the GPIO Ports clocks remains - * enabled after this deinitialization. - */ -uint32_t CPAL_I2C_DeInit(CPAL_InitTypeDef* pDevInitStruct) -{ - CPAL_LOG("\n\r\n\rLOG : I2C Device Deinit"); - - /* If CPAL_State is not BUSY */ - if ((pDevInitStruct->CPAL_State == CPAL_STATE_READY) - || (pDevInitStruct->CPAL_State == CPAL_STATE_ERROR) - || (pDevInitStruct->CPAL_State == CPAL_STATE_DISABLED)) - { - /* - - If CPAL_State is CPAL_STATE_ERROR (an Error occurred in transaction): - Perform the deinitialization routines - - If CPAL_State is CPAL_STATE_READY: - Perform the deinitialization routines - - If CPAL_State is CPAL_STATE_DISABLED: - Perform the deinitialization routines */ - - /*-------------------------------------------------------------------------- - GPIO pins Deinitialization - Note: The GPIO clock remains enabled after this deinitialization - ---------------------------------------------------------------------------*/ - /* Deinitialize I2Cx GPIO */ - CPAL_I2C_HAL_GPIODeInit(pDevInitStruct->CPAL_Dev); - - CPAL_LOG("\n\rLOG : I2C Device IOs Deinit"); - - /*-------------------------------------------------------------------------- - Peripheral Deinitialization - ---------------------------------------------------------------------------*/ - /* Disable I2Cx device */ - __CPAL_I2C_HAL_DISABLE_DEV(pDevInitStruct->CPAL_Dev); - - CPAL_LOG("\n\rLOG : I2C Device Disabled"); - - /*-------------------------------------------------------------------------- - Peripheral Clock Deinitialization - ---------------------------------------------------------------------------*/ - /* Deinitialize I2Cx clock */ - CPAL_I2C_HAL_CLKDeInit(pDevInitStruct->CPAL_Dev); - - CPAL_LOG("\n\rLOG : I2C Device Clock Deinit"); - -#ifdef CPAL_I2C_DMA_PROGMODEL - /*-------------------------------------------------------------------------- - DMA Deinitialization : if DMA Programming model is selected - ---------------------------------------------------------------------------*/ - if (pDevInitStruct->CPAL_ProgModel == CPAL_PROGMODEL_DMA) - { - CPAL_I2C_HAL_DMADeInit(pDevInitStruct->CPAL_Dev, pDevInitStruct->CPAL_Direction); - - CPAL_LOG("\n\rLOG : I2C Device DMA Deinit"); - } -#endif /* CPAL_I2C_DMA_PROGMODEL */ - - /*-------------------------------------------------------------------------- - Interrupts Deinitialization - ---------------------------------------------------------------------------*/ - CPAL_I2C_HAL_ITDeInit(pDevInitStruct->CPAL_Dev, pDevInitStruct->wCPAL_Options); - - CPAL_LOG("\n\rLOG : I2C Device IT Deinit"); - - /*-------------------------------------------------------------------------- - Structure fields initialization - ----------------------------------------------------------------------------*/ - /* Initialize pDevInitStruct state parameters to their default values */ - pDevInitStruct-> CPAL_State = CPAL_STATE_DISABLED; /* Device Disabled */ - pDevInitStruct-> wCPAL_DevError = CPAL_I2C_ERR_NONE; /* No Device Error */ - pDevInitStruct-> wCPAL_Timeout = ((uint32_t)CPAL_I2C_TIMEOUT_DEFAULT); /* Set timeout value to CPAL_I2C_TIMEOUT_DEFAULT */ - - CPAL_LOG("\n\rLOG :Set State fields to default"); - - /*---------------------------------------------------------------------------- - Deinitialize Timeout Procedure - -----------------------------------------------------------------------------*/ - _CPAL_TIMEOUT_DEINIT(); - - return CPAL_PASS; - } - /* If CPAL_State is BUSY (a transaction is still on going) Exit Init function */ - else - { - CPAL_LOG("\n\rERROR : I2C Device Busy"); - - return CPAL_FAIL; - } -} - - -/** - * @brief Initialize the peripheral structure with default values according - * to the specified parameters in the CPAL_I2CDevTypeDef structure. - * @param pDevInitStruct: Pointer to the peripheral configuration structure. - * @retval CPAL_PASS or CPAL_FAIL. - */ -uint32_t CPAL_I2C_StructInit(CPAL_InitTypeDef* pDevInitStruct) -{ - /* Initialize I2C_InitStructure to their default values */ - I2C_InitStructure.I2C_Timing = 0; /* Initialize the I2C_Timing member */ - I2C_InitStructure.I2C_Mode = I2C_Mode_I2C; /* Initialize the I2C_Mode member */ - I2C_InitStructure.I2C_AnalogFilter = I2C_AnalogFilter_Enable; /* Initialize the I2C_AnalogFilter member */ - I2C_InitStructure.I2C_DigitalFilter = 0x00; /* Initialize the I2C_DigitalFilter member */ - I2C_InitStructure.I2C_OwnAddress1 = 0; /* Initialize the I2C_OwnAddress1 member */ - I2C_InitStructure.I2C_Ack = I2C_Ack_Enable; /* Initialize the I2C_Ack member */ - I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; /* Initialize the I2C_AcknowledgedAddress member */ - - /* Initialize pDevInitStruct parameter to their default values */ - pDevInitStruct->CPAL_Direction = CPAL_DIRECTION_TXRX; /* Transmitter and Receiver direction selected */ - pDevInitStruct->CPAL_Mode = CPAL_MODE_MASTER; /* Mode Master selected */ - pDevInitStruct->CPAL_ProgModel = CPAL_PROGMODEL_DMA; /* DMA Programming Model selected */ - pDevInitStruct->pCPAL_TransferTx = pNULL; /* Point pCPAL_TransferTx to a Null pointer */ - pDevInitStruct->pCPAL_TransferRx = pNULL; /* Point pCPAL_TransferRx to a Null pointer */ - pDevInitStruct->CPAL_State = CPAL_STATE_DISABLED; /* Device Disabled */ - pDevInitStruct->wCPAL_DevError = CPAL_I2C_ERR_NONE; /* No Device Error */ - pDevInitStruct->wCPAL_Options = ((uint32_t)0x00000000); /* No Options selected */ - pDevInitStruct->wCPAL_Timeout = ((uint32_t)CPAL_I2C_TIMEOUT_DEFAULT); /* Set timeout value to CPAL_I2C_TIMEOUT_DEFAULT */ - pDevInitStruct->pCPAL_I2C_Struct = &I2C_InitStructure; /* Point to I2C_InitStructure (with default values) */ - - CPAL_LOG("\n\r\n\rLOG : I2C Device Structure set to Default Value"); - - return CPAL_PASS; -} - -#if defined (CPAL_I2C_MASTER_MODE) || ! defined (CPAL_I2C_LISTEN_MODE) - -/** - * @brief Allows to send a data or a buffer of data through the peripheral to - * a selected device in a selected location address. - * @param pDevInitStruct: Pointer to the peripheral configuration structure. - * @retval CPAL_PASS or CPAL_FAIL. - */ -uint32_t CPAL_I2C_Write(CPAL_InitTypeDef* pDevInitStruct) -{ - CR2_tmp = 0; - - /* Check I2C State: - - If busy --> exit Write operation - - If disabled --> exit Write operation - - If error --> exit Write operation - - If ready --> - *- Update CPAL_State to CPAL_STATE_BUSY - *- If CPAL_OPT_I2C_NOSTOP_MODE is not selected : - - Check if device is busy. - *- Update CPAL_State to CPAL_STATE_READY_TX - *- If DMA Prog Model : - - Configure and enable DMA - *- If Master mode : - - If 10Bit Mode : Enable ADD10 - - Configure Slave address - *- If Memory Address mode (master) - - Send target and memory address - *- Update CPAL_State to CPAL_STATE_BUSY_TX - *- If Master mode : - - Configure AUTOEND, RELOAD and NBYTES - - If Interrupt Prog Model : - - Generate start and enable interrupts - - If DMA Prog Model : - - Enable TX DMA request - - Generate start and enable interrupts - *- If Slave mode : - - If Interrupt Prog Model : - - Enable interrupts - - If DMA Prog Model : - - Enable TX DMA request - - Enable interrupts */ - - CPAL_LOG("\n\r\n\rLOG : I2C Device Write OP"); - - /* If Device is Busy (a transaction is still on going) Exit Write function */ - if (((pDevInitStruct->CPAL_State & CPAL_STATE_BUSY) != 0) - || (pDevInitStruct->CPAL_State == CPAL_STATE_READY_TX) - || (pDevInitStruct->CPAL_State == CPAL_STATE_READY_RX)) - { - CPAL_LOG("\n\rERROR : I2C Device Busy"); - - return CPAL_FAIL; - } - /* If CPAL_State is CPAL_STATE_DISABLED (device is not initialized) Exit Write function */ - else if (pDevInitStruct->CPAL_State == CPAL_STATE_DISABLED) - { - CPAL_LOG("\n\rERROR : I2C Device Not Initialized"); - - return CPAL_FAIL; - } - /* If CPAL_State is CPAL_STATE_ERROR (Error occurred ) */ - else if (pDevInitStruct->CPAL_State == CPAL_STATE_ERROR) - { - CPAL_LOG("\n\rERROR : I2C Device Error"); - - return CPAL_FAIL; - } - /* If CPAL_State is CPAL_STATE_READY ( Start Communication )*/ - else - { - /* Update CPAL_State to CPAL_STATE_BUSY */ - pDevInitStruct->CPAL_State = CPAL_STATE_BUSY; - - /* IF CPAL_OPT_I2C_NOSTOP_MODE is not selected */ - if ((pDevInitStruct->wCPAL_Options & CPAL_OPT_I2C_NOSTOP_MODE) == 0) - { - /* Wait until BUSY flag is reset */ - __CPAL_I2C_TIMEOUT(!(__CPAL_I2C_HAL_GET_BUSY(pDevInitStruct->CPAL_Dev)), CPAL_I2C_TIMEOUT_BUSY); - } - - /* Update CPAL_State to CPAL_STATE_READY_TX */ - pDevInitStruct->CPAL_State = CPAL_STATE_READY_TX; - CPAL_LOG("\n\rLOG : I2C Device Ready TX"); - -#ifdef CPAL_I2C_DMA_PROGMODEL - /* If DMA programming model */ - if (pDevInitStruct->CPAL_ProgModel == CPAL_PROGMODEL_DMA) - { - /* Configure and enable TX DMA channel */ - I2C_Enable_DMA(pDevInitStruct, CPAL_DIRECTION_TX); - } -#endif /* CPAL_I2C_DMA_PROGMODEL */ - -#ifdef CPAL_I2C_MASTER_MODE - /* If master mode selected */ - if (pDevInitStruct->CPAL_Mode == CPAL_MODE_MASTER) - { - #ifdef CPAL_I2C_10BIT_ADDR_MODE - /* If 10 Bit addressing mode */ - if (pDevInitStruct->pCPAL_I2C_Struct->I2C_AcknowledgedAddress == I2C_AcknowledgedAddress_10bit) - { - /* Enable 10Bit addressing mode */ - CR2_tmp |= I2C_CR2_ADD10; - } - #endif /* CPAL_I2C_10BIT_ADDR_MODE */ - - /* Configure slave address */ - CR2_tmp |= (uint32_t)((pDevInitStruct->pCPAL_TransferTx->wAddr1) & 0x000003FF); - } - - #ifdef CPAL_I2C_MEM_ADDR - /* If CPAL_OPT_NO_MEM_ADDR is not selected and master mode selected */ - if (((pDevInitStruct->wCPAL_Options & CPAL_OPT_NO_MEM_ADDR) == 0) - && (pDevInitStruct->CPAL_Mode == CPAL_MODE_MASTER )) - { - CPAL_LOG("\n\rLOG : I2C Device Master Mem Addr Mode"); - - /* Enable reload */ - CR2_tmp |= I2C_CR2_RELOAD; - - /* Disable error interrupt to manage error without interrupt */ - __CPAL_I2C_HAL_DISABLE_ERRIT(pDevInitStruct->CPAL_Dev); - - /* If 8 Bit register mode */ - if ((pDevInitStruct->wCPAL_Options & CPAL_OPT_16BIT_REG) == 0) - { - /* Configure Nbytes */ - CR2_tmp |= (uint32_t)((uint32_t)(1) << 16); - - /* Update CR2 Register */ - __CPAL_I2C_HAL_CR2_UPDATE(pDevInitStruct->CPAL_Dev, CR2_tmp); - - /* Generate start */ - __CPAL_I2C_HAL_START(pDevInitStruct->CPAL_Dev); - - /* Wait until TXIS flag is set or NACK is set */ - __CPAL_I2C_TIMEOUT((__CPAL_I2C_HAL_GET_TXIS(pDevInitStruct->CPAL_Dev) || __CPAL_I2C_HAL_GET_NACK(pDevInitStruct->CPAL_Dev)), CPAL_I2C_TIMEOUT_TXIS); - - /* If acknowledge failure detected generate stop and abort communication */ - if (__CPAL_I2C_HAL_GET_NACK(pDevInitStruct->CPAL_Dev)) - { - /* Generate stop if autoend option is disabled */ - if((CPAL_I2C_DEVICE[(pDevInitStruct->CPAL_Dev)]->CR2 & I2C_CR2_AUTOEND) != I2C_CR2_AUTOEND) - { - /* Generate stop */ - __CPAL_I2C_HAL_STOP(pDevInitStruct->CPAL_Dev); - } - - /* Clear NACK flag */ - __CPAL_I2C_HAL_CLEAR_NACK(pDevInitStruct->CPAL_Dev); - - /* Wait until STOP flag is set */ - __CPAL_I2C_TIMEOUT(__CPAL_I2C_HAL_GET_STOP(pDevInitStruct->CPAL_Dev), CPAL_I2C_TIMEOUT_BUSY); - - /* Clear STOP flag */ - __CPAL_I2C_HAL_CLEAR_STOP(pDevInitStruct->CPAL_Dev); - - /* Update wCPAL_DevError */ - pDevInitStruct->wCPAL_DevError = CPAL_I2C_ERR_AF; - - /* Set CPAL_State to CPAL_STATE_ERROR */ - pDevInitStruct->CPAL_State = CPAL_STATE_ERROR; - - return CPAL_FAIL; - } - - /* Send register address */ - __CPAL_I2C_HAL_SEND(pDevInitStruct->CPAL_Dev, (uint8_t)(pDevInitStruct->pCPAL_TransferTx->wAddr2)); - } - #ifdef CPAL_16BIT_REG_OPTION - /* If 16 Bit register mode */ - else - { - /* Configure Nbytes */ - CR2_tmp |= (uint32_t)((uint32_t)(2) << 16); - - /* Update CR2 Register */ - __CPAL_I2C_HAL_CR2_UPDATE(pDevInitStruct->CPAL_Dev, CR2_tmp); - - /* Generate start */ - __CPAL_I2C_HAL_START(pDevInitStruct->CPAL_Dev); - - /* Wait until TXIS flag is set or NACK is set */ - __CPAL_I2C_TIMEOUT((__CPAL_I2C_HAL_GET_TXIS(pDevInitStruct->CPAL_Dev) || __CPAL_I2C_HAL_GET_NACK(pDevInitStruct->CPAL_Dev)), CPAL_I2C_TIMEOUT_TXIS); - - /* If acknowledge failure detected generate stop and abort communication */ - if (__CPAL_I2C_HAL_GET_NACK(pDevInitStruct->CPAL_Dev)) - { - /* Generate stop if autoend option is disabled */ - if((CPAL_I2C_DEVICE[(pDevInitStruct->CPAL_Dev)]->CR2 & I2C_CR2_AUTOEND) != I2C_CR2_AUTOEND) - { - /* Generate stop */ - __CPAL_I2C_HAL_STOP(pDevInitStruct->CPAL_Dev); - } - - /* Clear NACK flag */ - __CPAL_I2C_HAL_CLEAR_NACK(pDevInitStruct->CPAL_Dev); - - /* Wait until STOP flag is set */ - __CPAL_I2C_TIMEOUT(__CPAL_I2C_HAL_GET_STOP(pDevInitStruct->CPAL_Dev), CPAL_I2C_TIMEOUT_BUSY); - - /* Clear STOP flag */ - __CPAL_I2C_HAL_CLEAR_STOP(pDevInitStruct->CPAL_Dev); - - /* Update wCPAL_DevError */ - pDevInitStruct->wCPAL_DevError = CPAL_I2C_ERR_AF; - - /* Set CPAL_State to CPAL_STATE_ERROR */ - pDevInitStruct->CPAL_State = CPAL_STATE_ERROR; - - return CPAL_FAIL; - } - - /* Send register address (MSB) */ - __CPAL_I2C_HAL_SEND(pDevInitStruct->CPAL_Dev, (uint8_t)(((pDevInitStruct->pCPAL_TransferTx->wAddr2)& 0xFF00) >> 8)); - - /* Wait until TXIS flag is set or NACK is set */ - __CPAL_I2C_TIMEOUT((__CPAL_I2C_HAL_GET_TXIS(pDevInitStruct->CPAL_Dev) || __CPAL_I2C_HAL_GET_NACK(pDevInitStruct->CPAL_Dev)), CPAL_I2C_TIMEOUT_TXIS); - - /* If acknowledge failure detected generate stop and abort communication */ - if (__CPAL_I2C_HAL_GET_NACK(pDevInitStruct->CPAL_Dev)) - { - /* Generate stop if autoend option is disabled */ - if((CPAL_I2C_DEVICE[(pDevInitStruct->CPAL_Dev)]->CR2 & I2C_CR2_AUTOEND) != I2C_CR2_AUTOEND) - { - /* Generate stop */ - __CPAL_I2C_HAL_STOP(pDevInitStruct->CPAL_Dev); - } - - /* Clear NACK flag */ - __CPAL_I2C_HAL_CLEAR_NACK(pDevInitStruct->CPAL_Dev); - - /* Wait until STOP flag is set */ - __CPAL_I2C_TIMEOUT(__CPAL_I2C_HAL_GET_STOP(pDevInitStruct->CPAL_Dev), CPAL_I2C_TIMEOUT_BUSY); - - /* Clear STOP flag */ - __CPAL_I2C_HAL_CLEAR_STOP(pDevInitStruct->CPAL_Dev); - - /* Update wCPAL_DevError */ - pDevInitStruct->wCPAL_DevError = CPAL_I2C_ERR_AF; - - /* Set CPAL_State to CPAL_STATE_ERROR */ - pDevInitStruct->CPAL_State = CPAL_STATE_ERROR; - - return CPAL_FAIL; - } - - /* Send register address (LSB) */ - __CPAL_I2C_HAL_SEND(pDevInitStruct->CPAL_Dev, (uint8_t)((pDevInitStruct->pCPAL_TransferTx->wAddr2)& 0x00FF)); - } - #endif /* CPAL_16BIT_REG_OPTION */ - - /* If I2C ERR Interrupt Option Bit not selected */ - if ((pDevInitStruct->wCPAL_Options & CPAL_OPT_I2C_ERRIT_DISABLE) == 0) - { - /* Enable I2C Error Interrupts */ - __CPAL_I2C_HAL_ENABLE_ERRIT(pDevInitStruct->CPAL_Dev); - } - - /* Wait until TCR flag is set */ - __CPAL_I2C_TIMEOUT(__CPAL_I2C_HAL_GET_TCR(pDevInitStruct->CPAL_Dev), CPAL_I2C_TIMEOUT_TCR); - - /* Set Nbytes to zero */ - CR2_tmp &= ~I2C_CR2_NBYTES; - } - #endif /* CPAL_I2C_MEM_ADDR */ -#endif /* CPAL_I2C_MASTER_MODE */ - - /* Update CPAL_State to CPAL_STATE_BUSY_TX */ - pDevInitStruct->CPAL_State = CPAL_STATE_BUSY_TX; - CPAL_LOG("\n\rLOG : I2C Device Busy TX"); - -#ifdef CPAL_I2C_MASTER_MODE - /* If master mode selected */ - if (pDevInitStruct->CPAL_Mode == CPAL_MODE_MASTER) - { - CPAL_LOG("\n\rLOG : I2C Device Master"); - - /* If automatic end mode is selected */ - if ((pDevInitStruct->wCPAL_Options & CPAL_OPT_I2C_AUTOMATIC_END) != 0) - { - /* Enable automatic end mode */ - CR2_tmp |= I2C_CR2_AUTOEND; - } - - /* If number of data is equal or lower than 255 bytes */ - if (pDevInitStruct->pCPAL_TransferTx->wNumData <= 0xFF ) - { - /* Update Num_Data */ - Num_Data = pDevInitStruct->pCPAL_TransferTx->wNumData; - - /* Set Nbytes to wNumData */ - CR2_tmp |= (uint32_t)((uint32_t)(Num_Data) << 16); - - /* Disable reload */ - CR2_tmp &= ~I2C_CR2_RELOAD; - } - /* If number of data is greater than 255 bytes */ - else - { - /* Set Nbytes to 255 */ - CR2_tmp |= (uint32_t)((uint32_t)(255) << 16); - - /* Enable reload */ - CR2_tmp |= I2C_CR2_RELOAD; - } - - /* If CPAL_OPT_NO_MEM_ADDR is selected */ - if ((pDevInitStruct->wCPAL_Options & CPAL_OPT_NO_MEM_ADDR) != 0) - { - /* Generate start */ - CR2_tmp |= I2C_CR2_START; - } - - /* Update CR2 Register */ - __CPAL_I2C_HAL_CR2_UPDATE(pDevInitStruct->CPAL_Dev, CR2_tmp); - - /* If interrupt programming model */ - if (pDevInitStruct->CPAL_ProgModel == CPAL_PROGMODEL_INTERRUPT) - { - CPAL_LOG("\n\rLOG : I2C Device IT Enabled"); - - /* Enable master interrupts */ - __CPAL_I2C_HAL_ENABLE_MASTER_TXIT(pDevInitStruct->CPAL_Dev); - } - /* If DMA programming model */ - else - { - CPAL_LOG("\n\rLOG : I2C Device DMA TX Enabled"); - - /* Enable TX DMA request */ - __CPAL_I2C_HAL_ENABLE_TXDMAREQ(pDevInitStruct->CPAL_Dev); - - /* Enable master interrupts */ - __CPAL_I2C_HAL_ENABLE_MASTER_IT(pDevInitStruct->CPAL_Dev); - } - } - /* If slave mode selected */ - else -#endif /* CPAL_I2C_MASTER_MODE */ - { -#ifdef CPAL_I2C_SLAVE_MODE - CPAL_LOG("\n\rLOG : I2C Device Slave"); - - /* If NACK Slave Own Address option bit selected */ - if ((pDevInitStruct->wCPAL_Options & CPAL_OPT_I2C_NACK_ADD) != 0) - { - /* Enable Acknowledgement of Own address */ - __CPAL_I2C_HAL_ENABLE_DEV(pDevInitStruct->CPAL_Dev); - } - - /* If interrupt programming model */ - if (pDevInitStruct->CPAL_ProgModel == CPAL_PROGMODEL_INTERRUPT) - { - CPAL_LOG("\n\rLOG : I2C Device IT Enabled"); - - /* Enable slave interrupts */ - __CPAL_I2C_HAL_ENABLE_SLAVE_TXIT(pDevInitStruct->CPAL_Dev); - } - /* If DMA programming model */ - else - { - CPAL_LOG("\n\rLOG : I2C Device DMA TX Enabled"); - - /* Enable TX DMA request */ - __CPAL_I2C_HAL_ENABLE_TXDMAREQ(pDevInitStruct->CPAL_Dev); - - /* Enable slave interrupts */ - __CPAL_I2C_HAL_ENABLE_SLAVE_IT(pDevInitStruct->CPAL_Dev); - } -#endif /* CPAL_I2C_SLAVE_MODE */ - } - } - return CPAL_PASS; -} - - - -/** - * @brief Allows to receive a data or a buffer of data through the peripheral - * from a selected device in a selected location address. - * @param pDevInitStruct: Pointer to the peripheral configuration structure. - * @retval CPAL_PASS or CPAL_FAIL. - */ -uint32_t CPAL_I2C_Read(CPAL_InitTypeDef* pDevInitStruct) -{ - CR2_tmp = 0; - - /* Check I2C State: - - If busy --> exit Read operation - - If disabled --> exit Read operation - - If error --> exit Read operation - - If ready --> - *- Update CPAL_State to CPAL_STATE_BUSY - *- If CPAL_OPT_I2C_NOSTOP_MODE is not selected : - - Check if device is busy - *- Update CPAL_State to CPAL_STATE_READY_RX - *- If DMA Prog Model : - - Configure and enable DMA - *- If Master mode : - - If 10Bit Mode : Enable ADD10 - - Configure Slave address - *- If Memory Address mode (master) - - Send target and memory address - *- Update CPAL_State to CPAL_STATE_BUSY_RX - *- If Master mode : - - Configure HEADR10, AUTOEND, RELOAD and NBYTES - - If Interrupt Prog Model : - - Generate start and enable interrupts - - If DMA Prog Model : - - Enable RX DMA request - - Generate start and enable interrupts - *- If Slave mode : - - If Interrupt Prog Model : - - Enable interrupts - - If DMA Prog Model : - - Enable RX DMA request - - Enable interrupts */ - - CPAL_LOG("\n\r\n\rLOG : I2C Device Perform Read OP"); - - /* If Device is Busy (a transaction is still on going) Exit Read function */ - if (((pDevInitStruct->CPAL_State & CPAL_STATE_BUSY) != 0) - || (pDevInitStruct->CPAL_State == CPAL_STATE_READY_TX) - || (pDevInitStruct->CPAL_State == CPAL_STATE_READY_RX)) - { - CPAL_LOG("\n\rERROR : I2C Device Busy"); - - return CPAL_FAIL; - } - /* If CPAL_State is CPAL_STATE_DISABLED (device is not initialized) Exit Read function */ - else if (pDevInitStruct->CPAL_State == CPAL_STATE_DISABLED) - { - CPAL_LOG("\n\rERROR : I2C Device Not Initialized"); - - return CPAL_FAIL; - } - /* If CPAL_State is CPAL_STATE_ERROR (Error occurred ) */ - else if (pDevInitStruct->CPAL_State == CPAL_STATE_ERROR) - { - CPAL_LOG("\n\rERROR : I2C Device Error"); - - return CPAL_FAIL; - } - /* If CPAL_State is CPAL_STATE_READY */ - else - { - /* Update CPAL_State to CPAL_STATE_BUSY */ - pDevInitStruct->CPAL_State = CPAL_STATE_BUSY; - - /* If CPAL_OPT_I2C_NOSTOP_MODE is not selected */ - if ((pDevInitStruct->wCPAL_Options & CPAL_OPT_I2C_NOSTOP_MODE) == 0) - { - /* Wait until BUSY flag is reset */ - __CPAL_I2C_TIMEOUT(!(__CPAL_I2C_HAL_GET_BUSY(pDevInitStruct->CPAL_Dev)), CPAL_I2C_TIMEOUT_BUSY); - } - - /* Update CPAL_State to CPAL_STATE_READY_RX */ - pDevInitStruct->CPAL_State = CPAL_STATE_READY_RX; - CPAL_LOG("\n\rLOG : I2C Device Ready RX"); - -#ifdef CPAL_I2C_DMA_PROGMODEL - /* If DMA programming model */ - if (pDevInitStruct->CPAL_ProgModel == CPAL_PROGMODEL_DMA) - { - /* Configure and enable RX DMA channel */ - I2C_Enable_DMA(pDevInitStruct, CPAL_DIRECTION_RX); - } -#endif /* CPAL_I2C_DMA_PROGMODEL */ - -#ifdef CPAL_I2C_MASTER_MODE - /* If master mode selected */ - if (pDevInitStruct->CPAL_Mode == CPAL_MODE_MASTER) - { - #ifdef CPAL_I2C_10BIT_ADDR_MODE - /* If 10 Bit addressing mode */ - if (pDevInitStruct->pCPAL_I2C_Struct->I2C_AcknowledgedAddress == I2C_AcknowledgedAddress_10bit) - { - /* Enable 10Bit addressing mode */ - CR2_tmp |= I2C_CR2_ADD10; - } - #endif /* CPAL_I2C_10BIT_ADDR_MODE */ - - /* Configure slave address */ - CR2_tmp |= (uint32_t)((pDevInitStruct->pCPAL_TransferRx->wAddr1) & 0x000003FF); - } - - #ifdef CPAL_I2C_MEM_ADDR - /* If No Memory Address option bit is not selected and master mode selected */ - if (((pDevInitStruct->wCPAL_Options & CPAL_OPT_NO_MEM_ADDR) == 0) - && (pDevInitStruct->CPAL_Mode == CPAL_MODE_MASTER )) - { - CPAL_LOG("\n\rLOG : I2C Device Master Mem Addr Mode"); - - /* Disable error interrupt to manage error without interrupt */ - __CPAL_I2C_HAL_DISABLE_ERRIT(pDevInitStruct->CPAL_Dev); - - /* If 8 Bit register mode */ - if ((pDevInitStruct->wCPAL_Options & CPAL_OPT_16BIT_REG) == 0) - { - /* Configure Nbytes */ - CR2_tmp |= (uint32_t)((uint32_t)(1) << 16); - - /* Update CR2 Register */ - __CPAL_I2C_HAL_CR2_UPDATE(pDevInitStruct->CPAL_Dev, CR2_tmp); - - /* Generate start */ - __CPAL_I2C_HAL_START(pDevInitStruct->CPAL_Dev); - - /* Wait until TXIS flag is set or NACK is set */ - __CPAL_I2C_TIMEOUT((__CPAL_I2C_HAL_GET_TXIS(pDevInitStruct->CPAL_Dev) || __CPAL_I2C_HAL_GET_NACK(pDevInitStruct->CPAL_Dev)), CPAL_I2C_TIMEOUT_TXIS); - - /* If acknowledge failure detected generate stop and abort communication */ - if (__CPAL_I2C_HAL_GET_NACK(pDevInitStruct->CPAL_Dev)) - { - /* Generate stop if autoend option is disabled */ - if((CPAL_I2C_DEVICE[(pDevInitStruct->CPAL_Dev)]->CR2 & I2C_CR2_AUTOEND) != I2C_CR2_AUTOEND) - { - /* Generate stop */ - __CPAL_I2C_HAL_STOP(pDevInitStruct->CPAL_Dev); - } - - /* Clear NACK flag */ - __CPAL_I2C_HAL_CLEAR_NACK(pDevInitStruct->CPAL_Dev); - - /* Wait until STOP flag is set */ - __CPAL_I2C_TIMEOUT(__CPAL_I2C_HAL_GET_STOP(pDevInitStruct->CPAL_Dev), CPAL_I2C_TIMEOUT_BUSY); - - /* Clear STOP flag */ - __CPAL_I2C_HAL_CLEAR_STOP(pDevInitStruct->CPAL_Dev); - - /* Update wCPAL_DevError */ - pDevInitStruct->wCPAL_DevError = CPAL_I2C_ERR_AF; - - /* Set CPAL_State to CPAL_STATE_ERROR */ - pDevInitStruct->CPAL_State = CPAL_STATE_ERROR; - - return CPAL_FAIL; - } - - /* Send register address */ - __CPAL_I2C_HAL_SEND(pDevInitStruct->CPAL_Dev, (uint8_t)(pDevInitStruct->pCPAL_TransferRx->wAddr2)); - } - #ifdef CPAL_16BIT_REG_OPTION - /* If 16 Bit register mode */ - else - { - /* Configure Nbytes */ - CR2_tmp |= (uint32_t)((uint32_t)(2) << 16); - - /* Update CR2 Register */ - __CPAL_I2C_HAL_CR2_UPDATE(pDevInitStruct->CPAL_Dev, CR2_tmp); - - /* Generate start */ - __CPAL_I2C_HAL_START(pDevInitStruct->CPAL_Dev); - - /* Wait until TXIS flag is set or NACK is set */ - __CPAL_I2C_TIMEOUT((__CPAL_I2C_HAL_GET_TXIS(pDevInitStruct->CPAL_Dev) || __CPAL_I2C_HAL_GET_NACK(pDevInitStruct->CPAL_Dev)), CPAL_I2C_TIMEOUT_TXIS); - - /* If acknowledge failure detected generate stop and abort communication */ - if (__CPAL_I2C_HAL_GET_NACK(pDevInitStruct->CPAL_Dev)) - { - /* Generate stop if autoend option is disabled */ - if((CPAL_I2C_DEVICE[(pDevInitStruct->CPAL_Dev)]->CR2 & I2C_CR2_AUTOEND) != I2C_CR2_AUTOEND) - { - /* Generate stop */ - __CPAL_I2C_HAL_STOP(pDevInitStruct->CPAL_Dev); - } - - /* Clear NACK flag */ - __CPAL_I2C_HAL_CLEAR_NACK(pDevInitStruct->CPAL_Dev); - - /* Wait until STOP flag is set */ - __CPAL_I2C_TIMEOUT(__CPAL_I2C_HAL_GET_STOP(pDevInitStruct->CPAL_Dev), CPAL_I2C_TIMEOUT_BUSY); - - /* Clear STOP flag */ - __CPAL_I2C_HAL_CLEAR_STOP(pDevInitStruct->CPAL_Dev); - - /* Update wCPAL_DevError */ - pDevInitStruct->wCPAL_DevError = CPAL_I2C_ERR_AF; - - /* Set CPAL_State to CPAL_STATE_ERROR */ - pDevInitStruct->CPAL_State = CPAL_STATE_ERROR; - - return CPAL_FAIL; - } - - /* Send register address (MSB) */ - __CPAL_I2C_HAL_SEND(pDevInitStruct->CPAL_Dev, (uint8_t)(((pDevInitStruct->pCPAL_TransferRx->wAddr2)& 0xFF00) >> 8)); - - /* Wait until TXIS flag is set or NACK is set */ - __CPAL_I2C_TIMEOUT((__CPAL_I2C_HAL_GET_TXIS(pDevInitStruct->CPAL_Dev) || __CPAL_I2C_HAL_GET_NACK(pDevInitStruct->CPAL_Dev)), CPAL_I2C_TIMEOUT_TXIS); - - /* If acknowledge failure detected generate stop and abort communication */ - if (__CPAL_I2C_HAL_GET_NACK(pDevInitStruct->CPAL_Dev)) - { - /* Generate stop if autoend option is disabled */ - if((CPAL_I2C_DEVICE[(pDevInitStruct->CPAL_Dev)]->CR2 & I2C_CR2_AUTOEND) != I2C_CR2_AUTOEND) - { - /* Generate stop */ - __CPAL_I2C_HAL_STOP(pDevInitStruct->CPAL_Dev); - } - - /* Clear NACK flag */ - __CPAL_I2C_HAL_CLEAR_NACK(pDevInitStruct->CPAL_Dev); - - /* Wait until STOP flag is set */ - __CPAL_I2C_TIMEOUT(__CPAL_I2C_HAL_GET_STOP(pDevInitStruct->CPAL_Dev), CPAL_I2C_TIMEOUT_BUSY); - - /* Clear STOP flag */ - __CPAL_I2C_HAL_CLEAR_STOP(pDevInitStruct->CPAL_Dev); - - /* Update wCPAL_DevError */ - pDevInitStruct->wCPAL_DevError = CPAL_I2C_ERR_AF; - - /* Set CPAL_State to CPAL_STATE_ERROR */ - pDevInitStruct->CPAL_State = CPAL_STATE_ERROR; - - return CPAL_FAIL; - } - - /* Send register address (LSB) */ - __CPAL_I2C_HAL_SEND(pDevInitStruct->CPAL_Dev, (uint8_t)((pDevInitStruct->pCPAL_TransferRx->wAddr2)& 0x00FF)); - } - #endif /* CPAL_16BIT_REG_OPTION */ - - /* If I2C ERR Interrupt Option Bit not selected */ - if ((pDevInitStruct->wCPAL_Options & CPAL_OPT_I2C_ERRIT_DISABLE) == 0) - { - /* Enable I2C Error Interrupts */ - __CPAL_I2C_HAL_ENABLE_ERRIT(pDevInitStruct->CPAL_Dev); - } - - /* Wait until TC flag is set */ - __CPAL_I2C_TIMEOUT(__CPAL_I2C_HAL_GET_TC(pDevInitStruct->CPAL_Dev), CPAL_I2C_TIMEOUT_TC); - - /* Set Nbytes to zero */ - CR2_tmp &= ~I2C_CR2_NBYTES; - - } - #endif /* CPAL_I2C_MEM_ADDR */ -#endif /* CPAL_I2C_MASTER_MODE */ - - /* Update CPAL_State to CPAL_STATE_BUSY_RX */ - pDevInitStruct->CPAL_State = CPAL_STATE_BUSY_RX; - CPAL_LOG("\n\rLOG : I2C Device Busy RX"); - -#ifdef CPAL_I2C_MASTER_MODE - /* If master mode selected */ - if (pDevInitStruct->CPAL_Mode == CPAL_MODE_MASTER) - { - CPAL_LOG("\n\rLOG : I2C Device Master"); - - /* Enable transfer request */ - CR2_tmp |= I2C_CR2_RD_WRN; - - #ifdef CPAL_I2C_10BIT_ADDR_MODE - /* If 10 Bit addressing mode */ - if (pDevInitStruct->pCPAL_I2C_Struct->I2C_AcknowledgedAddress == I2C_AcknowledgedAddress_10bit) - { - /* If CPAL_OPT_NO_MEM_ADDR is not selected and CPAL_OPT_I2C_10BIT_HEADR option enabled */ - if (((pDevInitStruct->wCPAL_Options & CPAL_OPT_I2C_10BIT_HEADR) != 0) || ((pDevInitStruct->wCPAL_Options & CPAL_OPT_NO_MEM_ADDR) == 0)) - { - /* Disable 10Bit addressing complete sequence for Read */ - CR2_tmp |= I2C_CR2_HEAD10R; - } - } - #endif /* CPAL_I2C_10BIT_ADDR_MODE */ - - /* If automatic end mode is selected */ - if ((pDevInitStruct->wCPAL_Options & CPAL_OPT_I2C_AUTOMATIC_END) != 0) - { - /* Enable automatic end mode */ - CR2_tmp |= I2C_CR2_AUTOEND; - } - - /* If number of data is equal or lower than 255 bytes */ - if (pDevInitStruct->pCPAL_TransferRx->wNumData <= 0xFF ) - { - /* Update Num_Data */ - Num_Data = pDevInitStruct->pCPAL_TransferRx->wNumData; - - /* Set Nbytes to wNumData */ - CR2_tmp |= (uint32_t)((uint32_t)(Num_Data) << 16); - - /* Disable reload */ - CR2_tmp &= ~I2C_CR2_RELOAD; - } - /* If number of data is greater than 255 bytes */ - else - { - /* Set Nbytes to wNumData */ - CR2_tmp |= (uint32_t)((uint32_t)(255) << 16); - - /* Enaable reload */ - CR2_tmp |= I2C_CR2_RELOAD; - } - - /* Generate start */ - CR2_tmp |= I2C_CR2_START; - - /* If interrupt programming model */ - if (pDevInitStruct->CPAL_ProgModel == CPAL_PROGMODEL_INTERRUPT) - { - CPAL_LOG("\n\rLOG : I2C Device IT Enabled"); - - /* Update CR2 Register */ - __CPAL_I2C_HAL_CR2_UPDATE(pDevInitStruct->CPAL_Dev, CR2_tmp); - - /* Enable master interrupts */ - __CPAL_I2C_HAL_ENABLE_MASTER_RXIT(pDevInitStruct->CPAL_Dev); - } - /* If DMA programming model */ - else - { - CPAL_LOG("\n\rLOG : I2C Device DMA RX Enabled"); - - /* Enable RX DMA request */ - __CPAL_I2C_HAL_ENABLE_RXDMAREQ(pDevInitStruct->CPAL_Dev); - - /* Update CR2 Register */ - __CPAL_I2C_HAL_CR2_UPDATE(pDevInitStruct->CPAL_Dev, CR2_tmp); - - /* Enable master interrupt */ - __CPAL_I2C_HAL_ENABLE_MASTER_IT(pDevInitStruct->CPAL_Dev); - } - } - /* If slave mode selected */ - else -#endif /* CPAL_I2C_MASTER_MODE */ - { -#ifdef CPAL_I2C_SLAVE_MODE - CPAL_LOG("\n\rLOG : I2C Device Slave"); - - /* If NACK Slave Own Address option bit selected */ - if ((pDevInitStruct->wCPAL_Options & CPAL_OPT_I2C_NACK_ADD) != 0) - { - /* Enable Acknowledgement of Own address */ - __CPAL_I2C_HAL_ENABLE_DEV(pDevInitStruct->CPAL_Dev); - } - - /* If interrupt programming model */ - if (pDevInitStruct->CPAL_ProgModel == CPAL_PROGMODEL_INTERRUPT) - { - CPAL_LOG("\n\rLOG : I2C Device IT Enabled"); - - /* Enable slave interrupts */ - __CPAL_I2C_HAL_ENABLE_SLAVE_RXIT(pDevInitStruct->CPAL_Dev); - } - /* If DMA programming model */ - else - { - CPAL_LOG("\n\rLOG : I2C Device DMA RX Enabled"); - - /* Enable RX DMA request */ - __CPAL_I2C_HAL_ENABLE_RXDMAREQ(pDevInitStruct->CPAL_Dev); - - /* Enable slave interrupt */ - __CPAL_I2C_HAL_ENABLE_SLAVE_IT(pDevInitStruct->CPAL_Dev); - } -#endif /* CPAL_I2C_SLAVE_MODE */ - } - } - return CPAL_PASS; -} -#endif /* CPAL_I2C_MASTER_MODE || ! CPAL_I2C_LISTEN_MODE */ - -#if defined (CPAL_I2C_LISTEN_MODE) && defined (CPAL_I2C_SLAVE_MODE) -/** - * @brief Allows slave device to start a communication without knowing in advance - * the nature of the operation (read or write). Slave waits until it receive - * its own address.CPAL_I2C_SLAVE_READ_UserCallback is called for a read request - * and CPAL_I2C_SLAVE_WRITE_UserCallback for a write request in I2C_SLAVE_ADDR_Handle. - * User must implement inorder to configure DMA, interrupts and transfer parameters. - * @param pDevInitStruct: Pointer to the peripheral configuration structure. - * @retval CPAL_PASS or CPAL_FAIL. - */ -uint32_t CPAL_I2C_Listen(CPAL_InitTypeDef* pDevInitStruct) -{ - /* Check I2C State: - - If busy --> exit operation - - If disabled --> exit operation - - If error --> exit operation - - If ready --> - - Enable Event Interrupt */ - - CPAL_LOG("\n\r\n\rLOG : I2C Device in listen mode"); - - /* If Device is Busy (a transaction is still on going) Exit function */ - if (((pDevInitStruct->CPAL_State & CPAL_STATE_BUSY) != 0) - || (pDevInitStruct->CPAL_State == CPAL_STATE_READY_TX) - || (pDevInitStruct->CPAL_State == CPAL_STATE_READY_RX)) - { - CPAL_LOG("\n\rERROR : I2C Device Busy"); - - return CPAL_FAIL; - } - /* If CPAL_State is CPAL_STATE_DISABLED (device is not initialized) Exit function */ - else if (pDevInitStruct->CPAL_State == CPAL_STATE_DISABLED) - { - CPAL_LOG("\n\rERROR : I2C Device Not Initialized"); - - return CPAL_FAIL; - } - /* If CPAL_State is CPAL_STATE_ERROR (Error occurred ) */ - else if (pDevInitStruct->CPAL_State == CPAL_STATE_ERROR) - { - CPAL_LOG("\n\rERROR : I2C Device Error"); - - return CPAL_FAIL; - } - /* If CPAL_State is CPAL_STATE_READY */ - else - { - - /* If NACK Slave Own Address option bit selected */ - if ((pDevInitStruct->wCPAL_Options & CPAL_OPT_I2C_NACK_ADD) != 0) - { - /* Enable Acknowledgement of Own address */ - __CPAL_I2C_HAL_ENABLE_DEV(pDevInitStruct->CPAL_Dev); - } - - /* Set device to slave mode */ - pDevInitStruct->CPAL_Mode = CPAL_MODE_SLAVE; - - /* Update CPAL_State to CPAL_STATE_BUSY */ - pDevInitStruct->CPAL_State = CPAL_STATE_BUSY; - - CPAL_LOG("\n\rLOG : I2C Device EVT IT Enabled"); - - /* Enable Slave Interrupts*/ - __CPAL_I2C_HAL_ENABLE_SLAVE_IT(pDevInitStruct->CPAL_Dev); - } - - return CPAL_PASS; -} -#endif /* CPAL_I2C_LISTEN_MODE && CPAL_I2C_SLAVE_MODE */ - -/** - * @brief Wait until target device is ready for communication (This function is - * used with Memory devices). - * @param pDevInitStruct: Pointer to the peripheral configuration structure. - * @retval CPAL_PASS or CPAL_FAIL. - */ -uint32_t CPAL_I2C_IsDeviceReady(CPAL_InitTypeDef* pDevInitStruct) -{ - CR2_tmp = 0; - - CPAL_LOG("\n\r\n\rLOG : Wait until I2C Device is Ready"); - - /* Set CPAL_State to CPAL_STATE_BUSY */ - pDevInitStruct->CPAL_State = CPAL_STATE_BUSY; - - /* Disable I2Cx device */ - __CPAL_I2C_HAL_DISABLE_DEV(pDevInitStruct->CPAL_Dev); - - /* Enable I2Cx device */ - __CPAL_I2C_HAL_ENABLE_DEV(pDevInitStruct->CPAL_Dev); - - /* Disable interrupts */ - __CPAL_I2C_HAL_DISABLE_ALLIT(pDevInitStruct->CPAL_Dev); - - /* Configure slave address */ - CR2_tmp |= (uint32_t)((pDevInitStruct->pCPAL_TransferTx->wAddr1) & 0x000003FF) | I2C_CR2_AUTOEND; - - /* Update CR2 Register */ - __CPAL_I2C_HAL_CR2_UPDATE(pDevInitStruct->CPAL_Dev, CR2_tmp); - - /* Generate Start */ - __CPAL_I2C_HAL_START(pDevInitStruct->CPAL_Dev); - - /* Set 35ms timeout */ - pDevInitStruct->wCPAL_Timeout = CPAL_I2C_TIMEOUT_MIN + 35; - - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is set or a NACK flag is set*/ - while((__CPAL_I2C_HAL_GET_STOP(pDevInitStruct->CPAL_Dev) == RESET) && (__CPAL_I2C_HAL_GET_NACK(pDevInitStruct->CPAL_Dev) == RESET)); - - /* Reinitialize Timeout Value to default */ - pDevInitStruct->wCPAL_Timeout = CPAL_I2C_TIMEOUT_DEFAULT; - - /* Check if the NACKF flag has not been set */ - if (__CPAL_I2C_HAL_GET_NACK(pDevInitStruct->CPAL_Dev) != RESET) - { - /* Clear NACK flag */ - __CPAL_I2C_HAL_CLEAR_NACK(pDevInitStruct->CPAL_Dev); - - /* Clear Stop flag */ - __CPAL_I2C_HAL_CLEAR_STOP(pDevInitStruct->CPAL_Dev); - - /* Enable error interrupt */ - __CPAL_I2C_HAL_ENABLE_ERRIT(pDevInitStruct->CPAL_Dev); - - /* Set CPAL_State to CPAL_STATE_READY */ - pDevInitStruct->CPAL_State = CPAL_STATE_READY; - - return CPAL_FAIL; - } - else - { - /* Clear Stop flag */ - __CPAL_I2C_HAL_CLEAR_STOP(pDevInitStruct->CPAL_Dev); - - /* Enable error interrupt */ - __CPAL_I2C_HAL_ENABLE_ERRIT(pDevInitStruct->CPAL_Dev); - - /* Set CPAL_State to CPAL_STATE_READY */ - pDevInitStruct->CPAL_State = CPAL_STATE_READY; - - CPAL_LOG("\n\rLOG : I2C Target device Ready"); - - return CPAL_PASS; - } -} - - -/*================== CPAL_I2C_Interrupt_Handler ==================*/ - -/** - * @brief This function handles I2C interrupt request for preparing communication - * and for transfer phase in case of using Interrupt Programming Model. - * @param pDevInitStruct: Pointer to the peripheral configuration structure. - * @retval CPAL_PASS. - */ -uint32_t CPAL_I2C_EV_IRQHandler( CPAL_InitTypeDef* pDevInitStruct) -{ - __IO uint32_t I2CFlagStatus = 0x00000000; - - /* Read I2C status registers (ISR) */ - I2CFlagStatus = __CPAL_I2C_HAL_GET_EVENT(pDevInitStruct->CPAL_Dev); - -#ifdef CPAL_I2C_MASTER_MODE - /*----------------------------------------------------------------------------------------------*/ - /*---------------------------------- If Master Mode selected ----------------------------------*/ - if (pDevInitStruct->CPAL_Mode == CPAL_MODE_MASTER) - { - #ifdef CPAL_I2C_IT_PROGMODEL - /*----------------------------------------*/ - /*------------- If TXIS event ------------*/ - if (((I2CFlagStatus & CPAL_I2C_EVT_TXIS) != 0) && (pDevInitStruct->CPAL_State == CPAL_STATE_BUSY_TX)) - { - I2C_MASTER_TXIS_Handle(pDevInitStruct); - } - - /*----------------------------------------*/ - /*------------- If RXNE event ------------*/ - if (((I2CFlagStatus & CPAL_I2C_EVT_RXNE) != 0) && (pDevInitStruct->CPAL_State == CPAL_STATE_BUSY_RX)) - { - I2C_MASTER_RXNE_Handle(pDevInitStruct); - } - #endif /* CPAL_I2C_IT_PROGMODEL */ - - /*----------------------------------------*/ - /*-------------- If TCR event ------------*/ - if ((I2CFlagStatus & CPAL_I2C_EVT_TCR) != 0) - { - I2C_MASTER_TCR_Handle(pDevInitStruct); - } - - /*----------------------------------------*/ - /*------------- If TC event --------------*/ - if ((I2CFlagStatus & CPAL_I2C_EVT_TC ) != 0) - { - I2C_MASTER_TC_Handle(pDevInitStruct); - } - - /*----------------------------------------*/ - /*------------- If STOP event ------------*/ - if ((I2CFlagStatus & CPAL_I2C_EVT_STOP) != 0) - { - I2C_MASTER_STOP_Handle(pDevInitStruct); - } - - /*----------------------------------------*/ - /*------------- If NACK event ------------*/ - if((I2CFlagStatus & CPAL_I2C_EVT_NACK ) != 0) - { - I2C_MASTER_NACK_Handle(pDevInitStruct); - } - } -#endif /* CPAL_I2C_MASTER_MODE */ - -#ifdef CPAL_I2C_SLAVE_MODE - /*----------------------------------------------------------------------------------------------*/ - /*---------------------------------- If Slave Mode selected ------------------------------------*/ - if (pDevInitStruct->CPAL_Mode == CPAL_MODE_SLAVE) - { - /*----------------------------------------*/ - /*------------- If ADDR event ------------*/ - if ((I2CFlagStatus & CPAL_I2C_EVT_ADDR ) != 0) - { - I2C_SLAVE_ADDR_Handle(pDevInitStruct); - } - - #ifdef CPAL_I2C_IT_PROGMODEL - /*----------------------------------------*/ - /*------------- If TXIS event ------------*/ - if ((I2CFlagStatus & CPAL_I2C_EVT_TXIS) != 0) - { - I2C_SLAVE_TXIS_Handle(pDevInitStruct); - } - - /*----------------------------------------*/ - /*------------- If RXNE event ------------*/ - if ((I2CFlagStatus & CPAL_I2C_EVT_RXNE) != 0) - { - I2C_SLAVE_RXNE_Handle(pDevInitStruct); - } - #endif /* CPAL_I2C_IT_PROGMODEL */ - - /*----------------------------------------*/ - /*------------- If NACK event ------------*/ - if ((I2CFlagStatus & CPAL_I2C_EVT_NACK) != 0) - { - I2C_SLAVE_NACK_Handle(pDevInitStruct); - } - - /*----------------------------------------*/ - /*------------- If STOP event ------------*/ - if ((I2CFlagStatus & CPAL_I2C_EVT_STOP) != 0) - { - I2C_SLAVE_STOP_Handle(pDevInitStruct); - } - } -#endif /* CPAL_I2C_SLAVE_MODE */ - - return CPAL_PASS; -} - - -/** - * @brief Allows to handle errors occurred during initialization or communication - * in order to recover the correct communication status or call specific - * user functions. - * @param pDevInitStruct: Pointer to the peripheral configuration structure. - * @retval CPAL_PASS. - */ -uint32_t CPAL_I2C_ER_IRQHandler(CPAL_InitTypeDef* pDevInitStruct) -{ - /* Read error register and affect to wCPAL_DevError */ - pDevInitStruct->wCPAL_DevError = __CPAL_I2C_HAL_GET_ERROR(pDevInitStruct->CPAL_Dev); - - /* Set CPAL_State to CPAL_STATE_ERROR */ - pDevInitStruct->CPAL_State = CPAL_STATE_ERROR; - - CPAL_LOG("\n\r\n\rERROR : I2C Device Error"); - - /* If Bus error occurred ---------------------------------------------------*/ - if ((pDevInitStruct->wCPAL_DevError & CPAL_I2C_ERR_BERR) != 0) - { - CPAL_LOG("\n\rERROR : I2C Device BERR"); - - /* Clear error flag */ - __CPAL_I2C_HAL_CLEAR_BERR(pDevInitStruct->CPAL_Dev); - -#ifdef USE_MULTIPLE_ERROR_CALLBACK - /* Call Bus Error UserCallback */ - CPAL_I2C_BERR_UserCallback(pDevInitStruct->CPAL_Dev); -#endif /* USE_MULTIPLE_ERROR_CALLBACK */ - } - - /* If Arbitration Loss error occurred --------------------------------------*/ - if ((pDevInitStruct->wCPAL_DevError & CPAL_I2C_ERR_ARLO) != 0) - { - CPAL_LOG("\n\rERROR : I2C Device ARLO"); - - /* Clear error flag */ - __CPAL_I2C_HAL_CLEAR_ARLO(pDevInitStruct->CPAL_Dev); - -#ifdef USE_MULTIPLE_ERROR_CALLBACK - /* Call Arbitration Lost UserCallback */ - CPAL_I2C_ARLO_UserCallback(pDevInitStruct->CPAL_Dev); -#endif /* USE_MULTIPLE_ERROR_CALLBACK */ - } - - /* If Overrun error occurred -----------------------------------------------*/ - if ((pDevInitStruct->wCPAL_DevError & CPAL_I2C_ERR_OVR) != 0) - { - CPAL_LOG("\n\rERROR : I2C Device OVR"); - - /* No I2C software reset is performed here in order to allow user to get back - the last data received correctly */ - - /* Clear error flag */ - __CPAL_I2C_HAL_CLEAR_OVR(pDevInitStruct->CPAL_Dev); - -#ifdef USE_MULTIPLE_ERROR_CALLBACK - /* Call Overrun error UserCallback */ - CPAL_I2C_OVR_UserCallback(pDevInitStruct->CPAL_Dev); -#endif /* USE_MULTIPLE_ERROR_CALLBACK */ - } - - /* USE_SINGLE_ERROR_CALLBACK is defined in stm32f0xx_i2c_cpal_conf.h file */ -#ifdef USE_SINGLE_ERROR_CALLBACK - /* Call Error UserCallback */ - CPAL_I2C_ERR_UserCallback(pDevInitStruct->CPAL_Dev, pDevInitStruct->wCPAL_DevError); -#endif /* USE_SINGLE_ERROR_CALLBACK */ - - return CPAL_PASS; -} - - -#ifdef CPAL_I2C_DMA_PROGMODEL -/** - * @brief Handle I2C DMA TX interrupt request when DMA programming Model is - * used for data transmission. - * @param pDevInitStruct: Pointer to the peripheral configuration structure. - * @retval CPAL_PASS. - */ -uint32_t CPAL_I2C_DMA_TX_IRQHandler(CPAL_InitTypeDef* pDevInitStruct) -{ - /* Reinitialize timeout value to default (no timeout initiated) */ - pDevInitStruct->wCPAL_Timeout = CPAL_I2C_TIMEOUT_DEFAULT; - - CPAL_LOG("\n\r\n\rLOG : I2C Device TX DMA "); - - /*------------- If TC interrupt ------------*/ - if((__CPAL_I2C_HAL_GET_DMATX_TCIT(pDevInitStruct->CPAL_Dev)) != 0) - { - CPAL_LOG("\n\rLOG : I2C Device TX Complete"); - - /* If DMA normal mode */ - if ((pDevInitStruct->wCPAL_Options & CPAL_OPT_DMATX_CIRCULAR) == 0) - { - /* Update remaining number of data */ - pDevInitStruct->pCPAL_TransferTx->wNumData = 0; - - /* Call DMA TX TC UserCallback */ - CPAL_I2C_DMATXTC_UserCallback(pDevInitStruct); - - /* Disable DMA request and channel */ - __CPAL_I2C_HAL_DISABLE_TXDMAREQ(pDevInitStruct->CPAL_Dev); - __CPAL_I2C_HAL_DISABLE_DMATX(pDevInitStruct->CPAL_Dev); - - CPAL_LOG("\n\rLOG : I2C Device TX DMA Disabled"); - } - /* If DMA circular mode */ - else - { - /* Call DMA TX TC UserCallback */ - CPAL_I2C_DMATXTC_UserCallback(pDevInitStruct); - } - - } - /*------------- If HT interrupt ------------*/ - else if ((__CPAL_I2C_HAL_GET_DMATX_HTIT(pDevInitStruct->CPAL_Dev)) != 0) - { - CPAL_LOG("\n\rLOG : I2C Device TX DMA Half Transfer "); - - /* Call DMA TX HT UserCallback */ - CPAL_I2C_DMATXHT_UserCallback(pDevInitStruct); - } - /*------------- If TE interrupt ------------*/ - else if ((__CPAL_I2C_HAL_GET_DMATX_TEIT(pDevInitStruct->CPAL_Dev)) != 0) - { - CPAL_LOG("\n\rERROR : I2C Device TX DMA Transfer Error "); - - /* Update CPAL_State to CPAL_STATE_ERROR */ - pDevInitStruct->CPAL_State = CPAL_STATE_ERROR; - - /* Update remaining number of data */ - pDevInitStruct->pCPAL_TransferTx->wNumData = __CPAL_I2C_HAL_DMATX_GET_CNDT(pDevInitStruct->CPAL_Dev); - - /* Call TX transfer complete UserCallback */ - CPAL_I2C_RXTC_UserCallback(pDevInitStruct); - } - - /* Clear DMA interrupt Flag */ - __CPAL_I2C_HAL_CLEAR_DMATX_IT(pDevInitStruct->CPAL_Dev); - - return CPAL_PASS; -} - - -/** - * @brief Handle I2C DMA RX interrupt request when DMA programming Model is - * used for data reception. - * @param pDevInitStruct: Pointer to the peripheral configuration structure. - * @retval CPAL_PASS. - */ -uint32_t CPAL_I2C_DMA_RX_IRQHandler(CPAL_InitTypeDef* pDevInitStruct) -{ - /* Reinitialize Timeout Value to default (no timeout initiated) */ - pDevInitStruct->wCPAL_Timeout = CPAL_I2C_TIMEOUT_DEFAULT; - - CPAL_LOG("\n\r\n\rLOG : I2C Device RX DMA "); - - /*------------- If TC interrupt ------------*/ - if ((__CPAL_I2C_HAL_GET_DMARX_TCIT(pDevInitStruct->CPAL_Dev)) != 0) - { - CPAL_LOG("\n\rLOG : I2C Device RX Complete"); - - /* If DMA normal mode */ - if ((pDevInitStruct->wCPAL_Options & CPAL_OPT_DMARX_CIRCULAR) == 0) - { - /* Update remaining number of data */ - pDevInitStruct->pCPAL_TransferRx->wNumData = 0; - - /* Disable DMA Request and Channel */ - __CPAL_I2C_HAL_DISABLE_RXDMAREQ(pDevInitStruct->CPAL_Dev); - __CPAL_I2C_HAL_DISABLE_DMARX(pDevInitStruct->CPAL_Dev); - - CPAL_LOG("\n\rLOG : I2C Device RX DMA Disabled"); - - /* Call DMA RX TC UserCallback */ - CPAL_I2C_DMARXTC_UserCallback(pDevInitStruct); - - /* If No Stop Condition Generation option bit selected */ - if (((pDevInitStruct->wCPAL_Options & CPAL_OPT_I2C_NOSTOP) != 0) && (pDevInitStruct->CPAL_Mode == CPAL_MODE_SLAVE)) - { - /* Disable slave interrupt */ - __CPAL_I2C_HAL_DISABLE_SLAVE_IT(pDevInitStruct->CPAL_Dev); - - /* Update CPAL_State to CPAL_STATE_READY */ - pDevInitStruct->CPAL_State = CPAL_STATE_READY; - - /* Call TX transfer complete UserCallback */ - CPAL_I2C_TXTC_UserCallback(pDevInitStruct); - } - } - /* If DMA circular mode */ - else - { - /* Call DMA RX TC UserCallback */ - CPAL_I2C_DMARXTC_UserCallback(pDevInitStruct); - } - } - /*------------- If HT interrupt ------------*/ - else if ((__CPAL_I2C_HAL_GET_DMARX_HTIT(pDevInitStruct->CPAL_Dev)) != 0) - { - CPAL_LOG("\n\rLOG : I2C Device RX DMA Half Transfer"); - - /* Call DMA RX HT UserCallback */ - CPAL_I2C_DMARXHT_UserCallback(pDevInitStruct); - } - /*------------- If TE interrupt ------------*/ - else if ((__CPAL_I2C_HAL_GET_DMARX_TEIT(pDevInitStruct->CPAL_Dev)) != 0) - { - CPAL_LOG("\n\rERROR : I2C Device RX DMA Transfer Error "); - - /* Update CPAL_State to CPAL_STATE_ERROR */ - pDevInitStruct->CPAL_State = CPAL_STATE_ERROR; - - /* Update remaining number of data */ - pDevInitStruct->pCPAL_TransferRx->wNumData = __CPAL_I2C_HAL_DMARX_GET_CNDT(pDevInitStruct->CPAL_Dev); - - /* Call DMA RX TE UserCallback */ - CPAL_I2C_DMARXTE_UserCallback(pDevInitStruct); - } - - /* Clear DMA interrupt Flag */ - __CPAL_I2C_HAL_CLEAR_DMARX_IT(pDevInitStruct->CPAL_Dev); - - return CPAL_PASS; -} -#endif /* CPAL_I2C_DMA_PROGMODEL */ - - -/*================== CPAL_I2C_Timeout_Function ==================*/ - -/** - * @brief This function Manages I2C Timeouts when waiting for specific events. - * @param None - * @retval CPAL_PASS or CPAL_FAIL. - */ -void CPAL_I2C_TIMEOUT_Manager(void) -{ - uint32_t index = 0; - - /* Manage I2C timeouts conditions */ - for (index = 0; index < CPAL_I2C_DEV_NUM; index ++) - { - if (I2C_DevStructures[index] != pNULL) - { - /* If Timeout occurred */ - if (I2C_DevStructures[index]->wCPAL_Timeout == CPAL_I2C_TIMEOUT_DETECTED) - { - /* Reinitialize timeout value */ - I2C_DevStructures[index]->wCPAL_Timeout = CPAL_I2C_TIMEOUT_DEFAULT; - - /* Update CPAL_State to CPAL_STATE_ERROR */ - I2C_DevStructures[index]->CPAL_State = CPAL_STATE_ERROR; - - /* In case of Device Error Timeout_Callback should not be called */ - if (I2C_DevStructures[index]->wCPAL_DevError == CPAL_I2C_ERR_NONE) - { - /* Update wCPAL_DevError to CPAL_I2C_ERR_TIMEOUT */ - I2C_DevStructures[index]->wCPAL_DevError = CPAL_I2C_ERR_TIMEOUT; - - CPAL_LOG("\n\r\n\rLOG : I2C Device Timeout Error"); - - /* Call CPAL_TIMEOUT_UserCallback */ - CPAL_TIMEOUT_UserCallback(I2C_DevStructures[index]); - } - } - /* If Timeout is triggered (wCPAL_Timeout != CPAL_I2C_TIMEOUT_DEFAULT)*/ - else if (I2C_DevStructures[index]->wCPAL_Timeout != CPAL_I2C_TIMEOUT_DEFAULT) - { - /* Decrement the timeout value */ - I2C_DevStructures[index]->wCPAL_Timeout--; - } - } - } -} - - -/** - * @brief This function Manages I2C Timeouts when Timeout occurred. - * @param pDevInitStruct: Pointer to the peripheral configuration structure. - * @retval CPAL_PASS or CPAL_FAIL. - */ -uint32_t CPAL_I2C_Timeout (CPAL_InitTypeDef* pDevInitStruct) -{ - /* Reinitialize timeout value */ - pDevInitStruct->wCPAL_Timeout = CPAL_I2C_TIMEOUT_DEFAULT; - - /* update CPAL_State to CPAL_STATE_ERROR */ - pDevInitStruct->CPAL_State = CPAL_STATE_ERROR; - - /* update wCPAL_DevError to CPAL_I2C_ERR_TIMEOUT */ - pDevInitStruct->wCPAL_DevError = CPAL_I2C_ERR_TIMEOUT; - - /* Call Timeout Callback and quit current function */ - return (CPAL_TIMEOUT_UserCallback(pDevInitStruct)); -} - -/*================== CPAL_I2C_Event_Handler ==================*/ - -#ifdef CPAL_I2C_MASTER_MODE -/** - * @brief Handles Master TCR interrupt event. - * @param pDevInitStruct: Pointer to the peripheral configuration structure. - * @retval CPAL_PASS or CPAL_FAIL. - */ -static uint32_t I2C_MASTER_TCR_Handle(CPAL_InitTypeDef* pDevInitStruct) -{ - CR2_tmp = 0; - - /* If DMA programming model */ - if (pDevInitStruct->CPAL_ProgModel == CPAL_PROGMODEL_DMA) - { - /* If master transmitter */ - if (pDevInitStruct->CPAL_State == CPAL_STATE_BUSY_TX) - { - /* Update wNumData */ - pDevInitStruct->pCPAL_TransferTx->wNumData = pDevInitStruct->pCPAL_TransferTx->wNumData - 0xff; - } - /* If master receiver */ - else - { - /* Update wNumData */ - pDevInitStruct->pCPAL_TransferRx->wNumData = pDevInitStruct->pCPAL_TransferRx->wNumData - 0xff; - } - } - - /* If master transmitter */ - if (pDevInitStruct->CPAL_State == CPAL_STATE_BUSY_TX) - { - /* If remaining number of data is equal or lower than 255 */ - if (pDevInitStruct->pCPAL_TransferTx->wNumData <= 0xff) - { - /* Update Num_Data */ - Num_Data = pDevInitStruct->pCPAL_TransferTx->wNumData; - - /* Set Nbytes to wNumData */ - CR2_tmp |= (uint32_t)((uint32_t)(Num_Data) << 16); - - /* Disable reload */ - CR2_tmp &= ~I2C_CR2_RELOAD; - } - /* If remaining number of data is greater than 255 */ - else - { - /* Set Nbytes to wNumData */ - CR2_tmp |= (uint32_t)((uint32_t)(255) << 16); - - /* Enaable reload */ - CR2_tmp |= I2C_CR2_RELOAD; - } - } - /* If master receiver */ - else - { - /* If remaining number of data is equal or lower than 255 */ - if (pDevInitStruct->pCPAL_TransferRx->wNumData <= 0xff) - { - /* Update num data */ - Num_Data = pDevInitStruct->pCPAL_TransferRx->wNumData; - - /* Set Nbytes to wNumData */ - CR2_tmp |= (uint32_t)((uint32_t)(Num_Data) << 16); - - /* Disable reload */ - CR2_tmp &= ~I2C_CR2_RELOAD; - - } - /* If remaining number of data is greater than 255 */ - else - { - /* Set Nbytes to wNumData */ - CR2_tmp |= (uint32_t)((uint32_t)(255) << 16); - - /* Enaable reload */ - CR2_tmp |= I2C_CR2_RELOAD; - } - } - - /* Update CR2 Register */ - __CPAL_I2C_HAL_CR2_UPDATE(pDevInitStruct->CPAL_Dev, CR2_tmp); - - return CPAL_PASS; -} - -/** - * @brief Handles Master TC interrupt event. - * @param pDevInitStruct: Pointer to the peripheral configuration structure. - * @retval CPAL_PASS or CPAL_FAIL. - */ -static uint32_t I2C_MASTER_TC_Handle(CPAL_InitTypeDef* pDevInitStruct) -{ - /* No Stop Condition Generation option bit is not selected */ - if ((pDevInitStruct->wCPAL_Options & CPAL_OPT_I2C_NOSTOP) == 0) - { - /* Generate stop condition */ - __CPAL_I2C_HAL_STOP(pDevInitStruct->CPAL_Dev); - } - /* No Stop Condition Generation option bit is selected */ - else - { - /* Disable master interrupts */ - __CPAL_I2C_HAL_DISABLE_MASTER_IT(pDevInitStruct->CPAL_Dev); - - /* If master transmitter */ - if (pDevInitStruct->CPAL_State == CPAL_STATE_BUSY_TX) - { - #ifdef CPAL_I2C_IT_PROGMODEL - /* If Interrupt Programming Model */ - if (pDevInitStruct->CPAL_ProgModel == CPAL_PROGMODEL_INTERRUPT) - { - /* Disable TX interrupt */ - __CPAL_I2C_HAL_DISABLE_TXIE_IT(pDevInitStruct->CPAL_Dev); - } - #endif /* CPAL_I2C_IT_PROGMODEL */ - - /* Update CPAL_State to CPAL_STATE_READY */ - pDevInitStruct->CPAL_State = CPAL_STATE_READY; - - /* Call TX Transfer complete Callback */ - CPAL_I2C_TXTC_UserCallback(pDevInitStruct); - } - /* If master receiver */ - else - { - #ifdef CPAL_I2C_IT_PROGMODEL - /* If Interrupt Programming Model */ - if (pDevInitStruct->CPAL_ProgModel == CPAL_PROGMODEL_INTERRUPT) - { - /* Disable RX interrupt */ - __CPAL_I2C_HAL_DISABLE_RXIE_IT(pDevInitStruct->CPAL_Dev); - } - #endif /* CPAL_I2C_IT_PROGMODEL */ - - /* Update CPAL_State to CPAL_STATE_READY */ - pDevInitStruct->CPAL_State = CPAL_STATE_READY; - - /* Call RX Transfer complete Callback */ - CPAL_I2C_RXTC_UserCallback(pDevInitStruct); - } - } - return CPAL_PASS; -} - -/** - * @brief Handles Master STOP interrupt event. - * @param pDevInitStruct: Pointer to the peripheral configuration structure. - * @retval CPAL_PASS or CPAL_FAIL. - */ -static uint32_t I2C_MASTER_STOP_Handle(CPAL_InitTypeDef* pDevInitStruct) -{ - /* If NACK received by master */ - if (pDevInitStruct->wCPAL_DevError == CPAL_I2C_ERR_AF) - { - /* Set CPAL_State to CPAL_STATE_ERROR */ - pDevInitStruct->CPAL_State = CPAL_STATE_ERROR; - - /* Clear STOP flag */ - __CPAL_I2C_HAL_CLEAR_STOP(pDevInitStruct->CPAL_Dev); - } - else - { - /* Clear STOP flag */ - __CPAL_I2C_HAL_CLEAR_STOP(pDevInitStruct->CPAL_Dev); - - CPAL_LOG("\n\r\n\rLOG : I2C Device Master IT"); - - CPAL_LOG("\n\rLOG : I2C Device Stop Generated"); - - /* Disable master interrupt */ - __CPAL_I2C_HAL_DISABLE_MASTER_IT(pDevInitStruct->CPAL_Dev); - - /* Wait until BUSY flag is reset */ - __CPAL_I2C_TIMEOUT(!(__CPAL_I2C_HAL_GET_BUSY(pDevInitStruct->CPAL_Dev)), CPAL_I2C_TIMEOUT_BUSY); - - /* If master transmitter */ - if (pDevInitStruct->CPAL_State == CPAL_STATE_BUSY_TX) - { - #ifdef CPAL_I2C_IT_PROGMODEL - /* If Interrupt Programming Model */ - if (pDevInitStruct->CPAL_ProgModel == CPAL_PROGMODEL_INTERRUPT) - { - /* Disable TX interrupt */ - __CPAL_I2C_HAL_DISABLE_TXIE_IT(pDevInitStruct->CPAL_Dev); - } - #endif /* CPAL_I2C_IT_PROGMODEL */ - - /* Update CPAL_State to CPAL_STATE_READY */ - pDevInitStruct->CPAL_State = CPAL_STATE_READY; - - /* Call TX Transfer complete Callback */ - CPAL_I2C_TXTC_UserCallback(pDevInitStruct); - } - /* If master receiver */ - else - { - #ifdef CPAL_I2C_IT_PROGMODEL - /* If Interrupt Programming Model */ - if (pDevInitStruct->CPAL_ProgModel == CPAL_PROGMODEL_INTERRUPT) - { - /* Disable RX interrupt */ - __CPAL_I2C_HAL_DISABLE_RXIE_IT(pDevInitStruct->CPAL_Dev); - } - #endif /* CPAL_I2C_IT_PROGMODEL */ - - /* Update CPAL_State to CPAL_STATE_READY */ - pDevInitStruct->CPAL_State = CPAL_STATE_READY; - - /* Call RX Transfer complete Callback */ - CPAL_I2C_RXTC_UserCallback(pDevInitStruct); - } - } - return CPAL_PASS; -} - -/** - * @brief Handles Master NACK interrupt event. - * @param pDevInitStruct: Pointer to the peripheral configuration structure. - * @retval CPAL_PASS or CPAL_FAIL. - */ -static uint32_t I2C_MASTER_NACK_Handle(CPAL_InitTypeDef* pDevInitStruct) -{ - /* Update wCPAL_DevError */ - pDevInitStruct->wCPAL_DevError = CPAL_I2C_ERR_AF; - - /* Clear NACK flag */ - __CPAL_I2C_HAL_CLEAR_NACK(pDevInitStruct->CPAL_Dev); - - /* USE_SINGLE_ERROR_CALLBACK is defined in stm32f0xx_i2c_cpal_conf.h file */ -#ifdef USE_SINGLE_ERROR_CALLBACK - /* Call Error UserCallback */ - CPAL_I2C_ERR_UserCallback(pDevInitStruct->CPAL_Dev, pDevInitStruct->wCPAL_DevError); -#elif defined(USE_MULTIPLE_ERROR_CALLBACK) - /* Call AF UserCallback */ - CPAL_I2C_AF_UserCallback(pDevInitStruct->CPAL_Dev); -#endif /* USE_SINGLE_ERROR_CALLBACK */ - - return CPAL_PASS; -} - - #ifdef CPAL_I2C_IT_PROGMODEL -/** - * @brief Handles Master transmission TXIS interrupt event. - * @param pDevInitStruct: Pointer to the peripheral configuration structure. - * @retval CPAL_PASS or CPAL_FAIL. - */ -static uint32_t I2C_MASTER_TXIS_Handle(CPAL_InitTypeDef* pDevInitStruct) -{ - /* Call TX UserCallback */ - CPAL_I2C_TX_UserCallback(pDevInitStruct); - - /* Write Byte */ - __CPAL_I2C_HAL_SEND((pDevInitStruct->CPAL_Dev), (*(pDevInitStruct->pCPAL_TransferTx->pbBuffer))); - - /* Decrement remaining number of data */ - pDevInitStruct->pCPAL_TransferTx->wNumData--; - - if (pDevInitStruct->pCPAL_TransferTx->wNumData != 0) - { - /* Point to next data */ - pDevInitStruct->pCPAL_TransferTx->pbBuffer++; - } - return CPAL_PASS; -} - -/** - * @brief Handles Master reception RXNE interrupt event. - * @param pDevInitStruct: Pointer to the peripheral configuration structure. - * @retval CPAL_PASS or CPAL_FAIL. - */ -static uint32_t I2C_MASTER_RXNE_Handle(CPAL_InitTypeDef* pDevInitStruct) -{ - /* Read Byte */ - *(pDevInitStruct->pCPAL_TransferRx->pbBuffer) = __CPAL_I2C_HAL_RECEIVE(pDevInitStruct->CPAL_Dev); - - /* Call RX UserCallback */ - CPAL_I2C_RX_UserCallback(pDevInitStruct); - - /* Decrement remaining number of data */ - pDevInitStruct->pCPAL_TransferRx->wNumData--; - - /* If data remaining for reception */ - if (pDevInitStruct->pCPAL_TransferRx->wNumData != 0) - { - /* Point to next data */ - pDevInitStruct->pCPAL_TransferRx->pbBuffer++; - } - return CPAL_PASS; -} - #endif /* CPAL_I2C_IT_PROGMODEL */ -#endif /* CPAL_I2C_MASTER_MODE */ - - -#ifdef CPAL_I2C_SLAVE_MODE -/** - * @brief Handles Slave ADDR interrupt event. - * @param pDevInitStruct: Pointer to the peripheral configuration structure. - * @retval CPAL_PASS or CPAL_FAIL. - */ -static uint32_t I2C_SLAVE_ADDR_Handle(CPAL_InitTypeDef* pDevInitStruct) -{ -#ifdef CPAL_I2C_LISTEN_MODE - /* If slave receive request for write */ - if (__CPAL_I2C_HAL_GET_DIR(pDevInitStruct->CPAL_Dev) == 0) - { - pDevInitStruct->CPAL_State = CPAL_STATE_BUSY_RX; - - /* Call Slave receive UserCallback */ - CPAL_I2C_SLAVE_READ_UserCallback(pDevInitStruct); - } - /* If slave receive request for read */ - else - { - pDevInitStruct->CPAL_State = CPAL_STATE_BUSY_TX; - - /* Call Slave Transmit UserCallback */ - CPAL_I2C_SLAVE_WRITE_UserCallback(pDevInitStruct); - } -#else - uint32_t slaveaddr = 0; - - /* If 7 Bit Addressing Mode */ - if (pDevInitStruct->pCPAL_I2C_Struct->I2C_AcknowledgedAddress == I2C_AcknowledgedAddress_7bit) - { - /* Get slave matched address */ - slaveaddr = __CPAL_I2C_HAL_GET_ADDCODE(pDevInitStruct->CPAL_Dev); - - /* if matched address is not equal to OA1 */ - if (slaveaddr !=__CPAL_I2C_HAL_GET_OA1(pDevInitStruct->CPAL_Dev)) - { - /* If General Call addressing mode selected */ - if ( slaveaddr == 0x00000000) - { - CPAL_LOG("\n\rLOG : I2C Device GENCALL Mode"); - - /* Call GENCALL UserCallback */ - CPAL_I2C_GENCALL_UserCallback(pDevInitStruct); - } - /* If DUAL addressing mode selected */ - else - { - CPAL_LOG("\n\rLOG : I2C Device DUAL ADDR Mode Selected"); - - /* Call DUALF UserCallback */ - CPAL_I2C_DUALF_UserCallback(pDevInitStruct); - } - } - } -#endif /* CPAL_I2C_LISTEN_MODE */ - - /* Clear ADDR flag */ - __CPAL_I2C_HAL_CLEAR_ADDR(pDevInitStruct->CPAL_Dev); - - return CPAL_PASS; -} - -/** - * @brief Handles Slave STOP interrupt event. - * @param pDevInitStruct: Pointer to the peripheral configuration structure. - * @retval CPAL_PASS or CPAL_FAIL. - */ -static uint32_t I2C_SLAVE_STOP_Handle(CPAL_InitTypeDef* pDevInitStruct) -{ - /* Clear STOP flag */ - __CPAL_I2C_HAL_CLEAR_STOP(pDevInitStruct->CPAL_Dev); - - CPAL_LOG("\n\r\n\rLOG : I2C Device Slave IT"); - - CPAL_LOG("\n\rLOG : I2C Device Stop Detected"); - - /* Disable slave interrupt */ - __CPAL_I2C_HAL_DISABLE_SLAVE_IT(pDevInitStruct->CPAL_Dev); - - /* Wait until BUSY flag is reset */ - __CPAL_I2C_TIMEOUT(!(__CPAL_I2C_HAL_GET_BUSY(pDevInitStruct->CPAL_Dev)), CPAL_I2C_TIMEOUT_BUSY); - - /* If NACK Slave Own Address option bit selected */ - if ((pDevInitStruct->wCPAL_Options & CPAL_OPT_I2C_NACK_ADD) != 0) - { - /* Disable Acknowledgement of own Address */ - __CPAL_I2C_HAL_DISABLE_DEV(pDevInitStruct->CPAL_Dev); - } - - /* If slave transmitter */ - if (pDevInitStruct->CPAL_State == CPAL_STATE_BUSY_TX) - { - #ifdef CPAL_I2C_IT_PROGMODEL - /* If Interrupt Programming Model */ - if (pDevInitStruct->CPAL_ProgModel == CPAL_PROGMODEL_INTERRUPT) - { - /* Disable TX interrupt */ - __CPAL_I2C_HAL_DISABLE_TXIE_IT(pDevInitStruct->CPAL_Dev); - } - #endif /* CPAL_I2C_IT_PROGMODEL */ - - /* Update CPAL_State to CPAL_STATE_READY */ - pDevInitStruct->CPAL_State = CPAL_STATE_READY; - - /* Call TX Transfer complete Callback */ - CPAL_I2C_TXTC_UserCallback(pDevInitStruct); - } - /* If slave receiver */ - else - { - #ifdef CPAL_I2C_IT_PROGMODEL - /* If Interrupt Programming Model */ - if (pDevInitStruct->CPAL_ProgModel == CPAL_PROGMODEL_INTERRUPT) - { - /* Disable RX interrupt */ - __CPAL_I2C_HAL_DISABLE_RXIE_IT(pDevInitStruct->CPAL_Dev); - } - #endif /* CPAL_I2C_IT_PROGMODEL */ - - /* Update CPAL_State to CPAL_STATE_READY */ - pDevInitStruct->CPAL_State = CPAL_STATE_READY; - - /* Call RX Transfer complete Callback */ - CPAL_I2C_RXTC_UserCallback(pDevInitStruct); - } - return CPAL_PASS; -} - -/** - * @brief Handles Slave NACK interrupt event. - * @param pDevInitStruct: Pointer to the peripheral configuration structure. - * @retval CPAL_PASS or CPAL_FAIL. - */ -static uint32_t I2C_SLAVE_NACK_Handle(CPAL_InitTypeDef* pDevInitStruct) -{ - /* Clear NACK flag */ - __CPAL_I2C_HAL_CLEAR_NACK(pDevInitStruct->CPAL_Dev); - - /* No Stop Condition Generation option bit selected and slave transmitter */ - if (((pDevInitStruct->wCPAL_Options & CPAL_OPT_I2C_NOSTOP) != 0) && (pDevInitStruct->CPAL_State == CPAL_STATE_BUSY_TX)) - { - /* Disable slave interrupt */ - __CPAL_I2C_HAL_DISABLE_SLAVE_IT(pDevInitStruct->CPAL_Dev); - - #ifdef CPAL_I2C_IT_PROGMODEL - /* If Interrupt Programming Model */ - if (pDevInitStruct->CPAL_ProgModel == CPAL_PROGMODEL_INTERRUPT) - { - /* Disable TX interrupt */ - __CPAL_I2C_HAL_DISABLE_TXIE_IT(pDevInitStruct->CPAL_Dev); - } - #endif /* CPAL_I2C_IT_PROGMODEL */ - - /* Update CPAL_State to CPAL_STATE_READY */ - pDevInitStruct->CPAL_State = CPAL_STATE_READY; - - /* Call TX Transfer complete Callback */ - CPAL_I2C_TXTC_UserCallback(pDevInitStruct); - } - return CPAL_PASS; -} - - #ifdef CPAL_I2C_IT_PROGMODEL -/** - * @brief Handles Slave transmission TXIS interrupt event. - * @param pDevInitStruct: Pointer to the peripheral configuration structure. - * @retval CPAL_PASS or CPAL_FAIL. - */ -static uint32_t I2C_SLAVE_TXIS_Handle(CPAL_InitTypeDef* pDevInitStruct) -{ - /* If data remaining for transmission */ - if (pDevInitStruct->pCPAL_TransferTx->wNumData != 0) - { - /* Call TX UserCallback */ - CPAL_I2C_TX_UserCallback(pDevInitStruct); - - /* Write Byte */ - __CPAL_I2C_HAL_SEND((pDevInitStruct->CPAL_Dev), (*(pDevInitStruct->pCPAL_TransferTx->pbBuffer))); - - /* Decrement remaining number of data */ - pDevInitStruct->pCPAL_TransferTx->wNumData--; - - if (pDevInitStruct->pCPAL_TransferTx->wNumData != 0) - { - /* Point to next data */ - pDevInitStruct->pCPAL_TransferTx->pbBuffer++; - } - } - return CPAL_PASS; -} - -/** - * @brief Handles Slave reception RXNE interrupt event. - * @param pDevInitStruct: Pointer to the peripheral configuration structure. - * @retval CPAL_PASS or CPAL_FAIL. - */ -static uint32_t I2C_SLAVE_RXNE_Handle(CPAL_InitTypeDef* pDevInitStruct) -{ - /* If data remaining for reception */ - if (pDevInitStruct->pCPAL_TransferRx->wNumData != 0) - { - /* Read Byte */ - *(pDevInitStruct->pCPAL_TransferRx->pbBuffer) = __CPAL_I2C_HAL_RECEIVE(pDevInitStruct->CPAL_Dev); - - /* Call RX UserCallback */ - CPAL_I2C_RX_UserCallback(pDevInitStruct); - - /* Decrement remaining number of data */ - pDevInitStruct->pCPAL_TransferRx->wNumData--; - - /* If data remaining for reception */ - if (pDevInitStruct->pCPAL_TransferRx->wNumData != 0) - { - /* Point to next data */ - pDevInitStruct->pCPAL_TransferRx->pbBuffer++; - } - /* If all data received and No Stop Condition Generation option bit selected */ - else if ((pDevInitStruct->wCPAL_Options & CPAL_OPT_I2C_NOSTOP) != 0) - { - /* Disable slave interrupt */ - __CPAL_I2C_HAL_DISABLE_SLAVE_IT(pDevInitStruct->CPAL_Dev); - - /* Disable RX interrupt */ - __CPAL_I2C_HAL_DISABLE_RXIE_IT(pDevInitStruct->CPAL_Dev); - - /* Update CPAL_State to CPAL_STATE_READY */ - pDevInitStruct->CPAL_State = CPAL_STATE_READY; - - /* Call RX Transfer complete Callback */ - CPAL_I2C_RXTC_UserCallback(pDevInitStruct); - } - } - return CPAL_PASS; -} - #endif /* CPAL_I2C_IT_PROGMODEL */ -#endif /* CPAL_I2C_SLAVE_MODE */ - - - -/*================== Local DMA and IT Manager ==================*/ - -#ifdef CPAL_I2C_DMA_PROGMODEL -/** - * @brief This function Configures and enables I2C DMA before starting transfer phase. - * @param pDevInitStruct: Pointer to the peripheral configuration structure. - * @param Direction : Transfer direction. - * @retval CPAL_PASS or CPAL_FAIL. - */ -static uint32_t I2C_Enable_DMA (CPAL_InitTypeDef* pDevInitStruct, CPAL_DirectionTypeDef Direction) -{ - /* If data transmission will be performed */ - if ((pDevInitStruct->CPAL_State == CPAL_STATE_BUSY_TX) || (Direction == CPAL_DIRECTION_TX)) - { - /* Configure TX DMA channels */ - CPAL_I2C_HAL_DMATXConfig(pDevInitStruct->CPAL_Dev, pDevInitStruct->pCPAL_TransferTx, pDevInitStruct->wCPAL_Options); - - /* Enable TX DMA channels */ - __CPAL_I2C_HAL_ENABLE_DMATX(pDevInitStruct->CPAL_Dev); - - CPAL_LOG("\n\rLOG : I2C Device DMA TX Configured and Enabled"); - } - /* If data reception will be performed */ - else if ((pDevInitStruct->CPAL_State == CPAL_STATE_BUSY_RX) || (Direction == CPAL_DIRECTION_RX)) - { - /* Configure RX DMA channels */ - CPAL_I2C_HAL_DMARXConfig(pDevInitStruct->CPAL_Dev, pDevInitStruct->pCPAL_TransferRx, pDevInitStruct->wCPAL_Options); - - /* Enable RX DMA channels */ - __CPAL_I2C_HAL_ENABLE_DMARX(pDevInitStruct->CPAL_Dev); - - CPAL_LOG("\n\rLOG : I2C Device DMA RX Configured and Enabled"); - } - return CPAL_PASS; -} -#endif /* CPAL_I2C_DMA_PROGMODEL */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_CPAL_Driver/src/stm32f0xx_i2c_cpal_hal.c b/libraries/STM32F0xx_CPAL_Driver/src/stm32f0xx_i2c_cpal_hal.c deleted file mode 100644 --- a/libraries/STM32F0xx_CPAL_Driver/src/stm32f0xx_i2c_cpal_hal.c +++ /dev/null @@ -1,615 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_i2c_cpal_hal.c - * @author MCD Application Team - * @version V1.2.0 - * @date 24-July-2014 - * @brief This file provides all the CPAL_I2C_HAL (hardware Abstraction Layer) - * firmware functions. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_i2c_cpal_hal.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private defines -----------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ - - -/* Private variables ---------------------------------------------------------*/ - -/*========= Local Structures declaration =========*/ - -CPAL_InitTypeDef* I2C_DevStructures[CPAL_I2C_DEV_NUM] = -{ -#ifdef CPAL_USE_I2C1 - &I2C1_DevStructure, -#else - pNULL, -#endif - -#ifdef CPAL_USE_I2C2 - &I2C2_DevStructure, -#else - pNULL, -#endif -}; - - -#ifdef CPAL_USE_I2C1 -CPAL_InitTypeDef I2C1_DevStructure = { CPAL_I2C1, /* I2C1 device number */ - CPAL_DIRECTION_TXRX, /* Transmitter and Receiver direction selected */ - CPAL_MODE_MASTER, /* Mode Master selected */ - #ifdef CPAL_I2C_DMA_PROGMODEL - CPAL_PROGMODEL_DMA, /* DMA Programming Model selected */ - #else - CPAL_PROGMODEL_INTERRUPT, /* IT Programming Model selected */ - #endif /* CPAL_I2C_DMA_PROGMODEL */ - (CPAL_TransferTypeDef*) pNULL, /* Point pCPAL_TransferTx to a Null pointer */ - (CPAL_TransferTypeDef*) pNULL, /* Point pCPAL_TransferRx to a Null pointer */ - CPAL_STATE_DISABLED, /* Device Disabled */ - CPAL_I2C_ERR_NONE, /* No Device Error */ - ((uint32_t)0x00000000), /* No Options selected */ - ((uint32_t)CPAL_I2C_TIMEOUT_DEFAULT),/* Set timeout value to CPAL_I2C_TIMEOUT_DEFAULT */ - (I2C_InitTypeDef*) pNULL}; /* Point pCPAL_I2C_Struct to a Null pointer */ - -#endif /* CPAL_USE_I2C1 */ - -#ifdef CPAL_USE_I2C2 -CPAL_InitTypeDef I2C2_DevStructure = { CPAL_I2C2, /* I2C2 device number */ - CPAL_DIRECTION_TXRX, /* Transmitter and Receiver direction selected */ - CPAL_MODE_MASTER, /* Mode Master selected */ - #ifdef CPAL_I2C_DMA_PROGMODEL - CPAL_PROGMODEL_DMA, /* DMA Programming Model selected */ - #else - CPAL_PROGMODEL_INTERRUPT, /* IT Programming Model selected */ - #endif /* CPAL_I2C_DMA_PROGMODEL */ - (CPAL_TransferTypeDef*) pNULL, /* Point pCPAL_TransferTx to a Null pointer */ - (CPAL_TransferTypeDef*) pNULL, /* Point pCPAL_TransferRx to a Null pointer */ - CPAL_STATE_DISABLED, /* Device Disabled */ - CPAL_I2C_ERR_NONE, /* No Device Error */ - ((uint32_t)0x00000000), /* No Options selected */ - ((uint32_t)CPAL_I2C_TIMEOUT_DEFAULT),/* Set timeout value to CPAL_I2C_TIMEOUT_DEFAULT */ - (I2C_InitTypeDef*) pNULL}; /* Point pCPAL_I2C_Struct to a Null pointer */ -#endif /* CPAL_USE_I2C2 */ - - -DMA_InitTypeDef CPAL_DMA_InitStructure; - -I2C_TypeDef* CPAL_I2C_DEVICE[2] = {I2C1,I2C2}; - -const uint32_t CPAL_I2C_CLK[2] = {CPAL_I2C1_CLK,CPAL_I2C2_CLK}; -const uint32_t CPAL_I2C_TXDR[2] = {CPAL_I2C1_TXDR,CPAL_I2C2_TXDR}; -const uint32_t CPAL_I2C_RXDR[2] = {CPAL_I2C1_RXDR,CPAL_I2C2_RXDR}; -const uint32_t CPAL_I2C_AF[2] = {CPAL_I2C1_AF,CPAL_I2C2_AF}; - -const GPIO_TypeDef* CPAL_I2C_SCL_GPIO_PORT[2] = {CPAL_I2C1_SCL_GPIO_PORT,CPAL_I2C2_SCL_GPIO_PORT}; -const uint16_t CPAL_I2C_SCL_GPIO_PIN[2] = {CPAL_I2C1_SCL_GPIO_PIN,CPAL_I2C2_SCL_GPIO_PIN}; -const uint32_t CPAL_I2C_SCL_GPIO_CLK[2] = {CPAL_I2C1_SCL_GPIO_CLK,CPAL_I2C2_SCL_GPIO_CLK}; -const uint16_t CPAL_I2C_SCL_GPIO_PINSOURCE[2] = {CPAL_I2C1_SCL_GPIO_PINSOURCE,CPAL_I2C2_SCL_GPIO_PINSOURCE}; - -const GPIO_TypeDef* CPAL_I2C_SDA_GPIO_PORT[2] = {CPAL_I2C1_SDA_GPIO_PORT,CPAL_I2C2_SDA_GPIO_PORT}; -const uint16_t CPAL_I2C_SDA_GPIO_PIN[2] = {CPAL_I2C1_SDA_GPIO_PIN,CPAL_I2C2_SDA_GPIO_PIN}; -const uint32_t CPAL_I2C_SDA_GPIO_CLK[2] = {CPAL_I2C1_SDA_GPIO_CLK,CPAL_I2C2_SDA_GPIO_CLK}; -const uint16_t CPAL_I2C_SDA_GPIO_PINSOURCE[2] = {CPAL_I2C1_SDA_GPIO_PINSOURCE,CPAL_I2C2_SDA_GPIO_PINSOURCE}; - -const uint32_t CPAL_I2C_DMA_CLK[2] = {CPAL_I2C1_DMA_CLK,CPAL_I2C2_DMA_CLK}; - -DMA_Channel_TypeDef* CPAL_I2C_DMA_TX_Channel[2] = {CPAL_I2C1_DMA_TX_Channel, CPAL_I2C2_DMA_TX_Channel}; -DMA_Channel_TypeDef* CPAL_I2C_DMA_RX_Channel[2] = {CPAL_I2C1_DMA_RX_Channel, CPAL_I2C2_DMA_RX_Channel}; - -const IRQn_Type CPAL_I2C_DMA_IRQn[2] = {CPAL_I2C1_DMA_IRQn, CPAL_I2C2_DMA_IRQn}; - -const IRQn_Type CPAL_I2C_IT_IRQn[2] = {CPAL_I2C1_IT_IRQn, CPAL_I2C2_IT_IRQn}; - -const uint8_t I2C_IT_PRIO[2] = {I2C1_IT_PRIO, I2C2_IT_PRIO}; - -const uint8_t I2C_IT_DMA_PRIO[2] = {I2C1_IT_DMA_PRIO, I2C2_IT_DMA_PRIO}; - -DMA_TypeDef* CPAL_I2C_DMA[2] = {CPAL_I2C1_DMA,CPAL_I2C2_DMA}; - -const uint32_t CPAL_I2C_DMA_TX_TC_FLAG[2] = {CPAL_I2C1_DMA_TX_TC_FLAG, CPAL_I2C2_DMA_TX_TC_FLAG}; -const uint32_t CPAL_I2C_DMA_TX_HT_FLAG[2] = {CPAL_I2C1_DMA_TX_HT_FLAG, CPAL_I2C2_DMA_TX_HT_FLAG}; -const uint32_t CPAL_I2C_DMA_TX_TE_FLAG[2] = {CPAL_I2C1_DMA_TX_TE_FLAG, CPAL_I2C2_DMA_TX_TE_FLAG}; - -const uint32_t CPAL_I2C_DMA_RX_TC_FLAG[2] = {CPAL_I2C1_DMA_RX_TC_FLAG, CPAL_I2C2_DMA_RX_TC_FLAG}; -const uint32_t CPAL_I2C_DMA_RX_HT_FLAG[2] = {CPAL_I2C1_DMA_RX_HT_FLAG, CPAL_I2C2_DMA_RX_HT_FLAG}; -const uint32_t CPAL_I2C_DMA_RX_TE_FLAG[2] = {CPAL_I2C1_DMA_RX_TE_FLAG, CPAL_I2C2_DMA_RX_TE_FLAG}; - - - -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/*================== CPAL_I2C_HAL_Config ==================*/ - -/** - * @brief Reset then enable the I2C device clock. - * @param Device : I2C Device instance. - * @retval None - */ -void CPAL_I2C_HAL_CLKInit(CPAL_DevTypeDef Device) -{ - /* Reset I2Cx device clock in order to avoid non-cleared error flags */ - __I2C_RCC_RESET(CPAL_I2C_CLK [Device]); - - /* Enable I2Cx device clock */ - __I2C_CLK_CMD(CPAL_I2C_CLK [Device], ENABLE); -} - - -/** - * @brief Reset then disable the I2C device clock. - * @param Device : I2C Device instance - * @retval None. - */ -void CPAL_I2C_HAL_CLKDeInit(CPAL_DevTypeDef Device) -{ - /* Reset I2Cx device clock in order to avoid non-cleared error flags */ - __I2C_RCC_RESET(CPAL_I2C_CLK[Device]); - - /* Disable I2Cx device clock */ - __I2C_CLK_CMD(CPAL_I2C_CLK[Device], DISABLE); -} - - -/** - * @brief Configure the IO pins used by the I2C device. - * @param Device : I2C Device instance. - * @retval None. - */ -void CPAL_I2C_HAL_GPIOInit(CPAL_DevTypeDef Device) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /* Enable I2Cx SCL and SDA Pin Clock */ - __I2C_GPIO_CLK_CMD((CPAL_I2C_SCL_GPIO_CLK[Device] | CPAL_I2C_SDA_GPIO_CLK[Device]), ENABLE); - - /* Connect PXx to I2C_SCL */ - GPIO_PinAFConfig((GPIO_TypeDef*)CPAL_I2C_SCL_GPIO_PORT[Device],CPAL_I2C_SCL_GPIO_PINSOURCE[Device],CPAL_I2C_AF[Device]); - - /* Connect PXx to I2C_SDA */ - GPIO_PinAFConfig((GPIO_TypeDef*)CPAL_I2C_SDA_GPIO_PORT[Device],CPAL_I2C_SDA_GPIO_PINSOURCE[Device],CPAL_I2C_AF[Device]); - - /* Set GPIO frequency to 50MHz */ - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - - /* Select Alternate function mode */ - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - - /* Select output Open Drain type */ - GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; - - /* Disable internal Pull-up */ - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - - /* Initialize I2Cx SCL Pin */ - GPIO_InitStructure.GPIO_Pin = CPAL_I2C_SCL_GPIO_PIN[Device]; - GPIO_Init((GPIO_TypeDef*)CPAL_I2C_SCL_GPIO_PORT[Device], &GPIO_InitStructure); - - /* Initialize I2Cx SDA Pin */ - GPIO_InitStructure.GPIO_Pin = CPAL_I2C_SDA_GPIO_PIN[Device]; - GPIO_Init((GPIO_TypeDef*)CPAL_I2C_SDA_GPIO_PORT[Device], &GPIO_InitStructure); -} - - -/** - * @brief Deinitialize the IO pins used by the I2C device - * (configured to their default state). - * @param Device : I2C Device instance. - * @retval None. - */ -void CPAL_I2C_HAL_GPIODeInit(CPAL_DevTypeDef Device) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /* Set GPIO frequency to 50MHz */ - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - - /* Select Input floating mode */ - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - - /* Select output Open Drain type */ - GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; - - /* Disable internal Pull-up */ - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - - /* Deinitialize I2Cx SCL Pin */ - GPIO_InitStructure.GPIO_Pin = CPAL_I2C_SCL_GPIO_PIN[Device]; - GPIO_Init((GPIO_TypeDef*)CPAL_I2C_SCL_GPIO_PORT[Device], &GPIO_InitStructure); - - /* Deinitialize I2Cx SDA Pin */ - GPIO_InitStructure.GPIO_Pin = CPAL_I2C_SDA_GPIO_PIN[Device]; - GPIO_Init((GPIO_TypeDef*)CPAL_I2C_SDA_GPIO_PORT[Device], &GPIO_InitStructure); -} - - - -#ifdef CPAL_I2C_DMA_PROGMODEL -/** - * @brief Enable the DMA clock and initialize needed DMA Channels - * used by the I2C device. - * @param Device : I2C Device instance. - * @param Direction : Transfer direction. - * @param Options : Transfer Options. - * @retval None. - */ -void CPAL_I2C_HAL_DMAInit(CPAL_DevTypeDef Device, CPAL_DirectionTypeDef Direction, uint32_t Options) -{ - /* Enable I2Cx DMA */ - __DMA_CLK_CMD(CPAL_I2C_DMA_CLK[Device], ENABLE); - - /* I2Cx Common Channel Configuration */ - CPAL_DMA_InitStructure.DMA_BufferSize = 0xFFFF; - CPAL_DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; - CPAL_DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; - CPAL_DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte ; - CPAL_DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; - CPAL_DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh; - CPAL_DMA_InitStructure.DMA_M2M = DMA_M2M_Disable; - CPAL_DMA_InitStructure.DMA_MemoryBaseAddr = 0; - CPAL_DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; - - /* If TX Direction (Transmission) selected */ - if ((Direction & CPAL_DIRECTION_TX) != 0) - { - /* Select I2Cx TXDR Address register as DMA PeripheralBaseAddress */ - CPAL_DMA_InitStructure.DMA_PeripheralBaseAddr = CPAL_I2C_TXDR [Device]; - - /* Select Memory to Peripheral transfer direction */ - CPAL_DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST; - - /* Initialize I2Cx DMA Tx Channel */ - DMA_Init((DMA_Channel_TypeDef*)CPAL_I2C_DMA_TX_Channel[Device], &CPAL_DMA_InitStructure); - } - - /* If RX Direction (Reception) selected */ - if ((Direction & CPAL_DIRECTION_RX ) != 0) - { - /* Select I2Cx RXDR Address register as DMA PeripheralBaseAddress */ - CPAL_DMA_InitStructure.DMA_PeripheralBaseAddr = CPAL_I2C_RXDR [Device]; - - /* Select Peripheral to Memory transfer direction */ - CPAL_DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC; - - /* Initialize I2Cx DMA Rx Channel */ - DMA_Init((DMA_Channel_TypeDef*)CPAL_I2C_DMA_RX_Channel[Device], &CPAL_DMA_InitStructure); - } -} - - -/** - * @brief Configure the DMA channel specific for TX transfer. - * @param Device : I2C Device instance. - * @param TXferStruct : DMA TX Transfer Parameters. - * @param Options : Transfer Options. - * @retval None. - */ -void CPAL_I2C_HAL_DMATXConfig(CPAL_DevTypeDef Device, CPAL_TransferTypeDef* TxXferStruct, uint32_t Options ) -{ - /* Set Memory Base Address */ - CPAL_DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)(TxXferStruct->pbBuffer); - - /* Set number of data */ - CPAL_DMA_InitStructure.DMA_BufferSize = TxXferStruct->wNumData; - - /* Select I2Cx TXDR Address register as DMA PeripheralBaseAddress */ - CPAL_DMA_InitStructure.DMA_PeripheralBaseAddr = CPAL_I2C_TXDR [Device]; - - /* If TX DMA Circular Mode Option Bit Selected */ - if ((Options & CPAL_OPT_DMATX_CIRCULAR) != 0) - { - /* Select DMA Circular Mode */ - CPAL_DMA_InitStructure.DMA_Mode = DMA_Mode_Circular; - } - /* If TX DMA Circular Mode Option Bit not selected */ - else - { - /* Select DMA Normal Mode */ - CPAL_DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; - } - - /* Select Peripheral to Memory transfer direction */ - CPAL_DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST; - - /* Initialize I2Cx DMA Tx Channel */ - DMA_Init((DMA_Channel_TypeDef*)CPAL_I2C_DMA_TX_Channel[Device], &CPAL_DMA_InitStructure); -} - - -/** - * @brief Configure the DMA channel specific for RX transfer. - * @param Device : I2C Device instance. - * @param RXferStruct : DMA RX Transfer Parameters. - * @param Options : Transfer Options. - * @retval None. - */ -void CPAL_I2C_HAL_DMARXConfig(CPAL_DevTypeDef Device, CPAL_TransferTypeDef* RxXferStruct, uint32_t Options ) -{ - /* Set Memory Base Address */ - CPAL_DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)(RxXferStruct->pbBuffer); - - /* Set number of data */ - CPAL_DMA_InitStructure.DMA_BufferSize = RxXferStruct->wNumData; - - /* Select I2Cx RXDR Address register as DMA PeripheralBaseAddress */ - CPAL_DMA_InitStructure.DMA_PeripheralBaseAddr = CPAL_I2C_RXDR [Device]; - - /* If RX DMA Circular Mode Option Bit Selected */ - if ((Options & CPAL_OPT_DMARX_CIRCULAR) != 0) - { - /* Select DMA Circular Mode */ - CPAL_DMA_InitStructure.DMA_Mode = DMA_Mode_Circular; - } - /* If RX DMA Circular Mode Option Bit not selected */ - else - { - /* Select DMA Normal Mode */ - CPAL_DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; - } - - /* Select Peripheral to Memory transfer direction */ - CPAL_DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC; - - /* Initialize I2Cx DMA Rx Channel */ - DMA_Init((DMA_Channel_TypeDef*)CPAL_I2C_DMA_RX_Channel[Device], &CPAL_DMA_InitStructure); -} - -/** - * @brief Deinitialize the DMA channel used by I2C Device(configured to their default state). - * DMA clock is not disabled. - * @param Device : I2C Device instance. - * @param Direction : Transfer direction. - * @retval None. - */ -void CPAL_I2C_HAL_DMADeInit(CPAL_DevTypeDef Device, CPAL_DirectionTypeDef Direction) -{ - /* If TX Direction (Transmission) selected */ - if ((Direction & CPAL_DIRECTION_TX) != 0) - { - /* Deinitialize I2Cx DMA Tx Channel */ - DMA_DeInit((DMA_Channel_TypeDef*)CPAL_I2C_DMA_TX_Channel[Device]); - } - - /* If RX Direction (Reception) selected */ - if ((Direction & CPAL_DIRECTION_RX) != 0) - { - /* Deinitialize I2Cx DMA Rx Channel */ - DMA_DeInit((DMA_Channel_TypeDef*)CPAL_I2C_DMA_RX_Channel[Device]); - } -} -#endif /* CPAL_I2C_DMA_PROGMODEL */ - - -/** - * @brief Configure NVIC and interrupts used by I2C Device according to - * enabled options - * @param Device : I2C Device instance. - * @param Options : I2C Transfer Options. - * @retval None. - */ -void CPAL_I2C_HAL_ITInit(CPAL_DevTypeDef Device, uint32_t Options) -{ - NVIC_InitTypeDef NVIC_InitStructure; - - /* Enable the IRQ channel */ - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - - /* Configure NVIC for I2Cx Interrupt */ - NVIC_InitStructure.NVIC_IRQChannel = CPAL_I2C_IT_IRQn [Device] ; - NVIC_InitStructure.NVIC_IRQChannelPriority = I2C_IT_PRIO[Device]; - NVIC_Init(&NVIC_InitStructure); - - /* If I2C ERR Interrupt Option Bit not selected */ - if ((Options & CPAL_OPT_I2C_ERRIT_DISABLE) == 0) - { - /* Enable I2C Error Interrupts */ - __CPAL_I2C_HAL_ENABLE_ERRIT(Device); - } - -#ifdef CPAL_I2C_DMA_PROGMODEL - /* If one or more DMA Interrupt option Bits selected */ - if (((Options & CPAL_OPT_I2C_DMA_TX_IT_MASK) != 0) || ((Options & CPAL_OPT_I2C_DMA_RX_IT_MASK) != 0)) - { - /* Configure NVIC for DMA TX channel interrupt */ - NVIC_InitStructure.NVIC_IRQChannel = CPAL_I2C_DMA_IRQn [Device]; - NVIC_InitStructure.NVIC_IRQChannelPriority = I2C_IT_DMA_PRIO[Device]; - NVIC_Init(&NVIC_InitStructure); - - /* If DMA TX TC interrupt Option Bits Selected */ - if ((Options & CPAL_OPT_DMATX_TCIT) != 0) - { - /* Enable DMA TX Channel TCIT */ - __I2C_HAL_ENABLE_DMATX_TCIT(Device); - } - - /* If DMA TX HT interrupt Option Bits Selected */ - if ((Options & CPAL_OPT_DMATX_HTIT) != 0) - { - /* Enable DMA TX Channel HTIT */ - __I2C_HAL_ENABLE_DMATX_HTIT(Device); - } - - /* If DMA TX TE interrupt Option Bits Selected */ - if ((Options & CPAL_OPT_DMATX_TEIT) != 0) - { - /* Enable DMA TX Channel TEIT */ - __I2C_HAL_ENABLE_DMATX_TEIT(Device); - } - - /* If DMA RX TC interrupt Option Bits Selected */ - if ((Options & CPAL_OPT_DMARX_TCIT) != 0) - { - /* Enable DMA RX Channel TCIT */ - __I2C_HAL_ENABLE_DMARX_TCIT(Device); - } - - /* If DMA RX HT interrupt Option Bits Selected */ - if ((Options & CPAL_OPT_DMARX_HTIT) != 0) - { - /* Enable DMA RX Channel HTIT */ - __I2C_HAL_ENABLE_DMARX_HTIT(Device); - } - - /* If DMA RX TE interrupt Option Bits Selected */ - if ((Options & CPAL_OPT_DMARX_TEIT) != 0) - { - /* Enable DMA RX Channel TEIT */ - __I2C_HAL_ENABLE_DMARX_TEIT(Device); - } - } -#endif /* CPAL_I2C_DMA_PROGMODEL */ -} - - -/** - * @brief Deinitialize NVIC and interrupts used by I2C Device in - * the current Configuration. - * @param Device : I2C Device instance. - * @param Options : I2C Transfer Options. - * @retval None. - */ -void CPAL_I2C_HAL_ITDeInit(CPAL_DevTypeDef Device, uint32_t Options ) -{ - NVIC_InitTypeDef NVIC_InitStructure; - - NVIC_InitStructure.NVIC_IRQChannelPriority = 0; - - /* Disable the IRQ channel */ - NVIC_InitStructure.NVIC_IRQChannelCmd = DISABLE; - - /* Disable I2Cx EVT IRQn */ - NVIC_InitStructure.NVIC_IRQChannel = CPAL_I2C_IT_IRQn [Device]; - NVIC_Init(&NVIC_InitStructure); - -#ifdef CPAL_I2C_DMA_PROGMODEL - /* If one or more DMA It option Bits selected */ - if (((Options & CPAL_OPT_I2C_DMA_TX_IT_MASK) != 0) || ((Options & CPAL_OPT_I2C_DMA_RX_IT_MASK) != 0)) - { - /* Disable I2Cx DMA TX IRQn */ - NVIC_InitStructure.NVIC_IRQChannel = CPAL_I2C_DMA_IRQn [Device]; - NVIC_Init(&NVIC_InitStructure); - } -#endif /* CPAL_I2C_DMA_PROGMODEL */ -} - - -/*================== CPAL_I2C1_IRQhandler ==================*/ - -#ifdef CPAL_USE_I2C1 - -/** - * @brief This function handles I2C1 interrupt request. - * @param None. - * @retval CPAL_PASS. - */ -uint32_t I2C1_IRQHandler(void) -{ - /* If interrupt sources is I2C event */ - if ((__CPAL_I2C_HAL_GET_ERROR(0) != 0) && ((I2C1_DevStructure.wCPAL_Options & CPAL_OPT_I2C_ERRIT_DISABLE) == 0)) - { - CPAL_LOG("\n\r\n\rLOG : I2C1 Device Error IT "); - - /* Call the Common Error handler function */ - return CPAL_I2C_ER_IRQHandler(&I2C1_DevStructure); - } - else - { - /* Call the Common Event handler function */ - return CPAL_I2C_EV_IRQHandler(&I2C1_DevStructure); - } -} - - #ifdef CPAL_I2C_DMA_PROGMODEL -/** - * @brief This function handles I2C1 DMA interrupt request. - * @param None. - * @retval CPAL_PASS. - */ -uint32_t CPAL_I2C1_DMA_IRQHandler(void) -{ - /* If interrupt source is DMA RX */ - if (__CPAL_I2C_HAL_GET_DMARX_IT(0) != 0) - { - /* Call the Common DMA RX handler function */ - return CPAL_I2C_DMA_RX_IRQHandler(&I2C1_DevStructure); - } - else - { - /* Call the Common DMA TX handler function */ - return CPAL_I2C_DMA_TX_IRQHandler(&I2C1_DevStructure); - } -} - #endif /* CPAL_I2C_DMA_PROGMODEL */ -#endif /* CPAL_USE_I2C1 */ - - -/*================== CPAL_I2C2_IRQhandler ==================*/ - -#ifdef CPAL_USE_I2C2 - -/** - * @brief This function handles I2C2 interrupt request. - * @param None. - * @retval CPAL_PASS. - */ -uint32_t I2C2_IRQHandler(void) -{ - /* If interrupt sources is I2C event */ - if ((__CPAL_I2C_HAL_GET_ERROR(1) != 0) && ((I2C2_DevStructure.wCPAL_Options & CPAL_OPT_I2C_ERRIT_DISABLE) == 0)) - { - CPAL_LOG("\n\r\n\rLOG : I2C2 Device Error IT "); - - /* Call the Common Error handler function */ - return CPAL_I2C_ER_IRQHandler(&I2C2_DevStructure); - } - else - { - /* Call the Common Event handler function */ - return CPAL_I2C_EV_IRQHandler(&I2C2_DevStructure); - } -} - - #ifdef CPAL_I2C_DMA_PROGMODEL -/** - * @brief This function handles I2C2 DMA interrupt request. - * @param None. - * @retval CPAL_PASS. - */ -uint32_t CPAL_I2C2_DMA_IRQHandler(void) -{ - /* If interrupt source is DMA RX */ - if (__CPAL_I2C_HAL_GET_DMARX_IT(1) != 0) - { - /* Call the Common DMA RX handler function */ - return CPAL_I2C_DMA_RX_IRQHandler(&I2C2_DevStructure); - } - else - { - /* Call the Common DMA TX handler function */ - return CPAL_I2C_DMA_TX_IRQHandler(&I2C2_DevStructure); - } -} - #endif /* CPAL_I2C_DMA_PROGMODEL */ -#endif /* CPAL_USE_I2C2 */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_CPAL_Driver/src/stm32f0xx_i2c_cpal_usercallback_template.c b/libraries/STM32F0xx_CPAL_Driver/src/stm32f0xx_i2c_cpal_usercallback_template.c deleted file mode 100644 --- a/libraries/STM32F0xx_CPAL_Driver/src/stm32f0xx_i2c_cpal_usercallback_template.c +++ /dev/null @@ -1,265 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_i2c_cpal_usercallback.c - * @author MCD Application Team - * @version V1.2.0 - * @date 24-July-2014 - * @brief This file provides all the CPAL UserCallback functions. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_i2c_cpal.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private defines -----------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/*------------------------------------------------------------------------------ - CPAL User Callbacks implementations -------------------------------------------------------------------------------*/ - - -/*=========== Timeout UserCallback ===========*/ - - -/** - * @brief User callback that manages the Timeout error - * @param pDevInitStruct - * @retval None. - */ -uint32_t CPAL_TIMEOUT_UserCallback(CPAL_InitTypeDef* pDevInitStruct) -{ - - return CPAL_PASS; -} - - -/*=========== Transfer UserCallback ===========*/ - - -/** - * @brief Manages the End of Tx transfer event - * @param pDevInitStruct - * @retval None - */ -/*void CPAL_I2C_TXTC_UserCallback(CPAL_InitTypeDef* pDevInitStruct) -{ - -}*/ - - -/** - * @brief Manages the End of Rx transfer event - * @param pDevInitStruct - * @retval None - */ -/*void CPAL_I2C_RXTC_UserCallback(CPAL_InitTypeDef* pDevInitStruct) -{ - -}*/ - - -/** - * @brief Manages Tx transfer event - * @param pDevInitStruct - * @retval None - */ -/*void CPAL_I2C_TX_UserCallback(CPAL_InitTypeDef* pDevInitStruct) -{ - -}*/ - - -/** - * @brief Manages Rx transfer event - * @param pDevInitStruct - * @retval None - */ -/*void CPAL_I2C_RX_UserCallback(CPAL_InitTypeDef* pDevInitStruct) -{ - -}*/ - - -/** - * @brief Manages the End of DMA Tx transfer event - * @param pDevInitStruct - * @retval None - */ -/*void CPAL_I2C_DMATXTC_UserCallback(CPAL_InitTypeDef* pDevInitStruct) -{ - -}*/ - - -/** - * @brief Manages the Half of DMA Tx transfer event - * @param pDevInitStruct - * @retval None - */ -/*void CPAL_I2C_DMATXHT_UserCallback(CPAL_InitTypeDef* pDevInitStruct) -{ - -}*/ - - -/** - * @brief Manages Error of DMA Tx transfer event - * @param pDevInitStruct - * @retval None - */ -/*void CPAL_I2C_DMATXTE_UserCallback(CPAL_InitTypeDef* pDevInitStruct) -{ - -}*/ - - -/** - * @brief Manages the End of DMA Rx transfer event - * @param pDevInitStruct - * @retval None - */ -/*void CPAL_I2C_DMARXTC_UserCallback(CPAL_InitTypeDef* pDevInitStruct) -{ - -}*/ - - -/** - * @brief Manages the Half of DMA Rx transfer event - * @param pDevInitStruct - * @retval None - */ -/*void CPAL_I2C_DMARXHT_UserCallback(CPAL_InitTypeDef* pDevInitStruct) -{ - -}*/ - - -/** - * @brief Manages Error of DMA Rx transfer event - * @param pDevInitStruct - * @retval None - */ -/*void CPAL_I2C_DMARXTE_UserCallback(CPAL_InitTypeDef* pDevInitStruct) -{ - -}*/ - - -/*=========== Error UserCallback ===========*/ - - -/** - * @brief User callback that manages the I2C device errors - * @note Make sure that the define USE_SINGLE_ERROR_CALLBACK is uncommented in - * the cpal_conf.h file, otherwise this callback will not be functional - * @param pDevInitStruct - * @param DeviceError - * @retval None - */ -/*void CPAL_I2C_ERR_UserCallback(CPAL_DevTypeDef pDevInstance, uint32_t DeviceError) -{ - -}*/ - - -/** - * @brief User callback that manages BERR I2C device errors - * @note Make sure that the define USE_MULTIPLE_ERROR_CALLBACK is uncommented in - * the cpal_conf.h file, otherwise this callback will not be functional - * @param pDevInstance - * @retval None - */ -/*void CPAL_I2C_BERR_UserCallback(CPAL_DevTypeDef pDevInstance) -{ - -}*/ - - -/** - * @brief User callback that manages ARLO I2C device errors - * @note Make sure that the define USE_MULTIPLE_ERROR_CALLBACK is uncommented in - * the cpal_conf.h file, otherwise this callback will not be functional - * @param pDevInstance - * @retval None - */ -/*void CPAL_I2C_ARLO_UserCallback(CPAL_DevTypeDef pDevInstance) -{ - -}*/ - - -/** - * @brief User callback that manages OVR I2C device errors - * @note Make sure that the define USE_MULTIPLE_ERROR_CALLBACK is uncommented in - * the cpal_conf.h file, otherwise this callback will not be functional - * @param pDevInstance - * @retval None - */ -/*void CPAL_I2C_OVR_UserCallback(CPAL_DevTypeDef pDevInstance) -{ - -}*/ - - -/** - * @brief User callback that manages AF I2C device errors. - * @note Make sure that the define USE_MULTIPLE_ERROR_CALLBACK is uncommented in - * the cpal_conf.h file, otherwise this callback will not be functional - * @param pDevInstance - * @retval None - */ -/*void CPAL_I2C_AF_UserCallback(CPAL_DevTypeDef pDevInstance) -{ - -}*/ - - -/*=========== Addressing Mode UserCallback ===========*/ - - -/** - * @brief User callback that manage General Call Addressing mode - * @param pDevInitStruct - * @retval None - */ -/*void CPAL_I2C_GENCALL_UserCallback(CPAL_InitTypeDef* pDevInitStruct) -{ - -}*/ - - -/** - * @brief User callback that manage Dual Address Addressing mode - * @param pDevInitStruct - * @retval None - */ -/*void CPAL_I2C_DUALF_UserCallback(CPAL_InitTypeDef* pDevInitStruct) -{ - -}*/ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h @@ -0,0 +1,698 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief This file contains all the functions prototypes for the HAL + * module driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_H +#define __STM32F0xx_HAL_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_conf.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup HAL + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup HAL_Exported_Constants HAL Exported Constants + * @{ + */ + +#if defined(SYSCFG_CFGR1_DMA_RMP) +/** @defgroup HAL_DMA_remapping HAL DMA remapping + * Elements values convention: 0xYYYYYYYY + * - YYYYYYYY : Position in the SYSCFG register CFGR1 + * @{ + */ +#define HAL_REMAPDMA_ADC_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_ADC_DMA_RMP) /*!< ADC DMA remap + 0: No remap (ADC DMA requests mapped on DMA channel 1 + 1: Remap (ADC DMA requests mapped on DMA channel 2 */ +#define HAL_REMAPDMA_USART1_TX_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_USART1TX_DMA_RMP) /*!< USART1 TX DMA remap + 0: No remap (USART1_TX DMA request mapped on DMA channel 2 + 1: Remap (USART1_TX DMA request mapped on DMA channel 4 */ +#define HAL_REMAPDMA_USART1_RX_DMA_CH5 ((uint32_t)SYSCFG_CFGR1_USART1RX_DMA_RMP) /*!< USART1 RX DMA remap + 0: No remap (USART1_RX DMA request mapped on DMA channel 3 + 1: Remap (USART1_RX DMA request mapped on DMA channel 5 */ +#define HAL_REMAPDMA_TIM16_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16 DMA request remap + 0: No remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3) + 1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4) */ +#define HAL_REMAPDMA_TIM17_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17 DMA request remap + 0: No remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 + 1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2) */ + +#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) +#define HAL_REMAPDMA_TIM16_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP2) /*!< TIM16 alternate DMA request remapping bit. Available on STM32F07x devices only + 0: No alternate remap (TIM16 DMA requestsmapped according to TIM16_DMA_RMP bit) + 1: Alternate remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 6) */ +#define HAL_REMAPDMA_TIM17_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP2) /*!< TIM17 alternate DMA request remapping bit. Available on STM32F07x devices only + 0: No alternate remap (TIM17 DMA requestsmapped according to TIM17_DMA_RMP bit) + 1: Alternate remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 7) */ +#define HAL_REMAPDMA_SPI2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_SPI2_DMA_RMP) /*!< SPI2 DMA request remapping bit. Available on STM32F07x devices only. + 0: No remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively) + 1: 1: Remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */ +#define HAL_REMAPDMA_USART2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_USART2_DMA_RMP) /*!< USART2 DMA request remapping bit. Available on STM32F07x devices only. + 0: No remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively) + 1: 1: Remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */ +#define HAL_REMAPDMA_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F07x devices only. + 0: No remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively) + 1: 1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */ +#define HAL_REMAPDMA_I2C1_DMA_CH76 ((uint32_t)SYSCFG_CFGR1_I2C1_DMA_RMP) /*!< I2C1 DMA request remapping bit. Available on STM32F07x devices only. + 0: No remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively) + 1: Remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively) */ +#define HAL_REMAPDMA_TIM1_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM1_DMA_RMP) /*!< TIM1 DMA request remapping bit. Available on STM32F07x devices only. + 0: No remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively) + 1: Remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 */ +#define HAL_REMAPDMA_TIM2_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM2_DMA_RMP) /*!< TIM2 DMA request remapping bit. Available on STM32F07x devices only. + 0: No remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively) + 1: Remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 */ +#define HAL_REMAPDMA_TIM3_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM3_DMA_RMP) /*!< TIM3 DMA request remapping bit. Available on STM32F07x devices only. + 0: No remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4) + 1: Remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6) */ +#endif + +#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) +#define IS_HAL_REMAPDMA(RMP) (((RMP) == HAL_REMAPDMA_ADC_DMA_CH2) || \ + ((RMP) == HAL_REMAPDMA_USART1_TX_DMA_CH4) || \ + ((RMP) == HAL_REMAPDMA_USART1_RX_DMA_CH5) || \ + ((RMP) == HAL_REMAPDMA_TIM16_DMA_CH4) || \ + ((RMP) == HAL_REMAPDMA_TIM17_DMA_CH2) || \ + ((RMP) == HAL_REMAPDMA_TIM16_DMA_CH6) || \ + ((RMP) == HAL_REMAPDMA_TIM17_DMA_CH7) || \ + ((RMP) == HAL_REMAPDMA_SPI2_DMA_CH67) || \ + ((RMP) == HAL_REMAPDMA_USART2_DMA_CH67) || \ + ((RMP) == HAL_REMAPDMA_USART3_DMA_CH32) || \ + ((RMP) == HAL_REMAPDMA_I2C1_DMA_CH76) || \ + ((RMP) == HAL_REMAPDMA_TIM1_DMA_CH6) || \ + ((RMP) == HAL_REMAPDMA_TIM2_DMA_CH7) || \ + ((RMP) == HAL_REMAPDMA_TIM3_DMA_CH6)) +#else +#define IS_HAL_REMAPDMA(RMP) (((RMP) == HAL_REMAPDMA_ADC_DMA_CH2) || \ + ((RMP) == HAL_REMAPDMA_USART1_TX_DMA_CH4) || \ + ((RMP) == HAL_REMAPDMA_USART1_RX_DMA_CH5) || \ + ((RMP) == HAL_REMAPDMA_TIM16_DMA_CH4) || \ + ((RMP) == HAL_REMAPDMA_TIM17_DMA_CH2)) +#endif +/** + * @} + */ +#endif /* SYSCFG_CFGR1_DMA_RMP */ + +#if defined(SYSCFG_CFGR1_PA11_PA12_RMP) +/** @defgroup HAL_Pin_remapping HAL Pin remapping + * @{ + */ +#define HAL_REMAP_PA11_PA12 (SYSCFG_CFGR1_PA11_PA12_RMP) /*!< PA11 and PA12 remapping bit for small packages (28 and 20 pins). + 0: No remap (pin pair PA9/10 mapped on the pins) + 1: Remap (pin pair PA11/12 mapped instead of PA9/10) */ + +#define IS_HAL_REMAP_PIN(RMP) ((RMP) == HAL_REMAP_PA11_PA12) +/** + * @} + */ +#endif /* SYSCFG_CFGR1_PA11_PA12_RMP */ + +#if defined(STM32F091xC) +/** @defgroup HAL_IRDA_ENV_SEL HAL IRDA Enveloppe Selection + * @{ + */ +#define HAL_SYSCFG_IRDA_ENV_SEL_TIM16 (SYSCFG_CFGR1_IRDA_ENV_SEL_0 & SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* 00: Timer16 is selected as IRDA Modulation enveloppe source */ +#define HAL_SYSCFG_IRDA_ENV_SEL_USART1 (SYSCFG_CFGR1_IRDA_ENV_SEL_0) /* 01: USART1 is selected as IRDA Modulation enveloppe source */ +#define HAL_SYSCFG_IRDA_ENV_SEL_USART4 (SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* 10: USART4 is selected as IRDA Modulation enveloppe source */ + +#define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16) || \ + ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1) || \ + ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART4)) +/** + * @} + */ +#endif /* STM32F091xC */ + + +/** @defgroup HAL_FastModePlus_I2C HAL FastModePlus I2C + * @{ + */ +#if defined(SYSCFG_CFGR1_I2C_FMP_PB6) +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 (SYSCFG_CFGR1_I2C_FMP_PB6) /*!< Fast Mode Plus (FM+) driving capability activation on the pad + 0: PB6 pin operates in standard mode + 1: I2C FM+ mode enabled on PB6 pin, and the Speed control is bypassed */ +#endif /* SYSCFG_CFGR1_I2C_FMP_PB6 */ + +#if defined(SYSCFG_CFGR1_I2C_FMP_PB7) +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 (SYSCFG_CFGR1_I2C_FMP_PB7) /*!< Fast Mode Plus (FM+) driving capability activation on the pad + 0: PB7 pin operates in standard mode + 1: I2C FM+ mode enabled on PB7 pin, and the Speed control is bypassed */ +#endif /* SYSCFG_CFGR1_I2C_FMP_PB7 */ + +#if defined(SYSCFG_CFGR1_I2C_FMP_PB8) +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 (SYSCFG_CFGR1_I2C_FMP_PB8) /*!< Fast Mode Plus (FM+) driving capability activation on the pad + 0: PB8 pin operates in standard mode + 1: I2C FM+ mode enabled on PB8 pin, and the Speed control is bypassed */ +#endif /* SYSCFG_CFGR1_I2C_FMP_PB8 */ + +#if defined(SYSCFG_CFGR1_I2C_FMP_PB9) +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 (SYSCFG_CFGR1_I2C_FMP_PB9) /*!< Fast Mode Plus (FM+) driving capability activation on the pad + 0: PB9 pin operates in standard mode + 1: I2C FM+ mode enabled on PB9 pin, and the Speed control is bypassed */ +#endif /* SYSCFG_CFGR1_I2C_FMP_PB9 */ + +#if defined(SYSCFG_CFGR1_I2C_FMP_I2C1) +#define HAL_SYSCFG_FASTMODEPLUS_I2C1 (SYSCFG_CFGR1_I2C_FMP_I2C1) /*!< I2C1 fast mode Plus driving capability activation + 0: FM+ mode is not enabled on I2C1 pins selected through AF selection bits + 1: FM+ mode is enabled on I2C1 pins selected through AF selection bits */ +#endif /* SYSCFG_CFGR1_I2C_FMP_I2C1 */ + +#if defined(SYSCFG_CFGR1_I2C_FMP_I2C2) +#define HAL_SYSCFG_FASTMODEPLUS_I2C2 (SYSCFG_CFGR1_I2C_FMP_I2C2) /*!< I2C2 fast mode Plus driving capability activation + 0: FM+ mode is not enabled on I2C2 pins selected through AF selection bits + 1: FM+ mode is enabled on I2C2 pins selected through AF selection bits */ +#endif /* SYSCFG_CFGR1_I2C_FMP_I2C2 */ + +#if defined(SYSCFG_CFGR1_I2C_FMP_PA9) +#define HAL_SYSCFG_FASTMODEPLUS_I2C2_PA9 (SYSCFG_CFGR1_I2C_FMP_PA9) /*!< Fast Mode Plus (FM+) driving capability activation on the pad + 0: PA9 pin operates in standard mode + 1: FM+ mode is enabled on PA9 pin, and the Speed control is bypassed */ +#endif /* SYSCFG_CFGR1_I2C_FMP_PA9 */ + +#if defined(SYSCFG_CFGR1_I2C_FMP_PA10) +#define HAL_SYSCFG_FASTMODEPLUS_I2C2_PA10 (SYSCFG_CFGR1_I2C_FMP_PA10) /*!< Fast Mode Plus (FM+) driving capability activation on the pad + 0: PA10 pin operates in standard mode + 1: FM+ mode is enabled on PA10 pin, and the Speed control is bypassed */ +#endif /* SYSCFG_CFGR1_I2C_FMP_PA10 */ + +#if defined(STM32F091xC)|| defined(STM32F098xx) +#define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) (((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C1) || \ + ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C2) || \ + ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C2_PA9) || \ + ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C2_PA10) || \ + ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) || \ + ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) || \ + ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) || \ + ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9)) +#elif defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) +#define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) (((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C1) || \ + ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C2) || \ + ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) || \ + ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) || \ + ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) || \ + ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9)) +#elif defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) +#define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) (((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C1) || \ + ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C2_PA9) || \ + ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C2_PA10) || \ + ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) || \ + ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) || \ + ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) || \ + ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9)) +#elif defined(STM32F042x6) || defined(STM32F048xx) +#define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) (((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C1) || \ + ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) || \ + ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) || \ + ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) || \ + ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9)) +#else +#define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) (((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) || \ + ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) || \ + ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) || \ + ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9)) +#endif + +/** + * @} + */ + +#if defined(STM32F091xC) || defined (STM32F098xx) +/** @defgroup HAL_ISR_Wrapper HAL ISR Wrapper + * @{ + */ +#define HAL_SYSCFG_ITLINE0 ((uint32_t) 0x00000000) +#define HAL_SYSCFG_ITLINE1 ((uint32_t) 0x00000001) +#define HAL_SYSCFG_ITLINE2 ((uint32_t) 0x00000002) +#define HAL_SYSCFG_ITLINE3 ((uint32_t) 0x00000003) +#define HAL_SYSCFG_ITLINE4 ((uint32_t) 0x00000004) +#define HAL_SYSCFG_ITLINE5 ((uint32_t) 0x00000005) +#define HAL_SYSCFG_ITLINE6 ((uint32_t) 0x00000006) +#define HAL_SYSCFG_ITLINE7 ((uint32_t) 0x00000007) +#define HAL_SYSCFG_ITLINE8 ((uint32_t) 0x00000008) +#define HAL_SYSCFG_ITLINE9 ((uint32_t) 0x00000009) +#define HAL_SYSCFG_ITLINE10 ((uint32_t) 0x0000000A) +#define HAL_SYSCFG_ITLINE11 ((uint32_t) 0x0000000B) +#define HAL_SYSCFG_ITLINE12 ((uint32_t) 0x0000000C) +#define HAL_SYSCFG_ITLINE13 ((uint32_t) 0x0000000D) +#define HAL_SYSCFG_ITLINE14 ((uint32_t) 0x0000000E) +#define HAL_SYSCFG_ITLINE15 ((uint32_t) 0x0000000F) +#define HAL_SYSCFG_ITLINE16 ((uint32_t) 0x00000010) +#define HAL_SYSCFG_ITLINE17 ((uint32_t) 0x00000011) +#define HAL_SYSCFG_ITLINE18 ((uint32_t) 0x00000012) +#define HAL_SYSCFG_ITLINE19 ((uint32_t) 0x00000013) +#define HAL_SYSCFG_ITLINE20 ((uint32_t) 0x00000014) +#define HAL_SYSCFG_ITLINE21 ((uint32_t) 0x00000015) +#define HAL_SYSCFG_ITLINE22 ((uint32_t) 0x00000016) +#define HAL_SYSCFG_ITLINE23 ((uint32_t) 0x00000017) +#define HAL_SYSCFG_ITLINE24 ((uint32_t) 0x00000018) +#define HAL_SYSCFG_ITLINE25 ((uint32_t) 0x00000019) +#define HAL_SYSCFG_ITLINE26 ((uint32_t) 0x0000001A) +#define HAL_SYSCFG_ITLINE27 ((uint32_t) 0x0000001B) +#define HAL_SYSCFG_ITLINE28 ((uint32_t) 0x0000001C) +#define HAL_SYSCFG_ITLINE29 ((uint32_t) 0x0000001D) +#define HAL_SYSCFG_ITLINE30 ((uint32_t) 0x0000001E) +#define HAL_SYSCFG_ITLINE31 ((uint32_t) 0x0000001F) + +#define HAL_ITLINE_EWDG ((uint32_t) ((HAL_SYSCFG_ITLINE0 << 0x18) | SYSCFG_ITLINE0_SR_EWDG)) /* EWDG has expired .... */ +#if defined(STM32F091xC) +#define HAL_ITLINE_PVDOUT ((uint32_t) ((HAL_SYSCFG_ITLINE1 << 0x18) | SYSCFG_ITLINE1_SR_PVDOUT)) /* Power voltage detection Interrupt .... */ +#endif +#define HAL_ITLINE_VDDIO2 ((uint32_t) ((HAL_SYSCFG_ITLINE1 << 0x18) | SYSCFG_ITLINE1_SR_VDDIO2)) /* VDDIO2 Interrupt .... */ +#define HAL_ITLINE_RTC_WAKEUP ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18) | SYSCFG_ITLINE2_SR_RTC_WAKEUP)) /* RTC WAKEUP -> exti[20] Interrupt */ +#define HAL_ITLINE_RTC_TSTAMP ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18) | SYSCFG_ITLINE2_SR_RTC_TSTAMP)) /* RTC Time Stamp -> exti[19] interrupt */ +#define HAL_ITLINE_RTC_ALRA ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18) | SYSCFG_ITLINE2_SR_RTC_ALRA)) /* RTC Alarm -> exti[17] interrupt .... */ +#define HAL_ITLINE_FLASH_ITF ((uint32_t) ((HAL_SYSCFG_ITLINE3 << 0x18) | SYSCFG_ITLINE3_SR_FLASH_ITF)) /* Flash ITF Interrupt */ +#define HAL_ITLINE_CRS ((uint32_t) ((HAL_SYSCFG_ITLINE4 << 0x18) | SYSCFG_ITLINE4_SR_CRS)) /* CRS Interrupt */ +#define HAL_ITLINE_CLK_CTRL ((uint32_t) ((HAL_SYSCFG_ITLINE4 << 0x18) | SYSCFG_ITLINE4_SR_CLK_CTRL)) /* CLK Control Interrupt */ +#define HAL_ITLINE_EXTI0 ((uint32_t) ((HAL_SYSCFG_ITLINE5 << 0x18) | SYSCFG_ITLINE5_SR_EXTI0)) /* External Interrupt 0 */ +#define HAL_ITLINE_EXTI1 ((uint32_t) ((HAL_SYSCFG_ITLINE5 << 0x18) | SYSCFG_ITLINE5_SR_EXTI1)) /* External Interrupt 1 */ +#define HAL_ITLINE_EXTI2 ((uint32_t) ((HAL_SYSCFG_ITLINE6 << 0x18) | SYSCFG_ITLINE6_SR_EXTI2)) /* External Interrupt 2 */ +#define HAL_ITLINE_EXTI3 ((uint32_t) ((HAL_SYSCFG_ITLINE6 << 0x18) | SYSCFG_ITLINE6_SR_EXTI3)) /* External Interrupt 3 */ +#define HAL_ITLINE_EXTI4 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI4)) /* EXTI4 Interrupt */ +#define HAL_ITLINE_EXTI5 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI5)) /* EXTI5 Interrupt */ +#define HAL_ITLINE_EXTI6 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI6)) /* EXTI6 Interrupt */ +#define HAL_ITLINE_EXTI7 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI7)) /* EXTI7 Interrupt */ +#define HAL_ITLINE_EXTI8 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI8)) /* EXTI8 Interrupt */ +#define HAL_ITLINE_EXTI9 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI9)) /* EXTI9 Interrupt */ +#define HAL_ITLINE_EXTI10 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI10)) /* EXTI10 Interrupt */ +#define HAL_ITLINE_EXTI11 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI11)) /* EXTI11 Interrupt */ +#define HAL_ITLINE_EXTI12 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI12)) /* EXTI12 Interrupt */ +#define HAL_ITLINE_EXTI13 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI13)) /* EXTI13 Interrupt */ +#define HAL_ITLINE_EXTI14 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI14)) /* EXTI14 Interrupt */ +#define HAL_ITLINE_EXTI15 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI15)) /* EXTI15 Interrupt */ +#define HAL_ITLINE_TSC_EOA ((uint32_t) ((HAL_SYSCFG_ITLINE8 << 0x18) | SYSCFG_ITLINE8_SR_TSC_EOA)) /* Touch control EOA Interrupt */ +#define HAL_ITLINE_TSC_MCE ((uint32_t) ((HAL_SYSCFG_ITLINE8 << 0x18) | SYSCFG_ITLINE8_SR_TSC_MCE)) /* Touch control MCE Interrupt */ +#define HAL_ITLINE_DMA1_CH1 ((uint32_t) ((HAL_SYSCFG_ITLINE9 << 0x18) | SYSCFG_ITLINE9_SR_DMA1_CH1)) /* DMA1 Channel 1 Interrupt */ +#define HAL_ITLINE_DMA1_CH2 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18) | SYSCFG_ITLINE10_SR_DMA1_CH2)) /* DMA1 Channel 2 Interrupt */ +#define HAL_ITLINE_DMA1_CH3 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18) | SYSCFG_ITLINE10_SR_DMA1_CH3)) /* DMA1 Channel 3 Interrupt */ +#define HAL_ITLINE_DMA2_CH1 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18) | SYSCFG_ITLINE10_SR_DMA2_CH1)) /* DMA2 Channel 1 Interrupt */ +#define HAL_ITLINE_DMA2_CH2 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18) | SYSCFG_ITLINE10_SR_DMA2_CH2)) /* DMA2 Channel 2 Interrupt */ +#define HAL_ITLINE_DMA1_CH4 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA1_CH4)) /* DMA1 Channel 4 Interrupt */ +#define HAL_ITLINE_DMA1_CH5 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA1_CH5)) /* DMA1 Channel 5 Interrupt */ +#define HAL_ITLINE_DMA1_CH6 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA1_CH6)) /* DMA1 Channel 6 Interrupt */ +#define HAL_ITLINE_DMA1_CH7 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA1_CH7)) /* DMA1 Channel 7 Interrupt */ +#define HAL_ITLINE_DMA2_CH3 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA2_CH3)) /* DMA2 Channel 3 Interrupt */ +#define HAL_ITLINE_DMA2_CH4 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA2_CH4)) /* DMA2 Channel 4 Interrupt */ +#define HAL_ITLINE_DMA2_CH5 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA2_CH5)) /* DMA2 Channel 5 Interrupt */ +#define HAL_ITLINE_ADC ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18) | SYSCFG_ITLINE12_SR_ADC)) /* ADC Interrupt */ +#define HAL_ITLINE_COMP1 ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18) | SYSCFG_ITLINE12_SR_COMP1)) /* COMP1 Interrupt -> exti[21] */ +#define HAL_ITLINE_COMP2 ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18) | SYSCFG_ITLINE12_SR_COMP2)) /* COMP2 Interrupt -> exti[21] */ +#define HAL_ITLINE_TIM1_BRK ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18) | SYSCFG_ITLINE13_SR_TIM1_BRK)) /* TIM1 BRK Interrupt */ +#define HAL_ITLINE_TIM1_UPD ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18) | SYSCFG_ITLINE13_SR_TIM1_UPD)) /* TIM1 UPD Interrupt */ +#define HAL_ITLINE_TIM1_TRG ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18) | SYSCFG_ITLINE13_SR_TIM1_TRG)) /* TIM1 TRG Interrupt */ +#define HAL_ITLINE_TIM1_CCU ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18) | SYSCFG_ITLINE13_SR_TIM1_CCU)) /* TIM1 CCU Interrupt */ +#define HAL_ITLINE_TIM1_CC ((uint32_t) ((HAL_SYSCFG_ITLINE14 << 0x18) | SYSCFG_ITLINE14_SR_TIM1_CC)) /* TIM1 CC Interrupt */ +#define HAL_ITLINE_TIM2 ((uint32_t) ((HAL_SYSCFG_ITLINE15 << 0x18) | SYSCFG_ITLINE15_SR_TIM2_GLB)) /* TIM2 Interrupt */ +#define HAL_ITLINE_TIM3 ((uint32_t) ((HAL_SYSCFG_ITLINE16 << 0x18) | SYSCFG_ITLINE16_SR_TIM3_GLB)) /* TIM3 Interrupt */ +#define HAL_ITLINE_DAC ((uint32_t) ((HAL_SYSCFG_ITLINE17 << 0x18) | SYSCFG_ITLINE17_SR_DAC)) /* DAC Interrupt */ +#define HAL_ITLINE_TIM6 ((uint32_t) ((HAL_SYSCFG_ITLINE17 << 0x18) | SYSCFG_ITLINE17_SR_TIM6_GLB)) /* TIM6 Interrupt */ +#define HAL_ITLINE_TIM7 ((uint32_t) ((HAL_SYSCFG_ITLINE18 << 0x18) | SYSCFG_ITLINE18_SR_TIM7_GLB)) /* TIM7 Interrupt */ +#define HAL_ITLINE_TIM14 ((uint32_t) ((HAL_SYSCFG_ITLINE19 << 0x18) | SYSCFG_ITLINE19_SR_TIM14_GLB)) /* TIM14 Interrupt */ +#define HAL_ITLINE_TIM15 ((uint32_t) ((HAL_SYSCFG_ITLINE20 << 0x18) | SYSCFG_ITLINE20_SR_TIM15_GLB)) /* TIM15 Interrupt */ +#define HAL_ITLINE_TIM16 ((uint32_t) ((HAL_SYSCFG_ITLINE21 << 0x18) | SYSCFG_ITLINE21_SR_TIM16_GLB)) /* TIM16 Interrupt */ +#define HAL_ITLINE_TIM17 ((uint32_t) ((HAL_SYSCFG_ITLINE22 << 0x18) | SYSCFG_ITLINE22_SR_TIM17_GLB)) /* TIM17 Interrupt */ +#define HAL_ITLINE_I2C1 ((uint32_t) ((HAL_SYSCFG_ITLINE23 << 0x18) | SYSCFG_ITLINE23_SR_I2C1_GLB)) /* I2C1 Interrupt -> exti[23] */ +#define HAL_ITLINE_I2C2 ((uint32_t) ((HAL_SYSCFG_ITLINE24 << 0x18) | SYSCFG_ITLINE24_SR_I2C2_GLB)) /* I2C2 Interrupt */ +#define HAL_ITLINE_SPI1 ((uint32_t) ((HAL_SYSCFG_ITLINE25 << 0x18) | SYSCFG_ITLINE25_SR_SPI1)) /* I2C1 Interrupt -> exti[23] */ +#define HAL_ITLINE_SPI2 ((uint32_t) ((HAL_SYSCFG_ITLINE26 << 0x18) | SYSCFG_ITLINE26_SR_SPI2)) /* SPI1 Interrupt */ +#define HAL_ITLINE_USART1 ((uint32_t) ((HAL_SYSCFG_ITLINE27 << 0x18) | SYSCFG_ITLINE27_SR_USART1_GLB)) /*!< USART1 GLB Interrupt -> exti[25] */ +#define HAL_ITLINE_USART2 ((uint32_t) ((HAL_SYSCFG_ITLINE28 << 0x18) | SYSCFG_ITLINE28_SR_USART2_GLB)) /*!< USART2 GLB Interrupt -> exti[26] */ +#define HAL_ITLINE_USART3 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART3_GLB)) /* USART3 Interrupt .... */ +#define HAL_ITLINE_USART4 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART4_GLB)) /* USART4 Interrupt .... */ +#define HAL_ITLINE_USART5 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART5_GLB)) /* USART5 Interrupt .... */ +#define HAL_ITLINE_USART6 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART6_GLB)) /* USART6 Interrupt .... */ +#define HAL_ITLINE_USART7 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART7_GLB)) /* USART7 Interrupt .... */ +#define HAL_ITLINE_USART8 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART8_GLB)) /* USART8 Interrupt .... */ +#define HAL_ITLINE_CAN ((uint32_t) ((HAL_SYSCFG_ITLINE30 << 0x18) | SYSCFG_ITLINE30_SR_CAN)) /* CAN Interrupt */ +#define HAL_ITLINE_CEC ((uint32_t) ((HAL_SYSCFG_ITLINE30 << 0x18) | SYSCFG_ITLINE30_SR_CEC)) /* CEC Interrupt -> exti[27] */ +/** + * @} + */ +#endif /* STM32F091xC || STM32F098xx */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup HAL_Exported_Macros HAL Exported Macros + * @{ + */ + +/** @defgroup HAL_Freeze_Unfreeze_Peripherals HAL Freeze Unfreeze Peripherals + * @brief Freeze/Unfreeze Peripherals in Debug mode + * @{ + */ + +#if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP) +#define __HAL_FREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN_STOP)) +#define __HAL_UNFREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN_STOP)) +#endif /* DBGMCU_APB1_FZ_DBG_CAN_STOP */ + +#if defined(DBGMCU_APB1_FZ_DBG_RTC_STOP) +#define __HAL_FREEZE_RTC_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP)) +#define __HAL_UNFREEZE_RTC_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP)) +#endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */ + +#if defined(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT) +#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) +#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) +#endif /* DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT */ + +#if defined(DBGMCU_APB1_FZ_DBG_IWDG_STOP) +#define __HAL_FREEZE_IWDG_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP)) +#define __HAL_UNFREEZE_IWDG_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP)) +#endif /* DBGMCU_APB1_FZ_DBG_IWDG_STOP */ + +#if defined(DBGMCU_APB1_FZ_DBG_WWDG_STOP) +#define __HAL_FREEZE_WWDG_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP)) +#define __HAL_UNFREEZE_WWDG_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP)) +#endif /* DBGMCU_APB1_FZ_DBG_WWDG_STOP */ + +#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP) +#define __HAL_FREEZE_TIM2_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP)) +#define __HAL_UNFREEZE_TIM2_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP)) +#endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */ + +#if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP) +#define __HAL_FREEZE_TIM3_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP)) +#define __HAL_UNFREEZE_TIM3_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP)) +#endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */ + +#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP) +#define __HAL_FREEZE_TIM6_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP)) +#define __HAL_UNFREEZE_TIM6_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP)) +#endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */ + +#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP) +#define __HAL_FREEZE_TIM7_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP)) +#define __HAL_UNFREEZE_TIM7_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP)) +#endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */ + +#if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP) +#define __HAL_FREEZE_TIM14_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP)) +#define __HAL_UNFREEZE_TIM14_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP)) +#endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */ + +#if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP) +#define __HAL_FREEZE_TIM1_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP)) +#define __HAL_UNFREEZE_TIM1_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP)) +#endif /* DBGMCU_APB2_FZ_DBG_TIM1_STOP */ + +#if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP) +#define __HAL_FREEZE_TIM15_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP)) +#define __HAL_UNFREEZE_TIM15_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP)) +#endif /* DBGMCU_APB2_FZ_DBG_TIM15_STOP */ + +#if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP) +#define __HAL_FREEZE_TIM16_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP)) +#define __HAL_UNFREEZE_TIM16_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP)) +#endif /* DBGMCU_APB2_FZ_DBG_TIM16_STOP */ + +#if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP) +#define __HAL_FREEZE_TIM17_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP)) +#define __HAL_UNFREEZE_TIM17_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP)) +#endif /* DBGMCU_APB2_FZ_DBG_TIM17_STOP */ + +/** + * @} + */ + +/** @defgroup Memory_Mapping_Selection Memory Mapping Selection + * @{ + */ +#if defined(SYSCFG_CFGR1_MEM_MODE) +/** @brief Main Flash memory mapped at 0x00000000 + */ +#define __HAL_REMAPMEMORY_FLASH() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE)) +#endif /* SYSCFG_CFGR1_MEM_MODE */ + +#if defined(SYSCFG_CFGR1_MEM_MODE_0) +/** @brief System Flash memory mapped at 0x00000000 + */ +#define __HAL_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \ + SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0; \ + }while(0) +#endif /* SYSCFG_CFGR1_MEM_MODE_0 */ + +#if defined(SYSCFG_CFGR1_MEM_MODE_0) && defined(SYSCFG_CFGR1_MEM_MODE_1) +/** @brief Embedded SRAM mapped at 0x00000000 + */ +#define __HAL_REMAPMEMORY_SRAM() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \ + SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \ + }while(0) +#endif /* SYSCFG_CFGR1_MEM_MODE_0 && SYSCFG_CFGR1_MEM_MODE_1 */ +/** + * @} + */ + +#if defined(SYSCFG_CFGR1_DMA_RMP) +/** @defgroup HAL_DMA_remap HAL DMA remap + * @brief DMA remapping enable/disable macros + * @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_remapping + * @{ + */ +#define __HAL_REMAPDMA_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_HAL_REMAPDMA((__DMA_REMAP__))); \ + SYSCFG->CFGR1 |= (__DMA_REMAP__); \ + }while(0) +#define __HAL_REMAPDMA_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_HAL_REMAPDMA((__DMA_REMAP__))); \ + SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \ + }while(0) +/** + * @} + */ +#endif /* SYSCFG_CFGR1_DMA_RMP */ + +#if defined(SYSCFG_CFGR1_PA11_PA12_RMP) +/** @defgroup HAL_Pin_remap HAL Pin remap + * @brief Pin remapping enable/disable macros + * @param __PIN_REMAP__: This parameter can be a value of @ref HAL_Pin_remapping + * @{ + */ +#define __HAL_REMAP_PIN_ENABLE(__PIN_REMAP__) do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__))); \ + SYSCFG->CFGR1 |= (__PIN_REMAP__); \ + }while(0) +#define __HAL_REMAP_PIN_DISABLE(__PIN_REMAP__) do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__))); \ + SYSCFG->CFGR1 &= ~(__PIN_REMAP__); \ + }while(0) +/** + * @} + */ +#endif /* SYSCFG_CFGR1_PA11_PA12_RMP */ + +/** @defgroup HAL_Fast_mode_plus_driving_cap HAL Fast mode plus driving cap + * @brief Fast mode Plus driving capability enable/disable macros + * @param __FASTMODEPLUS__: This parameter can be a value of @ref HAL_FastModePlus_I2C + * @{ + */ +#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG((__FASTMODEPLUS__))); \ + SYSCFG->CFGR1 |= (__FASTMODEPLUS__); \ + }while(0) + +#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG((__FASTMODEPLUS__))); \ + SYSCFG->CFGR1 &= ~(__FASTMODEPLUS__); \ + }while(0) +/** + * @} + */ + +#if defined(SYSCFG_CFGR2_LOCKUP_LOCK) +/** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable + * @{ + */ +/** @brief SYSCFG Break Lockup lock + * Enables and locks the connection of Cortex-M0 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input + * @note The selected configuration is locked and can be unlocked by system reset + */ +#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \ + SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \ + }while(0) +/** + * @} + */ +#endif /* SYSCFG_CFGR2_LOCKUP_LOCK */ + +#if defined(SYSCFG_CFGR2_PVD_LOCK) +/** @defgroup PVD_Lock_Enable PVD Lock + * @{ + */ +/** @brief SYSCFG Break PVD lock + * Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register + * @note The selected configuration is locked and can be unlocked by system reset + */ +#define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \ + SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \ + }while(0) +/** + * @} + */ +#endif /* SYSCFG_CFGR2_PVD_LOCK */ + +#if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK) +/** @defgroup SRAM_Parity_Lock SRAM Parity Lock + * @{ + */ +/** @brief SYSCFG Break SRAM PARITY lock + * Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17 + * @note The selected configuration is locked and can be unlocked by system reset + */ +#define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK); \ + SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK; \ + }while(0) +/** + * @} + */ +#endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */ + +#if defined(SYSCFG_CFGR2_SRAM_PEF) +/** @defgroup HAL_SYSCFG_Parity_check_on_RAM HAL SYSCFG Parity check on RAM + * @brief Parity check on RAM disable macro + * @note Disabling the parity check on RAM locks the configuration bit. + * To re-enable the parity check on RAM perform a system reset. + * @{ + */ +#define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PEF) +/** + * @} + */ +#endif /* SYSCFG_CFGR2_SRAM_PEF */ + + +#if defined(STM32F091xC) || defined (STM32F098xx) +/** @defgroup HAL_ISR_wrapper_check HAL ISR wrapper check + * @brief ISR wrapper check + * @note Allow to determine interrupt source per line. + * @{ + */ +#define __HAL_GET_PENDING_IT(__SOURCE__) (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18)] & ((__SOURCE__) & 0x00FFFFFF)) +/** + * @} + */ +#endif /* (STM32F091xC) || defined (STM32F098xx)*/ + +#if defined(STM32F091xC) || defined (STM32F098xx) +/** @defgroup HAL_SYSCFG_IRDA_modulation_envelope_selection HAL SYSCFG IRDA modulation envelope selection + * @brief selection of the modulation envelope signal macro, using bits [7:6] of SYS_CTRL(CFGR1) register + * @param __SOURCE__: This parameter can be a value of @ref HAL_IRDA_ENV_SEL + * @{ + */ +#define __HAL_SYSCFG_IRDA_ENV_SELECTION(__SOURCE__) do {assert_param(IS_HAL_SYSCFG_IRDA_ENV_SEL((__SOURCE__))); \ + SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_IRDA_ENV_SEL); \ + SYSCFG->CFGR1 |= (__SOURCE__); \ + }while(0) + +#define __HAL_SYSCFG_GET_IRDA_ENV_SELECTION() ((SYSCFG->CFGR1) & 0x000000C0) +/** + * @} + */ +#endif /* (STM32F091xC) || defined (STM32F098xx)*/ + +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup HAL_Exported_Functions HAL Exported Functions + * @{ + */ + +/** @addtogroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions + * @brief Initialization and de-initialization functions + * @{ + */ +/* Initialization and de-initialization functions ******************************/ +HAL_StatusTypeDef HAL_Init(void); +HAL_StatusTypeDef HAL_DeInit(void); +void HAL_MspInit(void); +void HAL_MspDeInit(void); +HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group2 HAL Control functions + * @brief HAL Control functions + * @{ + */ +/* Peripheral Control functions **********************************************/ +void HAL_IncTick(void); +void HAL_Delay(__IO uint32_t Delay); +uint32_t HAL_GetTick(void); +void HAL_SuspendTick(void); +void HAL_ResumeTick(void); +uint32_t HAL_GetHalVersion(void); +uint32_t HAL_GetREVID(void); +uint32_t HAL_GetDEVID(void); +void HAL_EnableDBGStopMode(void); +void HAL_DisableDBGStopMode(void); +void HAL_EnableDBGStandbyMode(void); +void HAL_DisableDBGStandbyMode(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h @@ -0,0 +1,958 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_adc.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Header file containing functions prototypes of ADC HAL library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_ADC_H +#define __STM32F0xx_HAL_ADC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup ADC_Exported_Types ADC Exported Types + * @{ + */ + +/** + * @brief Structure definition of ADC initialization and regular group + * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. + * ADC state can be either: + * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ClockPrescaler') + * - For all parameters except 'ClockPrescaler': ADC enabled without conversion on going on regular group. + * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed + * without error reporting without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). + */ +typedef struct +{ + uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from ADC dedicated HSI RC oscillator 14MHz) and clock prescaler. + This parameter can be a value of @ref ADC_ClockPrescaler + Note: In case of usage of the ADC dedicated HSI RC oscillator, it must be preliminarily enabled at RCC top level. + Note: This parameter can be modified only if the ADC is disabled */ + uint32_t Resolution; /*!< Configures the ADC resolution. + This parameter can be a value of @ref ADC_Resolution */ + uint32_t DataAlign; /*!< Specifies whether the ADC data alignment is left or right. + This parameter can be a value of @ref ADC_Data_align */ + uint32_t ScanConvMode; /*!< Configures the sequencer of regular group. + This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. + Sequencer is automatically enabled if several channels are set (sequencer cannot be disabled, as it can be the case on other STM32 devices): + If only 1 channel is set: Conversion is performed in single mode. + If several channels are set: Conversions are performed in sequence mode (ranks defined by each channel number: channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + Scan direction can be set to forward (from channel 0 to channel 18) or backward (from channel 18 to channel 0). + This parameter can be a value of @ref ADC_Scan_mode */ + uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence. + This parameter can be a value of @ref ADC_EOCSelection. */ + uint32_t LowPowerAutoWait; /*!< Selects the dynamic low power Auto Delay: new conversion start only when the previous + conversion (for regular group) or previous sequence (for injected group) has been treated by user software. + This feature automatically adapts the speed of ADC to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications. + This parameter can be set to ENABLE or DISABLE. + Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they have to clear immediately the EOC flag to free the IRQ vector sequencer. + Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed + and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion. */ + uint32_t LowPowerAutoPowerOff; /*!< Selects the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling). + This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait'). + This parameter can be set to ENABLE or DISABLE. + Note: If enabled, this feature also turns off the ADC dedicated 14 MHz RC oscillator (HSI14) */ + uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, + after the selected trigger occurred (software start or external trigger). + This parameter can be set to ENABLE or DISABLE. */ + uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). + Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. + Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. + This parameter can be set to ENABLE or DISABLE + Note: Number of discontinuous ranks increment is fixed to one-by-one. */ + uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group. + If set to ADC_SOFTWARE_START, external triggers are disabled. + This parameter can be a value of @ref ADC_External_trigger_source_Regular */ + uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group. + If trigger is set to ADC_SOFTWARE_START, this parameter is discarded. + This parameter can be a value of @ref ADC_External_trigger_edge_Regular */ + uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached) + or in Continuous mode (DMA transfer unlimited, whatever number of conversions). + Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. + This parameter can be set to ENABLE or DISABLE. */ + uint32_t Overrun; /*!< Select the behaviour in case of overrun: data preserved or overwritten + This parameter has an effect on regular group only, including in DMA mode. + This parameter can be a value of @ref ADC_Overrun */ +}ADC_InitTypeDef; + +/** + * @brief Structure definition of ADC channel for regular group + * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. + * ADC state can be either: + * - For all parameters: ADC disabled or enabled without conversion on going on regular group. + * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed + * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). + */ +typedef struct +{ + uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group. + This parameter can be a value of @ref ADC_channels + Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */ + uint32_t Rank; /*!< Add or remove the channel from ADC regular group sequencer. + On STM32F0 devices, rank is defined by each channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer. + This parameter can be a value of @ref ADC_rank */ + uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. + Unit: ADC clock cycles + Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). + This parameter can be a value of @ref ADC_sampling_times + Caution: this setting impacts the entire regular group. Therefore, call of HAL_ADC_ConfigChannel() to configure a channel can impact the configuration of other channels previously set. + Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), + sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) + Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17us). */ +}ADC_ChannelConfTypeDef; + +/** + * @brief Structure definition of ADC analog watchdog + * @note The setting of these parameters with function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. + * ADC state can be either: ADC disabled or ADC enabled without conversion on going on regular group. + */ +typedef struct +{ + uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all/none channels. + This parameter can be a value of @ref ADC_analog_watchdog_mode. */ + uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog. + This parameter has an effect only if parameter 'WatchdogMode' is configured on single channel. Only 1 channel can be monitored. + This parameter can be a value of @ref ADC_channels. */ + uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode. + This parameter can be set to ENABLE or DISABLE */ + uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. + Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ + uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. + Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ +}ADC_AnalogWDGConfTypeDef; + +/** + * @brief HAL ADC state machine: ADC States structure definition + */ +typedef enum +{ + HAL_ADC_STATE_RESET = 0x00, /*!< ADC not yet initialized or disabled */ + HAL_ADC_STATE_READY = 0x01, /*!< ADC peripheral ready for use */ + HAL_ADC_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ + HAL_ADC_STATE_BUSY_REG = 0x12, /*!< Regular conversion is ongoing */ + HAL_ADC_STATE_BUSY_INJ = 0x22, /*!< Not used on STM32F0xx devices (kept for compatibility with other devices featuring an injected group) */ + HAL_ADC_STATE_BUSY_INJ_REG = 0x32, /*!< Not used on STM32F0xx devices (kept for compatibility with other devices featuring an injected group) */ + HAL_ADC_STATE_TIMEOUT = 0x03, /*!< Timeout state */ + HAL_ADC_STATE_ERROR = 0x04, /*!< ADC state error */ + HAL_ADC_STATE_EOC = 0x05, /*!< Conversion is completed */ + HAL_ADC_STATE_EOC_REG = 0x15, /*!< Regular conversion is completed */ + HAL_ADC_STATE_EOC_INJ = 0x25, /*!< Not used on STM32F0xx devices (kept for compatibility with other devices featuring an injected group) */ + HAL_ADC_STATE_EOC_INJ_REG = 0x35, /*!< Not used on STM32F0xx devices (kept for compatibility with other devices featuring an injected group) */ + HAL_ADC_STATE_AWD = 0x06, /*!< ADC state analog watchdog */ + HAL_ADC_STATE_AWD2 = 0x07, /*!< Not used on STM32F0xx devices (kept for compatibility with other devices featuring several AWD) */ + HAL_ADC_STATE_AWD3 = 0x08, /*!< Not used on STM32F0xx devices (kept for compatibility with other devices featuring several AWD) */ +}HAL_ADC_StateTypeDef; + +/** + * @brief ADC handle Structure definition + */ +typedef struct +{ + ADC_TypeDef *Instance; /*!< Register base address */ + + ADC_InitTypeDef Init; /*!< ADC required parameters */ + + __IO uint32_t NbrOfConversionRank ; /*!< ADC conversion rank counter */ + + DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ + + HAL_LockTypeDef Lock; /*!< ADC locking object */ + + __IO HAL_ADC_StateTypeDef State; /*!< ADC communication state */ + + __IO uint32_t ErrorCode; /*!< ADC Error code */ +}ADC_HandleTypeDef; +/** + * @} + */ + + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup ADC_Exported_Constants ADC Exported Constants + * @{ + */ + +/** @defgroup ADC_Error_Code ADC Error Code + * @{ + */ +#define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */ +#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error: if problem of clocking, + enable/disable, erroneous state */ +#define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /*!< Overrun error */ +#define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /*!< DMA transfer error */ + +/** + * @} + */ + +/** @defgroup ADC_ClockPrescaler ADC ClockPrescaler + * @{ + */ +#define ADC_CLOCK_ASYNC ((uint32_t)0x00000000) /*!< ADC asynchronous clock derived from ADC dedicated HSI */ + +#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 2 */ +#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CFGR2_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 4 */ + +#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 /* Obsolete naming, kept for compatibility with some other devices */ +#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 /* Obsolete naming, kept for compatibility with some other devices */ + +#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC) || \ + ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ + ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) ) + +/** + * @} + */ + +/** @defgroup ADC_Resolution ADC Resolution + * @{ + */ +#define ADC_RESOLUTION12b ((uint32_t)0x00000000) /*!< ADC 12-bit resolution */ +#define ADC_RESOLUTION10b ((uint32_t)ADC_CFGR1_RES_0) /*!< ADC 10-bit resolution */ +#define ADC_RESOLUTION8b ((uint32_t)ADC_CFGR1_RES_1) /*!< ADC 8-bit resolution */ +#define ADC_RESOLUTION6b ((uint32_t)ADC_CFGR1_RES) /*!< ADC 6-bit resolution */ + +#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION12b) || \ + ((RESOLUTION) == ADC_RESOLUTION10b) || \ + ((RESOLUTION) == ADC_RESOLUTION8b) || \ + ((RESOLUTION) == ADC_RESOLUTION6b) ) +/** + * @} + */ + +/** @defgroup ADC_Data_align ADC Data_align + * @{ + */ +#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000) +#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR1_ALIGN) + +#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ + ((ALIGN) == ADC_DATAALIGN_LEFT) ) +/** + * @} + */ + +/** @defgroup ADC_Scan_mode ADC Scan mode + * @{ + */ +/* Note: Scan mode values must be compatible with other STM32 devices having */ +/* a configurable sequencer. */ +/* Scan direction setting values are defined by taking in account */ +/* already defined values for other STM32 devices: */ +/* ADC_SCAN_DISABLE ((uint32_t)0x00000000) */ +/* ADC_SCAN_ENABLE ((uint32_t)0x00000001) */ +/* Scan direction forward is considered as default setting equivalent */ +/* to scan enable. */ +/* Scan direction backward is considered as additional setting. */ +/* In case of migration from another STM32 device, the user will be */ +/* warned of change of setting choices with assert check. */ +#define ADC_SCAN_DIRECTION_FORWARD ((uint32_t)0x00000001) /*!< Scan direction forward: from channel 0 to channel 18 */ +#define ADC_SCAN_DIRECTION_BACKWARD ((uint32_t)0x00000002) /*!< Scan direction backward: from channel 18 to channel 0 */ + +#define ADC_SCAN_ENABLE ADC_SCAN_DIRECTION_FORWARD /* For compatibility with other STM32 devices */ + +#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DIRECTION_FORWARD) || \ + ((SCAN_MODE) == ADC_SCAN_DIRECTION_BACKWARD) ) +/** + * @} + */ + +/** @defgroup ADC_External_trigger_edge_Regular ADC External trigger edge Regular + * @{ + */ +#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000) +#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR1_EXTEN_0) +#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR1_EXTEN_1) +#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR1_EXTEN) + +#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ + ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ + ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ + ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) +/** + * @} + */ + +/** @defgroup ADC_External_trigger_source_Regular ADC External trigger source Regular + * @{ + */ +/* List of external triggers with generic trigger name, sorted by trigger */ +/* name: */ + +/* External triggers of regular group for ADC1 */ +#define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_2_EXTERNALTRIG_T1_TRGO +#define ADC_EXTERNALTRIGCONV_T1_CC4 ADC1_2_EXTERNALTRIG_T1_CC4 +#define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_2_EXTERNALTRIG_T2_TRGO +#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO +#define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_2_EXTERNALTRIG_T15_TRGO +#define ADC_SOFTWARE_START ((uint32_t)0x00000010) + +#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC4) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \ + ((REGTRIG) == ADC_SOFTWARE_START) ) +/** + * @} + */ + +/** @defgroup ADC_Internal_HAL_driver_Ext_trig_src_Regular ADC Internal HAL driver Ext trig src Regular + * @{ + */ + +/* List of external triggers of regular group for ADC1: */ +/* (used internally by HAL driver. To not use into HAL structure parameters) */ +#define ADC1_2_EXTERNALTRIG_T1_TRGO ((uint32_t)0x00000000) +#define ADC1_2_EXTERNALTRIG_T1_CC4 ((uint32_t)ADC_CFGR1_EXTSEL_0) +#define ADC1_2_EXTERNALTRIG_T2_TRGO ((uint32_t)ADC_CFGR1_EXTSEL_1) +#define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)(ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0)) +#define ADC1_2_EXTERNALTRIG_T15_TRGO ((uint32_t)ADC_CFGR1_EXTSEL_2) + +/** + * @} + */ + +/** @defgroup ADC_EOCSelection ADC EOCSelection + * @{ + */ +#define EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC) +#define EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS) +#define EOC_SINGLE_SEQ_CONV ((uint32_t)(ADC_ISR_EOC | ADC_ISR_EOS)) /*!< reserved for future use */ + +#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == EOC_SINGLE_CONV) || \ + ((EOC_SELECTION) == EOC_SEQ_CONV) || \ + ((EOC_SELECTION) == EOC_SINGLE_SEQ_CONV) ) +/** + * @} + */ + +/** @defgroup ADC_Overrun ADC Overrun + * @{ + */ +#define OVR_DATA_OVERWRITTEN ((uint32_t)0x00000000) +#define OVR_DATA_PRESERVED ((uint32_t)0x00000001) + +#define IS_ADC_OVERRUN(OVR) (((OVR) == OVR_DATA_PRESERVED) || \ + ((OVR) == OVR_DATA_OVERWRITTEN) ) +/** + * @} + */ + +/** @defgroup ADC_channels ADC channels + * @{ + */ +/* Note: Depending on devices, some channels may not be available on package */ +/* pins. Refer to device datasheet for channels availability. */ +/* Note: Channels are used by bitfields for setting of channel selection */ +/* (register ADC_CHSELR) and used by number for setting of analog watchdog */ +/* channel (bits AWDCH in register ADC_CFGR1). */ +/* Channels are defined with decimal numbers and converted them to bitfields */ +/* when needed. */ +#define ADC_CHANNEL_0 ((uint32_t) 0x00000000) +#define ADC_CHANNEL_1 ((uint32_t) 0x00000001) +#define ADC_CHANNEL_2 ((uint32_t) 0x00000002) +#define ADC_CHANNEL_3 ((uint32_t) 0x00000003) +#define ADC_CHANNEL_4 ((uint32_t) 0x00000004) +#define ADC_CHANNEL_5 ((uint32_t) 0x00000005) +#define ADC_CHANNEL_6 ((uint32_t) 0x00000006) +#define ADC_CHANNEL_7 ((uint32_t) 0x00000007) +#define ADC_CHANNEL_8 ((uint32_t) 0x00000008) +#define ADC_CHANNEL_9 ((uint32_t) 0x00000009) +#define ADC_CHANNEL_10 ((uint32_t) 0x0000000A) +#define ADC_CHANNEL_11 ((uint32_t) 0x0000000B) +#define ADC_CHANNEL_12 ((uint32_t) 0x0000000C) +#define ADC_CHANNEL_13 ((uint32_t) 0x0000000D) +#define ADC_CHANNEL_14 ((uint32_t) 0x0000000E) +#define ADC_CHANNEL_15 ((uint32_t) 0x0000000F) +#define ADC_CHANNEL_16 ((uint32_t) 0x00000010) +#define ADC_CHANNEL_17 ((uint32_t) 0x00000011) +#define ADC_CHANNEL_18 ((uint32_t) 0x00000012) + +#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 +#define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 +#define ADC_CHANNEL_VBAT ADC_CHANNEL_18 + +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ + ((CHANNEL) == ADC_CHANNEL_1) || \ + ((CHANNEL) == ADC_CHANNEL_2) || \ + ((CHANNEL) == ADC_CHANNEL_3) || \ + ((CHANNEL) == ADC_CHANNEL_4) || \ + ((CHANNEL) == ADC_CHANNEL_5) || \ + ((CHANNEL) == ADC_CHANNEL_6) || \ + ((CHANNEL) == ADC_CHANNEL_7) || \ + ((CHANNEL) == ADC_CHANNEL_8) || \ + ((CHANNEL) == ADC_CHANNEL_9) || \ + ((CHANNEL) == ADC_CHANNEL_10) || \ + ((CHANNEL) == ADC_CHANNEL_11) || \ + ((CHANNEL) == ADC_CHANNEL_12) || \ + ((CHANNEL) == ADC_CHANNEL_13) || \ + ((CHANNEL) == ADC_CHANNEL_14) || \ + ((CHANNEL) == ADC_CHANNEL_15) || \ + ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \ + ((CHANNEL) == ADC_CHANNEL_VREFINT) || \ + ((CHANNEL) == ADC_CHANNEL_VBAT) ) +/** + * @} + */ + +/** @defgroup ADC_rank ADC rank + * @{ + */ +#define ADC_RANK_CHANNEL_NUMBER ((uint32_t)0x00001000) /*!< Enable the rank of the selected channels. Rank is defined by each channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */ +#define ADC_RANK_NONE ((uint32_t)0x00001001) /*!< Disable the selected rank (selected channel) from sequencer */ + +#define IS_ADC_RANK(WATCHDOG) (((WATCHDOG) == ADC_RANK_CHANNEL_NUMBER) || \ + ((WATCHDOG) == ADC_RANK_NONE) ) +/** + * @} + */ + +/** @defgroup ADC_sampling_times ADC sampling times + * @{ + */ +#define ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x00000000) /*!< Sampling time 1.5 ADC clock cycle */ +#define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t) ADC_SMPR_SMP_0) /*!< Sampling time 7.5 ADC clock cycles */ +#define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t) ADC_SMPR_SMP_1) /*!< Sampling time 13.5 ADC clock cycles */ +#define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)(ADC_SMPR_SMP_1 | ADC_SMPR_SMP_0)) /*!< Sampling time 28.5 ADC clock cycles */ +#define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t) ADC_SMPR_SMP_2) /*!< Sampling time 41.5 ADC clock cycles */ +#define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR_SMP_2 | ADC_SMPR_SMP_0)) /*!< Sampling time 55.5 ADC clock cycles */ +#define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR_SMP_2 | ADC_SMPR_SMP_1)) /*!< Sampling time 71.5 ADC clock cycles */ +#define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t) ADC_SMPR_SMP) /*!< Sampling time 239.5 ADC clock cycles */ + +#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \ + ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \ + ((TIME) == ADC_SAMPLETIME_13CYCLES_5) || \ + ((TIME) == ADC_SAMPLETIME_28CYCLES_5) || \ + ((TIME) == ADC_SAMPLETIME_41CYCLES_5) || \ + ((TIME) == ADC_SAMPLETIME_55CYCLES_5) || \ + ((TIME) == ADC_SAMPLETIME_71CYCLES_5) || \ + ((TIME) == ADC_SAMPLETIME_239CYCLES_5) ) +/** + * @} + */ + +/** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode + * @{ + */ +#define ADC_ANALOGWATCHDOG_NONE ((uint32_t) 0x00000000) +#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN)) +#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR1_AWDEN) + + +#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) ) +/** + * @} + */ + +/** @defgroup ADC_Event_type ADC Event type + * @{ + */ +#define AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog 1 event */ +#define OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /*!< ADC overrun event */ + +#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == AWD_EVENT) || \ + ((EVENT) == OVR_EVENT) ) +/** + * @} + */ + +/** @defgroup ADC_interrupts_definition ADC interrupts definition + * @{ + */ +#define ADC_IT_AWD ADC_IER_AWDIE /*!< ADC Analog watchdog interrupt source */ +#define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ +#define ADC_IT_EOS ADC_IER_EOSEQIE /*!< ADC End of Regular sequence of Conversions interrupt source */ +#define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of Regular Conversion interrupt source */ +#define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of Sampling interrupt source */ +#define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */ +/** + * @} + */ + +/** @defgroup ADC_flags_definition ADC flags definition + * @{ + */ +#define ADC_FLAG_AWD ADC_ISR_AWD /*!< ADC Analog watchdog flag */ +#define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ +#define ADC_FLAG_EOS ADC_ISR_EOSEQ /*!< ADC End of Regular sequence of Conversions flag */ +#define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ +#define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ +#define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */ + +#define ADC_FLAG_ALL (ADC_FLAG_AWD | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC | \ + ADC_FLAG_EOSMP | ADC_FLAG_RDY ) + +/* Combination of all post-conversion flags bits: EOC/EOS, OVR, AWD */ +#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_AWD | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC) +/** + * @} + */ + +/** @defgroup ADC_range_verification ADC range verification + * in function of ADC resolution selected (12, 10, 8 or 6 bits) + * @{ + */ +#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \ + ((((RESOLUTION) == ADC_RESOLUTION12b) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) || \ + (((RESOLUTION) == ADC_RESOLUTION10b) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) || \ + (((RESOLUTION) == ADC_RESOLUTION8b) && ((ADC_VALUE) <= ((uint32_t)0x00FF))) || \ + (((RESOLUTION) == ADC_RESOLUTION6b) && ((ADC_VALUE) <= ((uint32_t)0x003F))) ) +/** + * @} + */ + +/** @defgroup ADC_regular_rank_verification ADC regular rank verification + * @{ + */ +#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= ((uint32_t)1)) && ((RANK) <= ((uint32_t)16))) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup ADC_Exported_Macros ADC Exported Macros + * @{ + */ +/** @brief Reset ADC handle state + * @param __HANDLE__: ADC handle + * @retval None + */ +#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET) + +/* Macro for internal HAL driver usage, and possibly can be used into code of */ +/* final user. */ + +/** + * @brief Verification of ADC state: enabled or disabled + * @param __HANDLE__: ADC handle + * @retval SET (ADC enabled) or RESET (ADC disabled) + */ +/* Note: If low power mode AutoPowerOff is enabled, power-on/off phases are */ +/* performed automatically by hardware and flag ADC_FLAG_RDY is not */ +/* set. */ +#define __HAL_ADC_IS_ENABLED(__HANDLE__) \ + (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \ + (((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) || \ + ((((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_AUTOFF) == ADC_CFGR1_AUTOFF) ) \ + ) ? SET : RESET) + +/** + * @brief Test if conversion trigger of regular group is software start + * or external trigger. + * @param __HANDLE__: ADC handle + * @retval SET (software start) or RESET (external trigger) + */ +#define __HAL_ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ + (((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == RESET) + +/** + * @brief Check if no conversion on going on regular group + * @param __HANDLE__: ADC handle + * @retval SET (conversion is on going) or RESET (no conversion is on going) + */ +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \ + (( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET \ + ) ? RESET : SET) + +/** + * @brief Returns resolution bits in CFGR1 register: RES[1:0]. + * Returned value is among parameters to @ref ADC_Resolution. + * @param __HANDLE__: ADC handle + * @retval None + */ +#define __HAL_ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES) + +/** + * @brief Returns ADC sample time bits in SMPR register: SMP[2:0]. + * Returned value is among parameters to @ref ADC_Resolution. + * @param __HANDLE__: ADC handle + * @retval None + */ +#define __HAL_ADC_GET_SAMPLINGTIME(__HANDLE__) (((__HANDLE__)->Instance->SMPR) & ADC_SMPR_SMP) + +/** @brief Checks if the specified ADC interrupt source is enabled or disabled. + * @param __HANDLE__: ADC handle + * @param __INTERRUPT__: ADC interrupt source to check + * @retval State ofinterruption (SET or RESET) + */ +#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + (( ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__) \ + )? SET : RESET \ + ) + +/** + * @brief Enable the ADC end of conversion interrupt. + * @param __HANDLE__: ADC handle + * @param __INTERRUPT__: ADC Interrupt + * @retval None + */ +#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) + +/** + * @brief Disable the ADC end of conversion interrupt. + * @param __HANDLE__: ADC handle + * @param __INTERRUPT__: ADC Interrupt + * @retval None + */ +#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) + +/** + * @brief Get the selected ADC's flag status. + * @param __HANDLE__: ADC handle + * @param __FLAG__: ADC flag + * @retval None + */ +#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear the ADC's pending flags + * @param __HANDLE__: ADC handle + * @param __FLAG__: ADC flag + * @retval None + */ +/* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ +#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR) = (__FLAG__)) + +/** + * @brief Clear ADC error code (set it to error code: "no error") + * @param __HANDLE__: ADC handle + * @retval None + */ +#define __HAL_ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) + + +/** + * @brief Configure the channel number into channel selection register + * @param _CHANNEL_: ADC Channel + * @retval None + */ +/* This function converts ADC channels from numbers (see defgroup ADC_channels) + to bitfields, to get the equivalence of CMSIS channels: + ADC_CHANNEL_0 ((uint32_t) ADC_CHSELR_CHSEL0) + ADC_CHANNEL_1 ((uint32_t) ADC_CHSELR_CHSEL1) + ADC_CHANNEL_2 ((uint32_t) ADC_CHSELR_CHSEL2) + ADC_CHANNEL_3 ((uint32_t) ADC_CHSELR_CHSEL3) + ADC_CHANNEL_4 ((uint32_t) ADC_CHSELR_CHSEL4) + ADC_CHANNEL_5 ((uint32_t) ADC_CHSELR_CHSEL5) + ADC_CHANNEL_6 ((uint32_t) ADC_CHSELR_CHSEL6) + ADC_CHANNEL_7 ((uint32_t) ADC_CHSELR_CHSEL7) + ADC_CHANNEL_8 ((uint32_t) ADC_CHSELR_CHSEL8) + ADC_CHANNEL_9 ((uint32_t) ADC_CHSELR_CHSEL9) + ADC_CHANNEL_10 ((uint32_t) ADC_CHSELR_CHSEL10) + ADC_CHANNEL_11 ((uint32_t) ADC_CHSELR_CHSEL11) + ADC_CHANNEL_12 ((uint32_t) ADC_CHSELR_CHSEL12) + ADC_CHANNEL_13 ((uint32_t) ADC_CHSELR_CHSEL13) + ADC_CHANNEL_14 ((uint32_t) ADC_CHSELR_CHSEL14) + ADC_CHANNEL_15 ((uint32_t) ADC_CHSELR_CHSEL15) + ADC_CHANNEL_16 ((uint32_t) ADC_CHSELR_CHSEL16) + ADC_CHANNEL_17 ((uint32_t) ADC_CHSELR_CHSEL17) + ADC_CHANNEL_18 ((uint32_t) ADC_CHSELR_CHSEL18) +*/ +#define __HAL_ADC_CHSELR_CHANNEL(_CHANNEL_) ( 1U << (_CHANNEL_)) + +/** + * @} + */ + +/** @defgroup ADC_Exported_Macro_internal_HAL_driver ADC Exported Macro internal HAL driver + * @{ + */ +/* Macro reserved for internal HAL driver usage, not intended to be used in */ +/* code of final user. */ + +/** + * @brief Set the Analog Watchdog 1 channel. + * @param _CHANNEL_: channel to be monitored by Analog Watchdog 1. + * @retval None + */ +#define __HAL_ADC_CFGR_AWDCH(_CHANNEL_) ((_CHANNEL_) << 26) + +/** + * @brief Enable ADC discontinuous conversion mode for regular group + * @param _REG_DISCONTINUOUS_MODE_: Regulat discontinuous mode. + * @retval None + */ +#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_) ((_REG_DISCONTINUOUS_MODE_) << 16) + +/** + * @brief Enable the ADC auto off mode. + * @param _AUTOOFF_: Auto off bit enable or disable. + * @retval None + */ +#define __HAL_ADC_CFGR1_AUTOOFF(_AUTOOFF_) ((_AUTOOFF_) << 15) + +/** + * @brief Enable the ADC auto delay mode. + * @param _AUTOWAIT_: Auto delay bit enable or disable. + * @retval None + */ +#define __HAL_ADC_CFGR1_AUTOWAIT(_AUTOWAIT_) ((_AUTOWAIT_) << 14) + +/** + * @brief Enable ADC continuous conversion mode. + * @param _CONTINUOUS_MODE_: Continuous mode. + * @retval None + */ +#define __HAL_ADC_CFGR1_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 13) + +/** + * @brief Enable ADC overrun mode. + * @param _OVERRUN_MODE_: Overrun mode. + * @retval Overun bit setting to be programmed into CFGR register + */ +/* Note: Bit ADC_CFGR1_OVRMOD not used directly in constant */ +/* "OVR_DATA_OVERWRITTEN" to have this case defined to 0x00, to set it as the */ +/* default case to be compliant with other STM32 devices. */ +#define __HAL_ADC_CFGR1_OVERRUN(_OVERRUN_MODE_) \ + ( ( (_OVERRUN_MODE_) != (OVR_DATA_PRESERVED) \ + )? (ADC_CFGR1_OVRMOD) : (0x00000000) \ + ) + +/** + * @brief Enable ADC scan mode to convert multiple ranks with sequencer. + * @param _SCAN_MODE_: Scan conversion mode. + * @retval None + */ +#define __HAL_ADC_CFGR1_SCANDIR(_SCAN_MODE_) \ + ( ( (_SCAN_MODE_) == (ADC_SCAN_DIRECTION_BACKWARD) \ + )? (ADC_CFGR1_SCANDIR) : (0x00000000) \ + ) + +/** + * @brief Enable the ADC DMA continuous request. + * @param _DMACONTREQ_MODE_: DMA continuous request mode. + * @retval None + */ +#define __HAL_ADC_CFGR1_DMACONTREQ(_DMACONTREQ_MODE_) ((_DMACONTREQ_MODE_) << 1) + +/** + * @brief Configure the channel number into offset OFRx register + * @param _CHANNEL_: ADC Channel + * @retval None + */ +#define __HAL_ADC_OFR_CHANNEL(_CHANNEL_) ((_CHANNEL_) << 26) + +/** + * @brief Configure the analog watchdog high threshold into register TR. + * @param _Threshold_: Threshold value + * @retval None + */ +#define __HAL_ADC_TRX_HIGHTHRESHOLD(_Threshold_) ((_Threshold_) << 16) + +/** + * @brief Enable the ADC peripheral + * @param __HANDLE__: ADC handle + * @retval None + */ +#define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN) + +/** + * @brief Verification of hardware constraints before ADC can be enabled + * @param __HANDLE__: ADC handle + * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled) + */ +#define __HAL_ADC_ENABLING_CONDITIONS(__HANDLE__) \ + (( ( ((__HANDLE__)->Instance->CR) & \ + (ADC_CR_ADCAL | ADC_CR_ADSTP | \ + ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN ) \ + ) == RESET \ + ) ? SET : RESET) + +/** + * @brief Disable the ADC peripheral + * @param __HANDLE__: ADC handle + * @retval None + */ +#define __HAL_ADC_DISABLE(__HANDLE__) \ + do{ \ + (__HANDLE__)->Instance->CR |= ADC_CR_ADDIS; \ + __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \ + } while(0) + +/** + * @brief Verification of hardware constraints before ADC can be disabled + * @param __HANDLE__: ADC handle + * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled) + */ +#define __HAL_ADC_DISABLING_CONDITIONS(__HANDLE__) \ + (( ( ((__HANDLE__)->Instance->CR) & \ + (ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN \ + ) ? SET : RESET) + +/** + * @brief Shift the AWD threshold in function of the selected ADC resolution. + * Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0. + * If resolution 12 bits, no shift. + * If resolution 10 bits, shift of 2 ranks on the left. + * If resolution 8 bits, shift of 4 ranks on the left. + * If resolution 6 bits, shift of 6 ranks on the left. + * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)) + * @param __HANDLE__: ADC handle + * @param _Threshold_: Value to be shifted + * @retval None + */ +#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \ + ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3)*2)) + +/** + * @} + */ + +/* Include ADC HAL Extension module */ +#include "stm32f0xx_hal_adc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup ADC_Exported_Functions + * @{ + */ + +/** @addtogroup ADC_Exported_Functions_Group1 + * @{ + */ + + +/* Initialization and de-initialization functions **********************************/ +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); +void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); +void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); +/** + * @} + */ + +/* IO operation functions *****************************************************/ + +/** @addtogroup ADC_Exported_Functions_Group2 + * @{ + */ + + +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); +HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); + +/* Non-blocking mode: Interruption */ +HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); + +/* Non-blocking mode: DMA */ +HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); +HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); + +/* ADC retrieve conversion value intended to be used with polling or interruption */ +uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); + +/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ +void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); +void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); +void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); +void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); +void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); +/** + * @} + */ + + +/* Peripheral Control functions ***********************************************/ +/** @addtogroup ADC_Exported_Functions_Group3 + * @{ + */ +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); +/** + * @} + */ + + +/* Peripheral State functions *************************************************/ +/** @addtogroup ADC_Exported_Functions_Group4 + * @{ + */ +HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc); +uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); +/** + * @} + */ + + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F0xx_HAL_ADC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h @@ -0,0 +1,98 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_adc_ex.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Header file of ADC HAL Extension module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_ADC_EX_H +#define __STM32F0xx_HAL_ADC_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup ADCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup ADCEx_Exported_Functions + * @{ + */ + +/* IO operation functions *****************************************************/ +/** @addtogroup ADCEx_Exported_Functions_Group1 + * @{ + */ + +/* ADC calibration */ +HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc); +/** + * @} + */ + + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_ADC_EX_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h @@ -0,0 +1,809 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_can.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Header file of CAN HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_CAN_H +#define __STM32F0xx_HAL_CAN_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(STM32F072xB) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F091xC) || defined(STM32F098xx) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup CAN CAN HAL Module Driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CAN_Exported_Types CAN Exported Types + * @{ + */ +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_CAN_STATE_RESET = 0x00, /*!< CAN not yet initialized or disabled */ + HAL_CAN_STATE_READY = 0x01, /*!< CAN initialized and ready for use */ + HAL_CAN_STATE_BUSY = 0x02, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX = 0x12, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_RX = 0x22, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX_RX = 0x32, /*!< CAN process is ongoing */ + HAL_CAN_STATE_TIMEOUT = 0x03, /*!< CAN in Timeout state */ + HAL_CAN_STATE_ERROR = 0x04 /*!< CAN error state */ + +}HAL_CAN_StateTypeDef; + +/** + * @brief HAL CAN Error Code structure definition + */ +typedef enum +{ + HAL_CAN_ERROR_NONE = 0x00, /*!< No error */ + HAL_CAN_ERROR_EWG = 0x01, /*!< EWG error */ + HAL_CAN_ERROR_EPV = 0x02, /*!< EPV error */ + HAL_CAN_ERROR_BOF = 0x04, /*!< BOF error */ + HAL_CAN_ERROR_STF = 0x08, /*!< Stuff error */ + HAL_CAN_ERROR_FOR = 0x10, /*!< Form error */ + HAL_CAN_ERROR_ACK = 0x20, /*!< Acknowledgment error */ + HAL_CAN_ERROR_BR = 0x40, /*!< Bit recessive */ + HAL_CAN_ERROR_BD = 0x80, /*!< LEC dominant */ + HAL_CAN_ERROR_CRC = 0x100 /*!< LEC transfer error */ +}HAL_CAN_ErrorTypeDef; + +/** + * @brief CAN init structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the length of a time quantum. + This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */ + + uint32_t Mode; /*!< Specifies the CAN operating mode. + This parameter can be a value of @ref CAN_operating_mode */ + + uint32_t SJW; /*!< Specifies the maximum number of time quanta + the CAN hardware is allowed to lengthen or + shorten a bit to perform resynchronization. + This parameter can be a value of @ref CAN_synchronisation_jump_width */ + + uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ + + uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ + + uint32_t TTCM; /*!< Enable or disable the time triggered communication mode. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t ABOM; /*!< Enable or disable the automatic bus-off management. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t RFLM; /*!< Enable or disable the Receive FIFO Locked mode. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority. + This parameter can be set to ENABLE or DISABLE. */ +}CAN_InitTypeDef; + +/** + * @brief CAN filter configuration structure definition + */ +typedef struct +{ + uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit + configuration, first one for a 16-bit configuration). + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit + configuration, second one for a 16-bit configuration). + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, + according to the mode (MSBs for a 32-bit configuration, + first one for a 16-bit configuration). + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, + according to the mode (LSBs for a 32-bit configuration, + second one for a 16-bit configuration). + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. + This parameter can be a value of @ref CAN_filter_FIFO */ + + uint32_t FilterNumber; /*!< Specifies the filter which will be initialized. + This parameter must be a number between Min_Data = 0 and Max_Data = 27. */ + + uint32_t FilterMode; /*!< Specifies the filter mode to be initialized. + This parameter can be a value of @ref CAN_filter_mode */ + + uint32_t FilterScale; /*!< Specifies the filter scale. + This parameter can be a value of @ref CAN_filter_scale */ + + uint32_t FilterActivation; /*!< Enable or disable the filter. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t BankNumber; /*!< Select the start slave bank filter + This parameter must be a number between Min_Data = 0 and Max_Data = 28. */ + +}CAN_FilterConfTypeDef; + +/** + * @brief CAN Tx message structure definition + */ +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ + + uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. + This parameter can be a value of @ref CAN_identifier_type */ + + uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. + This parameter can be a value of @ref CAN_remote_transmission_request */ + + uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. + This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ + + uint32_t Data[8]; /*!< Contains the data to be transmitted. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */ + +}CanTxMsgTypeDef; + +/** + * @brief CAN Rx message structure definition + */ +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ + + uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received. + This parameter can be a value of @ref CAN_identifier_type */ + + uint32_t RTR; /*!< Specifies the type of frame for the received message. + This parameter can be a value of @ref CAN_remote_transmission_request */ + + uint32_t DLC; /*!< Specifies the length of the frame that will be received. + This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ + + uint32_t Data[8]; /*!< Contains the data to be received. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */ + + uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */ + + uint32_t FIFONumber; /*!< Specifies the receive FIFO number. + This parameter can be CAN_FIFO0 or CAN_FIFO1 */ + +}CanRxMsgTypeDef; + +/** + * @brief CAN handle Structure definition + */ +typedef struct +{ + CAN_TypeDef *Instance; /*!< Register base address */ + + CAN_InitTypeDef Init; /*!< CAN required parameters */ + + CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */ + + CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure */ + + HAL_LockTypeDef Lock; /*!< CAN locking object */ + + __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ + + __IO HAL_CAN_ErrorTypeDef ErrorCode; /*!< CAN Error code */ + +}CAN_HandleTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CAN_Exported_Constants CAN Exported Constants + * @{ + */ + +/** @defgroup CAN_InitStatus CAN InitStatus + * @{ + */ +#define CAN_INITSTATUS_FAILED ((uint32_t)0x00000000) /*!< CAN initialization failed */ +#define CAN_INITSTATUS_SUCCESS ((uint32_t)0x00000001) /*!< CAN initialization OK */ +/** + * @} + */ + +/** @defgroup CAN_operating_mode CAN operating mode + * @{ + */ +#define CAN_MODE_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */ +#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */ +#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */ +#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */ + +#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \ + ((MODE) == CAN_MODE_LOOPBACK)|| \ + ((MODE) == CAN_MODE_SILENT) || \ + ((MODE) == CAN_MODE_SILENT_LOOPBACK)) +/** + * @} + */ + + +/** @defgroup CAN_synchronisation_jump_width CAN synchronisation jump width + * @{ + */ +#define CAN_SJW_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */ +#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */ +#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */ +#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */ + +#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \ + ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ)) +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN time quantum in bit segment 1 + * @{ + */ +#define CAN_BS1_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */ +#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */ +#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */ +#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */ +#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */ +#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */ +#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */ +#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */ +#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */ +#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */ +#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */ +#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */ +#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */ +#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */ +#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */ +#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */ + +#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ) +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN time quantum in bit segment 2 + * @{ + */ +#define CAN_BS2_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */ +#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */ +#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */ +#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */ +#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */ +#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */ +#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */ +#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */ + +#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ) +/** + * @} + */ + +/** @defgroup CAN_clock_prescaler CAN clock prescaler + * @{ + */ +#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) +/** + * @} + */ + +/** @defgroup CAN_filter_number CAN filter number + * @{ + */ +#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) +/** + * @} + */ + +/** @defgroup CAN_filter_mode CAN filter mode + * @{ + */ +#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */ +#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */ + +#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \ + ((MODE) == CAN_FILTERMODE_IDLIST)) +/** + * @} + */ + +/** @defgroup CAN_filter_scale CAN filter scale + * @{ + */ +#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */ +#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */ + +#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \ + ((SCALE) == CAN_FILTERSCALE_32BIT)) +/** + * @} + */ + +/** @defgroup CAN_filter_FIFO CAN filter FIFO + * @{ + */ +#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ +#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ + +#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \ + ((FIFO) == CAN_FILTER_FIFO1)) + +/* Legacy defines */ +#define CAN_FilterFIFO0 CAN_FILTER_FIFO0 +#define CAN_FilterFIFO1 CAN_FILTER_FIFO1 +/** + * @} + */ + +/** @defgroup CAN_Start_bank_filter_for_slave_CAN CAN Start bank filter for slave CAN + * @{ + */ +#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28) +/** + * @} + */ + +/** @defgroup CAN_Tx CAN Tx + * @{ + */ +#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) +#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) +#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) +#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) +/** + * @} + */ + +/** @defgroup CAN_identifier_type CAN identifier type + * @{ + */ +#define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */ +#define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */ +#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \ + ((IDTYPE) == CAN_ID_EXT)) +/** + * @} + */ + +/** @defgroup CAN_remote_transmission_request CAN remote transmission request + * @{ + */ +#define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */ +#define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */ +#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) + +/** + * @} + */ + +/** @defgroup CAN_transmit_constants CAN transmit constants + * @{ + */ +#define CAN_TXSTATUS_FAILED ((uint8_t)0x00) /*!< CAN transmission failed */ +#define CAN_TXSTATUS_OK ((uint8_t)0x01) /*!< CAN transmission succeeded */ +#define CAN_TXSTATUS_PENDING ((uint8_t)0x02) /*!< CAN transmission pending */ +#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */ + +/** + * @} + */ + +/** @defgroup CAN_receive_FIFO_number_constants CAN receive FIFO number constants + * @{ + */ +#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ +#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ + +#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) +/** + * @} + */ + +/** @defgroup CAN_flags CAN flags + * @{ + */ +/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() + and CAN_ClearFlag() functions. */ +/* If the flag is 0x1XXXXXXX, it means that it can only be used with + CAN_GetFlagStatus() function. */ + +/* Transmit Flags */ +#define CAN_FLAG_RQCP0 ((uint32_t)0x00000500) /*!< Request MailBox0 flag */ +#define CAN_FLAG_RQCP1 ((uint32_t)0x00000508) /*!< Request MailBox1 flag */ +#define CAN_FLAG_RQCP2 ((uint32_t)0x00000510) /*!< Request MailBox2 flag */ +#define CAN_FLAG_TXOK0 ((uint32_t)0x00000501) /*!< Transmission OK MailBox0 flag */ +#define CAN_FLAG_TXOK1 ((uint32_t)0x00000509) /*!< Transmission OK MailBox1 flag */ +#define CAN_FLAG_TXOK2 ((uint32_t)0x00000511) /*!< Transmission OK MailBox2 flag */ +#define CAN_FLAG_TME0 ((uint32_t)0x0000051A) /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_TME1 ((uint32_t)0x0000051B) /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_TME2 ((uint32_t)0x0000051C) /*!< Transmit mailbox 0 empty flag */ + +/* Receive Flags */ +#define CAN_FLAG_FF0 ((uint32_t)0x00000203) /*!< FIFO 0 Full flag */ +#define CAN_FLAG_FOV0 ((uint32_t)0x00000204) /*!< FIFO 0 Overrun flag */ + +#define CAN_FLAG_FF1 ((uint32_t)0x00000403) /*!< FIFO 1 Full flag */ +#define CAN_FLAG_FOV1 ((uint32_t)0x00000404) /*!< FIFO 1 Overrun flag */ + +/* Operating Mode Flags */ +#define CAN_FLAG_WKU ((uint32_t)0x00000103) /*!< Wake up flag */ +#define CAN_FLAG_SLAK ((uint32_t)0x00000101) /*!< Sleep acknowledge flag */ +#define CAN_FLAG_SLAKI ((uint32_t)0x00000104) /*!< Sleep acknowledge flag */ +/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. + In this case the SLAK bit can be polled.*/ + +/* Error Flags */ +#define CAN_FLAG_EWG ((uint32_t)0x00000300) /*!< Error warning flag */ +#define CAN_FLAG_EPV ((uint32_t)0x00000301) /*!< Error passive flag */ +#define CAN_FLAG_BOF ((uint32_t)0x00000302) /*!< Bus-Off flag */ +/** + * @} + */ + + +/** @defgroup CAN_interrupts CAN interrupts + * @{ + */ +#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */ + +/* Receive Interrupts */ +#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */ +#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */ +#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */ +#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */ +#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */ +#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */ + +/* Operating Mode Interrupts */ +#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */ +#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */ + +/* Error Interrupts */ +#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */ +#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */ +#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */ +#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */ +#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */ + +/* Flags named as Interrupts : kept only for FW compatibility */ +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME +/** + * @} + */ + +/** @defgroup CAN_Timeouts CAN Timeouts +* @{ +*/ + +/* Time out for INAK bit */ +#define INAK_TIMEOUT ((uint32_t)0x00FFFFFF) +/* Time out for SLAK bit */ +#define SLAK_TIMEOUT ((uint32_t)0x00FFFFFF) +/** + * @} + */ + +/** @defgroup CAN_Mailboxes CAN Mailboxes +* @{ +*/ +/* Mailboxes definition */ +#define CAN_TXMAILBOX_0 ((uint8_t)0x00) +#define CAN_TXMAILBOX_1 ((uint8_t)0x01) +#define CAN_TXMAILBOX_2 ((uint8_t)0x02) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup CAN_Exported_Macros CAN Exported Macros + * @{ + */ + +/** @brief Reset CAN handle state + * @param __HANDLE__: CAN handle. + * @retval None + */ +#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET) + +/** + * @brief Enable the specified CAN interrupts. + * @param __HANDLE__: CAN handle. + * @param __INTERRUPT__: CAN Interrupt + * @retval None + */ +#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) + +/** + * @brief Disable the specified CAN interrupts. + * @param __HANDLE__: CAN handle. + * @param __INTERRUPT__: CAN Interrupt + * @retval None + */ +#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) + +/** + * @brief Return the number of pending received messages. + * @param __HANDLE__: CAN handle. + * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. + * @retval The number of pending message. + */ +#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ +((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&(uint32_t)0x03))) + +/** @brief Check whether the specified CAN flag is set or not. + * @param __HANDLE__: specifies the CAN Handle. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg CAN_TSR_RQCP0: Request MailBox0 Flag + * @arg CAN_TSR_RQCP1: Request MailBox1 Flag + * @arg CAN_TSR_RQCP2: Request MailBox2 Flag + * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag + * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag + * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag + * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag + * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag + * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag + * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag + * @arg CAN_FLAG_FF0: FIFO 0 Full Flag + * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag + * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag + * @arg CAN_FLAG_FF1: FIFO 1 Full Flag + * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag + * @arg CAN_FLAG_WKU: Wake up Flag + * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag + * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag + * @arg CAN_FLAG_EWG: Error Warning Flag + * @arg CAN_FLAG_EPV: Error Passive Flag + * @arg CAN_FLAG_BOF: Bus-Off Flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define CAN_FLAG_MASK ((uint32_t)0x000000FF) +#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \ +((((__FLAG__) >> 8) == 5)? ((((__HANDLE__)->Instance->TSR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8) == 2)? ((((__HANDLE__)->Instance->RF0R) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8) == 4)? ((((__HANDLE__)->Instance->RF1R) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8) == 1)? ((((__HANDLE__)->Instance->MSR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \ + ((((__HANDLE__)->Instance->ESR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK)))) + +/** @brief Clear the specified CAN pending flag. + * @param __HANDLE__: specifies the CAN Handle. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg CAN_TSR_RQCP0: Request MailBox0 Flag + * @arg CAN_TSR_RQCP1: Request MailBox1 Flag + * @arg CAN_TSR_RQCP2: Request MailBox2 Flag + * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag + * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag + * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag + * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag + * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag + * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag + * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag + * @arg CAN_FLAG_FF0: FIFO 0 Full Flag + * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag + * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag + * @arg CAN_FLAG_FF1: FIFO 1 Full Flag + * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag + * @arg CAN_FLAG_WKU: Wake up Flag + * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag + * @arg CAN_FLAG_EWG: Error Warning Flag + * @arg CAN_FLAG_EPV: Error Passive Flag + * @arg CAN_FLAG_BOF: Bus-Off Flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ +((((__FLAG__) >> 8U) == 5)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 2)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 4)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 1)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0) + + +/** @brief Check if the specified CAN interrupt source is enabled or disabled. + * @param __HANDLE__: specifies the CAN Handle. + * @param __INTERRUPT__: specifies the CAN interrupt source to check. + * This parameter can be one of the following values: + * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable + * @arg CAN_IT_FMP0: FIFO0 message pending interrupt enablev + * @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** + * @brief Check the transmission status of a CAN Frame. + * @param __HANDLE__: CAN handle. + * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission. + * @retval The new status of transmission (TRUE or FALSE). + */ +#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\ +(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\ + ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\ + ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2))) + + + +/** + * @brief Release the specified receive FIFO. + * @param __HANDLE__: CAN handle. + * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. + * @retval None + */ +#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ +((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1)) + +/** + * @brief Cancel a transmit request. + * @param __HANDLE__: specifies the CAN Handle. + * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission. + * @retval None + */ +#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\ +(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\ + ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\ + ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2)) + +/** + * @brief Enable or disables the DBG Freeze for CAN. + * @param __HANDLE__: specifies the CAN Handle. + * @param __NEWSTATE__: new state of the CAN peripheral. + * This parameter can be: ENABLE (CAN reception/transmission is frozen + * during debug. Reception FIFOs can still be accessed/controlled normally) + * or DISABLE (CAN is working during debug). + * @retval None + */ +#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \ +((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CAN_Exported_Functions CAN Exported Functions + * @{ + */ + +/** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan); +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig); +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan); +void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan); +void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan); +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group2 I/O operation functions + * @brief I/O operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout); +HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout); +HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber); +HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan); + +void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan); + +void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan); +void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan); +void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan); +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group3 Peripheral State and Error functions + * @brief CAN Peripheral State functions + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan); +HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32F072xB || STM32F042x6 || STM32F048xx || STM32F091xC || STM32F098xx */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_CAN_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cec.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cec.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cec.h @@ -0,0 +1,598 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_cec.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Header file of CEC HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_CEC_H +#define __STM32F0xx_HAL_CEC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(STM32F042x6) || defined(STM32F048xx) ||\ + defined(STM32F051x8) || defined(STM32F058xx) ||\ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) ||\ + defined(STM32F091xC) || defined(STM32F098xx) +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup CEC CEC HAL Module Driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CEC_Exported_Types CEC Exported Types + * @{ + */ + +/** + * @brief CEC Init Structure definition + */ +typedef struct +{ + uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time. + It can be one of @ref CEC_Signal_Free_Time + and belongs to the set {0,...,7} where + 0x0 is the default configuration + else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */ + + uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms, + it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE + or CEC_EXTENDED_TOLERANCE */ + + uint32_t BRERxStop; /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception. + CEC_NO_RX_STOP_ON_BRE: reception is not stopped. + CEC_RX_STOP_ON_BRE: reception is stopped. */ + + uint32_t BREErrorBitGen; /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the + CEC line upon Bit Rising Error detection. + CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation. + CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */ + + uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the + CEC line upon Long Bit Period Error detection. + CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation. + CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */ + + uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line + upon an error detected on a broadcast message. + + It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values: + + 1) CEC_BROADCASTERROR_ERRORBIT_GENERATION. + a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE + and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION. + b) LBPE detection: error-bit generation on the CEC line + if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION. + + 2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION. + no error-bit generation in case neither a) nor b) are satisfied. Additionally, + there is no error-bit generation in case of Short Bit Period Error detection in + a broadcast message while LSTN bit is set. */ + + uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts. + CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software. + CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception. */ + + uint32_t OwnAddress; /*!< Set OAR field, specifies CEC device address within a 15-bit long field */ + + uint32_t ListenMode; /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values: + + CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its + own address (OAR). Messages addressed to different destination are ignored. + Broadcast messages are always received. + + CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own + address (OAR) with positive acknowledge. Messages addressed to different destination + are received, but without interfering with the CEC bus: no acknowledge sent. */ + + uint8_t InitiatorAddress; /* Initiator address (source logical address, sent in each header) */ + +}CEC_InitTypeDef; + +/** + * @brief HAL CEC State structures definition + */ +typedef enum +{ + HAL_CEC_STATE_RESET = 0x00, /*!< Peripheral Reset state */ + HAL_CEC_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ + HAL_CEC_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ + HAL_CEC_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */ + HAL_CEC_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */ + HAL_CEC_STATE_STANDBY_RX = 0x05, /*!< IP ready to receive, doesn't prevent IP to transmit */ + HAL_CEC_STATE_TIMEOUT = 0x06, /*!< Timeout state */ + HAL_CEC_STATE_ERROR = 0x07 /*!< State Error */ +}HAL_CEC_StateTypeDef; + +/** + * @brief HAL Error structures definition + */ +typedef enum +{ + HAL_CEC_ERROR_NONE = (uint32_t) 0x0, /*!< no error */ + HAL_CEC_ERROR_RXOVR = CEC_ISR_RXOVR, /*!< CEC Rx-Overrun */ + HAL_CEC_ERROR_BRE = CEC_ISR_BRE, /*!< CEC Rx Bit Rising Error */ + HAL_CEC_ERROR_SBPE = CEC_ISR_SBPE, /*!< CEC Rx Short Bit period Error */ + HAL_CEC_ERROR_LBPE = CEC_ISR_LBPE, /*!< CEC Rx Long Bit period Error */ + HAL_CEC_ERROR_RXACKE = CEC_ISR_RXACKE, /*!< CEC Rx Missing Acknowledge */ + HAL_CEC_ERROR_ARBLST = CEC_ISR_ARBLST, /*!< CEC Arbitration Lost */ + HAL_CEC_ERROR_TXUDR = CEC_ISR_TXUDR, /*!< CEC Tx-Buffer Underrun */ + HAL_CEC_ERROR_TXERR = CEC_ISR_TXERR, /*!< CEC Tx-Error */ + HAL_CEC_ERROR_TXACKE = CEC_ISR_TXACKE /*!< CEC Tx Missing Acknowledge */ +} +HAL_CEC_ErrorTypeDef; + +/** + * @brief CEC handle Structure definition + */ +typedef struct +{ + CEC_TypeDef *Instance; /* CEC registers base address */ + + CEC_InitTypeDef Init; /* CEC communication parameters */ + + uint8_t *pTxBuffPtr; /* Pointer to CEC Tx transfer Buffer */ + + uint16_t TxXferCount; /* CEC Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /* Pointer to CEC Rx transfer Buffer */ + + uint16_t RxXferSize; /* CEC Rx Transfer size, 0: header received only */ + + uint32_t ErrorCode; /* For errors handling purposes, copy of ISR register + in case error is reported */ + + HAL_LockTypeDef Lock; /* Locking object */ + + HAL_CEC_StateTypeDef State; /* CEC communication state */ + +}CEC_HandleTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CEC_Exported_Constants CEC Exported Constants + * @{ + */ + +/** @defgroup CEC_Signal_Free_Time Signal Free Time setting parameter + * @{ + */ +#define CEC_DEFAULT_SFT ((uint32_t)0x00000000) +#define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001) +#define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002) +#define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003) +#define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004) +#define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005) +#define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006) +#define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007) +#define IS_CEC_SIGNALFREETIME(SFT) ((SFT) <= CEC_CFGR_SFT) +/** + * @} + */ + +/** @defgroup CEC_Tolerance Receiver Tolerance + * @{ + */ +#define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000) +#define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL) +#define IS_CEC_TOLERANCE(RXTOL) (((RXTOL) == CEC_STANDARD_TOLERANCE) || \ + ((RXTOL) == CEC_EXTENDED_TOLERANCE)) +/** + * @} + */ + +/** @defgroup CEC_BRERxStop Reception Stop on Error + * @{ + */ +#define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000) +#define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP) +#define IS_CEC_BRERXSTOP(BRERXSTOP) (((BRERXSTOP) == CEC_NO_RX_STOP_ON_BRE) || \ + ((BRERXSTOP) == CEC_RX_STOP_ON_BRE)) +/** + * @} + */ + +/** @defgroup CEC_BREErrorBitGen Error Bit Generation if Bit Rise Error reported + * @{ + */ +#define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000) +#define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN) +#define IS_CEC_BREERRORBITGEN(ERRORBITGEN) (((ERRORBITGEN) == CEC_BRE_ERRORBIT_NO_GENERATION) || \ + ((ERRORBITGEN) == CEC_BRE_ERRORBIT_GENERATION)) +/** + * @} + */ + +/** @defgroup CEC_LBPEErrorBitGen Error Bit Generation if Long Bit Period Error reported + * @{ + */ +#define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000) +#define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN) +#define IS_CEC_LBPEERRORBITGEN(ERRORBITGEN) (((ERRORBITGEN) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \ + ((ERRORBITGEN) == CEC_LBPE_ERRORBIT_GENERATION)) +/** + * @} + */ + +/** @defgroup CEC_BroadCastMsgErrorBitGen Error Bit Generation on Broadcast message + * @{ + */ +#define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000) +#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN) +#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(ERRORBITGEN) (((ERRORBITGEN) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \ + ((ERRORBITGEN) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION)) +/** + * @} + */ + +/** @defgroup CEC_SFT_Option Signal Free Time start option + * @{ + */ +#define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000) +#define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT) +#define IS_CEC_SFTOP(SFTOP) (((SFTOP) == CEC_SFT_START_ON_TXSOM) || \ + ((SFTOP) == CEC_SFT_START_ON_TX_RX_END)) +/** + * @} + */ + +/** @defgroup CEC_Listening_Mode Listening mode option + * @{ + */ +#define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000) +#define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN) +#define IS_CEC_LISTENING_MODE(MODE) (((MODE) == CEC_REDUCED_LISTENING_MODE) || \ + ((MODE) == CEC_FULL_LISTENING_MODE)) +/** + * @} + */ + +/** @defgroup CEC_ALL_ERROR all RX or TX errors flags in CEC ISR register + * @{ + */ +#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\ + CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE) +/** + * @} + */ + +/** @defgroup CEC_IER_ALL_RX all RX errors interrupts enabling flag + * @{ + */ +#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE) +/** + * @} + */ + +/** @defgroup CEC_IER_ALL_TX all TX errors interrupts enabling flag + * @{ + */ +#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE) +/** + * @} + */ + +/** @defgroup CEC_OAR_Position Device Own Address position in CEC CFGR register + * @{ + */ +#define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16) +/** + * @} + */ + +/** @defgroup CEC_Initiator_Position Initiator logical address position in message header + * @{ + */ +#define CEC_INITIATOR_LSB_POS ((uint32_t) 4) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup CEC_Exported_Macros CEC Exported Macros + * @{ + */ + +/** @brief Reset CEC handle state + * @param __HANDLE__: CEC handle. + * @retval None + */ +#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CEC_STATE_RESET) + +/** @brief Checks whether or not the specified CEC interrupt flag is set. + * @param __HANDLE__: specifies the CEC Handle. + * @param __INTERRUPT__: specifies the interrupt to check. + * This parameter can be one of the following values: + * @arg CEC_ISR_RXBR : Rx-Byte Received + * @arg CEC_ISR_RXEND : End of Reception + * @arg CEC_ISR_RXOVR : Rx Overrun + * @arg CEC_ISR_BRE : Rx Bit Rising Error + * @arg CEC_ISR_SBPE : Rx Short Bit Period Error + * @arg CEC_ISR_LBPE : Rx Long Bit Period Error + * @arg CEC_ISR_RXACKE : Rx Missing Acknowledge + * @arg CEC_ISR_ARBLST : Arbitration lost + * @arg CEC_ISR_TXBR : Tx-Byte Request + * @arg CEC_ISR_TXEND : End of Transmission + * @arg CEC_ISR_TXUDR : Tx-buffer Underrun + * @arg CEC_ISR_TXERR : Tx Error + * @arg CEC_ISR_TXACKE : Tx Missing Acknowledge + * @retval ITStatus + */ +#define __HAL_CEC_GET_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->ISR & (__INTERRUPT__)) + +/** @brief Clears the interrupt or status flag when raised (write at 1) + * @param __HANDLE__: specifies the CEC Handle. + * @param __FLAG__: specifies the interrupt/status flag to clear. + * This parameter can be one of the following values: + * @arg CEC_ISR_RXBR : Rx-Byte Received + * @arg CEC_ISR_RXEND : End of Reception + * @arg CEC_ISR_RXOVR : Rx Overrun + * @arg CEC_ISR_BRE : Rx Bit Rising Error + * @arg CEC_ISR_SBPE : Rx Short Bit Period Error + * @arg CEC_ISR_LBPE : Rx Long Bit Period Error + * @arg CEC_ISR_RXACKE : Rx Missing Acknowledge + * @arg CEC_ISR_ARBLST : Arbitration lost + * @arg CEC_ISR_TXBR : Tx-Byte Request + * @arg CEC_ISR_TXEND : End of Transmission + * @arg CEC_ISR_TXUDR : Tx-buffer Underrun + * @arg CEC_ISR_TXERR : Tx Error + * @arg CEC_ISR_TXACKE : Tx Missing Acknowledge + * @retval none + */ +#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR = (__FLAG__)) + +/** @brief Enables the specified CEC interrupt. + * @param __HANDLE__: specifies the CEC Handle. + * @param __INTERRUPT__: specifies the CEC interrupt to enable. + * This parameter can be one of the following values: + * @arg CEC_IER_RXBRIE : Rx-Byte Received IT Enable + * @arg CEC_IER_RXENDIE : End Of Reception IT Enable + * @arg CEC_IER_RXOVRIE : Rx-Overrun IT Enable + * @arg CEC_IER_BREIE : Rx Bit Rising Error IT Enable + * @arg CEC_IER_SBPEIE : Rx Short Bit period Error IT Enable + * @arg CEC_IER_LBPEIE : Rx Long Bit period Error IT Enable + * @arg CEC_IER_RXACKEIE : Rx Missing Acknowledge IT Enable + * @arg CEC_IER_ARBLSTIE : Arbitration Lost IT Enable + * @arg CEC_IER_TXBRIE : Tx Byte Request IT Enable + * @arg CEC_IER_TXENDIE : End of Transmission IT Enable + * @arg CEC_IER_TXUDRIE : Tx-Buffer Underrun IT Enable + * @arg CEC_IER_TXERRIE : Tx-Error IT Enable + * @arg CEC_IER_TXACKEIE : Tx Missing Acknowledge IT Enable + * @retval none + */ +#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) + +/** @brief Disables the specified CEC interrupt. + * @param __HANDLE__: specifies the CEC Handle. + * @param __INTERRUPT__: specifies the CEC interrupt to disable. + * This parameter can be one of the following values: + * @arg CEC_IER_RXBRIE : Rx-Byte Received IT Enable + * @arg CEC_IER_RXENDIE : End Of Reception IT Enable + * @arg CEC_IER_RXOVRIE : Rx-Overrun IT Enable + * @arg CEC_IER_BREIE : Rx Bit Rising Error IT Enable + * @arg CEC_IER_SBPEIE : Rx Short Bit period Error IT Enable + * @arg CEC_IER_LBPEIE : Rx Long Bit period Error IT Enable + * @arg CEC_IER_RXACKEIE : Rx Missing Acknowledge IT Enable + * @arg CEC_IER_ARBLSTIE : Arbitration Lost IT Enable + * @arg CEC_IER_TXBRIE : Tx Byte Request IT Enable + * @arg CEC_IER_TXENDIE : End of Transmission IT Enable + * @arg CEC_IER_TXUDRIE : Tx-Buffer Underrun IT Enable + * @arg CEC_IER_TXERRIE : Tx-Error IT Enable + * @arg CEC_IER_TXACKEIE : Tx Missing Acknowledge IT Enable + * @retval none + */ +#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) + +/** @brief Checks whether or not the specified CEC interrupt is enabled. + * @param __HANDLE__: specifies the CEC Handle. + * @param __INTERRUPT__: specifies the CEC interrupt to check. + * This parameter can be one of the following values: + * @arg CEC_IER_RXBRIE : Rx-Byte Received IT Enable + * @arg CEC_IER_RXENDIE : End Of Reception IT Enable + * @arg CEC_IER_RXOVRIE : Rx-Overrun IT Enable + * @arg CEC_IER_BREIE : Rx Bit Rising Error IT Enable + * @arg CEC_IER_SBPEIE : Rx Short Bit period Error IT Enable + * @arg CEC_IER_LBPEIE : Rx Long Bit period Error IT Enable + * @arg CEC_IER_RXACKEIE : Rx Missing Acknowledge IT Enable + * @arg CEC_IER_ARBLSTIE : Arbitration Lost IT Enable + * @arg CEC_IER_TXBRIE : Tx Byte Request IT Enable + * @arg CEC_IER_TXENDIE : End of Transmission IT Enable + * @arg CEC_IER_TXUDRIE : Tx-Buffer Underrun IT Enable + * @arg CEC_IER_TXERRIE : Tx-Error IT Enable + * @arg CEC_IER_TXACKEIE : Tx Missing Acknowledge IT Enable + * @retval FlagStatus + */ +#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) + +/** @brief Enables the CEC device + * @param __HANDLE__: specifies the CEC Handle. + * @retval none + */ +#define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN) + +/** @brief Disables the CEC device + * @param __HANDLE__: specifies the CEC Handle. + * @retval none + */ +#define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN) + +/** @brief Set Transmission Start flag + * @param __HANDLE__: specifies the CEC Handle. + * @retval none + */ +#define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM) + +/** @brief Set Transmission End flag + * @param __HANDLE__: specifies the CEC Handle. + * @retval none + * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM. + */ +#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM) + +/** @brief Get Transmission Start flag + * @param __HANDLE__: specifies the CEC Handle. + * @retval FlagStatus + */ +#define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM) + +/** @brief Get Transmission End flag + * @param __HANDLE__: specifies the CEC Handle. + * @retval FlagStatus + */ +#define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM) + +/** @brief Clear OAR register + * @param __HANDLE__: specifies the CEC Handle. + * @retval none + */ +#define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR) + +/** @brief Set OAR register (without resetting previously set address in case of multi-address mode) + * To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand + * @param __HANDLE__: specifies the CEC Handle. + * @param __ADDRESS__: Own Address value (CEC logical address is identified by bit position) + * @retval none + */ +#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS) + +/** @brief Check CEC device Own Address Register (OAR) setting. + * OAR address is written in a 15-bit field within CEC_CFGR register. + * @param __ADDRESS__: CEC own address. + * @retval Test result (TRUE or FALSE). + */ +#define IS_CEC_OAR_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x07FFF) + +/** @brief Check CEC initiator or destination logical address setting. + * Initiator and destination addresses are coded over 4 bits. + * @param __ADDRESS__: CEC initiator or logical address. + * @retval Test result (TRUE or FALSE). + */ +#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF) + +/** @brief Check CEC message size. + * The message size is the payload size: without counting the header, + * it varies from 0 byte (ping operation, one header only, no payload) to + * 15 bytes (1 opcode and up to 14 operands following the header). + * @param __SIZE__: CEC message size. + * @retval Test result (TRUE or FALSE). + */ +#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0xF) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CEC_Exported_Functions CEC Exported Functions + * @{ + */ +/** @addtogroup CEC_Exported_Functions_Group1 Initialization/de-initialization function + * @brief Initialization and Configuration functions + * @{ + */ +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec); +HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec); +void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec); +void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec); +/** + * @} + */ + +/** @addtogroup CEC_Exported_Functions_Group2 IO operation function + * @brief CEC Transmit/Receive functions + * @{ + */ +/* I/O operation functions ***************************************************/ +HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout); +HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size); +HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData); +void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec); +void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec); +void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec); +void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec); +/** + * @} + */ + +/** @addtogroup CEC_Exported_Functions_Group3 Peripheral Control function + * @brief CEC control functions + * @{ + */ +/* Peripheral State functions ************************************************/ +HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec); +uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(STM32F042x6) || defined(STM32F048xx) || */ + /* defined(STM32F051x8) || defined(STM32F058xx) || */ + /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || */ + /* defined(STM32F091xC) || defined(STM32F098xx) */ +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_CEC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_comp.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_comp.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_comp.h @@ -0,0 +1,478 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_comp.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Header file of COMP HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_COMP_H +#define __STM32F0xx_HAL_COMP_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(STM32F051x8) || defined(STM32F058xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup COMP COMP HAL Module Driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup COMP_Exported_Types COMP Exported Types + * @{ + */ + +/** + * @brief COMP Init structure definition + */ +typedef struct +{ + + uint32_t InvertingInput; /*!< Selects the inverting input of the comparator. + This parameter can be a value of @ref COMP_InvertingInput */ + + uint32_t NonInvertingInput; /*!< Selects the non inverting input of the comparator. + This parameter can be a value of @ref COMP_NonInvertingInput */ + + uint32_t Output; /*!< Selects the output redirection of the comparator. + This parameter can be a value of @ref COMP_Output */ + + uint32_t OutputPol; /*!< Selects the output polarity of the comparator. + This parameter can be a value of @ref COMP_OutputPolarity */ + + uint32_t Hysteresis; /*!< Selects the hysteresis voltage of the comparator. + This parameter can be a value of @ref COMP_Hysteresis */ + + uint32_t Mode; /*!< Selects the operating comsumption mode of the comparator + to adjust the speed/consumption. + This parameter can be a value of @ref COMP_Mode */ + + uint32_t WindowMode; /*!< Selects the window mode of the comparator 1 & 2. + This parameter can be a value of @ref COMP_WindowMode */ + + uint32_t TriggerMode; /*!< Selects the trigger mode of the comparator (interrupt mode). + This parameter can be a value of @ref COMP_TriggerMode */ + +}COMP_InitTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_COMP_STATE_RESET = 0x00, /*!< COMP not yet initialized or disabled */ + HAL_COMP_STATE_READY = 0x01, /*!< COMP initialized and ready for use */ + HAL_COMP_STATE_READY_LOCKED = 0x11, /*!< COMP initialized but the configuration is locked */ + HAL_COMP_STATE_BUSY = 0x02, /*!< COMP is running */ + HAL_COMP_STATE_BUSY_LOCKED = 0x12 /*!< COMP is running and the configuration is locked */ +}HAL_COMP_StateTypeDef; + +/** + * @brief COMP Handle Structure definition + */ +typedef struct +{ + COMP_TypeDef *Instance; /*!< Register base address */ + COMP_InitTypeDef Init; /*!< COMP required parameters */ + HAL_LockTypeDef Lock; /*!< Locking object */ + __IO HAL_COMP_StateTypeDef State; /*!< COMP communication state */ +}COMP_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup COMP_Exported_Constants COMP Exported Constants + * @{ + */ + +/** @defgroup COMP_OutputPolarity COMP OutputPolarity + * @{ + */ +#define COMP_OUTPUTPOL_NONINVERTED ((uint32_t)0x00000000) /*!< COMP output on GPIO isn't inverted */ +#define COMP_OUTPUTPOL_INVERTED COMP_CSR_COMP1POL /*!< COMP output on GPIO is inverted */ + +#define IS_COMP_OUTPUTPOL(POL) (((POL) == COMP_OUTPUTPOL_NONINVERTED) || \ + ((POL) == COMP_OUTPUTPOL_INVERTED)) +/** + * @} + */ + +/** @defgroup COMP_Hysteresis COMP Hysteresis + * @{ + */ +#define COMP_HYSTERESIS_NONE ((uint32_t)0x00000000) /*!< No hysteresis */ +#define COMP_HYSTERESIS_LOW COMP_CSR_COMP1HYST_0 /*!< Hysteresis level low */ +#define COMP_HYSTERESIS_MEDIUM COMP_CSR_COMP1HYST_1 /*!< Hysteresis level medium */ +#define COMP_HYSTERESIS_HIGH COMP_CSR_COMP1HYST /*!< Hysteresis level high */ + +#define IS_COMP_HYSTERESIS(HYSTERESIS) (((HYSTERESIS) == COMP_HYSTERESIS_NONE) || \ + ((HYSTERESIS) == COMP_HYSTERESIS_LOW) || \ + ((HYSTERESIS) == COMP_HYSTERESIS_MEDIUM) || \ + ((HYSTERESIS) == COMP_HYSTERESIS_HIGH)) +/** + * @} + */ + +/** @defgroup COMP_Mode COMP Mode + * @{ + */ +/* Please refer to the electrical characteristics in the device datasheet for + the power consumption values */ +#define COMP_MODE_HIGHSPEED ((uint32_t)0x00000000) /*!< High Speed */ +#define COMP_MODE_MEDIUMSPEED COMP_CSR_COMP1MODE_0 /*!< Medium Speed */ +#define COMP_MODE_LOWPOWER COMP_CSR_COMP1MODE_1 /*!< Low power mode */ +#define COMP_MODE_ULTRALOWPOWER COMP_CSR_COMP1MODE /*!< Ultra-low power mode */ + +#define IS_COMP_MODE(MODE) (((MODE) == COMP_MODE_HIGHSPEED) || \ + ((MODE) == COMP_MODE_MEDIUMSPEED) || \ + ((MODE) == COMP_MODE_LOWPOWER) || \ + ((MODE) == COMP_MODE_ULTRALOWPOWER)) + +/** + * @} + */ + +/** @defgroup COMP_InvertingInput COMP InvertingInput + * @{ + */ + +#define COMP_INVERTINGINPUT_1_4VREFINT ((uint32_t)0x00000000) /*!< 1/4 VREFINT connected to comparator inverting input */ +#define COMP_INVERTINGINPUT_1_2VREFINT COMP_CSR_COMP1INSEL_0 /*!< 1/2 VREFINT connected to comparator inverting input */ +#define COMP_INVERTINGINPUT_3_4VREFINT COMP_CSR_COMP1INSEL_1 /*!< 3/4 VREFINT connected to comparator inverting input */ +#define COMP_INVERTINGINPUT_VREFINT (COMP_CSR_COMP1INSEL_1|COMP_CSR_COMP1INSEL_0) /*!< VREFINT connected to comparator inverting input */ +#define COMP_INVERTINGINPUT_DAC1 COMP_CSR_COMP1INSEL_2 /*!< DAC_OUT1 (PA4) connected to comparator inverting input */ +#define COMP_INVERTINGINPUT_DAC1SWITCHCLOSED (COMP_CSR_COMP1INSEL_2|COMP_CSR_COMP1SW1) /*!< DAC_OUT1 (PA4) connected to comparator inverting input + and close switch (PA0 for COMP1 only) */ +#define COMP_INVERTINGINPUT_DAC2 (COMP_CSR_COMP1INSEL_2|COMP_CSR_COMP1INSEL_0) /*!< DAC_OUT2 (PA5) connected to comparator inverting input */ +#define COMP_INVERTINGINPUT_IO1 (COMP_CSR_COMP1INSEL_2|COMP_CSR_COMP1INSEL_1) /*!< IO (PA0 for COMP1 and PA2 for COMP2) connected to comparator inverting input */ + +#define IS_COMP_INVERTINGINPUT(INPUT) (((INPUT) == COMP_INVERTINGINPUT_1_4VREFINT) || \ + ((INPUT) == COMP_INVERTINGINPUT_1_2VREFINT) || \ + ((INPUT) == COMP_INVERTINGINPUT_3_4VREFINT) || \ + ((INPUT) == COMP_INVERTINGINPUT_VREFINT) || \ + ((INPUT) == COMP_INVERTINGINPUT_DAC1) || \ + ((INPUT) == COMP_INVERTINGINPUT_DAC1SWITCHCLOSED) || \ + ((INPUT) == COMP_INVERTINGINPUT_DAC2) || \ + ((INPUT) == COMP_INVERTINGINPUT_IO1)) +/** + * @} + */ + +/** @defgroup COMP_NonInvertingInput COMP NonInvertingInput + * @{ + */ +#define COMP_NONINVERTINGINPUT_IO1 ((uint32_t)0x00000000) /*!< I/O1 (PA1 for COMP1, PA3 for COMP2) + connected to comparator non inverting input */ +#define COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED COMP_CSR_COMP1SW1 /*!< DAC ouput connected to comparator COMP1 non inverting input */ + +#define IS_COMP_NONINVERTINGINPUT(INPUT) (((INPUT) == COMP_NONINVERTINGINPUT_IO1) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED)) +/** + * @} + */ + +/** @defgroup COMP_Output COMP Output + * @{ + */ + +/* Output Redirection common for COMP1 and COMP2 */ +#define COMP_OUTPUT_NONE ((uint32_t)0x00000000) /*!< COMP output isn't connected to other peripherals */ +#define COMP_OUTPUT_TIM1BKIN COMP_CSR_COMP1OUTSEL_0 /*!< COMP output connected to TIM1 Break Input (BKIN) */ +#define COMP_OUTPUT_TIM1IC1 COMP_CSR_COMP1OUTSEL_1 /*!< COMP output connected to TIM1 Input Capture 1 */ +#define COMP_OUTPUT_TIM1OCREFCLR (COMP_CSR_COMP1OUTSEL_1|COMP_CSR_COMP1OUTSEL_0) /*!< COMP output connected to TIM1 OCREF Clear */ +#define COMP_OUTPUT_TIM2IC4 COMP_CSR_COMP1OUTSEL_2 /*!< COMP output connected to TIM2 Input Capture 4 */ +#define COMP_OUTPUT_TIM2OCREFCLR (COMP_CSR_COMP1OUTSEL_2|COMP_CSR_COMP1OUTSEL_0) /*!< COMP output connected to TIM2 OCREF Clear */ +#define COMP_OUTPUT_TIM3IC1 (COMP_CSR_COMP1OUTSEL_2|COMP_CSR_COMP1OUTSEL_1) /*!< COMP output connected to TIM3 Input Capture 1 */ +#define COMP_OUTPUT_TIM3OCREFCLR COMP_CSR_COMP1OUTSEL /*!< COMP output connected to TIM3 OCREF Clear */ + +#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OUTPUT_NONE) || \ + ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \ + ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \ + ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \ + ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \ + ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \ + ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \ + ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR)) + +/** + * @} + */ + +/** @defgroup COMP_OutputLevel COMP OutputLevel + * @{ + */ +/* When output polarity is not inverted, comparator output is low when + the non-inverting input is at a lower voltage than the inverting input*/ +#define COMP_OUTPUTLEVEL_LOW ((uint32_t)0x00000000) +/* When output polarity is not inverted, comparator output is high when + the non-inverting input is at a higher voltage than the inverting input */ +#define COMP_OUTPUTLEVEL_HIGH COMP_CSR_COMP1OUT +/** + * @} + */ + +/** @defgroup COMP_TriggerMode COMP TriggerMode + * @{ + */ +#define COMP_TRIGGERMODE_NONE ((uint32_t)0x00000000) /*!< No External Interrupt trigger detection */ +#define COMP_TRIGGERMODE_IT_RISING ((uint32_t)0x00000001) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define COMP_TRIGGERMODE_IT_FALLING ((uint32_t)0x00000002) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define COMP_TRIGGERMODE_IT_RISING_FALLING ((uint32_t)0x00000003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ + +#define IS_COMP_TRIGGERMODE(MODE) (((MODE) == COMP_TRIGGERMODE_NONE) || \ + ((MODE) == COMP_TRIGGERMODE_IT_RISING) || \ + ((MODE) == COMP_TRIGGERMODE_IT_FALLING) || \ + ((MODE) == COMP_TRIGGERMODE_IT_RISING_FALLING)) +/** + * @} + */ + +/** @defgroup COMP_WindowMode COMP WindowMode + * @{ + */ +#define COMP_WINDOWMODE_DISABLED ((uint32_t)0x00000000) /*!< Window mode disabled */ +#define COMP_WINDOWMODE_ENABLED COMP_CSR_WNDWEN /*!< Window mode enabled: non inverting input of comparator 2 + is connected to the non inverting input of comparator 1 (PA1) */ + +#define IS_COMP_WINDOWMODE(WINDOWMODE) (((WINDOWMODE) == COMP_WINDOWMODE_DISABLED) || \ + ((WINDOWMODE) == COMP_WINDOWMODE_ENABLED)) +/** + * @} + */ + +/** @defgroup COMP_ExtiLineEvent COMP ExtiLineEvent + * Elements values convention: XXXX0000 + * - XXXX : Interrupt mask in the EMR/IMR/RTSR/FTSR register + * @{ + */ +#define COMP_EXTI_LINE_COMP1_EVENT ((uint32_t)0x00200000) /*!< External interrupt line 21 Connected to COMP1 */ +#define COMP_EXTI_LINE_COMP2_EVENT ((uint32_t)0x00400000) /*!< External interrupt line 22 Connected to COMP2 */ + +/** + * @} + */ + +/** @defgroup COMP_Lock COMP Lock + * @{ + */ +#define COMP_LOCK_DISABLE ((uint32_t)0x00000000) +#define COMP_LOCK_ENABLE COMP_CSR_COMP1LOCK + +#define COMP_STATE_BIT_LOCK ((uint32_t)0x10) +/** + * @} + */ + + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup COMP_Exported_Macros COMP Exported Macros + * @{ + */ + +/** @brief Reset COMP handle state + * @param __HANDLE__: COMP handle. + * @retval None + */ +#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET) + +/** + * @brief Checks whether the specified EXTI line flag is set or not. + * @param __FLAG__: specifies the COMP Exti sources to be checked. + * This parameter can be a value of @ref COMP_ExtiLineEvent + * @retval The state of __FLAG__ (SET or RESET). + */ +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (EXTI->PR & (__FLAG__)) + +/** + * @brief Clear the COMP Exti flags. + * @param __FLAG__: specifies the COMP Exti sources to be cleared. + * This parameter can be a value of @ref COMP_ExtiLineEvent + * @retval None. + */ +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (EXTI->PR = (__FLAG__)) + +/** + * @brief Enable the COMP Exti Line. + * @param __EXTILINE__: specifies the COMP Exti sources to be enabled. + * This parameter can be a value of @ref COMP_ExtiLineEvent + * @retval None. + */ +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (EXTI->IMR |= (__EXTILINE__)) + +/** + * @brief Disable the COMP Exti Line. + * @param __EXTILINE__: specifies the COMP Exti sources to be disabled. + * This parameter can be a value of @ref COMP_ExtiLineEvent + * @retval None. + */ +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (EXTI->IMR &= ~(__EXTILINE__)) + +/** + * @brief Enable the Exti Line rising edge trigger. + * @param __EXTILINE__: specifies the COMP Exti sources to be enabled. + * This parameter can be a value of @ref COMP_ExtiLineEvent + * @retval None. + */ +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (EXTI->RTSR |= (__EXTILINE__)) + +/** + * @brief Disable the Exti Line rising edge trigger. + * @param __EXTILINE__: specifies the COMP Exti sources to be disabled. + * This parameter can be a value of @ref COMP_ExtiLineEvent + * @retval None. + */ +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (EXTI->RTSR &= ~(__EXTILINE__)) + +/** + * @brief Enable the Exti Line falling edge trigger. + * @param __EXTILINE__: specifies the COMP Exti sources to be enabled. + * This parameter can be a value of @ref COMP_ExtiLineEvent + * @retval None. + */ +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (EXTI->FTSR |= (__EXTILINE__)) + +/** + * @brief Disable the Exti Line falling edge trigger. + * @param __EXTILINE__: specifies the COMP Exti sources to be disabled. + * This parameter can be a value of @ref COMP_ExtiLineEvent + * @retval None. + */ +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (EXTI->FTSR &= ~(__EXTILINE__)) + +/** + * @brief Get the specified EXTI line for a comparator instance + * @param __INSTANCE__: specifies the COMP instance. + * @retval value of @ref COMP_ExtiLineEvent + */ +#define __HAL_COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1_EVENT : \ + COMP_EXTI_LINE_COMP2_EVENT) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup COMP_Exported_Functions COMP Exported Functions + * @{ + */ +/** @addtogroup COMP_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * @{ + */ +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp); +HAL_StatusTypeDef HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp); +void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp); +void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp); +/** + * @} + */ + +/** @addtogroup COMP_Exported_Functions_Group2 I/O operation functions + * @brief Data transfers functions + * @{ + */ +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp); +HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp); +HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp); +HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp); +void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp); +/** + * @} + */ + +/** @addtogroup COMP_Exported_Functions_Group3 Peripheral Control functions + * @brief management functions + * @{ + */ +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp); +uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp); + +/* Callback in Interrupt mode */ +void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp); +/** + * @} + */ + +/** @addtogroup COMP_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_COMP_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_conf_template.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_conf_template.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_conf_template.h @@ -0,0 +1,307 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_conf_template.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_CONF_H +#define __STM32F0xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +#define HAL_ADC_MODULE_ENABLED +#define HAL_CAN_MODULE_ENABLED +#define HAL_CEC_MODULE_ENABLED +#define HAL_COMP_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED +#define HAL_CRC_MODULE_ENABLED +#define HAL_DAC_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_GPIO_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +#define HAL_I2S_MODULE_ENABLED +#define HAL_IRDA_MODULE_ENABLED +#define HAL_IWDG_MODULE_ENABLED +#define HAL_PCD_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_RTC_MODULE_ENABLED +#define HAL_SMARTCARD_MODULE_ENABLED +#define HAL_SMBUS_MODULE_ENABLED +#define HAL_SPI_MODULE_ENABLED +#define HAL_TIM_MODULE_ENABLED +#define HAL_TSC_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +#define HAL_USART_MODULE_ENABLED +#define HAL_WWDG_MODULE_ENABLED + +/* ######################### Oscillator Values adaptation ################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +/** + * @brief In the following line adjust the External High Speed oscillator (HSE) Startup + * Timeout value + */ +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup + * Timeout value + */ +#if !defined (HSI_STARTUP_TIMEOUT) + #define HSI_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSI start up */ +#endif /* HSI_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator for ADC (HSI14) value. + */ +#if !defined (HSI14_VALUE) +#define HSI14_VALUE ((uint32_t)14000000) /*!< Value of the Internal High Speed oscillator for ADC in Hz. + The real value may vary depending on the variations + in voltage and temperature. */ +#endif /* HSI14_VALUE */ + +/** + * @brief Internal High Speed oscillator for USB (HSI48) value. + */ +#if !defined (HSI48_VALUE) +#define HSI48_VALUE ((uint32_t)48000000) /*!< Value of the Internal High Speed oscillator for USB in Hz. + The real value may vary depending on the variations + in voltage and temperature. */ +#endif /* HSI48_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)40000) +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)(1<<__NVIC_PRIO_BITS) - 1) /*!< tick interrupt priority (lowest by default) */ + /* Warning: Must be set to higher priority for HAL_Delay() */ + /* and HAL_GetTick() usage under interrupt context */ +#define USE_RTOS 0 +#define PREFETCH_ENABLE 1 +#define INSTRUCTION_CACHE_ENABLE 0 +#define DATA_CACHE_ENABLE 0 + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/*#define USE_FULL_ASSERT 1*/ + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f0xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f0xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f0xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f0xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f0xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f0xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32f0xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_COMP_MODULE_ENABLED + #include "stm32f0xx_hal_comp.h" +#endif /* HAL_COMP_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f0xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f0xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f0xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f0xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f0xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f0xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f0xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f0xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f0xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f0xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f0xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32f0xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f0xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f0xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_TSC_MODULE_ENABLED + #include "stm32f0xx_hal_tsc.h" +#endif /* HAL_TSC_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f0xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f0xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f0xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_CONF_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h @@ -0,0 +1,166 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_cortex.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Header file of CORTEX HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_CORTEX_H +#define __STM32F0xx_HAL_CORTEX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup CORTEX CORTEX HAL module driver + * @{ + */ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_Priority CORTEX Priority + * @{ + */ +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x4) +/** + * @} + */ + +/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source + * @{ + */ +#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000) +#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004) +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ + ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported Macros -----------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Macro CORTEX Exported Macro + * @{ + */ + +/** @brief Configures the SysTick clock source. + * @param __CLKSRC__: specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. + * @retval None + */ +#define __HAL_CORTEX_SYSTICKCLK_CONFIG(__CLKSRC__) \ + do { \ + if ((__CLKSRC__) == SYSTICK_CLKSOURCE_HCLK) \ + { \ + SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; \ + } \ + else \ + SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; \ + } while(0) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CORTEX_Exported_Functions CORTEX Exported Functions + * @{ + */ +/** @addtogroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * @{ + */ +/* Initialization and de-initialization functions *******************************/ +void HAL_NVIC_SetPriority(IRQn_Type IRQn,uint32_t PreemptPriority, uint32_t SubPriority); +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); +void HAL_NVIC_SystemReset(void); +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); +/** + * @} + */ + +/** @addtogroup CORTEX_Exported_Functions_Group2 Peripheral Control functions + * @brief Cortex control functions + * @{ + */ + +/* Peripheral Control functions *************************************************/ +uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn); +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); +void HAL_SYSTICK_IRQHandler(void); +void HAL_SYSTICK_Callback(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_CORTEX_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_crc.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_crc.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_crc.h @@ -0,0 +1,327 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_crc.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Header file of CRC HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_CRC_H +#define __STM32F0xx_HAL_CRC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup CRC CRC HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CRC_Exported_Types CRC Exported Types + * @{ + */ +/** + * @brief CRC HAL State Structure definition + */ +typedef enum +{ + HAL_CRC_STATE_RESET = 0x00, /*!< CRC not yet initialized or disabled */ + HAL_CRC_STATE_READY = 0x01, /*!< CRC initialized and ready for use */ + HAL_CRC_STATE_BUSY = 0x02, /*!< CRC internal process is ongoing */ + HAL_CRC_STATE_TIMEOUT = 0x03, /*!< CRC timeout state */ + HAL_CRC_STATE_ERROR = 0x04 /*!< CRC error state */ +}HAL_CRC_StateTypeDef; + + +/** + * @brief CRC Init Structure definition + */ +typedef struct +{ + uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used. + If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default + X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1. + In that case, there is no need to set GeneratingPolynomial field. + If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set */ + + uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used. + If set to DEFAULT_INIT_VALUE_ENABLE, resort to default + 0xFFFFFFFF value. In that case, there is no need to set InitValue field. + If otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set */ + + uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial. 7, 8, 16 or 32-bit long value for a polynomial degree + respectively equal to 7, 8, 16 or 32. This field is written in normal representation, + e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65. + No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE */ + + uint32_t CRCLength; /*!< This parameter is a value of @ref CRCEx_Polynomial_Size_Definitions and indicates CRC length. + Value can be either one of + CRC_POLYLENGTH_32B (32-bit CRC) + CRC_POLYLENGTH_16B (16-bit CRC) + CRC_POLYLENGTH_8B (8-bit CRC) + CRC_POLYLENGTH_7B (7-bit CRC) */ + + uint32_t InitValue; /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse + is set to DEFAULT_INIT_VALUE_ENABLE */ + + uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode. + Can be either one of the following values + CRC_INPUTDATA_INVERSION_NONE no input data inversion + CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2 + CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C + CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */ + + uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode. + Can be either + CRC_OUTPUTDATA_INVERSION_DISABLED no CRC inversion, or + CRC_OUTPUTDATA_INVERSION_ENABLED CRC 0x11223344 is converted into 0x22CC4488 */ +}CRC_InitTypeDef; + + +/** + * @brief CRC Handle Structure definition + */ +typedef struct +{ + CRC_TypeDef *Instance; /*!< Register base address */ + + CRC_InitTypeDef Init; /*!< CRC configuration parameters */ + + HAL_LockTypeDef Lock; /*!< CRC Locking object */ + + __IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */ + + uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format. + Can be either + CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes (8-bit data) + CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of half-words (16-bit data) + CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words (32-bits data) + Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error + must occur if InputBufferFormat is not one of the three values listed above */ +}CRC_HandleTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CRC_Exported_Constants CRC Exported Constants + * @{ + */ +/** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial + * @{ + */ +#define DEFAULT_CRC32_POLY 0x04C11DB7 + +/** + * @} + */ + +/** @defgroup CRC_Default_InitValue Default CRC computation initialization value + * @{ + */ +#define DEFAULT_CRC_INITVALUE 0xFFFFFFFF + +/** + * @} + */ + +/** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used + * @{ + */ +#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00) +#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01) + +#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \ + ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE)) + +/** + * @} + */ + +/** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used + * @{ + */ +#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00) +#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01) + +#define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \ + ((VALUE) == DEFAULT_INIT_VALUE_DISABLE)) +/** + * @} + */ + +/** @defgroup CRC_Input_Buffer_Format Input Buffer Format + * @{ + */ +/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but + * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set + * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for + * the CRC APIs to provide a correct result */ +#define CRC_INPUTDATA_FORMAT_UNDEFINED ((uint32_t)0x00000000) +#define CRC_INPUTDATA_FORMAT_BYTES ((uint32_t)0x00000001) +#define CRC_INPUTDATA_FORMAT_HALFWORDS ((uint32_t)0x00000002) +#define CRC_INPUTDATA_FORMAT_WORDS ((uint32_t)0x00000003) + +#define IS_CRC_INPUTDATA_FORMAT(FORMAT) (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES) || \ + ((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \ + ((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup CRC_Exported_Macros CRC Exported Macros + * @{ + */ + +/** @brief Reset CRC handle state + * @param __HANDLE__: CRC handle. + * @retval None + */ +#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET) + +/** + * @brief Reset CRC Data Register. + * @param __HANDLE__: CRC handle + * @retval None. + */ +#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET) + +/** + * @brief Set CRC INIT non-default value + * @param __HANDLE__ : CRC handle + * @param __INIT__ : 32-bit initial value + * @retval None. + */ +#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__)) + +/** + * @} + */ + + +/* Include CRC HAL Extension module */ +#include "stm32f0xx_hal_crc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CRC_Exported_Functions CRC Exported Functions + * @{ + */ + +/** @addtogroup CRC_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions. + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc); +HAL_StatusTypeDef HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc); +void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc); +void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc); +/** + * @} + */ + +/** @addtogroup CRC_Exported_Functions_Group2 Peripheral Control functions + * @brief management functions. + * @{ + */ + +/* Peripheral Control functions ***********************************************/ +uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength); +uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength); +/** + * @} + */ + +/** @addtogroup CRC_Exported_Functions_Group3 Peripheral State functions + * @brief Peripheral State functions. + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc); +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup CRC_Exported_Constants CRC Exported Constants + * @brief aliases for inter STM32 series compatibility + * @{ + */ +/** @defgroup CRC_Aliases Aliases for inter STM32 series compatibility + * @{ + */ +/* Aliases for inter STM32 series compatibility */ +#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse +#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_CRC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_crc_ex.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_crc_ex.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_crc_ex.h @@ -0,0 +1,194 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_crc_ex.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Header file of CRC HAL extension module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_CRC_EX_H +#define __STM32F0xx_HAL_CRC_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup CRCEx CRCEx Extended HAL Module Driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CRCEx_Exported_Constants CRCEx Exported Constants + * @{ + */ +/** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes + * @{ + */ +#define CRC_INPUTDATA_INVERSION_NONE ((uint32_t)0x00000000) +#define CRC_INPUTDATA_INVERSION_BYTE ((uint32_t)CRC_CR_REV_IN_0) +#define CRC_INPUTDATA_INVERSION_HALFWORD ((uint32_t)CRC_CR_REV_IN_1) +#define CRC_INPUTDATA_INVERSION_WORD ((uint32_t)CRC_CR_REV_IN) + +#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \ + ((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \ + ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \ + ((MODE) == CRC_INPUTDATA_INVERSION_WORD)) +/** + * @} + */ + +/** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes + * @{ + */ +#define CRC_OUTPUTDATA_INVERSION_DISABLED ((uint32_t)0x00000000) +#define CRC_OUTPUTDATA_INVERSION_ENABLED ((uint32_t)CRC_CR_REV_OUT) + +#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLED) || \ + ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLED)) +/** + * @} + */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) +/** @defgroup CRCEx_Polynomial_Sizes Polynomial sizes to configure the IP + * @{ + */ +#define CRC_POLYLENGTH_32B ((uint32_t)0x00000000) +#define CRC_POLYLENGTH_16B ((uint32_t)CRC_CR_POLYSIZE_0) +#define CRC_POLYLENGTH_8B ((uint32_t)CRC_CR_POLYSIZE_1) +#define CRC_POLYLENGTH_7B ((uint32_t)CRC_CR_POLYSIZE) +#define IS_CRC_POL_LENGTH(LENGTH) (((LENGTH) == CRC_POLYLENGTH_32B) || \ + ((LENGTH) == CRC_POLYLENGTH_16B) || \ + ((LENGTH) == CRC_POLYLENGTH_8B) || \ + ((LENGTH) == CRC_POLYLENGTH_7B)) +/** + * @} + */ + +/** @defgroup CRCEx_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions + * @{ + */ +#define HAL_CRC_LENGTH_32B 32 +#define HAL_CRC_LENGTH_16B 16 +#define HAL_CRC_LENGTH_8B 8 +#define HAL_CRC_LENGTH_7B 7 +/** + * @} + */ +#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */ +/** + * @} + */ +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup CRCEx_Exported_Macros CRCEx Exported Macros + * @{ + */ + +/** + * @brief Set CRC output reversal + * @param __HANDLE__ : CRC handle + * @retval None. + */ +#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT) + +/** + * @brief Unset CRC output reversal + * @param __HANDLE__ : CRC handle + * @retval None. + */ +#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT)) + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) +/** + * @brief Set CRC non-default polynomial + * @param __HANDLE__ : CRC handle + * @param __POLYNOMIAL__: 7, 8, 16 or 32-bit polynomial + * @retval None. + */ +#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__)) +#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CRCEx_Exported_Functions + * @{ + */ + +/** @addtogroup CRCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions + * @brief Extended Initialization and Configuration functions. + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_CRCEx_Init(CRC_HandleTypeDef *hcrc); +HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode); +HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode); + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) +HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength); +#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */ +/** + * @} + */ +/* Peripheral Control functions ***********************************************/ +/* Peripheral State and Error functions ***************************************/ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_CRC_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dac.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dac.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dac.h @@ -0,0 +1,354 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_dac.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Header file of DAC HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_DAC_H +#define __STM32F0xx_HAL_DAC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(STM32F051x8) || defined(STM32F058xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup DAC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup DAC_Exported_Types DAC Exported Types + * @{ + */ + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_DAC_STATE_RESET = 0x00, /*!< DAC not yet initialized or disabled */ + HAL_DAC_STATE_READY = 0x01, /*!< DAC initialized and ready for use */ + HAL_DAC_STATE_BUSY = 0x02, /*!< DAC internal processing is ongoing */ + HAL_DAC_STATE_TIMEOUT = 0x03, /*!< DAC timeout state */ + HAL_DAC_STATE_ERROR = 0x04 /*!< DAC error state */ + +}HAL_DAC_StateTypeDef; + +/** + * @brief DAC handle Structure definition + */ +typedef struct +{ + DAC_TypeDef *Instance; /*!< Register base address */ + + __IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */ + + HAL_LockTypeDef Lock; /*!< DAC locking object */ + + DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */ + + DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */ + + __IO uint32_t ErrorCode; /*!< DAC Error code */ + +}DAC_HandleTypeDef; + +/** + * @brief DAC Configuration regular Channel structure definition + */ +typedef struct +{ + uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. + This parameter can be a value of @ref DAC_trigger_selection */ + + uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. + This parameter can be a value of @ref DAC_output_buffer */ + +}DAC_ChannelConfTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DAC_Exported_Constants DAC Exported Constants + * @{ + */ + +/** @defgroup DAC_Error_Code DAC Error Code + * @{ + */ +#define HAL_DAC_ERROR_NONE 0x00 /*!< No error */ +#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01 /*!< DAC channel1 DAM underrun error */ +#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02 /*!< DAC channel2 DAM underrun error */ +#define HAL_DAC_ERROR_DMA 0x04 /*!< DMA error */ +/** + * @} + */ + +/** @defgroup DAC_output_buffer DAC output buffer + * @{ + */ +#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000) +#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1) + +#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \ + ((STATE) == DAC_OUTPUTBUFFER_DISABLE)) +/** + * @} + */ + +/** @defgroup DAC_data_alignement DAC data alignement + * @{ + */ +#define DAC_ALIGN_12B_R ((uint32_t)0x00000000) +#define DAC_ALIGN_12B_L ((uint32_t)0x00000004) +#define DAC_ALIGN_8B_R ((uint32_t)0x00000008) + +#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \ + ((ALIGN) == DAC_ALIGN_12B_L) || \ + ((ALIGN) == DAC_ALIGN_8B_R)) +/** + * @} + */ + +/** @defgroup DAC_data DAC data + * @{ + */ +#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) +/** + * @} + */ + +/** @defgroup DAC_flags_definition DAC flags definition + * @{ + */ +#define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1) +#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2) +/** + * @} + */ + +/** @defgroup DAC_IT_definition DAC IT definition + * @{ + */ +#define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1) +#define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup DAC_Exported_Macros DAC Exported Macros + * @{ + */ + +/** @brief Reset DAC handle state + * @param __HANDLE__: specifies the DAC handle. + * @retval None + */ +#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET) + +/** @brief Enable the DAC channel + * @param __HANDLE__: specifies the DAC handle. + * @param __DAC_Channel__: specifies the DAC channel + * @retval None + */ +#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \ +((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__))) + +/** @brief Disable the DAC channel + * @param __HANDLE__: specifies the DAC handle + * @param __DAC_Channel__: specifies the DAC channel. + * @retval None + */ +#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \ +((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__))) + +/** @brief Set DHR12R1 alignment + * @param __ALIGNEMENT__: specifies the DAC alignement + * @retval None + */ +#define __HAL_DHR12R1_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000008) + (__ALIGNEMENT__)) + +/** @brief Set DHR12R2 alignment + * @param __ALIGNEMENT__: specifies the DAC alignement + * @retval None + */ +#define __HAL_DHR12R2_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000014) + (__ALIGNEMENT__)) + +/** @brief Set DHR12RD alignment + * @param __ALIGNEMENT__: specifies the DAC alignement + * @retval None + */ +#define __HAL_DHR12RD_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000020) + (__ALIGNEMENT__)) + +/** @brief Enable the DAC interrupt + * @param __HANDLE__: specifies the DAC handle + * @param __INTERRUPT__: specifies the DAC interrupt. + * @retval None + */ +#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__)) + +/** @brief Disable the DAC interrupt + * @param __HANDLE__: specifies the DAC handle + * @param __INTERRUPT__: specifies the DAC interrupt. + * @retval None + */ +#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__)) + +/** @brief Get the selected DAC's flag status. + * @param __HANDLE__: specifies the DAC handle. + * @param __FLAG__: specifies the FLAG. + * @retval None + */ +#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the DAC's flag. + * @param __HANDLE__: specifies the DAC handle. + * @param __FLAG__: specifies the FLAG. + * @retval None + */ +#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__)) + +/** + * @} + */ + + +/* Include DAC HAL Extension module */ +#include "stm32f0xx_hal_dac_ex.h" + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup DAC_Exported_Functions + * @{ + */ + +/** @addtogroup DAC_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac); +HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac); +void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac); +void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac); + +/** + * @} + */ + +/** @addtogroup DAC_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel); +HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel); +HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment); +HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel); + +void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac); +void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac); +void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac); +void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac); +/** + * @} + */ + +/** @addtogroup DAC_Exported_Functions_Group3 + * @{ + */ +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data); +uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup DAC_Exported_Functions_Group4 + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac); +void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac); +uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#ifdef __cplusplus +} +#endif + + +#endif /*__STM32F0xx_HAL_DAC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dac_ex.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dac_ex.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dac_ex.h @@ -0,0 +1,297 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_dac_ex.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Header file of DAC HAL Extension module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_DAC_EX_H +#define __STM32F0xx_HAL_DAC_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(STM32F051x8) || defined(STM32F058xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup DACEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief HAL State structures definition + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DACEx_Exported_Constants DACEx Exported Constants + * @{ + */ +/** @defgroup DACEx_wave_generation DACEx wave generation + * @{ + */ +#define DAC_WAVEGENERATION_NONE ((uint32_t)0x00000000) +#define DAC_WAVEGENERATION_NOISE ((uint32_t)DAC_CR_WAVE1_0) +#define DAC_WAVEGENERATION_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1) + +#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WAVEGENERATION_NONE) || \ + ((WAVE) == DAC_WAVEGENERATION_NOISE) || \ + ((WAVE) == DAC_WAVEGENERATION_TRIANGLE)) +/** + * @} + */ + +/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangleamplitude + * @{ + */ +#define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ +#define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ +#define DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ +#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */ +#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */ +#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */ +#define DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */ +#define DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */ +#define DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */ +#define DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */ +#define DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */ +#define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */ +#define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */ +#define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */ + +#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095)) +/** + * @} + */ + +/** @defgroup DACEx_wave_generationbis DACEx wave generation bis + * @{ + */ +#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0) +#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1) + +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NOISE) || \ + ((WAVE) == DAC_WAVE_TRIANGLE)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup DACEx_Exported_Macros DACEx Exported Macros + * @{ + */ + +/** @defgroup DAC_trigger_selection DAC trigger selection + * @{ + */ +#if defined(STM32F051x8) || defined(STM32F058xx) + +#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register + has been loaded, and not by external trigger */ +#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */ + +#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \ + ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \ + ((TRIGGER) == DAC_TRIGGER_SOFTWARE)) + +#endif /* STM32F051x8 || STM32F058xx */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register + has been loaded, and not by external trigger */ +#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */ + +#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \ + ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \ + ((TRIGGER) == DAC_TRIGGER_SOFTWARE)) + +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ +/** + * @} + */ + +/** @defgroup DAC_Channel_selection DAC Channel selection + * @{ + */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +#define DAC_CHANNEL_1 ((uint32_t)0x00000000) +#define DAC_CHANNEL_2 ((uint32_t)0x00000010) + +#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \ + ((CHANNEL) == DAC_CHANNEL_2)) + +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F051x8) || defined(STM32F058xx) + +#define DAC_CHANNEL_1 ((uint32_t)0x00000000) +#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1)) + +#endif /* STM32F051x8 || STM32F058xx */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/* Extension features functions ***********************************************/ + +/** @addtogroup DACEx_Exported_Functions + * @{ + */ + +/** @addtogroup DACEx_Exported_Functions_Group1 Extended features functions + * @brief Extended features functions + * @{ + */ + +uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac); +HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude); +HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude); +HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2); + +void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac); +void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac); +void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac); +void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac); + +void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma); +void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma); +void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); +/** + * @} + */ + + /** + * @} + */ +#endif /* */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#endif /*__STM32F0xx_HAL_DAC_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h @@ -0,0 +1,164 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_def.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief This file contains HAL common defines, enumeration, macros and + * structures definitions. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_DEF +#define __STM32F0xx_HAL_DEF + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief HAL Status structures definition + */ +typedef enum +{ + HAL_OK = 0x00, + HAL_ERROR = 0x01, + HAL_BUSY = 0x02, + HAL_TIMEOUT = 0x03 +} HAL_StatusTypeDef; + +/** + * @brief HAL Lock structures definition + */ +typedef enum +{ + HAL_UNLOCKED = 0x00, + HAL_LOCKED = 0x01 +} HAL_LockTypeDef; + +/* Exported macro ------------------------------------------------------------*/ +#ifndef NULL + #define NULL (void *) 0 +#endif + +#define HAL_MAX_DELAY 0xFFFFFFFF + +#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET) +#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET) + +#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD_, __DMA_HANDLE_) \ + do{ \ + (__HANDLE__)->__PPP_DMA_FIELD_ = &(__DMA_HANDLE_); \ + (__DMA_HANDLE_).Parent = (__HANDLE__); \ + } while(0) + +/** @brief Reset the Handle's State field. + * @param __HANDLE__: specifies the Peripheral Handle. + * @note This macro can be used for the following purpose: + * - When the Handle is declared as local variable; before passing it as parameter + * to HAL_PPP_Init() for the first time, it is mandatory to use this macro + * to set to 0 the Handle's "State" field. + * Otherwise, "State" field may have any random value and the first time the function + * HAL_PPP_Init() is called, the low level hardware initialization will be missed + * (i.e. HAL_PPP_MspInit() will not be executed). + * - When there is a need to reconfigure the low level hardware: instead of calling + * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). + * In this later function, when the Handle's "State" field is set to 0, it will execute the function + * HAL_PPP_MspInit() which will reconfigure the low level hardware. + * @retval None + */ +#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0) + +#if (USE_RTOS == 1) + #error " USE_RTOS should be 0 in the current HAL release " +#else + #define __HAL_LOCK(__HANDLE__) \ + do{ \ + if((__HANDLE__)->Lock == HAL_LOCKED) \ + { \ + return HAL_BUSY; \ + } \ + else \ + { \ + (__HANDLE__)->Lock = HAL_LOCKED; \ + } \ + }while (0) + + #define __HAL_UNLOCK(__HANDLE__) \ + do{ \ + (__HANDLE__)->Lock = HAL_UNLOCKED; \ + }while (0) +#endif /* USE_RTOS */ + +#if defined ( __GNUC__ ) + #ifndef __weak + #define __weak __attribute__((weak)) + #endif /* __weak */ + #ifndef __packed + #define __packed __attribute__((__packed__)) + #endif /* __packed */ +#endif /* __GNUC__ */ + + +/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ +#if defined (__GNUC__) /* GNU Compiler */ + #ifndef __ALIGN_END + #define __ALIGN_END __attribute__ ((aligned (4))) + #endif /* __ALIGN_END */ + #ifndef __ALIGN_BEGIN + #define __ALIGN_BEGIN + #endif /* __ALIGN_BEGIN */ +#else + #ifndef __ALIGN_END + #define __ALIGN_END + #endif /* __ALIGN_END */ + #ifndef __ALIGN_BEGIN + #if defined (__CC_ARM) /* ARM Compiler */ + #define __ALIGN_BEGIN __align(4) + #elif defined (__ICCARM__) /* IAR Compiler */ + #define __ALIGN_BEGIN + #endif /* __CC_ARM */ + #endif /* __ALIGN_BEGIN */ +#endif /* __GNUC__ */ + +#ifdef __cplusplus +} +#endif + +#endif /* ___STM32F0xx_HAL_DEF */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h @@ -0,0 +1,459 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_dma.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Header file of DMA HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_DMA_H +#define __STM32F0xx_HAL_DMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup DMA_Exported_Types DMA Exported Types + * @{ + */ + +/** + * @brief DMA Configuration Structure definition + */ +typedef struct +{ + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_Data_transfer_direction */ + + uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. + This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ + + uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. + This parameter can be a value of @ref DMA_Memory_incremented_mode */ + + uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_Peripheral_data_size */ + + uint32_t MemDataAlignment; /*!< Specifies the Memory data width. + This parameter can be a value of @ref DMA_Memory_data_size */ + + uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of @ref DMA_mode + @note The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Channel */ + + uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. + This parameter can be a value of @ref DMA_Priority_level */ + +} DMA_InitTypeDef; + +/** + * @brief DMA Configuration enumeration values definition + */ +typedef enum +{ + DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */ + DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */ + +} DMA_ControlTypeDef; + +/** + * @brief HAL DMA State structures definition + */ +typedef enum +{ + HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */ + HAL_DMA_STATE_READY = 0x01, /*!< DMA process success and ready for use */ + HAL_DMA_STATE_READY_HALF = 0x11, /*!< DMA Half process success */ + HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */ + HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */ + HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */ + +}HAL_DMA_StateTypeDef; + +/** + * @brief HAL DMA Error Code structure definition + */ +typedef enum +{ + HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */ + HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */ + +}HAL_DMA_LevelCompleteTypeDef; + + +/** + * @brief DMA handle Structure definition + */ +typedef struct __DMA_HandleTypeDef +{ + DMA_Channel_TypeDef *Instance; /*!< Register base address */ + + DMA_InitTypeDef Init; /*!< DMA communication parameters */ + + HAL_LockTypeDef Lock; /*!< DMA locking object */ + + HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ + + void *Parent; /*!< Parent object state */ + + void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ + + void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ + + void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ + + __IO uint32_t ErrorCode; /*!< DMA Error code */ + +} DMA_HandleTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DMA_Exported_Constants DMA Exported Constants + * @{ + */ + +/** @defgroup DMA_Error_Code DMA Error Code + * @{ + */ +#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ +#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */ +#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */ +/** + * @} + */ + +/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction + * @{ + */ +#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */ +#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ +#define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */ + +#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ + ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ + ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) +/** + * @} + */ + +/** @defgroup DMA_Data_buffer_size DMA Data buffer size + * @{ + */ +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) +/** + * @} + */ + +/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode + * @{ + */ +#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ +#define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */ + +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ + ((STATE) == DMA_PINC_DISABLE)) +/** + * @} + */ + +/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode + * @{ + */ +#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ +#define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */ + +#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ + ((STATE) == DMA_MINC_DISABLE)) +/** + * @} + */ + +/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size + * @{ + */ +#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */ +#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */ +#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */ + +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ + ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_PDATAALIGN_WORD)) +/** + * @} + */ + + +/** @defgroup DMA_Memory_data_size DMA Memory data size + * @{ + */ +#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */ +#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */ +#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */ + +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ + ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_MDATAALIGN_WORD )) +/** + * @} + */ + +/** @defgroup DMA_mode DMA mode + * @{ + */ +#define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal Mode */ +#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */ + +#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ + ((MODE) == DMA_CIRCULAR)) +/** + * @} + */ + +/** @defgroup DMA_Priority_level DMA Priority level + * @{ + */ +#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */ +#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ +#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ +#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ + +#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ + ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ + ((PRIORITY) == DMA_PRIORITY_HIGH) || \ + ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) +/** + * @} + */ + + +/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions + * @{ + */ + +#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) +#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) +#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) + +/** + * @} + */ + +/** @defgroup DMA_flag_definitions DMA flag definitions + * @{ + */ + +#define DMA_FLAG_GL1 ((uint32_t)0x00000001) +#define DMA_FLAG_TC1 ((uint32_t)0x00000002) +#define DMA_FLAG_HT1 ((uint32_t)0x00000004) +#define DMA_FLAG_TE1 ((uint32_t)0x00000008) +#define DMA_FLAG_GL2 ((uint32_t)0x00000010) +#define DMA_FLAG_TC2 ((uint32_t)0x00000020) +#define DMA_FLAG_HT2 ((uint32_t)0x00000040) +#define DMA_FLAG_TE2 ((uint32_t)0x00000080) +#define DMA_FLAG_GL3 ((uint32_t)0x00000100) +#define DMA_FLAG_TC3 ((uint32_t)0x00000200) +#define DMA_FLAG_HT3 ((uint32_t)0x00000400) +#define DMA_FLAG_TE3 ((uint32_t)0x00000800) +#define DMA_FLAG_GL4 ((uint32_t)0x00001000) +#define DMA_FLAG_TC4 ((uint32_t)0x00002000) +#define DMA_FLAG_HT4 ((uint32_t)0x00004000) +#define DMA_FLAG_TE4 ((uint32_t)0x00008000) +#define DMA_FLAG_GL5 ((uint32_t)0x00010000) +#define DMA_FLAG_TC5 ((uint32_t)0x00020000) +#define DMA_FLAG_HT5 ((uint32_t)0x00040000) +#define DMA_FLAG_TE5 ((uint32_t)0x00080000) +#define DMA_FLAG_GL6 ((uint32_t)0x00100000) +#define DMA_FLAG_TC6 ((uint32_t)0x00200000) +#define DMA_FLAG_HT6 ((uint32_t)0x00400000) +#define DMA_FLAG_TE6 ((uint32_t)0x00800000) +#define DMA_FLAG_GL7 ((uint32_t)0x01000000) +#define DMA_FLAG_TC7 ((uint32_t)0x02000000) +#define DMA_FLAG_HT7 ((uint32_t)0x04000000) +#define DMA_FLAG_TE7 ((uint32_t)0x08000000) + + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup DMA_Exported_Macros DMA Exported Macros + * @{ + */ + +/** @brief Reset DMA handle state + * @param __HANDLE__: DMA handle. + * @retval None + */ +#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) + +/** + * @brief Enable the specified DMA Channel. + * @param __HANDLE__: DMA handle + * @retval None. + */ +#define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) + +/** + * @brief Disable the specified DMA Channel. + * @param __HANDLE__: DMA handle + * @retval None. + */ +#define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) + + +/* Interrupt & Flag management */ + +/** + * @brief Enables the specified DMA Channel interrupts. + * @param __HANDLE__: DMA handle + * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer complete interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @retval None + */ +#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__))) + +/** + * @brief Disables the specified DMA Channel interrupts. + * @param __HANDLE__: DMA handle + * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer complete interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @retval None + */ +#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__))) + +/** + * @brief Checks whether the specified DMA Channel interrupt has occurred or not. + * @param __HANDLE__: DMA handle + * @param __INTERRUPT__: specifies the DMA interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer complete interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @retval The state of DMA_IT (SET or RESET). + */ +#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** + * @} + */ + +/* Include DMA HAL Extension module */ +#include "stm32f0xx_hal_dma_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup DMA_Exported_Functions DMA Exported Functions + * @{ + */ +/** @addtogroup DMA_Exported_Functions_Group1 + * @brief Initialization and de-initialization functions + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group2 + * @brief I/O operation functions + * @{ + */ +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/* Peripheral State and Error functions ***************************************/ +/** @addtogroup DMA_Exported_Functions_Group3 + * @brief Peripheral State functions + * @{ + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_DMA_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h @@ -0,0 +1,687 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_dma_ex.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Header file of DMA HAL Extension module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_DMA_EX_H +#define __STM32F0xx_HAL_DMA_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMAEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +#if defined(STM32F091xC) || defined(STM32F098xx) +/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants + * @{ + */ +#define DMA1_CHANNEL1_RMP 0x00000000 +#define DMA1_CHANNEL2_RMP 0x10000000 +#define DMA1_CHANNEL3_RMP 0x20000000 +#define DMA1_CHANNEL4_RMP 0x30000000 +#define DMA1_CHANNEL5_RMP 0x40000000 +#define DMA1_CHANNEL6_RMP 0x50000000 +#define DMA1_CHANNEL7_RMP 0x60000000 +#define DMA2_CHANNEL1_RMP 0x00000000 +#define DMA2_CHANNEL2_RMP 0x10000000 +#define DMA2_CHANNEL3_RMP 0x20000000 +#define DMA2_CHANNEL4_RMP 0x30000000 +#define DMA2_CHANNEL5_RMP 0x40000000 + +/****************** DMA1 remap bit field definition********************/ +/* DMA1 - Channel 1 */ +#define HAL_DMA1_CH1_DEFAULT (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ +#define HAL_DMA1_CH1_ADC (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_ADC) /*!< Remap ADC on DMA1 Channel 1*/ +#define HAL_DMA1_CH1_TIM17_CH1 (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 1 */ +#define HAL_DMA1_CH1_TIM17_UP (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 1 */ +#define HAL_DMA1_CH1_USART1_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 1 */ +#define HAL_DMA1_CH1_USART2_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 1 */ +#define HAL_DMA1_CH1_USART3_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 1 */ +#define HAL_DMA1_CH1_USART4_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 1 */ +#define HAL_DMA1_CH1_USART5_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 1 */ +#define HAL_DMA1_CH1_USART6_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 1 */ +#define HAL_DMA1_CH1_USART7_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 1 */ +#define HAL_DMA1_CH1_USART8_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 1 */ +/* DMA1 - Channel 2 */ +#define HAL_DMA1_CH2_DEFAULT (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ +#define HAL_DMA1_CH2_ADC (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_ADC) /*!< Remap ADC on DMA1 channel 2 */ +#define HAL_DMA1_CH2_I2C1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 2 */ +#define HAL_DMA1_CH2_SPI1_RX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_SPI1_RX) /*!< Remap SPI1 Rx on DMA1 channel 2 */ +#define HAL_DMA1_CH2_TIM1_CH1 (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 2 */ +#define HAL_DMA1_CH2_TIM17_CH1 (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 2 */ +#define HAL_DMA1_CH2_TIM17_UP (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 2 */ +#define HAL_DMA1_CH2_USART1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 2 */ +#define HAL_DMA1_CH2_USART2_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 2 */ +#define HAL_DMA1_CH2_USART3_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 2 */ +#define HAL_DMA1_CH2_USART4_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 2 */ +#define HAL_DMA1_CH2_USART5_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 2 */ +#define HAL_DMA1_CH2_USART6_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 2 */ +#define HAL_DMA1_CH2_USART7_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 2 */ +#define HAL_DMA1_CH2_USART8_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 2 */ +/* DMA1 - Channel 3 */ +#define HAL_DMA1_CH3_DEFAULT (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ +#define HAL_DMA1_CH3_TIM6_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA1 channel 3 */ +#define HAL_DMA1_CH3_DAC_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_DAC_CH1) /*!< Remap DAC Channel 1on DMA1 channel 3 */ +#define HAL_DMA1_CH3_I2C1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 3 */ +#define HAL_DMA1_CH3_SPI1_TX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_SPI1_TX) /*!< Remap SPI1 Tx on DMA1 channel 3 */ +#define HAL_DMA1_CH3_TIM1_CH2 (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 3 */ +#define HAL_DMA1_CH3_TIM2_CH2 (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 3 */ +#define HAL_DMA1_CH3_TIM16_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 3 */ +#define HAL_DMA1_CH3_TIM16_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 3 */ +#define HAL_DMA1_CH3_USART1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 3 */ +#define HAL_DMA1_CH3_USART2_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 3 */ +#define HAL_DMA1_CH3_USART3_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 3 */ +#define HAL_DMA1_CH3_USART4_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 3 */ +#define HAL_DMA1_CH3_USART5_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 3 */ +#define HAL_DMA1_CH3_USART6_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 3 */ +#define HAL_DMA1_CH3_USART7_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 3 */ +#define HAL_DMA1_CH3_USART8_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 3 */ +/* DMA1 - Channel 4 */ +#define HAL_DMA1_CH4_DEFAULT (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ +#define HAL_DMA1_CH4_TIM7_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA1 channel 4 */ +#define HAL_DMA1_CH4_DAC_CH2 (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_DAC_CH2) /*!< Remap DAC Channel 2 on DMA1 channel 4 */ +#define HAL_DMA1_CH4_I2C2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_I2C2_TX) /*!< Remap I2C2 Tx on DMA1 channel 4 */ +#define HAL_DMA1_CH4_SPI2_RX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 4 */ +#define HAL_DMA1_CH4_TIM2_CH4 (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 4 */ +#define HAL_DMA1_CH4_TIM3_CH1 (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 4 */ +#define HAL_DMA1_CH4_TIM3_TRIG (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 4 */ +#define HAL_DMA1_CH4_TIM16_CH1 (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 4 */ +#define HAL_DMA1_CH4_TIM16_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 4 */ +#define HAL_DMA1_CH4_USART1_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 4 */ +#define HAL_DMA1_CH4_USART2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 4 */ +#define HAL_DMA1_CH4_USART3_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 4 */ +#define HAL_DMA1_CH4_USART4_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 4 */ +#define HAL_DMA1_CH4_USART5_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 4 */ +#define HAL_DMA1_CH4_USART6_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 4 */ +#define HAL_DMA1_CH4_USART7_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 4 */ +#define HAL_DMA1_CH4_USART8_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 4 */ +/* DMA1 - Channel 5 */ +#define HAL_DMA1_CH5_DEFAULT (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ +#define HAL_DMA1_CH5_I2C2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_I2C2_RX) /*!< Remap I2C2 Rx on DMA1 channel 5 */ +#define HAL_DMA1_CH5_SPI2_TX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_SPI2_TX) /*!< Remap SPI1 Tx on DMA1 channel 5 */ +#define HAL_DMA1_CH5_TIM1_CH3 (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 5 */ +#define HAL_DMA1_CH5_USART1_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 5 */ +#define HAL_DMA1_CH5_USART2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 5 */ +#define HAL_DMA1_CH5_USART3_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 5 */ +#define HAL_DMA1_CH5_USART4_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 5 */ +#define HAL_DMA1_CH5_USART5_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 5 */ +#define HAL_DMA1_CH5_USART6_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 5 */ +#define HAL_DMA1_CH5_USART7_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 5 */ +#define HAL_DMA1_CH5_USART8_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 5 */ +/* DMA1 - Channel 6 */ +#define HAL_DMA1_CH6_DEFAULT (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ +#define HAL_DMA1_CH6_I2C1_TX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 6 */ +#define HAL_DMA1_CH6_SPI2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 6 */ +#define HAL_DMA1_CH6_TIM1_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 6 */ +#define HAL_DMA1_CH6_TIM1_CH2 (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 6 */ +#define HAL_DMA1_CH6_TIM1_CH3 (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 6 */ +#define HAL_DMA1_CH6_TIM3_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 6 */ +#define HAL_DMA1_CH6_TIM3_TRIG (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 6 */ +#define HAL_DMA1_CH6_TIM16_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 6 */ +#define HAL_DMA1_CH6_TIM16_UP (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 6 */ +#define HAL_DMA1_CH6_USART1_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 6 */ +#define HAL_DMA1_CH6_USART2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 6 */ +#define HAL_DMA1_CH6_USART3_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 6 */ +#define HAL_DMA1_CH6_USART4_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 6 */ +#define HAL_DMA1_CH6_USART5_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 6 */ +#define HAL_DMA1_CH6_USART6_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 6 */ +#define HAL_DMA1_CH6_USART7_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 6 */ +#define HAL_DMA1_CH6_USART8_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 6 */ +/* DMA1 - Channel 7 */ +#define HAL_DMA1_CH7_DEFAULT (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ +#define HAL_DMA1_CH7_I2C1_RX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 7 */ +#define HAL_DMA1_CH7_SPI2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_SPI2_TX) /*!< Remap SPI2 Tx on DMA1 channel 7 */ +#define HAL_DMA1_CH7_TIM2_CH2 (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 7 */ +#define HAL_DMA1_CH7_TIM2_CH4 (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 7 */ +#define HAL_DMA1_CH7_TIM17_CH1 (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 7 */ +#define HAL_DMA1_CH7_TIM17_UP (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 7 */ +#define HAL_DMA1_CH7_USART1_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 7 */ +#define HAL_DMA1_CH7_USART2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 7 */ +#define HAL_DMA1_CH7_USART3_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 7 */ +#define HAL_DMA1_CH7_USART4_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 7 */ +#define HAL_DMA1_CH7_USART5_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 7 */ +#define HAL_DMA1_CH7_USART6_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 7 */ +#define HAL_DMA1_CH7_USART7_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 7 */ +#define HAL_DMA1_CH7_USART8_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 7 */ + +/****************** DMA2 remap bit field definition********************/ +/* DMA2 - Channel 1 */ +#define HAL_DMA2_CH1_DEFAULT (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */ +#define HAL_DMA2_CH1_I2C2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_I2C2_TX) /*!< Remap I2C2 TX on DMA2 channel 1 */ +#define HAL_DMA2_CH1_USART1_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 1 */ +#define HAL_DMA2_CH1_USART2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 1 */ +#define HAL_DMA2_CH1_USART3_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 1 */ +#define HAL_DMA2_CH1_USART4_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 1 */ +#define HAL_DMA2_CH1_USART5_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 1 */ +#define HAL_DMA2_CH1_USART6_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 1 */ +#define HAL_DMA2_CH1_USART7_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 1 */ +#define HAL_DMA2_CH1_USART8_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 1 */ +/* DMA2 - Channel 2 */ +#define HAL_DMA2_CH2_DEFAULT (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */ +#define HAL_DMA2_CH2_I2C2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_I2C2_RX) /*!< Remap I2C2 Rx on DMA2 channel 2 */ +#define HAL_DMA2_CH2_USART1_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 2 */ +#define HAL_DMA2_CH2_USART2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 2 */ +#define HAL_DMA2_CH2_USART3_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 2 */ +#define HAL_DMA2_CH2_USART4_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 2 */ +#define HAL_DMA2_CH2_USART5_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 2 */ +#define HAL_DMA2_CH2_USART6_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 2 */ +#define HAL_DMA2_CH2_USART7_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 2 */ +#define HAL_DMA2_CH2_USART8_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 2 */ +/* DMA2 - Channel 3 */ +#define HAL_DMA2_CH3_DEFAULT (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */ +#define HAL_DMA2_CH3_TIM6_UP (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA2 channel 3 */ +#define HAL_DMA2_CH3_DAC_CH1 (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_DAC_CH1) /*!< Remap DAC channel 1 on DMA2 channel 3 */ +#define HAL_DMA2_CH3_SPI1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_SPI1_RX) /*!< Remap SPI1 Rx on DMA2 channel 3 */ +#define HAL_DMA2_CH3_USART1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 3 */ +#define HAL_DMA2_CH3_USART2_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 3 */ +#define HAL_DMA2_CH3_USART3_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 3 */ +#define HAL_DMA2_CH3_USART4_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 3 */ +#define HAL_DMA2_CH3_USART5_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 3 */ +#define HAL_DMA2_CH3_USART6_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 3 */ +#define HAL_DMA2_CH3_USART7_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 3 */ +#define HAL_DMA2_CH3_USART8_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 3 */ +/* DMA2 - Channel 4 */ +#define HAL_DMA2_CH4_DEFAULT (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */ +#define HAL_DMA2_CH4_TIM7_UP (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA2 channel 4 */ +#define HAL_DMA2_CH4_DAC_CH2 (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_DAC_CH2) /*!< Remap DAC channel 2 on DMA2 channel 4 */ +#define HAL_DMA2_CH4_SPI1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_SPI1_TX) /*!< Remap SPI1 Tx on DMA2 channel 4 */ +#define HAL_DMA2_CH4_USART1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 4 */ +#define HAL_DMA2_CH4_USART2_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 4 */ +#define HAL_DMA2_CH4_USART3_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 4 */ +#define HAL_DMA2_CH4_USART4_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 4 */ +#define HAL_DMA2_CH4_USART5_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 4 */ +#define HAL_DMA2_CH4_USART6_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 4 */ +#define HAL_DMA2_CH4_USART7_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 4 */ +#define HAL_DMA2_CH4_USART8_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 4 */ +/* DMA2 - Channel 5 */ +#define HAL_DMA2_CH5_DEFAULT (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */ +#define HAL_DMA2_CH5_ADC (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_ADC) /*!< Remap ADC on DMA2 channel 5 */ +#define HAL_DMA2_CH5_USART1_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 5 */ +#define HAL_DMA2_CH5_USART2_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 5 */ +#define HAL_DMA2_CH5_USART3_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 5 */ +#define HAL_DMA2_CH5_USART4_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 5 */ +#define HAL_DMA2_CH5_USART5_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 5 */ +#define HAL_DMA2_CH5_USART6_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 5 */ +#define HAL_DMA2_CH5_USART7_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 5 */ +#define HAL_DMA2_CH5_USART8_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 5 */ + +#define IS_HAL_DMA1_REMAP(REQUEST) (((REQUEST) == HAL_DMA1_CH1_DEFAULT) ||\ + ((REQUEST) == HAL_DMA1_CH1_ADC) ||\ + ((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH1_TIM17_UP) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART1_RX) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART2_RX) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART3_RX) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART4_RX) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART5_RX) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART6_RX) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART7_RX) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART8_RX) ||\ + ((REQUEST) == HAL_DMA1_CH2_DEFAULT) ||\ + ((REQUEST) == HAL_DMA1_CH2_ADC) ||\ + ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_SPI1_RX) ||\ + ((REQUEST) == HAL_DMA1_CH2_TIM1_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH2_TIM17_UP) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART1_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART2_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART3_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART4_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART5_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART6_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART7_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART8_TX) ||\ + ((REQUEST) == HAL_DMA1_CH3_DEFAULT) ||\ + ((REQUEST) == HAL_DMA1_CH3_TIM6_UP) ||\ + ((REQUEST) == HAL_DMA1_CH3_DAC_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH3_I2C1_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_SPI1_TX) ||\ + ((REQUEST) == HAL_DMA1_CH3_TIM1_CH2) ||\ + ((REQUEST) == HAL_DMA1_CH3_TIM2_CH2) ||\ + ((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH3_TIM16_UP) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART1_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART2_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART3_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART4_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART5_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART6_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART7_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART8_RX) ||\ + ((REQUEST) == HAL_DMA1_CH4_DEFAULT) ||\ + ((REQUEST) == HAL_DMA1_CH4_TIM7_UP) ||\ + ((REQUEST) == HAL_DMA1_CH4_DAC_CH2) ||\ + ((REQUEST) == HAL_DMA1_CH4_I2C2_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_SPI2_RX) ||\ + ((REQUEST) == HAL_DMA1_CH4_TIM2_CH4) ||\ + ((REQUEST) == HAL_DMA1_CH4_TIM3_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) ||\ + ((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH4_TIM16_UP) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART1_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART2_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART3_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART4_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART5_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART6_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART7_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART8_TX) ||\ + ((REQUEST) == HAL_DMA1_CH5_DEFAULT) ||\ + ((REQUEST) == HAL_DMA1_CH5_I2C2_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_SPI2_TX) ||\ + ((REQUEST) == HAL_DMA1_CH5_TIM1_CH3) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART1_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART2_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART3_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART4_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART5_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART6_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART7_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART8_RX) ||\ + ((REQUEST) == HAL_DMA1_CH6_DEFAULT) ||\ + ((REQUEST) == HAL_DMA1_CH6_I2C1_TX) ||\ + ((REQUEST) == HAL_DMA1_CH6_SPI2_RX) ||\ + ((REQUEST) == HAL_DMA1_CH6_TIM1_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH6_TIM1_CH2) ||\ + ((REQUEST) == HAL_DMA1_CH6_TIM1_CH3) ||\ + ((REQUEST) == HAL_DMA1_CH6_TIM3_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH6_TIM3_TRIG) ||\ + ((REQUEST) == HAL_DMA1_CH6_TIM16_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH6_TIM16_UP) ||\ + ((REQUEST) == HAL_DMA1_CH6_USART1_RX) ||\ + ((REQUEST) == HAL_DMA1_CH6_USART2_RX) ||\ + ((REQUEST) == HAL_DMA1_CH6_USART3_RX) ||\ + ((REQUEST) == HAL_DMA1_CH6_USART4_RX) ||\ + ((REQUEST) == HAL_DMA1_CH6_USART5_RX) ||\ + ((REQUEST) == HAL_DMA1_CH6_USART6_RX) ||\ + ((REQUEST) == HAL_DMA1_CH6_USART7_RX) ||\ + ((REQUEST) == HAL_DMA1_CH6_USART8_RX) ||\ + ((REQUEST) == HAL_DMA1_CH7_DEFAULT) ||\ + ((REQUEST) == HAL_DMA1_CH7_I2C1_RX) ||\ + ((REQUEST) == HAL_DMA1_CH7_SPI2_TX) ||\ + ((REQUEST) == HAL_DMA1_CH7_TIM2_CH2) ||\ + ((REQUEST) == HAL_DMA1_CH7_TIM2_CH4) ||\ + ((REQUEST) == HAL_DMA1_CH7_TIM17_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH7_TIM17_UP) ||\ + ((REQUEST) == HAL_DMA1_CH7_USART1_TX) ||\ + ((REQUEST) == HAL_DMA1_CH7_USART2_TX) ||\ + ((REQUEST) == HAL_DMA1_CH7_USART3_TX) ||\ + ((REQUEST) == HAL_DMA1_CH7_USART4_TX) ||\ + ((REQUEST) == HAL_DMA1_CH7_USART5_TX) ||\ + ((REQUEST) == HAL_DMA1_CH7_USART6_TX) ||\ + ((REQUEST) == HAL_DMA1_CH7_USART7_TX) ||\ + ((REQUEST) == HAL_DMA1_CH7_USART8_TX)) + +#define IS_HAL_DMA2_REMAP(REQUEST) (((REQUEST) == HAL_DMA2_CH1_DEFAULT) ||\ + ((REQUEST) == HAL_DMA2_CH1_I2C2_TX) ||\ + ((REQUEST) == HAL_DMA2_CH1_USART1_TX) ||\ + ((REQUEST) == HAL_DMA2_CH1_USART2_TX) ||\ + ((REQUEST) == HAL_DMA2_CH1_USART3_TX) ||\ + ((REQUEST) == HAL_DMA2_CH1_USART4_TX) ||\ + ((REQUEST) == HAL_DMA2_CH1_USART5_TX) ||\ + ((REQUEST) == HAL_DMA2_CH1_USART6_TX) ||\ + ((REQUEST) == HAL_DMA2_CH1_USART7_TX) ||\ + ((REQUEST) == HAL_DMA2_CH1_USART8_TX) ||\ + ((REQUEST) == HAL_DMA2_CH2_DEFAULT) ||\ + ((REQUEST) == HAL_DMA2_CH2_I2C2_RX) ||\ + ((REQUEST) == HAL_DMA2_CH2_USART1_RX) ||\ + ((REQUEST) == HAL_DMA2_CH2_USART2_RX) ||\ + ((REQUEST) == HAL_DMA2_CH2_USART3_RX) ||\ + ((REQUEST) == HAL_DMA2_CH2_USART4_RX) ||\ + ((REQUEST) == HAL_DMA2_CH2_USART5_RX) ||\ + ((REQUEST) == HAL_DMA2_CH2_USART6_RX) ||\ + ((REQUEST) == HAL_DMA2_CH2_USART7_RX) ||\ + ((REQUEST) == HAL_DMA2_CH2_USART8_RX) ||\ + ((REQUEST) == HAL_DMA2_CH3_DEFAULT) ||\ + ((REQUEST) == HAL_DMA2_CH3_TIM6_UP) ||\ + ((REQUEST) == HAL_DMA2_CH3_DAC_CH1) ||\ + ((REQUEST) == HAL_DMA2_CH3_SPI1_RX) ||\ + ((REQUEST) == HAL_DMA2_CH3_USART1_RX) ||\ + ((REQUEST) == HAL_DMA2_CH3_USART2_RX) ||\ + ((REQUEST) == HAL_DMA2_CH3_USART3_RX) ||\ + ((REQUEST) == HAL_DMA2_CH3_USART4_RX) ||\ + ((REQUEST) == HAL_DMA2_CH3_USART5_RX) ||\ + ((REQUEST) == HAL_DMA2_CH3_USART6_RX) ||\ + ((REQUEST) == HAL_DMA2_CH3_USART7_RX) ||\ + ((REQUEST) == HAL_DMA2_CH3_USART8_RX) ||\ + ((REQUEST) == HAL_DMA2_CH4_DEFAULT) ||\ + ((REQUEST) == HAL_DMA2_CH4_TIM7_UP) ||\ + ((REQUEST) == HAL_DMA2_CH4_DAC_CH2) ||\ + ((REQUEST) == HAL_DMA2_CH4_SPI1_TX) ||\ + ((REQUEST) == HAL_DMA2_CH4_USART1_TX) ||\ + ((REQUEST) == HAL_DMA2_CH4_USART2_TX) ||\ + ((REQUEST) == HAL_DMA2_CH4_USART3_TX) ||\ + ((REQUEST) == HAL_DMA2_CH4_USART4_TX) ||\ + ((REQUEST) == HAL_DMA2_CH4_USART5_TX) ||\ + ((REQUEST) == HAL_DMA2_CH4_USART6_TX) ||\ + ((REQUEST) == HAL_DMA2_CH4_USART7_TX) ||\ + ((REQUEST) == HAL_DMA2_CH4_USART8_TX) ||\ + ((REQUEST) == HAL_DMA2_CH5_DEFAULT) ||\ + ((REQUEST) == HAL_DMA2_CH5_ADC) ||\ + ((REQUEST) == HAL_DMA2_CH5_USART1_TX) ||\ + ((REQUEST) == HAL_DMA2_CH5_USART2_TX) ||\ + ((REQUEST) == HAL_DMA2_CH5_USART3_TX) ||\ + ((REQUEST) == HAL_DMA2_CH5_USART4_TX) ||\ + ((REQUEST) == HAL_DMA2_CH5_USART5_TX) ||\ + ((REQUEST) == HAL_DMA2_CH5_USART6_TX) ||\ + ((REQUEST) == HAL_DMA2_CH5_USART7_TX) ||\ + ((REQUEST) == HAL_DMA2_CH5_USART8_TX )) +/** + * @} + */ +#endif /* STM32F091xC || STM32F098xx */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup DMAEx_Exported_Macros DMAEx Exported Macros + * @{ + */ +/* Interrupt & Flag management */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) +/** + * @brief Returns the current DMA Channel transfer complete flag. + * @param __HANDLE__: DMA handle + * @retval The specified transfer complete flag index. + */ +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ + DMA_FLAG_TC7) + +/** + * @brief Returns the current DMA Channel half transfer complete flag. + * @param __HANDLE__: DMA handle + * @retval The specified half transfer complete flag index. + */ +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ + DMA_FLAG_HT7) + +/** + * @brief Returns the current DMA Channel transfer error flag. + * @param __HANDLE__: DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ + DMA_FLAG_TE7) + +/** + * @brief Get the DMA Channel pending flags. + * @param __HANDLE__: DMA handle + * @param __FLAG__: Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCIFx: Transfer complete flag + * @arg DMA_FLAG_HTIFx: Half transfer complete flag + * @arg DMA_FLAG_TEIFx: Transfer error flag + * Where x can be 1_7 to select the DMA Channel flag. + * @retval The state of FLAG (SET or RESET). + */ + +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) + +/** + * @brief Clears the DMA Channel pending flags. + * @param __HANDLE__: DMA handle + * @param __FLAG__: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCIFx: Transfer complete flag + * @arg DMA_FLAG_HTIFx: Half transfer complete flag + * @arg DMA_FLAG_TEIFx: Transfer error flag + * Where x can be 1_7 to select the DMA Channel flag. + * @retval None + */ +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) + +#elif defined(STM32F091xC) || defined(STM32F098xx) +/** + * @brief Returns the current DMA Channel transfer complete flag. + * @param __HANDLE__: DMA handle + * @retval The specified transfer complete flag index. + */ +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ + DMA_FLAG_TC5) + +/** + * @brief Returns the current DMA Channel half transfer complete flag. + * @param __HANDLE__: DMA handle + * @retval The specified half transfer complete flag index. + */ +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ + DMA_FLAG_HT5) + +/** + * @brief Returns the current DMA Channel transfer error flag. + * @param __HANDLE__: DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ + DMA_FLAG_TE5) + +/** + * @brief Get the DMA Channel pending flags. + * @param __HANDLE__: DMA handle + * @param __FLAG__: Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCIFx: Transfer complete flag + * @arg DMA_FLAG_HTIFx: Half transfer complete flag + * @arg DMA_FLAG_TEIFx: Transfer error flag + * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag. + * @retval The state of FLAG (SET or RESET). + */ + +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ +(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\ + (DMA1->ISR & (__FLAG__))) + +/** + * @brief Clears the DMA Channel pending flags. + * @param __HANDLE__: DMA handle + * @param __FLAG__: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCIFx: Transfer complete flag + * @arg DMA_FLAG_HTIFx: Half transfer complete flag + * @arg DMA_FLAG_TEIFx: Transfer error flag + * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag. + * @retval None + */ +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ +(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\ + (DMA1->IFCR = (__FLAG__))) + +#else /* STM32F030x8_STM32F031x6_STM32F038xx_STM32F051x8_STM32F058xx Product devices */ +/** + * @brief Returns the current DMA Channel transfer complete flag. + * @param __HANDLE__: DMA handle + * @retval The specified transfer complete flag index. + */ +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ + DMA_FLAG_TC5) + +/** + * @brief Returns the current DMA Channel half transfer complete flag. + * @param __HANDLE__: DMA handle + * @retval The specified half transfer complete flag index. + */ +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ + DMA_FLAG_HT5) + +/** + * @brief Returns the current DMA Channel transfer error flag. + * @param __HANDLE__: DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ + DMA_FLAG_TE5) + +/** + * @brief Get the DMA Channel pending flags. + * @param __HANDLE__: DMA handle + * @param __FLAG__: Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCIFx: Transfer complete flag + * @arg DMA_FLAG_HTIFx: Half transfer complete flag + * @arg DMA_FLAG_TEIFx: Transfer error flag + * Where x can be 1_5 to select the DMA Channel flag. + * @retval The state of FLAG (SET or RESET). + */ + +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) + +/** + * @brief Clears the DMA Channel pending flags. + * @param __HANDLE__: DMA handle + * @param __FLAG__: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCIFx: Transfer complete flag + * @arg DMA_FLAG_HTIFx: Half transfer complete flag + * @arg DMA_FLAG_TEIFx: Transfer error flag + * Where x can be 1_5 to select the DMA Channel flag. + * @retval None + */ +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) + +#endif + + +#if defined(STM32F091xC) || defined(STM32F098xx) +#define __HAL_DMA1_REMAP(__REQUEST__) \ + do { assert_param(IS_HAL_DMA1_REMAP(__REQUEST__)); \ + DMA1->RMPCR &= ~((uint32_t)0x0F << (uint32_t)(((__REQUEST__) >> 28) * 4)); \ + DMA1->RMPCR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFF); \ + }while(0) + +#define __HAL_DMA2_REMAP(__REQUEST__) \ + do { assert_param(IS_HAL_DMA2_REMAP(__REQUEST__)); \ + DMA2->RMPCR &= ~((uint32_t)0x0F << (uint32_t)(((__REQUEST__) >> 28) * 4)); \ + DMA2->RMPCR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFF); \ + }while(0) + + #endif /* STM32F091xC || STM32F098xx */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_DMA_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h @@ -0,0 +1,513 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_flash.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Header file of Flash HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_FLASH_H +#define __STM32F0xx_HAL_FLASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup FLASH_Exported_Types FLASH Exported Types + * @{ + */ + +/** + * @brief FLASH Error source + */ +typedef enum +{ + FLASH_ERROR_PG = 0x01, + FLASH_ERROR_WRP = 0x02 +} FLASH_ErrorTypeDef; + +/** + * @brief FLASH Erase structure definition + */ +typedef struct +{ + uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase. + This parameter can be a value of @ref FLASH_Type_Erase */ + + uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled + This parameter must be a value of @ref FLASHEx_Address */ + + uint32_t NbPages; /*!< NbPages: Number of pagess to be erased. + This parameter must be a value between 1 and (max number of pages - value of initial page)*/ + +} FLASH_EraseInitTypeDef; + +/** + * @brief FLASH Options bytes program structure definition + */ +typedef struct +{ + uint32_t OptionType; /*!< OptionType: Option byte to be configured. + This parameter can be a value of @ref FLASH_OB_Type */ + + uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation. + This parameter can be a value of @ref FLASH_OB_WRP_State */ + + uint32_t WRPPage; /*!< WRPSector: specifies the page(s) to be write protected + This parameter can be a value of @ref FLASHEx_OB_Write_Protection */ + + uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level.. + This parameter can be a value of @ref FLASH_OB_Read_Protection */ + + uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: + IWDG / STOP / STDBY / BOOT1 / VDDA_ANALOG / SRAM_PARITY + This parameter can be a combination of @ref FLASH_OB_Watchdog, @ref FLASH_OB_nRST_STOP, + @ref FLASH_OB_nRST_STDBY, @ref FLASH_OB_BOOT1, @ref FLASH_OB_VDDA_Analog_Monitoring and + @ref FLASH_OB_RAM_Parity_Check_Enable */ + + uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be prgrammed + This parameter can be a value of @ref FLASH_OB_Data_Address */ + + uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA + This parameter can have any value */ + +} FLASH_OBProgramInitTypeDef; + +/** + * @brief FLASH Procedure structure definition + */ +typedef enum +{ + FLASH_PROC_NONE = 0, + FLASH_PROC_PAGEERASE = 1, + FLASH_PROC_MASSERASE = 2, + FLASH_PROC_PROGRAMHALFWORD = 3, + FLASH_PROC_PROGRAMWORD = 4, + FLASH_PROC_PROGRAMDOUBLEWORD = 5 +} FLASH_ProcedureTypeDef; + +/** + * @brief FLASH handle Structure definition + */ +typedef struct +{ + __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */ + + __IO uint32_t DataRemaining; /* Internal variable to save the remaining pages to erase or half-word to program in IT context */ + + __IO uint32_t Address; /* Internal variable to save address selected for program or erase */ + + __IO uint64_t Data; /* Internal variable to save data to be programmed */ + + HAL_LockTypeDef Lock; /* FLASH locking object */ + + __IO FLASH_ErrorTypeDef ErrorCode; /* FLASH error code */ + +} FLASH_ProcessTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup FLASH_Exported_Constants FLASH Exported Constants + * @{ + */ + +/** @defgroup FLASH_Type_Erase FLASH Type Erase + * @{ + */ +#define TYPEERASE_PAGES ((uint32_t)0x00) /*!ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__)) +/** + * @} + */ + +/** @defgroup FLASH_Prefetch FLASH Prefetch + * @brief macros to handle FLASH Prefetch buffer + * @{ + */ +/** + * @brief Enable the FLASH prefetch buffer. + * @retval None + */ +#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE) + +/** + * @brief Disable the FLASH prefetch buffer. + * @retval None + */ +#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE)) + +/** + * @} + */ + +/** @defgroup FLASH_Interrupt FLASH Interrupt + * @brief macros to handle FLASH interrupts + * @{ + */ + +/** + * @brief Enable the specified FLASH interrupt. + * @param __INTERRUPT__ : FLASH interrupt + * This parameter can be any combination of the following values: + * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt + * @arg FLASH_IT_ERR: Error Interrupt + * @retval none + */ +#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__)) + +/** + * @brief Disable the specified FLASH interrupt. + * @param __INTERRUPT__ : FLASH interrupt + * This parameter can be any combination of the following values: + * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt + * @arg FLASH_IT_ERR: Error Interrupt + * @retval none + */ +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(uint32_t)(__INTERRUPT__)) + +/** + * @brief Get the specified FLASH flag status. + * @param __FLAG__: specifies the FLASH flag to check. + * This parameter can be one of the following values: + * @arg FLASH_FLAG_EOP : FLASH End of Operation flag + * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag + * @arg FLASH_FLAG_PGERR : FLASH Programming error flag + * @arg FLASH_FLAG_BSY : FLASH Busy flag + * @retval The new state of __FLAG__ (SET or RESET). + */ +#define __HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear the specified FLASH flag. + * @param __FLAG__: specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg FLASH_FLAG_EOP : FLASH End of Operation flag + * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag + * @arg FLASH_FLAG_PGERR : FLASH Programming error flag + * @retval none + */ +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__)) + +/** + * @} + */ + +/** + * @} + */ + +/* Include FLASH HAL Extension module */ +#include "stm32f0xx_hal_flash_ex.h" + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup FLASH_Exported_Functions + * @{ + */ + +/** @addtogroup FLASH_Exported_Functions_Group1 + * @brief Data transfers functions + * @{ + */ + +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); + +/* FLASH IRQ handler method */ +void HAL_FLASH_IRQHandler(void); +/* Callbacks in non blocking modes */ +void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); +void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); + +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions_Group2 + * @brief management functions + * @{ + */ + +/* FLASH Memory Programming functions *****************************************/ +HAL_StatusTypeDef HAL_FLASH_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_Lock(void); + +/* Option Bytes Programming functions *****************************************/ +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); + +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +FLASH_ErrorTypeDef HAL_FLASH_GetError(void); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_FLASH_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h @@ -0,0 +1,296 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_flash_ex.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Header file of FLASH HAL Extension module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_FLASH_EX_H +#define __STM32F0xx_HAL_FLASH_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASHEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants + * @{ + */ +/** @defgroup FLASHEx_Address FLASHEx Address + * @{ + */ +#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F038xx) +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x08007FFF)) +#endif /* STM32F030x6 || STM32F031x6 || STM32F042x6 || STM32F048xx || STM32F038xx */ + +#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx) +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0800FFFF)) +#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0801FFFF)) +#endif /* STM32F071xB || STM32F072xB || STM32F078xx */ + +#if defined(STM32F091xC) || defined(STM32F098xx) +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0803FFFF)) +#endif /* STM32F091xC || STM32F098xx */ +/** + * @} + */ + +/** @defgroup FLASHEx_Page_Size FLASHEx Page Size + * @{ + */ +#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || \ + defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx) +#define FLASH_PAGE_SIZE 0x400 +#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F058xx */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) +#define FLASH_PAGE_SIZE 0x800 +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */ + +/** + * @} + */ + +/** @defgroup FLASHEx_Nb_Pages FLASHEx Nb Pages + * @{ + */ +#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F038xx) +#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08007FFF) +#endif /* STM32F030x6 || STM32F031x6 || STM32F042x6 || STM32F048xx || STM32F038xx */ + +#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx) +#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFF) +#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) +#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFF) +#endif /* STM32F071xB || STM32F072xB || STM32F078xx */ + +#if defined(STM32F091xC) || defined(STM32F098xx) +#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFF) +#endif /* STM32F091xC || STM32F098xx */ +/** + * @} + */ + +/** @defgroup FLASHEx_OB_Write_Protection FLASHEx OB Write Protection + * @{ + */ +#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || \ + defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx) +#define OB_WRP_PAGES0TO3 ((uint32_t)0x00000001) /* Write protection of page 0 to 3 */ +#define OB_WRP_PAGES4TO7 ((uint32_t)0x00000002) /* Write protection of page 4 to 7 */ +#define OB_WRP_PAGES8TO11 ((uint32_t)0x00000004) /* Write protection of page 8 to 11 */ +#define OB_WRP_PAGES12TO15 ((uint32_t)0x00000008) /* Write protection of page 12 to 15 */ +#define OB_WRP_PAGES16TO19 ((uint32_t)0x00000010) /* Write protection of page 16 to 19 */ +#define OB_WRP_PAGES20TO23 ((uint32_t)0x00000020) /* Write protection of page 20 to 23 */ +#define OB_WRP_PAGES24TO27 ((uint32_t)0x00000040) /* Write protection of page 24 to 27 */ +#define OB_WRP_PAGES28TO31 ((uint32_t)0x00000080) /* Write protection of page 28 to 31 */ +#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx) +#define OB_WRP_PAGES32TO35 ((uint32_t)0x00000100) /* Write protection of page 32 to 35 */ +#define OB_WRP_PAGES36TO39 ((uint32_t)0x00000200) /* Write protection of page 36 to 39 */ +#define OB_WRP_PAGES40TO43 ((uint32_t)0x00000400) /* Write protection of page 40 to 43 */ +#define OB_WRP_PAGES44TO47 ((uint32_t)0x00000800) /* Write protection of page 44 to 47 */ +#define OB_WRP_PAGES48TO51 ((uint32_t)0x00001000) /* Write protection of page 48 to 51 */ +#define OB_WRP_PAGES52TO57 ((uint32_t)0x00002000) /* Write protection of page 52 to 57 */ +#define OB_WRP_PAGES56TO59 ((uint32_t)0x00004000) /* Write protection of page 56 to 59 */ +#define OB_WRP_PAGES60TO63 ((uint32_t)0x00008000) /* Write protection of page 60 to 63 */ +#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */ + +#define OB_WRP_PAGES0TO31MASK ((uint32_t)0x000000FF) +#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx) +#define OB_WRP_PAGES32TO63MASK ((uint32_t)0x0000FF00) +#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */ + +#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F038xx) +#define OB_WRP_ALLPAGES ((uint32_t)0x000000FF) /*!< Write protection of all pages */ +#endif /* STM32F030x6 || STM32F031x6 || STM32F042x6 || STM32F048xx || STM32F038xx */ + +#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx) +#define OB_WRP_ALLPAGES ((uint32_t)0x0000FFFF) /*!< Write protection of all pages */ +#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */ +#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F038xx || STM32F058xx */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) +#define OB_WRP_PAGES0TO1 ((uint32_t)0x00000001) /* Write protection of page 0 to 1 */ +#define OB_WRP_PAGES2TO3 ((uint32_t)0x00000002) /* Write protection of page 2 to 3 */ +#define OB_WRP_PAGES4TO5 ((uint32_t)0x00000004) /* Write protection of page 4 to 5 */ +#define OB_WRP_PAGES6TO7 ((uint32_t)0x00000008) /* Write protection of page 6 to 7 */ +#define OB_WRP_PAGES8TO9 ((uint32_t)0x00000010) /* Write protection of page 8 to 9 */ +#define OB_WRP_PAGES10TO11 ((uint32_t)0x00000020) /* Write protection of page 10 to 11 */ +#define OB_WRP_PAGES12TO13 ((uint32_t)0x00000040) /* Write protection of page 12 to 13 */ +#define OB_WRP_PAGES14TO15 ((uint32_t)0x00000080) /* Write protection of page 14 to 15 */ +#define OB_WRP_PAGES16TO17 ((uint32_t)0x00000100) /* Write protection of page 16 to 17 */ +#define OB_WRP_PAGES18TO19 ((uint32_t)0x00000200) /* Write protection of page 18 to 19 */ +#define OB_WRP_PAGES20TO21 ((uint32_t)0x00000400) /* Write protection of page 20 to 21 */ +#define OB_WRP_PAGES22TO23 ((uint32_t)0x00000800) /* Write protection of page 22 to 23 */ +#define OB_WRP_PAGES24TO25 ((uint32_t)0x00001000) /* Write protection of page 24 to 25 */ +#define OB_WRP_PAGES26TO27 ((uint32_t)0x00002000) /* Write protection of page 26 to 27 */ +#define OB_WRP_PAGES28TO29 ((uint32_t)0x00004000) /* Write protection of page 28 to 29 */ +#define OB_WRP_PAGES30TO31 ((uint32_t)0x00008000) /* Write protection of page 30 to 31 */ +#define OB_WRP_PAGES32TO33 ((uint32_t)0x00010000) /* Write protection of page 32 to 33 */ +#define OB_WRP_PAGES34TO35 ((uint32_t)0x00020000) /* Write protection of page 34 to 35 */ +#define OB_WRP_PAGES36TO37 ((uint32_t)0x00040000) /* Write protection of page 36 to 37 */ +#define OB_WRP_PAGES38TO39 ((uint32_t)0x00080000) /* Write protection of page 38 to 39 */ +#define OB_WRP_PAGES40TO41 ((uint32_t)0x00100000) /* Write protection of page 40 to 41 */ +#define OB_WRP_PAGES42TO43 ((uint32_t)0x00200000) /* Write protection of page 42 to 43 */ +#define OB_WRP_PAGES44TO45 ((uint32_t)0x00400000) /* Write protection of page 44 to 45 */ +#define OB_WRP_PAGES46TO47 ((uint32_t)0x00800000) /* Write protection of page 46 to 47 */ +#define OB_WRP_PAGES48TO49 ((uint32_t)0x01000000) /* Write protection of page 48 to 49 */ +#define OB_WRP_PAGES50TO51 ((uint32_t)0x02000000) /* Write protection of page 50 to 51 */ +#define OB_WRP_PAGES52TO53 ((uint32_t)0x04000000) /* Write protection of page 52 to 53 */ +#define OB_WRP_PAGES54TO55 ((uint32_t)0x08000000) /* Write protection of page 54 to 55 */ +#define OB_WRP_PAGES56TO57 ((uint32_t)0x10000000) /* Write protection of page 56 to 57 */ +#define OB_WRP_PAGES58TO59 ((uint32_t)0x20000000) /* Write protection of page 58 to 59 */ +#define OB_WRP_PAGES60TO61 ((uint32_t)0x40000000) /* Write protection of page 60 to 61 */ +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) +#define OB_WRP_PAGES62TO63 ((uint32_t)0x80000000) /* Write protection of page 62 to 63 */ +#endif /* STM32F071xB || STM32F072xB || STM32F078xx */ +#if defined(STM32F091xC) || defined(STM32F098xx) +#define OB_WRP_PAGES62TO127 ((uint32_t)0x80000000) /* Write protection of page 62 to 127 */ +#endif /* STM32F091xC || STM32F098xx */ + +#define OB_WRP_PAGES0TO15MASK ((uint32_t)0x000000FF) +#define OB_WRP_PAGES16TO31MASK ((uint32_t)0x0000FF00) +#define OB_WRP_PAGES32TO47MASK ((uint32_t)0x00FF0000) +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) +#define OB_WRP_PAGES48TO63MASK ((uint32_t)0xFF000000) +#endif /* STM32F071xB || STM32F072xB || STM32F078xx */ +#if defined(STM32F091xC) || defined(STM32F098xx) +#define OB_WRP_PAGES48TO127MASK ((uint32_t)0xFF000000) +#endif /* STM32F091xC || STM32F098xx */ + +#define OB_WRP_ALLPAGES ((uint32_t)0xFFFFFFFF) /*!< Write protection of all pages */ +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */ + +#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000)) +/** + * @} + */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F091xC) || defined(STM32F098xx) +/** @defgroup FLASHEx_OB_BOOT_SEL FLASHEx OB BOOT SEL + * @{ + */ +#define OB_BOOT_SEL_RESET ((uint8_t)0x00) /*!< BOOT_SEL Reset */ +#define OB_BOOT_SEL_SET ((uint8_t)0x80) /*!< BOOT_SEL Set */ +#define IS_OB_BOOT_SEL(BOOT_SEL) (((BOOT_SEL) == OB_BOOT_SEL_RESET) || ((BOOT_SEL) == OB_BOOT_SEL_SET)) +/** + * @} + */ + +/** @defgroup FLASHEx_OB_BOOT0 FLASHEx OB BOOT0 + * @{ + */ +#define OB_BOOT0_RESET ((uint8_t)0x00) /*!< BOOT0 Reset */ +#define OB_BOOT0_SET ((uint8_t)0x08) /*!< BOOT0 Set */ +#define IS_OB_BOOT0(BOOT0) (((BOOT0) == OB_BOOT0_RESET) || ((BOOT0) == OB_BOOT0_SET)) +/** + * @} + */ +#endif /* STM32F042x6 || STM32F048xx || STM32F091xC || STM32F098xx */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASHEx_Exported_Functions FLASHEx Exported Functions + * @{ + */ + +/** @addtogroup FLASHEx_Exported_Functions_Group2 Extended I/O operation functions + * @brief Extended I/O operation functions + * @{ + */ +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError); +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); + +/** + * @} + */ + +/** @addtogroup FLASHEx_Exported_Functions_Group3 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions + * @{ + */ +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_FLASHEx_OBErase(void); +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_FLASH_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h @@ -0,0 +1,318 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_gpio.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Header file of GPIO HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_GPIO_H +#define __STM32F0xx_HAL_GPIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Types GPIO Exported Types + * @{ + */ +/** + * @brief GPIO Init structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_mode */ + + uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. + This parameter can be a value of @ref GPIO_pull */ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_speed */ + + uint32_t Alternate; /*!< Peripheral to be connected to the selected pins + This parameter can be a value of @ref GPIOEx_Alternate_function_selection */ +}GPIO_InitTypeDef; + +/** + * @brief GPIO Bit SET and Bit RESET enumeration + */ +typedef enum +{ + GPIO_PIN_RESET = 0, + GPIO_PIN_SET +}GPIO_PinState; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Constants GPIO Exported Constants + * @{ + */ + +/** @defgroup GPIO_pin_actions GPIO pin actions + * @{ + */ +#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) +/** + * @} + */ + +/** @defgroup GPIO_pins GPIO pins + * @{ + */ +#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ + +#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */ + +#define IS_GPIO_PIN(PIN) (((PIN) & GPIO_PIN_MASK) != (uint32_t)0x00) +/** + * @} + */ + +/** @defgroup GPIO_mode GPIO mode + * @brief GPIO Configuration Mode + * Elements values convention: 0xX0yz00YZ + * - X : GPIO mode or EXTI Mode + * - y : External IT or Event trigger detection + * - z : IO configuration on External IT or Event + * - Y : Output type (Push Pull or Open Drain) + * - Z : IO Direction mode (Input, Output, Alternate or Analog) + * @{ + */ +#define GPIO_MODE_INPUT ((uint32_t)0x00000000) /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001) /*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011) /*!< Output Open Drain Mode */ +#define GPIO_MODE_AF_PP ((uint32_t)0x00000002) /*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_OD ((uint32_t)0x00000012) /*!< Alternate Function Open Drain Mode */ + +#define GPIO_MODE_ANALOG ((uint32_t)0x00000003) /*!< Analog Mode */ + +#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ + +#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000) /*!< External Event Mode with Rising edge trigger detection */ +#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000) /*!< External Event Mode with Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000) /*!< External Event Mode with Rising/Falling edge trigger detection */ + +#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\ + ((MODE) == GPIO_MODE_OUTPUT_PP) ||\ + ((MODE) == GPIO_MODE_OUTPUT_OD) ||\ + ((MODE) == GPIO_MODE_AF_PP) ||\ + ((MODE) == GPIO_MODE_AF_OD) ||\ + ((MODE) == GPIO_MODE_IT_RISING) ||\ + ((MODE) == GPIO_MODE_IT_FALLING) ||\ + ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\ + ((MODE) == GPIO_MODE_EVT_RISING) ||\ + ((MODE) == GPIO_MODE_EVT_FALLING) ||\ + ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\ + ((MODE) == GPIO_MODE_ANALOG)) + +/** + * @} + */ + +/** @defgroup GPIO_speed GPIO speed + * @brief GPIO Output Maximum frequency + * @{ + */ +#define GPIO_SPEED_LOW ((uint32_t)0x00000000) /*!< Low speed */ +#define GPIO_SPEED_MEDIUM ((uint32_t)0x00000001) /*!< Medium speed */ +#define GPIO_SPEED_HIGH ((uint32_t)0x00000003) /*!< High speed */ + +#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_LOW) || ((SPEED) == GPIO_SPEED_MEDIUM) || \ + ((SPEED) == GPIO_SPEED_HIGH)) +/** + * @} + */ + + /** @defgroup GPIO_pull GPIO pull + * @brief GPIO Pull-Up or Pull-Down Activation + * @{ + */ +#define GPIO_NOPULL ((uint32_t)0x00000000) /*!< No Pull-up or Pull-down activation */ +#define GPIO_PULLUP ((uint32_t)0x00000001) /*!< Pull-up activation */ +#define GPIO_PULLDOWN ((uint32_t)0x00000002) /*!< Pull-down activation */ + +#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \ + ((PULL) == GPIO_PULLDOWN)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** + * @brief Checks whether the specified EXTI line flag is set or not. + * @param __EXTI_LINE__: specifies the EXTI line flag to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) + +/** + * @brief Clears the EXTI's line pending flags. + * @param __EXTI_LINE__: specifies the EXTI lines flags to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) + +/** + * @brief Checks whether the specified EXTI line is asserted or not. + * @param __EXTI_LINE__: specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) + +/** + * @brief Clears the EXTI's line pending bits. + * @param __EXTI_LINE__: specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) + +/** + * @brief Generates a Software interrupt on selected EXTI line. + * @param __EXTI_LINE__: specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) + +/** + * @} + */ + +/* Include GPIO HAL Extension module */ +#include "stm32f0xx_hal_gpio_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup GPIO_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @addtogroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/* Initialization and de-initialization functions *****************************/ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); + +/** + * @} + */ + +/** @addtogroup GPIO_Exported_Functions_Group2 IO operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); +void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_GPIO_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h @@ -0,0 +1,636 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_gpio_ex.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Header file of GPIO HAL Extension module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_GPIO_EX_H +#define __STM32F0xx_HAL_GPIO_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIOEx GPIOEx Extended HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants + * @{ + */ + +/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection + * @{ + */ + +#if defined (STM32F030x6) +/*------------------------- STM32F030x6---------------------------*/ +/* AF 0 */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< AF0: EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< AF0: MCO Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< AF0: SPI1 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00) /*!< AF0: TIM17 Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00) /*!< AF0: SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00) /*!< AF0: SWCLK Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< AF0: TIM14 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< AF0: USART1 Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00) /*!< AF0: IR Alternate Function mapping */ + +/* AF 1 */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< AF1: TIM3 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< AF1: USART1 Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /*!< AF1: EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01) /*!< AF1: I2C1 Alternate Function mapping */ + +/* AF 2 */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< AF2: TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< AF2: TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< AF2: TIM17 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /*!< AF2: EVENTOUT Alternate Function mapping */ + +/* AF 3 */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /*!< AF3: EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03) /*!< AF3: I2C1 Alternate Function mapping */ + +/* AF 4 */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< AF4: TIM14 Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< AF4: I2C1 Alternate Function mapping */ + +/* AF 5 */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< AF5: TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< AF5: TIM17 Alternate Function mapping */ + +/* AF 6 */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06) /*!< AF6: EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06) + +#endif /* STM32F030x6 */ + +/*---------------------------------- STM32F030x8 -------------------------------------------*/ +#if defined (STM32F030x8) +/* AF 0 */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< AF0: EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< AF0: MCO Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< AF0: SPI1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00) /*!< AF0: SPI2 Alternate Function mapping */ +#define GPIO_AF0_TIM15 ((uint8_t)0x00) /*!< AF0: TIM15 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00) /*!< AF0: TIM17 Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00) /*!< AF0: SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00) /*!< AF0: SWCLK Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< AF0: TIM14 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< AF0: USART1 Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00) /*!< AF0: IR Alternate Function mapping */ + +/* AF 1 */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< AF1: TIM3 Alternate Function mapping */ +#define GPIO_AF1_TIM15 ((uint8_t)0x01) /*!< AF1: TIM15 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< AF1: USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01) /*!< AF1: USART2 Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /*!< AF1: EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_I2C2 ((uint8_t)0x01) /*!< AF1: I2C2 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01) /*!< AF1: IR Alternate Function mapping */ + +/* AF 2 */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< AF2: TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< AF2: TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< AF2: TIM17 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /*!< AF2: EVENTOUT Alternate Function mapping */ + +/* AF 3 */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /*!< AF3: EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03) /*!< AF3: I2C1 Alternate Function mapping */ +#define GPIO_AF3_TIM15 ((uint8_t)0x03) /*!< AF3: TIM15 Alternate Function mapping */ + +/* AF 4 */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< AF4: TIM14 Alternate Function mapping */ + +/* AF 5 */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< AF5: TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< AF5: TIM17 Alternate Function mapping */ + +/* AF 6 */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06) /*!< AF6: EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06) + +#endif /* STM32F030x8 */ + +#if defined (STM32F031x6) || defined (STM32F038xx) +/*--------------------------- STM32F031x6/STM32F038xx ---------------------------*/ +/* AF 0 */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< AF0: EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< AF0: MCO Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< AF0: SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00) /*!< AF0: TIM17 Alternate Function mapping */ +#define GPIO_AF0_SWDAT ((uint8_t)0x00) /*!< AF0: SWDAT Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00) /*!< AF0: SWCLK Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< AF0: TIM14 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< AF0: USART1 Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00) /*!< AF0: IR Alternate Function mapping */ + +/* AF 1 */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< AF1: TIM3 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< AF1: USART1 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01) /*!< AF1: IR Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /*!< AF1: EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01) /*!< AF1: I2C1 Alternate Function mapping */ + +/* AF 2 */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< AF2: TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< AF2: TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< AF2: TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< AF2: TIM17 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /*!< AF2: EVENTOUT Alternate Function mapping */ + +/* AF 3 */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /*!< AF3: EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03) /*!< AF3: I2C1 Alternate Function mapping */ + +/* AF 4 */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< AF4: TIM14 Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< AF4: I2C1 Alternate Function mapping */ + +/* AF 5 */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< AF5: TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< AF5: TIM17 Alternate Function mapping */ + +/* AF 6 */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06) /*!< AF6: EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06) + +#endif /* STM32F031x6 || STM32F038xx */ + +#if defined (STM32F051x8) || defined (STM32F058xx) +/*--------------------------- STM32F051x8/STM32F058xx---------------------------*/ +/* AF 0 */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< AF0: EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< AF0: MCO Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< AF0: SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00) /*!< AF0: SPI2 Alternate Function mapping */ +#define GPIO_AF0_TIM15 ((uint8_t)0x00) /*!< AF0: TIM15 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00) /*!< AF0: TIM17 Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00) /*!< AF0: SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00) /*!< AF0: SWCLK Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< AF0: TIM14 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< AF0: USART1 Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00) /*!< AF0: IR Alternate Function mapping */ +#define GPIO_AF0_CEC ((uint8_t)0x00) /*!< AF0: CEC Alternate Function mapping */ + +/* AF 1 */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< AF1: TIM3 Alternate Function mapping */ +#define GPIO_AF1_TIM15 ((uint8_t)0x01) /*!< AF1: TIM15 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< AF1: USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01) /*!< AF1: USART2 Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /*!< AF1: EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_I2C2 ((uint8_t)0x01) /*!< AF1: I2C2 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01) /*!< AF1: IR Alternate Function mapping */ +#define GPIO_AF1_CEC ((uint8_t)0x01) /*!< AF1: CEC Alternate Function mapping */ + +/* AF 2 */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< AF2: TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< AF2: TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< AF2: TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< AF2: TIM17 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /*!< AF2: EVENTOUT Alternate Function mapping */ + +/* AF 3 */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /*!< AF3: EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03) /*!< AF3: I2C1 Alternate Function mapping */ +#define GPIO_AF3_TIM15 ((uint8_t)0x03) /*!< AF3: TIM15 Alternate Function mapping */ +#define GPIO_AF3_TSC ((uint8_t)0x03) /*!< AF3: TSC Alternate Function mapping */ + +/* AF 4 */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< AF4: TIM14 Alternate Function mapping */ + +/* AF 5 */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< AF5: TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< AF5: TIM17 Alternate Function mapping */ + +/* AF 6 */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06) /*!< AF6: EVENTOUT Alternate Function mapping */ + +/* AF 7 */ +#define GPIO_AF7_COMP1 ((uint8_t)0x07) /*!< AF7: COMP1 Alternate Function mapping */ +#define GPIO_AF7_COMP2 ((uint8_t)0x07) /*!< AF7: COMP2 Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07) + +#endif /* STM32F051x8/STM32F058xx */ + +#if defined (STM32F071xB) +/*--------------------------- STM32F071xB ---------------------------*/ +/* AF 0 */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< AF0: AEVENTOUT Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00) /*!< AF0: SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00) /*!< AF0: SWCLK Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< AF0: MCO Alternate Function mapping */ +#define GPIO_AF0_CEC ((uint8_t)0x00) /*!< AF0: CEC Alternate Function mapping */ +#define GPIO_AF0_CRS ((uint8_t)0x00) /*!< AF0: CRS Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00) /*!< AF0: IR Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< AF0: SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00) /*!< AF0: SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF0_TIM1 ((uint8_t)0x00) /*!< AF0: TIM1 Alternate Function mapping */ +#define GPIO_AF0_TIM3 ((uint8_t)0x00) /*!< AF0: TIM3 Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< AF0: TIM14 Alternate Function mapping */ +#define GPIO_AF0_TIM15 ((uint8_t)0x00) /*!< AF0: TIM15 Alternate Function mapping */ +#define GPIO_AF0_TIM16 ((uint8_t)0x00) /*!< AF0: TIM16 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00) /*!< AF0: TIM17 Alternate Function mapping */ +#define GPIO_AF0_TSC ((uint8_t)0x00) /*!< AF0: TSC Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< AF0: USART1 Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00) /*!< AF0: USART2 Alternate Function mapping */ +#define GPIO_AF0_USART3 ((uint8_t)0x00) /*!< AF0: USART3 Alternate Function mapping */ +#define GPIO_AF0_USART4 ((uint8_t)0x00) /*!< AF0: USART4 Alternate Function mapping */ + +/* AF 1 */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< AF1: TIM3 Alternate Function mapping */ +#define GPIO_AF1_TIM15 ((uint8_t)0x01) /*!< AF1: TIM15 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< AF1: USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01) /*!< AF1: USART2 Alternate Function mapping */ +#define GPIO_AF1_USART3 ((uint8_t)0x01) /*!< AF1: USART3 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01) /*!< AF1: IR Alternate Function mapping */ +#define GPIO_AF1_CEC ((uint8_t)0x01) /*!< AF1: CEC Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /*!< AF1: EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_I2C2 ((uint8_t)0x01) /*!< AF1: I2C2 Alternate Function mapping */ +#define GPIO_AF1_TSC ((uint8_t)0x01) /*!< AF1: TSC Alternate Function mapping */ +#define GPIO_AF1_SPI1 ((uint8_t)0x01) /*!< AF1: SPI1 Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01) /*!< AF1: SPI2 Alternate Function mapping */ + +/* AF 2 */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< AF2: TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< AF2: TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< AF2: TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< AF2: TIM17 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /*!< AF2: EVENTOUT Alternate Function mapping */ + +/* AF 3 */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /*!< AF3: EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_TSC ((uint8_t)0x03) /*!< AF3: TSC Alternate Function mapping */ +#define GPIO_AF3_TIM15 ((uint8_t)0x03) /*!< AF3: TIM15 Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03) /*!< AF3: I2C1 Alternate Function mapping */ + +/* AF 4 */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< AF4: TIM14 Alternate Function mapping */ +#define GPIO_AF4_USART4 ((uint8_t)0x04) /*!< AF4: USART4 Alternate Function mapping */ +#define GPIO_AF4_USART3 ((uint8_t)0x04) /*!< AF4: USART3 Alternate Function mapping */ +#define GPIO_AF4_CRS ((uint8_t)0x04) /*!< AF4: CRS Alternate Function mapping */ + +/* AF 5 */ +#define GPIO_AF5_TIM15 ((uint8_t)0x05) /*!< AF5: TIM15 Alternate Function mapping */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< AF5: TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< AF5: TIM17 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< AF5: SPI2 Alternate Function mapping */ +#define GPIO_AF5_I2C2 ((uint8_t)0x05) /*!< AF5: I2C2 Alternate Function mapping */ + +/* AF 6 */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06) /*!< AF6: EVENTOUT Alternate Function mapping */ + +/* AF 7 */ +#define GPIO_AF7_COMP1 ((uint8_t)0x07) /*!< AF7: COMP1 Alternate Function mapping */ +#define GPIO_AF7_COMP2 ((uint8_t)0x07) /*!< AF7: COMP2 Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07) + +#endif /* STM32F071xB */ + + +#if defined(STM32F091xC) || defined(STM32F098xx) +/*--------------------------- STM32F091xC || STM32F098xx ------------------------------*/ +/* AF 0 */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< AF0: EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00) /*!< AF0: SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00) /*!< AF0: SWCLK Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< AF0: MCO Alternate Function mapping */ +#define GPIO_AF0_CEC ((uint8_t)0x00) /*!< AF0: CEC Alternate Function mapping */ +#define GPIO_AF0_CRS ((uint8_t)0x00) /*!< AF0: CRS Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00) /*!< AF0: IR Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< AF0: SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00) /*!< AF0: SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF0_TIM1 ((uint8_t)0x00) /*!< AF0: TIM1 Alternate Function mapping */ +#define GPIO_AF0_TIM3 ((uint8_t)0x00) /*!< AF0: TIM3 Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< AF0: TIM14 Alternate Function mapping */ +#define GPIO_AF0_TIM15 ((uint8_t)0x00) /*!< AF0: TIM15 Alternate Function mapping */ +#define GPIO_AF0_TIM16 ((uint8_t)0x00) /*!< AF0: TIM16 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00) /*!< AF0: TIM17 Alternate Function mapping */ +#define GPIO_AF0_TSC ((uint8_t)0x00) /*!< AF0: TSC Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< AF0: USART1 Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00) /*!< AF0: USART2 Alternate Function mapping */ +#define GPIO_AF0_USART3 ((uint8_t)0x00) /*!< AF0: USART3 Alternate Function mapping */ +#define GPIO_AF0_USART4 ((uint8_t)0x00) /*!< AF0: USART4 Alternate Function mapping */ +#define GPIO_AF0_USART8 ((uint8_t)0x00) /*!< AF0: USART8 Alternate Function mapping */ +#define GPIO_AF0_CAN ((uint8_t)0x00) /*!< AF0: CAN Alternate Function mapping */ + +/* AF 1 */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< AF1: TIM3 Alternate Function mapping */ +#define GPIO_AF1_TIM15 ((uint8_t)0x01) /*!< AF1: TIM15 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< AF1: USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01) /*!< AF1: USART2 Alternate Function mapping */ +#define GPIO_AF1_USART3 ((uint8_t)0x01) /*!< AF1: USART3 Alternate Function mapping */ +#define GPIO_AF1_USART4 ((uint8_t)0x01) /*!< AF1: USART4 Alternate Function mapping */ +#define GPIO_AF1_USART5 ((uint8_t)0x01) /*!< AF1: USART5 Alternate Function mapping */ +#define GPIO_AF1_USART6 ((uint8_t)0x01) /*!< AF1: USART6 Alternate Function mapping */ +#define GPIO_AF1_USART7 ((uint8_t)0x01) /*!< AF1: USART7 Alternate Function mapping */ +#define GPIO_AF1_USART8 ((uint8_t)0x01) /*!< AF1: USART8 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01) /*!< AF1: IR Alternate Function mapping */ +#define GPIO_AF1_CEC ((uint8_t)0x01) /*!< AF1: CEC Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /*!< AF1: EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_I2C2 ((uint8_t)0x01) /*!< AF1: I2C2 Alternate Function mapping */ +#define GPIO_AF1_TSC ((uint8_t)0x01) /*!< AF1: TSC Alternate Function mapping */ +#define GPIO_AF1_SPI1 ((uint8_t)0x01) /*!< AF1: SPI1 Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01) /*!< AF1: SPI2 Alternate Function mapping */ + +/* AF 2 */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< AF2: TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< AF2: TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< AF2: TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< AF2: TIM17 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /*!< AF2: EVENTOUT Alternate Function mapping */ +#define GPIO_AF2_USART5 ((uint8_t)0x02) /*!< AF2: USART5 Alternate Function mapping */ +#define GPIO_AF2_USART6 ((uint8_t)0x02) /*!< AF2: USART6 Alternate Function mapping */ +#define GPIO_AF2_USART7 ((uint8_t)0x02) /*!< AF2: USART7 Alternate Function mapping */ +#define GPIO_AF2_USART8 ((uint8_t)0x02) /*!< AF2: USART8 Alternate Function mapping */ + +/* AF 3 */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /*!< AF3: EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_TSC ((uint8_t)0x03) /*!< AF3: TSC Alternate Function mapping */ +#define GPIO_AF3_TIM15 ((uint8_t)0x03) /*!< AF3: TIM15 Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03) /*!< AF3: I2C1 Alternate Function mapping */ + +/* AF 4 */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< AF4: TIM14 Alternate Function mapping */ +#define GPIO_AF4_USART4 ((uint8_t)0x04) /*!< AF4: USART4 Alternate Function mapping */ +#define GPIO_AF4_USART3 ((uint8_t)0x04) /*!< AF4: USART3 Alternate Function mapping */ +#define GPIO_AF4_CRS ((uint8_t)0x04) /*!< AF4: CRS Alternate Function mapping */ +#define GPIO_AF4_CAN ((uint8_t)0x04) /*!< AF4: CAN Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< AF4: I2C1 Alternate Function mapping */ +#define GPIO_AF4_USART5 ((uint8_t)0x04) /*!< AF4: USART5 Alternate Function mapping */ + +/* AF 5 */ +#define GPIO_AF5_TIM15 ((uint8_t)0x05) /*!< AF5: TIM15 Alternate Function mapping */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< AF5: TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< AF5: TIM17 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< AF5: SPI2 Alternate Function mapping */ +#define GPIO_AF5_I2C2 ((uint8_t)0x05) /*!< AF5: I2C2 Alternate Function mapping */ +#define GPIO_AF5_MCO ((uint8_t)0x05) /*!< AF5: MCO Alternate Function mapping */ +#define GPIO_AF5_USART6 ((uint8_t)0x05) /*!< AF5: USART6 Alternate Function mapping */ + +/* AF 6 */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06) /*!< AF6: EVENTOUT Alternate Function mapping */ + +/* AF 7 */ +#define GPIO_AF7_COMP1 ((uint8_t)0x07) /*!< AF7: COMP1 Alternate Function mapping */ +#define GPIO_AF7_COMP2 ((uint8_t)0x07) /*!< AF7: COMP2 Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07) + +#endif /* STM32F091xC || STM32F098xx */ + +#if defined (STM32F072xB) || defined (STM32F078xx) +/*--------------------------- STM32F072xB/STM32F078xx ---------------------------*/ +/* AF 0 */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< AF0: EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00) /*!< AF0: SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00) /*!< AF0: SWCLK Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< AF0: MCO Alternate Function mapping */ +#define GPIO_AF0_CEC ((uint8_t)0x00) /*!< AF0: CEC Alternate Function mapping */ +#define GPIO_AF0_CRS ((uint8_t)0x00) /*!< AF0: CRS Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00) /*!< AF0: IR Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< AF0: SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00) /*!< AF0: SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF0_TIM1 ((uint8_t)0x00) /*!< AF0: TIM1 Alternate Function mapping */ +#define GPIO_AF0_TIM3 ((uint8_t)0x00) /*!< AF0: TIM3 Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< AF0: TIM14 Alternate Function mapping */ +#define GPIO_AF0_TIM15 ((uint8_t)0x00) /*!< AF0: TIM15 Alternate Function mapping */ +#define GPIO_AF0_TIM16 ((uint8_t)0x00) /*!< AF0: TIM16 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00) /*!< AF0: TIM17 Alternate Function mapping */ +#define GPIO_AF0_TSC ((uint8_t)0x00) /*!< AF0: TSC Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< AF0: USART1 Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00) /*!< AF0: USART2 Alternate Function mapping */ +#define GPIO_AF0_USART3 ((uint8_t)0x00) /*!< AF0: USART2 Alternate Function mapping */ +#define GPIO_AF0_USART4 ((uint8_t)0x00) /*!< AF0: USART4 Alternate Function mapping */ +#define GPIO_AF0_CAN ((uint8_t)0x00) /*!< AF0: CAN Alternate Function mapping */ + +/* AF 1 */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< AF1: TIM3 Alternate Function mapping */ +#define GPIO_AF1_TIM15 ((uint8_t)0x01) /*!< AF1: TIM15 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< AF1: USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01) /*!< AF1: USART2 Alternate Function mapping */ +#define GPIO_AF1_USART3 ((uint8_t)0x01) /*!< AF1: USART3 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01) /*!< AF1: IR Alternate Function mapping */ +#define GPIO_AF1_CEC ((uint8_t)0x01) /*!< AF1: CEC Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /*!< AF1: EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_I2C2 ((uint8_t)0x01) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_TSC ((uint8_t)0x01) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_SPI1 ((uint8_t)0x01) /*!< AF1: SPI1 Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01) /*!< AF1: SPI2 Alternate Function mapping */ + +/* AF 2 */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< AF2: TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< AF2: TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< AF2: TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< AF2: TIM17 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /*!< AF2: EVENTOUT Alternate Function mapping */ +#define GPIO_AF2_USB ((uint8_t)0x02) /*!< AF2: USB Alternate Function mapping */ + +/* AF 3 */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /*!< AF3: EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_TSC ((uint8_t)0x03) /*!< AF3: TSC Alternate Function mapping */ +#define GPIO_AF3_TIM15 ((uint8_t)0x03) /*!< AF3: TIM15 Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03) /*!< AF3: I2C1 Alternate Function mapping */ + +/* AF 4 */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< AF4: TIM14 Alternate Function mapping */ +#define GPIO_AF4_USART4 ((uint8_t)0x04) /*!< AF4: USART4 Alternate Function mapping */ +#define GPIO_AF4_USART3 ((uint8_t)0x04) /*!< AF4: USART3 Alternate Function mapping */ +#define GPIO_AF4_CRS ((uint8_t)0x04) /*!< AF4: CRS Alternate Function mapping */ +#define GPIO_AF4_CAN ((uint8_t)0x04) /*!< AF4: CAN Alternate Function mapping */ + +/* AF 5 */ +#define GPIO_AF5_TIM15 ((uint8_t)0x05) /*!< AF5: TIM15 Alternate Function mapping */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< AF5: TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< AF5: TIM17 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< AF5: SPI2 Alternate Function mapping */ +#define GPIO_AF5_I2C2 ((uint8_t)0x05) /*!< AF5: I2C2 Alternate Function mapping */ + +/* AF 6 */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06) /*!< AF6: EVENTOUT Alternate Function mapping */ + +/* AF 7 */ +#define GPIO_AF7_COMP1 ((uint8_t)0x07) /*!< AF7: COMP1 Alternate Function mapping */ +#define GPIO_AF7_COMP2 ((uint8_t)0x07) /*!< AF7: COMP2 Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07) + +#endif /* STM32F072xB || STM32F078xx */ + +#if defined (STM32F042x6) || defined (STM32F048xx) +/*--------------------------- STM32F042x6/STM32F048xx ---------------------------*/ +/* AF 0 */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< AF0: EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_CEC ((uint8_t)0x00) /*!< AF0: CEC Alternate Function mapping */ +#define GPIO_AF0_CRS ((uint8_t)0x00) /*!< AF0: CRS Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00) /*!< AF0: IR Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< AF0: MCO Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< AF0: SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00) /*!< AF0: SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00) /*!< AF0: SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00) /*!< AF0: SWCLK Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< AF0: TIM14 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00) /*!< AF0: TIM17 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< AF0: USART1 Alternate Function mapping */ + +/* AF 1 */ +#define GPIO_AF1_CEC ((uint8_t)0x01) /*!< AF1: CEC Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /*!< AF1: EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01) /*!< AF1: IR Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< AF1: USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01) /*!< AF1: USART2 Alternate Function mapping */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< AF1: TIM3 Alternate Function mapping */ + +/* AF 2 */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /*!< AF2: EVENTOUT Alternate Function mapping */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< AF2: TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< AF2: TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< AF2: TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< AF2: TIM17 Alternate Function mapping */ +#define GPIO_AF2_USB ((uint8_t)0x02) /*!< AF2: USB Alternate Function mapping */ + +/* AF 3 */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /*!< AF3: EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03) /*!< AF3: I2C1 Alternate Function mapping */ +#define GPIO_AF3_TSC ((uint8_t)0x03) /*!< AF3: TSC Alternate Function mapping */ + +/* AF 4 */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< AF4: TIM14 Alternate Function mapping */ +#define GPIO_AF4_CAN ((uint8_t)0x04) /*!< AF4: CAN Alternate Function mapping */ +#define GPIO_AF4_CRS ((uint8_t)0x04) /*!< AF4: CRS Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< AF4: I2C1 Alternate Function mapping */ + +/* AF 5 */ +#define GPIO_AF5_MCO ((uint8_t)0x05) /*!< AF5: MCO Alternate Function mapping */ +#define GPIO_AF5_I2C1 ((uint8_t)0x05) /*!< AF5: I2C1 Alternate Function mapping */ +#define GPIO_AF5_I2C2 ((uint8_t)0x05) /*!< AF5: I2C2 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< AF5: SPI2 Alternate Function mapping */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< AF5: TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< AF5: TIM17 Alternate Function mapping */ +#define GPIO_AF5_USB ((uint8_t)0x05) /*!< AF5: USB Alternate Function mapping */ + +/* AF 6 */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06) /*!< AF6: EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06) + +#endif /* STM32F042x6 || STM32F048xx */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros + * @{ + */ + +/** @defgroup GPIOEx_Get_Port_Index GPIOEx_Get Port Index +* @{ + */ +#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) +#define GET_GPIO_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U :\ + ((__GPIOx__) == (GPIOE))? 4U : 5U) +#endif + +#if defined (STM32F030x6) || defined (STM32F030x8) || \ + defined (STM32F051x8) || defined (STM32F058xx) +#define GET_GPIO_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U : 5U) +#endif + +#if defined (STM32F031x6) || defined (STM32F038xx) || \ + defined (STM32F042x6) || defined (STM32F048xx) +#define GET_GPIO_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U : 5U) +#endif + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_GPIO_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h @@ -0,0 +1,563 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_i2c.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Header file of I2C HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_I2C_H +#define __STM32F0xx_HAL_I2C_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Types I2C Exported Types + * @{ + */ + +/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition + * @brief I2C Configuration Structure definition + * @{ + */ +typedef struct +{ + uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value. + This parameter calculated by referring to I2C initialization + section in Reference manual */ + + uint32_t OwnAddress1; /*!< Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. + This parameter can be a value of @ref I2C_addressing_mode */ + + uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. + This parameter can be a value of @ref I2C_dual_addressing_mode */ + + uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected + This parameter can be a 7-bit address. */ + + uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected + This parameter can be a value of @ref I2C_own_address2_masks. */ + + uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. + This parameter can be a value of @ref I2C_general_call_addressing_mode. */ + + uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. + This parameter can be a value of @ref I2C_nostretch_mode */ + +}I2C_InitTypeDef; + +/** + * @} + */ + +/** @defgroup HAL_state_structure_definition HAL state structure definition + * @brief HAL State structure definition + * @{ + */ + +typedef enum +{ + HAL_I2C_STATE_RESET = 0x00, /*!< I2C not yet initialized or disabled */ + HAL_I2C_STATE_READY = 0x01, /*!< I2C initialized and ready for use */ + HAL_I2C_STATE_BUSY = 0x02, /*!< I2C internal process is ongoing */ + HAL_I2C_STATE_MASTER_BUSY_TX = 0x12, /*!< Master Data Transmission process is ongoing */ + HAL_I2C_STATE_MASTER_BUSY_RX = 0x22, /*!< Master Data Reception process is ongoing */ + HAL_I2C_STATE_SLAVE_BUSY_TX = 0x32, /*!< Slave Data Transmission process is ongoing */ + HAL_I2C_STATE_SLAVE_BUSY_RX = 0x42, /*!< Slave Data Reception process is ongoing */ + HAL_I2C_STATE_MEM_BUSY_TX = 0x52, /*!< Memory Data Transmission process is ongoing */ + HAL_I2C_STATE_MEM_BUSY_RX = 0x62, /*!< Memory Data Reception process is ongoing */ + HAL_I2C_STATE_TIMEOUT = 0x03, /*!< Timeout state */ + HAL_I2C_STATE_ERROR = 0x04 /*!< Reception process is ongoing */ + +}HAL_I2C_StateTypeDef; + +/** + * @} + */ + +/** @defgroup I2C_Error_Code_structure_definition I2C Error Code structure definition + * @brief I2C Error Code structure definition + * @{ + */ + +typedef enum +{ + HAL_I2C_ERROR_NONE = 0x00, /*!< No error */ + HAL_I2C_ERROR_BERR = 0x01, /*!< BERR error */ + HAL_I2C_ERROR_ARLO = 0x02, /*!< ARLO error */ + HAL_I2C_ERROR_AF = 0x04, /*!< AF error */ + HAL_I2C_ERROR_OVR = 0x08, /*!< OVR error */ + HAL_I2C_ERROR_DMA = 0x10, /*!< DMA transfer error */ + HAL_I2C_ERROR_TIMEOUT = 0x20, /*!< Timeout error */ + HAL_I2C_ERROR_SIZE = 0x40 /*!< Size Management error */ +}HAL_I2C_ErrorTypeDef; + +/** + * @} + */ + +/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition + * @brief I2C handle Structure definition + * @{ + */ + +typedef struct +{ + I2C_TypeDef *Instance; /*!< I2C registers base address */ + + I2C_InitTypeDef Init; /*!< I2C communication parameters */ + + uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ + + uint16_t XferSize; /*!< I2C transfer size */ + + __IO uint16_t XferCount; /*!< I2C transfer counter */ + + DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ + + HAL_LockTypeDef Lock; /*!< I2C locking object */ + + __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ + + __IO HAL_I2C_ErrorTypeDef ErrorCode; /* I2C Error code */ + +}I2C_HandleTypeDef; +/** + * @} + */ + +/** + * @} + */ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Constants I2C Exported Constants + * @{ + */ + +/** @defgroup I2C_addressing_mode I2C addressing mode + * @{ + */ +#define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001) +#define I2C_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002) + +#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \ + ((MODE) == I2C_ADDRESSINGMODE_10BIT)) +/** + * @} + */ + +/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode + * @{ + */ + +#define I2C_DUALADDRESS_DISABLED ((uint32_t)0x00000000) +#define I2C_DUALADDRESS_ENABLED I2C_OAR2_OA2EN + +#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLED) || \ + ((ADDRESS) == I2C_DUALADDRESS_ENABLED)) +/** + * @} + */ + +/** @defgroup I2C_own_address2_masks I2C own address2 masks + * @{ + */ + +#define I2C_OA2_NOMASK ((uint8_t)0x00) +#define I2C_OA2_MASK01 ((uint8_t)0x01) +#define I2C_OA2_MASK02 ((uint8_t)0x02) +#define I2C_OA2_MASK03 ((uint8_t)0x03) +#define I2C_OA2_MASK04 ((uint8_t)0x04) +#define I2C_OA2_MASK05 ((uint8_t)0x05) +#define I2C_OA2_MASK06 ((uint8_t)0x06) +#define I2C_OA2_MASK07 ((uint8_t)0x07) + +#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \ + ((MASK) == I2C_OA2_MASK01) || \ + ((MASK) == I2C_OA2_MASK02) || \ + ((MASK) == I2C_OA2_MASK03) || \ + ((MASK) == I2C_OA2_MASK04) || \ + ((MASK) == I2C_OA2_MASK05) || \ + ((MASK) == I2C_OA2_MASK06) || \ + ((MASK) == I2C_OA2_MASK07)) +/** + * @} + */ + +/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode + * @{ + */ +#define I2C_GENERALCALL_DISABLED ((uint32_t)0x00000000) +#define I2C_GENERALCALL_ENABLED I2C_CR1_GCEN + +#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLED) || \ + ((CALL) == I2C_GENERALCALL_ENABLED)) +/** + * @} + */ + +/** @defgroup I2C_nostretch_mode I2C nostretch mode + * @{ + */ +#define I2C_NOSTRETCH_DISABLED ((uint32_t)0x00000000) +#define I2C_NOSTRETCH_ENABLED I2C_CR1_NOSTRETCH + +#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLED) || \ + ((STRETCH) == I2C_NOSTRETCH_ENABLED)) +/** + * @} + */ + +/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size + * @{ + */ +#define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001) +#define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000002) + +#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ + ((SIZE) == I2C_MEMADD_SIZE_16BIT)) +/** + * @} + */ + +/** @defgroup I2C_ReloadEndMode_definition I2C ReloadEndMode definition + * @{ + */ + +#define I2C_RELOAD_MODE I2C_CR2_RELOAD +#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND +#define I2C_SOFTEND_MODE ((uint32_t)0x00000000) + +#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \ + ((MODE) == I2C_AUTOEND_MODE) || \ + ((MODE) == I2C_SOFTEND_MODE)) +/** + * @} + */ + +/** @defgroup I2C_StartStopMode_definition I2C StartStopMode definition + * @{ + */ + +#define I2C_NO_STARTSTOP ((uint32_t)0x00000000) +#define I2C_GENERATE_STOP I2C_CR2_STOP +#define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) +#define I2C_GENERATE_START_WRITE I2C_CR2_START + +#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \ + ((REQUEST) == I2C_GENERATE_START_READ) || \ + ((REQUEST) == I2C_GENERATE_START_WRITE) || \ + ((REQUEST) == I2C_NO_STARTSTOP)) + +/** + * @} + */ + +/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition + * @brief I2C Interrupt definition + * Elements values convention: 0xXXXXXXXX + * - XXXXXXXX : Interrupt control mask + * @{ + */ +#define I2C_IT_ERRI I2C_CR1_ERRIE +#define I2C_IT_TCI I2C_CR1_TCIE +#define I2C_IT_STOPI I2C_CR1_STOPIE +#define I2C_IT_NACKI I2C_CR1_NACKIE +#define I2C_IT_ADDRI I2C_CR1_ADDRIE +#define I2C_IT_RXI I2C_CR1_RXIE +#define I2C_IT_TXI I2C_CR1_TXIE + +/** + * @} + */ + + +/** @defgroup I2C_Flag_definition I2C Flag definition + * @{ + */ + +#define I2C_FLAG_TXE I2C_ISR_TXE +#define I2C_FLAG_TXIS I2C_ISR_TXIS +#define I2C_FLAG_RXNE I2C_ISR_RXNE +#define I2C_FLAG_ADDR I2C_ISR_ADDR +#define I2C_FLAG_AF I2C_ISR_NACKF +#define I2C_FLAG_STOPF I2C_ISR_STOPF +#define I2C_FLAG_TC I2C_ISR_TC +#define I2C_FLAG_TCR I2C_ISR_TCR +#define I2C_FLAG_BERR I2C_ISR_BERR +#define I2C_FLAG_ARLO I2C_ISR_ARLO +#define I2C_FLAG_OVR I2C_ISR_OVR +#define I2C_FLAG_PECERR I2C_ISR_PECERR +#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT +#define I2C_FLAG_ALERT I2C_ISR_ALERT +#define I2C_FLAG_BUSY I2C_ISR_BUSY +#define I2C_FLAG_DIR I2C_ISR_DIR +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Macros I2C Exported Macros + * @{ + */ + +/** @brief Reset I2C handle state + * @param __HANDLE__: I2C handle. + * @retval None + */ +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) + +/** @brief Enables or disables the specified I2C interrupts. + * @param __HANDLE__: specifies the I2C Handle. + * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. + * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * This parameter can be one of the following values: + * @arg I2C_IT_ERRI: Errors interrupt enable + * @arg I2C_IT_TCI: Transfer complete interrupt enable + * @arg I2C_IT_STOPI: STOP detection interrupt enable + * @arg I2C_IT_NACKI: NACK received interrupt enable + * @arg I2C_IT_ADDRI: Address match interrupt enable + * @arg I2C_IT_RXI: RX interrupt enable + * @arg I2C_IT_TXI: TX interrupt enable + * + * @retval None + */ + +#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) +#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) + +/** @brief Checks if the specified I2C interrupt source is enabled or disabled. + * @param __HANDLE__: specifies the I2C Handle. + * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. + * @param __INTERRUPT__: specifies the I2C interrupt source to check. + * This parameter can be one of the following values: + * @arg I2C_IT_ERRI: Errors interrupt enable + * @arg I2C_IT_TCI: Transfer complete interrupt enable + * @arg I2C_IT_STOPI: STOP detection interrupt enable + * @arg I2C_IT_NACKI: NACK received interrupt enable + * @arg I2C_IT_ADDRI: Address match interrupt enable + * @arg I2C_IT_RXI: RX interrupt enable + * @arg I2C_IT_TXI: TX interrupt enable + * + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Checks whether the specified I2C flag is set or not. + * @param __HANDLE__: specifies the I2C Handle. + * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg I2C_FLAG_TXE: Transmit data register empty + * @arg I2C_FLAG_TXIS: Transmit interrupt status + * @arg I2C_FLAG_RXNE: Receive data register not empty + * @arg I2C_FLAG_ADDR: Address matched (slave mode) + * @arg I2C_FLAG_AF: Acknowledge failure received flag + * @arg I2C_FLAG_STOPF: STOP detection flag + * @arg I2C_FLAG_TC: Transfer complete (master mode) + * @arg I2C_FLAG_TCR: Transfer complete reload + * @arg I2C_FLAG_BERR: Bus error + * @arg I2C_FLAG_ARLO: Arbitration lost + * @arg I2C_FLAG_OVR: Overrun/Underrun + * @arg I2C_FLAG_PECERR: PEC error in reception + * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag + * @arg I2C_FLAG_ALERT: SMBus alert + * @arg I2C_FLAG_BUSY: Bus busy + * @arg I2C_FLAG_DIR: Transfer direction (slave mode) + * + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) + +/** @brief Clears the I2C pending flags which are cleared by writing 1 in a specific bit. + * @param __HANDLE__: specifies the I2C Handle. + * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. + * @param __FLAG__: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg I2C_FLAG_ADDR: Address matched (slave mode) + * @arg I2C_FLAG_AF: Acknowledge failure flag + * @arg I2C_FLAG_STOPF: STOP detection flag + * @arg I2C_FLAG_BERR: Bus error + * @arg I2C_FLAG_ARLO: Arbitration lost + * @arg I2C_FLAG_OVR: Overrun/Underrun + * @arg I2C_FLAG_PECERR: PEC error in reception + * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag + * @arg I2C_FLAG_ALERT: SMBus alert + * + * @retval None + */ +#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) + + +#define __HAL_I2C_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE) +#define __HAL_I2C_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE) + +#define __HAL_I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) + +#define __HAL_I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8))) +#define __HAL_I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF)))) + +#define __HAL_I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) + +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF) +#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF) +/** + * @} + */ + +/* Include I2C HAL Extended module */ +#include "stm32f0xx_hal_i2c_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2C_Exported_Functions + * @{ + */ + +/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization/de-initialization functions **********************************/ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); + +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ + + /******* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); + + /******* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + + /******* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + + /******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); + +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State and Errors functions + * @{ + */ + +/* Peripheral State and Errors functions **************************************/ +HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); +uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F0xx_HAL_I2C_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h @@ -0,0 +1,130 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_i2c_ex.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Header file of I2C HAL Extension module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_I2C_EX_H +#define __STM32F0xx_HAL_I2C_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2CEx I2CEx Extended HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup I2CEx_Exported_Constants I2CEx Exported Constants + * @{ + */ + +/** @defgroup I2CEx_Analog_Filter I2CEx Analog Filter + * @{ + */ +#define I2C_ANALOGFILTER_ENABLED ((uint32_t)0x00000000) +#define I2C_ANALOGFILTER_DISABLED I2C_CR1_ANFOFF + +#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLED) || \ + ((FILTER) == I2C_ANALOGFILTER_DISABLED)) +/** + * @} + */ + +/** @defgroup I2CEx_Digital_Filter I2CEx Digital Filter + * @{ + */ +#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup I2CEx_Exported_Functions + * @{ + */ + +/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions + * @brief Extended features functions + * @{ + */ + +/* Peripheral Control functions ************************************************/ +HAL_StatusTypeDef HAL_I2CEx_AnalogFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); +HAL_StatusTypeDef HAL_I2CEx_DigitalFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); +HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_I2C_EX_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2s.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2s.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2s.h @@ -0,0 +1,445 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_i2s.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Header file of I2S HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_I2S_H +#define __STM32F0xx_HAL_I2S_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(STM32F031x6) || defined(STM32F038xx) || \ + defined(STM32F051x8) || defined(STM32F058xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F042x6) || defined(STM32F048xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2S + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup I2S_Exported_Types I2S Exported Types + * @{ + */ + +/** + * @brief I2S Init structure definition + */ +typedef struct +{ + uint32_t Mode; /*!< Specifies the I2S operating mode. + This parameter can be a value of @ref I2S_Mode */ + + uint32_t Standard; /*!< Specifies the standard used for the I2S communication. + This parameter can be a value of @ref I2S_Standard */ + + uint32_t DataFormat; /*!< Specifies the data format for the I2S communication. + This parameter can be a value of @ref I2S_Data_Format */ + + uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. + This parameter can be a value of @ref I2S_MCLK_Output */ + + uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref I2S_Audio_Frequency */ + + uint32_t CPOL; /*!< Specifies the idle state of the I2S clock. + This parameter can be a value of @ref I2S_Clock_Polarity */ +}I2S_InitTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_I2S_STATE_RESET = 0x00, /*!< I2S not yet initialized or disabled */ + HAL_I2S_STATE_READY = 0x01, /*!< I2S initialized and ready for use */ + HAL_I2S_STATE_BUSY = 0x02, /*!< I2S internal process is ongoing */ + HAL_I2S_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */ + HAL_I2S_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */ + HAL_I2S_STATE_PAUSE = 0x06, /*!< I2S pause state: used in case of DMA */ + HAL_I2S_STATE_ERROR = 0x07 /*!< I2S error state */ +}HAL_I2S_StateTypeDef; + +/** + * @brief HAL I2S Error Code structure definition + */ +typedef enum +{ + HAL_I2S_ERROR_NONE = 0x00, /*!< No error */ + HAL_I2S_ERROR_TIMEOUT = 0x01, /*!< Timeout error */ + HAL_I2S_ERROR_OVR = 0x02, /*!< OVR error */ + HAL_I2S_ERROR_UDR = 0x04, /*!< UDR error */ + HAL_I2S_ERROR_DMA = 0x08, /*!< DMA transfer error */ + HAL_I2S_ERROR_UNKNOW = 0x10 /*!< Unknow Error error */ +}HAL_I2S_ErrorTypeDef; + +/** + * @brief I2S handle Structure definition + */ +typedef struct +{ + SPI_TypeDef *Instance; /* I2S registers base address */ + + I2S_InitTypeDef Init; /* I2S communication parameters */ + + uint16_t *pTxBuffPtr; /* Pointer to I2S Tx transfer buffer */ + + __IO uint16_t TxXferSize; /* I2S Tx transfer size */ + + __IO uint16_t TxXferCount; /* I2S Tx transfer Counter */ + + uint16_t *pRxBuffPtr; /* Pointer to I2S Rx transfer buffer */ + + __IO uint16_t RxXferSize; /* I2S Rx transfer size */ + + __IO uint16_t RxXferCount; /* I2S Rx transfer counter + (This field is initialized at the + same value as transfer size at the + beginning of the transfer and + decremented when a sample is received. + NbSamplesReceived = RxBufferSize-RxBufferCount) */ + + DMA_HandleTypeDef *hdmatx; /* I2S Tx DMA handle parameters */ + + DMA_HandleTypeDef *hdmarx; /* I2S Rx DMA handle parameters */ + + __IO HAL_LockTypeDef Lock; /* I2S locking object */ + + __IO HAL_I2S_StateTypeDef State; /* I2S communication state */ + + __IO HAL_I2S_ErrorTypeDef ErrorCode; /* I2S Error code */ + +}I2S_HandleTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2S_Exported_Constants I2S Exported Constants + * @{ + */ + +/** @defgroup I2S_Mode I2S Mode + * @{ + */ +#define I2S_MODE_SLAVE_TX ((uint32_t)0x00000000) +#define I2S_MODE_SLAVE_RX ((uint32_t)0x00000100) +#define I2S_MODE_MASTER_TX ((uint32_t)0x00000200) +#define I2S_MODE_MASTER_RX ((uint32_t)0x00000300) + +#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \ + ((MODE) == I2S_MODE_SLAVE_RX) || \ + ((MODE) == I2S_MODE_MASTER_TX)|| \ + ((MODE) == I2S_MODE_MASTER_RX)) +/** + * @} + */ + +/** @defgroup I2S_Standard I2S Standard + * @{ + */ +#define I2S_STANDARD_PHILIPS ((uint32_t)0x00000000) +#define I2S_STANDARD_MSB ((uint32_t)0x00000010) +#define I2S_STANDARD_LSB ((uint32_t)0x00000020) +#define I2S_STANDARD_PCM_SHORT ((uint32_t)0x00000030) +#define I2S_STANDARD_PCM_LONG ((uint32_t)0x000000B0) + +#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \ + ((STANDARD) == I2S_STANDARD_MSB) || \ + ((STANDARD) == I2S_STANDARD_LSB) || \ + ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \ + ((STANDARD) == I2S_STANDARD_PCM_LONG)) +/** + * @} + */ + +/** @defgroup I2S_Data_Format I2S Data Format + * @{ + */ +#define I2S_DATAFORMAT_16B ((uint32_t)0x00000000) +#define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t)0x00000001) +#define I2S_DATAFORMAT_24B ((uint32_t)0x00000003) +#define I2S_DATAFORMAT_32B ((uint32_t)0x00000005) + +#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \ + ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \ + ((FORMAT) == I2S_DATAFORMAT_24B) || \ + ((FORMAT) == I2S_DATAFORMAT_32B)) +/** + * @} + */ + +/** @defgroup I2S_MCLK_Output I2S MCLK Output + * @{ + */ +#define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE) +#define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000) + +#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \ + ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE)) +/** + * @} + */ + +/** @defgroup I2S_Audio_Frequency I2S Audio Frequency + * @{ + */ +#define I2S_AUDIOFREQ_192K ((uint32_t)192000) +#define I2S_AUDIOFREQ_96K ((uint32_t)96000) +#define I2S_AUDIOFREQ_48K ((uint32_t)48000) +#define I2S_AUDIOFREQ_44K ((uint32_t)44100) +#define I2S_AUDIOFREQ_32K ((uint32_t)32000) +#define I2S_AUDIOFREQ_22K ((uint32_t)22050) +#define I2S_AUDIOFREQ_16K ((uint32_t)16000) +#define I2S_AUDIOFREQ_11K ((uint32_t)11025) +#define I2S_AUDIOFREQ_8K ((uint32_t)8000) +#define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2) + +#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \ + ((FREQ) <= I2S_AUDIOFREQ_192K)) || \ + ((FREQ) == I2S_AUDIOFREQ_DEFAULT)) +/** + * @} + */ + +/** @defgroup I2S_Clock_Polarity I2S Clock Polarity + * @{ + */ +#define I2S_CPOL_LOW ((uint32_t)0x00000000) +#define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL) + +#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \ + ((CPOL) == I2S_CPOL_HIGH)) +/** + * @} + */ + +/** @defgroup I2S_Interrupt_configuration_definition I2S Interrupt configuration definition + * @{ + */ +#define I2S_IT_TXE SPI_CR2_TXEIE +#define I2S_IT_RXNE SPI_CR2_RXNEIE +#define I2S_IT_ERR SPI_CR2_ERRIE +/** + * @} + */ + +/** @defgroup I2S_Flag_definition I2S Flag definition + * @{ + */ +#define I2S_FLAG_TXE SPI_SR_TXE +#define I2S_FLAG_RXNE SPI_SR_RXNE + +#define I2S_FLAG_UDR SPI_SR_UDR +#define I2S_FLAG_OVR SPI_SR_OVR +#define I2S_FLAG_FRE SPI_SR_FRE + +#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE +#define I2S_FLAG_BSY SPI_SR_BSY +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup I2S_Exported_macros I2S Exported Macros + * @{ + */ + +/** @brief Reset I2S handle state + * @param __HANDLE__: I2S handle. + * @retval None + */ +#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET) + +/** @brief Enable or disable the specified SPI peripheral (in I2S mode). + * @param __HANDLE__: specifies the I2S Handle. + * @retval None + */ +#define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE) +#define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= (uint16_t)(~SPI_I2SCFGR_I2SE)) + +/** @brief Enable or disable the specified I2S interrupts. + * @param __HANDLE__: specifies the I2S Handle. + * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * This parameter can be one of the following values: + * @arg I2S_IT_TXE: Tx buffer empty interrupt enable + * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable + * @arg I2S_IT_ERR: Error interrupt enable + * @retval None + */ +#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__)) +#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (uint16_t)(~(__INTERRUPT__))) + +/** @brief Checks if the specified I2S interrupt source is enabled or disabled. + * @param __HANDLE__: specifies the I2S Handle. + * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral. + * @param __INTERRUPT__: specifies the I2S interrupt source to check. + * This parameter can be one of the following values: + * @arg I2S_IT_TXE: Tx buffer empty interrupt enable + * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable + * @arg I2S_IT_ERR: Error interrupt enable + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Checks whether the specified I2S flag is set or not. + * @param __HANDLE__: specifies the I2S Handle. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg I2S_FLAG_RXNE: Receive buffer not empty flag + * @arg I2S_FLAG_TXE: Transmit buffer empty flag + * @arg I2S_FLAG_UDR: Underrun flag + * @arg I2S_FLAG_OVR: Overrun flag + * @arg I2S_FLAG_FRE: Frame error flag + * @arg I2S_FLAG_CHSIDE: Channel Side flag + * @arg I2S_FLAG_BSY: Busy flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) + +/** @brief Clears the I2S OVR pending flag. + * @param __HANDLE__: specifies the I2S Handle. + * @retval None + */ +#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{__IO uint32_t tmpreg = (__HANDLE__)->Instance->DR;\ + tmpreg = (__HANDLE__)->Instance->SR;}while(0) +/** @brief Clears the I2S UDR pending flag. + * @param __HANDLE__: specifies the I2S Handle. + * @retval None + */ +#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)((__HANDLE__)->Instance->SR) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2S_Exported_Functions + * @{ + */ + +/** @addtogroup I2S_Exported_Functions_Group1 + * @{ + */ +/* Initialization/de-initialization functions **********************************/ +HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s); +HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s); +void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s); +void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s); +/** + * @} + */ + +/** @addtogroup I2S_Exported_Functions_Group2 + * @{ + */ +/* I/O operation functions ***************************************************/ + /* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout); + + /* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); +void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s); + +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s); +HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s); +HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s); + +/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/ +void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s); +void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s); +void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s); +void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s); +void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s); +/** + * @} + */ + +/** @addtogroup I2S_Exported_Functions_Group3 + * @{ + */ +/* Peripheral Control and State functions ************************************/ +HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s); +HAL_I2S_ErrorTypeDef HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); +/** + * @} + */ + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined(STM32F031x6) || defined(STM32F038xx) || */ + /* defined(STM32F051x8) || defined(STM32F058xx) || */ + /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) ||*/ + /* defined(STM32F042x6) || defined(STM32F048xx) || */ + /* defined(STM32F091xC) || defined(STM32F098xx) */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F0xx_HAL_I2S_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_irda.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_irda.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_irda.h @@ -0,0 +1,630 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_irda.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief This file contains all the functions prototypes for the IRDA + * firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_IRDA_H +#define __STM32F0xx_HAL_IRDA_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if !defined(STM32F030x6) && !defined(STM32F030x8) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup IRDA + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup IRDA_Exported_Types IRDA Exported Types + * @{ + */ + +/** + * @brief IRDA Init Structure definition + */ +typedef struct +{ + uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate. + The baud rate register is computed using the following formula: + Baud Rate Register = ((PCLKx) / ((hirda->Init.BaudRate))) */ + + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref IRDAEx_Word_Length */ + + uint16_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref IRDA_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint16_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref IRDA_Mode */ + + uint8_t Prescaler; /*!< Specifies the Prescaler value for dividing the UART/USART source clock + to achieve low-power frequency. + @note Prescaler value 0 is forbidden */ + + uint16_t PowerMode; /*!< Specifies the IRDA power mode. + This parameter can be a value of @ref IRDA_Low_Power */ +}IRDA_InitTypeDef; + +/** + * @brief HAL IRDA State structures definition + */ +typedef enum +{ + HAL_IRDA_STATE_RESET = 0x00, /*!< Peripheral is not initialized */ + HAL_IRDA_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ + HAL_IRDA_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ + HAL_IRDA_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ + HAL_IRDA_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ + HAL_IRDA_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ + HAL_IRDA_STATE_TIMEOUT = 0x03, /*!< Timeout state */ + HAL_IRDA_STATE_ERROR = 0x04 /*!< Error */ +}HAL_IRDA_StateTypeDef; + +/** + * @brief HAL IRDA Error Code structure definition + */ +typedef enum +{ + HAL_IRDA_ERROR_NONE = 0x00, /*!< No error */ + HAL_IRDA_ERROR_PE = 0x01, /*!< Parity error */ + HAL_IRDA_ERROR_NE = 0x02, /*!< Noise error */ + HAL_IRDA_ERROR_FE = 0x04, /*!< frame error */ + HAL_IRDA_ERROR_ORE = 0x08, /*!< Overrun error */ + HAL_IRDA_ERROR_DMA = 0x10 /*!< DMA transfer error */ +}HAL_IRDA_ErrorTypeDef; + +/** + * @brief IRDA clock sources definition + */ +typedef enum +{ + IRDA_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */ + IRDA_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */ + IRDA_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */ + IRDA_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */ + IRDA_CLOCKSOURCE_UNDEFINED = 0x10 /*!< undefined clock source */ +}IRDA_ClockSourceTypeDef; + +/** + * @brief IRDA handle Structure definition + */ +typedef struct +{ + USART_TypeDef *Instance; /* USART registers base address */ + + IRDA_InitTypeDef Init; /* IRDA communication parameters */ + + uint8_t *pTxBuffPtr; /* Pointer to IRDA Tx transfer Buffer */ + + uint16_t TxXferSize; /* IRDA Tx Transfer size */ + + uint16_t TxXferCount; /* IRDA Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /* Pointer to IRDA Rx transfer Buffer */ + + uint16_t RxXferSize; /* IRDA Rx Transfer size */ + + uint16_t RxXferCount; /* IRDA Rx Transfer Counter */ + + uint16_t Mask; /* USART RX RDR register mask */ + + DMA_HandleTypeDef *hdmatx; /* IRDA Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /* IRDA Rx DMA Handle parameters */ + + HAL_LockTypeDef Lock; /* Locking object */ + + HAL_IRDA_StateTypeDef State; /* IRDA communication state */ + + HAL_IRDA_ErrorTypeDef ErrorCode; /* IRDA Error code */ + +}IRDA_HandleTypeDef; + +/** + * @brief IRDA Configuration enumeration values definition + */ +typedef enum +{ + IRDA_BAUDRATE = 0x00, + IRDA_PARITY = 0x01, + IRDA_WORDLENGTH = 0x02, + IRDA_MODE = 0x03, + IRDA_PRESCALER = 0x04, + IRDA_POWERMODE = 0x05 +}IRDA_ControlTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup IRDA_Exported_Constants IRDA Exported constants + * @{ + */ + +/** @defgroup IRDA_Parity IRDA Parity + * @{ + */ +#define IRDA_PARITY_NONE ((uint16_t)0x0000) +#define IRDA_PARITY_EVEN ((uint16_t)USART_CR1_PCE) +#define IRDA_PARITY_ODD ((uint16_t)(USART_CR1_PCE | USART_CR1_PS)) +#define IS_IRDA_PARITY(PARITY) (((PARITY) == IRDA_PARITY_NONE) || \ + ((PARITY) == IRDA_PARITY_EVEN) || \ + ((PARITY) == IRDA_PARITY_ODD)) +/** + * @} + */ + + +/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode + * @{ + */ +#define IRDA_MODE_RX ((uint16_t)USART_CR1_RE) +#define IRDA_MODE_TX ((uint16_t)USART_CR1_TE) +#define IRDA_MODE_TX_RX ((uint16_t)(USART_CR1_TE |USART_CR1_RE)) +#define IS_IRDA_TX_RX_MODE(MODE) ((((MODE) & ((uint16_t)(~((uint16_t)(IRDA_MODE_TX_RX))))) == (uint16_t)0x00) && ((MODE) != (uint16_t)0x00)) +/** + * @} + */ + +/** @defgroup IRDA_Low_Power IRDA Low Power + * @{ + */ +#define IRDA_POWERMODE_NORMAL ((uint16_t)0x0000) +#define IRDA_POWERMODE_LOWPOWER ((uint16_t)USART_CR3_IRLP) +#define IS_IRDA_POWERMODE(MODE) (((MODE) == IRDA_POWERMODE_LOWPOWER) || \ + ((MODE) == IRDA_POWERMODE_NORMAL)) +/** + * @} + */ + + /** @defgroup IRDA_State IRDA State + * @{ + */ +#define IRDA_STATE_DISABLE ((uint16_t)0x0000) +#define IRDA_STATE_ENABLE ((uint16_t)USART_CR1_UE) +#define IS_IRDA_STATE(STATE) (((STATE) == IRDA_STATE_DISABLE) || \ + ((STATE) == IRDA_STATE_ENABLE)) +/** + * @} + */ + + /** @defgroup IRDA_Mode IRDA Mode + * @{ + */ +#define IRDA_MODE_DISABLE ((uint16_t)0x0000) +#define IRDA_MODE_ENABLE ((uint16_t)USART_CR3_IREN) +#define IS_IRDA_MODE(STATE) (((STATE) == IRDA_MODE_DISABLE) || \ + ((STATE) == IRDA_MODE_ENABLE)) +/** + * @} + */ + +/** @defgroup IRDA_One_Bit IRDA One Bit Sampling + * @{ + */ +#define IRDA_ONE_BIT_SAMPLE_DISABLED ((uint16_t)0x00000000) +#define IRDA_ONE_BIT_SAMPLE_ENABLED ((uint16_t)USART_CR3_ONEBIT) +#define IS_IRDA_ONEBIT_SAMPLE(ONEBIT) (((ONEBIT) == IRDA_ONE_BIT_SAMPLE_DISABLED) || \ + ((ONEBIT) == IRDA_ONE_BIT_SAMPLE_ENABLED)) +/** + * @} + */ + +/** @defgroup IRDA_DMA_Tx IRDA DMA Tx + * @{ + */ +#define IRDA_DMA_TX_DISABLE ((uint16_t)0x00000000) +#define IRDA_DMA_TX_ENABLE ((uint16_t)USART_CR3_DMAT) +#define IS_IRDA_DMA_TX(DMATX) (((DMATX) == IRDA_DMA_TX_DISABLE) || \ + ((DMATX) == IRDA_DMA_TX_ENABLE)) +/** + * @} + */ + +/** @defgroup IRDA_DMA_Rx IRDA DMA Rx + * @{ + */ +#define IRDA_DMA_RX_DISABLE ((uint16_t)0x0000) +#define IRDA_DMA_RX_ENABLE ((uint16_t)USART_CR3_DMAR) +#define IS_IRDA_DMA_RX(DMARX) (((DMARX) == IRDA_DMA_RX_DISABLE) || \ + ((DMARX) == IRDA_DMA_RX_ENABLE)) +/** + * @} + */ + +/** @defgroup IRDA_Flags IRDA Flags + * Elements values convention: 0xXXXX + * - 0xXXXX : Flag mask in the ISR register + * @{ + */ +#define IRDA_FLAG_REACK ((uint32_t)0x00400000) +#define IRDA_FLAG_TEACK ((uint32_t)0x00200000) +#define IRDA_FLAG_BUSY ((uint32_t)0x00010000) +#define IRDA_FLAG_ABRF ((uint32_t)0x00008000) +#define IRDA_FLAG_ABRE ((uint32_t)0x00004000) +#define IRDA_FLAG_TXE ((uint32_t)0x00000080) +#define IRDA_FLAG_TC ((uint32_t)0x00000040) +#define IRDA_FLAG_RXNE ((uint32_t)0x00000020) +#define IRDA_FLAG_ORE ((uint32_t)0x00000008) +#define IRDA_FLAG_NE ((uint32_t)0x00000004) +#define IRDA_FLAG_FE ((uint32_t)0x00000002) +#define IRDA_FLAG_PE ((uint32_t)0x00000001) +/** + * @} + */ + +/** @defgroup IRDA_Interrupt_definition IRDA Interrupt Definition + * Elements values convention: 0000ZZZZ0XXYYYYYb + * - YYYYY : Interrupt source position in the XX register (5bits) + * - XX : Interrupt source register (2bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + * - ZZZZ : Flag position in the ISR register(4bits) + * @{ + */ +#define IRDA_IT_PE ((uint16_t)0x0028) +#define IRDA_IT_TXE ((uint16_t)0x0727) +#define IRDA_IT_TC ((uint16_t)0x0626) +#define IRDA_IT_RXNE ((uint16_t)0x0525) +#define IRDA_IT_IDLE ((uint16_t)0x0424) + + + +/** Elements values convention: 000000000XXYYYYYb + * - YYYYY : Interrupt source position in the XX register (5bits) + * - XX : Interrupt source register (2bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + */ +#define IRDA_IT_ERR ((uint16_t)0x0060) + +/** Elements values convention: 0000ZZZZ00000000b + * - ZZZZ : Flag position in the ISR register(4bits) + */ +#define IRDA_IT_ORE ((uint16_t)0x0300) +#define IRDA_IT_NE ((uint16_t)0x0200) +#define IRDA_IT_FE ((uint16_t)0x0100) +/** + * @} + */ + +/** @defgroup IRDA_IT_CLEAR_Flags IRDA Interruption Clear Flags + * @{ + */ +#define IRDA_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ +#define IRDA_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ +#define IRDA_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */ +#define IRDA_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */ +#define IRDA_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ +/** + * @} + */ + + + +/** @defgroup IRDA_Request_Parameters IRDA Request Parameters + * @{ + */ +#define IRDA_AUTOBAUD_REQUEST ((uint16_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */ +#define IRDA_RXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */ +#define IRDA_TXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */ +#define IS_IRDA_REQUEST_PARAMETER(PARAM) (((PARAM) == IRDA_AUTOBAUD_REQUEST) || \ + ((PARAM) == IRDA_RXDATA_FLUSH_REQUEST) || \ + ((PARAM) == IRDA_TXDATA_FLUSH_REQUEST)) +/** + * @} + */ + +/** @defgroup IRDA_Interruption_Mask IRDA interruptions flag mask + * @{ + */ +#define IRDA_IT_MASK ((uint16_t)0x001F) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup IRDA_Exported_Macros IRDA Exported Macros + * @{ + */ + +/** @brief Reset IRDA handle state + * @param __HANDLE__: IRDA handle. + * @retval None + */ +#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IRDA_STATE_RESET) + +/** @brief Checks whether the specified IRDA flag is set or not. + * @param __HANDLE__: specifies the IRDA Handle. + * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or + * UART peripheral + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg IRDA_FLAG_REACK: Receive enable ackowledge flag + * @arg IRDA_FLAG_TEACK: Transmit enable ackowledge flag + * @arg IRDA_FLAG_BUSY: Busy flag + * @arg IRDA_FLAG_ABRF: Auto Baud rate detection flag + * @arg IRDA_FLAG_ABRE: Auto Baud rate detection error flag + * @arg IRDA_FLAG_TXE: Transmit data register empty flag + * @arg IRDA_FLAG_TC: Transmission Complete flag + * @arg IRDA_FLAG_RXNE: Receive data register not empty flag + * @arg IRDA_FLAG_IDLE: Idle Line detection flag + * @arg IRDA_FLAG_ORE: OverRun Error flag + * @arg IRDA_FLAG_NE: Noise Error flag + * @arg IRDA_FLAG_FE: Framing Error flag + * @arg IRDA_FLAG_PE: Parity Error flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) + +/** @brief Enables the specified IRDA interrupt. + * @param __HANDLE__: specifies the IRDA Handle. + * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or + * UART peripheral + * @param __INTERRUPT__: specifies the IRDA interrupt source to enable. + * This parameter can be one of the following values: + * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt + * @arg IRDA_IT_TC: Transmission complete interrupt + * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt + * @arg IRDA_IT_IDLE: Idle line detection interrupt + * @arg IRDA_IT_PE: Parity Error interrupt + * @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK)))) + +/** @brief Disables the specified IRDA interrupt. + * @param __HANDLE__: specifies the IRDA Handle. + * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or + * UART peripheral + * @param __INTERRUPT__: specifies the IRDA interrupt source to disable. + * This parameter can be one of the following values: + * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt + * @arg IRDA_IT_TC: Transmission complete interrupt + * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt + * @arg IRDA_IT_IDLE: Idle line detection interrupt + * @arg IRDA_IT_PE: Parity Error interrupt + * @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK)))) + + +/** @brief Checks whether the specified IRDA interrupt has occurred or not. + * @param __HANDLE__: specifies the IRDA Handle. + * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or + * UART peripheral + * @param __IT__: specifies the IRDA interrupt source to check. + * This parameter can be one of the following values: + * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt + * @arg IRDA_IT_TC: Transmission complete interrupt + * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt + * @arg IRDA_IT_IDLE: Idle line detection interrupt + * @arg IRDA_IT_ORE: OverRun Error interrupt + * @arg IRDA_IT_NE: Noise Error interrupt + * @arg IRDA_IT_FE: Framing Error interrupt + * @arg IRDA_IT_PE: Parity Error interrupt + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1U << ((__IT__)>> 0x08))) + +/** @brief Checks whether the specified IRDA interrupt source is enabled. + * @param __HANDLE__: specifies the IRDA Handle. + * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or + * UART peripheral + * @param __IT__: specifies the IRDA interrupt source to check. + * This parameter can be one of the following values: + * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt + * @arg IRDA_IT_TC: Transmission complete interrupt + * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt + * @arg IRDA_IT_IDLE: Idle line detection interrupt + * @arg IRDA_IT_ORE: OverRun Error interrupt + * @arg IRDA_IT_NE: Noise Error interrupt + * @arg IRDA_IT_FE: Framing Error interrupt + * @arg IRDA_IT_PE: Parity Error interrupt + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \ + (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & IRDA_IT_MASK))) + + +/** @brief Clears the specified IRDA ISR flag, in setting the proper ICR register flag. + * @param __HANDLE__: specifies the IRDA Handle. + * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or + * UART peripheral + * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set + * to clear the corresponding interrupt + * This parameter can be one of the following values: + * @arg IRDA_CLEAR_PEF: Parity Error Clear Flag + * @arg IRDA_CLEAR_FEF: Framing Error Clear Flag + * @arg IRDA_CLEAR_NEF: Noise detected Clear Flag + * @arg IRDA_CLEAR_OREF: OverRun Error Clear Flag + * @arg IRDA_CLEAR_TCF: Transmission Complete Clear Flag + * @retval None + */ +#define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) + + +/** @brief Set a specific IRDA request flag. + * @param __HANDLE__: specifies the IRDA Handle. + * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or + * UART peripheral + * @param __REQ__: specifies the request flag to set + * This parameter can be one of the following values: + * @arg IRDA_AUTOBAUD_REQUEST: Auto-Baud Rate Request + * @arg IRDA_RXDATA_FLUSH_REQUEST: Receive Data flush Request + * @arg IRDA_TXDATA_FLUSH_REQUEST: Transmit data flush Request + * + * @retval None + */ +#define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) + + + +/** @brief Enable UART/USART associated to IRDA Handle + * @param __HANDLE__: specifies the IRDA Handle. + * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or + * UART peripheral + * @retval None + */ +#define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) + +/** @brief Disable UART/USART associated to IRDA Handle + * @param __HANDLE__: specifies the IRDA Handle. + * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or + * UART peripheral + * @retval None + */ +#define __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) + +/** @brief Ensure that IRDA Baud rate is less or equal to maximum value + * @param __BAUDRATE__: specifies the IRDA Baudrate set by the user. + * @retval True or False + */ +#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201) + +/** @brief Ensure that IRDA prescaler value is strictly larger than 0 + * @param __PRESCALER__: specifies the IRDA prescaler value set by the user. + * @retval True or False + */ +#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0) + +/** + * @} + */ + +/* Include IRDA HAL Extension module */ +#include "stm32f0xx_hal_irda_ex.h" + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions + * @{ + */ + +/** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda); +HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda); + +/** + * @} + */ + +/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); +void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda); + +/** + * @} + */ + +/** @addtogroup IRDA_Exported_Functions_Group3 + * @{ + */ + +/* Peripheral State and Error functions ***************************************/ +HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda); +uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_IRDA_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_irda_ex.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_irda_ex.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_irda_ex.h @@ -0,0 +1,416 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_irda_ex.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Header file of IRDA HAL Extension module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_IRDA_EX_H +#define __STM32F0xx_HAL_IRDA_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if !defined(STM32F030x6) && !defined(STM32F030x8) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup IRDAEx IRDAEx Extended HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup IRDAEx_Exported_Constants IRDAEx Exported Constants + * @{ + */ + +/** @defgroup IRDAEx_Word_Length IRDA Word Length + * @{ + */ +#if defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) +#define IRDA_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) +#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000) +#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) +#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_7B) || \ + ((LENGTH) == IRDA_WORDLENGTH_8B) || \ + ((LENGTH) == IRDA_WORDLENGTH_9B)) +#else +#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000) +#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M) +#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_8B) || \ + ((LENGTH) == IRDA_WORDLENGTH_9B)) +#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx)*/ +/** + * @} + */ + + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup IRDAEx_Exported_Macros IRDAEx Exported Macros + * @{ + */ + +/** @brief Reports the IRDA clock source. + * @param __HANDLE__: specifies the IRDA Handle + * @param __CLOCKSOURCE__ : output variable + * @retval IRDA clocking source, written in __CLOCKSOURCE__. + */ + +#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) +#define __HAL_IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } while(0) +#elif defined (STM32F030x8) || \ + defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F051x8) || defined (STM32F058xx) +#define __HAL_IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0) +#elif defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) +#define __HAL_IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == USART4) \ + { \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0) +#elif defined(STM32F091xC) || defined(STM32F098xx) +#define __HAL_IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ + case RCC_USART3CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART3CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART3CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART3CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART4) \ + { \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == USART5) \ + { \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == USART6) \ + { \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == USART7) \ + { \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == USART8) \ + { \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0) + +#endif /* defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) */ + + +/** @brief Computes the mask to apply to retrieve the received data + * according to the word length and to the parity bits activation. + * @param __HANDLE__: specifies the IRDA Handle + * @retval none + */ +#if defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) +#define __HAL_IRDA_MASK_COMPUTATION(__HANDLE__) \ + do { \ + if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \ + { \ + if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x01FF ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x00FF ; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \ + { \ + if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x00FF ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x007F ; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \ + { \ + if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x007F ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x003F ; \ + } \ + } \ +} while(0) +#else +#define __HAL_IRDA_MASK_COMPUTATION(__HANDLE__) \ + do { \ + if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \ + { \ + if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x01FF ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x00FF ; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \ + { \ + if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x00FF ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x007F ; \ + } \ + } \ +} while(0) +#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined(STM32F098xx) */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/* Initialization and de-initialization functions ****************************/ +/* IO operation functions *****************************************************/ +/* Peripheral Control functions ***********************************************/ +/* Peripheral State and Error functions ***************************************/ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_IRDA_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_iwdg.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_iwdg.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_iwdg.h @@ -0,0 +1,311 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_iwdg.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Header file of IWDG HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_IWDG_H +#define __STM32F0xx_HAL_IWDG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup IWDG + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup IWDG_Exported_Types IWDG Exported Types + * @{ + */ + +/** + * @brief IWDG HAL State Structure definition + */ +typedef enum +{ + HAL_IWDG_STATE_RESET = 0x00, /*!< IWDG not yet initialized or disabled */ + HAL_IWDG_STATE_READY = 0x01, /*!< IWDG initialized and ready for use */ + HAL_IWDG_STATE_BUSY = 0x02, /*!< IWDG internal process is ongoing */ + HAL_IWDG_STATE_TIMEOUT = 0x03, /*!< IWDG timeout state */ + HAL_IWDG_STATE_ERROR = 0x04 /*!< IWDG error state */ + +}HAL_IWDG_StateTypeDef; + +/** + * @brief IWDG Init structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Select the prescaler of the IWDG. + This parameter can be a value of @ref IWDG_Prescaler */ + + uint32_t Reload; /*!< Specifies the IWDG down-counter reload value. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */ + + uint32_t Window; /*!< Specifies the window value to be compared to the down-counter. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */ + +} IWDG_InitTypeDef; + +/** + * @brief IWDG Handle Structure definition + */ +typedef struct +{ + IWDG_TypeDef *Instance; /*!< Register base address */ + + IWDG_InitTypeDef Init; /*!< IWDG required parameters */ + + HAL_LockTypeDef Lock; /*!< IWDG Locking object */ + + __IO HAL_IWDG_StateTypeDef State; /*!< IWDG communication state */ + +}IWDG_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup IWDG_Exported_Constants IWDG Exported Constants + * @{ + */ + +/** @defgroup IWDG_Registers_BitMask IWDG Registers BitMask + * @brief IWDG registers bit mask + * @{ + */ +/* --- KR Register ---*/ +/* KR register bit mask */ +#define KR_KEY_RELOAD ((uint32_t)0xAAAA) /*!< IWDG Reload Counter Enable */ +#define KR_KEY_ENABLE ((uint32_t)0xCCCC) /*!< IWDG Peripheral Enable */ +#define KR_KEY_EWA ((uint32_t)0x5555) /*!< IWDG KR Write Access Enable */ +#define KR_KEY_DWA ((uint32_t)0x0000) /*!< IWDG KR Write Access Disable */ + +#define IS_IWDG_KR(__KR__) (((__KR__) == KR_KEY_RELOAD) || \ + ((__KR__) == KR_KEY_ENABLE))|| \ + ((__KR__) == KR_KEY_EWA)) || \ + ((__KR__) == KR_KEY_DWA)) +/** + * @} + */ + +/** @defgroup IWDG_Flag_definition IWDG Flag definition + * @{ + */ +#define IWDG_FLAG_PVU ((uint32_t)IWDG_SR_PVU) /*!< Watchdog counter prescaler value update Flag */ +#define IWDG_FLAG_RVU ((uint32_t)IWDG_SR_RVU) /*!< Watchdog counter reload value update Flag */ +#define IWDG_FLAG_WVU ((uint32_t)IWDG_SR_WVU) /*!< Watchdog counter window value update Flag */ + +/** + * @} + */ + +/** @defgroup IWDG_Prescaler IWDG Prescaler + * @{ + */ +#define IWDG_PRESCALER_4 ((uint8_t)0x00) /*!< IWDG prescaler set to 4 */ +#define IWDG_PRESCALER_8 ((uint8_t)(IWDG_PR_PR_0)) /*!< IWDG prescaler set to 8 */ +#define IWDG_PRESCALER_16 ((uint8_t)(IWDG_PR_PR_1)) /*!< IWDG prescaler set to 16 */ +#define IWDG_PRESCALER_32 ((uint8_t)(IWDG_PR_PR_1 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 32 */ +#define IWDG_PRESCALER_64 ((uint8_t)(IWDG_PR_PR_2)) /*!< IWDG prescaler set to 64 */ +#define IWDG_PRESCALER_128 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 128 */ +#define IWDG_PRESCALER_256 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_1)) /*!< IWDG prescaler set to 256 */ + +#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \ + ((__PRESCALER__) == IWDG_PRESCALER_8) || \ + ((__PRESCALER__) == IWDG_PRESCALER_16) || \ + ((__PRESCALER__) == IWDG_PRESCALER_32) || \ + ((__PRESCALER__) == IWDG_PRESCALER_64) || \ + ((__PRESCALER__) == IWDG_PRESCALER_128)|| \ + ((__PRESCALER__) == IWDG_PRESCALER_256)) + +/** + * @} + */ + +/** @defgroup IWDG_Reload_Value IWDG Reload Value + * @{ + */ +#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= 0xFFF) +/** + * @} + */ + +/** @defgroup IWDG_CounterWindow_Value IWDG CounterWindow Value + * @{ + */ +#define IS_IWDG_WINDOW(__VALUE__) ((__VALUE__) <= 0xFFF) +/** + * @} + */ +/** @defgroup IWDG_Window_option IWDG Window option + * @{ + */ +#define IWDG_WINDOW_DISABLE 0xFFF +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup IWDG_Exported_Macros IWDG Exported Macros + * @{ + */ + +/** @brief Reset IWDG handle state + * @param __HANDLE__: IWDG handle. + * @retval None + */ +#define __HAL_IWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IWDG_STATE_RESET) + +/** + * @brief Enables the IWDG peripheral. + * @param __HANDLE__: IWDG handle + * @retval None + */ +#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_ENABLE) + +/** + * @brief Reloads IWDG counter with value defined in the reload register + * (write access to IWDG_PR and IWDG_RLR registers disabled). + * @param __HANDLE__: IWDG handle + * @retval None + */ +#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_RELOAD) + +/** + * @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers. + * @param __HANDLE__: IWDG handle + * @retval None + */ +#define __HAL_IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_EWA) + +/** + * @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers. + * @param __HANDLE__: IWDG handle + * @retval None + */ +#define __HAL_IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_DWA) + +/** + * @brief Gets the selected IWDG's flag status. + * @param __HANDLE__: IWDG handle + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg IWDG_FLAG_PVU: Watchdog counter reload value update flag + * @arg IWDG_FLAG_RVU: Watchdog counter prescaler value flag + * @arg IWDG_FLAG_WVU: Watchdog counter window value flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_IWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup IWDG_Exported_Functions + * @{ + */ + +/** @addtogroup IWDG_Exported_Functions_Group1 + * @{ + */ +/* Initialization/de-initialization functions ********************************/ +HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg); +void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg); + +/** + * @} + */ + +/** @addtogroup IWDG_Exported_Functions_Group2 + * @{ + */ +/* I/O operation functions ****************************************************/ +HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg); +HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg); + +/** + * @} + */ + +/** @addtogroup IWDG_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State functions ************************************************/ +HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_IWDG_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pcd.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pcd.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pcd.h @@ -0,0 +1,783 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_pcd.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Header file of PCD HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_PCD_H +#define __STM32F0xx_HAL_PCD_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup PCD + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup PCD_Exported_Types PCD Exported Types + * @{ + */ + +/** + * @brief PCD State structures definition + */ +typedef enum +{ + PCD_READY = 0x00, + PCD_ERROR = 0x01, + PCD_BUSY = 0x02, + PCD_TIMEOUT = 0x03 +} PCD_StateTypeDef; + +typedef enum +{ + /* double buffered endpoint direction */ + PCD_EP_DBUF_OUT, + PCD_EP_DBUF_IN, + PCD_EP_DBUF_ERR, +}PCD_EP_DBUF_DIR; + +/* endpoint buffer number */ +typedef enum +{ + PCD_EP_NOBUF, + PCD_EP_BUF0, + PCD_EP_BUF1 +}PCD_EP_BUF_NUM; + +/** + * @brief PCD Initialization Structure definition + */ +typedef struct +{ + uint32_t dev_endpoints; /*!< Device Endpoints number. + This parameter depends on the used USB core. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint32_t speed; /*!< USB Core speed. + This parameter can be any value of @ref USB_Core_Speed */ + + uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. + This parameter can be any value of @ref USB_EP0_MPS */ + + uint32_t phy_itface; /*!< Select the used PHY interface. + This parameter can be any value of @ref USB_Core_PHY */ + + uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t low_power_enable; /*!< Enable or disable Low Power mode + This parameter can be set to ENABLE or DISABLE */ + + uint32_t lpm_enable; /*!< Enable or disable the Link Power Management . + This parameter can be set to ENABLE or DISABLE */ + + uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. + This parameter can be set to ENABLE or DISABLE */ + +}PCD_InitTypeDef; + +typedef struct +{ + uint8_t num; /*!< Endpoint number + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t is_in; /*!< Endpoint direction + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t is_stall; /*!< Endpoint stall condition + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t type; /*!< Endpoint type + This parameter can be any value of @ref USB_EP_Type */ + + uint16_t pmaadress; /*!< PMA Address + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + + + uint16_t pmaaddr0; /*!< PMA Address0 + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + + + uint16_t pmaaddr1; /*!< PMA Address1 + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + + + uint8_t doublebuffer; /*!< Double buffer enable + This parameter can be 0 or 1 */ + + uint32_t maxpacket; /*!< Endpoint Max packet size + This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ + + uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ + + + uint32_t xfer_len; /*!< Current transfer length */ + + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ + +}PCD_EPTypeDef; + +typedef USB_TypeDef PCD_TypeDef; + +/** + * @brief PCD Handle Structure definition + */ +typedef struct +{ + PCD_TypeDef *Instance; /*!< Register base address */ + PCD_InitTypeDef Init; /*!< PCD required parameters */ + __IO uint8_t USB_Address; /*!< USB Address */ + PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */ + PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */ + HAL_LockTypeDef Lock; /*!< PCD peripheral status */ + __IO PCD_StateTypeDef State; /*!< PCD communication state */ + uint32_t Setup[12]; /*!< Setup packet buffer */ + void *pData; /*!< Pointer to upper stack Handler */ + +} PCD_HandleTypeDef; + +/** + * @} + */ + +#include "stm32f0xx_hal_pcd_ex.h" +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PCD_Exported_Constants PCD Exported Constants + * @{ + */ + +/** @defgroup USB_Core_Speed USB Core Speed + * @{ + */ +#define PCD_SPEED_HIGH 0 /* Not Supported */ +#define PCD_SPEED_FULL 2 +/** + * @} + */ + +/** @defgroup USB_Core_PHY USB Core PHY + * @{ + */ +#define PCD_PHY_EMBEDDED 2 +/** + * @} + */ + +/** @defgroup USB_EP0_MPS USB EP0 MPS + * @{ + */ +#define DEP0CTL_MPS_64 0 +#define DEP0CTL_MPS_32 1 +#define DEP0CTL_MPS_16 2 +#define DEP0CTL_MPS_8 3 + +#define PCD_EP0MPS_64 DEP0CTL_MPS_64 +#define PCD_EP0MPS_32 DEP0CTL_MPS_32 +#define PCD_EP0MPS_16 DEP0CTL_MPS_16 +#define PCD_EP0MPS_08 DEP0CTL_MPS_8 +/** + * @} + */ + +/** @defgroup USB_EP_Type USB EP Type + * @{ + */ +#define PCD_EP_TYPE_CTRL 0 +#define PCD_EP_TYPE_ISOC 1 +#define PCD_EP_TYPE_BULK 2 +#define PCD_EP_TYPE_INTR 3 +/** + * @} + */ + +/** @defgroup USB_ENDP USB ENDP + * @{ + */ + +#define PCD_ENDP0 ((uint8_t)0) +#define PCD_ENDP1 ((uint8_t)1) +#define PCD_ENDP2 ((uint8_t)2) +#define PCD_ENDP3 ((uint8_t)3) +#define PCD_ENDP4 ((uint8_t)4) +#define PCD_ENDP5 ((uint8_t)5) +#define PCD_ENDP6 ((uint8_t)6) +#define PCD_ENDP7 ((uint8_t)7) + +/* Endpoint Kind */ +#define PCD_SNG_BUF 0 +#define PCD_DBL_BUF 1 + +#define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup PCD_Exported_Macros PCD Exported Macros + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ +#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISTR) & (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) = ~(__INTERRUPT__)) + +#define USB_EXTI_LINE_WAKEUP ((uint32_t)0x00040000) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */ + +#define __HAL_USB_EXTI_ENABLE_IT() EXTI->IMR |= USB_EXTI_LINE_WAKEUP +#define __HAL_USB_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_EXTI_LINE_WAKEUP) +#define __HAL_USB_EXTI_GENERATE_SWIT(__EXTILINE__) (EXTI->SWIER |= (__EXTILINE__)) + +/** + * @} + */ + +/* Internal macros -----------------------------------------------------------*/ + +/** @defgroup PCD_Private_Macros PCD Private Macros + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ + +/* SetENDPOINT */ +#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*(&(USBx)->EP0R + (bEpNum) * 2)= (uint16_t)(wRegValue)) + +/* GetENDPOINT */ +#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(&(USBx)->EP0R + (bEpNum) * 2)) + + + +/** + * @brief sets the type in the endpoint register(bits EP_TYPE[1:0]) + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @param wType: Endpoint Type. + * @retval None + */ +#define PCD_SET_EPTYPE(USBx, bEpNum,wType) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ + ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) ))) + +/** + * @brief gets the type in the endpoint register(bits EP_TYPE[1:0]) + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @retval Endpoint Type + */ +#define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD) + + +/** + * @brief free buffer used from the application realizing it to the line + toggles bit SW_BUF in the double buffered endpoint register + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @param bDir: Direction + * @retval None + */ +#define PCD_FreeUserBuffer(USBx, bEpNum, bDir)\ +{\ + if ((bDir) == PCD_EP_DBUF_OUT)\ + { /* OUT double buffered endpoint */\ + PCD_TX_DTOG((USBx), (bEpNum));\ + }\ + else if ((bDir) == PCD_EP_DBUF_IN)\ + { /* IN double buffered endpoint */\ + PCD_RX_DTOG((USBx), (bEpNum));\ + }\ +} + +/** + * @brief gets direction of the double buffered endpoint + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @retval EP_DBUF_OUT, EP_DBUF_IN, + * EP_DBUF_ERR if the endpoint counter not yet programmed. + */ +#define PCD_GET_DB_DIR(USBx, bEpNum)\ +{\ + if ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum)) & 0xFC00) != 0)\ + return(PCD_EP_DBUF_OUT);\ + else if (((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x03FF) != 0)\ + return(PCD_EP_DBUF_IN);\ + else\ + return(PCD_EP_DBUF_ERR);\ +} + +/** + * @brief sets the status for tx transfer (bits STAT_TX[1:0]). + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @param wState: new state + * @retval None + */ +#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) {\ + register uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK;\ + /* toggle first bit ? */ \ + if((USB_EPTX_DTOG1 & (wState))!= 0) \ + _wRegVal ^= USB_EPTX_DTOG1; \ + /* toggle second bit ? */ \ + if((USB_EPTX_DTOG2 & (wState))!= 0) \ + _wRegVal ^= USB_EPTX_DTOG2; \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \ + } /* PCD_SET_EP_TX_STATUS */ + +/** + * @brief sets the status for rx transfer (bits STAT_TX[1:0]) + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @param wState: new state + * @retval None + */ +#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) {\ + register uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK;\ + /* toggle first bit ? */ \ + if((USB_EPRX_DTOG1 & (wState))!= 0) \ + _wRegVal ^= USB_EPRX_DTOG1; \ + /* toggle second bit ? */ \ + if((USB_EPRX_DTOG2 & (wState))!= 0) \ + _wRegVal ^= USB_EPRX_DTOG2; \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \ + } /* PCD_SET_EP_RX_STATUS */ + +/** + * @brief sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0]) + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @param wStaterx: new state. + * @param wStatetx: new state. + * @retval None + */ +#define PCD_SET_EP_TXRX_STATUS(USBx,bEpNum,wStaterx,wStatetx) {\ + register uint32_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK |USB_EPTX_STAT) ;\ + /* toggle first bit ? */ \ + if((USB_EPRX_DTOG1 & ((wStaterx)))!= 0) \ + _wRegVal ^= USB_EPRX_DTOG1; \ + /* toggle second bit ? */ \ + if((USB_EPRX_DTOG2 & (wStaterx))!= 0) \ + _wRegVal ^= USB_EPRX_DTOG2; \ + /* toggle first bit ? */ \ + if((USB_EPTX_DTOG1 & (wStatetx))!= 0) \ + _wRegVal ^= USB_EPTX_DTOG1; \ + /* toggle second bit ? */ \ + if((USB_EPTX_DTOG2 & (wStatetx))!= 0) \ + _wRegVal ^= USB_EPTX_DTOG2; \ + PCD_SET_ENDPOINT((USBx), (bEpNum), _wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX); \ + } /* PCD_SET_EP_TXRX_STATUS */ + +/** + * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0] + * /STAT_RX[1:0]) + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @retval status + */ +#define PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT) + +#define PCD_GET_EP_RX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT) + +/** + * @brief sets directly the VALID tx/rx-status into the endpoint register + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @retval None + */ +#define PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID)) + +#define PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID)) + +/** + * @brief checks stall condition in an endpoint. + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @retval TRUE = endpoint in stall condition. + */ +#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \ + == USB_EP_TX_STALL) +#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) \ + == USB_EP_RX_STALL) + +/** + * @brief set & clear EP_KIND bit. + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @retval None + */ +#define PCD_SET_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ + (USB_EP_CTR_RX|USB_EP_CTR_TX|((PCD_GET_ENDPOINT((USBx), (bEpNum)) | USB_EP_KIND) & USB_EPREG_MASK)))) +#define PCD_CLEAR_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ + (USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK)))) + +/** + * @brief Sets/clears directly STATUS_OUT bit in the endpoint register. + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @retval None + */ +#define PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum)) +#define PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum)) + +/** + * @brief Sets/clears directly EP_KIND bit in the endpoint register. + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @retval None + */ +#define PCD_SET_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum)) +#define PCD_CLEAR_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum)) + +/** + * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @retval None + */ +#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ + PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFF & USB_EPREG_MASK)) +#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ + PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7F & USB_EPREG_MASK)) + +/** + * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register. + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @retval None + */ +#define PCD_RX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ + USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK))) +#define PCD_TX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ + USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK))) + +/** + * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register. + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @retval None + */ +#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_RX) != 0)\ + PCD_RX_DTOG((USBx), (bEpNum)) +#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_TX) != 0)\ + PCD_TX_DTOG((USBx), (bEpNum)) + +/** + * @brief Sets address in an endpoint register. + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @param bAddr: Address. + * @retval None + */ +#define PCD_SET_EP_ADDRESS(USBx, bEpNum,bAddr) PCD_SET_ENDPOINT((USBx), (bEpNum),\ + USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr)) + +/** + * @brief Gets address in an endpoint register. + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @retval None + */ +#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD)) + +#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8)+ ((uint32_t)(USBx) + 0x400))) +#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8+2)+ ((uint32_t)(USBx) + 0x400))) +#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8+4)+ ((uint32_t)(USBx) + 0x400))) +#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8+6)+ ((uint32_t)(USBx) + 0x400))) + +/** + * @brief sets address of the tx/rx buffer. + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @param wAddr: address to be set (must be word aligned). + * @retval None + */ +#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1) << 1)) +#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_RX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1) << 1)) + +/** + * @brief Gets address of the tx/rx buffer. + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @retval address of the buffer. + */ +#define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum))) +#define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum))) + +/** + * @brief Sets counter of rx buffer with no. of blocks. + * @param dwReg: Register + * @param wCount: Counter. + * @param wNBlocks: no. of Blocks. + * @retval None + */ +#define PCD_CALC_BLK32(dwReg,wCount,wNBlocks) {\ + (wNBlocks) = (wCount) >> 5;\ + if(((wCount) & 0x1f) == 0)\ + (wNBlocks)--;\ + *pdwReg = (uint16_t)(((wNBlocks) << 10) | 0x8000);\ + }/* PCD_CALC_BLK32 */ + +#define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) {\ + (wNBlocks) = (wCount) >> 1;\ + if(((wCount) & 0x1) != 0)\ + (wNBlocks)++;\ + *pdwReg = (uint16_t)((wNBlocks) << 10);\ + }/* PCD_CALC_BLK2 */ + +#define PCD_SET_EP_CNT_RX_REG(dwReg,wCount) {\ + uint16_t wNBlocks;\ + if((wCount) > 62){PCD_CALC_BLK32((dwReg),(wCount),wNBlocks);}\ + else {PCD_CALC_BLK2((dwReg),(wCount),wNBlocks);}\ + }/* PCD_SET_EP_CNT_RX_REG */ + +#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum,wCount) {\ + uint16_t *pdwReg = PCD_EP_TX_CNT((USBx), (bEpNum)); \ + PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\ + } +/** + * @brief sets counter for the tx/rx buffer. + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @param wCount: Counter value. + * @retval None + */ +#define PCD_SET_EP_TX_CNT(USBx, bEpNum,wCount) (*PCD_EP_TX_CNT((USBx), (bEpNum)) = (wCount)) +#define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\ + uint16_t *pdwReg = PCD_EP_RX_CNT(USBx, bEpNum); \ + PCD_SET_EP_CNT_RX_REG(pdwReg, wCount);\ + } + +/** + * @brief gets counter of the tx buffer. + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @retval Counter value + */ +#define PCD_GET_EP_TX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ff) +#define PCD_GET_EP_RX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ff) + +/** + * @brief Sets buffer 0/1 address in a double buffer endpoint. + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @param wBuf0Addr: buffer 0 address. + * @retval Counter value + */ +#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) {PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr));} +#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum,wBuf1Addr) {PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr));} + +/** + * @brief Sets addresses in a double buffer endpoint. + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @param wBuf0Addr: buffer 0 address. + * @param wBuf1Addr = buffer 1 address. + * @retval None + */ +#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum,wBuf0Addr,wBuf1Addr) { \ + PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr));\ + PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr));\ + } /* PCD_SET_EP_DBUF_ADDR */ + +/** + * @brief Gets buffer 0/1 address of a double buffer endpoint. + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @retval None + */ +#define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum))) +#define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum))) + +/** + * @brief Gets buffer 0/1 address of a double buffer endpoint. + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @param bDir: endpoint dir EP_DBUF_OUT = OUT + * EP_DBUF_IN = IN + * @param wCount: Counter value + * @retval None + */ +#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) { \ + if((bDir) == PCD_EP_DBUF_OUT)\ + /* OUT endpoint */ \ + {PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum),(wCount));} \ + else if((bDir) == PCD_EP_DBUF_IN)\ + /* IN endpoint */ \ + *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \ + } /* SetEPDblBuf0Count*/ + +#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) { \ + if((bDir) == PCD_EP_DBUF_OUT)\ + /* OUT endpoint */ \ + {PCD_SET_EP_RX_CNT((USBx), (bEpNum),(wCount));}\ + else if((bDir) == PCD_EP_DBUF_IN)\ + /* IN endpoint */\ + *PCD_EP_RX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \ + } /* SetEPDblBuf1Count */ + +#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) {\ + PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \ + PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \ + } /* PCD_SET_EP_DBUF_CNT */ + +/** + * @brief Gets buffer 0/1 rx/tx counter for double buffering. + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @retval None + */ +#define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum))) +#define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum))) + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup PCD_Exported_Functions + * @{ + */ + +/** @addtogroup PCD_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions **********************************/ +HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd); +void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd); +void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd); + +/** + * @} + */ + +/** @addtogroup PCD_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions *****************************************************/ + /* Non Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd); +void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd); + +void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd); + +/** + * @} + */ + +/** @addtogroup PCD_Exported_Functions_Group3 + * @{ + */ +/* Peripheral Control functions ************************************************/ +HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address); +HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type); +HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); +HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); +uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_ActiveRemoteWakeup(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_DeActiveRemoteWakeup(PCD_HandleTypeDef *hpcd); +/** + * @} + */ + +/** @addtogroup PCD_Exported_Functions_Group4 + * @{ + */ +/* Peripheral State functions **************************************************/ +PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32F042x6 || STM32F072xB || STM32F078xx */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F0xx_HAL_PCD_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pcd_ex.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pcd_ex.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pcd_ex.h @@ -0,0 +1,103 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_pcd_ex.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Header file of PCD HAL Extension module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L0xx_HAL_PCD_EX_H +#define __STM32L0xx_HAL_PCD_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup PCDEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ +/* Internal macros -----------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup PCDEx_Exported_Functions + * @{ + */ +/** @addtogroup PCDEx_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, + uint16_t ep_addr, + uint16_t ep_kind, + uint32_t pmaadress); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32F042x6 || STM32F072xB || STM32F078xx */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F0xx_HAL_PCD_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_ppp.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_ppp.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_ppp.h @@ -0,0 +1,325 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_ppp.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Header file of PPP HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_PPP_H +#define __STM32F0xx_HAL_PPP_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup PPP PPP HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup PPP_Exported_Types PPP Exported Types + * @{ + */ + +/** + * @brief PPP + */ + +typedef struct +{ + __IO uint32_t REGx; /*!< PPP register x Address offset: 0x00 */ +} PPP_TypeDef; + +/** + * @brief PPP Configuration Structure definition + */ +typedef struct +{ + uint32_t Config1; /*!< Add Config1 description + This parameter can be any value of @ref PPP_CONFIGx_Define */ + + uint32_t Config2; /*!< Add Config2 description + This parameter can be any value of @ref PPP_CONFIGx_Define */ + + uint32_t Config3; /*!< Add Config3 description + This parameter can be any value of @ref PPP_CONFIGx_Define */ + + uint32_t Config4; /*!< Add Config4 description + This parameter can be any value of @ref PPP_CONFIGx_Define */ + + uint32_t Config5; /*!< Add Config5 description + This parameter can be any value of @ref PPP_CONFIGx_Define */ + + uint32_t Config6; /*!< Add Config6 description + This parameter can be any value of @ref PPP_CONFIGx_Define */ +} PPP_InitTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_PPP_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ + HAL_PPP_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ + HAL_PPP_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */ + HAL_PPP_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */ + HAL_PPP_STATE_BUSY_TX_RX = 0x05, /*!< Data Transmission and Reception process is ongoing */ + HAL_PPP_STATE_TIMEOUT = 0x06, /*!< Timeout state */ + HAL_PPP_STATE_ERROR = 0x07, /*!< Error state */ + HAL_PPP_STATE_DISABLED = 0x08 /*!< Disabled state */ + +}HAL_PPP_StateTypeDef; + + +/** + * @brief PPP Handle Structure definition + */ +typedef struct +{ + PPP_TypeDef *Instance; /*!< Register base address */ + PPP_InitTypeDef Config; /*!< PPP required parameters */ + + /* !!! Add HAL PPP required handler parameters !!! */ + + HAL_StatusTypeDef Status; /*!< PPP peripheral status */ + HAL_LockTypeDef Lock; /*!< Locking object */ + __IO HAL_PPP_StateTypeDef State; /*!< PPP communication state */ + +} PPP_HandleTypeDef; + +/** + * @brief PPP Configuration enumeration values definition + */ +typedef enum +{ + Control1 = 0, /*!< Control related Config1 Paramater in PPP_InitTypeDef */ + Control2 = 1, /*!< Control related Config2 Paramater in PPP_InitTypeDef */ + Control3 = 2, /*!< Control related Config3 Paramater in PPP_InitTypeDef */ + Control4 = 3, /*!< Control related Config4 Paramater in PPP_InitTypeDef */ + Control5 = 4, /*!< Control related Config5 Paramater in PPP_InitTypeDef */ + Control6 = 5 /*!< Control related Config6 Paramater in PPP_InitTypeDef */ +}PPP_ControlTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PPP_Exported_Constants PPP Exported Constants + * @{ + */ + +/** @defgroup PPP_CONFIGx_Define PPP CONFIGx Define + * @{ + */ +#define PPP_CONFIGx_VALUE1 ((uint32_t)0x00) /*!< PPP Config Value description */ +#define PPP_CONFIGx_VALUE2 ((uint32_t)0x01) /*!< PPP Config Value description */ +#define PPP_CONFIGx_VALUE3 ((uint32_t)0x02) /*!< PPP Config Value description */ + +#define IS_PPP_CONFIGx(CONFIG) (((CONFIG) == PPP_CONFIGx_VALUE1) || \ + ((CONFIG) == PPP_CONFIGx_VALUE2) || \ + ((CONFIG) == PPP_CONFIGx_VALUE3)) + +/** + * @} + */ + +/** @defgroup PPP_Flag_definition PPP Flag definition + * @brief Flag definition + * Elements values convention: 0x00000ZZZZ + * - ZZZZ: Flag mask + * + * @#define PPP_FLAG_xxxx ((uint32_t)0x0000ZZZZ) + * @{ + */ +#define PPP_FLAG_TC ((uint32_t)0x00000002) +#define PPP_FLAG_RXNE ((uint32_t)0x00000001) +/** + * @} + */ + + +/** @defgroup PPP_Interrupt_definition PPP Interrupt definition + * @brief PPP Interrupt definition + * Elements values convention: 0xXXYYZZZZ + * - XX : Interrupt register Index + * - YY : Interrupt Source Position + * - ZZZZ: Interrupt mask + * + * @#define PPP_IT_xxxx ((uint32_t)0xXXYYZZZZ) + * @{ + */ +#define PPP_IT_TC ((uint32_t)0x00000002) +#define PPP_IT_RXNE ((uint32_t)0x00000001) +/** + * @} + */ + +/** @defgroup PPP_Instance_definition PPP Instance definition + * @{ + */ +#define IS_PPP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PPP1) || \ + ((INSTANCE) == PPP2) || \ + ((INSTANCE) == PPP3) || \ + ((INSTANCE) == PPP4)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PPP_Exported_Macros PPP Exported Macros + * @{ + */ + +/** @defgroup PPP_Interrupt_Clock PPP Interrupt Clock + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ + +#define __HAL_PPP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->REGx |= (ENABLE)) +#define __HAL_PPP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->REGx &= ~(ENABLE)) + +#define __HAL_PPP_ENABLE_I(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->REGx |= (__INTERRUPT__)) +#define __HAL_PPP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->REGx &= ~(__INTERRUPT__)) +#define __HAL_PPP_GET_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->REGx & ((uint16_t)1 << ((__INTERRUPT__)>> 0x08))) +#define __HAL_PPP_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->REGx &= ((uint16_t)~((uint16_t)0x01 << (uint16_t)((__INTERRUPT__) >> 0x08)))) +#define __HAL_PPP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->REGx & (__FLAG__)) == (__FLAG__)) +#define __HAL_PPP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->REGx &= ~(__FLAG__)) + +#define __HAL_PPP_PRESCALER(__HANDLE__, __PRESC__) +#define __HAL_PPP_YYYY(__HANDLE__, __PRESC__) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PPP_Exported_Functions PPP Exported Functions + * @{ + */ + +/** @addtogroup PPP_Exported_Functions_Group1 Initialization/de-initialization functions + * @{ + */ +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_PPP_Init(PPP_HandleTypeDef *hppp); +HAL_StatusTypeDef HAL_PPP_DeInit (PPP_HandleTypeDef *hppp); +void HAL_PPP_MspInit(PPP_HandleTypeDef *hppp); +void HAL_PPP_MspDeInit(PPP_HandleTypeDef *hppp); + +/** + * @} + */ + +/** @addtogroup PPP_Exported_Functions_Group2 I/O operation functions + * @{ + */ +/* IO operation functions *****************************************************/ + /* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_PPP_Transmit(PPP_HandleTypeDef *hppp, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_PPP_Receive(PPP_HandleTypeDef *hppp, uint8_t *pData, uint16_t Size); + + /* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_PPP_Transmit_IT(PPP_HandleTypeDef *hppp, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_PPP_Receive_IT(PPP_HandleTypeDef *hppp, uint8_t *pData, uint16_t Size); +void HAL_PPP_IRQHandler(PPP_HandleTypeDef *hppp); + + /* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_PPP_Transmit_DMA(PPP_HandleTypeDef *hppp, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_PPP_Receive_DMA(PPP_HandleTypeDef *hppp, uint8_t *pData, uint16_t Size); + + /* Callback in non blocking modes (Interrupt and DMA) */ +void HAL_PPP_TxCpltCallback(PPP_HandleTypeDef *hppp); +void HAL_PPP_RxCpltCallback(PPP_HandleTypeDef *hppp); + +/** + * @} + */ + +/** @addtogroup PPP_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_PPP_Ctl(PPP_HandleTypeDef *hppp, PPP_ControlTypeDef control, uint16_t *args); + +/** + * @} + */ + +/** @addtogroup PPP_Exported_Functions_Group4 Peripheral State functions + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +HAL_PPP_StateTypeDef HAL_PPP_GetState(PPP_HandleTypeDef *hppp); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_PPP_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h @@ -0,0 +1,202 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_pwr.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Header file of PWR HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_PWR_H +#define __STM32F0xx_HAL_PWR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWR PWR HAL module Driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in STOP mode + * @{ + */ +#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000) +#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS + +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ + ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) +/** + * @} + */ + +/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry + * @{ + */ +#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) +#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) +#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) +/** + * @} + */ + +/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry + * @{ + */ +#define PWR_STOPENTRY_WFI ((uint8_t)0x01) +#define PWR_STOPENTRY_WFE ((uint8_t)0x02) +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) +/** + * @} + */ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWR_Exported_Macro PWR Exported Macro + * @{ + */ + +/** @brief Check PWR flag is set or not. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event + * was received from the WKUP pin or from the RTC alarm (Alarm A), + * RTC Tamper event, RTC TimeStamp event or RTC Wakeup. + * An additional wakeup event is detected if the WKUP pin is enabled + * (by setting the EWUP bit) when the WKUP pin level is already high. + * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was + * resumed from StandBy mode. + * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled + * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode + * For this reason, this bit is equal to 0 after Standby or reset + * until the PVDE bit is set. + * Warning: this Flag is not available on STM32F030x8 products + * @arg PWR_FLAG_VREFINTRDY: This flag indicates that the internal reference + * voltage VREFINT is ready. + * Warning: this Flag is not available on STM32F030x8 products + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the PWR's pending flags. + * @param __FLAG__: specifies the flag to clear. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag + * @arg PWR_FLAG_SB: StandBy flag + */ +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2) + + +/** + * @} + */ + +/* Include PWR HAL Extension module */ +#include "stm32f0xx_hal_pwr_ex.h" + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions *****************************/ +void HAL_PWR_DeInit(void); + +/** + * @} + */ + +/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions + * @{ + */ + +/* Peripheral Control functions **********************************************/ +void HAL_PWR_EnableBkUpAccess(void); +void HAL_PWR_DisableBkUpAccess(void); + +/* WakeUp pins configuration functions ****************************************/ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); + +/* Low Power modes configuration functions ************************************/ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); +void HAL_PWR_EnterSTANDBYMode(void); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F0xx_HAL_PWR_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h @@ -0,0 +1,421 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_pwr_ex.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Header file of PWR HAL Extension module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_PWR_EX_H +#define __STM32F0xx_HAL_PWR_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWREx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Types PWREx Exported Types + * @{ + */ + +#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ + defined (STM32F071xB) || defined (STM32F072xB) || \ + defined (STM32F091xC) + +/** + * @brief PWR PVD configuration structure definition + */ +typedef struct +{ + uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level + This parameter can be a value of @ref PWREx_PVD_detection_level */ + + uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. + This parameter can be a value of @ref PWREx_PVD_Mode */ +}PWR_PVDTypeDef; + +#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ + /* defined (STM32F071xB) || defined (STM32F072xB) || */ + /* defined (STM32F091xC) */ +/** + * @} + */ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Constants PWREx Exported Constants + * @{ + */ + + +/** @defgroup PWREx_WakeUp_Pins PWREx Wakeup Pins + * @{ + */ +#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) +#define PWR_WAKEUP_PIN1 ((uint32_t)0x00) +#define PWR_WAKEUP_PIN2 ((uint32_t)0x01) +#define PWR_WAKEUP_PIN3 ((uint32_t)0x02) +#define PWR_WAKEUP_PIN4 ((uint32_t)0x03) +#define PWR_WAKEUP_PIN5 ((uint32_t)0x04) +#define PWR_WAKEUP_PIN6 ((uint32_t)0x05) +#define PWR_WAKEUP_PIN7 ((uint32_t)0x06) +#define PWR_WAKEUP_PIN8 ((uint32_t)0x07) + +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ + ((PIN) == PWR_WAKEUP_PIN2) || \ + ((PIN) == PWR_WAKEUP_PIN3) || \ + ((PIN) == PWR_WAKEUP_PIN4) || \ + ((PIN) == PWR_WAKEUP_PIN5) || \ + ((PIN) == PWR_WAKEUP_PIN6) || \ + ((PIN) == PWR_WAKEUP_PIN7) || \ + ((PIN) == PWR_WAKEUP_PIN8)) +#else +#define PWR_WAKEUP_PIN1 ((uint32_t)0x00) +#define PWR_WAKEUP_PIN2 ((uint32_t)0x01) + +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ + ((PIN) == PWR_WAKEUP_PIN2)) +#endif /* defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || */ + /* defined (STM32F091xC) || defined (STM32F098xx) */ +/** + * @} + */ + +/** @defgroup PWREx_EXTI_Line PWREx EXTI Line + * @{ + */ +#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ + defined (STM32F071xB) || defined (STM32F072xB) || \ + defined (STM32F091xC) + +#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ + +#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ + /* defined (STM32F071xB) || defined (STM32F072xB) || */ + /* defined (STM32F091xC) */ + +#if defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) + +#define PWR_EXTI_LINE_VDDIO2 ((uint32_t)0x80000000) /*!< External interrupt line 31 Connected to the Vddio2 Monitor EXTI Line */ + +#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) */ +/** + * @} + */ + +#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ + defined (STM32F071xB) || defined (STM32F072xB) || \ + defined (STM32F091xC) +/** @defgroup PWREx_PVD_detection_level PWREx PVD detection level + * @{ + */ +#define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0 +#define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1 +#define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2 +#define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3 +#define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4 +#define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5 +#define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6 +#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7 +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ + ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ + ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ + ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) +/** + * @} + */ + +/** @defgroup PWREx_PVD_Mode PWREx PVD Mode + * @{ + */ +#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */ +#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */ + +#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ + ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ + ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ + ((MODE) == PWR_PVD_MODE_NORMAL)) +/** + * @} + */ +#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ + /* defined (STM32F071xB) || defined (STM32F072xB) || */ + /* defined (STM32F091xC) */ + +/** @defgroup PWREx_Flag PWREx Flag + * @{ + */ +#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ + defined (STM32F071xB) || defined (STM32F072xB) || \ + defined (STM32F091xC) + +#define PWR_FLAG_WU PWR_CSR_WUF +#define PWR_FLAG_SB PWR_CSR_SBF +#define PWR_FLAG_PVDO PWR_CSR_PVDO +#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF +#else +#define PWR_FLAG_WU PWR_CSR_WUF +#define PWR_FLAG_SB PWR_CSR_SBF + +#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ + /* defined (STM32F071xB) || defined (STM32F072xB) || */ + /* defined (STM32F091xC) */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWREx_Exported_Macros PWREx Exported Macros + * @{ + */ +#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ + defined (STM32F071xB) || defined (STM32F072xB) || \ + defined (STM32F091xC) +/** + * @brief Enable interrupt on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD)) + +/** + * @brief Disable interrupt on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD)) + +/** + * @brief Enable event on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD)) + +/** + * @brief Disable event on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD)) + +/** + * @brief PVD EXTI line configuration: clear falling edge and rising edge trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() EXTI->FTSR &= ~(PWR_EXTI_LINE_PVD); \ + EXTI->RTSR &= ~(PWR_EXTI_LINE_PVD) + +/** + * @brief PVD EXTI line configuration: set falling edge trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER() EXTI->FTSR |= (PWR_EXTI_LINE_PVD) + +/** + * @brief PVD EXTI line configuration: set rising edge trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER() EXTI->RTSR |= (PWR_EXTI_LINE_PVD) + +/** + * @brief Check whether the specified PVD EXTI interrupt flag is set or not. + * @retval EXTI PVD Line Status. + */ +#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) + +/** + * @brief Clear the PVD EXTI flag. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) + +/** + * @brief Generate a Software interrupt on selected EXTI line. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD)) + +#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ + /* defined (STM32F071xB) || defined (STM32F072xB) || */ + /* defined (STM32F091xC) */ + + +#if defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) +/** + * @brief Enable interrupt on Vddio2 Monitor Exti Line 31. + * @retval None. + */ +#define __HAL_PWR_VDDIO2_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_VDDIO2)) + +/** + * @brief Disable interrupt on Vddio2 Monitor Exti Line 31. + * @retval None. + */ +#define __HAL_PWR_VDDIO2_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_VDDIO2)) + +/** + * @brief Vddio2 Monitor EXTI line configuration: clear falling edge and rising edge trigger. + * @retval None. + */ +#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER() EXTI->FTSR &= ~(PWR_EXTI_LINE_VDDIO2); \ + EXTI->RTSR &= ~(PWR_EXTI_LINE_VDDIO2) + +/** + * @brief Vddio2 Monitor EXTI line configuration: set falling edge trigger. + * @retval None. + */ +#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER() EXTI->FTSR |= (PWR_EXTI_LINE_VDDIO2) + +/** + * @brief Check whether the specified VDDIO2 monitor EXTI interrupt flag is set or not. + * @retval EXTI VDDIO2 Monitor Line Status. + */ +#define __HAL_PWR_VDDIO2_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_VDDIO2)) + +/** + * @brief Clear the VDDIO2 Monitor EXTI flag. + * @retval None. + */ +#define __HAL_PWR_VDDIO2_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_VDDIO2)) + +/** + * @brief Generate a Software interrupt on selected EXTI line. + * @retval None. + */ +#define __HAL_PWR_VDDIO2_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_VDDIO2)) + + +#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions + * @{ + */ + +/** @addtogroup PWREx_Exported_Functions_Group1 + * @{ + */ +/* I/O operation functions ***************************************************/ +#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ + defined (STM32F071xB) || defined (STM32F072xB) || \ + defined (STM32F091xC) +void HAL_PWR_PVD_IRQHandler(void); +void HAL_PWR_PVDCallback(void); +#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ + /* defined (STM32F071xB) || defined (STM32F072xB) || */ + /* defined (STM32F091xC) */ + +#if defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) +void HAL_PWR_Vddio2Monitor_IRQHandler(void); +void HAL_PWR_Vddio2MonitorCallback(void); +#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) */ + +/* Peripheral Control functions **********************************************/ +#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ + defined (STM32F071xB) || defined (STM32F072xB) || \ + defined (STM32F091xC) +void HAL_PWR_PVDConfig(PWR_PVDTypeDef *sConfigPVD); +void HAL_PWR_EnablePVD(void); +void HAL_PWR_DisablePVD(void); +#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ + /* defined (STM32F071xB) || defined (STM32F072xB) || */ + /* defined (STM32F091xC) */ + +#if defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) +void HAL_PWR_EnableVddio2Monitor(void); +void HAL_PWR_DisableVddio2Monitor(void); +#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_PWR_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h @@ -0,0 +1,1281 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_rcc.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Header file of RCC HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_RCC_H +#define __STM32F0xx_HAL_RCC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Types RCC Exported Types + * @{ + */ + +/** + * @brief RCC PLL configuration structure definition + */ +typedef struct +{ + uint32_t PLLState; /*!< PLLState: The new state of the PLL. + This parameter can be a value of @ref RCC_PLL_Config */ + + uint32_t PLLSource; /*!< PLLSource: PLL entry clock source. + This parameter must be a value of @ref RCC_PLL_Clock_Source */ + + uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock + This parameter must be a value of @ref RCC_PLL_Prediv_Factor */ + + uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock + This parameter must be a value of @ref RCC_PLL_Multiplication_Factor */ + +}RCC_PLLInitTypeDef; + +/** + * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition + */ +typedef struct +{ + uint32_t OscillatorType; /*!< The Oscillators to be configured. + This parameter can be a value of @ref RCC_Oscillator_Type */ + + uint32_t HSEState; /*!< The new state of the HSE. + This parameter can be a value of @ref RCC_HSE_Config */ + + uint32_t LSEState; /*!< The new state of the LSE. + This parameter can be a value of @ref RCC_LSE_Config */ + + uint32_t HSIState; /*!< The new state of the HSI. + This parameter can be a value of @ref RCC_HSI_Config */ + + uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ + + uint32_t HSI14State; /*!< The new state of the HSI14. + This parameter can be a value of @ref RCC_HSI14_Config */ + + uint32_t HSI14CalibrationValue; /*!< The HSI14 calibration trimming value (default is RCC_HSI14CALIBRATION_DEFAULT). + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ + + uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32F07x and STM32F0x2 devices). + This parameter can be a value of @ref RCCEx_HSI48_Config */ + + uint32_t LSIState; /*!< The new state of the LSI. + This parameter can be a value of @ref RCC_LSI_Config */ + + RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ + +}RCC_OscInitTypeDef; + +/** + * @brief RCC System, AHB and APB busses clock configuration structure definition + */ +typedef struct +{ + uint32_t ClockType; /*!< The clock to be configured. + This parameter can be a value of @ref RCC_System_Clock_Type */ + + uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. + This parameter can be a value of @ref RCC_System_Clock_Source */ + + uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_AHB_Clock_Source */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_Clock_Source */ + +}RCC_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion + * @brief RCC registers bit address in the alias region + * @{ + */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) +/* --- CR Register ---*/ +#define RCC_CR_OFFSET (RCC_OFFSET + 0x00) +/* --- CFGR Register ---*/ +#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x04) +/* --- CIR Register ---*/ +#define RCC_CIR_OFFSET (RCC_OFFSET + 0x08) +/* --- BDCR Register ---*/ +#define RCC_BDCR_OFFSET (RCC_OFFSET + 0x20) +/* --- CSR Register ---*/ +#define RCC_CSR_OFFSET (RCC_OFFSET + 0x24) +/* --- CR2 Register ---*/ +#define RCC_CR2_OFFSET (RCC_OFFSET + 0x34) + +/* CR register byte 2 (Bits[23:16]) base address */ +#define RCC_CR_BYTE2_ADDRESS (PERIPH_BASE + RCC_CR_OFFSET + 0x02) + +/* CIR register byte 1 (Bits[15:8]) base address */ +#define RCC_CIR_BYTE1_ADDRESS (PERIPH_BASE + RCC_CIR_OFFSET + 0x01) + +/* CIR register byte 2 (Bits[23:16]) base address */ +#define RCC_CIR_BYTE2_ADDRESS (PERIPH_BASE + RCC_CIR_OFFSET + 0x02) + +/* CSR register byte 1 (Bits[15:8]) base address */ +#define RCC_CSR_BYTE1_ADDRESS (PERIPH_BASE + RCC_CSR_OFFSET + 0x01) + +/* BDCR register byte 0 (Bits[7:0] base address */ +#define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET) + +#define RCC_CFGR_PLLMUL_BITNUMBER 18 +#define RCC_CFGR2_PREDIV_BITNUMBER 0 + +/** + * @} + */ + +/** @defgroup RCC_Timeout RCC Timeout + * @{ + */ +/* LSE state change timeout */ +#define LSE_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */ + +/* Disable Backup domain write protection state change timeout */ +#define DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ +/** + * @} + */ + +/** @defgroup RCC_Oscillator_Type RCC Oscillator Type + * @{ + */ +#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000) +#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001) +#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002) +#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004) +#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008) +#define RCC_OSCILLATORTYPE_HSI14 ((uint32_t)0x00000010) +#define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020) + +#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)) +/** + * @} + */ + +/** @defgroup RCC_HSE_Config RCC HSE Config + * @{ + */ +#define RCC_HSE_OFF ((uint8_t)0x00) +#define RCC_HSE_ON ((uint8_t)0x01) +#define RCC_HSE_BYPASS ((uint8_t)0x05) + +#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ + ((HSE) == RCC_HSE_BYPASS)) +/** + * @} + */ + +/** @defgroup RCC_LSE_Config RCC_LSE_Config + * @{ + */ +#define RCC_LSE_OFF ((uint8_t)0x00) +#define RCC_LSE_ON ((uint8_t)0x01) +#define RCC_LSE_BYPASS ((uint8_t)0x05) + +#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ + ((LSE) == RCC_LSE_BYPASS)) +/** + * @} + */ + +/** @defgroup RCC_HSI_Config RCC HSI Config + * @{ + */ +#define RCC_HSI_OFF ((uint8_t)0x00) +#define RCC_HSI_ON ((uint8_t)0x01) + +#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON)) + +#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */ +/** + * @} + */ + +/** @defgroup RCC_HSI14_Config RCC HSI14 Config + * @{ + */ +#define RCC_HSI14_OFF ((uint32_t)0x00) +#define RCC_HSI14_ON RCC_CR2_HSI14ON +#define RCC_HSI14_ADC_CONTROL (~RCC_CR2_HSI14DIS) + +#define IS_RCC_HSI14(HSI14) (((HSI14) == RCC_HSI14_OFF) || ((HSI14) == RCC_HSI14_ON) || ((HSI14) == RCC_HSI14_ADC_CONTROL)) + +#define RCC_HSI14CALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI14 calibration trimming value */ +/** + * @} + */ + +/** @defgroup RCC_LSI_Config RCC LSI Config + * @{ + */ +#define RCC_LSI_OFF ((uint8_t)0x00) +#define RCC_LSI_ON ((uint8_t)0x01) + +#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON)) +/** + * @} + */ + +/** @defgroup RCC_PLL_Config RCC PLL Config + * @{ + */ +#define RCC_PLL_NONE ((uint8_t)0x00) +#define RCC_PLL_OFF ((uint8_t)0x01) +#define RCC_PLL_ON ((uint8_t)0x02) + +#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON)) +/** + * @} + */ + +/** @defgroup RCC_PLL_Prediv_Factor RCC PLL Prediv Factor + * @{ + */ +#define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1 +#define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2 +#define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3 +#define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4 +#define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5 +#define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6 +#define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7 +#define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8 +#define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9 +#define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10 +#define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11 +#define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12 +#define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13 +#define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14 +#define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15 +#define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16 + +#define IS_RCC_PREDIV(PREDIV) (((PREDIV) == RCC_PREDIV_DIV1) || ((PREDIV) == RCC_PREDIV_DIV2) || \ + ((PREDIV) == RCC_PREDIV_DIV3) || ((PREDIV) == RCC_PREDIV_DIV4) || \ + ((PREDIV) == RCC_PREDIV_DIV5) || ((PREDIV) == RCC_PREDIV_DIV6) || \ + ((PREDIV) == RCC_PREDIV_DIV7) || ((PREDIV) == RCC_PREDIV_DIV8) || \ + ((PREDIV) == RCC_PREDIV_DIV9) || ((PREDIV) == RCC_PREDIV_DIV10) || \ + ((PREDIV) == RCC_PREDIV_DIV11) || ((PREDIV) == RCC_PREDIV_DIV12) || \ + ((PREDIV) == RCC_PREDIV_DIV13) || ((PREDIV) == RCC_PREDIV_DIV14) || \ + ((PREDIV) == RCC_PREDIV_DIV15) || ((PREDIV) == RCC_PREDIV_DIV16)) +/** + * @} + */ + +/** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor + * @{ + */ +#define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2 +#define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3 +#define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4 +#define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5 +#define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6 +#define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7 +#define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8 +#define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9 +#define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10 +#define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11 +#define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12 +#define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13 +#define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14 +#define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15 +#define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16 + +#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLL_MUL2) || ((MUL) == RCC_PLL_MUL3) || \ + ((MUL) == RCC_PLL_MUL4) || ((MUL) == RCC_PLL_MUL5) || \ + ((MUL) == RCC_PLL_MUL6) || ((MUL) == RCC_PLL_MUL7) || \ + ((MUL) == RCC_PLL_MUL8) || ((MUL) == RCC_PLL_MUL9) || \ + ((MUL) == RCC_PLL_MUL10) || ((MUL) == RCC_PLL_MUL11) || \ + ((MUL) == RCC_PLL_MUL12) || ((MUL) == RCC_PLL_MUL13) || \ + ((MUL) == RCC_PLL_MUL14) || ((MUL) == RCC_PLL_MUL15) || \ + ((MUL) == RCC_PLL_MUL16)) +/** + * @} + */ + +/** @defgroup RCC_PLL_Clock_Source RCC PLL Clock Source + * @{ + */ +#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Type RCC System Clock Type + * @{ + */ +#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) +#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) +#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) + +#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \ + (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \ + (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)) +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source RCC System Clock Source + * @{ + */ +#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI +#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE +#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source_Status RCC System Clock Source Status + * @{ + */ +#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI +#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE +#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL +/** + * @} + */ + +/** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source + * @{ + */ +#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 +#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 +#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 +#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 +#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 +#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 +#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 +#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 +#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 + +#define IS_RCC_SYSCLK_DIV(DIV) (((DIV) == RCC_SYSCLK_DIV1) || ((DIV) == RCC_SYSCLK_DIV2) || \ + ((DIV) == RCC_SYSCLK_DIV4) || ((DIV) == RCC_SYSCLK_DIV8) || \ + ((DIV) == RCC_SYSCLK_DIV16) || ((DIV) == RCC_SYSCLK_DIV64) || \ + ((DIV) == RCC_SYSCLK_DIV128) || ((DIV) == RCC_SYSCLK_DIV256) || \ + ((DIV) == RCC_SYSCLK_DIV512)) +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Source RCC APB1 Clock Source + * @{ + */ +#define RCC_HCLK_DIV1 RCC_CFGR_PPRE_DIV1 +#define RCC_HCLK_DIV2 RCC_CFGR_PPRE_DIV2 +#define RCC_HCLK_DIV4 RCC_CFGR_PPRE_DIV4 +#define RCC_HCLK_DIV8 RCC_CFGR_PPRE_DIV8 +#define RCC_HCLK_DIV16 RCC_CFGR_PPRE_DIV16 + +#define IS_RCC_HCLK_DIV(DIV) (((DIV) == RCC_HCLK_DIV1) || ((DIV) == RCC_HCLK_DIV2) || \ + ((DIV) == RCC_HCLK_DIV4) || ((DIV) == RCC_HCLK_DIV8) || \ + ((DIV) == RCC_HCLK_DIV16)) +/** + * @} + */ + +/** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source + * @{ + */ +#define RCC_RTCCLKSOURCE_NONE RCC_BDCR_RTCSEL_NOCLOCK +#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE +#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI +#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE + +#define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_NONE) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_LSE) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32)) +/** + * @} + */ + +/** @defgroup RCC_USART1_Clock_Source RCC USART1 Clock Source + * @{ + */ +#define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK +#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK +#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE +#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI + +#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART1CLKSOURCE_HSI)) +/** + * @} + */ + +/** @defgroup RCC_I2C1_Clock_Source RCC I2C1 Clock Source + * @{ + */ +#define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI +#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK + +#define IS_RCC_I2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1CLKSOURCE_HSI) || \ + ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK)) +/** + * @} + */ + +/** @defgroup RCC_MCOx_Index RCC MCOx Index + * @{ + */ +#define RCC_MCO ((uint32_t)0x00000000) + +#define IS_RCC_MCO(MCOx) ((MCOx) == RCC_MCO) +/** + * @} + */ + +/** @defgroup RCC_MCO_Clock_Source RCC MCO Clock Source + * @{ + */ +#define RCC_MCOSOURCE_NONE RCC_CFGR_MCO_NOCLOCK +#define RCC_MCOSOURCE_LSI RCC_CFGR_MCO_LSI +#define RCC_MCOSOURCE_LSE RCC_CFGR_MCO_LSE +#define RCC_MCOSOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK +#define RCC_MCOSOURCE_HSI RCC_CFGR_MCO_HSI +#define RCC_MCOSOURCE_HSE RCC_CFGR_MCO_HSE +#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL +#define RCC_MCOSOURCE_HSI14 RCC_CFGR_MCO_HSI14 +/** + * @} + */ + +/** @defgroup RCC_Interrupt RCC Interrupt + * @{ + */ +#define RCC_IT_LSIRDY ((uint8_t)0x01) +#define RCC_IT_LSERDY ((uint8_t)0x02) +#define RCC_IT_HSIRDY ((uint8_t)0x04) +#define RCC_IT_HSERDY ((uint8_t)0x08) +#define RCC_IT_PLLRDY ((uint8_t)0x10) +#define RCC_IT_HSI14 ((uint8_t)0x20) +#define RCC_IT_CSS ((uint8_t)0x80) +/** + * @} + */ + +/** @defgroup RCC_Flag RCC Flag + * Elements values convention: 0XXYYYYYb + * - YYYYY : Flag position in the register + * - XX : Register index + * - 00: CR register + * - 01: CR2 register + * - 10: BDCR register + * - 11: CSR register + * @{ + */ +#define CR_REG_INDEX 0 +#define CR2_REG_INDEX 1 +#define BDCR_REG_INDEX 2 +#define CSR_REG_INDEX 3 + +/* Flags in the CR register */ +#define RCC_CR_HSIRDY_BitNumber 1 +#define RCC_CR_HSERDY_BitNumber 17 +#define RCC_CR_PLLRDY_BitNumber 25 + +#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_HSIRDY_BitNumber)) +#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_HSERDY_BitNumber)) +#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_PLLRDY_BitNumber)) + +/* Flags in the CR2 register */ +#define RCC_CR2_HSI14RDY_BitNumber 1 + +#define RCC_FLAG_HSI14RDY ((uint8_t)((CR2_REG_INDEX << 5) | RCC_CR2_HSI14RDY_BitNumber)) + +/* Flags in the BDCR register */ +#define RCC_BDCR_LSERDY_BitNumber 1 + +#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5) | RCC_BDCR_LSERDY_BitNumber)) + +/* Flags in the CSR register */ +#define RCC_CSR_LSIRDY_BitNumber 1 +#define RCC_CSR_V18PWRRSTF_BitNumber 23 +#define RCC_CSR_RMVF_BitNumber 24 +#define RCC_CSR_OBLRSTF_BitNumber 25 +#define RCC_CSR_PINRSTF_BitNumber 26 +#define RCC_CSR_PORRSTF_BitNumber 27 +#define RCC_CSR_SFTRSTF_BitNumber 28 +#define RCC_CSR_IWDGRSTF_BitNumber 29 +#define RCC_CSR_WWDGRSTF_BitNumber 30 +#define RCC_CSR_LPWRRSTF_BitNumber 31 + +#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LSIRDY_BitNumber)) +#define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LSIRDY_BitNumber)) +#define RCC_FLAG_RMV ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_RMVF_BitNumber)) +#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_OBLRSTF_BitNumber)) +#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_PINRSTF_BitNumber)) +#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_PORRSTF_BitNumber)) +#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_SFTRSTF_BitNumber)) +#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_IWDGRSTF_BitNumber)) +#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_WWDGRSTF_BitNumber)) +#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LPWRRSTF_BitNumber)) +/** + * @} + */ + +/** @defgroup RCC_Calibration_values RCC Calibration values + * @{ + */ +#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) + +/** + * @} + */ + +/** @addtogroup RCC_Timeout + * @{ + */ + +#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT +#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ +#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ +#define LSE_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */ +#define HSI14_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ +#define HSI48_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ +#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ +#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable + * @brief Enable or disable the AHB peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __GPIOA_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOAEN)) +#define __GPIOB_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOBEN)) +#define __GPIOC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOCEN)) +#define __GPIOF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOFEN)) +#define __CRC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_CRCEN)) +#define __DMA1_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA1EN)) +#define __SRAM_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_SRAMEN)) +#define __FLITF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_FLITFEN)) + +#define __GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN)) +#define __GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN)) +#define __GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN)) +#define __GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN)) +#define __CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN)) +#define __DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN)) +#define __SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN)) +#define __FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN)) +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable + * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __TIM3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN)) +#define __TIM14_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM14EN)) +#define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN)) +#define __I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN)) +#define __PWR_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_PWREN)) + +#define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) +#define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) +#define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) +#define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) +#define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SYSCFGEN)) +#define __ADC1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN)) +#define __TIM1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM1EN)) +#define __SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN)) +#define __TIM16_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM16EN)) +#define __TIM17_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM17EN)) +#define __USART1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART1EN)) +#define __DBGMCU_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_DBGMCUEN)) + +#define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) +#define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) +#define __TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) +#define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) +#define __TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN)) +#define __TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN)) +#define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) +#define __DBGMCU_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DBGMCUEN)) +/** + * @} + */ + +/** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset + * @brief Force or release AHB peripheral reset. + * @{ + */ +#define __AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF) +#define __GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST)) +#define __GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST)) +#define __GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST)) +#define __GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST)) + +#define __AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00) +#define __GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST)) +#define __GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST)) +#define __GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST)) +#define __GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST)) +/** + * @} + */ + +/** @defgroup RCC_APB1_Force_Release_Reset RCC APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF) +#define __TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) +#define __TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) +#define __WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) +#define __I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) +#define __PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) + +#define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00) +#define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) +#define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) +#define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) +#define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) +#define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) +/** + * @} + */ + +/** @defgroup RCC_APB2_Force_Release_Reset RCC APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ +#define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF) +#define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) +#define __ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST)) +#define __TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) +#define __SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) +#define __USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) +#define __TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST)) +#define __TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST)) +#define __DBGMCU_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DBGMCURST)) + +#define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00) +#define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) +#define __ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST)) +#define __TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) +#define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) +#define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) +#define __TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST)) +#define __TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST)) +#define __DBGMCU_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DBGMCURST)) +/** + * @} + */ + +/** @defgroup RCC_HSI_Configuration RCC HSI Configuration + * @{ + */ + +/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). + * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. + * It is used (enabled by hardware) as system clock source after startup + * from Reset, wakeup from STOP and STANDBY mode, or in case of failure + * of the HSE used directly or indirectly as system clock (if the Clock + * Security System CSS is enabled). + * @note HSI can not be stopped if it is used as system clock source. In this case, + * you have to select another source of the system clock then stop the HSI. + * @note After enabling the HSI, the application software should wait on HSIRDY + * flag to be set indicating that HSI clock is stable and can be used as + * system clock source. + * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator + * clock cycles. + */ +#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) +#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) + +/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI RC. + * @param __HSICalibrationValue__: specifies the calibration trimming value + * (default is RCC_HSICALIBRATION_DEFAULT). + * This parameter must be a number between 0 and 0x1F. + */ +#define RCC_CR_HSITRIM_BitNumber 3 +#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \ + MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_CR_HSITRIM_BitNumber) +/** + * @} + */ + +/** @defgroup RCC_LSI_Configuration RCC LSI Configuration + * @{ + */ + +/** @brief Macro to enable or disable the Internal Low Speed oscillator (LSI). + * @note After enabling the LSI, the application software should wait on + * LSIRDY flag to be set indicating that LSI clock is stable and can + * be used to clock the IWDG and/or the RTC. + * @note LSI can not be disabled if the IWDG is running. + * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator + * clock cycles. + */ +#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION) +#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION) +/** + * @} + */ + +/** @defgroup RCC_HSE_Configuration RCC HSE Configuration + * @{ + */ + +/** + * @brief Macro to configure the External High Speed oscillator (HSE). + * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application + * software should wait on HSERDY flag to be set indicating that HSE clock + * is stable and can be used to clock the PLL and/or system clock. + * @note HSE state can not be changed if it is used directly or through the + * PLL as system clock. In this case, you have to select another source + * of the system clock then change the HSE state (ex. disable it). + * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. + * @note This function reset the CSSON bit, so if the Clock security system(CSS) + * was previously enabled you have to enable it again after calling this + * function. + * @param __STATE__: specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after + * 6 HSE oscillator clock cycles. + * @arg RCC_HSE_ON: turn ON the HSE oscillator + * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock + */ +#define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *)RCC_CR_BYTE2_ADDRESS = (__STATE__)) + +/** + * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL. + * @note Predivision factor can not be changed if PLL is used as system clock + * In this case, you have to select another source of the system clock, disable the PLL and + * then change the HSE predivision factor. + * @param __HSEPredivValue__: specifies the division value applied to HSE. + * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16. + */ +#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSEPredivValue__) \ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSEPredivValue__)) +/** + * @} + */ + +/** @defgroup RCC_LSE_Configuration RCC LSE Configuration + * @{ + */ +/** + * @brief Macro to configure the External Low Speed oscillator (LSE). + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * HAL_PWR_EnableBkUpAccess() function before to configure the LSE + * (to be done once after reset). + * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application + * software should wait on LSERDY flag to be set indicating that LSE clock + * is stable and can be used to clock the RTC. + * @param __STATE__: specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after + * 6 LSE oscillator clock cycles. + * @arg RCC_LSE_ON: turn ON the LSE oscillator + * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock + */ +#define __HAL_RCC_LSE_CONFIG(__STATE__) \ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEON|RCC_BDCR_LSEBYP, (uint32_t)(__STATE__)) +/** + * @} + */ + +/** @defgroup RCC_HSI14_Configuration RCC_HSI14_Configuration + * @{ + */ + +/** @brief Macros to enable or disable the Internal 14Mhz High Speed oscillator (HSI14). + * @note The HSI14 is stopped by hardware when entering STOP and STANDBY modes. + * @note HSI14 can not be stopped if it is used as system clock source. In this case, + * you have to select another source of the system clock then stop the HSI14. + * @note After enabling the HSI14 with __HAL_RCC_HSI14_ENABLE(), the application software + * should wait on HSI14RDY flag to be set indicating that HSI clock is stable and can be + * used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used. + * @note When the HSI14 is stopped, HSI14RDY flag goes low after 6 HSI14 oscillator + * clock cycles. + */ +#define __HAL_RCC_HSI14_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14ON) +#define __HAL_RCC_HSI14_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14ON) + +/** @brief macros to Enable or Disable the Internal 14Mhz High Speed oscillator (HSI14) usage by ADC. + */ +#define __HAL_RCC_HSI14ADC_ENABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14DIS) +#define __HAL_RCC_HSI14ADC_DISABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14DIS) + +/** @brief Macro to adjust the Internal 14Mhz High Speed oscillator (HSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI14 RC. + * @param __HSI14CalibrationValue__: specifies the calibration trimming value + * (default is RCC_HSI14CALIBRATION_DEFAULT). + * This parameter must be a number between 0 and 0x1F. + */ +#define RCC_CR2_HSI14TRIM_BitNumber 3 +#define __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(__HSI14CalibrationValue__) \ + MODIFY_REG(RCC->CR2, RCC_CR2_HSI14TRIM, (uint32_t)(__HSI14CalibrationValue__) << RCC_CR2_HSI14TRIM_BitNumber) +/** + * @} + */ + +/** @defgroup RCC_USARTx_Clock_Config RCC USARTx Clock Config + * @{ + */ + +/** @brief Macro to configure the USART1 clock (USART1CLK). + * @param __USART1CLKSource__: specifies the USART1 clock source. + * This parameter can be one of the following values: + * @arg RCC_USART1CLKSOURCE_PCLK1: PCLK1 selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock + */ +#define __HAL_RCC_USART1_CONFIG(__USART1CLKSource__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSource__)) + +/** @brief Macro to get the USART1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART1CLKSOURCE_PCLK1: PCLK1 selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock + */ +#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW))) +/** + * @} + */ + +/** @defgroup RCC_I2Cx_Clock_Config RCC I2Cx Clock Config + * @{ + */ + +/** @brief Macro to configure the I2C1 clock (I2C1CLK). + * @param __I2C1CLKSource__: specifies the I2C1 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock + * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock + */ +#define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSource__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSource__)) + +/** @brief Macro to get the I2C1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock + * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock + */ +#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW))) +/** + * @} + */ + +/** @addtogroup RCC_USARTx_Clock_Config RCC USARTx Clock Config + * @{ + */ +/** @brief Macro to configure the USART2 clock (USART2CLK). + * @param __USART2CLKSource__: specifies the USART2 clock source. + * This parameter can be one of the following values: + * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock + */ +#define __HAL_RCC_USART2_CONFIG(__USART2CLKSource__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSource__)) + +/** @brief Macro to get the USART2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock + */ +#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW))) +/** + * @} + */ + +/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration + * @{ + */ +/** @brief Macros to enable or disable the the RTC clock. + * @note These macros must be used only after the RTC clock source was selected. + */ +#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) +#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) + +/** @brief Macro to configure the RTC clock (RTCCLK). + * @note As the RTC clock configuration bits are in the Backup domain and write + * access is denied to this domain after reset, you have to enable write + * access using the Power Backup Access macro before to configure + * the RTC clock source (to be done once after reset). + * @note Once the RTC clock is configured it can't be changed unless the + * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by + * a Power On Reset (POR). + * @param __RTCCLKSource__: specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg RCC_RTCCLKSOURCE_NONE: No clock selected as RTC clock + * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock + * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock + * @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32 + * + * @note If the LSE is used as RTC clock source, the RTC continues to + * work in STOP and STANDBY modes, and can be used as wakeup source. + * However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source, + * the RTC cannot be used in STOP and STANDBY modes. + * @note The system must always be configured so as to get a PCLK frequency greater than or + * equal to the RTCCLK frequency for a proper operation of the RTC. + */ +#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) \ + MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (uint32_t)(__RTCCLKSource__)) + +/** @brief Macro to get the RTC clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_RTCCLKSOURCE_NONE: No clock selected as RTC clock + * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock + * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock + * @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32 selected as RTC clock + */ +#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))) +/** + * @} + */ + +/** @defgroup RCC_Force_Release_Backup RCC Force Release Backup + * @{ + */ + +/** @brief Macro to force or release the Backup domain reset. + * @note These macros reset the RTC peripheral (including the backup registers) + * and the RTC clock source selection in RCC_CSR register. + * @note The BKPSRAM is not affected by this reset. + */ +#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST) +#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST) +/** + * @} + */ + +/** @defgroup RCC_PLL_Configuration RCC PLL Configuration + * @{ + */ + +/** @brief Macro to enable or disable the PLL. + * @note After enabling the PLL, the application software should wait on + * PLLRDY flag to be set indicating that PLL clock is stable and can + * be used as system clock source. + * @note The PLL can not be disabled if it is used as system clock source + * @note The PLL is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) +#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) + +/** @brief Macro to configure the PLL clock source, multiplication and division factors. + * @note This macro must be used only when the PLL is disabled. + * + * @param __RCC_PLLSource__: specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry + * @param __PREDIV__: specifies the predivider factor for PLL VCO input clock + * This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16. + * @param __PLLMUL__: specifies the multiplication factor for PLL VCO input clock + * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16. + * + */ +#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PREDIV__, __PLLMUL__) \ + do { \ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__))); \ + } while(0) +/** + * @} + */ + +/** @defgroup RCC_Get_Clock_source RCC Get Clock source + * @{ + */ + +/** @brief Macro to get the clock source used as system clock. + * @retval The clock source used as system clock. + * The returned value can be one of the following value: + * @arg RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock + * @arg RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock + * @arg RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock + */ +#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS))) + +/** @brief Macro to get the oscillator used as PLL clock source. + * @retval The oscillator used as PLL clock source. The returned value can be one + * of the following: + * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. + * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. + */ +#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC))) +/** + * @} + */ + +/** @defgroup RCC_Flags_Interrupts_Management RCC Flags Interrupts Management + * @brief macros to manage the specified RCC Flags and interrupts. + * @{ + */ + +/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[12:8] bits to enable + * the selected interrupts.). + * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt enable + * @arg RCC_IT_LSERDY: LSE ready interrupt enable + * @arg RCC_IT_HSIRDY: HSI ready interrupt enable + * @arg RCC_IT_HSERDY: HSE ready interrupt enable + * @arg RCC_IT_PLLRDY: PLL ready interrupt enable + * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable + * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices) + */ +#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *)RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) + +/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[12:8] bits to disable + * the selected interrupts.). + * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt enable + * @arg RCC_IT_LSERDY: LSE ready interrupt enable + * @arg RCC_IT_HSIRDY: HSI ready interrupt enable + * @arg RCC_IT_HSERDY: HSE ready interrupt enable + * @arg RCC_IT_PLLRDY: PLL ready interrupt enable + * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable + * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices) + */ +#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *)RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__)) + +/** @brief Clear the RCC's interrupt pending bits ( Perform Byte access to RCC_CIR[23:16] + * bits to clear the selected interrupt pending bits. + * @param __IT__: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt clear + * @arg RCC_IT_LSERDY: LSE ready interrupt clear + * @arg RCC_IT_HSIRDY: HSI ready interrupt clear + * @arg RCC_IT_HSERDY: HSE ready interrupt clear + * @arg RCC_IT_PLLRDY: PLL ready interrupt clear + * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt clear + * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt clear (only applicable to STM32F0X2 USB devices) + * @arg RCC_IT_CSS: Clock Security System interrupt clear + */ +#define __HAL_RCC_CLEAR_IT(__IT__) (*(__IO uint8_t *)RCC_CIR_BYTE2_ADDRESS = (__IT__)) + +/** @brief Check the RCC's interrupt has occurred or not. + * @param __IT__: specifies the RCC interrupt source to check. + * This parameter can be one of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt flag + * @arg RCC_IT_LSERDY: LSE ready interrupt flag + * @arg RCC_IT_HSIRDY: HSI ready interrupt flag + * @arg RCC_IT_HSERDY: HSE ready interrupt flag + * @arg RCC_IT_PLLRDY: PLL ready interrupt flag + * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt flag + * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt flag (only applicable to STM32F0X2 USB devices) + * @arg RCC_IT_CSS: Clock Security System interrupt flag + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_RCC_GET_IT(__IT__) ((RCC->CIR & (__IT__)) == (__IT__)) + +/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, + * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST + */ +#define __HAL_RCC_CLEAR_RESET_FLAGS() SET_BIT(RCC->CSR, RCC_CSR_RMVF) + +/** @brief Check RCC flag is set or not. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready + * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready + * @arg RCC_FLAG_PLLRDY: PLL clock ready + * @arg RCC_FLAG_HSI14RDY: HSI14 oscillator clock ready + * @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready (only applicable to STM32F0X2 USB devices) + * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready + * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready + * @arg RCC_FLAG_OBLRST: Option Byte Load reset + * @arg RCC_FLAG_PINRST: Pin reset + * @arg RCC_FLAG_PORRST: POR/PDR reset + * @arg RCC_FLAG_SFTRST: Software reset + * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset + * @arg RCC_FLAG_WWDGRST: Window Watchdog reset + * @arg RCC_FLAG_LPWRRST: Low Power reset + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define RCC_FLAG_MASK ((uint8_t)0x1F) +#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR : \ + (((__FLAG__) >> 5) == CR2_REG_INDEX)? RCC->CR2 : \ + (((__FLAG__) >> 5) == BDCR_REG_INDEX) ? RCC->BDCR : \ + RCC->CSR) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) + + + +/** + * @} + */ + +/** + * @} + */ + +/* Include RCC HAL Extension module */ +#include "stm32f0xx_hal_rcc_ex.h" + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup RCC_Exported_Functions + * @{ + */ + +/** @addtogroup RCC_Exported_Functions_Group1 + * @{ + */ + +/* Initialization and de-initialization functions ***************************/ +void HAL_RCC_DeInit(void); +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); + +/** + * @} + */ + +/** @addtogroup RCC_Exported_Functions_Group2 + * @{ + */ + +/* Peripheral Control functions *********************************************/ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); +void HAL_RCC_EnableCSS(void); +void HAL_RCC_DisableCSS(void); +uint32_t HAL_RCC_GetSysClockFreq(void); +uint32_t HAL_RCC_GetHCLKFreq(void); +uint32_t HAL_RCC_GetPCLK1Freq(void); +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); + +/* CSS NMI IRQ handler */ +void HAL_RCC_NMI_IRQHandler(void); + +/* User Callbacks in non blocking mode (IT mode) */ +void HAL_RCC_CCSCallback(void); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_RCC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h @@ -0,0 +1,1582 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_rcc_ex.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Header file of RCC HAL Extension module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_RCC_EX_H +#define __STM32F0xx_HAL_RCC_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup RCCEx_Exported_Types RCCEx Exported Types + * @{ + */ + +/** + * @brief RCC extended clocks structure definition + */ +#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< USART1 clock source + This parameter can be a value of @ref RCC_USART1_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source + This parameter can be a value of @ref RCC_I2C1_Clock_Source */ + +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx */ + +#if defined(STM32F042x6) || defined(STM32F048xx) +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< USART1 clock source + This parameter can be a value of @ref RCC_USART1_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source + This parameter can be a value of @ref RCC_I2C1_Clock_Source */ + + uint32_t CecClockSelection; /*!< HDMI CEC clock source + This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ + + uint32_t UsbClockSelection; /*!< USB clock source + This parameter can be a value of @ref RCCEx_USB_Clock_Source */ + +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F042x6 || STM32F048xx */ + +#if defined(STM32F051x8) || defined(STM32F058xx) +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< USART1 clock source + This parameter can be a value of @ref RCC_USART1_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source + This parameter can be a value of @ref RCC_I2C1_Clock_Source */ + + uint32_t CecClockSelection; /*!< HDMI CEC clock source + This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ + +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F051x8 || STM32F058xx */ + +#if defined(STM32F071xB) +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< USART1 clock source + This parameter can be a value of @ref RCC_USART1_Clock_Source */ + + uint32_t Usart2ClockSelection; /*!< USART2 clock source + This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source + This parameter can be a value of @ref RCC_I2C1_Clock_Source */ + + uint32_t CecClockSelection; /*!< HDMI CEC clock source + This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ + +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F071xB */ + +#if defined(STM32F072xB) || defined(STM32F078xx) +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< USART1 clock source + This parameter can be a value of @ref RCC_USART1_Clock_Source */ + + uint32_t Usart2ClockSelection; /*!< USART2 clock source + This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source + This parameter can be a value of @ref RCC_I2C1_Clock_Source */ + + uint32_t CecClockSelection; /*!< HDMI CEC clock source + This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ + + uint32_t UsbClockSelection; /*!< USB clock source + This parameter can be a value of @ref RCCEx_USB_Clock_Source */ + +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F072xB || STM32F078xx */ + + +#if defined(STM32F091xC) || defined(STM32F098xx) +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< USART1 clock source + This parameter can be a value of @ref RCC_USART1_Clock_Source */ + + uint32_t Usart2ClockSelection; /*!< USART2 clock source + This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ + + uint32_t Usart3ClockSelection; /*!< USART3 clock source + This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source + This parameter can be a value of @ref RCC_I2C1_Clock_Source */ + + uint32_t CecClockSelection; /*!< HDMI CEC clock source + This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ + +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F091xC || STM32F098xx */ + + +#if defined(STM32F042x6) || defined(STM32F048xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) +/** + * @brief RCC CRS Status structures definition + */ +typedef enum +{ + RCC_CRS_NONE = 0x00, + RCC_CRS_TIMEOUT = 0x01, + RCC_CRS_SYNCOK = 0x02, + RCC_CRS_SYNCWARM = 0x04, + RCC_CRS_SYNCERR = 0x08, + RCC_CRS_SYNCMISS = 0x10, + RCC_CRS_TRIMOV = 0x20 +} RCC_CRSStatusTypeDef; + +/** + * @brief RCC_CRS Init structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. + This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ + + uint32_t Source; /*!< Specifies the SYNC signal source. + This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ + + uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. + This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ + + uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event. + It can be calculated in using macro __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_) + This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/ + + uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. + This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */ + + uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. + This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ + +}RCC_CRSInitTypeDef; + +/** + * @brief RCC_CRS Synchronization structure definition + */ +typedef struct +{ + uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. + This parameter must be a number between 0 and 0xFFFF*/ + + uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. + This parameter must be a number between 0 and 0x3F */ + + uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter + value latched in the time of the last SYNC event. + This parameter must be a number between 0 and 0xFFFF */ + + uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the + frequency error counter latched in the time of the last SYNC event. + It shows whether the actual frequency is below or above the target. + This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ + +}RCC_CRSSynchroInfoTypeDef; + +#endif /* STM32F042x6 || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants + * @{ + */ + +/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection + * @{ + */ +#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) +#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) +#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020) +#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) + +#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ + RCC_PERIPHCLK_RTC)) +#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx */ + +#if defined(STM32F042x6) || defined(STM32F048xx) +#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) +#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020) +#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400) +#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) +#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000) + +#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ + RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_USB)) +#endif /* STM32F042x6 || STM32F048xx */ + +#if defined(STM32F051x8) || defined(STM32F058xx) +#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) +#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020) +#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400) +#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) + +#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ + RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC)) +#endif /* STM32F051x8 || STM32F058xx */ + +#if defined(STM32F071xB) +#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) +#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002) +#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020) +#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400) +#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) + +#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \ + RCC_PERIPHCLK_RTC)) +#endif /* STM32F071xB */ + +#if defined(STM32F072xB) || defined(STM32F078xx) +#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) +#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002) +#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020) +#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400) +#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) +#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000) + +#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \ + RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB)) +#endif /* STM32F072xB || STM32F078xx */ + +#if defined(STM32F091xC) || defined(STM32F098xx) +#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) +#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002) +#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020) +#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400) +#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) +#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00040000) + +#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \ + RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3 )) +#endif /* STM32F091xC || STM32F098xx */ + +/** + * @} + */ + +/** @defgroup RCCEx_MCO_Clock_Source RCCEx MCO Clock Source + * @{ + */ + +#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) + +#define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV) + +#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \ + ((SOURCE) == RCC_MCOSOURCE_LSI) || \ + ((SOURCE) == RCC_MCOSOURCE_LSE) || \ + ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_MCOSOURCE_HSI) || \ + ((SOURCE) == RCC_MCOSOURCE_HSE) || \ + ((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) || \ + ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) || \ + ((SOURCE) == RCC_MCOSOURCE_HSI14)) + +#endif /* STM32F030x6 || STM32F031x6 || STM32F038xx */ + +#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx) + +#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \ + ((SOURCE) == RCC_MCOSOURCE_LSI) || \ + ((SOURCE) == RCC_MCOSOURCE_LSE) || \ + ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_MCOSOURCE_HSI) || \ + ((SOURCE) == RCC_MCOSOURCE_HSE) || \ + ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) || \ + ((SOURCE) == RCC_MCOSOURCE_HSI14)) + +#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +#define RCC_MCOSOURCE_HSI48 RCC_CFGR_MCO_HSI48 +#define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV) + +#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \ + ((SOURCE) == RCC_MCOSOURCE_LSI) || \ + ((SOURCE) == RCC_MCOSOURCE_LSE) || \ + ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_MCOSOURCE_HSI) || \ + ((SOURCE) == RCC_MCOSOURCE_HSE) || \ + ((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) || \ + ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) || \ + ((SOURCE) == RCC_MCOSOURCE_HSI14) || \ + ((SOURCE) == RCC_MCOSOURCE_HSI48)) + +#define RCC_IT_HSI48 ((uint8_t)0x40) + +/* Flags in the CR2 register */ +#define RCC_CR2_HSI48RDY_BitNumber 16 + +#define RCC_FLAG_HSI48RDY ((uint8_t)((CR2_REG_INDEX << 5) | RCC_CR2_HSI48RDY_BitNumber)) + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ +/** + * @} + */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) + +/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source + * @{ + */ +#define RCC_USBCLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48 +#define RCC_USBCLKSOURCE_PLLCLK RCC_CFGR3_USBSW_PLLCLK + +#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_HSI48) || \ + ((SOURCE) == RCC_USBCLKSOURCE_PLLCLK)) +/** + * @} + */ + +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source + * @{ + */ +#define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK +#define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK +#define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE +#define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI + +#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART2CLKSOURCE_HSI)) +/** + * @} + */ + +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F091xC) || defined(STM32F098xx) + +/** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source + * @{ + */ +#define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK +#define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK +#define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE +#define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI + +#define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART3CLKSOURCE_HSI)) +/** + * @} + */ + +#endif /* STM32F091xC || STM32F098xx */ + + +#if defined(STM32F042x6) || defined(STM32F048xx) || \ + defined(STM32F051x8) || defined(STM32F058xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +/** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source + * @{ + */ +#define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244 +#define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE + +#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \ + ((SOURCE) == RCC_CECCLKSOURCE_LSE)) +/** + * @} + */ + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +/** @defgroup RCCEx_PLL_Clock_Source RCCEx PLL Clock Source + * @{ + */ +#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV +#define RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV + +#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ + ((SOURCE) == RCC_PLLSOURCE_HSI48) || \ + ((SOURCE) == RCC_PLLSOURCE_HSE)) +/** + * @} + */ + +/** @defgroup RCCEx_System_Clock_Source RCCEx System Clock Source + * @{ + */ +#define RCC_SYSCLKSOURCE_HSI48 RCC_CFGR_SW_HSI48 + +#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_HSI48)) + +#define RCC_SYSCLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48 + +#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI48)) +/** + * @} + */ + +/** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config + * @{ + */ +#define RCC_HSI48_OFF ((uint8_t)0x00) +#define RCC_HSI48_ON ((uint8_t)0x01) + +#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON)) +/** + * @} + */ + +#else +/** @defgroup RCCEx_PLL_Clock_Source RCCEx PLL Clock Source + * @{ + */ +#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2 + +#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ + ((SOURCE) == RCC_PLLSOURCE_HSE)) +/** + * @} + */ + +/** @defgroup RCCEx_System_Clock_Source RCCEx System Clock Source + * @{ + */ +#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK)) + +#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK)) +/** + * @} + */ + +/** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config + * @{ + */ +#define RCC_HSI48_OFF ((uint8_t)0x00) + +#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF)) +/** + * @} + */ + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + + +/** @defgroup RCCEx_MCOx_Clock_Prescaler RCCEx MCOx Clock Prescaler + * @{ + */ + +#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx) + +#define RCC_MCO_NODIV ((uint32_t)0x00000000) + +#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_NODIV)) + +#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */ + +#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || \ + defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F071xB) || \ + defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +#define RCC_MCO_DIV1 ((uint32_t)0x00000000) +#define RCC_MCO_DIV2 ((uint32_t)0x10000000) +#define RCC_MCO_DIV4 ((uint32_t)0x20000000) +#define RCC_MCO_DIV8 ((uint32_t)0x30000000) +#define RCC_MCO_DIV16 ((uint32_t)0x40000000) +#define RCC_MCO_DIV32 ((uint32_t)0x50000000) +#define RCC_MCO_DIV64 ((uint32_t)0x60000000) +#define RCC_MCO_DIV128 ((uint32_t)0x70000000) + +#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_DIV1) || ((DIV) == RCC_MCO_DIV2) || \ + ((DIV) == RCC_MCO_DIV4) || ((DIV) == RCC_MCO_DIV8) || \ + ((DIV) == RCC_MCO_DIV16) || ((DIV) == RCC_MCO_DIV32) || \ + ((DIV) == RCC_MCO_DIV64) || ((DIV) == RCC_MCO_DIV128)) + +#endif /* STM32F030x6 || STM32F031x6 || STM32F038xx || STM32F042x6 || STM32F048xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +/** + * @} + */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource + * @{ + */ +#define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00) /*!< Synchro Signal soucre GPIO */ +#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ +#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ + +#define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) || \ + ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) || \ + ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB)) +/** + * @} + */ + +/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider + * @{ + */ +#define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00) /*!< Synchro Signal not divided (default) */ +#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ +#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ +#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ +#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ +#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ +#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ +#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ + +#define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) || ((_DIV_) == RCC_CRS_SYNC_DIV2) || \ + ((_DIV_) == RCC_CRS_SYNC_DIV4) || ((_DIV_) == RCC_CRS_SYNC_DIV8) || \ + ((_DIV_) == RCC_CRS_SYNC_DIV16) || ((_DIV_) == RCC_CRS_SYNC_DIV32) || \ + ((_DIV_) == RCC_CRS_SYNC_DIV64) || ((_DIV_) == RCC_CRS_SYNC_DIV128)) +/** + * @} + */ + +/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity + * @{ + */ +#define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00) /*!< Synchro Active on rising edge (default) */ +#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ + +#define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) || \ + ((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING)) +/** + * @} + */ + +/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault + * @{ + */ +#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7F) /*!< The reset value of the RELOAD field corresponds + to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ + +#define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFF)) +/** + * @} + */ + +/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault + * @{ + */ +#define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22) /*!< Default Frequency error limit */ + +#define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFF)) +/** + * @} + */ + +/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault + * @{ + */ +#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20) /*!< The default value is 32, which corresponds to the middle of the trimming interval. + The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value + corresponds to a higher output frequency */ + +#define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3F)) +/** + * @} + */ + +/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection + * @{ + */ +#define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00) /*!< Upcounting direction, the actual frequency is above the target */ +#define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */ + +#define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) || \ + ((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN)) +/** + * @} + */ + +/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources + * @{ + */ +#define RCC_CRS_IT_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK */ +#define RCC_CRS_IT_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning */ +#define RCC_CRS_IT_ERR CRS_ISR_ERRF /*!< error */ +#define RCC_CRS_IT_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC */ +#define RCC_CRS_IT_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ +#define RCC_CRS_IT_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ +#define RCC_CRS_IT_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ + +/** + * @} + */ + +/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags + * @{ + */ +#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /* SYNC event OK flag */ +#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /* SYNC warning flag */ +#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /* Error flag */ +#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /* Expected SYNC flag */ +#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ +#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ +#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +/* Exported macros ------------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros + * @{ + */ + +/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable + * @brief Enables or disables the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(STM32F030x6) || defined(STM32F030x8) || \ + defined(STM32F051x8) || defined(STM32F058xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +#define __GPIOD_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIODEN)) + +#define __GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN)) + +#endif /* STM32F030x6 || STM32F030x8 || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx |[ */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +#define __GPIOE_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOEEN)) + +#define __GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN)) + +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || \ + defined(STM32F051x8) || defined(STM32F058xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +#define __TSC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_TSCEN)) + +#define __TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN)) + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F091xC) || defined(STM32F098xx) + +#define __DMA2_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA2EN)) + +#define __DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) + +#endif /* STM32F091xC || STM32F098xx */ + +/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#if defined(STM32F030x8) || \ + defined(STM32F042x6) || defined(STM32F048xx) || \ + defined(STM32F051x8) || defined(STM32F058xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +#define __USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN)) +#define __SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN)) + +#define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) +#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) + +#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F031x6) || defined(STM32F038xx) || \ + defined(STM32F042x6) || defined(STM32F048xx) || \ + defined(STM32F051x8) || defined(STM32F058xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +#define __TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN)) + +#define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) + +#endif /* STM32F031x6 || STM32F038xx || */ + /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F030x8) || \ + defined(STM32F051x8) || defined(STM32F058xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +#define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN)) +#define __I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN)) + +#define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) +#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) + +#endif /* STM32F030x8 || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F051x8) || defined(STM32F058xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +#define __DAC1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN)) + +#define __DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) + +#endif /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || \ + defined(STM32F051x8) || defined(STM32F058xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +#define __CEC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CECEN)) + +#define __CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +#define __TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN)) +#define __USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN)) +#define __USART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART4EN)) + +#define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) +#define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) +#define __USART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART4EN)) + +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || \ + defined(STM32F072xB) || defined(STM32F078xx) + +#define __USB_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USBEN)) + +#define __USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN)) + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F072xB || STM32F078xx */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +#define __CAN_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CANEN)) +#define __CAN_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN)) + +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +#define __CRS_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CRSEN)) + +#define __CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN)) + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F091xC) || defined(STM32F098xx) + +#define __USART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART5EN)) + +#define __USART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART5EN)) + +#endif /* STM32F091xC || STM32F098xx */ + +/** @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || \ + defined(STM32F051x8) || defined(STM32F058xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +#define __TIM15_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM15EN)) + +#define __TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN)) + +#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F091xC) || defined(STM32F098xx) + +#define __USART6_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART6EN)) +#define __USART7_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART7EN)) +#define __USART8_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART8EN)) + +#define __USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)) +#define __USART7_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART7EN)) +#define __USART8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART8EN)) + +#endif /* STM32F091xC || STM32F098xx */ + +/** + * @} + */ + + +/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset + * @brief Forces or releases peripheral reset. + * @{ + */ + +/** @brief Force or release AHB peripheral reset. + */ +#if defined(STM32F030x6) || defined(STM32F030x8) || \ + defined(STM32F051x8) || defined(STM32F058xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +#define __GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST)) + +#define __GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST)) + +#endif /* STM32F030x6 || STM32F030x8 || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +#define __GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST)) + +#define __GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST)) + +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || \ + defined(STM32F051x8) || defined(STM32F058xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +#define __TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST)) + +#define __TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST)) + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +/** @brief Force or release APB1 peripheral reset. + */ +#if defined(STM32F030x8) || \ + defined(STM32F042x6) || defined(STM32F048xx) || \ + defined(STM32F051x8) || defined(STM32F058xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +#define __USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) +#define __SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) + +#define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) +#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) + +#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F031x6) || defined(STM32F038xx) || \ + defined(STM32F042x6) || defined(STM32F048xx) || \ + defined(STM32F051x8) || defined(STM32F058xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +#define __TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) + +#define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) + +#endif /* STM32F031x6 || STM32F038xx || */ + /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F030x8) || \ + defined(STM32F051x8) || defined(STM32F058xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +#define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) +#define __I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) + +#define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) +#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) + +#endif /* STM32F030x8 || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F051x8) || defined(STM32F058xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +#define __DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) + +#define __DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) + +#endif /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || \ + defined(STM32F051x8) || defined(STM32F058xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +#define __CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) + +#define __CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +#define __TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) +#define __USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) +#define __USART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART4RST)) + +#define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) +#define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) +#define __USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART4RST)) + +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || \ + defined(STM32F072xB) || defined(STM32F078xx) + +#define __USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST)) + +#define __USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST)) + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F072xB || STM32F078xx */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +#define __CAN_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CANRST)) + +#define __CAN_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST)) + +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +#define __CRS_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CRSRST)) + +#define __CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST)) + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F091xC) || defined(STM32F098xx) + +#define __USART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART5RST)) + +#define __USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART5RST)) + +#endif /* STM32F091xC || STM32F098xx */ + + +/** @brief Force or release APB2 peripheral reset. + */ +#if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || \ + defined(STM32F051x8) || defined(STM32F058xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +#define __TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST)) + +#define __TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST)) + +#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F091xC) || defined(STM32F098xx) + +#define __USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST)) +#define __USART7_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART7RST)) +#define __USART8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART8RST)) + +#define __USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST)) +#define __USART7_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART7RST)) +#define __USART8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART8RST)) + +#endif /* STM32F091xC || STM32F098xx */ + +/** + * @} + */ + +/** @defgroup RCCEx_HSI48_Enable_Disable RCCEx HSI48 Enable Disable + * @brief Macros to enable or disable the Internal 48Mhz High Speed oscillator (HSI48). + * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. + * @note HSI48 can not be stopped if it is used as system clock source. In this case, + * you have to select another source of the system clock then stop the HSI14. + * @note After enabling the HSI48 with __HAL_RCC_HSI48_ENABLE(), the application software + * should wait on HSI48RDY flag to be set indicating that HSI48 clock is stable and can be + * used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used. + * @note When the HSI48 is stopped, HSI48RDY flag goes low after 6 HSI48 oscillator + * clock cycles. + * @{ + */ +#if defined(STM32F042x6) || defined(STM32F048xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI48ON) +#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON) + +/** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state. + * @retval The clock source can be one of the following values: + * @arg RCC_HSI48_ON: HSI48 enabled + * @arg RCC_HSI48_OFF: HSI48 disabled + */ +#define __HAL_RCC_GET_HSI48_STATE() \ + (((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CR2_HSI48ON)) != RESET) ? RCC_HSI48_ON : RCC_HSI48_OFF) + +#else + +/** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state. + * @retval The clock source can be one of the following values: + * @arg RCC_HSI_OFF: HSI48 disabled + */ +#define __HAL_RCC_GET_HSI48_STATE() RCC_HSI_OFF + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +/** + * @} + */ + +/** @defgroup RCCEx_Peripheral_Clock_Source_Config RCCEx Peripheral Clock Source Config + * @{ + */ +#if defined(STM32F042x6) || defined(STM32F048xx) || \ + defined(STM32F072xB) || defined(STM32F078xx) + +/** @brief Macro to configure the USB clock (USBCLK). + * @param __USBCLKSource__: specifies the USB clock source. + * This parameter can be one of the following values: + * @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock + * @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock + */ +#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USBSW, (uint32_t)(__USBCLKSource__)) + +/** @brief Macro to get the USB clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock + * @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock + */ +#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USBSW))) + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F072xB || STM32F078xx */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || \ + defined(STM32F051x8) || defined(STM32F058xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +/** @brief Macro to configure the CEC clock. + * @param __CECCLKSource__: specifies the CEC clock source. + * This parameter can be one of the following values: + * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock + * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock + */ +#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSource__)) + +/** @brief Macro to get the HDMI CEC clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock + * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock + */ +#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW))) + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || defined(STM32F098xx) */ + +#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || \ + defined(STM32F042x6) || defined(STM32F048xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +/** @brief Macro to configure the MCO clock. + * @param __MCOCLKSource__: specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock + * @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock + * @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock + * @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock + * @arg RCC_MCOSOURCE_PLLCLK_NODIV: PLLCLK selected as MCO clock + * @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock + * @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock + * @arg RCC_MCOSOURCE_HSI14: HSI14 selected as MCO clock + * @arg RCC_MCOSOURCE_HSI48: HSI48 selected as MCO clock + * @param __MCODiv__: specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCO_DIV1: MCO clock source is divided by 1 + * @arg RCC_MCO_DIV2: MCO clock source is divided by 2 + * @arg RCC_MCO_DIV4: MCO clock source is divided by 4 + * @arg RCC_MCO_DIV8: MCO clock source is divided by 8 + * @arg RCC_MCO_DIV16: MCO clock source is divided by 16 + * @arg RCC_MCO_DIV32: MCO clock source is divided by 32 + * @arg RCC_MCO_DIV64: MCO clock source is divided by 64 + * @arg RCC_MCO_DIV128: MCO clock source is divided by 128 + */ +#define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO | RCC_CFGR_MCOPRE), ((__MCOCLKSource__) | (__MCODiv__))) +#else + +/** @brief Macro to configure the MCO clock. + * @param __MCOCLKSource__: specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock + * @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock + * @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock + * @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock + * @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock + * @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock + * @arg RCC_MCOSOURCE_HSI14: HSI14 selected as MCO clock + * @arg RCC_MCOSOURCE_HSI48: HSI48 selected as MCO clock + * @param __MCODiv__: specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCO_NODIV: No division applied on MCO clock source + */ +#define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, __MCOCLKSource__) + +#endif /* STM32F030x6 || STM32F031x6 || STM32F038xx || */ + /* STM32F042x6 || STM32F048xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F091xC) || defined(STM32F098xx) +/** @brief Macro to configure the USART3 clock (USART3CLK). + * @param __USART3CLKSource__: specifies the USART3 clock source. + * This parameter can be one of the following values: + * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock + */ +#define __HAL_RCC_USART3_CONFIG(__USART3CLKSource__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSource__)) + +/** @brief Macro to get the USART3 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock + */ +#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW))) + +#endif /*STM32F091xC || STM32F098xx*/ +/** + * @} + */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +/** @defgroup RCCEx_IT_And_Flag RCCEx IT and Flag + * @{ + */ +/* Interrupt & Flag management */ + +/** + * @brief Enables the specified CRS interrupts. + * @param __INTERRUPT__: specifies the CRS interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg RCC_CRS_IT_SYNCOK + * @arg RCC_CRS_IT_SYNCWARN + * @arg RCC_CRS_IT_ERR + * @arg RCC_CRS_IT_ESYNC + * @retval None + */ +#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) (CRS->CR |= (__INTERRUPT__)) + +/** + * @brief Disables the specified CRS interrupts. + * @param __INTERRUPT__: specifies the CRS interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg RCC_CRS_IT_SYNCOK + * @arg RCC_CRS_IT_SYNCWARN + * @arg RCC_CRS_IT_ERR + * @arg RCC_CRS_IT_ESYNC + * @retval None + */ +#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) (CRS->CR &= ~(__INTERRUPT__)) + +/** @brief Check the CRS's interrupt has occurred or not. + * @param __INTERRUPT__: specifies the CRS interrupt source to check. + * This parameter can be one of the following values: + * @arg RCC_CRS_IT_SYNCOK + * @arg RCC_CRS_IT_SYNCWARN + * @arg RCC_CRS_IT_ERR + * @arg RCC_CRS_IT_ESYNC + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((CRS->CR & (__INTERRUPT__))? SET : RESET) + +/** @brief Clear the CRS's interrupt pending bits + * bits to clear the selected interrupt pending bits. + * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg RCC_CRS_IT_SYNCOK + * @arg RCC_CRS_IT_SYNCWARN + * @arg RCC_CRS_IT_ERR + * @arg RCC_CRS_IT_ESYNC + * @arg RCC_CRS_IT_TRIMOVF + * @arg RCC_CRS_IT_SYNCERR + * @arg RCC_CRS_IT_SYNCMISS + */ +/* CRS IT Error Mask */ +#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) + +#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) ((((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK)!= 0) ? (CRS->ICR |= CRS_ICR_ERRC) : \ + (CRS->ICR |= (__INTERRUPT__))) + +/** + * @brief Checks whether the specified CRS flag is set or not. + * @param _FLAG_: specifies the flag to check. + * This parameter can be one of the following values: + * @arg RCC_CRS_FLAG_SYNCOK + * @arg RCC_CRS_FLAG_SYNCWARN + * @arg RCC_CRS_FLAG_ERR + * @arg RCC_CRS_FLAG_ESYNC + * @arg RCC_CRS_FLAG_TRIMOVF + * @arg RCC_CRS_FLAG_SYNCERR + * @arg RCC_CRS_FLAG_SYNCMISS + * @retval The new state of _FLAG_ (TRUE or FALSE). + */ +#define __HAL_RCC_CRS_GET_FLAG(_FLAG_) ((CRS->ISR & (_FLAG_)) == (_FLAG_)) + +/** + * @brief Clears the CRS specified FLAG. + * @param _FLAG_: specifies the flag to clear. + * This parameter can be one of the following values: + * @arg RCC_CRS_FLAG_SYNCOK + * @arg RCC_CRS_FLAG_SYNCWARN + * @arg RCC_CRS_FLAG_ERR + * @arg RCC_CRS_FLAG_ESYNC + * @arg RCC_CRS_FLAG_TRIMOVF + * @arg RCC_CRS_FLAG_SYNCERR + * @arg RCC_CRS_FLAG_SYNCMISS + * @retval None + */ + +/* CRS Flag Error Mask */ +#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) + +#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) ((((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK)!= 0) ? (CRS->ICR |= CRS_ICR_ERRC) : \ + (CRS->ICR |= (__FLAG__))) + +/** + * @} + */ + +/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features + * @{ + */ +/** + * @brief Enables the oscillator clock for frequency error counter. + * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. + * @retval None + */ +#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER() (CRS->CR |= CRS_CR_CEN) + +/** + * @brief Disables the oscillator clock for frequency error counter. + * @retval None + */ +#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER() (CRS->CR &= ~CRS_CR_CEN) + +/** + * @brief Enables the automatic hardware adjustement of TRIM bits. + * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. + * @retval None + */ +#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB() (CRS->CR |= CRS_CR_AUTOTRIMEN) + +/** + * @brief Enables or disables the automatic hardware adjustement of TRIM bits. + * @retval None + */ +#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB() (CRS->CR &= ~CRS_CR_AUTOTRIMEN) + +/** + * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies + * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency + * of the synchronization source after prescaling. It is then decreased by one in order to + * reach the expected synchronization on the zero value. The formula is the following: + * RELOAD = (fTARGET / fSYNC) -1 + * @param _FTARGET_ Target frequency (value in Hz) + * @param _FSYNC_ Synchronization signal frequency (value in Hz) + * @retval None + */ +#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_) (((_FTARGET_) / (_FSYNC_)) - 1) + +/** + * @} + */ + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCCEx_Exported_Functions + * @{ + */ + +/** @addtogroup RCCEx_Exported_Functions_Group1 + * @{ + */ + +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); + +#if defined(STM32F042x6) || defined(STM32F048xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) +void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); +void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); +void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); +RCC_CRSStatusTypeDef HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_RCC_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rtc.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rtc.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rtc.h @@ -0,0 +1,785 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_rtc.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Header file of RTC HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_RTC_H +#define __STM32F0xx_HAL_RTC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup RTC RTC HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RTC_Exported_Types RTC Exported Types + * @{ + */ + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_RTC_STATE_RESET = 0x00, /*!< RTC not yet initialized or disabled */ + HAL_RTC_STATE_READY = 0x01, /*!< RTC initialized and ready for use */ + HAL_RTC_STATE_BUSY = 0x02, /*!< RTC process is ongoing */ + HAL_RTC_STATE_TIMEOUT = 0x03, /*!< RTC timeout state */ + HAL_RTC_STATE_ERROR = 0x04 /*!< RTC error state */ + +}HAL_RTCStateTypeDef; + +/** + * @brief RTC Configuration Structure definition + */ +typedef struct +{ + uint32_t HourFormat; /*!< Specifies the RTC Hour Format. + This parameter can be a value of @ref RTC_Hour_Formats */ + + uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */ + + uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */ + + uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output. + This parameter can be a value of @ref RTCEx_Output_selection_Definitions */ + + uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal. + This parameter can be a value of @ref RTC_Output_Polarity_Definitions */ + + uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode. + This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */ +}RTC_InitTypeDef; + +/** + * @brief RTC Time structure definition + */ +typedef struct +{ + uint8_t Hours; /*!< Specifies the RTC Time Hour. + This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected. + This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */ + + uint8_t Minutes; /*!< Specifies the RTC Time Minutes. + This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ + + uint8_t Seconds; /*!< Specifies the RTC Time Seconds. + This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ + + uint32_t SubSeconds; /*!< Specifies the RTC Time SubSeconds. + This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ + + uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time. + This parameter can be a value of @ref RTC_AM_PM_Definitions */ + + uint32_t DayLightSaving; /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment. + This parameter can be a value of @ref RTC_DayLightSaving_Definitions */ + + uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BCK bit + in CR register to store the operation. + This parameter can be a value of @ref RTC_StoreOperation_Definitions */ +}RTC_TimeTypeDef; + +/** + * @brief RTC Date structure definition + */ +typedef struct +{ + uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay. + This parameter can be a value of @ref RTC_WeekDay_Definitions */ + + uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format). + This parameter can be a value of @ref RTC_Month_Date_Definitions */ + + uint8_t Date; /*!< Specifies the RTC Date. + This parameter must be a number between Min_Data = 1 and Max_Data = 31 */ + + uint8_t Year; /*!< Specifies the RTC Date Year. + This parameter must be a number between Min_Data = 0 and Max_Data = 99 */ + +}RTC_DateTypeDef; + +/** + * @brief RTC Alarm structure definition + */ +typedef struct +{ + RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */ + + uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks. + This parameter can be a value of @ref RTC_AlarmMask_Definitions */ + + uint32_t AlarmSubSecondMask; /*!< Specifies the RTC Alarm SubSeconds Masks. + This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */ + + uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay. + This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ + + uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay. + If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range. + If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */ + + uint32_t Alarm; /*!< Specifies the alarm . + This parameter can be a value of @ref RTC_Alarms_Definitions */ +}RTC_AlarmTypeDef; + +/** + * @brief Time Handle Structure definition + */ +typedef struct +{ + RTC_TypeDef *Instance; /*!< Register base address */ + + RTC_InitTypeDef Init; /*!< RTC required parameters */ + + HAL_LockTypeDef Lock; /*!< RTC locking object */ + + __IO HAL_RTCStateTypeDef State; /*!< Time communication state */ + +}RTC_HandleTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RTC_Exported_Constants RTC Exported Constants + * @{ + */ + +/** @defgroup RTC_Mask_Definition RTC Mask Definition + * @{ + */ +/* Masks Definition */ +#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F) +#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F) +#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF) +#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F) + +#define RTC_TIMEOUT_VALUE 1000 +/** + * @} + */ + +/** @defgroup RTC_Hour_Formats RTC Hour Formats + * @{ + */ +#define RTC_HOURFORMAT_24 ((uint32_t)0x00000000) +#define RTC_HOURFORMAT_12 ((uint32_t)0x00000040) + +#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \ + ((FORMAT) == RTC_HOURFORMAT_24)) +/** + * @} + */ + +/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions + * @{ + */ +#define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000) +#define RTC_OUTPUT_POLARITY_LOW ((uint32_t)0x00100000) + +#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \ + ((POL) == RTC_OUTPUT_POLARITY_LOW)) +/** + * @} + */ + +/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT + * @{ + */ +#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000) +#define RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)0x00040000) + +#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \ + ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL)) + +/** + * @} + */ + +/** @defgroup RTC_Asynchronous_Predivider RTC Asynchronous Predivider + * @{ + */ +#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7F) +/** + * @} + */ + +/** @defgroup RTC_Synchronous_Predivider RTC Synchronous Predivider + * @{ + */ +#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FFF) +/** + * @} + */ + +/** @defgroup RTC_Time_Definitions RTC Time Definitions + * @{ + */ +#define IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12)) +#define IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23) +#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59) +#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59) +/** + * @} + */ + +/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions + * @{ + */ +#define RTC_HOURFORMAT12_AM ((uint8_t)0x00) +#define RTC_HOURFORMAT12_PM ((uint8_t)0x40) + +#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM)) +/** + * @} + */ + +/** @defgroup RTC_DayLightSaving_Definitions RTC DayLightSaving Definitions + * @{ + */ +#define RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000) +#define RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000) +#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000) + +#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \ + ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \ + ((SAVE) == RTC_DAYLIGHTSAVING_NONE)) +/** + * @} + */ + +/** @defgroup RTC_StoreOperation_Definitions RTC StoreOperation Definitions + * @{ + */ +#define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000) +#define RTC_STOREOPERATION_SET ((uint32_t)0x00040000) + +#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \ + ((OPERATION) == RTC_STOREOPERATION_SET)) +/** + * @} + */ + +/** @defgroup RTC_Input_parameter_format_definitions RTC Input parameter format definitions + * @{ + */ +#define FORMAT_BIN ((uint32_t)0x000000000) +#define FORMAT_BCD ((uint32_t)0x000000001) + +#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == FORMAT_BIN) || ((FORMAT) == FORMAT_BCD)) +/** + * @} + */ + +/** @defgroup RTC_Year_Date_Definitions RTC Year Date Definitions + * @{ + */ +#define IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99) +/** + * @} + */ + +/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions + * @{ + */ + +/* Coded in BCD format */ +#define RTC_MONTH_JANUARY ((uint8_t)0x01) +#define RTC_MONTH_FEBRUARY ((uint8_t)0x02) +#define RTC_MONTH_MARCH ((uint8_t)0x03) +#define RTC_MONTH_APRIL ((uint8_t)0x04) +#define RTC_MONTH_MAY ((uint8_t)0x05) +#define RTC_MONTH_JUNE ((uint8_t)0x06) +#define RTC_MONTH_JULY ((uint8_t)0x07) +#define RTC_MONTH_AUGUST ((uint8_t)0x08) +#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09) +#define RTC_MONTH_OCTOBER ((uint8_t)0x10) +#define RTC_MONTH_NOVEMBER ((uint8_t)0x11) +#define RTC_MONTH_DECEMBER ((uint8_t)0x12) + +#define IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12)) +#define IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31)) +/** + * @} + */ + +/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions + * @{ + */ +#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01) +#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02) +#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03) +#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04) +#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05) +#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06) +#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07) + +#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) +/** + * @} + */ + +/** @defgroup RTC_Alarm_Definitions RTC Alarm Definitions + * @{ + */ +#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31)) +#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) +/** + * @} + */ + +/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC AlarmDateWeekDay Definitions + * @{ + */ +#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000) +#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000) + +#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \ + ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY)) +/** + * @} + */ + +/** @defgroup RTC_AlarmMask_Definitions RTC AlarmMask Definitions + * @{ + */ +#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000) +#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4 +#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3 +#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2 +#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1 +#define RTC_ALARMMASK_ALL ((uint32_t)0x80808080) + +#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET) +/** + * @} + */ + +/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions + * @{ + */ +#define RTC_ALARM_A RTC_CR_ALRAE + +#define IS_ALARM(ALARM) ((ALARM) == RTC_ALARM_A) +/** + * @} + */ + +/** @defgroup RTC_Alarm_Sub_Seconds_Value RTC Alarm Sub Seconds Value + * @{ + */ +#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= (uint32_t)0x00007FFF) +/** + * @} + */ + + /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions + * @{ + */ +#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. + There is no comparison on sub seconds + for Alarm */ +#define RTC_ALARMSUBSECONDMASK_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm + comparison. Only SS[0] is compared. */ +#define RTC_ALARMSUBSECONDMASK_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm + comparison. Only SS[1:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm + comparison. Only SS[2:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm + comparison. Only SS[3:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm + comparison. Only SS[4:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm + comparison. Only SS[5:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm + comparison. Only SS[6:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm + comparison. Only SS[7:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm + comparison. Only SS[8:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm + comparison. Only SS[9:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm + comparison. Only SS[10:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm + comparison.Only SS[11:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm + comparison. Only SS[12:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm + comparison.Only SS[13:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_None ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match + to activate alarm. */ + +#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_None)) +/** + * @} + */ + +/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions + * @{ + */ +#define RTC_IT_TS ((uint32_t)0x00008000) +#define RTC_IT_WUT ((uint32_t)0x00004000) +#define RTC_IT_ALRA ((uint32_t)0x00001000) +#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */ +#define RTC_IT_TAMP1 ((uint32_t)0x00020000) +#define RTC_IT_TAMP2 ((uint32_t)0x00040000) +#define RTC_IT_TAMP3 ((uint32_t)0x00080000) +/** + * @} + */ + +/** @defgroup RTC_Flags_Definitions RTC Flags Definitions + * @{ + */ +#define RTC_FLAG_RECALPF ((uint32_t)0x00010000) +#define RTC_FLAG_TAMP3F ((uint32_t)0x00008000) +#define RTC_FLAG_TAMP2F ((uint32_t)0x00004000) +#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000) +#define RTC_FLAG_TSOVF ((uint32_t)0x00001000) +#define RTC_FLAG_TSF ((uint32_t)0x00000800) +#define RTC_FLAG_WUTF ((uint32_t)0x00000400) +#define RTC_FLAG_ALRAF ((uint32_t)0x00000100) +#define RTC_FLAG_INITF ((uint32_t)0x00000040) +#define RTC_FLAG_RSF ((uint32_t)0x00000020) +#define RTC_FLAG_INITS ((uint32_t)0x00000010) +#define RTC_FLAG_SHPF ((uint32_t)0x00000008) +#define RTC_FLAG_WUTWF ((uint32_t)0x00000004) +#define RTC_FLAG_ALRAWF ((uint32_t)0x00000001) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup RTC_Exported_Macros RTC Exported Macros + * @{ + */ + +/** @brief Reset RTC handle state + * @param __HANDLE__: RTC handle. + * @retval None + */ +#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET) + +/** + * @brief Disable the write protection for RTC registers. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \ + do{ \ + (__HANDLE__)->Instance->WPR = 0xCA; \ + (__HANDLE__)->Instance->WPR = 0x53; \ + } while(0) + +/** + * @brief Enable the write protection for RTC registers. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \ + do{ \ + (__HANDLE__)->Instance->WPR = 0xFF; \ + } while(0) + +/** + * @brief Enable the RTC ALARMA peripheral. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE)) + +/** + * @brief Disable the RTC ALARMA peripheral. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE)) + +/** + * @brief Enable the RTC Alarm interrupt. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_ALRA: Alarm A interrupt + * @retval None + */ +#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) + +/** + * @brief Disable the RTC Alarm interrupt. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_ALRA: Alarm A interrupt + * @retval None + */ +#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) + +/** + * @brief Check whether the specified RTC Alarm interrupt has occurred or not. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC Alarm interrupt sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_IT_ALRA: Alarm A interrupt + * @retval None + */ +#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __FLAG__) ((((((__HANDLE__)->Instance->ISR)& ((__FLAG__)>> 4)) & 0x0000FFFF) != RESET)? SET : RESET) + +/** + * @brief Get the selected RTC Alarm's flag status. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_FLAG_ALRAF + * @arg RTC_FLAG_ALRAWF + * @retval None + */ +#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) + +/** + * @brief Clear the RTC Alarm's pending flags. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_FLAG_ALRAF + * @retval None + */ +#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) + + +#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)0x00020000) /*!< External interrupt line 17 Connected to the RTC Alarm event */ +#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)0x00080000) /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events */ +#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the RTC Wakeup event */ + +/** + * @brief Enable the RTC Exti line. + * @param __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_EXTI_LINE_ALARM_EVENT + * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT + * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT + * @retval None + */ +#define __HAL_RTC_EXTI_ENABLE_IT(__EXTILINE__) (EXTI->IMR |= (__EXTILINE__)) + +/* alias define maintained for legacy */ +#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT + +/** + * @brief Disable the RTC Exti line. + * @param __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_EXTI_LINE_ALARM_EVENT + * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT + * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT + * @retval None + */ +#define __HAL_RTC_EXTI_DISABLE_IT(__EXTILINE__) (EXTI->IMR &= ~(__EXTILINE__)) + +/* alias define maintained for legacy */ +#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT + +/** + * @brief Generates a Software interrupt on selected EXTI line. + * @param __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_EXTI_LINE_ALARM_EVENT + * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT + * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT + * @retval None + */ +#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTILINE__) (EXTI->SWIER |= (__EXTILINE__)) + +/** + * @brief Clear the RTC Exti flags. + * @param __FLAG__: specifies the RTC Exti sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_EXTI_LINE_ALARM_EVENT + * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT + * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT + * @retval None + */ +#define __HAL_RTC_EXTI_CLEAR_FLAG(__FLAG__) (EXTI->PR = (__FLAG__)) + +/* alias define maintained for legacy */ +#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG + +/** + * @} + */ + +/* Include RTC HAL Extension module */ +#include "stm32f0xx_hal_rtc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RTC_Exported_Functions RTC Exported Functions + * @{ + */ + +/** @addtogroup RTC_Exported_Functions_Group1 + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc); +void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc); +void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc); +/** + * @} + */ + +/** @addtogroup RTC_Exported_Functions_Group2 + * @{ + */ + +/* RTC Time and Date functions ************************************************/ +HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); +/** + * @} + */ + +/** @addtogroup RTC_Exported_Functions_Group3 + * @{ + */ +/* RTC Alarm functions ********************************************************/ +HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm); +HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format); +void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc); +/** + * @} + */ + +/** @addtogroup RTC_Exported_Functions_Group4 + * @{ + */ +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc); +/** + * @} + */ + +/** @addtogroup RTC_Exported_Functions_Group5 + * @{ + */ +/* Peripheral State functions *************************************************/ +HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup RTC_Private_Functions + * @{ + */ +HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc); +uint8_t RTC_ByteToBcd2(uint8_t Value); +uint8_t RTC_Bcd2ToByte(uint8_t Value); +/** + * @} + */ + +/** + * @} + */ + + /** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_RTC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rtc_ex.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rtc_ex.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rtc_ex.h @@ -0,0 +1,708 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_rtc_ex.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Header file of RTC HAL Extension module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_RTC_EX_H +#define __STM32F0xx_HAL_RTC_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup RTCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup RTCEx_Exported_Types RTCEx Exported Types + * @{ + */ + +/** + * @brief RTC Tamper structure definition + */ +typedef struct +{ + uint32_t Tamper; /*!< Specifies the Tamper Pin. + This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions */ + + uint32_t Trigger; /*!< Specifies the Tamper Trigger. + This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */ + + uint32_t Filter; /*!< Specifies the RTC Filter Tamper. + This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */ + + uint32_t SamplingFrequency; /*!< Specifies the sampling frequency. + This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies_Definitions */ + + uint32_t PrechargeDuration; /*!< Specifies the Precharge Duration . + This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration_Definitions */ + + uint32_t TamperPullUp; /*!< Specifies the Tamper PullUp . + This parameter can be a value of @ref RTCEx_Tamper_Pull_UP_Definitions */ + + uint32_t TimeStampOnTamperDetection; /*!< Specifies the TimeStampOnTamperDetection. + This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */ +}RTC_TamperTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants + * @{ + */ + +/** @defgroup RTCEx_Output_selection_Definitions RTCEx Output Selection Definition + * @{ + */ +#define RTC_OUTPUT_DISABLE ((uint32_t)0x00000000) +#define RTC_OUTPUT_ALARMA ((uint32_t)0x00200000) +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) +#define RTC_OUTPUT_WAKEUP ((uint32_t)0x00600000) +#endif + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) +#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \ + ((OUTPUT) == RTC_OUTPUT_ALARMA) || \ + ((OUTPUT) == RTC_OUTPUT_WAKEUP)) +#else +#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \ + ((OUTPUT) == RTC_OUTPUT_ALARMA)) +#endif +/** + * @} + */ + +#if !defined(STM32F030x6) && !defined(STM32F030x8) +/** @defgroup RTCEx_Backup_Registers_Definitions RTCEx Backup Registers Definition + * @{ + */ +#define RTC_BKP_DR0 ((uint32_t)0x00000000) +#define RTC_BKP_DR1 ((uint32_t)0x00000001) +#define RTC_BKP_DR2 ((uint32_t)0x00000002) +#define RTC_BKP_DR3 ((uint32_t)0x00000003) +#define RTC_BKP_DR4 ((uint32_t)0x00000004) + +#define IS_RTC_BKP(BKP) ((BKP) < (uint32_t) RTC_BKP_NUMBER) +/** + * @} + */ +#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */ + +/** @defgroup RTCEx_Time_Stamp_Edges_definitions RTCEx Time Stamp Edges definition + * @{ + */ +#define RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000) +#define RTC_TIMESTAMPEDGE_FALLING ((uint32_t)0x00000008) + +#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \ + ((EDGE) == RTC_TIMESTAMPEDGE_FALLING)) +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Pins_Definitions RTCEx Tamper Pins Definition + * @{ + */ +#define RTC_TAMPER_1 RTC_TAFCR_TAMP1E +#define RTC_TAMPER_2 RTC_TAFCR_TAMP2E +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) +#define RTC_TAMPER_3 RTC_TAFCR_TAMP3E +#endif + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) +#define IS_TAMPER(TAMPER) (((TAMPER) == RTC_TAMPER_1) || \ + ((TAMPER) == RTC_TAMPER_2) || \ + ((TAMPER) == RTC_TAMPER_3)) +#else +#define IS_TAMPER(TAMPER) (((TAMPER) == RTC_TAMPER_1) || \ + ((TAMPER) == RTC_TAMPER_2)) +#endif +/** + * @} + */ + +/** @defgroup RTCEx_TimeStamp_Pin_Selections RTCEx TimeStamp Pin Selection + * @{ + */ +#define RTC_TIMESTAMPPIN_PC13 ((uint32_t)0x00000000) + +#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_PC13)) +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Trigger_Definitions RTCEx Tamper Trigger Definition + * @{ + */ +#define RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000) +#define RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002) +#define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE +#define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE + +#define IS_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \ + ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \ + ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \ + ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL)) + +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Filter_Definitions RTCEx Tamper Filter Definition + * @{ + */ +#define RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000) /*!< Tamper filter is disabled */ + +#define RTC_TAMPERFILTER_2SAMPLE ((uint32_t)0x00000800) /*!< Tamper is activated after 2 + consecutive samples at the active level */ +#define RTC_TAMPERFILTER_4SAMPLE ((uint32_t)0x00001000) /*!< Tamper is activated after 4 + consecutive samples at the active level */ +#define RTC_TAMPERFILTER_8SAMPLE ((uint32_t)0x00001800) /*!< Tamper is activated after 8 + consecutive samples at the active level. */ + +#define IS_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \ + ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \ + ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \ + ((FILTER) == RTC_TAMPERFILTER_8SAMPLE)) +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTCEx Tamper Sampling Frequencies Definition + * @{ + */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 32768 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 ((uint32_t)0x00000100) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 16384 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 8192 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 4096 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 2048 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 1024 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 512 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 256 */ + +#define IS_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \ + ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \ + ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \ + ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \ + ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \ + ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \ + ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || \ + ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256)) +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTCEx Tamper Pin Precharge Duration Definition + * @{ + */ +#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before + sampling during 1 RTCCLK cycle */ +#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before + sampling during 2 RTCCLK cycles */ +#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before + sampling during 4 RTCCLK cycles */ +#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before + sampling during 8 RTCCLK cycles */ + +#define IS_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \ + ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \ + ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \ + ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK)) +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTCEx Tamper TimeStampOnTamperDetection Definition + * @{ + */ +#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAFCR_TAMPTS) /*!< TimeStamp on Tamper Detection event saved */ +#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event is not saved */ + +#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \ + ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE)) +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTCEx Tamper Pull UP Definition + * @{ + */ +#define RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event saved */ +#define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAFCR_TAMPPUDIS) /*!< TimeStamp on Tamper Detection event is not saved */ + +#define IS_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \ + ((STATE) == RTC_TAMPER_PULLUP_DISABLE)) +/** + * @} + */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) +/** @defgroup RTCEx_Wakeup_Timer_Definitions RTCEx Wakeup Timer Definition + * @{ + */ +#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000) +#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 ((uint32_t)0x00000001) +#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 ((uint32_t)0x00000002) +#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 ((uint32_t)0x00000003) +#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS ((uint32_t)0x00000004) +#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t)0x00000006) + +#define IS_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \ + ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \ + ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \ + ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \ + ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \ + ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS)) + +#define IS_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF) +/** + * @} + */ +#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */ + +/** @defgroup RTCEx_Smooth_calib_period_Definitions RTCEx Smooth calib period Definition + * @{ + */ +#define RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000) /*!< If RTCCLK = 32768 Hz, Smooth calibation + period is 32s, else 2exp20 RTCCLK seconds */ +#define RTC_SMOOTHCALIB_PERIOD_16SEC ((uint32_t)0x00002000) /*!< If RTCCLK = 32768 Hz, Smooth calibation + period is 16s, else 2exp19 RTCCLK seconds */ +#define RTC_SMOOTHCALIB_PERIOD_8SEC ((uint32_t)0x00004000) /*!< If RTCCLK = 32768 Hz, Smooth calibation + period is 8s, else 2exp18 RTCCLK seconds */ + +#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \ + ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \ + ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC)) +/** + * @} + */ + +/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTCEx Smooth calib Plus pulses Definition + * @{ + */ +#define RTC_SMOOTHCALIB_PLUSPULSES_SET ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added + during a X -second window = Y - CALM[8:0] + with Y = 512, 256, 128 when X = 32, 16, 8 */ +#define RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited + during a 32-second window = CALM[8:0] */ + +#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \ + ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET)) +/** + * @} + */ + +/** @defgroup RTCEx_Smooth_calib_Minus_pulses_Definitions RTCEx Smooth calib Minus pulses Definition + * @{ + */ +#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF) +/** + * @} + */ + +/** @defgroup RTCEx_Add_1_Second_Parameter_Definition RTCEx Add 1 Second Parameter Definition + * @{ + */ +#define RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000) +#define RTC_SHIFTADD1S_SET ((uint32_t)0x80000000) + +#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \ + ((SEL) == RTC_SHIFTADD1S_SET)) +/** + * @} + */ + +/** @defgroup RTCEx_Substract_Fraction_Of_Second_Value RTCEx Substract Fraction Of Second Value + * @{ + */ +#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF) +/** + * @} + */ + + /** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output selection Definition + * @{ + */ +#define RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000) +#define RTC_CALIBOUTPUT_1HZ ((uint32_t)0x00080000) + +#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \ + ((OUTPUT) == RTC_CALIBOUTPUT_1HZ)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros + * @{ + */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) +/** + * @brief Enable the RTC WakeUp Timer peripheral. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE)) +#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */ + +/** + * @brief Enable the RTC TimeStamp peripheral. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE)) + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) +/** + * @brief Disable the RTC WakeUp Timer peripheral. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE)) +#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */ + +/** + * @brief Disable the RTC TimeStamp peripheral. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE)) + +/** + * @brief Enable the RTC calibration output. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE)) + +/** + * @brief Disable the calibration output. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE)) + +/** + * @brief Enable the clock reference detection. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON)) + +/** + * @brief Disable the clock reference detection. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON)) + +/** + * @brief Enable the RTC TimeStamp interrupt. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_IT_TS: TimeStamp interrupt + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) +/** + * @brief Enable the RTC WakeUpTimer interrupt. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_IT_WUT: WakeUpTimer A interrupt + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) +#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */ + +/** + * @brief Disable the RTC TimeStamp interrupt. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_IT_TS: TimeStamp interrupt + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) +/** + * @brief Disable the RTC WakeUpTimer interrupt. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_IT_WUT: WakeUpTimer A interrupt + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) +#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */ + +/** + * @brief Check whether the specified RTC Tamper interrupt has occurred or not. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC Tamper interrupt sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_IT_TAMP1 + * @retval None + */ +#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET) + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) +/** + * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_IT_WUT: WakeUpTimer A interrupt + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET) +#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */ + +/** + * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_IT_TS: TimeStamp interrupt + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET) + +/** + * @brief Get the selected RTC TimeStamp's flag status. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC TimeStamp Flag sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_FLAG_TSF + * @arg RTC_FLAG_TSOVF + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) +/** + * @brief Get the selected RTC WakeUpTimer's flag status. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC WakeUpTimer Flag sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_FLAG_WUTF + * @arg RTC_FLAG_WUTWF + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) +#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */ + +/** + * @brief Get the selected RTC Tamper's flag status. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_FLAG_TAMP1F + * @retval None + */ +#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) + +/** + * @brief Get the selected RTC shift operation's flag status. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC shift operation Flag is pending or not. + * This parameter can be: + * @arg RTC_FLAG_SHPF + * @retval None + */ +#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) + +/** + * @brief Clear the RTC Time Stamp's pending flags. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_FLAG_TSF + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) + +/** + * @brief Clear the RTC Tamper's pending flags. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_FLAG_TAMP1F + * @retval None + */ +#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) +/** + * @brief Clear the RTC Wake Up timer's pending flags. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_FLAG_WUTF + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) +#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RTCEx_Exported_Functions + * @{ + */ + +/** @addtogroup RTCEx_Exported_Functions_Group1 + * @{ + */ + +/* RTC TimeStamp and Tamper functions *****************************************/ +HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin); +HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin); +HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format); + +HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper); +HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper); +HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper); +void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc); + +void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc); +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) +void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc); +#endif +void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) +HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +#endif +/** + * @} + */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) +/** @addtogroup RTCEx_Exported_Functions_Group2 + * @{ + */ + +/* RTC Wake-up functions ******************************************************/ +HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock); +HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock); +uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc); +uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +#endif +/** + * @} + */ + +/** @addtogroup RTCEx_Exported_Functions_Group3 + * @{ + */ + +/* Extension Control functions ************************************************/ +#if !defined(STM32F030x6) && !defined(STM32F030x8) +void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data); +uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister); +#endif + +HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue); +HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS); +HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput); +HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc); +/** + * @} + */ + +/* Extension RTC features functions *******************************************/ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_RTC_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_smartcard.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_smartcard.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_smartcard.h @@ -0,0 +1,816 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_smartcard.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Header file of SMARTCARD HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_SMARTCARD_H +#define __STM32F0xx_HAL_SMARTCARD_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if !defined(STM32F030x4) && !defined(STM32F030x6) && !defined(STM32F030x8) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup SMARTCARD + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types + * @{ + */ + + +/** + * @brief SMARTCARD Init Structure definition + */ +typedef struct +{ + uint32_t BaudRate; /*!< Configures the SmartCard communication baud rate. + The baud rate register is computed using the following formula: + Baud Rate Register = ((PCLKx) / ((hsmartcard->Init.BaudRate))) */ + + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */ + + uint32_t StopBits; /*!< Specifies the number of stop bits @ref SMARTCARD_Stop_Bits. + Only 1.5 stop bits are authorized in SmartCard mode. */ + + uint16_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref SMARTCARD_Parity + @note The parity is enabled by default (PCE is forced to 1). + Since the WordLength is forced to 8 bits + parity, M is + forced to 1 and the parity bit is the 9th bit. */ + + uint16_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref SMARTCARD_Mode */ + + uint16_t CLKPolarity; /*!< Specifies the steady state of the serial clock. + This parameter can be a value of @ref SMARTCARD_Clock_Polarity */ + + uint16_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref SMARTCARD_Clock_Phase */ + + uint16_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref SMARTCARD_Last_Bit */ + + uint16_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. + Selecting the single sample method increases the receiver tolerance to clock + deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling. */ + + uint8_t Prescaler; /*!< Specifies the SmartCard Prescaler */ + + uint8_t GuardTime; /*!< Specifies the SmartCard Guard Time */ + + uint16_t NACKEnable; /*!< Specifies whether the SmartCard NACK transmission is enabled + in case of parity error. + This parameter can be a value of @ref SMARTCARD_NACK_State */ + + uint32_t TimeOutEnable; /*!< Specifies whether the receiver timeout is enabled. + This parameter can be a value of @ref SMARTCARD_Timeout_Enable*/ + + uint32_t TimeOutValue; /*!< Specifies the receiver time out value in number of baud blocks: + it is used to implement the Character Wait Time (CWT) and + Block Wait Time (BWT). It is coded over 24 bits. */ + + uint8_t BlockLength; /*!< Specifies the SmartCard Block Length in T=1 Reception mode. + This parameter can be any value from 0x0 to 0xFF */ + + uint8_t AutoRetryCount; /*!< Specifies the SmartCard auto-retry count (number of retries in + receive and transmit mode). When set to 0, retransmission is + disabled. Otherwise, its maximum value is 7 (before signalling + an error) */ + +}SMARTCARD_InitTypeDef; + +/** + * @brief SMARTCARD advanced features initalization structure definition + */ +typedef struct +{ + uint32_t AdvFeatureInit; /*!< Specifies which advanced SMARTCARD features is initialized. Several + advanced features may be initialized at the same time. This parameter + can be a value of @ref SMARTCARD_Advanced_Features_Initialization_Type */ + + uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted. + This parameter can be a value of @ref SMARTCARD_Tx_Inv */ + + uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted. + This parameter can be a value of @ref SMARTCARD_Rx_Inv */ + + uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic + vs negative/inverted logic). + This parameter can be a value of @ref SMARTCARD_Data_Inv */ + + uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped. + This parameter can be a value of @ref SMARTCARD_Rx_Tx_Swap */ + + uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled. + This parameter can be a value of @ref SMARTCARD_Overrun_Disable */ + + uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error. + This parameter can be a value of @ref SMARTCARD_DMA_Disable_on_Rx_Error */ + + uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line. + This parameter can be a value of @ref SMARTCARD_MSB_First */ +}SMARTCARD_AdvFeatureInitTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_SMARTCARD_STATE_RESET = 0x00, /*!< Peripheral is not initialized */ + HAL_SMARTCARD_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ + HAL_SMARTCARD_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ + HAL_SMARTCARD_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ + HAL_SMARTCARD_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ + HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ + HAL_SMARTCARD_STATE_TIMEOUT = 0x03, /*!< Timeout state */ + HAL_SMARTCARD_STATE_ERROR = 0x04 /*!< Error */ +}HAL_SMARTCARD_StateTypeDef; + +/** + * @brief HAL SMARTCARD Error Code structure definition + */ +typedef enum +{ + HAL_SMARTCARD_ERROR_NONE = 0x00, /*!< No error */ + HAL_SMARTCARD_ERROR_PE = 0x01, /*!< Parity error */ + HAL_SMARTCARD_ERROR_NE = 0x02, /*!< Noise error */ + HAL_SMARTCARD_ERROR_FE = 0x04, /*!< frame error */ + HAL_SMARTCARD_ERROR_ORE = 0x08, /*!< Overrun error */ + HAL_SMARTCARD_ERROR_DMA = 0x10, /*!< DMA transfer error */ + HAL_SMARTCARD_ERROR_RTO = 0x20 /*!< Receiver TimeOut error */ +}HAL_SMARTCARD_ErrorTypeDef; + +/** + * @brief SMARTCARD clock sources + */ +typedef enum +{ + SMARTCARD_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */ + SMARTCARD_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */ + SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */ + SMARTCARD_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */ + SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10 /*!< undefined clock source */ +}SMARTCARD_ClockSourceTypeDef; + +/** + * @brief SMARTCARD handle Structure definition + */ +typedef struct +{ + USART_TypeDef *Instance; /* USART registers base address */ + + SMARTCARD_InitTypeDef Init; /* SmartCard communication parameters */ + + SMARTCARD_AdvFeatureInitTypeDef AdvancedInit; /* SmartCard advanced features initialization parameters */ + + uint8_t *pTxBuffPtr; /* Pointer to SmartCard Tx transfer Buffer */ + + uint16_t TxXferSize; /* SmartCard Tx Transfer size */ + + uint16_t TxXferCount; /* SmartCard Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /* Pointer to SmartCard Rx transfer Buffer */ + + uint16_t RxXferSize; /* SmartCard Rx Transfer size */ + + uint16_t RxXferCount; /* SmartCard Rx Transfer Counter */ + + DMA_HandleTypeDef *hdmatx; /* SmartCard Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /* SmartCard Rx DMA Handle parameters */ + + HAL_LockTypeDef Lock; /* Locking object */ + + HAL_SMARTCARD_StateTypeDef State; /* SmartCard communication state */ + + HAL_SMARTCARD_ErrorTypeDef ErrorCode; /* SmartCard Error code */ + +}SMARTCARD_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SMARTCARD_Exported_Constants SMARTCARD Exported constants + * @{ + */ + +/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length + * @{ + */ +#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) +#define IS_SMARTCARD_WORD_LENGTH(LENGTH) ((LENGTH) == SMARTCARD_WORDLENGTH_9B) +/** + * @} + */ + +/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Stop Bits + * @{ + */ +#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP)) +#define IS_SMARTCARD_STOPBITS(STOPBITS) ((STOPBITS) == SMARTCARD_STOPBITS_1_5) +/** + * @} + */ + +/** @defgroup SMARTCARD_Parity SMARTCARD Parity + * @{ + */ +#define SMARTCARD_PARITY_EVEN ((uint16_t)USART_CR1_PCE) +#define SMARTCARD_PARITY_ODD ((uint16_t)(USART_CR1_PCE | USART_CR1_PS)) +#define IS_SMARTCARD_PARITY(PARITY) (((PARITY) == SMARTCARD_PARITY_EVEN) || \ + ((PARITY) == SMARTCARD_PARITY_ODD)) +/** + * @} + */ + +/** @defgroup SMARTCARD_Mode SMARTCARD Transfer Mode + * @{ + */ +#define SMARTCARD_MODE_RX ((uint16_t)USART_CR1_RE) +#define SMARTCARD_MODE_TX ((uint16_t)USART_CR1_TE) +#define SMARTCARD_MODE_TX_RX ((uint16_t)(USART_CR1_TE |USART_CR1_RE)) +#define IS_SMARTCARD_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00)) +/** + * @} + */ + +/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity + * @{ + */ +#define SMARTCARD_POLARITY_LOW ((uint16_t)0x0000) +#define SMARTCARD_POLARITY_HIGH ((uint16_t)USART_CR2_CPOL) +#define IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH)) +/** + * @} + */ + +/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase + * @{ + */ +#define SMARTCARD_PHASE_1EDGE ((uint16_t)0x0000) +#define SMARTCARD_PHASE_2EDGE ((uint16_t)USART_CR2_CPHA) +#define IS_SMARTCARD_PHASE(CPHA) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE)) +/** + * @} + */ + +/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit + * @{ + */ +#define SMARTCARD_LASTBIT_DISABLED ((uint16_t)0x0000) +#define SMARTCARD_LASTBIT_ENABLED ((uint16_t)USART_CR2_LBCL) +#define IS_SMARTCARD_LASTBIT(LASTBIT) (((LASTBIT) == SMARTCARD_LASTBIT_DISABLED) || \ + ((LASTBIT) == SMARTCARD_LASTBIT_ENABLED)) +/** + * @} + */ + +/** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD One Bit Sampling Method + * @{ + */ +#define SMARTCARD_ONEBIT_SAMPLING_DISABLED ((uint16_t)0x0000) +#define SMARTCARD_ONEBIT_SAMPLING_ENABLED ((uint16_t)USART_CR3_ONEBIT) +#define IS_SMARTCARD_ONEBIT_SAMPLING(ONEBIT) (((ONEBIT) == SMARTCARD_ONEBIT_SAMPLING_DISABLED) || \ + ((ONEBIT) == SMARTCARD_ONEBIT_SAMPLING_ENABLED)) +/** + * @} + */ + +/** @defgroup SMARTCARD_NACK_State SMARTCARD NACK State + * @{ + */ +#define SMARTCARD_NACK_ENABLED ((uint16_t)USART_CR3_NACK) +#define SMARTCARD_NACK_DISABLED ((uint16_t)0x0000) +#define IS_SMARTCARD_NACK(NACK) (((NACK) == SMARTCARD_NACK_ENABLED) || \ + ((NACK) == SMARTCARD_NACK_DISABLED)) +/** + * @} + */ + +/** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable + * @{ + */ +#define SMARTCARD_TIMEOUT_DISABLED ((uint32_t)0x00000000) +#define SMARTCARD_TIMEOUT_ENABLED ((uint32_t)USART_CR2_RTOEN) +#define IS_SMARTCARD_TIMEOUT(TIMEOUT) (((TIMEOUT) == SMARTCARD_TIMEOUT_DISABLED) || \ + ((TIMEOUT) == SMARTCARD_TIMEOUT_ENABLED)) +/** + * @} + */ + +/** @defgroup SMARTCARD_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type + * @{ + */ +#define SMARTCARD_ADVFEATURE_NO_INIT ((uint32_t)0x00000000) +#define SMARTCARD_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001) +#define SMARTCARD_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002) +#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004) +#define SMARTCARD_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008) +#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010) +#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020) +#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080) +#define IS_SMARTCARD_ADVFEATURE_INIT(INIT) ((INIT) <= (SMARTCARD_ADVFEATURE_NO_INIT | \ + SMARTCARD_ADVFEATURE_TXINVERT_INIT | \ + SMARTCARD_ADVFEATURE_RXINVERT_INIT | \ + SMARTCARD_ADVFEATURE_DATAINVERT_INIT | \ + SMARTCARD_ADVFEATURE_SWAP_INIT | \ + SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT | \ + SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \ + SMARTCARD_ADVFEATURE_MSBFIRST_INIT)) +/** + * @} + */ + +/** @defgroup SMARTCARD_Tx_Inv SMARTCARD advanced feature TX pin active level inversion + * @{ + */ +#define SMARTCARD_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000) +#define SMARTCARD_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV) +#define IS_SMARTCARD_ADVFEATURE_TXINV(TXINV) (((TXINV) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \ + ((TXINV) == SMARTCARD_ADVFEATURE_TXINV_ENABLE)) +/** + * @} + */ + +/** @defgroup SMARTCARD_Rx_Inv SMARTCARD advanced feature RX pin active level inversion + * @{ + */ +#define SMARTCARD_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000) +#define SMARTCARD_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV) +#define IS_SMARTCARD_ADVFEATURE_RXINV(RXINV) (((RXINV) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \ + ((RXINV) == SMARTCARD_ADVFEATURE_RXINV_ENABLE)) +/** + * @} + */ + +/** @defgroup SMARTCARD_Data_Inv SMARTCARD advanced feature Binary Data inversion + * @{ + */ +#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000) +#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV) +#define IS_SMARTCARD_ADVFEATURE_DATAINV(DATAINV) (((DATAINV) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \ + ((DATAINV) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE)) +/** + * @} + */ + +/** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD advanced feature RX TX pins swap + * @{ + */ +#define SMARTCARD_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000) +#define SMARTCARD_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP) +#define IS_SMARTCARD_ADVFEATURE_SWAP(SWAP) (((SWAP) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \ + ((SWAP) == SMARTCARD_ADVFEATURE_SWAP_ENABLE)) +/** + * @} + */ + +/** @defgroup SMARTCARD_Overrun_Disable SMARTCARD advanced feature Overrun Disable + * @{ + */ +#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000) +#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS) +#define IS_SMARTCARD_OVERRUN(OVERRUN) (((OVERRUN) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \ + ((OVERRUN) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE)) +/** + * @} + */ + +/** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD advanced feature DMA Disable on Rx Error + * @{ + */ +#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000) +#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE) +#define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(DMA) (((DMA) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \ + ((DMA) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR)) +/** + * @} + */ + +/** @defgroup SMARTCARD_MSB_First SMARTCARD advanced feature MSB first + * @{ + */ +#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000) +#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST) +#define IS_SMARTCARD_ADVFEATURE_MSBFIRST(MSBFIRST) (((MSBFIRST) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \ + ((MSBFIRST) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE)) +/** + * @} + */ + +/** @defgroup SMARTCARD_Flags SMARTCARD Flags + * Elements values convention: 0xXXXX + * - 0xXXXX : Flag mask in the ISR register + * @{ + */ +#define SMARTCARD_FLAG_REACK ((uint32_t)0x00400000) +#define SMARTCARD_FLAG_TEACK ((uint32_t)0x00200000) +#define SMARTCARD_FLAG_BUSY ((uint32_t)0x00010000) +#define SMARTCARD_FLAG_EOBF ((uint32_t)0x00001000) +#define SMARTCARD_FLAG_RTOF ((uint32_t)0x00000800) +#define SMARTCARD_FLAG_TXE ((uint32_t)0x00000080) +#define SMARTCARD_FLAG_TC ((uint32_t)0x00000040) +#define SMARTCARD_FLAG_RXNE ((uint32_t)0x00000020) +#define SMARTCARD_FLAG_ORE ((uint32_t)0x00000008) +#define SMARTCARD_FLAG_NE ((uint32_t)0x00000004) +#define SMARTCARD_FLAG_FE ((uint32_t)0x00000002) +#define SMARTCARD_FLAG_PE ((uint32_t)0x00000001) +/** + * @} + */ + +/** @defgroup SMARTCARD_Interrupt_definition SMARTCARD Interrupts Definition + * Elements values convention: 0000ZZZZ0XXYYYYYb + * - YYYYY : Interrupt source position in the XX register (5bits) + * - XX : Interrupt source register (2bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + * - ZZZZ : Flag position in the ISR register(4bits) + * @{ + */ + +#define SMARTCARD_IT_PE ((uint16_t)0x0028) +#define SMARTCARD_IT_TXE ((uint16_t)0x0727) +#define SMARTCARD_IT_TC ((uint16_t)0x0626) +#define SMARTCARD_IT_RXNE ((uint16_t)0x0525) + +#define SMARTCARD_IT_ERR ((uint16_t)0x0060) +#define SMARTCARD_IT_ORE ((uint16_t)0x0300) +#define SMARTCARD_IT_NE ((uint16_t)0x0200) +#define SMARTCARD_IT_FE ((uint16_t)0x0100) + +#define SMARTCARD_IT_EOB ((uint16_t)0x0C3B) +#define SMARTCARD_IT_RTO ((uint16_t)0x0B3A) +/** + * @} + */ + + +/** @defgroup SMARTCARD_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags + * @{ + */ +#define SMARTCARD_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ +#define SMARTCARD_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ +#define SMARTCARD_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */ +#define SMARTCARD_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */ +#define SMARTCARD_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ +#define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF /*!< Receiver Time Out Clear Flag */ +#define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF /*!< End Of Block Clear Flag */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Request_Parameters SMARTCARD Request Parameters + * @{ + */ +#define SMARTCARD_RXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */ +#define SMARTCARD_TXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */ +#define IS_SMARTCARD_REQUEST_PARAMETER(PARAM) (((PARAM) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \ + ((PARAM) == SMARTCARD_TXDATA_FLUSH_REQUEST)) +/** + * @} + */ + + +/** @defgroup SMARTCARD_CR3_SCARCNT_LSB_POS SMARTCARD auto retry counter LSB position in CR3 register + * @{ + */ +#define SMARTCARD_CR3_SCARCNT_LSB_POS ((uint32_t) 17) +/** + * @} + */ + +/** @defgroup SMARTCARD_GTPR_GT_LSB_POS SMARTCARD guard time value LSB position in GTPR register + * @{ + */ +#define SMARTCARD_GTPR_GT_LSB_POS ((uint32_t) 8) +/** + * @} + */ + +/** @defgroup SMARTCARD_RTOR_BLEN_LSB_POS SMARTCARD block length LSB position in RTOR register + * @{ + */ +#define SMARTCARD_RTOR_BLEN_LSB_POS ((uint32_t) 24) +/** + * @} + */ + +/** @defgroup SMARTCARD_Interruption_Mask SMARTCARD interruptions flag mask + * @{ + */ +#define SMARTCARD_IT_MASK ((uint16_t)0x001F) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros + * @{ + */ + +/** @brief Reset SMARTCARD handle state + * @param __HANDLE__: SMARTCARD handle. + * @retval None + */ +#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMARTCARD_STATE_RESET) + +/** @brief Checks whether the specified Smartcard flag is set or not. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg SMARTCARD_FLAG_REACK: Receive enable ackowledge flag + * @arg SMARTCARD_FLAG_TEACK: Transmit enable ackowledge flag + * @arg SMARTCARD_FLAG_BUSY: Busy flag + * @arg SMARTCARD_FLAG_EOBF: End of block flag + * @arg SMARTCARD_FLAG_RTOF: Receiver timeout flag + * @arg SMARTCARD_FLAG_TXE: Transmit data register empty flag + * @arg SMARTCARD_FLAG_TC: Transmission Complete flag + * @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag + * @arg SMARTCARD_FLAG_ORE: OverRun Error flag + * @arg SMARTCARD_FLAG_NE: Noise Error flag + * @arg SMARTCARD_FLAG_FE: Framing Error flag + * @arg SMARTCARD_FLAG_PE: Parity Error flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) + + +/** @brief Enables the specified SmartCard interrupt. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral. + * @param __INTERRUPT__: specifies the SMARTCARD interrupt to enable. + * This parameter can be one of the following values: + * @arg SMARTCARD_IT_EOBF: End Of Block interrupt + * @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt + * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt + * @arg SMARTCARD_IT_TC: Transmission complete interrupt + * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt + * @arg SMARTCARD_IT_PE: Parity Error interrupt + * @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) + +/** @brief Disables the specified SmartCard interrupt. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral. + * @param __INTERRUPT__: specifies the SMARTCARD interrupt to disable. + * This parameter can be one of the following values: + * @arg SMARTCARD_IT_EOBF: End Of Block interrupt + * @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt + * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt + * @arg SMARTCARD_IT_TC: Transmission complete interrupt + * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt + * @arg SMARTCARD_IT_PE: Parity Error interrupt + * @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) + + +/** @brief Checks whether the specified SmartCard interrupt has occurred or not. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral. + * @param __IT__: specifies the SMARTCARD interrupt to check. + * This parameter can be one of the following values: + * @arg SMARTCARD_IT_EOBF: End Of Block interrupt + * @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt + * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt + * @arg SMARTCARD_IT_TC: Transmission complete interrupt + * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt + * @arg SMARTCARD_IT_ORE: OverRun Error interrupt + * @arg SMARTCARD_IT_NE: Noise Error interrupt + * @arg SMARTCARD_IT_FE: Framing Error interrupt + * @arg SMARTCARD_IT_PE: Parity Error interrupt + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08))) + +/** @brief Checks whether the specified SmartCard interrupt interrupt source is enabled. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral. + * @param __IT__: specifies the SMARTCARD interrupt source to check. + * This parameter can be one of the following values: + * @arg SMARTCARD_IT_EOBF: End Of Block interrupt + * @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt + * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt + * @arg SMARTCARD_IT_TC: Transmission complete interrupt + * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt + * @arg SMARTCARD_IT_ORE: OverRun Error interrupt + * @arg SMARTCARD_IT_NE: Noise Error interrupt + * @arg SMARTCARD_IT_FE: Framing Error interrupt + * @arg SMARTCARD_IT_PE: Parity Error interrupt + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1 : \ + (((((uint8_t)(__IT__)) >> 5U) == 2)? (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & SMARTCARD_IT_MASK))) + + +/** @brief Clears the specified SMARTCARD ISR flag, in setting the proper ICR register flag. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral. + * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set + * to clear the corresponding interrupt + * This parameter can be one of the following values: + * @arg USART_CLEAR_PEF: Parity Error Clear Flag + * @arg USART_CLEAR_FEF: Framing Error Clear Flag + * @arg USART_CLEAR_NEF: Noise detected Clear Flag + * @arg USART_CLEAR_OREF: OverRun Error Clear Flag + * @arg USART_CLEAR_TCF: Transmission Complete Clear Flag + * @arg USART_CLEAR_RTOF: Receiver Time Out Clear Flag + * @arg USART_CLEAR_EOBF: End Of Block Clear Flag + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) + +/** @brief Set a specific SMARTCARD request flag. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral. + * @param __REQ__: specifies the request flag to set + * This parameter can be one of the following values: + * @arg SMARTCARD_RXDATA_FLUSH_REQUEST: Receive Data flush Request + * @arg SMARTCARD_TXDATA_FLUSH_REQUEST: Transmit data flush Request + * + * @retval None + */ +#define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) + +/** @brief Enable the USART associated to the SMARTCARD Handle + * @param __HANDLE__: specifies the SMARTCARD Handle. + * The Handle Instance can be UARTx where x: 1, 2, 3 to select the USART peripheral + * @retval None + */ +#define __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) + +/** @brief Disable the USART associated to the SMARTCARD Handle + * @param __HANDLE__: specifies the SMARTCARD Handle. + * The Handle Instance can be UARTx where x: 1, 2, 3 to select the USART peripheral + * @retval None + */ +#define __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) + +/** @brief Check the Baud rate range. The maximum Baud Rate is derived from the + * maximum clock on F0 (i.e. 48 MHz) divided by the oversampling used + * on the SMARTCARD (i.e. 16) + * @param __BAUDRATE__: Baud rate set by the configuration function. + * @retval Test result (TRUE or FALSE) + */ +#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4500001) + +/** @brief Check the block length range. The maximum SMARTCARD block length is 0xFF. + * @param __LENGTH__: block length. + * @retval Test result (TRUE or FALSE) + */ +#define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFF) + +/** @brief Check the receiver timeout value. The maximum SMARTCARD receiver timeout + * value is 0xFFFFFF. + * @param __TIMEOUTVALUE__: receiver timeout value. + * @retval Test result (TRUE or FALSE) + */ +#define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFF) + +/** @brief Check the SMARTCARD autoretry counter value. The maximum number of + * retransmissions is 0x7. + * @param __COUNT__: number of retransmissions + * @retval Test result (TRUE or FALSE) + */ +#define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7) + +/** + * @} + */ + +/* Include SMARTCARD HAL Extension module */ +#include "stm32f0xx_hal_smartcard_ex.h" + + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions + * @{ + */ + +/** @addtogroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard); +HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard); +/** + * @} + */ + +/** @addtogroup SMARTCARD_Exported_Functions_Group2 IO operation functions + * @{ + */ +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); +void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard); +/** + * @} + */ + +/** @addtogroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard); +uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* !defined(STM32F030x4) && !defined(STM32F030x6) && !defined(STM32F030x8) */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_SMARTCARD_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_smartcard_ex.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_smartcard_ex.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_smartcard_ex.h @@ -0,0 +1,330 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_smartcard_ex.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Header file of SMARTCARD HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_SMARTCARD_EX_H +#define __STM32F0xx_HAL_SMARTCARD_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if !defined(STM32F030x6) && !defined(STM32F030x8) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup SMARTCARDEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup SMARTCARD_Extended_Exported_Macros SMARTCARDEx Exported Macros + * @{ + */ + +/** @brief Reports the SMARTCARD clock source. + * @param __HANDLE__: specifies the SMARTCARD Handle + * @param __CLOCKSOURCE__ : output variable + * @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__. + */ +#if defined(STM32F031x6) || defined(STM32F038xx) +#define __HAL_SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } while(0) +#elif defined (STM32F030x8) || \ + defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F051x8) || defined (STM32F058xx) +#define __HAL_SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0) +#elif defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) +#define __HAL_SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == USART4) \ + { \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0) +#elif defined(STM32F091xC) || defined(STM32F098xx) +#define __HAL_SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ + case RCC_USART3CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART3CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART3CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART3CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART4) \ + { \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == USART5) \ + { \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == USART6) \ + { \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == USART7) \ + { \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == USART8) \ + { \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0) +#endif /* defined(STM32F031x6) || defined(STM32F038xx) */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/* Initialization and de-initialization functions ****************************/ +/* IO operation functions *****************************************************/ + +/** @addtogroup SMARTCARDEx_Exported_Functions + * @{ + */ + +/** @addtogroup SMARTCARDEx_Exported_Functions_Group1 + * @{ + */ + +/* Peripheral Control functions ***********************************************/ +void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength); +void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue); +HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard); +HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard); + +/* Peripheral State and Error functions ***************************************/ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_SMARTCARD_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_smbus.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_smbus.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_smbus.h @@ -0,0 +1,613 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_smbus.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Header file of SMBUS HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_SMBUS_H +#define __STM32F0xx_HAL_SMBUS_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup SMBUS + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SMBUS_Exported_Types SMBUS Exported Types + * @{ + */ + +/** + * @brief SMBUS Configuration Structure definition + */ +typedef struct +{ + uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value. + This parameter calculated by referring to SMBUS initialization + section in Reference manual */ + uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not. + This parameter can be a a value of @ref SMBUS_Analog_Filter */ + + uint32_t OwnAddress1; /*!< Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected. + This parameter can be a value of @ref SMBUS_addressing_mode */ + + uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. + This parameter can be a value of @ref SMBUS_dual_addressing_mode */ + + uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected + This parameter can be a 7-bit address. */ + + uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected + This parameter can be a value of @ref SMBUS_own_address2_masks. */ + + uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. + This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */ + + uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. + This parameter can be a value of @ref SMBUS_nostretch_mode */ + + uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected. + This parameter can be a value of @ref SMBUS_packet_error_check_mode */ + + uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected. + This parameter can be a value of @ref SMBUS_peripheral_mode */ + + uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value. + (Enable bits and different timeout values) + This parameter calculated by referring to SMBUS initialization + section in Reference manual */ +} SMBUS_InitTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_SMBUS_STATE_RESET = 0x00, /*!< SMBUS not yet initialized or disabled */ + HAL_SMBUS_STATE_READY = 0x01, /*!< SMBUS initialized and ready for use */ + HAL_SMBUS_STATE_BUSY = 0x02, /*!< SMBUS internal process is ongoing */ + HAL_SMBUS_STATE_MASTER_BUSY_TX = 0x12, /*!< Master Data Transmission process is ongoing */ + HAL_SMBUS_STATE_MASTER_BUSY_RX = 0x22, /*!< Master Data Reception process is ongoing */ + HAL_SMBUS_STATE_SLAVE_BUSY_TX = 0x32, /*!< Slave Data Transmission process is ongoing */ + HAL_SMBUS_STATE_SLAVE_BUSY_RX = 0x42, /*!< Slave Data Reception process is ongoing */ + HAL_SMBUS_STATE_TIMEOUT = 0x03, /*!< Timeout state */ + HAL_SMBUS_STATE_ERROR = 0x04, /*!< Reception process is ongoing */ + HAL_SMBUS_STATE_SLAVE_LISTEN = 0x08, /*!< Address Listen Mode is ongoing */ + /* Aliases for inter STM32 series compatibility */ + HAL_SMBUS_STATE_LISTEN = HAL_SMBUS_STATE_SLAVE_LISTEN +}HAL_SMBUS_StateTypeDef; + +/** + * @brief HAL SMBUS Error Code structure definition + */ +typedef enum +{ + HAL_SMBUS_ERROR_NONE = 0x00, /*!< No error */ + HAL_SMBUS_ERROR_BERR = 0x01, /*!< BERR error */ + HAL_SMBUS_ERROR_ARLO = 0x02, /*!< ARLO error */ + HAL_SMBUS_ERROR_ACKF = 0x04, /*!< ACKF error */ + HAL_SMBUS_ERROR_OVR = 0x08, /*!< OVR error */ + HAL_SMBUS_ERROR_HALTIMEOUT = 0x10, /*!< Timeout error */ + HAL_SMBUS_ERROR_BUSTIMEOUT = 0x20, /*!< Bus Timeout error */ + HAL_SMBUS_ERROR_ALERT = 0x40, /*!< Alert error */ + HAL_SMBUS_ERROR_PECERR = 0x80 /*!< PEC error */ + +}HAL_SMBUS_ErrorTypeDef; + +/** + * @brief SMBUS handle Structure definition + */ +typedef struct +{ + I2C_TypeDef *Instance; /*!< SMBUS registers base address */ + + SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */ + + uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */ + + uint16_t XferSize; /*!< SMBUS transfer size */ + + __IO uint16_t XferCount; /*!< SMBUS transfer counter */ + + __IO uint32_t XferOptions; /*!< SMBUS transfer options */ + + __IO HAL_SMBUS_StateTypeDef PreviousState; /*!< SMBUS communication Previous tate */ + + HAL_LockTypeDef Lock; /*!< SMBUS locking object */ + + __IO HAL_SMBUS_StateTypeDef State; /*!< SMBUS communication state */ + + __IO HAL_SMBUS_ErrorTypeDef ErrorCode; /*!< SMBUS Error code */ + +}SMBUS_HandleTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants + * @{ + */ + +/** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter + * @{ + */ +#define SMBUS_ANALOGFILTER_ENABLED ((uint32_t)0x00000000) +#define SMBUS_ANALOGFILTER_DISABLED I2C_CR1_ANFOFF + +#define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLED) || \ + ((FILTER) == SMBUS_ANALOGFILTER_DISABLED)) +/** + * @} + */ + +/** @defgroup SMBUS_addressing_mode SMBUS addressing mode + * @{ + */ +#define SMBUS_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001) +#define SMBUS_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002) + +#define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \ + ((MODE) == SMBUS_ADDRESSINGMODE_10BIT)) +/** + * @} + */ + +/** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode + * @{ + */ + +#define SMBUS_DUALADDRESS_DISABLED ((uint32_t)0x00000000) +#define SMBUS_DUALADDRESS_ENABLED I2C_OAR2_OA2EN + +#define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLED) || \ + ((ADDRESS) == SMBUS_DUALADDRESS_ENABLED)) +/** + * @} + */ + +/** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks + * @{ + */ + +#define SMBUS_OA2_NOMASK ((uint8_t)0x00) +#define SMBUS_OA2_MASK01 ((uint8_t)0x01) +#define SMBUS_OA2_MASK02 ((uint8_t)0x02) +#define SMBUS_OA2_MASK03 ((uint8_t)0x03) +#define SMBUS_OA2_MASK04 ((uint8_t)0x04) +#define SMBUS_OA2_MASK05 ((uint8_t)0x05) +#define SMBUS_OA2_MASK06 ((uint8_t)0x06) +#define SMBUS_OA2_MASK07 ((uint8_t)0x07) + +#define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \ + ((MASK) == SMBUS_OA2_MASK01) || \ + ((MASK) == SMBUS_OA2_MASK02) || \ + ((MASK) == SMBUS_OA2_MASK03) || \ + ((MASK) == SMBUS_OA2_MASK04) || \ + ((MASK) == SMBUS_OA2_MASK05) || \ + ((MASK) == SMBUS_OA2_MASK06) || \ + ((MASK) == SMBUS_OA2_MASK07)) +/** + * @} + */ + + +/** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode + * @{ + */ +#define SMBUS_GENERALCALL_DISABLED ((uint32_t)0x00000000) +#define SMBUS_GENERALCALL_ENABLED I2C_CR1_GCEN + +#define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLED) || \ + ((CALL) == SMBUS_GENERALCALL_ENABLED)) +/** + * @} + */ + +/** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode + * @{ + */ +#define SMBUS_NOSTRETCH_DISABLED ((uint32_t)0x00000000) +#define SMBUS_NOSTRETCH_ENABLED I2C_CR1_NOSTRETCH + +#define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLED) || \ + ((STRETCH) == SMBUS_NOSTRETCH_ENABLED)) +/** + * @} + */ + +/** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode + * @{ + */ +#define SMBUS_PEC_DISABLED ((uint32_t)0x00000000) +#define SMBUS_PEC_ENABLED I2C_CR1_PECEN + +#define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLED) || \ + ((PEC) == SMBUS_PEC_ENABLED)) +/** + * @} + */ + +/** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode + * @{ + */ +#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBHEN) +#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (uint32_t)(0x00000000) +#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP (uint32_t)(I2C_CR1_SMBDEN) + +#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \ + ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \ + ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)) +/** + * @} + */ + +/** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition + * @{ + */ + +#define SMBUS_SOFTEND_MODE ((uint32_t)0x00000000) +#define SMBUS_RELOAD_MODE I2C_CR2_RELOAD +#define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND +#define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE + +#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \ + ((MODE) == SMBUS_AUTOEND_MODE) || \ + ((MODE) == SMBUS_SOFTEND_MODE) || \ + ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \ + ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \ + ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \ + ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE ))) + +/** + * @} + */ + +/** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition + * @{ + */ + +#define SMBUS_NO_STARTSTOP ((uint32_t)0x00000000) +#define SMBUS_GENERATE_STOP I2C_CR2_STOP +#define SMBUS_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) +#define SMBUS_GENERATE_START_WRITE I2C_CR2_START + +#define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \ + ((REQUEST) == SMBUS_GENERATE_START_READ) || \ + ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \ + ((REQUEST) == SMBUS_NO_STARTSTOP)) + +/** + * @} + */ + +/** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition + * @{ + */ + +#define SMBUS_FIRST_FRAME ((uint32_t)(SMBUS_SOFTEND_MODE)) +#define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE)) +#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE +#define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE +#define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) +#define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) + +#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_FIRST_FRAME) || \ + ((REQUEST) == SMBUS_NEXT_FRAME) || \ + ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ + ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)) + +/** + * @} + */ + +/** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition + * @brief SMBUS Interrupt definition + * Elements values convention: 0xXXXXXXXX + * - XXXXXXXX : Interrupt control mask + * @{ + */ +#define SMBUS_IT_ERRI I2C_CR1_ERRIE +#define SMBUS_IT_TCI I2C_CR1_TCIE +#define SMBUS_IT_STOPI I2C_CR1_STOPIE +#define SMBUS_IT_NACKI I2C_CR1_NACKIE +#define SMBUS_IT_ADDRI I2C_CR1_ADDRIE +#define SMBUS_IT_RXI I2C_CR1_RXIE +#define SMBUS_IT_TXI I2C_CR1_TXIE +#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI) +#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI) +#define SMBUS_IT_ALERT (SMBUS_IT_ERRI) +#define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI) +/** + * @} + */ + +/** @defgroup SMBUS_Flag_definition SMBUS Flag definition + * @brief Flag definition + * Elements values convention: 0xXXXXYYYY + * - XXXXXXXX : Flag mask + * @{ + */ + +#define SMBUS_FLAG_TXE I2C_ISR_TXE +#define SMBUS_FLAG_TXIS I2C_ISR_TXIS +#define SMBUS_FLAG_RXNE I2C_ISR_RXNE +#define SMBUS_FLAG_ADDR I2C_ISR_ADDR +#define SMBUS_FLAG_AF I2C_ISR_NACKF +#define SMBUS_FLAG_STOPF I2C_ISR_STOPF +#define SMBUS_FLAG_TC I2C_ISR_TC +#define SMBUS_FLAG_TCR I2C_ISR_TCR +#define SMBUS_FLAG_BERR I2C_ISR_BERR +#define SMBUS_FLAG_ARLO I2C_ISR_ARLO +#define SMBUS_FLAG_OVR I2C_ISR_OVR +#define SMBUS_FLAG_PECERR I2C_ISR_PECERR +#define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT +#define SMBUS_FLAG_ALERT I2C_ISR_ALERT +#define SMBUS_FLAG_BUSY I2C_ISR_BUSY +#define SMBUS_FLAG_DIR I2C_ISR_DIR +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros ------------------------------------------------------------*/ +/** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros + * @{ + */ + +/** @brief Reset SMBUS handle state + * @param __HANDLE__: SMBUS handle. + * @retval None + */ +#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET) + +/** @brief Enable or disable the specified SMBUS interrupts. + * @param __HANDLE__: specifies the SMBUS Handle. + * This parameter can be SMBUS where x: 1 or 2 to select the SMBUS peripheral. + * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * This parameter can be one of the following values: + * @arg SMBUS_IT_ERRI: Errors interrupt enable + * @arg SMBUS_IT_TCI: Transfer complete interrupt enable + * @arg SMBUS_IT_STOPI: STOP detection interrupt enable + * @arg SMBUS_IT_NACKI: NACK received interrupt enable + * @arg SMBUS_IT_ADDRI: Address match interrupt enable + * @arg SMBUS_IT_RXI: RX interrupt enable + * @arg SMBUS_IT_TXI: TX interrupt enable + * + * @retval None + */ + +#define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) +#define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) + +/** @brief Checks if the specified SMBUS interrupt source is enabled or disabled. + * @param __HANDLE__: specifies the SMBUS Handle. + * This parameter can be SMBUS where x: 1 or 2 to select the SMBUS peripheral. + * @param __INTERRUPT__: specifies the SMBUS interrupt source to check. + * This parameter can be one of the following values: + * @arg SMBUS_IT_ERRI: Errors interrupt enable + * @arg SMBUS_IT_TCI: Transfer complete interrupt enable + * @arg SMBUS_IT_STOPI: STOP detection interrupt enable + * @arg SMBUS_IT_NACKI: NACK received interrupt enable + * @arg SMBUS_IT_ADDRI: Address match interrupt enable + * @arg SMBUS_IT_RXI: RX interrupt enable + * @arg SMBUS_IT_TXI: TX interrupt enable + * + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Checks whether the specified SMBUS flag is set or not. + * @param __HANDLE__: specifies the SMBUS Handle. + * This parameter can be SMBUS where x: 1 or 2 to select the SMBUS peripheral. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg SMBUS_FLAG_TXE: Transmit data register empty + * @arg SMBUS_FLAG_TXIS: Transmit interrupt status + * @arg SMBUS_FLAG_RXNE: Receive data register not empty + * @arg SMBUS_FLAG_ADDR: Address matched (slave mode) + * @arg SMBUS_FLAG_AF: NACK received flag + * @arg SMBUS_FLAG_STOPF: STOP detection flag + * @arg SMBUS_FLAG_TC: Transfer complete (master mode) + * @arg SMBUS_FLAG_TCR: Transfer complete reload + * @arg SMBUS_FLAG_BERR: Bus error + * @arg SMBUS_FLAG_ARLO: Arbitration lost + * @arg SMBUS_FLAG_OVR: Overrun/Underrun + * @arg SMBUS_FLAG_PECERR: PEC error in reception + * @arg SMBUS_FLAG_TIMEOUT: Timeout or Tlow detection flag + * @arg SMBUS_FLAG_ALERT: SMBus alert + * @arg SMBUS_FLAG_BUSY: Bus busy + * @arg SMBUS_FLAG_DIR: Transfer direction (slave mode) + * + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define SMBUS_FLAG_MASK ((uint32_t)0x0001FFFF) +#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK))) + +/** @brief Clears the SMBUS pending flags which are cleared by writing 1 in a specific bit. + * @param __HANDLE__: specifies the SMBUS Handle. + * This parameter can be SMBUS where x: 1 or 2 to select the SMBUS peripheral. + * @param __FLAG__: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg SMBUS_FLAG_ADDR: Address matched (slave mode) + * @arg SMBUS_FLAG_AF: NACK received flag + * @arg SMBUS_FLAG_STOPF: STOP detection flag + * @arg SMBUS_FLAG_BERR: Bus error + * @arg SMBUS_FLAG_ARLO: Arbitration lost + * @arg SMBUS_FLAG_OVR: Overrun/Underrun + * @arg SMBUS_FLAG_PECERR: PEC error in reception + * @arg SMBUS_FLAG_TIMEOUT: Timeout or Tlow detection flag + * @arg SMBUS_FLAG_ALERT: SMBus alert + * + * @retval None + */ +#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) + + +#define __HAL_SMBUS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE) +#define __HAL_SMBUS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE) + +#define __HAL_SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN))) +#define __HAL_SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) + +#define __HAL_SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) + +#define __HAL_SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17) +#define __HAL_SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16) +#define __HAL_SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) +#define __HAL_SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE) +#define __HAL_SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN) +#define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= I2C_CR2_NACK) + +#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF) +#define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions + * @{ + */ + +/** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions **********************************/ +HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus); +HAL_StatusTypeDef HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus); +void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus); +void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus); + +/** + * @} + */ + +/** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +/******* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); + +/******* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress); +HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); + +HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus); +HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus); +HAL_StatusTypeDef HAL_SMBUS_Slave_Listen_IT(SMBUS_HandleTypeDef *hsmbus); +HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus); + +/* Aliases for new API and to insure inter STM32 series compatibility */ +#define HAL_SMBUS_EnableListen_IT HAL_SMBUS_Slave_Listen_IT + +/******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */ +void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus); +void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus); +void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus); +void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); +void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus); +void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); +void HAL_SMBUS_SlaveAddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); +void HAL_SMBUS_SlaveListenCpltCallback(SMBUS_HandleTypeDef *hsmbus); + +/* Aliases for new API and to insure inter STM32 series compatibility */ +#define HAL_SMBUS_AddrCallback HAL_SMBUS_SlaveAddrCallback +#define HAL_SMBUS_ListenCpltCallback HAL_SMBUS_SlaveListenCpltCallback + +void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus); + +/** + * @} + */ + +/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions + * @{ + */ + +/* Peripheral State and Errors functions **************************************************/ +HAL_SMBUS_StateTypeDef HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus); +uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F0xx_HAL_SMBUS_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_spi.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_spi.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_spi.h @@ -0,0 +1,670 @@ + /** + ****************************************************************************** + * @file stm32f0xx_hal_spi.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Header file of SPI HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_SPI_H +#define __STM32F0xx_HAL_SPI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Types SPI Exported Types + * @{ + */ + +/** + * @brief SPI Configuration Structure definition + */ +typedef struct +{ + uint32_t Mode; /*!< Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_mode */ + + uint32_t Direction; /*!< Specifies the SPI bidirectional mode state. + This parameter can be a value of @ref SPI_Direction */ + + uint32_t DataSize; /*!< Specifies the SPI data size. + This parameter can be a value of @ref SPI_data_size */ + + uint32_t CLKPolarity; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity */ + + uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_LSB_transmission */ + + uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not . + This parameter can be a value of @ref SPI_TI_mode */ + + uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. + This parameter can be a value of @ref SPI_CRC_Calculation */ + + uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. + This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */ + + uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation. + CRC Length is only used with Data8 and Data16, not other data size + This parameter must 0 or 1 or 2*/ + + uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not . + This mode is activated by the NSSP bit in the SPIx_CR2 register and + it takes effect only if the SPI interface is configured as Motorola SPI + master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0, + CPOL setting is ignored).. */ +} SPI_InitTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_SPI_STATE_RESET = 0x00, /*!< Peripheral not Initialized */ + HAL_SPI_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ + HAL_SPI_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ + HAL_SPI_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */ + HAL_SPI_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */ + HAL_SPI_STATE_BUSY_TX_RX = 0x05, /*!< Data Transmission and Reception process is ongoing */ + HAL_SPI_STATE_TIMEOUT = 0x06, /*!< Timeout state */ + HAL_SPI_STATE_ERROR = 0x07 /*!< Data Transmission and Reception process is ongoing */ + +}HAL_SPI_StateTypeDef; + +/** + * @brief HAL SPI Error Code structure definition + */ +typedef enum +{ + HAL_SPI_ERROR_NONE = 0x00, /*!< No error */ + HAL_SPI_ERROR_MODF = 0x01, /*!< MODF error */ + HAL_SPI_ERROR_CRC = 0x02, /*!< CRC error */ + HAL_SPI_ERROR_OVR = 0x04, /*!< OVR error */ + HAL_SPI_ERROR_FRE = 0x08, /*!< FRE error */ + HAL_SPI_ERROR_DMA = 0x10, /*!< DMA transfer error */ + HAL_SPI_ERROR_FLAG = 0x20, /*!< Error on BSY/TXE/FTLVL/FRLVL Flag */ + HAL_SPI_ERROR_UNKNOW = 0x40, /*!< Unknow Error error */ +}HAL_SPI_ErrorTypeDef; + +/** + * @brief SPI handle Structure definition + */ +typedef struct __SPI_HandleTypeDef +{ + SPI_TypeDef *Instance; /* SPI registers base address */ + + SPI_InitTypeDef Init; /* SPI communication parameters */ + + uint8_t *pTxBuffPtr; /* Pointer to SPI Tx transfer Buffer */ + + uint16_t TxXferSize; /* SPI Tx Transfer size */ + + uint16_t TxXferCount; /* SPI Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /* Pointer to SPI Rx transfer Buffer */ + + uint16_t RxXferSize; /* SPI Rx Transfer size */ + + uint16_t RxXferCount; /* SPI Rx Transfer Counter */ + + uint32_t CRCSize; /* SPI CRC size used for the transfer */ + + void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /* function pointer on Rx IRQ handler */ + + void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /* function pointer on Tx IRQ handler */ + + DMA_HandleTypeDef *hdmatx; /* SPI Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /* SPI Rx DMA Handle parameters */ + + HAL_LockTypeDef Lock; /* Locking object */ + + HAL_SPI_StateTypeDef State; /* SPI communication state */ + + HAL_SPI_ErrorTypeDef ErrorCode; /* SPI Error code */ + +}SPI_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup SPI_Exported_Constants SPI Exported Constants + * @{ + */ + +/** @defgroup SPI_mode SPI mode + * @{ + */ + +#define SPI_MODE_SLAVE ((uint32_t)0x00000000) +#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) +#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \ + ((MODE) == SPI_MODE_MASTER)) +/** + * @} + */ + +/** @defgroup SPI_Direction SPI Direction + * @{ + */ +#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000) +#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY +#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE + +#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ + ((MODE) == SPI_DIRECTION_2LINES_RXONLY) ||\ + ((MODE) == SPI_DIRECTION_1LINE)) + +#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES) + +#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \ + ((MODE) == SPI_DIRECTION_1LINE)) +/** + * @} + */ + +/** @defgroup SPI_data_size SPI data size + * @{ + */ + +#define SPI_DATASIZE_4BIT ((uint16_t)0x0300) +#define SPI_DATASIZE_5BIT ((uint16_t)0x0400) +#define SPI_DATASIZE_6BIT ((uint16_t)0x0500) +#define SPI_DATASIZE_7BIT ((uint16_t)0x0600) +#define SPI_DATASIZE_8BIT ((uint16_t)0x0700) +#define SPI_DATASIZE_9BIT ((uint16_t)0x0800) +#define SPI_DATASIZE_10BIT ((uint16_t)0x0900) +#define SPI_DATASIZE_11BIT ((uint16_t)0x0A00) +#define SPI_DATASIZE_12BIT ((uint16_t)0x0B00) +#define SPI_DATASIZE_13BIT ((uint16_t)0x0C00) +#define SPI_DATASIZE_14BIT ((uint16_t)0x0D00) +#define SPI_DATASIZE_15BIT ((uint16_t)0x0E00) +#define SPI_DATASIZE_16BIT ((uint16_t)0x0F00) +#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \ + ((DATASIZE) == SPI_DATASIZE_15BIT) || \ + ((DATASIZE) == SPI_DATASIZE_14BIT) || \ + ((DATASIZE) == SPI_DATASIZE_13BIT) || \ + ((DATASIZE) == SPI_DATASIZE_12BIT) || \ + ((DATASIZE) == SPI_DATASIZE_11BIT) || \ + ((DATASIZE) == SPI_DATASIZE_10BIT) || \ + ((DATASIZE) == SPI_DATASIZE_9BIT) || \ + ((DATASIZE) == SPI_DATASIZE_8BIT) || \ + ((DATASIZE) == SPI_DATASIZE_7BIT) || \ + ((DATASIZE) == SPI_DATASIZE_6BIT) || \ + ((DATASIZE) == SPI_DATASIZE_5BIT) || \ + ((DATASIZE) == SPI_DATASIZE_4BIT)) + +/** + * @} + */ + +/** @defgroup SPI_Clock_Polarity SPI Clock Polarity + * @{ + */ + +#define SPI_POLARITY_LOW ((uint32_t)0x00000000) +#define SPI_POLARITY_HIGH SPI_CR1_CPOL +#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \ + ((CPOL) == SPI_POLARITY_HIGH)) +/** + * @} + */ + +/** @defgroup SPI_Clock_Phase SPI Clock Phase + * @{ + */ + +#define SPI_PHASE_1EDGE ((uint32_t)0x00000000) +#define SPI_PHASE_2EDGE SPI_CR1_CPHA +#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \ + ((CPHA) == SPI_PHASE_2EDGE)) +/** + * @} + */ + +/** @defgroup SPI_Slave_Select_management SPI Slave Select management + * @{ + */ + +#define SPI_NSS_SOFT SPI_CR1_SSM +#define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000) +#define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000) +#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \ + ((NSS) == SPI_NSS_HARD_INPUT) || \ + ((NSS) == SPI_NSS_HARD_OUTPUT)) + +/** + * @} + */ + +/** @defgroup SPI_NSS_pulse_management SPI NSS pulse management + * @{ + */ +#define SPI_NSS_PULSE_ENABLED SPI_CR2_NSSP +#define SPI_NSS_PULSE_DISABLED ((uint32_t)0x00000000) + +#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLED) || \ + ((NSSP) == SPI_NSS_PULSE_DISABLED)) + +/** + * @} + */ + + +/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler + * @{ + */ + +#define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000) +#define SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008) +#define SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010) +#define SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018) +#define SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020) +#define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028) +#define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030) +#define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038) +#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_256)) +/** + * @} + */ + +/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission + * @{ + */ + +#define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000) +#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST +#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \ + ((BIT) == SPI_FIRSTBIT_LSB)) +/** + * @} + */ + +/** @defgroup SPI_TI_mode SPI TI mode + * @{ + */ + +#define SPI_TIMODE_DISABLED ((uint32_t)0x00000000) +#define SPI_TIMODE_ENABLED SPI_CR2_FRF +#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLED) || \ + ((MODE) == SPI_TIMODE_ENABLED)) +/** + * @} + */ + +/** @defgroup SPI_CRC_Calculation SPI CRC Calculation + * @{ + */ + +#define SPI_CRCCALCULATION_DISABLED ((uint32_t)0x00000000) +#define SPI_CRCCALCULATION_ENABLED SPI_CR1_CRCEN +#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLED) || \ + ((CALCULATION) == SPI_CRCCALCULATION_ENABLED)) +/** + * @} + */ + +/** @defgroup SPI_CRC_length SPI CRC length + * @{ + * This parameter can be one of the following values: + * SPI_CRC_LENGTH_DATASIZE: aligned with the data size + * SPI_CRC_LENGTH_8BIT : CRC 8bit + * SPI_CRC_LENGTH_16BIT : CRC 16bit + */ +#define SPI_CRC_LENGTH_DATASIZE 0 +#define SPI_CRC_LENGTH_8BIT 1 +#define SPI_CRC_LENGTH_16BIT 2 +#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\ + ((LENGTH) == SPI_CRC_LENGTH_8BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_16BIT)) +/** + * @} + */ + +/** @defgroup SPI_FIFO_reception_threshold SPI FIFO reception threshold + * @{ + * This parameter can be one of the following values: + * SPI_RxFIFOThreshold_HF: RXNE event is generated if the FIFO + * level is greater or equal to 1/2(16-bits). + * SPI_RxFIFOThreshold_QF: RXNE event is generated if the FIFO + * level is greater or equal to 1/4(8 bits). + */ +#define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH +#define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH +#define SPI_RXFIFO_THRESHOLD_HF ((uint32_t)0x0) + +/** + * @} + */ + +/** @defgroup SPI_Interrupt_configuration_definition SPI Interrupt configuration definition + * @brief SPI Interrupt definition + * Elements values convention: 0xXXXXXXXX + * - XXXXXXXX : Interrupt control mask + * @{ + */ +#define SPI_IT_TXE SPI_CR2_TXEIE +#define SPI_IT_RXNE SPI_CR2_RXNEIE +#define SPI_IT_ERR SPI_CR2_ERRIE +/** + * @} + */ + + +/** @defgroup SPI_Flag_definition SPI Flag definition + * @brief Flag definition + * Elements values convention: 0xXXXXYYYY + * - XXXX : Flag register Index + * - YYYY : Flag mask + * @{ + */ +#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */ +#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */ +#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */ +#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */ +#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */ +#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */ +#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */ +#define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */ +#define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */ +/** + * @} + */ + +/** @defgroup SPI_transmission_fifo_status_level SPI transmission fifo status level + * @{ + */ + +#define SPI_FTLVL_EMPTY ((uint16_t)0x0000) +#define SPI_FTLVL_QUARTER_FULL ((uint16_t)0x0800) +#define SPI_FTLVL_HALF_FULL ((uint16_t)0x1000) +#define SPI_FTLVL_FULL ((uint16_t)0x1800) + +/** + * @} + */ + +/** @defgroup SPI_reception_fifo_status_level SPI reception fifo status level + * @{ + */ +#define SPI_FRLVL_EMPTY ((uint16_t)0x0000) +#define SPI_FRLVL_QUARTER_FULL ((uint16_t)0x0200) +#define SPI_FRLVL_HALF_FULL ((uint16_t)0x0400) +#define SPI_FRLVL_FULL ((uint16_t)0x0600) + +/** + * @} + */ + +/** + * @} + */ + + +/* Exported macros ------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Macros SPI Exported Macros + * @{ + */ + +/** @brief Reset SPI handle state + * @param __HANDLE__: SPI handle. + * @retval None + */ +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) + +/** @brief Enables or disables the specified SPI interrupts. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval None + */ + +#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__)) +#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (uint16_t)(~(__INTERRUPT__))) + +/** @brief Checks if the specified SPI interrupt source is enabled or disabled. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @param __INTERRUPT__: specifies the SPI interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Checks whether the specified SPI flag is set or not. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg SPI_FLAG_RXNE: Receive buffer not empty flag + * @arg SPI_FLAG_TXE: Transmit buffer empty flag + * @arg SPI_FLAG_CRCERR: CRC error flag + * @arg SPI_FLAG_MODF: Mode fault flag + * @arg SPI_FLAG_OVR: Overrun flag + * @arg SPI_FLAG_BSY: Busy flag + * @arg SPI_FLAG_FRE: Frame format error flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) + +/** @brief Clears the SPI CRCERR pending flag. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR)) + +/** @brief Clears the SPI MODF pending flag. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * + * @retval None + */ +#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\ + (__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_SPE);}while(0) + +/** @brief Clears the SPI OVR pending flag. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * + * @retval None + */ +#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->DR;\ + (__HANDLE__)->Instance->SR;}while(0) + +/** @brief Clears the SPI FRE pending flag. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * + * @retval None + */ +#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR) + +/** @brief Enables the SPI. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE) + +/** @brief Disables the SPI. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_SPE)) + +/** @brief Sets the SPI transmit-only mode. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE) + +/** @brief Sets the SPI receive-only mode. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_BIDIOE)) + +/** @brief Resets the CRC calculation of the SPI. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\ + (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0) + + +#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SPI_Exported_Functions + * @{ + */ + +/** @addtogroup SPI_Exported_Functions_Group1 + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_InitExtended(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi); +void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); +void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); +/** + * @} + */ + +/** @addtogroup SPI_Exported_Functions_Group2 + * @{ + */ + +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); +void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); +/** + * @} + */ + +/** @addtogroup SPI_Exported_Functions_Group3 + * @{ + */ + +/* Peripheral State and Error functions ***************************************/ +HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_SPI_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim.h @@ -0,0 +1,1645 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_tim.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Header file of TIM HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_TIM_H +#define __STM32F0xx_HAL_TIM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup TIM + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIM_Exported_Types TIM Exported Types + * @{ + */ + +/** + * @brief TIM Time base Configuration Structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint32_t Period; /*!< Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_ClockDivision */ + + uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_Base_InitTypeDef; + +/** + * @brief TIM Output Compare Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for TIM1 and TIM8. */ + + uint32_t OCFastMode; /*!< Specifies the Fast mode state. + This parameter can be a value of @ref TIM_Output_Fast_State + @note This parameter is valid only in PWM1 and PWM2 mode. */ + + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_OC_InitTypeDef; + +/** + * @brief TIM One Pulse Mode Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for TIM1 and TIM8. */ + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ + + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_OnePulse_InitTypeDef; + + +/** + * @brief TIM Input Capture Configuration Structure definition + */ +typedef struct +{ + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_IC_InitTypeDef; + +/** + * @brief TIM Encoder Configuration Structure definition + */ +typedef struct +{ + uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Mode */ + + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t IC1Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t IC2Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC2Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_Encoder_InitTypeDef; + + +/** + * @brief Clock Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClockSource; /*!< TIM clock sources + This parameter can be a value of @ref TIM_Clock_Source */ + uint32_t ClockPolarity; /*!< TIM clock polarity + This parameter can be a value of @ref TIM_Clock_Polarity */ + uint32_t ClockPrescaler; /*!< TIM clock prescaler + This parameter can be a value of @ref TIM_Clock_Prescaler */ + uint32_t ClockFilter; /*!< TIM clock filter + This parameter can be a value of @ref TIM_Clock_Filter */ +}TIM_ClockConfigTypeDef; + +/** + * @brief Clear Input Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClearInputState; /*!< TIM clear Input state + This parameter can be ENABLE or DISABLE */ + uint32_t ClearInputSource; /*!< TIM clear Input sources + This parameter can be a value of @ref TIM_ClearInput_Source */ + uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity + This parameter can be a value of @ref TIM_ClearInput_Polarity */ + uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler + This parameter can be a value of @ref TIM_ClearInput_Prescaler */ + uint32_t ClearInputFilter; /*!< TIM Clear Input filter + This parameter can be a value of @ref TIM_ClearInput_Filter */ +}TIM_ClearInputConfigTypeDef; + +/** + * @brief TIM Slave configuration Structure definition + */ +typedef struct { + uint32_t SlaveMode; /*!< Slave mode selection + This parameter can be a value of @ref TIM_Slave_Mode */ + uint32_t InputTrigger; /*!< Input Trigger source + This parameter can be a value of @ref TIM_Trigger_Selection */ + uint32_t TriggerPolarity; /*!< Input Trigger polarity + This parameter can be a value of @ref TIM_Trigger_Polarity */ + uint32_t TriggerPrescaler; /*!< Input trigger prescaler + This parameter can be a value of @ref TIM_Trigger_Prescaler */ + uint32_t TriggerFilter; /*!< Input trigger filter + This parameter can be a value of @ref TIM_Trigger_Filter */ + +}TIM_SlaveConfigTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */ + HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ + HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ + HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */ + HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */ +}HAL_TIM_StateTypeDef; + +/** + * @brief HAL Active channel structures definition + */ +typedef enum +{ + HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */ + HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */ + HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */ + HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */ + HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */ +}HAL_TIM_ActiveChannel; + +/** + * @brief TIM Time Base Handle Structure definition + */ +typedef struct +{ + TIM_TypeDef *Instance; /*!< Register base address */ + TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ + HAL_TIM_ActiveChannel Channel; /*!< Active channel */ + DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array + This array is accessed by a @ref DMA_Handle_index */ + HAL_LockTypeDef Lock; /*!< Locking object */ + __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ +}TIM_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIM_Exported_Constants TIM Exported Constants + * @{ + */ + +/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity + * @{ + */ +#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Polarity TIM ETR Polarity + * @{ + */ +#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */ +#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler + * @{ + */ +#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */ +#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */ +#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */ +#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */ +/** + * @} + */ + +/** @defgroup TIM_Counter_Mode TIM Counter Mode + * @{ + */ + +#define TIM_COUNTERMODE_UP ((uint32_t)0x0000) +#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR +#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 +#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 +#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS + +#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \ + ((MODE) == TIM_COUNTERMODE_DOWN) || \ + ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \ + ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \ + ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3)) +/** + * @} + */ + +/** @defgroup TIM_ClockDivision TIM Clock Division + * @{ + */ + +#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000) +#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0) +#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1) + +#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \ + ((DIV) == TIM_CLOCKDIVISION_DIV2) || \ + ((DIV) == TIM_CLOCKDIVISION_DIV4)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare & PWM modes + * @{ + */ + +#define TIM_OCMODE_TIMING ((uint32_t)0x0000) +#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0) +#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1) +#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1) +#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) +#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M) +#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) +#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2) + +#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \ + ((MODE) == TIM_OCMODE_PWM2)) + +#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \ + ((MODE) == TIM_OCMODE_ACTIVE) || \ + ((MODE) == TIM_OCMODE_INACTIVE) || \ + ((MODE) == TIM_OCMODE_TOGGLE) || \ + ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \ + ((MODE) == TIM_OCMODE_FORCED_INACTIVE)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_State TIM Output Compare State + * @{ + */ + +#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000) +#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E) + +#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \ + ((STATE) == TIM_OUTPUTSTATE_ENABLE)) +/** + * @} + */ +/** @defgroup TIM_Output_Fast_State TIM Output Fast State + * @{ + */ +#define TIM_OCFAST_DISABLE ((uint32_t)0x0000) +#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE) + +#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \ + ((STATE) == TIM_OCFAST_ENABLE)) +/** + * @} + */ +/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State + * @{ + */ + +#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000) +#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE) + +#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \ + ((STATE) == TIM_OUTPUTNSTATE_ENABLE)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity + * @{ + */ + +#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000) +#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P) + +#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \ + ((POLARITY) == TIM_OCPOLARITY_LOW)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity + * @{ + */ + +#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000) +#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP) + +#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \ + ((POLARITY) == TIM_OCNPOLARITY_LOW)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State + * @{ + */ + +#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1) +#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000) +#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \ + ((STATE) == TIM_OCIDLESTATE_RESET)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State + * @{ + */ + +#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N) +#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000) +#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \ + ((STATE) == TIM_OCNIDLESTATE_RESET)) +/** + * @} + */ + +/** @defgroup TIM_Channel TIM Channel + * @{ + */ +#define TIM_CHANNEL_1 ((uint32_t)0x0000) +#define TIM_CHANNEL_2 ((uint32_t)0x0004) +#define TIM_CHANNEL_3 ((uint32_t)0x0008) +#define TIM_CHANNEL_4 ((uint32_t)0x000C) +#define TIM_CHANNEL_ALL ((uint32_t)0x0018) + +#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_ALL)) + +#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2)) + +#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2)) + +#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity + * @{ + */ + +#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING +#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING +#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE + +#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \ + ((POLARITY) == TIM_ICPOLARITY_FALLING) || \ + ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection + * @{ + */ + +#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC2, IC1, IC4 or IC3, respectively */ +#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ + +#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \ + ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \ + ((SELECTION) == TIM_ICSELECTION_TRC)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler + * @{ + */ + +#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */ +#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */ +#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */ +#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */ + +#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ + ((PRESCALER) == TIM_ICPSC_DIV2) || \ + ((PRESCALER) == TIM_ICPSC_DIV4) || \ + ((PRESCALER) == TIM_ICPSC_DIV8)) +/** + * @} + */ + +/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode + * @{ + */ + +#define TIM_OPMODE_SINGLE (TIM_CR1_OPM) +#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000) + +#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \ + ((MODE) == TIM_OPMODE_REPETITIVE)) +/** + * @} + */ +/** @defgroup TIM_Encoder_Mode TIM Encoder Mode + * @{ + */ +#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0) +#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1) +#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) + +#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \ + ((MODE) == TIM_ENCODERMODE_TI2) || \ + ((MODE) == TIM_ENCODERMODE_TI12)) +/** + * @} + */ +/** @defgroup TIM_Interrupt_definition TIM interrupt Definition + * @{ + */ +#define TIM_IT_UPDATE (TIM_DIER_UIE) +#define TIM_IT_CC1 (TIM_DIER_CC1IE) +#define TIM_IT_CC2 (TIM_DIER_CC2IE) +#define TIM_IT_CC3 (TIM_DIER_CC3IE) +#define TIM_IT_CC4 (TIM_DIER_CC4IE) +#define TIM_IT_COM (TIM_DIER_COMIE) +#define TIM_IT_TRIGGER (TIM_DIER_TIE) +#define TIM_IT_BREAK (TIM_DIER_BIE) +/** + * @} + */ + +/** @defgroup TIM_COMMUTATION TIM Commutation + * @{ + */ +#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS) +#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000) + +/** + * @} + */ +/** @defgroup TIM_DMA_sources TIM DMA Sources + * @{ + */ + +#define TIM_DMA_UPDATE (TIM_DIER_UDE) +#define TIM_DMA_CC1 (TIM_DIER_CC1DE) +#define TIM_DMA_CC2 (TIM_DIER_CC2DE) +#define TIM_DMA_CC3 (TIM_DIER_CC3DE) +#define TIM_DMA_CC4 (TIM_DIER_CC4DE) +#define TIM_DMA_COM (TIM_DIER_COMDE) +#define TIM_DMA_TRIGGER (TIM_DIER_TDE) + +#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000)) +/** + * @} + */ + +/** @defgroup TIM_Event_Source TIM Event Source + * @{ + */ +#define TIM_EventSource_Update TIM_EGR_UG +#define TIM_EventSource_CC1 TIM_EGR_CC1G +#define TIM_EventSource_CC2 TIM_EGR_CC2G +#define TIM_EventSource_CC3 TIM_EGR_CC3G +#define TIM_EventSource_CC4 TIM_EGR_CC4G +#define TIM_EventSource_COM TIM_EGR_COMG +#define TIM_EventSource_Trigger TIM_EGR_TG +#define TIM_EventSource_Break TIM_EGR_BG + +#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000)) +/** + * @} + */ + +/** @defgroup TIM_Flag_definition TIM Flag Definition + * @{ + */ + +#define TIM_FLAG_UPDATE (TIM_SR_UIF) +#define TIM_FLAG_CC1 (TIM_SR_CC1IF) +#define TIM_FLAG_CC2 (TIM_SR_CC2IF) +#define TIM_FLAG_CC3 (TIM_SR_CC3IF) +#define TIM_FLAG_CC4 (TIM_SR_CC4IF) +#define TIM_FLAG_COM (TIM_SR_COMIF) +#define TIM_FLAG_TRIGGER (TIM_SR_TIF) +#define TIM_FLAG_BREAK (TIM_SR_BIF) +#define TIM_FLAG_CC1OF (TIM_SR_CC1OF) +#define TIM_FLAG_CC2OF (TIM_SR_CC2OF) +#define TIM_FLAG_CC3OF (TIM_SR_CC3OF) +#define TIM_FLAG_CC4OF (TIM_SR_CC4OF) + +#define IS_TIM_FLAG(FLAG) (((FLAG) == TIM_FLAG_UPDATE) || \ + ((FLAG) == TIM_FLAG_CC1) || \ + ((FLAG) == TIM_FLAG_CC2) || \ + ((FLAG) == TIM_FLAG_CC3) || \ + ((FLAG) == TIM_FLAG_CC4) || \ + ((FLAG) == TIM_FLAG_COM) || \ + ((FLAG) == TIM_FLAG_TRIGGER) || \ + ((FLAG) == TIM_FLAG_BREAK) || \ + ((FLAG) == TIM_FLAG_CC1OF) || \ + ((FLAG) == TIM_FLAG_CC2OF) || \ + ((FLAG) == TIM_FLAG_CC3OF) || \ + ((FLAG) == TIM_FLAG_CC4OF)) +/** + * @} + */ + +/** @defgroup TIM_Clock_Source TIM Clock Source + * @{ + */ +#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) +#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0) +#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000) +#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0) +#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1) +#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) +#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2) +#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) +#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) +#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS) + +#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \ + ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \ + ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \ + ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \ + ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \ + ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \ + ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \ + ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1)) +/** + * @} + */ + +/** @defgroup TIM_Clock_Polarity TIM Clock Polarity + * @{ + */ +#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ + +#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \ + ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \ + ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \ + ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \ + ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE)) +/** + * @} + */ +/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler + * @{ + */ +#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ +#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ +#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ + +#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \ + ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \ + ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \ + ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8)) +/** + * @} + */ +/** @defgroup TIM_Clock_Filter TIM Clock Filter + * @{ + */ + +#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF) +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Source TIM ClearInput Source + * @{ + */ +#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001) +#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000) + +#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \ + ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR)) +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity + * @{ + */ +#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ +#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ + + +#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ + ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler + * @{ + */ +#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ + +#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \ + ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \ + ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \ + ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8)) +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Filter TIM Clear Input Filter + * @{ + */ + +#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF) +/** + * @} + */ + +/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM Off-state Selection for Run Mode + * @{ + */ +#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR) +#define TIM_OSSR_DISABLE ((uint32_t)0x0000) + +#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \ + ((STATE) == TIM_OSSR_DISABLE)) +/** + * @} + */ + +/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM Off-state Selection for Idle Mode + * @{ + */ +#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI) +#define TIM_OSSI_DISABLE ((uint32_t)0x0000) + +#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \ + ((STATE) == TIM_OSSI_DISABLE)) +/** + * @} + */ +/** @defgroup TIM_Lock_level TIM Lock Configuration + * @{ + */ +#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000) +#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0) +#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1) +#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK) + +#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \ + ((LEVEL) == TIM_LOCKLEVEL_1) || \ + ((LEVEL) == TIM_LOCKLEVEL_2) || \ + ((LEVEL) == TIM_LOCKLEVEL_3)) +/** + * @} + */ +/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable + * @{ + */ +#define TIM_BREAK_ENABLE (TIM_BDTR_BKE) +#define TIM_BREAK_DISABLE ((uint32_t)0x0000) + +#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \ + ((STATE) == TIM_BREAK_DISABLE)) +/** + * @} + */ +/** @defgroup TIM_Break_Polarity TIM Break Input Polarity + * @{ + */ +#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000) +#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP) + +#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \ + ((POLARITY) == TIM_BREAKPOLARITY_HIGH)) +/** + * @} + */ +/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable + * @{ + */ +#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE) +#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000) + +#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \ + ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE)) +/** + * @} + */ + +/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection + * @{ + */ +#define TIM_TRGO_RESET ((uint32_t)0x0000) +#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) +#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) +#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) +#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2) +#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) +#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) +#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) + +#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \ + ((SOURCE) == TIM_TRGO_ENABLE) || \ + ((SOURCE) == TIM_TRGO_UPDATE) || \ + ((SOURCE) == TIM_TRGO_OC1) || \ + ((SOURCE) == TIM_TRGO_OC1REF) || \ + ((SOURCE) == TIM_TRGO_OC2REF) || \ + ((SOURCE) == TIM_TRGO_OC3REF) || \ + ((SOURCE) == TIM_TRGO_OC4REF)) + + +/** + * @} + */ + +/** @defgroup TIM_Slave_Mode TIM Slave Mode + * @{ + */ + +#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000) +#define TIM_SLAVEMODE_RESET ((uint32_t)0x0004) +#define TIM_SLAVEMODE_GATED ((uint32_t)0x0005) +#define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006) +#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007) + +#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \ + ((MODE) == TIM_SLAVEMODE_GATED) || \ + ((MODE) == TIM_SLAVEMODE_RESET) || \ + ((MODE) == TIM_SLAVEMODE_TRIGGER) || \ + ((MODE) == TIM_SLAVEMODE_EXTERNAL1)) +/** + * @} + */ + +/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode + * @{ + */ + +#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080) +#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000) + +#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \ + ((STATE) == TIM_MASTERSLAVEMODE_DISABLE)) +/** + * @} + */ +/** @defgroup TIM_Trigger_Selection TIM Trigger Selection + * @{ + */ + +#define TIM_TS_ITR0 ((uint32_t)0x0000) +#define TIM_TS_ITR1 ((uint32_t)0x0010) +#define TIM_TS_ITR2 ((uint32_t)0x0020) +#define TIM_TS_ITR3 ((uint32_t)0x0030) +#define TIM_TS_TI1F_ED ((uint32_t)0x0040) +#define TIM_TS_TI1FP1 ((uint32_t)0x0050) +#define TIM_TS_TI2FP2 ((uint32_t)0x0060) +#define TIM_TS_ETRF ((uint32_t)0x0070) +#define TIM_TS_NONE ((uint32_t)0xFFFF) + +#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3) || \ + ((SELECTION) == TIM_TS_TI1F_ED) || \ + ((SELECTION) == TIM_TS_TI1FP1) || \ + ((SELECTION) == TIM_TS_TI2FP2) || \ + ((SELECTION) == TIM_TS_ETRF)) + +#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3)) + +#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3) || \ + ((SELECTION) == TIM_TS_NONE)) +/** + * @} + */ + +/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity + * @{ + */ +#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ + +#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \ + ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ + ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \ + ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \ + ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE )) +/** + * @} + */ + +/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler + * @{ + */ +#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ +#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ +#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ + +#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \ + ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \ + ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \ + ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8)) +/** + * @} + */ + +/** @defgroup TIM_Trigger_Filter TIM Trigger Filter + * @{ + */ + +#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF) +/** + * @} + */ + +/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection + * @{ + */ + +#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000) +#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S) + +#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \ + ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION)) + +/** + * @} + */ + +/** @defgroup TIM_DMA_Base_address TIM DMA Base address + * @{ + */ +#define TIM_DMABase_CR1 (0x00000000) +#define TIM_DMABase_CR2 (0x00000001) +#define TIM_DMABase_SMCR (0x00000002) +#define TIM_DMABase_DIER (0x00000003) +#define TIM_DMABase_SR (0x00000004) +#define TIM_DMABase_EGR (0x00000005) +#define TIM_DMABase_CCMR1 (0x00000006) +#define TIM_DMABase_CCMR2 (0x00000007) +#define TIM_DMABase_CCER (0x00000008) +#define TIM_DMABase_CNT (0x00000009) +#define TIM_DMABase_PSC (0x0000000A) +#define TIM_DMABase_ARR (0x0000000B) +#define TIM_DMABase_RCR (0x0000000C) +#define TIM_DMABase_CCR1 (0x0000000D) +#define TIM_DMABase_CCR2 (0x0000000E) +#define TIM_DMABase_CCR3 (0x0000000F) +#define TIM_DMABase_CCR4 (0x00000010) +#define TIM_DMABase_BDTR (0x00000011) +#define TIM_DMABase_DCR (0x00000012) +#define TIM_DMABase_OR (0x00000013) + +#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ + ((BASE) == TIM_DMABase_CR2) || \ + ((BASE) == TIM_DMABase_SMCR) || \ + ((BASE) == TIM_DMABase_DIER) || \ + ((BASE) == TIM_DMABase_SR) || \ + ((BASE) == TIM_DMABase_EGR) || \ + ((BASE) == TIM_DMABase_CCMR1) || \ + ((BASE) == TIM_DMABase_CCMR2) || \ + ((BASE) == TIM_DMABase_CCER) || \ + ((BASE) == TIM_DMABase_CNT) || \ + ((BASE) == TIM_DMABase_PSC) || \ + ((BASE) == TIM_DMABase_ARR) || \ + ((BASE) == TIM_DMABase_RCR) || \ + ((BASE) == TIM_DMABase_CCR1) || \ + ((BASE) == TIM_DMABase_CCR2) || \ + ((BASE) == TIM_DMABase_CCR3) || \ + ((BASE) == TIM_DMABase_CCR4) || \ + ((BASE) == TIM_DMABase_BDTR) || \ + ((BASE) == TIM_DMABase_DCR) || \ + ((BASE) == TIM_DMABase_OR)) +/** + * @} + */ + +/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length + * @{ + */ + +#define TIM_DMABurstLength_1Transfer (0x00000000) +#define TIM_DMABurstLength_2Transfers (0x00000100) +#define TIM_DMABurstLength_3Transfers (0x00000200) +#define TIM_DMABurstLength_4Transfers (0x00000300) +#define TIM_DMABurstLength_5Transfers (0x00000400) +#define TIM_DMABurstLength_6Transfers (0x00000500) +#define TIM_DMABurstLength_7Transfers (0x00000600) +#define TIM_DMABurstLength_8Transfers (0x00000700) +#define TIM_DMABurstLength_9Transfers (0x00000800) +#define TIM_DMABurstLength_10Transfers (0x00000900) +#define TIM_DMABurstLength_11Transfers (0x00000A00) +#define TIM_DMABurstLength_12Transfers (0x00000B00) +#define TIM_DMABurstLength_13Transfers (0x00000C00) +#define TIM_DMABurstLength_14Transfers (0x00000D00) +#define TIM_DMABurstLength_15Transfers (0x00000E00) +#define TIM_DMABurstLength_16Transfers (0x00000F00) +#define TIM_DMABurstLength_17Transfers (0x00001000) +#define TIM_DMABurstLength_18Transfers (0x00001100) + +#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \ + ((LENGTH) == TIM_DMABurstLength_2Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_3Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_4Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_5Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_6Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_7Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_8Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_9Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_10Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_11Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_12Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_13Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_14Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_15Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_16Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_17Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_18Transfers)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Filer_Value TIM Input Capture Value + * @{ + */ + +#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) +/** + * @} + */ + +/** @defgroup DMA_Handle_index TIM DMA Handle Index + * @{ + */ +#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */ +#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ +#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ +#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ +#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ +#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /*!< Index of the DMA handle used for Commutation DMA requests */ +#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */ +/** + * @} + */ + +/** @defgroup Channel_CC_State TIM Capture/Compare Channel State + * @{ + */ +#define TIM_CCx_ENABLE ((uint32_t)0x0001) +#define TIM_CCx_DISABLE ((uint32_t)0x0000) +#define TIM_CCxN_ENABLE ((uint32_t)0x0004) +#define TIM_CCxN_DISABLE ((uint32_t)0x0000) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup TIM_Exported_Macros TIM Exported Macros + * @{ + */ + +/** @brief Reset TIM handle state + * @param __HANDLE__: TIM handle. + * @retval None + */ +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) + +/** + * @brief Enable the TIM peripheral. + * @param __HANDLE__: TIM handle + * @retval None + */ +#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) + +/** + * @brief Enable the TIM main Output. + * @param __HANDLE__: TIM handle + * @retval None + */ +#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) + +/** + * @brief Disable the TIM peripheral. + * @param __HANDLE__: TIM handle + * @retval None + */ +#define __HAL_TIM_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \ + { \ + if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \ + { \ + (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ + } \ + } \ + } while(0) +/* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN + channels have been disabled */ +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__: TIM handle + * @retval None + */ +#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \ + { \ + if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \ + { \ + (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ + } \ + } \ + } while(0) + +#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) +#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) +#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) +#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) +#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) +#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) + +#define __HAL_TIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) + +#define __HAL_TIM_DIRECTION_STATUS(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR)) +#define __HAL_TIM_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) + +#define __HAL_TIM_SetICPrescalerValue(__HANDLE__, __CHANNEL__, __ICPSC__) \ +(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ + ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8))) + +#define __HAL_TIM_ResetICPrescalerValue(__HANDLE__, __CHANNEL__) \ +(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) + +/** + * @brief Sets the TIM Capture Compare Register value on runtime without + * calling another time ConfigChannel function. + * @param __HANDLE__: TIM handle. + * @param __CHANNEL__ : TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __COMPARE__: specifies the Capture Compare register new value. + * @retval None + */ +#define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \ +(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__)) + +/** + * @brief Gets the TIM Capture Compare Register value on runtime + * @param __HANDLE__: TIM handle. + * @param __CHANNEL__ : TIM Channel associated with the capture compare register + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get capture/compare 1 register value + * @arg TIM_CHANNEL_2: get capture/compare 2 register value + * @arg TIM_CHANNEL_3: get capture/compare 3 register value + * @arg TIM_CHANNEL_4: get capture/compare 4 register value + * @retval None + */ +#define __HAL_TIM_GetCompare(__HANDLE__, __CHANNEL__) \ + (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2))) + +/** + * @brief Sets the TIM Counter Register value on runtime. + * @param __HANDLE__: TIM handle. + * @param __COUNTER__: specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SetCounter(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) + +/** + * @brief Gets the TIM Counter Register value on runtime. + * @param __HANDLE__: TIM handle. + * @retval None + */ +#define __HAL_TIM_GetCounter(__HANDLE__) \ + ((__HANDLE__)->Instance->CNT) + +/** + * @brief Sets the TIM Autoreload Register value on runtime without calling + * another time any Init function. + * @param __HANDLE__: TIM handle. + * @param __AUTORELOAD__: specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SetAutoreload(__HANDLE__, __AUTORELOAD__) \ + do{ \ + (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ + (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ + } while(0) + +/** + * @brief Gets the TIM Autoreload Register value on runtime + * @param __HANDLE__: TIM handle. + * @retval None + */ +#define __HAL_TIM_GetAutoreload(__HANDLE__) \ + ((__HANDLE__)->Instance->ARR) + +/** + * @brief Sets the TIM Clock Division value on runtime without calling + * another time any Init function. + * @param __HANDLE__: TIM handle. + * @param __CKD__: specifies the clock division value. + * This parameter can be one of the following value: + * @arg TIM_CLOCKDIVISION_DIV1 + * @arg TIM_CLOCKDIVISION_DIV2 + * @arg TIM_CLOCKDIVISION_DIV4 + * @retval None + */ +#define __HAL_TIM_SetClockDivision(__HANDLE__, __CKD__) \ + do{ \ + (__HANDLE__)->Instance->CR1 &= ~TIM_CR1_CKD; \ + (__HANDLE__)->Instance->CR1 |= (__CKD__); \ + (__HANDLE__)->Init.ClockDivision = (__CKD__); \ + } while(0) + +/** + * @brief Gets the TIM Clock Division value on runtime + * @param __HANDLE__: TIM handle. + * @retval None + */ +#define __HAL_TIM_GetClockDivision(__HANDLE__) \ + ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) + +/** + * @brief Sets the TIM Input Capture prescaler on runtime without calling + * another time HAL_TIM_IC_ConfigChannel() function. + * @param __HANDLE__: TIM handle. + * @param __CHANNEL__ : TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __ICPSC__: specifies the Input Capture4 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +#define __HAL_TIM_SetICPrescaler(__HANDLE__, __CHANNEL__, __ICPSC__) \ + do{ \ + __HAL_TIM_ResetICPrescalerValue((__HANDLE__), (__CHANNEL__)); \ + __HAL_TIM_SetICPrescalerValue((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ + } while(0) + +/** + * @brief Gets the TIM Input Capture prescaler on runtime + * @param __HANDLE__: TIM handle. + * @param __CHANNEL__: TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get input capture 1 prescaler value + * @arg TIM_CHANNEL_2: get input capture 2 prescaler value + * @arg TIM_CHANNEL_3: get input capture 3 prescaler value + * @arg TIM_CHANNEL_4: get input capture 4 prescaler value + * @retval None + */ +#define __HAL_TIM_GetICPrescaler(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ + (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8) + +/** + * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register + * @param __HANDLE__: TIM handle. + * @note When the USR bit of the TIMx_CR1 register is set, only counter + * overflow/underflow generates an update interrupt or DMA request (if + * enabled) + * @retval None + */ +#define __HAL_TIM_URS_ENABLE(__HANDLE__) \ + ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS)) + +/** + * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register + * @param __HANDLE__: TIM handle. + * @note When the USR bit of the TIMx_CR1 register is reset, any of the + * following events generate an update interrupt or DMA request (if + * enabled): + * (+) Counter overflow/underflow + * (+) Setting the UG bit + * (+) Update generation through the slave mode controller + * @retval None + */ +#define __HAL_TIM_URS_DISABLE(__HANDLE__) \ + ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS)) + +/** + * @} + */ + +/* Include TIM HAL Extension module */ +#include "stm32f0xx_hal_tim_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIM_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @addtogroup TIM_Exported_Functions_Group1 Time Base functions + * @brief Time Base functions + * @{ + */ +/* Time Base functions ********************************************************/ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group2 Time Output Compare functions + * @brief Time Output Compare functions + * @{ + */ +/* Timer Output Compare functions **********************************************/ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group3 Time PWM functions + * @brief Time PWM functions + * @{ + */ +/* Timer PWM functions *********************************************************/ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group4 Time Input Capture functions + * @brief Time Input Capture functions + * @{ + */ +/* Timer Input Capture functions ***********************************************/ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group5 Time One Pulse functions + * @brief Time One Pulse functions + * @{ + */ +/* Timer One Pulse functions ***************************************************/ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group6 Time Encoder functions + * @brief Time Encoder functions + * @{ + */ +/* Timer Encoder functions *****************************************************/ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig); +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); + /* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief IRQ handler management + * @{ + */ +/* Interrupt Handler functions **********************************************/ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group8 Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Control functions *********************************************************/ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel); +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig); +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ + uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ + uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); +uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group9 + * @brief TIM Callbacks functions + * @{ + */ +/* Callback in non blocking modes (Interrupt and DMA) *************************/ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group10 + * @brief Peripheral State functions + * @{ + */ +/* Peripheral State functions **************************************************/ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** + * @} + */ + +/* Private Macros -----------------------------------------------------------*/ +/** @defgroup TIM_Private_Macros TIM Private Macros + * @{ + */ +/* The counter of a timer instance is disabled only if all the CCx and CCxN + channels have been disabled */ +#define CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) +#define CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) +/** + * @} + */ + +/* Private Functions --------------------------------------------------------*/ +/** @addtogroup TIM_Private_Functions + * @{ + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); +void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma); +void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); +void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_TIM_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim_ex.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim_ex.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim_ex.h @@ -0,0 +1,293 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_tim_ex.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Header file of TIM HAL Extended module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_TIM_EX_H +#define __STM32F0xx_HAL_TIM_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup TIMEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Types TIMEx Extended Exported Types + * @{ + */ + +/** + * @brief TIM Hall sensor Configuration Structure definition + */ + +typedef struct +{ + + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ +} TIM_HallSensor_InitTypeDef; + +/** + * @brief TIM Master configuration Structure definition + */ +typedef struct { + uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection + This parameter can be a value of @ref TIM_Master_Mode_Selection */ + uint32_t MasterSlaveMode; /*!< Master/slave mode selection + This parameter can be a value of @ref TIM_Master_Slave_Mode */ +}TIM_MasterConfigTypeDef; + +/** + * @brief TIM Break and Dead time configuration Structure definition + */ +typedef struct +{ + uint32_t OffStateRunMode; /*!< TIM off state in run mode + This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ + uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode + This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ + uint32_t LockLevel; /*!< TIM Lock level + This parameter can be a value of @ref TIM_Lock_level */ + uint32_t DeadTime; /*!< TIM dead Time + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + uint32_t BreakState; /*!< TIM Break State + This parameter can be a value of @ref TIM_Break_Input_enable_disable */ + uint32_t BreakPolarity; /*!< TIM Break input polarity + This parameter can be a value of @ref TIM_Break_Polarity */ + uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ +} TIM_BreakDeadTimeConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants + * @{ + */ + +/** @defgroup TIMEx_Remap TIMEx Remap + * @{ + */ + +#define TIM_TIM14_GPIO (0x00000000) /*!< TIM14 TI1 is connected to GPIO */ +#define TIM_TIM14_RTC (0x00000001) /*!< TIM14 TI1 is connected to RTC_clock */ +#define TIM_TIM14_HSE (0x00000002) /*!< TIM14 TI1 is connected to HSE/32 */ +#define TIM_TIM14_MCO (0x00000003) /*!< TIM14 TI1 is connected to MCO */ + +#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM_TIM14_GPIO) ||\ + ((TIM_REMAP) == TIM_TIM14_RTC) ||\ + ((TIM_REMAP) == TIM_TIM14_HSE) ||\ + ((TIM_REMAP) == TIM_TIM14_MCO)) +/** + * @} + */ + +/** @defgroup TIM_Clock_Filter TIM Clock Filter + * @{ + */ +#define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFF) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIMEx_Exported_Functions + * @{ + */ + +/** @addtogroup TIMEx_Exported_Functions_Group1 Timer Hall Sensor functions + * @brief Timer Hall Sensor functions + * @{ + */ +/* Timer Hall Sensor functions **********************************************/ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); + +void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); + + /* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group2 Timer Complementary Output Compare functions + * @brief Timer Complementary Output Compare functions + * @{ + */ +/* Timer Complementary Output Compare functions *****************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group3 Timer Complementary PWM functions + * @brief Timer Complementary PWM functions + * @{ + */ +/* Timer Complementary PWM functions ****************************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group4 Timer Complementary One Pulse functions + * @brief Timer Complementary One Pulse functions + * @{ + */ +/* Timer Complementary One Pulse functions **********************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group5 Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Extended Control functions ************************************************/ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig); +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group6 Extension Callbacks functions + * @brief Extended Callbacks functions + * @{ + */ +/* Extension Callback *********************************************************/ +void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group7 Extension Peripheral State functions + * @brief Extended Peripheral State functions + * @{ + */ +/* Extension Peripheral State functions **************************************/ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F0xx_HAL_TIM_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tsc.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tsc.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tsc.h @@ -0,0 +1,724 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_tsc.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief This file contains all the functions prototypes for the TSC firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_TSC_H +#define __STM32F0xx_TSC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(STM32F051x8) || defined(STM32F071xB) || defined(STM32F091xC) || \ + defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || \ + defined(STM32F058xx) || defined(STM32F078xx) || defined(STM32F098xx) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup TSC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup TSC_Exported_Types TSC Exported Types + * @{ + */ +/** + * @brief TSC state structure definition + */ +typedef enum +{ + HAL_TSC_STATE_RESET = 0x00, /*!< TSC registers have their reset value */ + HAL_TSC_STATE_READY = 0x01, /*!< TSC registers are initialized or acquisition is completed with success */ + HAL_TSC_STATE_BUSY = 0x02, /*!< TSC initialization or acquisition is on-going */ + HAL_TSC_STATE_ERROR = 0x03 /*!< Acquisition is completed with max count error */ +} HAL_TSC_StateTypeDef; + +/** + * @brief TSC group status structure definition + */ +typedef enum +{ + TSC_GROUP_ONGOING = 0x00, /*!< Acquisition on group is on-going or not started */ + TSC_GROUP_COMPLETED = 0x01 /*!< Acquisition on group is completed with success (no max count error) */ +} TSC_GroupStatusTypeDef; + +/** + * @brief TSC init structure definition + */ +typedef struct +{ + uint32_t CTPulseHighLength; /*!< Charge-transfer high pulse length */ + uint32_t CTPulseLowLength; /*!< Charge-transfer low pulse length */ + uint32_t SpreadSpectrum; /*!< Spread spectrum activation */ + uint32_t SpreadSpectrumDeviation; /*!< Spread spectrum deviation */ + uint32_t SpreadSpectrumPrescaler; /*!< Spread spectrum prescaler */ + uint32_t PulseGeneratorPrescaler; /*!< Pulse generator prescaler */ + uint32_t MaxCountValue; /*!< Max count value */ + uint32_t IODefaultMode; /*!< IO default mode */ + uint32_t SynchroPinPolarity; /*!< Synchro pin polarity */ + uint32_t AcquisitionMode; /*!< Acquisition mode */ + uint32_t MaxCountInterrupt; /*!< Max count interrupt activation */ + uint32_t ChannelIOs; /*!< Channel IOs mask */ + uint32_t ShieldIOs; /*!< Shield IOs mask */ + uint32_t SamplingIOs; /*!< Sampling IOs mask */ +} TSC_InitTypeDef; + +/** + * @brief TSC IOs configuration structure definition + */ +typedef struct +{ + uint32_t ChannelIOs; /*!< Channel IOs mask */ + uint32_t ShieldIOs; /*!< Shield IOs mask */ + uint32_t SamplingIOs; /*!< Sampling IOs mask */ +} TSC_IOConfigTypeDef; + +/** + * @brief TSC handle Structure definition + */ +typedef struct +{ + TSC_TypeDef *Instance; /*!< Register base address */ + TSC_InitTypeDef Init; /*!< Initialization parameters */ + __IO HAL_TSC_StateTypeDef State; /*!< Peripheral state */ + HAL_LockTypeDef Lock; /*!< Lock feature */ +} TSC_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup TSC_Exported_Constants TSC Exported Constants + * @{ + */ + +/** @defgroup TSC_CTPH_Cycles TSC Charge Transfer Pulse High + * @{ + */ +#define TSC_CTPH_1CYCLE ((uint32_t)((uint32_t) 0 << 28)) +#define TSC_CTPH_2CYCLES ((uint32_t)((uint32_t) 1 << 28)) +#define TSC_CTPH_3CYCLES ((uint32_t)((uint32_t) 2 << 28)) +#define TSC_CTPH_4CYCLES ((uint32_t)((uint32_t) 3 << 28)) +#define TSC_CTPH_5CYCLES ((uint32_t)((uint32_t) 4 << 28)) +#define TSC_CTPH_6CYCLES ((uint32_t)((uint32_t) 5 << 28)) +#define TSC_CTPH_7CYCLES ((uint32_t)((uint32_t) 6 << 28)) +#define TSC_CTPH_8CYCLES ((uint32_t)((uint32_t) 7 << 28)) +#define TSC_CTPH_9CYCLES ((uint32_t)((uint32_t) 8 << 28)) +#define TSC_CTPH_10CYCLES ((uint32_t)((uint32_t) 9 << 28)) +#define TSC_CTPH_11CYCLES ((uint32_t)((uint32_t)10 << 28)) +#define TSC_CTPH_12CYCLES ((uint32_t)((uint32_t)11 << 28)) +#define TSC_CTPH_13CYCLES ((uint32_t)((uint32_t)12 << 28)) +#define TSC_CTPH_14CYCLES ((uint32_t)((uint32_t)13 << 28)) +#define TSC_CTPH_15CYCLES ((uint32_t)((uint32_t)14 << 28)) +#define TSC_CTPH_16CYCLES ((uint32_t)((uint32_t)15 << 28)) +#define IS_TSC_CTPH(VAL) (((VAL) == TSC_CTPH_1CYCLE) || \ + ((VAL) == TSC_CTPH_2CYCLES) || \ + ((VAL) == TSC_CTPH_3CYCLES) || \ + ((VAL) == TSC_CTPH_4CYCLES) || \ + ((VAL) == TSC_CTPH_5CYCLES) || \ + ((VAL) == TSC_CTPH_6CYCLES) || \ + ((VAL) == TSC_CTPH_7CYCLES) || \ + ((VAL) == TSC_CTPH_8CYCLES) || \ + ((VAL) == TSC_CTPH_9CYCLES) || \ + ((VAL) == TSC_CTPH_10CYCLES) || \ + ((VAL) == TSC_CTPH_11CYCLES) || \ + ((VAL) == TSC_CTPH_12CYCLES) || \ + ((VAL) == TSC_CTPH_13CYCLES) || \ + ((VAL) == TSC_CTPH_14CYCLES) || \ + ((VAL) == TSC_CTPH_15CYCLES) || \ + ((VAL) == TSC_CTPH_16CYCLES)) +/** + * @} + */ + +/** @defgroup TSC_CTPL_Cycles TSC Charge Transfer Pulse Low + * @{ + */ +#define TSC_CTPL_1CYCLE ((uint32_t)((uint32_t) 0 << 24)) +#define TSC_CTPL_2CYCLES ((uint32_t)((uint32_t) 1 << 24)) +#define TSC_CTPL_3CYCLES ((uint32_t)((uint32_t) 2 << 24)) +#define TSC_CTPL_4CYCLES ((uint32_t)((uint32_t) 3 << 24)) +#define TSC_CTPL_5CYCLES ((uint32_t)((uint32_t) 4 << 24)) +#define TSC_CTPL_6CYCLES ((uint32_t)((uint32_t) 5 << 24)) +#define TSC_CTPL_7CYCLES ((uint32_t)((uint32_t) 6 << 24)) +#define TSC_CTPL_8CYCLES ((uint32_t)((uint32_t) 7 << 24)) +#define TSC_CTPL_9CYCLES ((uint32_t)((uint32_t) 8 << 24)) +#define TSC_CTPL_10CYCLES ((uint32_t)((uint32_t) 9 << 24)) +#define TSC_CTPL_11CYCLES ((uint32_t)((uint32_t)10 << 24)) +#define TSC_CTPL_12CYCLES ((uint32_t)((uint32_t)11 << 24)) +#define TSC_CTPL_13CYCLES ((uint32_t)((uint32_t)12 << 24)) +#define TSC_CTPL_14CYCLES ((uint32_t)((uint32_t)13 << 24)) +#define TSC_CTPL_15CYCLES ((uint32_t)((uint32_t)14 << 24)) +#define TSC_CTPL_16CYCLES ((uint32_t)((uint32_t)15 << 24)) +#define IS_TSC_CTPL(VAL) (((VAL) == TSC_CTPL_1CYCLE) || \ + ((VAL) == TSC_CTPL_2CYCLES) || \ + ((VAL) == TSC_CTPL_3CYCLES) || \ + ((VAL) == TSC_CTPL_4CYCLES) || \ + ((VAL) == TSC_CTPL_5CYCLES) || \ + ((VAL) == TSC_CTPL_6CYCLES) || \ + ((VAL) == TSC_CTPL_7CYCLES) || \ + ((VAL) == TSC_CTPL_8CYCLES) || \ + ((VAL) == TSC_CTPL_9CYCLES) || \ + ((VAL) == TSC_CTPL_10CYCLES) || \ + ((VAL) == TSC_CTPL_11CYCLES) || \ + ((VAL) == TSC_CTPL_12CYCLES) || \ + ((VAL) == TSC_CTPL_13CYCLES) || \ + ((VAL) == TSC_CTPL_14CYCLES) || \ + ((VAL) == TSC_CTPL_15CYCLES) || \ + ((VAL) == TSC_CTPL_16CYCLES)) +/** + * @} + */ + +/** @defgroup TSC_SS_Prescaler_definition TSC Spread spectrum prescaler definition + * @{ + */ +#define TSC_SS_PRESC_DIV1 ((uint32_t)0) +#define TSC_SS_PRESC_DIV2 (TSC_CR_SSPSC) +#define IS_TSC_SS_PRESC(VAL) (((VAL) == TSC_SS_PRESC_DIV1) || ((VAL) == TSC_SS_PRESC_DIV2)) + +/** + * @} + */ + +/** @defgroup TSC_PG_Prescaler_definition TSC Pulse Generator prescaler definition + * @{ + */ +#define TSC_PG_PRESC_DIV1 ((uint32_t)(0 << 12)) +#define TSC_PG_PRESC_DIV2 ((uint32_t)(1 << 12)) +#define TSC_PG_PRESC_DIV4 ((uint32_t)(2 << 12)) +#define TSC_PG_PRESC_DIV8 ((uint32_t)(3 << 12)) +#define TSC_PG_PRESC_DIV16 ((uint32_t)(4 << 12)) +#define TSC_PG_PRESC_DIV32 ((uint32_t)(5 << 12)) +#define TSC_PG_PRESC_DIV64 ((uint32_t)(6 << 12)) +#define TSC_PG_PRESC_DIV128 ((uint32_t)(7 << 12)) +#define IS_TSC_PG_PRESC(VAL) (((VAL) == TSC_PG_PRESC_DIV1) || \ + ((VAL) == TSC_PG_PRESC_DIV2) || \ + ((VAL) == TSC_PG_PRESC_DIV4) || \ + ((VAL) == TSC_PG_PRESC_DIV8) || \ + ((VAL) == TSC_PG_PRESC_DIV16) || \ + ((VAL) == TSC_PG_PRESC_DIV32) || \ + ((VAL) == TSC_PG_PRESC_DIV64) || \ + ((VAL) == TSC_PG_PRESC_DIV128)) +/** + * @} + */ + +/** @defgroup TSC_MCV_definition TSC Max Count Value definition + * @{ + */ +#define TSC_MCV_255 ((uint32_t)(0 << 5)) +#define TSC_MCV_511 ((uint32_t)(1 << 5)) +#define TSC_MCV_1023 ((uint32_t)(2 << 5)) +#define TSC_MCV_2047 ((uint32_t)(3 << 5)) +#define TSC_MCV_4095 ((uint32_t)(4 << 5)) +#define TSC_MCV_8191 ((uint32_t)(5 << 5)) +#define TSC_MCV_16383 ((uint32_t)(6 << 5)) +#define IS_TSC_MCV(VAL) (((VAL) == TSC_MCV_255) || \ + ((VAL) == TSC_MCV_511) || \ + ((VAL) == TSC_MCV_1023) || \ + ((VAL) == TSC_MCV_2047) || \ + ((VAL) == TSC_MCV_4095) || \ + ((VAL) == TSC_MCV_8191) || \ + ((VAL) == TSC_MCV_16383)) +/** + * @} + */ + +/** @defgroup TSC_IO_default_mode_definition TSC I/O default mode definition + * @{ + */ +#define TSC_IODEF_OUT_PP_LOW ((uint32_t)0) +#define TSC_IODEF_IN_FLOAT (TSC_CR_IODEF) +#define IS_TSC_IODEF(VAL) (((VAL) == TSC_IODEF_OUT_PP_LOW) || ((VAL) == TSC_IODEF_IN_FLOAT)) +/** + * @} + */ + +/** @defgroup TSC_Synchronization_pin_polarity TSC Synchronization pin polarity + * @{ + */ +#define TSC_SYNC_POL_FALL ((uint32_t)0) +#define TSC_SYNC_POL_RISE_HIGH (TSC_CR_SYNCPOL) +#define IS_TSC_SYNC_POL(VAL) (((VAL) == TSC_SYNC_POL_FALL) || ((VAL) == TSC_SYNC_POL_RISE_HIGH)) +/** + * @} + */ + +/** @defgroup TSC_Acquisition_mode TSC Acquisition mode + * @{ + */ +#define TSC_ACQ_MODE_NORMAL ((uint32_t)0) +#define TSC_ACQ_MODE_SYNCHRO (TSC_CR_AM) +#define IS_TSC_ACQ_MODE(VAL) (((VAL) == TSC_ACQ_MODE_NORMAL) || ((VAL) == TSC_ACQ_MODE_SYNCHRO)) +/** + * @} + */ + +/** @defgroup TSC_IO_mode_definition TSC I/O mode definition + * @{ + */ +#define TSC_IOMODE_UNUSED ((uint32_t)0) +#define TSC_IOMODE_CHANNEL ((uint32_t)1) +#define TSC_IOMODE_SHIELD ((uint32_t)2) +#define TSC_IOMODE_SAMPLING ((uint32_t)3) +#define IS_TSC_IOMODE(VAL) (((VAL) == TSC_IOMODE_UNUSED) || \ + ((VAL) == TSC_IOMODE_CHANNEL) || \ + ((VAL) == TSC_IOMODE_SHIELD) || \ + ((VAL) == TSC_IOMODE_SAMPLING)) +/** + * @} + */ + +/** @defgroup TSC_interrupts_definition TSC interrupts definition + * @{ + */ +#define TSC_IT_EOA ((uint32_t)TSC_IER_EOAIE) +#define TSC_IT_MCE ((uint32_t)TSC_IER_MCEIE) +#define IS_TSC_MCE_IT(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE)) +/** + * @} + */ + +/** @defgroup TSC_flags_definition TSC Flags Definition + * @{ + */ +#define TSC_FLAG_EOA ((uint32_t)TSC_ISR_EOAF) +#define TSC_FLAG_MCE ((uint32_t)TSC_ISR_MCEF) +/** + * @} + */ + +/** @defgroup TSC_groups_definition TSC groups definition + * @{ + */ +#define TSC_NB_OF_GROUPS (8) + +#define TSC_GROUP1 ((uint32_t)0x00000001) +#define TSC_GROUP2 ((uint32_t)0x00000002) +#define TSC_GROUP3 ((uint32_t)0x00000004) +#define TSC_GROUP4 ((uint32_t)0x00000008) +#define TSC_GROUP5 ((uint32_t)0x00000010) +#define TSC_GROUP6 ((uint32_t)0x00000020) +#define TSC_GROUP7 ((uint32_t)0x00000040) +#define TSC_GROUP8 ((uint32_t)0x00000080) +#define TSC_ALL_GROUPS ((uint32_t)0x000000FF) + +#define TSC_GROUP1_IDX ((uint32_t)0) +#define TSC_GROUP2_IDX ((uint32_t)1) +#define TSC_GROUP3_IDX ((uint32_t)2) +#define TSC_GROUP4_IDX ((uint32_t)3) +#define TSC_GROUP5_IDX ((uint32_t)4) +#define TSC_GROUP6_IDX ((uint32_t)5) +#define TSC_GROUP7_IDX ((uint32_t)6) +#define TSC_GROUP8_IDX ((uint32_t)7) +#define IS_GROUP_INDEX(VAL) (((VAL) == 0) || (((VAL) > 0) && ((VAL) < TSC_NB_OF_GROUPS))) + +#define TSC_GROUP1_IO1 ((uint32_t)0x00000001) +#define TSC_GROUP1_IO2 ((uint32_t)0x00000002) +#define TSC_GROUP1_IO3 ((uint32_t)0x00000004) +#define TSC_GROUP1_IO4 ((uint32_t)0x00000008) +#define TSC_GROUP1_ALL_IOS ((uint32_t)0x0000000F) + +#define TSC_GROUP2_IO1 ((uint32_t)0x00000010) +#define TSC_GROUP2_IO2 ((uint32_t)0x00000020) +#define TSC_GROUP2_IO3 ((uint32_t)0x00000040) +#define TSC_GROUP2_IO4 ((uint32_t)0x00000080) +#define TSC_GROUP2_ALL_IOS ((uint32_t)0x000000F0) + +#define TSC_GROUP3_IO1 ((uint32_t)0x00000100) +#define TSC_GROUP3_IO2 ((uint32_t)0x00000200) +#define TSC_GROUP3_IO3 ((uint32_t)0x00000400) +#define TSC_GROUP3_IO4 ((uint32_t)0x00000800) +#define TSC_GROUP3_ALL_IOS ((uint32_t)0x00000F00) + +#define TSC_GROUP4_IO1 ((uint32_t)0x00001000) +#define TSC_GROUP4_IO2 ((uint32_t)0x00002000) +#define TSC_GROUP4_IO3 ((uint32_t)0x00004000) +#define TSC_GROUP4_IO4 ((uint32_t)0x00008000) +#define TSC_GROUP4_ALL_IOS ((uint32_t)0x0000F000) + +#define TSC_GROUP5_IO1 ((uint32_t)0x00010000) +#define TSC_GROUP5_IO2 ((uint32_t)0x00020000) +#define TSC_GROUP5_IO3 ((uint32_t)0x00040000) +#define TSC_GROUP5_IO4 ((uint32_t)0x00080000) +#define TSC_GROUP5_ALL_IOS ((uint32_t)0x000F0000) + +#define TSC_GROUP6_IO1 ((uint32_t)0x00100000) +#define TSC_GROUP6_IO2 ((uint32_t)0x00200000) +#define TSC_GROUP6_IO3 ((uint32_t)0x00400000) +#define TSC_GROUP6_IO4 ((uint32_t)0x00800000) +#define TSC_GROUP6_ALL_IOS ((uint32_t)0x00F00000) + +#define TSC_GROUP7_IO1 ((uint32_t)0x01000000) +#define TSC_GROUP7_IO2 ((uint32_t)0x02000000) +#define TSC_GROUP7_IO3 ((uint32_t)0x04000000) +#define TSC_GROUP7_IO4 ((uint32_t)0x08000000) +#define TSC_GROUP7_ALL_IOS ((uint32_t)0x0F000000) + +#define TSC_GROUP8_IO1 ((uint32_t)0x10000000) +#define TSC_GROUP8_IO2 ((uint32_t)0x20000000) +#define TSC_GROUP8_IO3 ((uint32_t)0x40000000) +#define TSC_GROUP8_IO4 ((uint32_t)0x80000000) +#define TSC_GROUP8_ALL_IOS ((uint32_t)0xF0000000) + +#define TSC_ALL_GROUPS_ALL_IOS ((uint32_t)0xFFFFFFFF) +/** + * @} + */ + +/** + * @} + */ + +/* Private macros -----------------------------------------------------------*/ +/** @defgroup TSC_Private_Macros TSC Private Macros + * @{ + */ +/** @defgroup TSC_Spread_Spectrum TSC Spread Spectrum + * @{ + */ +#define IS_TSC_SS(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE)) + +#define IS_TSC_SSD(VAL) (((VAL) == 0) || (((VAL) > 0) && ((VAL) < 128))) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup TSC_Exported_Macros TSC Exported Macros + * @{ + */ + +/** @brief Reset TSC handle state + * @param __HANDLE__: TSC handle. + * @retval None + */ +#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET) + +/** + * @brief Enable the TSC peripheral. + * @param __HANDLE__: TSC handle + * @retval None + */ +#define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE) + +/** + * @brief Disable the TSC peripheral. + * @param __HANDLE__: TSC handle + * @retval None + */ +#define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_TSCE)) + +/** + * @brief Start acquisition + * @param __HANDLE__: TSC handle + * @retval None + */ +#define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START) + +/** + * @brief Stop acquisition + * @param __HANDLE__: TSC handle + * @retval None + */ +#define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_START)) + +/** + * @brief Set IO default mode to output push-pull low + * @param __HANDLE__: TSC handle + * @retval None + */ +#define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_IODEF)) + +/** + * @brief Set IO default mode to input floating + * @param __HANDLE__: TSC handle + * @retval None + */ +#define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF) + +/** + * @brief Set synchronization polarity to falling edge + * @param __HANDLE__: TSC handle + * @retval None + */ +#define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_SYNCPOL)) + +/** + * @brief Set synchronization polarity to rising edge and high level + * @param __HANDLE__: TSC handle + * @retval None + */ +#define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL) + +/** + * @brief Enable TSC interrupt. + * @param __HANDLE__: TSC handle + * @param __INTERRUPT__: TSC interrupt + * @retval None + */ +#define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) + +/** + * @brief Disable TSC interrupt. + * @param __HANDLE__: TSC handle + * @param __INTERRUPT__: TSC interrupt + * @retval None + */ +#define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (uint32_t)(~(__INTERRUPT__))) + +/** @brief Check if the specified TSC interrupt source is enabled or disabled. + * @param __HANDLE__: TSC Handle + * @param __INTERRUPT__: TSC interrupt + * @retval SET or RESET + */ +#define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** + * @brief Get the selected TSC's flag status. + * @param __HANDLE__: TSC handle + * @param __FLAG__: TSC flag + * @retval SET or RESET + */ +#define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET) + +/** + * @brief Clear the TSC's pending flag. + * @param __HANDLE__: TSC handle + * @param __FLAG__: TSC flag + * @retval None + */ +#define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) + +/** + * @brief Enable schmitt trigger hysteresis on a group of IOs + * @param __HANDLE__: TSC handle + * @param __GX_IOY_MASK__: IOs mask + * @retval None + */ +#define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__)) + +/** + * @brief Disable schmitt trigger hysteresis on a group of IOs + * @param __HANDLE__: TSC handle + * @param __GX_IOY_MASK__: IOs mask + * @retval None + */ +#define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR &= (uint32_t)(~(__GX_IOY_MASK__))) + +/** + * @brief Open analog switch on a group of IOs + * @param __HANDLE__: TSC handle + * @param __GX_IOY_MASK__: IOs mask + * @retval None + */ +#define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR &= (uint32_t)(~(__GX_IOY_MASK__))) + +/** + * @brief Close analog switch on a group of IOs + * @param __HANDLE__: TSC handle + * @param __GX_IOY_MASK__: IOs mask + * @retval None + */ +#define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__)) + +/** + * @brief Enable a group of IOs in channel mode + * @param __HANDLE__: TSC handle + * @param __GX_IOY_MASK__: IOs mask + * @retval None + */ +#define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__)) + +/** + * @brief Disable a group of channel IOs + * @param __HANDLE__: TSC handle + * @param __GX_IOY_MASK__: IOs mask + * @retval None + */ +#define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR &= (uint32_t)(~(__GX_IOY_MASK__))) + +/** + * @brief Enable a group of IOs in sampling mode + * @param __HANDLE__: TSC handle + * @param __GX_IOY_MASK__: IOs mask + * @retval None + */ +#define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__)) + +/** + * @brief Disable a group of sampling IOs + * @param __HANDLE__: TSC handle + * @param __GX_IOY_MASK__: IOs mask + * @retval None + */ +#define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (uint32_t)(~(__GX_IOY_MASK__))) + +/** + * @brief Enable acquisition groups + * @param __HANDLE__: TSC handle + * @param __GX_MASK__: Groups mask + * @retval None + */ +#define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__)) + +/** + * @brief Disable acquisition groups + * @param __HANDLE__: TSC handle + * @param __GX_MASK__: Groups mask + * @retval None + */ +#define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (uint32_t)(~(__GX_MASK__))) + +/** @brief Gets acquisition group status + * @param __HANDLE__: TSC Handle + * @param __GX_INDEX__: Group index + * @retval SET or RESET + */ +#define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \ +((((__HANDLE__)->Instance->IOGCSR & (uint32_t)((uint32_t)1 << ((__GX_INDEX__) + (uint32_t)16))) == (uint32_t)((uint32_t)1 << ((__GX_INDEX__) + (uint32_t)16))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TSC_Exported_Functions TSC Exported Functions + * @{ + */ + +/** @addtogroup TSC_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc); +HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc); +void HAL_TSC_MspInit(TSC_HandleTypeDef* htsc); +void HAL_TSC_MspDeInit(TSC_HandleTypeDef* htsc); +/** + * @} + */ + +/** @addtogroup TSC_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions * @{ + */ +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef* htsc); +HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc); +HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef* htsc); +HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef* htsc); +TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef* htsc, uint32_t gx_index); +uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index); +/** + * @} + */ + +/** @addtogroup TSC_Exported_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfigTypeDef* config); +HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice); +/** + * @} + */ + +/** @addtogroup TSC_Exported_Functions_Group4 State functions + * @brief State functions + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef* htsc); +HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef* htsc); +void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc); +/** + * @} + */ + +/** @addtogroup TSC_Exported_Functions_Group5 Callback functions + * @brief Callback functions + * @{ + */ +/* Callback functions *********************************************************/ +void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef* htsc); +void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(STM32F051x8) || defined(STM32F071xB) || defined(STM32F091xC) || */ + /* defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || */ + /* defined(STM32F058xx) || defined(STM32F078xx) || defined(STM32F098xx) */ + + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F0xx_TSC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h @@ -0,0 +1,947 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_uart.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Header file of UART HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_UART_H +#define __STM32F0xx_HAL_UART_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup UART + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UART_Exported_Types UART Exported Types + * @{ + */ + + +/** + * @brief UART Init Structure definition + */ +typedef struct +{ + uint32_t BaudRate; /*!< This member configures the UART communication baud rate. + The baud rate register is computed using the following formula: + - If oversampling is 16 or in LIN mode (LIN mode not available on F030xx devices), + Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate))) + - If oversampling is 8, + Baud Rate Register[15:4] = ((2 * PCLKx) / ((huart->Init.BaudRate)))[15:4] + Baud Rate Register[3] = 0 + Baud Rate Register[2:0] = (((2 * PCLKx) / ((huart->Init.BaudRate)))[3:0]) >> 1 */ + + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref UARTEx_Word_Length */ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref UART_Stop_Bits */ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref UART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref UART_Mode */ + + uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref UART_Hardware_Flow_Control */ + + uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8). + This parameter can be a value of @ref UART_Over_Sampling */ + + uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. + Selecting the single sample method increases the receiver tolerance to clock + deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */ +}UART_InitTypeDef; + +/** + * @brief UART Advanced Features initalization structure definition + */ +typedef struct +{ + uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several + Advanced Features may be initialized at the same time . + This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type */ + + uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted. + This parameter can be a value of @ref UART_Tx_Inv */ + + uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted. + This parameter can be a value of @ref UART_Rx_Inv */ + + uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic + vs negative/inverted logic). + This parameter can be a value of @ref UART_Data_Inv */ + + uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped. + This parameter can be a value of @ref UART_Rx_Tx_Swap */ + + uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled. + This parameter can be a value of @ref UART_Overrun_Disable */ + + uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error. + This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error */ + + uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled. + This parameter can be a value of @ref UART_AutoBaudRate_Enable */ + + uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate + detection is carried out. + This parameter can be a value of @ref UARTEx_AutoBaud_Rate_Mode */ + + uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line. + This parameter can be a value of @ref UART_MSB_First */ +} UART_AdvFeatureInitTypeDef; + +/** + * @brief UART wake up from stop mode parameters + */ +typedef struct +{ + uint32_t WakeUpEvent; /*!< Specifies which event will activat the Wakeup from Stop mode flag (WUF). + This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection. + If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must + be filled up. */ + + uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long. + This parameter can be a value of @ref UART_WakeUp_Address_Length */ + + uint8_t Address; /*!< UART/USART node address (7-bit long max) */ +} UART_WakeUpTypeDef; + +/** + * @brief HAL UART State structures definition + */ +typedef enum +{ + HAL_UART_STATE_RESET = 0x00, /*!< Peripheral is not initialized */ + HAL_UART_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ + HAL_UART_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ + HAL_UART_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ + HAL_UART_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ + HAL_UART_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ + HAL_UART_STATE_TIMEOUT = 0x03, /*!< Timeout state */ + HAL_UART_STATE_ERROR = 0x04 /*!< Error */ +}HAL_UART_StateTypeDef; + +/** + * @brief HAL UART Error Code structure definition + */ +typedef enum +{ + HAL_UART_ERROR_NONE = 0x00, /*!< No error */ + HAL_UART_ERROR_PE = 0x01, /*!< Parity error */ + HAL_UART_ERROR_NE = 0x02, /*!< Noise error */ + HAL_UART_ERROR_FE = 0x04, /*!< frame error */ + HAL_UART_ERROR_ORE = 0x08, /*!< Overrun error */ + HAL_UART_ERROR_DMA = 0x10 /*!< DMA transfer error */ +}HAL_UART_ErrorTypeDef; + +/** + * @brief UART clock sources definition + */ +typedef enum +{ + UART_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */ + UART_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */ + UART_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */ + UART_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */ + UART_CLOCKSOURCE_UNDEFINED = 0x10 /*!< undefined clock source */ +}UART_ClockSourceTypeDef; + +/** + * @brief UART handle Structure definition + */ +typedef struct +{ + USART_TypeDef *Instance; /* UART registers base address */ + + UART_InitTypeDef Init; /* UART communication parameters */ + + UART_AdvFeatureInitTypeDef AdvancedInit; /* UART Advanced Features initialization parameters */ + + uint8_t *pTxBuffPtr; /* Pointer to UART Tx transfer Buffer */ + + uint16_t TxXferSize; /* UART Tx Transfer size */ + + uint16_t TxXferCount; /* UART Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /* Pointer to UART Rx transfer Buffer */ + + uint16_t RxXferSize; /* UART Rx Transfer size */ + + uint16_t RxXferCount; /* UART Rx Transfer Counter */ + + uint16_t Mask; /* UART Rx RDR register mask */ + + DMA_HandleTypeDef *hdmatx; /* UART Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /* UART Rx DMA Handle parameters */ + + HAL_LockTypeDef Lock; /* Locking object */ + + HAL_UART_StateTypeDef State; /* UART communication state */ + + HAL_UART_ErrorTypeDef ErrorCode; /* UART Error code */ + +}UART_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UART_Exported_Constants UART Exported constants + * @{ + */ + +/** @defgroup UART_Stop_Bits UART Number of Stop Bits + * @{ + */ +#define UART_STOPBITS_1 ((uint32_t)0x0000) +#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) +#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \ + ((STOPBITS) == UART_STOPBITS_2)) +/** + * @} + */ + +/** @defgroup UART_Parity UART Parity + * @{ + */ +#define UART_PARITY_NONE ((uint32_t)0x0000) +#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) +#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) +#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \ + ((PARITY) == UART_PARITY_EVEN) || \ + ((PARITY) == UART_PARITY_ODD)) +/** + * @} + */ + +/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control + * @{ + */ +#define UART_HWCONTROL_NONE ((uint32_t)0x0000) +#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE) +#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE) +#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE)) +#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\ + (((CONTROL) == UART_HWCONTROL_NONE) || \ + ((CONTROL) == UART_HWCONTROL_RTS) || \ + ((CONTROL) == UART_HWCONTROL_CTS) || \ + ((CONTROL) == UART_HWCONTROL_RTS_CTS)) +/** + * @} + */ + +/** @defgroup UART_Mode UART Transfer Mode + * @{ + */ +#define UART_MODE_RX ((uint32_t)USART_CR1_RE) +#define UART_MODE_TX ((uint32_t)USART_CR1_TE) +#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) +#define IS_UART_MODE(MODE) ((((MODE) & (~((uint32_t)(UART_MODE_TX_RX)))) == (uint32_t)0x00) && ((MODE) != (uint32_t)0x00)) +/** + * @} + */ + + /** @defgroup UART_State UART State + * @{ + */ +#define UART_STATE_DISABLE ((uint32_t)0x0000) +#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE) +#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \ + ((STATE) == UART_STATE_ENABLE)) +/** + * @} + */ + +/** @defgroup UART_Over_Sampling UART Over Sampling + * @{ + */ +#define UART_OVERSAMPLING_16 ((uint32_t)0x0000) +#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8) +#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \ + ((SAMPLING) == UART_OVERSAMPLING_8)) +/** + * @} + */ + +/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method + * @{ + */ +#define UART_ONEBIT_SAMPLING_DISABLED ((uint32_t)0x0000) +#define UART_ONEBIT_SAMPLING_ENABLED ((uint32_t)USART_CR3_ONEBIT) +#define IS_UART_ONEBIT_SAMPLING(ONEBIT) (((ONEBIT) == UART_ONEBIT_SAMPLING_DISABLED) || \ + ((ONEBIT) == UART_ONEBIT_SAMPLING_ENABLED)) +/** + * @} + */ + + +/** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut + * @{ + */ +#define UART_RECEIVER_TIMEOUT_DISABLE ((uint32_t)0x00000000) +#define UART_RECEIVER_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN) +#define IS_UART_RECEIVER_TIMEOUT(TIMEOUT) (((TIMEOUT) == UART_RECEIVER_TIMEOUT_DISABLE) || \ + ((TIMEOUT) == UART_RECEIVER_TIMEOUT_ENABLE)) +/** + * @} + */ + +/** @defgroup UART_One_Bit UART One Bit sampling + * @{ + */ +#define UART_ONE_BIT_SAMPLE_DISABLED ((uint32_t)0x00000000) +#define UART_ONE_BIT_SAMPLE_ENABLED ((uint32_t)USART_CR3_ONEBIT) +#define IS_UART_ONEBIT_SAMPLE(ONEBIT) (((ONEBIT) == UART_ONE_BIT_SAMPLE_DISABLED) || \ + ((ONEBIT) == UART_ONE_BIT_SAMPLE_ENABLED)) +/** + * @} + */ + +/** @defgroup UART_DMA_Tx UART DMA Tx + * @{ + */ +#define UART_DMA_TX_DISABLE ((uint32_t)0x00000000) +#define UART_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT) +#define IS_UART_DMA_TX(DMATX) (((DMATX) == UART_DMA_TX_DISABLE) || \ + ((DMATX) == UART_DMA_TX_ENABLE)) +/** + * @} + */ + +/** @defgroup UART_DMA_Rx UART DMA Rx + * @{ + */ +#define UART_DMA_RX_DISABLE ((uint32_t)0x0000) +#define UART_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR) +#define IS_UART_DMA_RX(DMARX) (((DMARX) == UART_DMA_RX_DISABLE) || \ + ((DMARX) == UART_DMA_RX_ENABLE)) +/** + * @} + */ + +/** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection + * @{ + */ +#define UART_HALF_DUPLEX_DISABLE ((uint32_t)0x0000) +#define UART_HALF_DUPLEX_ENABLE ((uint32_t)USART_CR3_HDSEL) +#define IS_UART_HALF_DUPLEX(HDSEL) (((HDSEL) == UART_HALF_DUPLEX_DISABLE) || \ + ((HDSEL) == UART_HALF_DUPLEX_ENABLE)) +/** + * @} + */ + +/** @defgroup UART_WakeUp_Address_Length UART WakeUp Address Length + * @{ + */ +#define UART_ADDRESS_DETECT_4B ((uint32_t)0x00000000) +#define UART_ADDRESS_DETECT_7B ((uint32_t)USART_CR2_ADDM7) +#define IS_UART_ADDRESSLENGTH_DETECT(ADDRESS) (((ADDRESS) == UART_ADDRESS_DETECT_4B) || \ + ((ADDRESS) == UART_ADDRESS_DETECT_7B)) +/** + * @} + */ + +/** @defgroup UART_WakeUp_Methods UART WakeUp Methods + * @{ + */ +#define UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000) +#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE) +#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \ + ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK)) +/** + * @} + */ + +/** @defgroup UART_IT UART IT + * Elements values convention: 000000000XXYYYYYb + * - YYYYY : Interrupt source position in the XX register (5bits) + * - XX : Interrupt source register (2bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + * @{ + */ +#define UART_IT_ERR ((uint16_t)0x0060) + +/** Elements values convention: 0000ZZZZ00000000b + * - ZZZZ : Flag position in the ISR register(4bits) + */ +#define UART_IT_ORE ((uint16_t)0x0300) +#define UART_IT_NE ((uint16_t)0x0200) +#define UART_IT_FE ((uint16_t)0x0100) +/** + * @} + */ + +/** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type + * @{ + */ +#define UART_ADVFEATURE_NO_INIT ((uint32_t)0x00000000) +#define UART_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001) +#define UART_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002) +#define UART_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004) +#define UART_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008) +#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010) +#define UART_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020) +#define UART_ADVFEATURE_AUTOBAUDRATE_INIT ((uint32_t)0x00000040) +#define UART_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080) +#define IS_UART_ADVFEATURE_INIT(INIT) ((INIT) <= (UART_ADVFEATURE_NO_INIT | \ + UART_ADVFEATURE_TXINVERT_INIT | \ + UART_ADVFEATURE_RXINVERT_INIT | \ + UART_ADVFEATURE_DATAINVERT_INIT | \ + UART_ADVFEATURE_SWAP_INIT | \ + UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \ + UART_ADVFEATURE_DMADISABLEONERROR_INIT | \ + UART_ADVFEATURE_AUTOBAUDRATE_INIT | \ + UART_ADVFEATURE_MSBFIRST_INIT)) +/** + * @} + */ + +/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion + * @{ + */ +#define UART_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000) +#define UART_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV) +#define IS_UART_ADVFEATURE_TXINV(TXINV) (((TXINV) == UART_ADVFEATURE_TXINV_DISABLE) || \ + ((TXINV) == UART_ADVFEATURE_TXINV_ENABLE)) +/** + * @} + */ + +/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion + * @{ + */ +#define UART_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000) +#define UART_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV) +#define IS_UART_ADVFEATURE_RXINV(RXINV) (((RXINV) == UART_ADVFEATURE_RXINV_DISABLE) || \ + ((RXINV) == UART_ADVFEATURE_RXINV_ENABLE)) +/** + * @} + */ + +/** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion + * @{ + */ +#define UART_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000) +#define UART_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV) +#define IS_UART_ADVFEATURE_DATAINV(DATAINV) (((DATAINV) == UART_ADVFEATURE_DATAINV_DISABLE) || \ + ((DATAINV) == UART_ADVFEATURE_DATAINV_ENABLE)) +/** + * @} + */ + +/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap + * @{ + */ +#define UART_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000) +#define UART_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP) +#define IS_UART_ADVFEATURE_SWAP(SWAP) (((SWAP) == UART_ADVFEATURE_SWAP_DISABLE) || \ + ((SWAP) == UART_ADVFEATURE_SWAP_ENABLE)) +/** + * @} + */ + +/** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable + * @{ + */ +#define UART_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000) +#define UART_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS) +#define IS_UART_OVERRUN(OVERRUN) (((OVERRUN) == UART_ADVFEATURE_OVERRUN_ENABLE) || \ + ((OVERRUN) == UART_ADVFEATURE_OVERRUN_DISABLE)) +/** + * @} + */ + +/** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable + * @{ + */ +#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE ((uint32_t)0x00000000) +#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE ((uint32_t)USART_CR2_ABREN) +#define IS_UART_ADVFEATURE_AUTOBAUDRATE(AUTOBAUDRATE) (((AUTOBAUDRATE) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \ + ((AUTOBAUDRATE) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)) +/** + * @} + */ + +/** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error + * @{ + */ +#define UART_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000) +#define UART_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE) +#define IS_UART_ADVFEATURE_DMAONRXERROR(DMA) (((DMA) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \ + ((DMA) == UART_ADVFEATURE_DMA_DISABLEONRXERROR)) +/** + * @} + */ + +/** @defgroup UART_MSB_First UART Advanced Feature MSB First + * @{ + */ +#define UART_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000) +#define UART_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST) +#define IS_UART_ADVFEATURE_MSBFIRST(MSBFIRST) (((MSBFIRST) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \ + ((MSBFIRST) == UART_ADVFEATURE_MSBFIRST_ENABLE)) +/** + * @} + */ + +/** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable + * @{ + */ +#define UART_ADVFEATURE_MUTEMODE_DISABLE ((uint32_t)0x00000000) +#define UART_ADVFEATURE_MUTEMODE_ENABLE ((uint32_t)USART_CR1_MME) +#define IS_UART_MUTE_MODE(MUTE) (((MUTE) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \ + ((MUTE) == UART_ADVFEATURE_MUTEMODE_ENABLE)) +/** + * @} + */ + +/** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register + * @{ + */ +#define UART_CR2_ADDRESS_LSB_POS ((uint32_t) 24) +/** + * @} + */ + +/** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity + * @{ + */ +#define UART_DE_POLARITY_HIGH ((uint32_t)0x00000000) +#define UART_DE_POLARITY_LOW ((uint32_t)USART_CR3_DEP) +#define IS_UART_DE_POLARITY(POLARITY) (((POLARITY) == UART_DE_POLARITY_HIGH) || \ + ((POLARITY) == UART_DE_POLARITY_LOW)) +/** + * @} + */ + +/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register + * @{ + */ +#define UART_CR1_DEAT_ADDRESS_LSB_POS ((uint32_t) 21) +/** + * @} + */ + +/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register + * @{ + */ +#define UART_CR1_DEDT_ADDRESS_LSB_POS ((uint32_t) 16) +/** + * @} + */ + +/** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask + * @{ + */ +#define UART_IT_MASK ((uint32_t)0x001F) +/** + * @} + */ + +/** @defgroup UART_TimeOut_Value UART polling-based communications time-out value + * @{ + */ +#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFF +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup UART_Exported_Macros UART Exported Macros + * @{ + */ + +/** @brief Reset UART handle state + * @param __HANDLE__: UART handle. + * @retval None + */ +#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_UART_STATE_RESET) + +/** @brief Checks whether the specified UART flag is set or not. + * @param __HANDLE__: specifies the UART Handle. + * This parameter can be UARTx where x: 1, 2, 3 or 4 to select the USART or + * UART peripheral (datasheet: up to four USART/UARTs) + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg UART_FLAG_REACK: Receive enable ackowledge flag + * @arg UART_FLAG_TEACK: Transmit enable ackowledge flag + * @arg UART_FLAG_WUF: Wake up from stop mode flag (not available on F030xx devices) + * @arg UART_FLAG_RWU: Receiver wake up flag (not available on F030xx devices) + * @arg UART_FLAG_SBKF: Send Break flag + * @arg UART_FLAG_CMF: Character match flag + * @arg UART_FLAG_BUSY: Busy flag + * @arg UART_FLAG_ABRF: Auto Baud rate detection flag + * @arg UART_FLAG_ABRE: Auto Baud rate detection error flag + * @arg UART_FLAG_EOBF: End of block flag (not available on F030xx devices) + * @arg UART_FLAG_RTOF: Receiver timeout flag + * @arg UART_FLAG_CTS: CTS Change flag + * @arg UART_FLAG_LBD: LIN Break detection flag (not available on F030xx devices) + * @arg UART_FLAG_TXE: Transmit data register empty flag + * @arg UART_FLAG_TC: Transmission Complete flag + * @arg UART_FLAG_RXNE: Receive data register not empty flag + * @arg UART_FLAG_IDLE: Idle Line detection flag + * @arg UART_FLAG_ORE: OverRun Error flag + * @arg UART_FLAG_NE: Noise Error flag + * @arg UART_FLAG_FE: Framing Error flag + * @arg UART_FLAG_PE: Parity Error flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) + +/** @brief Enables the specified UART interrupt. + * @param __HANDLE__: specifies the UART Handle. + * This parameter can be UARTx where x: 1, 2, 3 or 4 to select the USART or + * UART peripheral. (datasheet: up to four USART/UARTs) + * @param __INTERRUPT__: specifies the UART interrupt source to enable. + * This parameter can be one of the following values: + * @arg UART_IT_WUF: Wakeup from stop mode interrupt (not available on F030xx devices) + * @arg UART_IT_CM: Character match interrupt + * @arg UART_IT_CTS: CTS change interrupt + * @arg UART_IT_LBD: LIN Break detection interrupt (not available on F030xx devices) + * @arg UART_IT_TXE: Transmit Data Register empty interrupt + * @arg UART_IT_TC: Transmission complete interrupt + * @arg UART_IT_RXNE: Receive Data register not empty interrupt + * @arg UART_IT_IDLE: Idle line detection interrupt + * @arg UART_IT_PE: Parity Error interrupt + * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK)))) + + +/** @brief Disables the specified UART interrupt. + * @param __HANDLE__: specifies the UART Handle. + * This parameter can be UARTx where x: 1, 2, 3 or 4 to select the USART or + * UART peripheral. (datasheet: up to four USART/UARTs) + * @param __INTERRUPT__: specifies the UART interrupt source to disable. + * This parameter can be one of the following values: + * @arg UART_IT_WUF: Wakeup from stop mode interrupt (not available on F030xx devices) + * @arg UART_IT_CM: Character match interrupt + * @arg UART_IT_CTS: CTS change interrupt + * @arg UART_IT_LBD: LIN Break detection interrupt (not available on F030xx devices) + * @arg UART_IT_TXE: Transmit Data Register empty interrupt + * @arg UART_IT_TC: Transmission complete interrupt + * @arg UART_IT_RXNE: Receive Data register not empty interrupt + * @arg UART_IT_IDLE: Idle line detection interrupt + * @arg UART_IT_PE: Parity Error interrupt + * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK)))) + +/** @brief Checks whether the specified UART interrupt has occurred or not. + * @param __HANDLE__: specifies the UART Handle. + * This parameter can be UARTx where x: 1, 2, 3 or 4 to select the USART or + * UART peripheral. (datasheet: up to four USART/UARTs) + * @param __IT__: specifies the UART interrupt to check. + * This parameter can be one of the following values: + * @arg UART_IT_WUF: Wakeup from stop mode interrupt (not available on F030xx devices) + * @arg UART_IT_CM: Character match interrupt + * @arg UART_IT_CTS: CTS change interrupt + * @arg UART_IT_LBD: LIN Break detection interrupt (not available on F030xx devices) + * @arg UART_IT_TXE: Transmit Data Register empty interrupt + * @arg UART_IT_TC: Transmission complete interrupt + * @arg UART_IT_RXNE: Receive Data register not empty interrupt + * @arg UART_IT_IDLE: Idle line detection interrupt + * @arg UART_IT_ORE: OverRun Error interrupt + * @arg UART_IT_NE: Noise Error interrupt + * @arg UART_IT_FE: Framing Error interrupt + * @arg UART_IT_PE: Parity Error interrupt + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08))) + +/** @brief Checks whether the specified UART interrupt source is enabled. + * @param __HANDLE__: specifies the UART Handle. + * This parameter can be UARTx where x: 1, 2, 3 or 4 to select the USART or + * UART peripheral. (datasheet: up to four USART/UARTs) + * @param __IT__: specifies the UART interrupt source to check. + * This parameter can be one of the following values: + * @arg UART_IT_WUF: Wakeup from stop mode interrupt (not available on F030xx devices) + * @arg UART_IT_CM: Character match interrupt + * @arg UART_IT_CTS: CTS change interrupt + * @arg UART_IT_LBD: LIN Break detection interrupt (not available on F030xx devices) + * @arg UART_IT_TXE: Transmit Data Register empty interrupt + * @arg UART_IT_TC: Transmission complete interrupt + * @arg UART_IT_RXNE: Receive Data register not empty interrupt + * @arg UART_IT_IDLE: Idle line detection interrupt + * @arg UART_IT_ORE: OverRun Error interrupt + * @arg UART_IT_NE: Noise Error interrupt + * @arg UART_IT_FE: Framing Error interrupt + * @arg UART_IT_PE: Parity Error interrupt + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \ + (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & UART_IT_MASK))) + +/** @brief Clears the specified UART ISR flag, in setting the proper ICR register flag. + * @param __HANDLE__: specifies the UART Handle. + * This parameter can be UARTx where x: 1, 2, 3 or 4 to select the USART or + * UART peripheral. (datasheet: up to four USART/UARTs) + * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set + * to clear the corresponding interrupt + * This parameter can be one of the following values: + * @arg UART_CLEAR_PEF: Parity Error Clear Flag + * @arg UART_CLEAR_FEF: Framing Error Clear Flag + * @arg UART_CLEAR_NEF: Noise detected Clear Flag + * @arg UART_CLEAR_OREF: OverRun Error Clear Flag + * @arg UART_CLEAR_IDLEF: IDLE line detected Clear Flag + * @arg UART_CLEAR_TCF: Transmission Complete Clear Flag + * @arg UART_CLEAR_LBDF: LIN Break Detection Clear Flag (not available on F030xx devices) + * @arg UART_CLEAR_CTSF: CTS Interrupt Clear Flag + * @arg UART_CLEAR_RTOF: Receiver Time Out Clear Flag + * @arg UART_CLEAR_EOBF: End Of Block Clear Flag (not available on F030xx devices) + * @arg UART_CLEAR_CMF: Character Match Clear Flag + * @arg UART_CLEAR_WUF: Wake Up from stop mode Clear Flag (not available on F030xx devices) + * @retval None + */ +#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) + +/** @brief Set a specific UART request flag. + * @param __HANDLE__: specifies the UART Handle. + * This parameter can be UARTx where x: 1, 2, 3 or 4 to select the USART or + * UART peripheral. (datasheet: up to four USART/UARTs) + * @param __REQ__: specifies the request flag to set + * This parameter can be one of the following values: + * @arg UART_AUTOBAUD_REQUEST: Auto-Baud Rate Request + * @arg UART_SENDBREAK_REQUEST: Send Break Request + * @arg UART_MUTE_MODE_REQUEST: Mute Mode Request + * @arg UART_RXDATA_FLUSH_REQUEST: Receive Data flush Request + * @arg UART_TXDATA_FLUSH_REQUEST: Transmit data flush Request (not available on F030xx devices) + * @retval None + */ +#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) + +/** @brief Enable UART + * @param __HANDLE__: specifies the UART Handle. + * The Handle Instance can be UARTx where x: 1, 2, 3, 4 or 5 to select the UART peripheral + * @retval None + */ +#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) + +/** @brief Disable UART + * @param __HANDLE__: specifies the UART Handle. + * The Handle Instance can be UARTx where x: 1, 2, 3, 4 or 5 to select the UART peripheral + * @retval None + */ +#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) + +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @defgroup UART_Private_Macros UART Private Macros + * @{ + */ + +/** @brief BRR division operation to set BRR register in 8-bit oversampling mode + * @param _PCLK_: UART clock + * @param _BAUD_: Baud rate set by the user + * @retval Division result + */ +#define __DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*2)/((_BAUD_))) + +/** @brief BRR division operation to set BRR register in 16-bit oversampling mode + * @param _PCLK_: UART clock + * @param _BAUD_: Baud rate set by the user + * @retval Division result + */ +#define __DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_))/((_BAUD_))) + +/** @brief Check UART Baud rate + * @param BAUDRATE: Baudrate specified by the user + * The maximum Baud Rate is derived from the maximum clock on F0 (i.e. 48 MHz) + * divided by the smallest oversampling used on the USART (i.e. 8) + * @retval Test result (TRUE or FALSE). + */ +#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 9000001) + +/** @brief Check UART assertion time + * @param TIME: 5-bit value assertion time + * @retval Test result (TRUE or FALSE). + */ +#define IS_UART_ASSERTIONTIME(TIME) ((TIME) <= 0x1F) + +/** @brief Check UART deassertion time + * @param TIME: 5-bit value deassertion time + * @retval Test result (TRUE or FALSE). + */ +#define IS_UART_DEASSERTIONTIME(TIME) ((TIME) <= 0x1F) + +/** + * @} + */ + +/* Include UART HAL Extension module */ +#include "stm32f0xx_hal_uart_ex.h" + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup UART_Exported_Functions UART Exported Functions + * @{ + */ + +/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod); +HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart); +void HAL_UART_MspInit(UART_HandleTypeDef *huart); +void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group2 IO operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart); +void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ + +/* Peripheral Control functions ***********************************************/ +void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Errors functions + * @{ + */ + +/* Peripheral State and Errors functions **************************************************/ +HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart); +uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup UART_Private_Functions + * @{ + */ +void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_UART_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h @@ -0,0 +1,649 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_uart_ex.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Header file of UART HAL Extension module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_UART_EX_H +#define __STM32F0xx_HAL_UART_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup UARTEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants + * @{ + */ + +/** @defgroup UARTEx_Word_Length UARTEx Word Length + * @{ + */ +#if defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) +#define UART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) +#define UART_WORDLENGTH_8B ((uint32_t)0x00000000) +#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) +#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_7B) || \ + ((LENGTH) == UART_WORDLENGTH_8B) || \ + ((LENGTH) == UART_WORDLENGTH_9B)) +#else +#define UART_WORDLENGTH_8B ((uint32_t)0x00000000) +#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) +#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \ + ((LENGTH) == UART_WORDLENGTH_9B)) +#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) */ +/** + * @} + */ + +/** @defgroup UARTEx_AutoBaud_Rate_Mode UARTEx Advanced Feature AutoBaud Rate Mode + * @{ + */ +#if defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) +#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT ((uint32_t)0x0000) +#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0) +#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME ((uint32_t)USART_CR2_ABRMODE_1) +#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME ((uint32_t)USART_CR2_ABRMODE) +#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(MODE) (((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \ + ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \ + ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \ + ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME)) +#else +#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT ((uint32_t)0x0000) +#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0) +#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(MODE) (((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \ + ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE)) +#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) */ +/** + * @} + */ + + +#if !defined(STM32F030x6) && !defined(STM32F030x8) +/** @defgroup UARTEx_LIN UARTEx Local Interconnection Network mode + * @{ + */ +#define UART_LIN_DISABLE ((uint32_t)0x00000000) +#define UART_LIN_ENABLE ((uint32_t)USART_CR2_LINEN) +#define IS_UART_LIN(LIN) (((LIN) == UART_LIN_DISABLE) || \ + ((LIN) == UART_LIN_ENABLE)) +/** + * @} + */ + +/** @defgroup UARTEx_LIN_Break_Detection UARTEx LIN Break Detection + * @{ + */ +#define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000) +#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL) +#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \ + ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B)) +/** + * @} + */ +#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */ + +/** @defgroup UART_Flags UARTEx Status Flags + * Elements values convention: 0xXXXX + * - 0xXXXX : Flag mask in the ISR register + * @{ + */ +#define UART_FLAG_REACK ((uint32_t)0x00400000) +#define UART_FLAG_TEACK ((uint32_t)0x00200000) +#if !defined(STM32F030x6) && !defined(STM32F030x8) +#define UART_FLAG_WUF ((uint32_t)0x00100000) +#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */ +#define UART_FLAG_RWU ((uint32_t)0x00080000) +#define UART_FLAG_SBKF ((uint32_t)0x00040000 +#define UART_FLAG_CMF ((uint32_t)0x00020000) +#define UART_FLAG_BUSY ((uint32_t)0x00010000) +#define UART_FLAG_ABRF ((uint32_t)0x00008000) +#define UART_FLAG_ABRE ((uint32_t)0x00004000) +#if !defined(STM32F030x6) && !defined(STM32F030x8) +#define UART_FLAG_EOBF ((uint32_t)0x00001000) +#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */ +#define UART_FLAG_RTOF ((uint32_t)0x00000800) +#define UART_FLAG_CTS ((uint32_t)0x00000400) +#define UART_FLAG_CTSIF ((uint32_t)0x00000200) +#if !defined(STM32F030x6) && !defined(STM32F030x8) +#define UART_FLAG_LBDF ((uint32_t)0x00000100) +#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */ +#define UART_FLAG_TXE ((uint32_t)0x00000080) +#define UART_FLAG_TC ((uint32_t)0x00000040) +#define UART_FLAG_RXNE ((uint32_t)0x00000020) +#define UART_FLAG_IDLE ((uint32_t)0x00000010) +#define UART_FLAG_ORE ((uint32_t)0x00000008) +#define UART_FLAG_NE ((uint32_t)0x00000004) +#define UART_FLAG_FE ((uint32_t)0x00000002) +#define UART_FLAG_PE ((uint32_t)0x00000001) +/** + * @} + */ + +/** @defgroup UART_Interrupt_definition UARTEx Interrupts Definition + * Elements values convention: 0000ZZZZ0XXYYYYYb + * - YYYYY : Interrupt source position in the XX register (5bits) + * - XX : Interrupt source register (2bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + * - ZZZZ : Flag position in the ISR register(4bits) + * @{ + */ +#define UART_IT_PE ((uint16_t)0x0028) +#define UART_IT_TXE ((uint16_t)0x0727) +#define UART_IT_TC ((uint16_t)0x0626) +#define UART_IT_RXNE ((uint16_t)0x0525) +#define UART_IT_IDLE ((uint16_t)0x0424) +#if !defined(STM32F030x6) && !defined(STM32F030x8) +#define UART_IT_LBD ((uint16_t)0x0846) +#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */ +#define UART_IT_CTS ((uint16_t)0x096A) +#define UART_IT_CM ((uint16_t)0x142E) +#if !defined(STM32F030x6) && !defined(STM32F030x8) +#define UART_IT_WUF ((uint16_t)0x1476) +#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */ +/** + * @} + */ + + +/** @defgroup UART_IT_CLEAR_Flags UARTEx Interruption Clear Flags + * @{ + */ +#define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ +#define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ +#define UART_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */ +#define UART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */ +#define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ +#define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ +#if !defined(STM32F030x6) && !defined(STM32F030x8) +#define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag (not available on F030xx devices)*/ +#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */ +#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */ +#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< Receiver Time Out Clear Flag */ +#define UART_CLEAR_EOBF USART_ICR_EOBCF /*!< End Of Block Clear Flag */ +#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */ +#if !defined(STM32F030x6) && !defined(STM32F030x8) +#define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */ +#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */ +/** + * @} + */ + +/** @defgroup UART_Request_Parameters UARTEx Request Parameters + * @{ + */ +#define UART_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */ +#define UART_SENDBREAK_REQUEST ((uint32_t)USART_RQR_SBKRQ) /*!< Send Break Request */ +#define UART_MUTE_MODE_REQUEST ((uint32_t)USART_RQR_MMRQ) /*!< Mute Mode Request */ +#define UART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */ +#if !defined(STM32F030x6) && !defined(STM32F030x8) +#define UART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */ +#define IS_UART_REQUEST_PARAMETER(PARAM) (((PARAM) == UART_AUTOBAUD_REQUEST) || \ + ((PARAM) == UART_SENDBREAK_REQUEST) || \ + ((PARAM) == UART_MUTE_MODE_REQUEST) || \ + ((PARAM) == UART_RXDATA_FLUSH_REQUEST) || \ + ((PARAM) == UART_TXDATA_FLUSH_REQUEST)) +#else +#define IS_UART_REQUEST_PARAMETER(PARAM) (((PARAM) == UART_AUTOBAUD_REQUEST) || \ + ((PARAM) == UART_SENDBREAK_REQUEST) || \ + ((PARAM) == UART_MUTE_MODE_REQUEST) || \ + ((PARAM) == UART_RXDATA_FLUSH_REQUEST)) +#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */ +/** + * @} + */ + +#if !defined(STM32F030x6) && !defined(STM32F030x8) +/** @defgroup UART_Stop_Mode_Enable UARTEx Advanced Feature Stop Mode Enable + * @{ + */ +#define UART_ADVFEATURE_STOPMODE_DISABLE ((uint32_t)0x00000000) +#define UART_ADVFEATURE_STOPMODE_ENABLE ((uint32_t)USART_CR1_UESM) +#define IS_UART_ADVFEATURE_STOPMODE(STOPMODE) (((STOPMODE) == UART_ADVFEATURE_STOPMODE_DISABLE) || \ + ((STOPMODE) == UART_ADVFEATURE_STOPMODE_ENABLE)) +/** + * @} + */ + +/** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection + * @{ + */ +#define UART_WAKEUP_ON_ADDRESS ((uint32_t)0x0000) +#define UART_WAKEUP_ON_STARTBIT ((uint32_t)USART_CR3_WUS_1) +#define UART_WAKEUP_ON_READDATA_NONEMPTY ((uint32_t)USART_CR3_WUS) +#define IS_UART_WAKEUP_SELECTION(WAKE) (((WAKE) == UART_WAKEUP_ON_ADDRESS) || \ + ((WAKE) == UART_WAKEUP_ON_STARTBIT) || \ + ((WAKE) == UART_WAKEUP_ON_READDATA_NONEMPTY)) +/** + * @} + */ +#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup UARTEx_Exported_Macros UARTEx Exported Macros + * @{ + */ + +/** @brief Reports the UART clock source. + * @param __HANDLE__: specifies the UART Handle + * @param __CLOCKSOURCE__ : output variable + * @retval UART clocking source, written in __CLOCKSOURCE__. + */ + + +#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) +#define __HAL_UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } while(0) +#elif defined (STM32F030x8) || \ + defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F051x8) || defined (STM32F058xx) +#define __HAL_UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0) +#elif defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) +#define __HAL_UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == USART4) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0) +#elif defined(STM32F091xC) || defined (STM32F098xx) +#define __HAL_UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ + case RCC_USART3CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART3CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART3CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART3CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART4) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == USART5) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == USART6) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == USART7) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == USART8) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0) + +#endif /* defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) */ + + +/** @brief Computes the UART mask to apply to retrieve the received data + * according to the word length and to the parity bits activation. + * If PCE = 1, the parity bit is not included in the data extracted + * by the reception API(). + * This masking operation is not carried out in the case of + * DMA transfers. + * @param __HANDLE__: specifies the UART Handle + * @retval none + */ +#if defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) +#define __HAL_UART_MASK_COMPUTATION(__HANDLE__) \ + do { \ + if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x01FF ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x00FF ; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x00FF ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x007F ; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x007F ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x003F ; \ + } \ + } \ +} while(0) +#else +#define __HAL_UART_MASK_COMPUTATION(__HANDLE__) \ + do { \ + if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x01FF ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x00FF ; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x00FF ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x007F ; \ + } \ + } \ +} while(0) +#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup UARTEx_Exported_Functions + * @{ + */ + +/** @addtogroup UARTEx_Exported_Functions_Group1 + * @brief Extended Initialization and Configuration Functions + * @{ + */ +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t UART_DEPolarity, uint32_t UART_DEAssertionTime, uint32_t UART_DEDeassertionTime); +HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength); +HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); +HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart); +/** + * @} + */ + +/** @addtogroup UARTEx_Exported_Functions_Group2 + * @brief Extended I/O operation functions + * @{ + */ + +/* I/O operation functions ***************************************************/ +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart); +void HAL_UART_WakeupCallback(UART_HandleTypeDef *huart); +/** + * @} + */ + +/** @addtogroup UARTEx_Exported_Functions_Group3 + * @brief Extended Peripheral Control functions + * @{ + */ + +/* Peripheral Control functions **********************************************/ +void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength); +HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); +/** + * @} + */ +/* Peripheral State functions ************************************************/ + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_UART_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_usart.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_usart.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_usart.h @@ -0,0 +1,597 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_usart.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Header file of USART HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_USART_H +#define __STM32F0xx_HAL_USART_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup USART + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup USART_Exported_Types USART Exported Types + * @{ + */ + + +/** + * @brief USART Init Structure definition + */ +typedef struct +{ + uint32_t BaudRate; /*!< This member configures the Usart communication baud rate. + The baud rate is computed using the following formula: + Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate))) */ + + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USARTEx_Word_Length */ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_Stop_Bits */ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref USART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_Mode */ + + uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock. + This parameter can be a value of @ref USART_Clock_Polarity */ + + uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_Clock_Phase */ + + uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_Last_Bit */ +}USART_InitTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_USART_STATE_RESET = 0x00, /*!< Peripheral is not initialized */ + HAL_USART_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ + HAL_USART_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ + HAL_USART_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ + HAL_USART_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ + HAL_USART_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission Reception process is ongoing */ + HAL_USART_STATE_TIMEOUT = 0x03, /*!< Timeout state */ + HAL_USART_STATE_ERROR = 0x04 /*!< Error */ +}HAL_USART_StateTypeDef; + +/** + * @brief HAL USART Error Code structure definition + */ +typedef enum +{ + HAL_USART_ERROR_NONE = 0x00, /*!< No error */ + HAL_USART_ERROR_PE = 0x01, /*!< Parity error */ + HAL_USART_ERROR_NE = 0x02, /*!< Noise error */ + HAL_USART_ERROR_FE = 0x04, /*!< frame error */ + HAL_USART_ERROR_ORE = 0x08, /*!< Overrun error */ + HAL_USART_ERROR_DMA = 0x10 /*!< DMA transfer error */ +}HAL_USART_ErrorTypeDef; + +/** + * @brief USART clock sources definitions + */ +typedef enum +{ + USART_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */ + USART_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */ + USART_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */ + USART_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */ + USART_CLOCKSOURCE_UNDEFINED = 0x10 /*!< undefined clock source */ +}USART_ClockSourceTypeDef; + +/** + * @brief USART handle Structure definition + */ +typedef struct +{ + USART_TypeDef *Instance; /*!< USART registers base address */ + + USART_InitTypeDef Init; /*!< USART communication parameters */ + + uint8_t *pTxBuffPtr; /*!< Pointer to USART Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< USART Tx Transfer size */ + + uint16_t TxXferCount; /*!< USART Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /*!< Pointer to USART Rx transfer Buffer */ + + uint16_t RxXferSize; /*!< USART Rx Transfer size */ + + uint16_t RxXferCount; /*!< USART Rx Transfer Counter */ + + uint16_t Mask; /*!< USART Rx RDR register mask */ + + DMA_HandleTypeDef *hdmatx; /*!< USART Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< USART Rx DMA Handle parameters */ + + HAL_LockTypeDef Lock; /*!< Locking object */ + + HAL_USART_StateTypeDef State; /*!< USART communication state */ + + HAL_USART_ErrorTypeDef ErrorCode; /*!< USART Error code */ + +}USART_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup USART_Exported_Constants USART Exported constants + * @{ + */ + +/** @defgroup USART_Stop_Bits USART Number of Stop Bits + * @{ + */ +#define USART_STOPBITS_1 ((uint32_t)0x0000) +#define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0) +#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) +#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) +#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_STOPBITS_1) || \ + ((STOPBITS) == USART_STOPBITS_0_5) || \ + ((STOPBITS) == USART_STOPBITS_1_5) || \ + ((STOPBITS) == USART_STOPBITS_2)) +/** + * @} + */ + +/** @defgroup USART_Parity USART Parity + * @{ + */ +#define USART_PARITY_NONE ((uint32_t)0x0000) +#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) +#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) +#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PARITY_NONE) || \ + ((PARITY) == USART_PARITY_EVEN) || \ + ((PARITY) == USART_PARITY_ODD)) +/** + * @} + */ + +/** @defgroup USART_Mode USART Mode + * @{ + */ +#define USART_MODE_RX ((uint32_t)USART_CR1_RE) +#define USART_MODE_TX ((uint32_t)USART_CR1_TE) +#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) +#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFFFFFF3) == 0x00) && ((MODE) != (uint32_t)0x00)) +/** + * @} + */ + +/** @defgroup USART_Clock USART Clock + * @{ + */ +#define USART_CLOCK_DISABLED ((uint32_t)0x0000) +#define USART_CLOCK_ENABLED ((uint32_t)USART_CR2_CLKEN) +#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLOCK_DISABLED) || \ + ((CLOCK) == USART_CLOCK_ENABLED)) +/** + * @} + */ + +/** @defgroup USART_Clock_Polarity USART Clock Polarity + * @{ + */ +#define USART_POLARITY_LOW ((uint32_t)0x0000) +#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) +#define IS_USART_POLARITY(CPOL) (((CPOL) == USART_POLARITY_LOW) || ((CPOL) == USART_POLARITY_HIGH)) +/** + * @} + */ + +/** @defgroup USART_Clock_Phase USART Clock Phase + * @{ + */ +#define USART_PHASE_1EDGE ((uint32_t)0x0000) +#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) +#define IS_USART_PHASE(CPHA) (((CPHA) == USART_PHASE_1EDGE) || ((CPHA) == USART_PHASE_2EDGE)) +/** + * @} + */ + +/** @defgroup USART_Last_Bit USART Last Bit + * @{ + */ +#define USART_LASTBIT_DISABLE ((uint32_t)0x0000) +#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) +#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LASTBIT_DISABLE) || \ + ((LASTBIT) == USART_LASTBIT_ENABLE)) +/** + * @} + */ + + +/** @defgroup USART_Flags USART Flags + * Elements values convention: 0xXXXX + * - 0xXXXX : Flag mask in the ISR register + * @{ + */ +#define USART_FLAG_REACK ((uint32_t)0x00400000) +#define USART_FLAG_TEACK ((uint32_t)0x00200000) +#define USART_FLAG_BUSY ((uint32_t)0x00010000) +#define USART_FLAG_CTS ((uint32_t)0x00000400) +#define USART_FLAG_CTSIF ((uint32_t)0x00000200) +#define USART_FLAG_LBDF ((uint32_t)0x00000100) +#define USART_FLAG_TXE ((uint32_t)0x00000080) +#define USART_FLAG_TC ((uint32_t)0x00000040) +#define USART_FLAG_RXNE ((uint32_t)0x00000020) +#define USART_FLAG_IDLE ((uint32_t)0x00000010) +#define USART_FLAG_ORE ((uint32_t)0x00000008) +#define USART_FLAG_NE ((uint32_t)0x00000004) +#define USART_FLAG_FE ((uint32_t)0x00000002) +#define USART_FLAG_PE ((uint32_t)0x00000001) +/** + * @} + */ + +/** @defgroup USART_Interrupt_definition USART Interrupts Definition + * Elements values convention: 0000ZZZZ0XXYYYYYb + * - YYYYY : Interrupt source position in the XX register (5bits) + * - XX : Interrupt source register (2bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + * - ZZZZ : Flag position in the ISR register(4bits) + * @{ + */ + +#define USART_IT_PE ((uint16_t)0x0028) +#define USART_IT_TXE ((uint16_t)0x0727) +#define USART_IT_TC ((uint16_t)0x0626) +#define USART_IT_RXNE ((uint16_t)0x0525) +#define USART_IT_IDLE ((uint16_t)0x0424) +#define USART_IT_ERR ((uint16_t)0x0060) + +#define USART_IT_ORE ((uint16_t)0x0300) +#define USART_IT_NE ((uint16_t)0x0200) +#define USART_IT_FE ((uint16_t)0x0100) +/** + * @} + */ + +/** @defgroup USART_IT_CLEAR_Flags USART Interruption Clear Flags + * @{ + */ +#define USART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ +#define USART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ +#define USART_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */ +#define USART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */ +#define USART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ +#define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ +#define USART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */ +/** + * @} + */ + +/** @defgroup USART_Request_Parameters USART Request Parameters + * @{ + */ +#define USART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */ +#define USART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */ +#define IS_USART_REQUEST_PARAMETER(PARAM) (((PARAM) == USART_RXDATA_FLUSH_REQUEST) || \ + ((PARAM) == USART_TXDATA_FLUSH_REQUEST)) +/** + * @} + */ + +/** @defgroup USART_Interruption_Mask USART interruptions flag mask + * @{ + */ +#define USART_IT_MASK ((uint16_t)0x001F) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup USART_Exported_Macros USART Exported Macros + * @{ + */ + + +/** @brief Reset USART handle state + * @param __HANDLE__: USART handle. + * @retval None + */ +#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET) + +/** @brief Checks whether the specified USART flag is set or not. + * @param __HANDLE__: specifies the USART Handle + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg USART_FLAG_REACK: Receive enable ackowledge flag + * @arg USART_FLAG_TEACK: Transmit enable ackowledge flag + * @arg USART_FLAG_BUSY: Busy flag + * @arg USART_FLAG_CTS: CTS Change flag + * @arg USART_FLAG_TXE: Transmit data register empty flag + * @arg USART_FLAG_TC: Transmission Complete flag + * @arg USART_FLAG_RXNE: Receive data register not empty flag + * @arg USART_FLAG_IDLE: Idle Line detection flag + * @arg USART_FLAG_ORE: OverRun Error flag + * @arg USART_FLAG_NE: Noise Error flag + * @arg USART_FLAG_FE: Framing Error flag + * @arg USART_FLAG_PE: Parity Error flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) + + +/** @brief Enables the specified USART interrupt. + * @param __HANDLE__: specifies the USART Handle + * @param __INTERRUPT__: specifies the USART interrupt source to enable. + * This parameter can be one of the following values: + * @arg USART_IT_TXE: Transmit Data Register empty interrupt + * @arg USART_IT_TC: Transmission complete interrupt + * @arg USART_IT_RXNE: Receive Data register not empty interrupt + * @arg USART_IT_IDLE: Idle line detection interrupt + * @arg USART_IT_PE: Parity Error interrupt + * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK)))) + +/** @brief Disables the specified USART interrupt. + * @param __HANDLE__: specifies the USART Handle. + * @param __INTERRUPT__: specifies the USART interrupt source to disable. + * This parameter can be one of the following values: + * @arg USART_IT_TXE: Transmit Data Register empty interrupt + * @arg USART_IT_TC: Transmission complete interrupt + * @arg USART_IT_RXNE: Receive Data register not empty interrupt + * @arg USART_IT_IDLE: Idle line detection interrupt + * @arg USART_IT_PE: Parity Error interrupt + * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK)))) + + +/** @brief Checks whether the specified USART interrupt has occurred or not. + * @param __HANDLE__: specifies the USART Handle + * @param __IT__: specifies the USART interrupt source to check. + * This parameter can be one of the following values: + * @arg USART_IT_TXE: Transmit Data Register empty interrupt + * @arg USART_IT_TC: Transmission complete interrupt + * @arg USART_IT_RXNE: Receive Data register not empty interrupt + * @arg USART_IT_IDLE: Idle line detection interrupt + * @arg USART_IT_ORE: OverRun Error interrupt + * @arg USART_IT_NE: Noise Error interrupt + * @arg USART_IT_FE: Framing Error interrupt + * @arg USART_IT_PE: Parity Error interrupt + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08))) + +/** @brief Checks whether the specified USART interrupt source is enabled. + * @param __HANDLE__: specifies the USART Handle. + * @param __IT__: specifies the USART interrupt source to check. + * This parameter can be one of the following values: + * @arg USART_IT_TXE: Transmit Data Register empty interrupt + * @arg USART_IT_TC: Transmission complete interrupt + * @arg USART_IT_RXNE: Receive Data register not empty interrupt + * @arg USART_IT_IDLE: Idle line detection interrupt + * @arg USART_IT_ORE: OverRun Error interrupt + * @arg USART_IT_NE: Noise Error interrupt + * @arg USART_IT_FE: Framing Error interrupt + * @arg USART_IT_PE: Parity Error interrupt + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5) == 2)? \ + (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << \ + (((uint16_t)(__IT__)) & USART_IT_MASK))) + + +/** @brief Clears the specified USART ISR flag, in setting the proper ICR register flag. + * @param __HANDLE__: specifies the USART Handle. + * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set + * to clear the corresponding interrupt + * This parameter can be one of the following values: + * @arg USART_CLEAR_PEF: Parity Error Clear Flag + * @arg USART_CLEAR_FEF: Framing Error Clear Flag + * @arg USART_CLEAR_NEF: Noise detected Clear Flag + * @arg USART_CLEAR_OREF: OverRun Error Clear Flag + * @arg USART_CLEAR_IDLEF: IDLE line detected Clear Flag + * @arg USART_CLEAR_TCF: Transmission Complete Clear Flag + * @arg USART_CLEAR_CTSF: CTS Interrupt Clear Flag + * @retval None + */ +#define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) + +/** @brief Set a specific USART request flag. + * @param __HANDLE__: specifies the USART Handle. + * @param __REQ__: specifies the request flag to set + * This parameter can be one of the following values: + * @arg USART_RXDATA_FLUSH_REQUEST: Receive Data flush Request + * @arg USART_TXDATA_FLUSH_REQUEST: Transmit data flush Request + * + * @retval None + */ +#define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) + +/** @brief Enable USART + * @param __HANDLE__: specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) + +/** @brief Disable USART + * @param __HANDLE__: specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) + +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @defgroup USART_Private_Macros USART Private Macros + * @{ + */ + +/** @brief Check USART Baud rate + * @param BAUDRATE: Baudrate specified by the user + * The maximum Baud Rate is derived from the maximum clock on F0 (i.e. 48 MHz) + * divided by the smallest oversampling used on the USART (i.e. 8) + * @retval Test result (TRUE or FALSE) + */ +#define IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 9000001) +/** + * @} + */ + +/* Include USART HAL Extension module */ +#include "stm32f0xx_hal_usart_ex.h" + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup USART_Exported_Functions USART Exported Functions + * @{ + */ + +/** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions ******************************/ +HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart); +void HAL_USART_MspInit(USART_HandleTypeDef *husart); +void HAL_USART_MspDeInit(USART_HandleTypeDef *husart); +void HAL_USART_SetConfig(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USART_CheckIdleState(USART_HandleTypeDef *husart); + +/** + * @} + */ + +/** @addtogroup USART_Exported_Functions_Group2 IO operation functions + * @{ + */ + +/* IO operation functions *******************************************************/ +HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart); +void HAL_USART_IRQHandler(USART_HandleTypeDef *husart); +void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart); +void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart); +void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart); +void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart); +void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart); +void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart); + +/** + * @} + */ + +/* Peripheral Control functions ***********************************************/ + +/** @addtogroup USART_Exported_Functions_Group3 Peripheral State and Errors functions + * @{ + */ + +/* Peripheral State and Error functions ***************************************/ +HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart); +uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_USART_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_usart_ex.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_usart_ex.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_usart_ex.h @@ -0,0 +1,413 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_usart_ex.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Header file of USART HAL Extension module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_USART_EX_H +#define __STM32F0xx_HAL_USART_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup USARTEx USARTEx Extended HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants + * @{ + */ + +/** @defgroup USARTEx_Word_Length USARTEx Word Length + * @{ + */ +#if defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) +#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) +#define USART_WORDLENGTH_8B ((uint32_t)0x00000000) +#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) +#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WORDLENGTH_7B) || \ + ((LENGTH) == USART_WORDLENGTH_8B) || \ + ((LENGTH) == USART_WORDLENGTH_9B)) +#else +#define USART_WORDLENGTH_8B ((uint32_t)0x00000000) +#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) +#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WORDLENGTH_8B) || \ + ((LENGTH) == USART_WORDLENGTH_9B)) +#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup USARTEx_Exported_Macros USARTEx Exported Macros + * @{ + */ + +/** @brief Reports the USART clock source. + * @param __HANDLE__: specifies the USART Handle + * @param __CLOCKSOURCE__ : output variable + * @retval the USART clocking source, written in __CLOCKSOURCE__. + */ +#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) +#define __HAL_USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } while(0) +#elif defined (STM32F030x8) || \ + defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F051x8) || defined (STM32F058xx) +#define __HAL_USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0) +#elif defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) +#define __HAL_USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == USART4) \ + { \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0) +#elif defined(STM32F091xC) || defined (STM32F098xx) +#define __HAL_USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ + case RCC_USART3CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART3CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART3CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART3CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART4) \ + { \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == USART5) \ + { \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == USART6) \ + { \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == USART7) \ + { \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == USART8) \ + { \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0) +#endif /* defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) */ + + +/** @brief Reports the USART mask to apply to retrieve the received data + * according to the word length and to the parity bits activation. + * If PCE = 1, the parity bit is not included in the data extracted + * by the reception API(). + * This masking operation is not carried out in the case of + * DMA transfers. + * @param __HANDLE__: specifies the USART Handle + * @retval none + */ +#if defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) +#define __HAL_USART_MASK_COMPUTATION(__HANDLE__) \ + do { \ + if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \ + { \ + if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x01FF ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x00FF ; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \ + { \ + if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x00FF ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x007F ; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \ + { \ + if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x007F ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x003F ; \ + } \ + } \ +} while(0) +#else +#define __HAL_USART_MASK_COMPUTATION(__HANDLE__) \ + do { \ + if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \ + { \ + if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x01FF ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x00FF ; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \ + { \ + if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x00FF ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x007F ; \ + } \ + } \ +} while(0) +#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/* Initialization and de-initialization functions ****************************/ +/* I/O operation functions ***************************************************/ +/* Peripheral Control functions **********************************************/ +/* Peripheral State functions ************************************************/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_USART_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_wwdg.h b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_wwdg.h new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_wwdg.h @@ -0,0 +1,311 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_wwdg.h + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Header file of WWDG HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_WWDG_H +#define __STM32F0xx_HAL_WWDG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup WWDG + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup WWDG_Exported_Types WWDG Exported Types + * @{ + */ + +/** + * @brief WWDG HAL State Structure definition + */ +typedef enum +{ + HAL_WWDG_STATE_RESET = 0x00, /*!< WWDG not yet initialized or disabled */ + HAL_WWDG_STATE_READY = 0x01, /*!< WWDG initialized and ready for use */ + HAL_WWDG_STATE_BUSY = 0x02, /*!< WWDG internal process is ongoing */ + HAL_WWDG_STATE_TIMEOUT = 0x03, /*!< WWDG timeout state */ + HAL_WWDG_STATE_ERROR = 0x04 /*!< WWDG error state */ +}HAL_WWDG_StateTypeDef; + +/** + * @brief WWDG Init structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDG. + This parameter can be a value of @ref WWDG_Prescaler */ + + uint32_t Window; /*!< Specifies the WWDG window value to be compared to the downcounter. + This parameter must be a number lower than Max_Data = 0x80 */ + + uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value. + This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */ + +} WWDG_InitTypeDef; + +/** + * @brief WWDG handle Structure definition + */ +typedef struct +{ + WWDG_TypeDef *Instance; /*!< Register base address */ + + WWDG_InitTypeDef Init; /*!< WWDG required parameters */ + + HAL_LockTypeDef Lock; /*!< WWDG locking object */ + + __IO HAL_WWDG_StateTypeDef State; /*!< WWDG communication state */ + +} WWDG_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup WWDG_Exported_Constants WWDG Exported Constants + * @{ + */ + +/** @defgroup WWDG_BitAddress_AliasRegion WWDG BitAddress AliasRegion + * @brief WWDG registers bit address in the alias region + * @{ + */ + +/* --- CFR Register ---*/ +/* Alias word address of EWI bit */ +#define CFR_BASE (uint32_t)(WWDG_BASE + 0x04) + +/** + * @} + */ + +/** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition + * @{ + */ +#define WWDG_IT_EWI ((uint32_t)WWDG_CFR_EWI) + +/** + * @} + */ + +/** @defgroup WWDG_Flag_definition WWDG Flag definition + * @brief WWDG Flag definition + * @{ + */ +#define WWDG_FLAG_EWIF ((uint32_t)WWDG_SR_EWIF) /*!< Early wakeup interrupt flag */ + +/** + * @} + */ + +/** @defgroup WWDG_Prescaler WWDG Prescaler + * @{ + */ +#define WWDG_PRESCALER_1 ((uint32_t)0x00000000) /*!< WWDG counter clock = (PCLK1/4096)/1 */ +#define WWDG_PRESCALER_2 ((uint32_t)WWDG_CFR_WDGTB0) /*!< WWDG counter clock = (PCLK1/4096)/2 */ +#define WWDG_PRESCALER_4 ((uint32_t)WWDG_CFR_WDGTB1) /*!< WWDG counter clock = (PCLK1/4096)/4 */ +#define WWDG_PRESCALER_8 ((uint32_t)WWDG_CFR_WDGTB) /*!< WWDG counter clock = (PCLK1/4096)/8 */ + +#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \ + ((__PRESCALER__) == WWDG_PRESCALER_2) || \ + ((__PRESCALER__) == WWDG_PRESCALER_4) || \ + ((__PRESCALER__) == WWDG_PRESCALER_8)) + +/** + * @} + */ + +/** @defgroup WWDG_Window WWDG Window + * @{ + */ +#define IS_WWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0x7F) + +/** + * @} + */ + +/** @defgroup WWDG_Counter WWDG Counter + * @{ + */ +#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= 0x40) && ((__COUNTER__) <= 0x7F)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup WWDG_Exported_Macros WWDG Exported Macros + * @{ + */ + +/** @brief Reset WWDG handle state + * @param __HANDLE__: WWDG handle + * @retval None + */ +#define __HAL_WWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_WWDG_STATE_RESET) + +/** + * @brief Enables the WWDG peripheral. + * @param __HANDLE__: WWDG handle + * @retval None + */ +#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA) + +/** + * @brief Gets the selected WWDG's flag status. + * @param __HANDLE__: WWDG handle + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag + * @retval The new state of WWDG_FLAG (SET or RESET). + */ +#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) + +/** + * @brief Clears the WWDG's pending flags. + * @param __HANDLE__: WWDG handle + * @param __FLAG__: specifies the flag to clear. + * This parameter can be one of the following values: + * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag + * @retval None + */ +#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__)) + +/** + * @brief Enables the WWDG early wakeup interrupt. + * @param __INTERRUPT__: specifies the interrupt to enable. + * This parameter can be one of the following values: + * @arg WWDG_IT_EWI: Early wakeup interrupt + * @note Once enabled this interrupt cannot be disabled except by a system reset. + * @retval None + */ +#define __HAL_WWDG_ENABLE_IT(__INTERRUPT__) (*(__IO uint32_t *) CFR_BASE |= (__INTERRUPT__)) + +/** @brief Clear the WWDG's interrupt pending bits + * bits to clear the selected interrupt pending bits. + * @param __HANDLE__: WWDG handle + * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag + */ +#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup WWDG_Exported_Functions + * @{ + */ + +/** @addtogroup WWDG_Exported_Functions_Group1 + * @{ + */ +/* Initialization/de-initialization functions **********************************/ +HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg); +HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg); +void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg); +void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg); +void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg); + +/** + * @} + */ + +/** @addtogroup WWDG_Exported_Functions_Group2 + * @{ + */ +/* I/O operation functions ******************************************************/ +HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg); +HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg); +HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter); +void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg); + +/** + * @} + */ + +/** @addtogroup WWDG_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State functions **************************************************/ +HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_WWDG_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c @@ -0,0 +1,430 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal.c + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief HAL module driver. + * This is the common part of the HAL initialization + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The common HAL driver contains a set of generic and common APIs that can be + used by the PPP peripheral drivers and the user to start using the HAL. + [..] + The HAL contains two APIs categories: + (+) HAL Initialization and de-initialization functions + (+) HAL Control functions + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup HAL HAL module driver + * @brief HAL module driver. + * @{ + */ + +#ifdef HAL_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup HAL_Private Constants + * @{ + */ +/** + * @brief STM32F0xx HAL Driver version number V1.1.0 + */ +#define __STM32F0xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32F0xx_HAL_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ +#define __STM32F0xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32F0xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F0xx_HAL_VERSION ((__STM32F0xx_HAL_VERSION_MAIN << 24)\ + |(__STM32F0xx_HAL_VERSION_SUB1 << 16)\ + |(__STM32F0xx_HAL_VERSION_SUB2 << 8 )\ + |(__STM32F0xx_HAL_VERSION_RC)) + +#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup HAL_Private_Variables HAL Private Variables + * @{ + */ +static __IO uint32_t uwTick; +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Functions HAL Exported Functions + * @{ + */ + +/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initializes the Flash interface, the NVIC allocation and initial clock + configuration. It initializes the source of time base also when timeout + is needed and the backup domain when enabled. + (+) de-Initializes common part of the HAL. + (+) Configure The time base source to have 1ms time base with a dedicated + Tick interrupt priority. + (++) Systick timer is used by default as source of time base, but user + can eventually implement his proper time base source (a general purpose + timer for example or other time source), keeping in mind that Time base + duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and + handled in milliseconds basis. + (++) Time base configuration function (HAL_InitTick ()) is called automatically + at the beginning of the program after reset by HAL_Init() or at any time + when clock is configured, by HAL_RCC_ClockConfig(). + (++) Source of time base is configured to generate interrupts at regular + time intervals. Care must be taken if HAL_Delay() is called from a + peripheral ISR process, the Tick interrupt line must have higher priority + (numerically lower) than the peripheral interrupt. Otherwise the caller + ISR process will be blocked. + (++) functions affecting time base configurations are declared as __Weak + to make override possible in case of other implementations in user file. + +@endverbatim + * @{ + */ + +/** + * @brief This function configures the Flash prefetch, + * Configures time base source, NVIC and Low level hardware + * @note This function is called at the beginning of program after reset and before + * the clock configuration + * @note The time base configuration is based on HSI clock when exiting from Reset. + * Once done, time base tick start incrementing. + * In the default implementation,Systick is used as source of time base. + * The tick variable is incremented each 1ms in its ISR. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + /* Configure Flash prefetch */ +#if (PREFETCH_ENABLE != 0) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); +#endif /* PREFETCH_ENABLE */ + + /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ + + HAL_InitTick(TICK_INT_PRIORITY); + + /* Init the low level hardware */ + HAL_MspInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief This function de-Initializes common part of the HAL and stops the source + * of time base. + * @note This function is optional. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DeInit(void) +{ + /* Reset of all peripherals */ + __APB1_FORCE_RESET(); + __APB1_RELEASE_RESET(); + + __APB2_FORCE_RESET(); + __APB2_RELEASE_RESET(); + + __AHB_FORCE_RESET(); + __AHB_RELEASE_RESET(); + + /* De-Init the low level hardware */ + HAL_MspDeInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the MSP. + * @retval None + */ +__weak void HAL_MspInit(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the MSP. + * @retval None + */ +__weak void HAL_MspDeInit(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief This function configures the source of the time base. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Care must be taken if HAL_Delay() is called from a peripheral ISR process, + * The the SysTick interrupt must have higher priority (numerically lower) + * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. + * The function is declared as __Weak to be overwritten in case of other + * implementation in user file. + * @param TickPriority: Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + /*Configure the SysTick to have interrupt in 1ms time basis*/ + HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000); + + /*Configure the SysTick IRQ priority */ + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions + * @brief HAL Control functions + * +@verbatim + =============================================================================== + ##### HAL Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Provide a tick value in millisecond + (+) Provide a blocking delay in millisecond + (+) Suspend the time base source interrupt + (+) Resume the time base source interrupt + (+) Get the HAL API driver version + (+) Get the device identifier + (+) Get the device revision identifier + (+) Enable/Disable Debug module during Sleep mode + (+) Enable/Disable Debug module during STOP mode + (+) Enable/Disable Debug module during STANDBY mode + +@endverbatim + * @{ + */ + +/** + * @brief This function is called to increment a global variable "uwTick" + * used as application time base. + * @note In the default implementation, this variable is incremented each 1ms + * in Systick ISR. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + uwTick++; +} + +/** + * @brief Povides a tick value in millisecond. + * @note The function is declared as __Weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + return uwTick; +} + +/** + * @brief Suspend Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() + * is called, the the SysTick interrupt will be disabled and so Tick increment + * is suspended. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_SuspendTick(void) + +{ + /* Disable SysTick Interrupt */ + SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; + +} + +/** + * @brief Resume Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() + * is called, the the SysTick interrupt will be enabled and so Tick increment + * is resumed. + * The function is declared as __Weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_ResumeTick(void) +{ + /* Enable SysTick Interrupt */ + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; + +} + +/** + * @brief This function provides accurate delay (in milliseconds) based + * on variable incremented. + * @note In the default implementation , SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals where uwTick + * is incremented. + * @note ThiS function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @param Delay: specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(__IO uint32_t Delay) +{ + uint32_t tickstart = 0; + tickstart = HAL_GetTick(); + while((HAL_GetTick() - tickstart) < Delay) + { + } +} + +/** + * @brief This method returns the HAL revision + * @retval version : 0xXYZR (8bits for each decimal, R for RC) + */ +uint32_t HAL_GetHalVersion(void) +{ + return __STM32F0xx_HAL_VERSION; +} + +/** + * @brief Returns the device revision identifier. + * @retval Device revision identifier + */ +uint32_t HAL_GetREVID(void) +{ + return((DBGMCU->IDCODE) >> 16); +} + +/** + * @brief Returns the device identifier. + * @retval Device identifier + */ +uint32_t HAL_GetDEVID(void) +{ + return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); +} + +/** + * @brief Enable the Debug Module during STOP mode + * @retval None + */ +void HAL_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP mode + * @retval None + */ +void HAL_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Enable the Debug Module during STANDBY mode + * @retval None + */ +void HAL_EnableDBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during STANDBY mode + * @retval None + */ +void HAL_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c @@ -0,0 +1,1826 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_adc.c + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the Analog to Digital Convertor (ADC) + * peripheral: + * + Initialization and de-initialization functions + * ++ Initialization and Configuration of ADC + * + Operation functions + * ++ Start, stop, get result of conversions of regular group, + * using 3 possible modes: polling, interruption or DMA. + * + Control functions + * ++ Analog Watchdog configuration + * ++ Channels configuration on regular group + * + State functions + * ++ ADC state machine management + * ++ Interrupts and flags management + * + @verbatim + ============================================================================== + ##### ADC specific features ##### + ============================================================================== + [..] + (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution + + (#) Interrupt generation at the end of regular conversion and in case of + analog watchdog or overrun events. + + (#) Single and continuous conversion modes. + + (#) Scan mode for automatic conversion of channel 0 to channel 'n'. + + (#) Data alignment with in-built data coherency. + + (#) Programmable sampling time. + + (#) ADC conversion group Regular. + + (#) External trigger (timer or EXTI) with configurable polarity. + + (#) DMA request generation for transfer of conversions data of regular group. + + (#) ADC calibration + + (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at + slower speed. + + (#) ADC input range: from Vref minus (connected to Vssa) to Vref plus (connected to + Vdda or to an external voltage reference). + + + ##### How to use this driver ##### + ============================================================================== + [..] + + (#) Enable the ADC interface + (++) As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured + at RCC top level: clock source and clock prescaler. + (++)Two possible clock sources: synchronous clock derived from APB clock + or asynchronous clock derived from ADC dedicated HSI RC oscillator + 14MHz. + (++)Example: + __ADC1_CLK_ENABLE(); (mandatory) + + HI14 enable or let under control of ADC: (optional) + + RCC_OscInitTypeDef RCC_OscInitStructure; + RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14; + RCC_OscInitStructure.HSI14CalibrationValue = RCC_HSI14CALIBRATION_DEFAULT; + RCC_OscInitStructure.HSI14State = RCC_HSI14_ADC_CONTROL; + RCC_OscInitStructure.PLL... (optional if used for system clock) + HAL_RCC_OscConfig(&RCC_OscInitStructure); + + Parameter "HSI14State" must be set either: + - to "...HSI14State = RCC_HSI14_ADC_CONTROL" to let the ADC control + the HSI14 oscillator enable/disable (if not used to supply the main + system clock): feature used if ADC mode LowPowerAutoPowerOff is + enabled. + - to "...HSI14State = RCC_HSI14_ON" to maintain the HSI14 oscillator + always enabled: can be used to supply the main system clock. + + (#) ADC pins configuration + (++) Enable the clock for the ADC GPIOs using the following function: + __GPIOx_CLK_ENABLE(); + (++) Configure these ADC pins in analog mode using HAL_GPIO_Init(); + + (#) Configure the ADC parameters (conversion resolution, data alignment, + continuous mode, ...) using the HAL_ADC_Init() function. + + (#) Activate the ADC peripheral using one of the start functions: + HAL_ADC_Start(), HAL_ADC_Start_IT(), HAL_ADC_Start_DMA(). + + *** Channels configuration to regular group *** + ================================================ + [..] + (+) To configure the ADC regular group features, use + HAL_ADC_Init() and HAL_ADC_ConfigChannel() functions. + (+) To activate the continuous mode, use the HAL_ADC_Init() function. + (+) To read the ADC converted values, use the HAL_ADC_GetValue() function. + + *** DMA for regular configuration *** + ============================================================= + [..] + (+) To enable the DMA mode for regular group, use the + HAL_ADC_Start_DMA() function. + (+) To enable the generation of DMA requests continuously at the end of + the last DMA transfer, use the HAL_ADC_Init() function. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup ADC ADC HAL module driver + * @brief ADC HAL module driver + * @{ + */ + +#ifdef HAL_ADC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup ADC_Private_Constants ADC Private Constants + * @{ + */ + + /* Fixed timeout values for ADC calibration, enable settling time, disable */ + /* settling time. */ + /* Values defined to be higher than worst cases: low clock frequency, */ + /* maximum prescaler. */ + /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */ + /* prescaler 4, sampling time 7.5 ADC clock cycles, resolution 12 bits. */ + /* Unit: ms */ + #define ADC_ENABLE_TIMEOUT ((uint32_t) 2) + #define ADC_DISABLE_TIMEOUT ((uint32_t) 2) + #define ADC_STOP_CONVERSION_TIMEOUT ((uint32_t) 2) + + /* Delay for temperature sensor stabilization time. */ + /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ + /* Delay in CPU cycles, fixed to worst case: maximum CPU frequency 48MHz to */ + /* have the minimum number of CPU cycles to fulfill this delay. */ + #define ADC_TEMPSENSOR_DELAY_CPU_CYCLES ((uint32_t) 480) + + /* Delay for ADC stabilization time. */ + /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */ + /* Delay in CPU cycles, fixed to worst case: maximum CPU frequency 48MHz to */ + /* have the minimum number of CPU cycles to fulfill this delay. */ + #define ADC_STAB_DELAY_CPU_CYCLES ((uint32_t)48) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup ADC_Private_Functions ADC Private Functions + * @{ + */ +static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc); +static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc); +static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc); +static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); +static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); +static void ADC_DMAError(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup ADC_Exported_Functions ADC Exported Functions + * @{ + */ + +/** @defgroup ADC_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the ADC. + (+) De-initialize the ADC +@endverbatim + * @{ + */ + +/** + * @brief Initializes the ADC peripheral and regular group according to + * parameters specified in structure "ADC_InitTypeDef". + * @note As prerequisite, ADC clock must be configured at RCC top level + * depending on both possible clock sources: APB clock of HSI clock. + * See commented example code below that can be copied and uncommented + * into HAL_ADC_MspInit(). + * @note Possibility to update parameters on the fly: + * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when + * coming from ADC state reset. Following calls to this function can + * be used to reconfigure some parameters of ADC_InitTypeDef + * structure on the fly, without modifying MSP configuration. If ADC + * MSP has to be modified again, HAL_ADC_DeInit() must be called + * before HAL_ADC_Init(). + * The setting of these parameters is conditioned to ADC state. + * For parameters constraints, see comments of structure + * "ADC_InitTypeDef". + * @note This function configures the ADC within 2 scopes: scope of entire + * ADC and scope of regular group. For parameters details, see comments + * of structure "ADC_InitTypeDef". + * @param hadc: ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmpHALStatus = HAL_OK; + uint32_t tmpCFGR1 = 0; + + /* Check ADC handle */ + if(hadc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); + assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution)); + assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); + assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); + assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); + assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); + assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); + assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoPowerOff)); + + /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */ + /* at RCC top level depending on both possible clock sources: */ + /* APB clock or HSI clock. */ + /* Refer to header of this file for more details on clock enabling procedure*/ + + /* Actions performed only if ADC is coming from state reset: */ + /* - Initialization of ADC MSP */ + /* - ADC voltage regulator enable */ + if (hadc->State == HAL_ADC_STATE_RESET) + { + /* Init the low level hardware */ + HAL_ADC_MspInit(hadc); + + } + + /* Configuration of ADC parameters if previous preliminary actions are */ + /* correctly completed. */ + /* and if there is no conversion on going on regular group (ADC can be */ + /* enabled anyway, in case of call of this function to update a parameter */ + /* on the fly). */ + if ((hadc->State != HAL_ADC_STATE_ERROR) && + (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) ) + { + /* Initialize the ADC state */ + hadc->State = HAL_ADC_STATE_BUSY; + + /* Parameters update conditioned to ADC state: */ + /* Parameters that can be updated only when ADC is disabled: */ + /* - ADC clock mode */ + /* - ADC clock prescaler */ + if (__HAL_ADC_IS_ENABLED(hadc) == RESET) + { + /* Some parameters of this register are not reset, since they are set */ + /* by other functions and must be kept in case of usage of this */ + /* function on the fly (update of a parameter of ADC_InitTypeDef */ + /* without needing to reconfigure all other ADC groups/channels */ + /* parameters): */ + /* - internal measurement paths: Vbat, temperature sensor, Vref */ + /* (set into HAL_ADC_ConfigChannel() ) */ + + /* Reset configuration of ADC configuration register CFGR2: */ + /* - ADC clock mode: CKMODE */ + hadc->Instance->CFGR2 &= ~(ADC_CFGR2_CKMODE); + + /* Configuration of ADC clock mode: clock source AHB or HSI with */ + /* selectable prescaler */ + hadc->Instance->CFGR2 |= hadc->Init.ClockPrescaler; + } + + /* Configuration of ADC: */ + /* - discontinuous mode */ + /* - LowPowerAutoWait mode */ + /* - LowPowerAutoPowerOff mode */ + /* - continuous conversion mode */ + /* - overrun */ + /* - external trigger to start conversion */ + /* - external trigger polarity */ + /* - data alignment */ + /* - resolution */ + /* - scan direction */ + /* - DMA continuous request */ + hadc->Instance->CFGR1 &= ~( ADC_CFGR1_DISCEN | + ADC_CFGR1_AUTOFF | + ADC_CFGR1_AUTDLY | + ADC_CFGR1_CONT | + ADC_CFGR1_OVRMOD | + ADC_CFGR1_EXTSEL | + ADC_CFGR1_EXTEN | + ADC_CFGR1_ALIGN | + ADC_CFGR1_RES | + ADC_CFGR1_SCANDIR | + ADC_CFGR1_DMACFG ); + + tmpCFGR1 |= (__HAL_ADC_CFGR1_AUTOWAIT(hadc->Init.LowPowerAutoWait) | + __HAL_ADC_CFGR1_AUTOOFF(hadc->Init.LowPowerAutoPowerOff) | + __HAL_ADC_CFGR1_CONTINUOUS(hadc->Init.ContinuousConvMode) | + __HAL_ADC_CFGR1_OVERRUN(hadc->Init.Overrun) | + hadc->Init.DataAlign | + hadc->Init.Resolution | + __HAL_ADC_CFGR1_SCANDIR(hadc->Init.ScanConvMode) | + __HAL_ADC_CFGR1_DMACONTREQ(hadc->Init.DMAContinuousRequests) ); + + /* Enable discontinuous mode only if continuous mode is disabled */ + if ((hadc->Init.DiscontinuousConvMode == ENABLE) && + (hadc->Init.ContinuousConvMode == DISABLE) ) + { + /* Enable discontinuous mode of regular group */ + tmpCFGR1 |= ADC_CFGR1_DISCEN; + } + + /* Enable external trigger if trigger selection is different of software */ + /* start. */ + /* Note: This configuration keeps the hardware feature of parameter */ + /* ExternalTrigConvEdge "trigger edge none" equivalent to */ + /* software start. */ + if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) + { + tmpCFGR1 |= ( hadc->Init.ExternalTrigConv | + hadc->Init.ExternalTrigConvEdge ); + } + + /* Update ADC configuration register with previous settings */ + hadc->Instance->CFGR1 |= tmpCFGR1; + + /* Check back that ADC registers have effectively been configured to */ + /* ensure of no potential problem of ADC core IP clocking. */ + /* Check through register CFGR1 (excluding analog watchdog configuration: */ + /* set into separate dedicated function). */ + if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)) + == tmpCFGR1) + { + /* Set ADC error code to none */ + __HAL_ADC_CLEAR_ERRORCODE(hadc); + + /* Initialize the ADC state */ + hadc->State = HAL_ADC_STATE_READY; + } + else + { + /* Update ADC state machine to error */ + hadc->State = HAL_ADC_STATE_ERROR; + + /* Set ADC error code to ADC IP internal error */ + hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL; + + tmpHALStatus = HAL_ERROR; + } + + } + else + { + /* Update ADC state machine to error */ + hadc->State = HAL_ADC_STATE_ERROR; + + tmpHALStatus = HAL_ERROR; + } + + /* Return function status */ + return tmpHALStatus; +} + + +/** + * @brief Deinitialize the ADC peripheral registers to their default reset + * values, with deinitialization of the ADC MSP. + * @note For devices with several ADCs: reset of ADC common registers is done + * only if all ADCs sharing the same common group are disabled. + * If this is not the case, reset of these common parameters reset is + * bypassed without error reporting: it can be the intended behaviour in + * case of reset of a single ADC while the other ADCs sharing the same + * common group is still running. + * @param hadc: ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmpHALStatus = HAL_OK; + + /* Check ADC handle */ + if(hadc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_BUSY; + + /* Stop potential conversion on going, on regular group */ + tmpHALStatus = ADC_ConversionStop(hadc); + + /* Disable ADC peripheral if conversions are effectively stopped */ + if (tmpHALStatus != HAL_ERROR) + { + /* Disable the ADC peripheral */ + tmpHALStatus = ADC_Disable(hadc); + + /* Check if ADC is effectively disabled */ + if (tmpHALStatus != HAL_ERROR) + { + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_READY; + } + } + + + /* Configuration of ADC parameters if previous preliminary actions are */ + /* correctly completed. */ + if (tmpHALStatus != HAL_ERROR) + { + + /* ========== Reset ADC registers ========== */ + /* Reset register IER */ + __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD | ADC_IT_OVR | + ADC_IT_EOS | ADC_IT_EOC | + ADC_IT_EOSMP | ADC_IT_RDY ) ); + + /* Reset register ISR */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_OVR | + ADC_FLAG_EOS | ADC_FLAG_EOC | + ADC_FLAG_EOSMP | ADC_FLAG_RDY ) ); + + /* Reset register CR */ + /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */ + /* "read-set": no direct reset applicable. */ + + /* Reset register CFGR1 */ + hadc->Instance->CFGR1 &= ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_DISCEN | + ADC_CFGR1_AUTOFF | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD | + ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES | + ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN ); + + /* Reset register CFGR2 */ + /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */ + /* already done above. */ + hadc->Instance->CFGR2 &= ~ADC_CFGR2_CKMODE; + + /* Reset register SMPR */ + hadc->Instance->SMPR &= ~ADC_SMPR_SMP; + + /* Reset register TR1 */ + hadc->Instance->TR &= ~(ADC_TR_HT | ADC_TR_LT); + + /* Reset register CHSELR */ + hadc->Instance->CHSELR &= ~(ADC_CHSELR_CHSEL18 | ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16 | + ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12 | + ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8 | + ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4 | + ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0 ); + + /* Reset register DR */ + /* bits in access mode read only, no direct reset applicable*/ + + /* Reset register CCR */ + ADC->CCR &= ~( ADC_CCR_VBATEN | + ADC_CCR_TSEN | + ADC_CCR_VREFEN ); + + /* ========== Hard reset ADC peripheral ========== */ + /* Performs a global reset of the entire ADC peripheral: ADC state is */ + /* forced to a similar state after device power-on. */ + /* If needed, copy-paste and uncomment the following reset code into */ + /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */ + /* */ + /* __ADC1_FORCE_RESET() */ + /* __ADC1_RELEASE_RESET() */ + + /* DeInit the low level hardware */ + HAL_ADC_MspDeInit(hadc); + + /* Set ADC error code to none */ + __HAL_ADC_CLEAR_ERRORCODE(hadc); + + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_RESET; + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmpHALStatus; +} + + +/** + * @brief Initializes the ADC MSP. + * @param hadc: ADC handle + * @retval None + */ +__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) +{ + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_MspInit must be implemented in the user file. + */ +} + +/** + * @brief DeInitializes the ADC MSP. + * @param hadc: ADC handle + * @retval None + */ +__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) +{ + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_MspDeInit must be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup ADC_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Start conversion of regular group. + (+) Stop conversion of regular group. + (+) Poll for conversion complete on regular group. + (+) Poll for conversion event. + (+) Get result of regular channel conversion. + (+) Start conversion of regular group and enable interruptions. + (+) Stop conversion of regular group and disable interruptions. + (+) Handle ADC interrupt request + (+) Start conversion of regular group and enable DMA transfer. + (+) Stop conversion of regular group and disable ADC DMA transfer. +@endverbatim + * @{ + */ + +/** + * @brief Enables ADC, starts conversion of regular group. + * Interruptions enabled in this function: None. + * @param hadc: ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmpHALStatus = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Enable the ADC peripheral */ + /* If low power mode AutoPowerOff is enabled, power-on/off phases are */ + /* performed automatically by hardware. */ + if (hadc->Init.LowPowerAutoPowerOff != ENABLE) + { + tmpHALStatus = ADC_Enable(hadc); + } + + /* Start conversion if ADC is effectively enabled */ + if (tmpHALStatus != HAL_ERROR) + { + /* State machine update: Change ADC state */ + hadc->State = HAL_ADC_STATE_BUSY_REG; + + /* Set ADC error code to none */ + __HAL_ADC_CLEAR_ERRORCODE(hadc); + + /* Clear regular group conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); + + /* Enable conversion of regular group. */ + /* If software start has been selected, conversion starts immediately. */ + /* If external trigger has been selected, conversion will start at next */ + /* trigger event. */ + hadc->Instance->CR |= ADC_CR_ADSTART; + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmpHALStatus; +} + +/** + * @brief Stop ADC conversion of regular group, disable ADC peripheral. + * @param hadc: ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmpHALStatus = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* 1. Stop potential conversion on going, on regular group */ + tmpHALStatus = ADC_ConversionStop(hadc); + + /* Disable ADC peripheral if conversions are effectively stopped */ + if (tmpHALStatus != HAL_ERROR) + { + /* 2. Disable the ADC peripheral */ + tmpHALStatus = ADC_Disable(hadc); + + /* Check if ADC is effectively disabled */ + if (tmpHALStatus != HAL_ERROR) + { + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_READY; + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmpHALStatus; +} + +/** + * @brief Wait for regular group conversion to be completed. + * @param hadc: ADC handle + * @param Timeout: Timeout value in millisecond. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) +{ + uint32_t tickstart; + uint32_t tmp_Flag_EOC; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* If end of conversion selected to end of sequence */ + if (hadc->Init.EOCSelection == EOC_SEQ_CONV) + { + tmp_Flag_EOC = ADC_FLAG_EOS; + } + /* If end of conversion selected to end of each conversion */ + else /* EOC_SINGLE_CONV */ + { + tmp_Flag_EOC = (ADC_FLAG_EOC | ADC_FLAG_EOS); + } + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait until End of Conversion flag is raised */ + while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC)) + { + /* Check if timeout is disabled (set to infinite wait) */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + { + /* Update ADC state machine to timeout */ + hadc->State = HAL_ADC_STATE_TIMEOUT; + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_ERROR; + } + } + } + + /* Clear end of conversion flag of regular group if low power feature */ + /* "LowPowerAutoWait " is disabled, to not interfere with this feature */ + /* until data register is read using function HAL_ADC_GetValue(). */ + if (hadc->Init.LowPowerAutoWait == DISABLE) + { + /* Clear regular group conversion flag */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); + } + + /* Update state machine on conversion status if not in error state */ + if(hadc->State != HAL_ADC_STATE_ERROR) + { + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_EOC_REG; + } + + /* Return ADC state */ + return HAL_OK; +} + +/** + * @brief Poll for conversion event. + * @param hadc: ADC handle + * @param EventType: the ADC event type. + * This parameter can be one of the following values: + * @arg AWD_EVENT: ADC Analog watchdog event + * @arg OVR_EVENT: ADC Overrun event + * @param Timeout: Timeout value in millisecond. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) +{ + uint32_t tickstart=0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_EVENT_TYPE(EventType)); + + tickstart = HAL_GetTick(); + + /* Check selected event flag */ + while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET) + { + /* Check if timeout is disabled (set to infinite wait) */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + { + /* Update ADC state machine to timeout */ + hadc->State = HAL_ADC_STATE_TIMEOUT; + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_ERROR; + } + } + } + + switch(EventType) + { + /* Analog watchdog (level out of window) event */ + case AWD_EVENT: + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_AWD; + + /* Clear ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); + break; + + /* Overrun event */ + default: /* Case OVR_EVENT */ + /* If overrun is set to overwrite previous data, overrun event is not */ + /* considered as an error. */ + /* (cf ref manual "Managing conversions without using the DMA and without */ + /* overrun ") */ + if (hadc->Init.Overrun == OVR_DATA_PRESERVED) + { + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_ERROR; + + /* Set ADC error code to overrun */ + hadc->ErrorCode |= HAL_ADC_ERROR_OVR; + } + + /* Clear ADC Overrun flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); + break; + } + + /* Return ADC state */ + return HAL_OK; +} + +/** + * @brief Enables ADC, starts conversion of regular group with interruption. + * Interruptions enabled in this function: EOC (end of conversion), + * overrun. + * Each of these interruptions has its dedicated callback function. + * @param hadc: ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmpHALStatus = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Enable the ADC peripheral */ + /* If low power mode AutoPowerOff is enabled, power-on/off phases are */ + /* performed automatically by hardware. */ + if (hadc->Init.LowPowerAutoPowerOff != ENABLE) + { + tmpHALStatus = ADC_Enable(hadc); + } + + /* Start conversion if ADC is effectively enabled */ + if (tmpHALStatus != HAL_ERROR) + { + /* State machine update: Change ADC state */ + hadc->State = HAL_ADC_STATE_BUSY_REG; + + /* Set ADC error code to none */ + __HAL_ADC_CLEAR_ERRORCODE(hadc); + + /* Clear regular group conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); + + /* Enable ADC end of conversion interrupt */ + /* Enable ADC overrun interrupt */ + switch(hadc->Init.EOCSelection) + { + case EOC_SEQ_CONV: + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); + __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOS | ADC_IT_OVR)); + break; + /* case EOC_SINGLE_CONV */ + default: + __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); + break; + } + + /* Enable conversion of regular group. */ + /* If software start has been selected, conversion starts immediately. */ + /* If external trigger has been selected, conversion will start at next */ + /* trigger event. */ + hadc->Instance->CR |= ADC_CR_ADSTART; + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmpHALStatus; +} + + +/** + * @brief Stop ADC conversion of regular group, disable interruption of + * end-of-conversion, disable ADC peripheral. + * @param hadc: ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmpHALStatus = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* 1. Stop potential conversion on going, on regular group */ + tmpHALStatus = ADC_ConversionStop(hadc); + + /* Disable ADC peripheral if conversions are effectively stopped */ + if (tmpHALStatus != HAL_ERROR) + { + /* Disable ADC end of conversion interrupt for regular group */ + /* Disable ADC overrun interrupt */ + __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); + + /* 2. Disable the ADC peripheral */ + tmpHALStatus = ADC_Disable(hadc); + + /* Check if ADC is effectively disabled */ + if (tmpHALStatus != HAL_ERROR) + { + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_READY; + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmpHALStatus; +} + +/** + * @brief Enables ADC, starts conversion of regular group and transfers result + * through DMA. + * Interruptions enabled in this function: + * overrun, DMA half transfer, DMA transfer complete. + * Each of these interruptions has its dedicated callback function. + * @param hadc: ADC handle + * @param pData: The destination Buffer address. + * @param Length: The length of data to be transferred from ADC peripheral to memory. + * @retval None + */ +HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) +{ + HAL_StatusTypeDef tmpHALStatus = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Enable the ADC peripheral */ + /* If low power mode AutoPowerOff is enabled, power-on/off phases are */ + /* performed automatically by hardware. */ + if (hadc->Init.LowPowerAutoPowerOff != ENABLE) + { + tmpHALStatus = ADC_Enable(hadc); + } + + /* Start conversion if ADC is effectively enabled */ + if (tmpHALStatus != HAL_ERROR) + { + /* State machine update: Change ADC state */ + hadc->State = HAL_ADC_STATE_BUSY_REG; + + /* Set ADC error code to none */ + __HAL_ADC_CLEAR_ERRORCODE(hadc); + + + /* Set the DMA transfer complete callback */ + hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; + + /* Set the DMA half transfer complete callback */ + hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; + + /* Set the DMA error callback */ + hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; + + + /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ + /* start (in case of SW start): */ + + /* Clear regular group conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC */ + /* operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); + + /* Enable ADC overrun interrupt */ + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); + + /* Enable ADC DMA mode */ + hadc->Instance->CFGR1 |= ADC_CFGR1_DMAEN; + + /* Start the DMA channel */ + HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); + + /* Enable conversion of regular group. */ + /* If software start has been selected, conversion starts immediately. */ + /* If external trigger has been selected, conversion will start at next */ + /* trigger event. */ + hadc->Instance->CR |= ADC_CR_ADSTART; + } + + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmpHALStatus; +} + +/** + * @brief Stop ADC conversion of regular group, disable ADC DMA transfer, disable + * ADC peripheral. + * Each of these interruptions has its dedicated callback function. + * @param hadc: ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmpHALStatus = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* 1. Stop potential conversion on going, on regular group */ + tmpHALStatus = ADC_ConversionStop(hadc); + + /* Disable ADC peripheral if conversions are effectively stopped */ + if (tmpHALStatus != HAL_ERROR) + { + /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */ + hadc->Instance->CFGR1 &= ~ADC_CFGR1_DMAEN; + + /* Disable the DMA channel (in case of DMA in circular mode or stop while */ + /* while DMA transfer is on going) */ + tmpHALStatus = HAL_DMA_Abort(hadc->DMA_Handle); + + /* Check if DMA channel effectively disabled */ + if (tmpHALStatus != HAL_OK) + { + /* Update ADC state machine to error */ + hadc->State = HAL_ADC_STATE_ERROR; + } + + /* Disable ADC overrun interrupt */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); + + /* 2. Disable the ADC peripheral */ + /* Update "tmpHALStatus" only if DMA channel disabling passed, to keep in */ + /* memory a potential failing status. */ + if (tmpHALStatus == HAL_OK) + { + tmpHALStatus = ADC_Disable(hadc); + } + else + { + ADC_Disable(hadc); + } + + /* Check if ADC is effectively disabled */ + if (tmpHALStatus == HAL_OK) + { + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_READY; + } + + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmpHALStatus; +} + +/** + * @brief Get ADC regular group conversion result. + * @param hadc: ADC handle + * @retval Converted value + */ +uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Note: EOC flag is automatically cleared by hardware when reading */ + /* register DR. Additionally, clear flag EOS by software. */ + + /* Clear regular group conversion flag */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS) ); + + /* Return ADC converted value */ + return hadc->Instance->DR; +} + +/** + * @brief DMA transfer complete callback. + * @param hdma: pointer to DMA handle. + * @retval None + */ +static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) +{ + /* Retrieve ADC handle corresponding to current DMA handle */ + ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Update state machine on conversion status if not in error state */ + if(hadc->State != HAL_ADC_STATE_ERROR) + { + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_EOC_REG; + } + + /* Conversion complete callback */ + HAL_ADC_ConvCpltCallback(hadc); +} + +/** + * @brief DMA half transfer complete callback. + * @param hdma: pointer to DMA handle. + * @retval None + */ +static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) +{ + /* Retrieve ADC handle corresponding to current DMA handle */ + ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Half conversion callback */ + HAL_ADC_ConvHalfCpltCallback(hadc); +} + +/** + * @brief DMA error callback + * @param hdma: pointer to DMA handle. + * @retval None + */ +static void ADC_DMAError(DMA_HandleTypeDef *hdma) +{ + /* Retrieve ADC handle corresponding to current DMA handle */ + ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_ERROR; + + /* Set ADC error code to DMA error */ + hadc->ErrorCode |= HAL_ADC_ERROR_DMA; + + /* Error callback */ + HAL_ADC_ErrorCallback(hadc); +} + +/** + * @brief Handles ADC interrupt request. + * @param hadc: ADC handle + * @retval None + */ +void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); + assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); + + /* ========== Check End of Conversion flag for regular group ========== */ + if( (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) || + (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOS)) ) + { + /* Update state machine on conversion status if not in error state */ + if(hadc->State != HAL_ADC_STATE_ERROR) + { + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_EOC_REG; + } + + /* Disable interruption if no further conversion upcoming by regular */ + /* external trigger or by continuous mode, */ + /* and if scan sequence if completed. */ + if(__HAL_ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) ) + { + /* If End of Sequence is reached, disable interrupts */ + if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) + { + /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ + /* ADSTART==0 (no conversion on going) */ + if (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) + { + /* Disable ADC end of sequence conversion interrupt */ + /* Note: Overrun interrupt was enabled with EOC interrupt in */ + /* HAL_Start_IT(), but is not disabled here because can be used */ + /* by overrun IRQ process below. */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); + } + else + { + /* Change ADC state to error state */ + hadc->State = HAL_ADC_STATE_ERROR; + + /* Set ADC error code to ADC IP internal error */ + hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL; + } + } + } + + /* Conversion complete callback */ + /* Note: into callback, to determine if conversion has been triggered */ + /* from EOC or EOS, possibility to use: */ + /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */ + HAL_ADC_ConvCpltCallback(hadc); + + + /* Clear regular group conversion flag */ + /* Note: in case of overrun set to OVR_DATA_PRESERVED, end of conversion */ + /* flags clear induces the release of the preserved data. */ + /* Therefore, if the preserved data value is needed, it must be */ + /* read preliminarily into HAL_ADC_ConvCpltCallback(). */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS) ); + } + + /* ========== Check Analog watchdog flags ========== */ + if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD)) + { + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_AWD; + + /* Clear ADC Analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); + + /* Level out of window callback */ + HAL_ADC_LevelOutOfWindowCallback(hadc); + } + + + /* ========== Check Overrun flag ========== */ + if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR)) + { + /* If overrun is set to overwrite previous data (default setting), */ + /* overrun event is not considered as an error. */ + /* (cf ref manual "Managing conversions without using the DMA and without */ + /* overrun ") */ + /* Exception for usage with DMA overrun event always considered as an */ + /* error. */ + if ((hadc->Init.Overrun == OVR_DATA_PRESERVED) || + HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN) ) + { + /* Change ADC state to error state */ + hadc->State = HAL_ADC_STATE_ERROR; + + /* Set ADC error code to overrun */ + hadc->ErrorCode |= HAL_ADC_ERROR_OVR; + + /* Error callback */ + HAL_ADC_ErrorCallback(hadc); + } + + /* Clear the Overrun flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); + } + +} + + +/** + * @brief Conversion complete callback in non blocking mode + * @param hadc: ADC handle + * @retval None + */ +__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) +{ + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_ConvCpltCallback must be implemented in the user file. + */ +} + +/** + * @brief Conversion DMA half-transfer callback in non blocking mode + * @param hadc: ADC handle + * @retval None + */ +__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) +{ + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. + */ +} + +/** + * @brief Analog watchdog callback in non blocking mode. + * @param hadc: ADC handle + * @retval None + */ +__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) +{ + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_LevelOoutOfWindowCallback must be implemented in the user file. + */ +} + +/** + * @brief ADC error callback in non blocking mode + * (ADC conversion with interruption or transfer by DMA) + * @param hadc: ADC handle + * @retval None + */ +__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) +{ + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_ErrorCallback must be implemented in the user file. + */ +} + + +/** + * @} + */ + +/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure channels on regular group + (+) Configure the analog watchdog + +@endverbatim + * @{ + */ + +/** + * @brief Configures the the selected channel to be linked to the regular + * group. + * @note In case of usage of internal measurement channels: + * VrefInt/Vbat/TempSensor. + * Sampling time constraints must be respected (sampling time can be + * adjusted in function of ADC clock frequency and sampling time + * setting). + * Refer to device datasheet for timings values, parameters TS_vrefint, + * TS_vbat, TS_temp (values rough order: 5us to 17us). + * These internal paths can be be disabled using function + * HAL_ADC_DeInit(). + * @note Possibility to update parameters on the fly: + * This function initializes channel into regular group, following + * calls to this function can be used to reconfigure some parameters + * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting + * the ADC. + * The setting of these parameters is conditioned to ADC state. + * For parameters constraints, see comments of structure + * "ADC_ChannelConfTypeDef". + * @param hadc: ADC handle + * @param sConfig: Structure of ADC channel for regular group. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) +{ + HAL_StatusTypeDef tmpHALStatus = HAL_OK; + __IO uint32_t wait_loop_index = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_CHANNEL(sConfig->Channel)); + assert_param(IS_ADC_RANK(sConfig->Rank)); + assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Parameters update conditioned to ADC state: */ + /* Parameters that can be updated when ADC is disabled or enabled without */ + /* conversion on going on regular group: */ + /* - Channel number */ + /* - Channel sampling time */ + /* - Management of internal measurement channels: Vbat/VrefInt/TempSensor */ + if (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) + { + /* Configure channel: depending on rank setting, add it or remove it from */ + /* ADC conversion sequencer. */ + if (sConfig->Rank != ADC_RANK_NONE) + { + /* Regular sequence configuration */ + /* Set the channel selection register from the selected channel */ + hadc->Instance->CHSELR |= __HAL_ADC_CHSELR_CHANNEL(sConfig->Channel); + + /* Channel sampling time configuration */ + /* Modify sampling time if needed (not needed in case of reoccurrence */ + /* for several channels programmed consecutively into the sequencer) */ + if (sConfig->SamplingTime != __HAL_ADC_GET_SAMPLINGTIME(hadc)) + { + /* Channel sampling time configuration */ + /* Clear the old sample time */ + hadc->Instance->SMPR &= ~(ADC_SMPR_SMP); + + /* Set the new sample time */ + hadc->Instance->SMPR |= (sConfig->SamplingTime); + } + + /* Management of internal measurement channels: Vbat/VrefInt/TempSensor */ + /* internal measurement paths enable: If internal channel selected, */ + /* enable dedicated internal buffers and path. */ + /* Note: these internal measurement paths can be disabled using */ + /* HAL_ADC_DeInit() or removing the channel from sequencer with */ + /* channel configuration parameter "Rank". */ + + /* If Channel_16 is selected, enable Temp. sensor measurement path. */ + if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) + { + ADC->CCR |= ADC_CCR_TSEN; + + /* Delay for temperature sensor stabilization time */ + while(wait_loop_index < ADC_TEMPSENSOR_DELAY_CPU_CYCLES) + { + wait_loop_index++; + } + } + /* If Channel_17 is selected, enable VBAT measurement path. */ + else if (sConfig->Channel == ADC_CHANNEL_VBAT) + { + ADC->CCR |= ADC_CCR_VBATEN; + } + /* If Channel_18 is selected, enable VREFINT measurement path. */ + else if (sConfig->Channel == ADC_CHANNEL_VREFINT) + { + ADC->CCR |= ADC_CCR_VREFEN; + } + + } + else + { + /* Regular sequence configuration */ + /* Reset the channel selection register from the selected channel */ + hadc->Instance->CHSELR &= ~__HAL_ADC_CHSELR_CHANNEL(sConfig->Channel); + + /* Management of internal measurement channels: Vbat/VrefInt/TempSensor */ + /* internal measurement paths disable: If internal channel selected, */ + /* disable dedicated internal buffers and path. */ + + /* If Channel_16 is selected, disable Temp. sensor measurement path. */ + if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) + { + ADC->CCR &= ~ADC_CCR_TSEN; + } + /* If Channel_17 is selected, disable VBAT measurement path. */ + else if (sConfig->Channel == ADC_CHANNEL_VBAT) + { + ADC->CCR &= ~ADC_CCR_VBATEN; + } + /* If Channel_18 is selected, disable VREFINT measurement path. */ + else if (sConfig->Channel == ADC_CHANNEL_VREFINT) + { + ADC->CCR &= ~ADC_CCR_VREFEN; + } + } + + } + + + /* If a conversion is on going on regular group, no update on regular */ + /* channel could be done on neither of the channel configuration structure */ + /* parameters. */ + else + { + /* Update ADC state machine to error */ + hadc->State = HAL_ADC_STATE_ERROR; + + tmpHALStatus = HAL_ERROR; + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmpHALStatus; +} + + +/** + * @brief Configures the analog watchdog. + * @note Possibility to update parameters on the fly: + * This function initializes the selected analog watchdog, following + * calls to this function can be used to reconfigure some parameters + * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without reseting + * the ADC. + * The setting of these parameters is conditioned to ADC state. + * For parameters constraints, see comments of structure + * "ADC_AnalogWDGConfTypeDef". + * @param hadc: ADC handle + * @param AnalogWDGConfig: Structure of ADC analog watchdog configuration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) +{ + HAL_StatusTypeDef tmpHALStatus = HAL_OK; + + uint32_t tmpAWDHighThresholdShifted; + uint32_t tmpAWDLowThresholdShifted; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); + assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); + + /* Verify if threshold is within the selected ADC resolution */ + assert_param(IS_ADC_RANGE(__HAL_ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold)); + assert_param(IS_ADC_RANGE(__HAL_ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Parameters update conditioned to ADC state: */ + /* Parameters that can be updated when ADC is disabled or enabled without */ + /* conversion on going on regular group: */ + /* - Analog watchdog channels */ + /* - Analog watchdog thresholds */ + if (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) + { + /* Configuration of analog watchdog: */ + /* - Set the analog watchdog enable mode: one or overall group of */ + /* channels. */ + /* - Set the Analog watchdog channel (is not used if watchdog */ + /* mode "all channels": ADC_CFGR_AWD1SGL=0). */ + hadc->Instance->CFGR1 &= ~( ADC_CFGR1_AWDSGL | + ADC_CFGR1_AWDEN | + ADC_CFGR1_AWDCH ); + + hadc->Instance->CFGR1 |= ( AnalogWDGConfig->WatchdogMode | + __HAL_ADC_CFGR_AWDCH(AnalogWDGConfig->Channel) ); + + /* Shift the offset in function of the selected ADC resolution: Thresholds*/ + /* have to be left-aligned on bit 11, the LSB (right bits) are set to 0 */ + tmpAWDHighThresholdShifted = __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold); + tmpAWDLowThresholdShifted = __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold); + + /* Set the high and low thresholds */ + hadc->Instance->TR &= ~(ADC_TR_HT | ADC_TR_LT); + hadc->Instance->TR |= ( __HAL_ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) | + tmpAWDLowThresholdShifted ); + + /* Clear the ADC Analog watchdog flag (in case of let enabled by */ + /* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */ + /* or HAL_ADC_PollForEvent(). */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_IT_AWD); + + /* Configure ADC Analog watchdog interrupt */ + if(AnalogWDGConfig->ITMode == ENABLE) + { + /* Enable the ADC Analog watchdog interrupt */ + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD); + } + else + { + /* Disable the ADC Analog watchdog interrupt */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD); + } + + } + /* If a conversion is on going on regular group, no update could be done */ + /* on neither of the AWD configuration structure parameters. */ + else + { + /* Update ADC state machine to error */ + hadc->State = HAL_ADC_STATE_ERROR; + + tmpHALStatus = HAL_ERROR; + } + + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmpHALStatus; +} + + +/** + * @} + */ + + +/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions to get in run-time the status of the + peripheral. + (+) Check the ADC state + (+) Check the ADC error code + +@endverbatim + * @{ + */ + +/** + * @brief return the ADC state + * @param hadc: ADC handle + * @retval HAL state + */ +HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Return ADC state */ + return hadc->State; +} + +/** + * @brief Return the ADC error code + * @param hadc: ADC handle + * @retval ADC Error Code + */ +uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) +{ + return hadc->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup ADC_Private_Functions ADC Private Functions + * @{ + */ + +/** + * @brief Enable the selected ADC. + * @note Prerequisite condition to use this function: ADC must be disabled + * and voltage regulator must be enabled (done into HAL_ADC_Init()). + * @param hadc: ADC handle + * @retval HAL status. + */ +static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) +{ + uint32_t tickstart = 0; + __IO uint32_t wait_loop_index = 0; + + /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ + /* enabling phase not yet completed: flag ADC ready not yet set). */ + /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ + /* causes: ADC clock not running, ...). */ + if (__HAL_ADC_IS_ENABLED(hadc) == RESET) + { + /* Check if conditions to enable the ADC are fulfilled */ + if (__HAL_ADC_ENABLING_CONDITIONS(hadc) == RESET) + { + /* Update ADC state machine to error */ + hadc->State = HAL_ADC_STATE_ERROR; + + /* Set ADC error code to ADC IP internal error */ + hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL; + + return HAL_ERROR; + } + + /* Enable the ADC peripheral */ + __HAL_ADC_ENABLE(hadc); + + /* Delay for ADC stabilization time. */ + /* Delay fixed to worst case: maximum CPU frequency */ + while(wait_loop_index < ADC_STAB_DELAY_CPU_CYCLES) + { + wait_loop_index++; + } + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait for ADC effectively enabled */ + while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET) + { + if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) + { + /* Update ADC state machine to error */ + hadc->State = HAL_ADC_STATE_ERROR; + + /* Set ADC error code to ADC IP internal error */ + hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL; + + return HAL_ERROR; + } + } + + } + + /* Return HAL status */ + return HAL_OK; +} + +/** + * @brief Disable the selected ADC. + * @note Prerequisite condition to use this function: ADC conversions must be + * stopped. + * @param hadc: ADC handle + * @retval HAL status. + */ +static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) +{ + uint32_t tickstart = 0; + + /* Verification if ADC is not already disabled: */ + /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ + /* disabled. */ + if (__HAL_ADC_IS_ENABLED(hadc) != RESET ) + { + /* Check if conditions to disable the ADC are fulfilled */ + if (__HAL_ADC_DISABLING_CONDITIONS(hadc) != RESET) + { + /* Disable the ADC peripheral */ + __HAL_ADC_DISABLE(hadc); + } + else + { + /* Update ADC state machine to error */ + hadc->State = HAL_ADC_STATE_ERROR; + + /* Set ADC error code to ADC IP internal error */ + hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL; + + return HAL_ERROR; + } + + /* Wait for ADC effectively disabled */ + tickstart = HAL_GetTick(); + + while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN)) + { + if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) + { + /* Update ADC state machine to error */ + hadc->State = HAL_ADC_STATE_ERROR; + + /* Set ADC error code to ADC IP internal error */ + hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL; + + return HAL_ERROR; + } + } + } + + /* Return HAL status */ + return HAL_OK; +} + + +/** + * @brief Stop ADC conversion. + * @note Prerequisite condition to use this function: ADC conversions must be + * stopped to disable the ADC. + * @param hadc: ADC handle + * @retval HAL status. + */ +static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc) +{ + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Verification if ADC is not already stopped on regular group to bypass */ + /* this function if not needed. */ + if (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(hadc)) + { + + /* Stop potential conversion on going on regular group */ + /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */ + if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) && + HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) ) + { + /* Stop conversions on regular group */ + hadc->Instance->CR |= ADC_CR_ADSTP; + } + + /* Wait for conversion effectively stopped */ + tickstart = HAL_GetTick(); + + while((hadc->Instance->CR & ADC_CR_ADSTART) != RESET) + { + if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) + { + /* Update ADC state machine to error */ + hadc->State = HAL_ADC_STATE_ERROR; + + /* Set ADC error code to ADC IP internal error */ + hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL; + + return HAL_ERROR; + } + } + + } + + /* Return HAL status */ + return HAL_OK; +} + +/** + * @} + */ + +#endif /* HAL_ADC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.c b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.c new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.c @@ -0,0 +1,265 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_adc_ex.c + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the Analog to Digital Convertor (ADC) + * peripheral: + * + Operation functions + * ++ Calibration (ADC automatic self-calibration) + * + @verbatim + ============================================================================== + ##### ADC specific features ##### + ============================================================================== + [..] + (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution + + (#) Interrupt generation at the end of regular conversion and in case of + analog watchdog or overrun events. + + (#) Single and continuous conversion modes. + + (#) Scan mode for automatic conversion of channel 0 to channel 'n'. + + (#) Data alignment with in-built data coherency. + + (#) Programmable sampling time. + + (#) ADC conversion group Regular. + + (#) External trigger (timer or EXTI) with configurable polarity. + + (#) DMA request generation for transfer of conversions data of regular group. + + (#) ADC calibration + + (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at + slower speed. + + (#) ADC input range: from Vref minud (connected to Vssa) to Vref plus(connected to + Vdda or to an external voltage reference). + + + ##### How to use this driver ##### + ============================================================================== + [..] + + (#) Enable the ADC interface + As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured + at RCC top level: clock source and clock prescaler. + Two possible clock sources: synchronous clock derived from APB clock + or asynchronous clock derived from ADC dedicated HSI RC oscillator + 14MHz. + Example: + __ADC1_CLK_ENABLE(); (mandatory) + + HI14 enable or let under control of ADC: (optional) + + RCC_OscInitTypeDef RCC_OscInitStructure; + RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14; + RCC_OscInitStructure.HSI14CalibrationValue = RCC_HSI14CALIBRATION_DEFAULT; + RCC_OscInitStructure.HSI14State = RCC_HSI14_ADC_CONTROL; + RCC_OscInitStructure.PLL... (optional if used for system clock) + HAL_RCC_OscConfig(&RCC_OscInitStructure); + + Parameter "HSI14State" must be set either: + - to "...HSI14State = RCC_HSI14_ADC_CONTROL" to let the ADC control + the HSI14 oscillator enable/disable (if not used to supply the main + system clock): feature used if ADC mode LowPowerAutoPowerOff is + enabled. + - to "...HSI14State = RCC_HSI14_ON" to maintain the HSI14 oscillator + always enabled: can be used to supply the main system clock. + + (#) ADC pins configuration + (++) Enable the clock for the ADC GPIOs using the following function: + __GPIOx_CLK_ENABLE(); + (++) Configure these ADC pins in analog mode using HAL_GPIO_Init(); + + (#) Configure the ADC parameters (conversion resolution, data alignment, + continuous mode, ...) using the HAL_ADC_Init() function. + + (#) Activate the ADC peripheral using one of the start functions: + HAL_ADC_Start(), HAL_ADC_Start_IT(), HAL_ADC_Start_DMA(). + + *** Regular channels group configuration *** + ============================================ + [..] + (+) To configure the ADC regular channels group features, use + HAL_ADC_Init() and HAL_ADC_ConfigChannel() functions. + (+) To activate the continuous mode, use the HAL_ADC_Init() function. + (+) To read the ADC converted values, use the HAL_ADC_GetValue() function. + + *** DMA for Regular channels group features configuration *** + ============================================================= + [..] + (+) To enable the DMA mode for regular channels group, use the + HAL_ADC_Start_DMA() function. + (+) To enable the generation of DMA requests continuously at the end of + the last DMA transfer, use the HAL_ADC_Init() function. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup ADCEx ADCEx Extended HAL Module Driver + * @brief ADC HAL module driver + * @{ + */ + +#ifdef HAL_ADC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup ADCEx_Private_Constants ADCEx Private Constants + * @{ + */ + +/* Fixed timeout values for ADC calibration, enable settling time, disable */ + /* settling time. */ + /* Values defined to be higher than worst cases: low clock frequency, */ + /* maximum prescaler. */ + /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */ + /* prescaler 4. */ + /* Unit: ms */ + #define ADC_DISABLE_TIMEOUT 2 + #define ADC_CALIBRATION_TIMEOUT 2 +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup ADCEx_Exported_Functions ADCEx Exported Functions + * @{ + */ + +/** @defgroup ADCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions + * @brief Extended Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Perform the ADC calibration. +@endverbatim + * @{ + */ + +/** + * @brief Perform an ADC automatic self-calibration + * Calibration prerequisite: ADC must be disabled (execute this + * function before HAL_ADC_Start() or after HAL_ADC_Stop() ). + * @note Calibration factor can be read after calibration, using function + * HAL_ADC_GetValue() (value on 7 bits: from DR[6;0]). + * @param hadc: ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmpHALStatus = HAL_OK; + uint32_t tickstart=0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Calibration prerequisite: ADC must be disabled. */ + if (__HAL_ADC_IS_ENABLED(hadc) == RESET ) + { + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_READY; + + /* Start ADC calibration */ + hadc->Instance->CR |= ADC_CR_ADCAL; + + tickstart = HAL_GetTick(); + + /* Wait for calibration completion */ + while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADCAL)) + { + if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) + { + /* Update ADC state machine to error */ + hadc->State = HAL_ADC_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_ERROR; + } + } + } + else + { + /* Update ADC state machine to error */ + hadc->State = HAL_ADC_STATE_ERROR; + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmpHALStatus; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_ADC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c @@ -0,0 +1,1399 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_can.c + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief CAN HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Controller Area Network (CAN) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Error functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the CAN controller interface clock using __CAN_CLK_ENABLE(); + + (#) CAN pins configuration + (++) Enable the clock for the CAN GPIOs using the following function: + __GPIOx_CLK_ENABLE(); + (++) Connect and configure the involved CAN pins to AF9 using the + following function HAL_GPIO_Init(); + + (#) Initialise and configure the CAN using HAL_CAN_Init() function. + + (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function. + + (#) Receive a CAN frame using HAL_CAN_Receive() function. + + *** Polling mode IO operation *** + ================================= + [..] + (+) Start the CAN peripheral transmission and wait the end of this operation + using HAL_CAN_Transmit(), at this stage user can specify the value of timeout + according to his end application + (+) Start the CAN peripheral reception and wait the end of this operation + using HAL_CAN_Receive(), at this stage user can specify the value of timeout + according to his end application + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT() + (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT() + (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine + (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can + add his own code by customization of function pointer HAL_CAN_TxCpltCallback + (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_CAN_ErrorCallback + + *** CAN HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in CAN HAL driver. + + (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts + (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts + (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled + (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags + (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status + + [..] + (@) You can refer to the CAN HAL driver header file for more useful macros + + @endverbatim + + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup CAN CAN HAL Module Driver + * @brief CAN driver modules + * @{ + */ + +#ifdef HAL_CAN_MODULE_ENABLED + +#if defined(STM32F072xB) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F091xC) || defined(STM32F098xx) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup CAN_Private_Constants CAN Private Constants + * @{ + */ +#define HAL_CAN_DEFAULT_TIMEOUT 10 +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup CAN_Private_Functions CAN Private Functions + * @{ + */ +static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber); +static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup CAN_Exported_Functions CAN Exported Functions + * @{ + */ + +/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the CAN. + (+) De-initialize the CAN. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_InitStruct. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) +{ + uint32_t status = CAN_INITSTATUS_FAILED; /* Default init status */ + uint32_t tickstart = 0; + + /* Check CAN handle */ + if(hcan == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP)); + assert_param(IS_CAN_MODE(hcan->Init.Mode)); + assert_param(IS_CAN_SJW(hcan->Init.SJW)); + assert_param(IS_CAN_BS1(hcan->Init.BS1)); + assert_param(IS_CAN_BS2(hcan->Init.BS2)); + assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler)); + + if(hcan->State == HAL_CAN_STATE_RESET) + { + /* Init the low level hardware */ + HAL_CAN_MspInit(hcan); + } + + /* Initialize the CAN state*/ + hcan->State = HAL_CAN_STATE_BUSY; + + /* Exit from sleep mode */ + hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP); + + /* Request initialisation */ + hcan->Instance->MCR |= CAN_MCR_INRQ ; + + /* Get tickstart */ + tickstart = HAL_GetTick(); + + /* Wait the acknowledge */ + while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) + { + if((HAL_GetTick() - tickstart) > HAL_CAN_DEFAULT_TIMEOUT) + { + hcan->State= HAL_CAN_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + + /* Check acknowledge */ + if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) + { + /* Set the time triggered communication mode */ + if (hcan->Init.TTCM == ENABLE) + { + hcan->Instance->MCR |= CAN_MCR_TTCM; + } + else + { + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM; + } + + /* Set the automatic bus-off management */ + if (hcan->Init.ABOM == ENABLE) + { + hcan->Instance->MCR |= CAN_MCR_ABOM; + } + else + { + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM; + } + + /* Set the automatic wake-up mode */ + if (hcan->Init.AWUM == ENABLE) + { + hcan->Instance->MCR |= CAN_MCR_AWUM; + } + else + { + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM; + } + + /* Set the no automatic retransmission */ + if (hcan->Init.NART == ENABLE) + { + hcan->Instance->MCR |= CAN_MCR_NART; + } + else + { + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART; + } + + /* Set the receive FIFO locked mode */ + if (hcan->Init.RFLM == ENABLE) + { + hcan->Instance->MCR |= CAN_MCR_RFLM; + } + else + { + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM; + } + + /* Set the transmit FIFO priority */ + if (hcan->Init.TXFP == ENABLE) + { + hcan->Instance->MCR |= CAN_MCR_TXFP; + } + else + { + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP; + } + + /* Set the bit timing register */ + hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \ + ((uint32_t)hcan->Init.SJW) | \ + ((uint32_t)hcan->Init.BS1) | \ + ((uint32_t)hcan->Init.BS2) | \ + ((uint32_t)hcan->Init.Prescaler - 1); + + /* Request leave initialisation */ + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ; + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait the acknowledge */ + while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) + { + if((HAL_GetTick() - tickstart) > HAL_CAN_DEFAULT_TIMEOUT) + { + hcan->State= HAL_CAN_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + + /* Check acknowledged */ + if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) + { + status = CAN_INITSTATUS_SUCCESS; + } + } + + if(status == CAN_INITSTATUS_SUCCESS) + { + /* Set CAN error code to none */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Initialize the CAN state */ + hcan->State = HAL_CAN_STATE_READY; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Initialize the CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Configures the CAN reception filter according to the specified + * parameters in the CAN_FilterInitStruct. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that + * contains the filter configuration information. + * @retval None + */ +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig) +{ + uint32_t filternbrbitpos = 0; + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber)); + assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode)); + assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale)); + assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment)); + assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation)); + assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber)); + + filternbrbitpos = ((uint32_t)1) << sFilterConfig->FilterNumber; + + /* Initialisation mode for the filter */ + hcan->Instance->FMR |= (uint32_t)CAN_FMR_FINIT; + + /* Filter Deactivation */ + hcan->Instance->FA1R &= ~(uint32_t)filternbrbitpos; + + /* Filter Scale */ + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) + { + /* 16-bit scale for the filter */ + hcan->Instance->FS1R &= ~(uint32_t)filternbrbitpos; + + /* First 16-bit identifier and First 16-bit mask */ + /* Or First 16-bit identifier and Second 16-bit identifier */ + hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16) | + (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow); + + /* Second 16-bit identifier and Second 16-bit mask */ + /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh); + } + + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) + { + /* 32-bit scale for the filter */ + hcan->Instance->FS1R |= filternbrbitpos; + /* 32-bit identifier or First 32-bit identifier */ + hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh) << 16) | + (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow); + /* 32-bit mask or Second 32-bit identifier */ + hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow); + } + + /* Filter Mode */ + if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) + { + /*Id/Mask mode for the filter*/ + hcan->Instance->FM1R &= ~(uint32_t)filternbrbitpos; + } + else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ + { + /*Identifier list mode for the filter*/ + hcan->Instance->FM1R |= (uint32_t)filternbrbitpos; + } + + /* Filter FIFO assignment */ + if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) + { + /* FIFO 0 assignation for the filter */ + hcan->Instance->FFA1R &= ~(uint32_t)filternbrbitpos; + } + + if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1) + { + /* FIFO 1 assignation for the filter */ + hcan->Instance->FFA1R |= (uint32_t)filternbrbitpos; + } + + /* Filter activation */ + if (sFilterConfig->FilterActivation == ENABLE) + { + hcan->Instance->FA1R |= filternbrbitpos; + } + + /* Leave the initialisation mode for the filter */ + hcan->Instance->FMR &= ~((uint32_t)CAN_FMR_FINIT); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Deinitializes the CANx peripheral registers to their default reset values. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan) +{ + /* Check CAN handle */ + if(hcan == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY; + + /* DeInit the low level hardware */ + HAL_CAN_MspDeInit(hcan); + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the CAN MSP. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the CAN MSP. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group2 I/O operation functions + * @brief I/O operation functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Transmit a CAN frame message. + (+) Receive a CAN frame message. + (+) Enter CAN peripheral in sleep mode. + (+) Wake up the CAN peripheral from sleep mode. + +@endverbatim + * @{ + */ + +/** + * @brief Initiates and transmits a CAN frame message. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param Timeout: Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) +{ + uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX; + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); + assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); + assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); + + /* Process locked */ + __HAL_LOCK(hcan); + + if(hcan->State == HAL_CAN_STATE_BUSY_RX) + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX_RX; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX; + } + + /* Select one empty transmit mailbox */ + if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) + { + transmitmailbox = 0; + } + else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) + { + transmitmailbox = 1; + } + else if ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) + { + transmitmailbox = 2; + } + + if (transmitmailbox != CAN_TXSTATUS_NOMAILBOX) + { + /* Set up the Id */ + hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; + if (hcan->pTxMsg->IDE == CAN_ID_STD) + { + assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \ + hcan->pTxMsg->RTR); + } + else + { + assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \ + hcan->pTxMsg->IDE | \ + hcan->pTxMsg->RTR); + } + + /* Set up the DLC */ + hcan->pTxMsg->DLC &= (uint8_t)0x0000000F; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; + + /* Set up the data field */ + hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) | + ((uint32_t)hcan->pTxMsg->Data[2] << 16) | + ((uint32_t)hcan->pTxMsg->Data[1] << 8) | + ((uint32_t)hcan->pTxMsg->Data[0])); + hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) | + ((uint32_t)hcan->pTxMsg->Data[6] << 16) | + ((uint32_t)hcan->pTxMsg->Data[5] << 8) | + ((uint32_t)hcan->pTxMsg->Data[4])); + /* Request transmission */ + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Check End of transmission flag */ + while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox))) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + { + hcan->State = HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } + } + } + if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_RX; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_READY; + } + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Initiates and transmits a CAN frame message. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) +{ + uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX; + + /* Check the parameters */ + assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); + assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); + assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); + + if((hcan->State == HAL_CAN_STATE_READY) || (hcan->State == HAL_CAN_STATE_BUSY_RX)) + { + /* Process Locked */ + __HAL_LOCK(hcan); + + /* Select one empty transmit mailbox */ + if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) + { + transmitmailbox = 0; + } + else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) + { + transmitmailbox = 1; + } + else if((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) + { + transmitmailbox = 2; + } + + if(transmitmailbox != CAN_TXSTATUS_NOMAILBOX) + { + /* Set up the Id */ + hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; + if(hcan->pTxMsg->IDE == CAN_ID_STD) + { + assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \ + hcan->pTxMsg->RTR); + } + else + { + assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \ + hcan->pTxMsg->IDE | \ + hcan->pTxMsg->RTR); + } + + /* Set up the DLC */ + hcan->pTxMsg->DLC &= (uint8_t)0x0000000F; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; + + /* Set up the data field */ + hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) | + ((uint32_t)hcan->pTxMsg->Data[2] << 16) | + ((uint32_t)hcan->pTxMsg->Data[1] << 8) | + ((uint32_t)hcan->pTxMsg->Data[0])); + hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) | + ((uint32_t)hcan->pTxMsg->Data[6] << 16) | + ((uint32_t)hcan->pTxMsg->Data[5] << 8) | + ((uint32_t)hcan->pTxMsg->Data[4])); + + if(hcan->State == HAL_CAN_STATE_BUSY_RX) + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX_RX; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX; + } + + /* Set CAN error code to none */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hcan); + + /* Enable Error warning Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG); + + /* Enable Error passive Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV); + + /* Enable Bus-off Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF); + + /* Enable Last error code Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC); + + /* Enable Error Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR); + + /* Enable Transmit mailbox empty Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_TME); + + /* Request transmission */ + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; + } + } + else + { + return HAL_BUSY; + } + + return HAL_OK; +} + +/** + * @brief Receives a correct CAN frame. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param FIFONumber: FIFO number. + * @param Timeout: Timeout duration. + * @retval HAL status + * @retval None + */ +HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout) +{ + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param(IS_CAN_FIFO(FIFONumber)); + + /* Process locked */ + __HAL_LOCK(hcan); + + if(hcan->State == HAL_CAN_STATE_BUSY_TX) + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX_RX; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_RX; + } + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Check pending message */ + while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + { + hcan->State = HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } + } + } + + /* Get the Id */ + hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + if (hcan->pRxMsg->IDE == CAN_ID_STD) + { + hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21); + } + else + { + hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3); + } + + hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + /* Get the DLC */ + hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; + /* Get the FMI */ + hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8); + /* Get the data field */ + hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; + hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8); + hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16); + hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24); + hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; + hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8); + hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16); + hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24); + + /* Release the FIFO */ + if(FIFONumber == CAN_FIFO0) + { + /* Release FIFO0 */ + __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0); + } + else /* FIFONumber == CAN_FIFO1 */ + { + /* Release FIFO1 */ + __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1); + } + + if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_READY; + } + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Receives a correct CAN frame. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param FIFONumber: FIFO number. + * @retval HAL status + * @retval None + */ +HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) +{ + /* Check the parameters */ + assert_param(IS_CAN_FIFO(FIFONumber)); + + if((hcan->State == HAL_CAN_STATE_READY) || (hcan->State == HAL_CAN_STATE_BUSY_TX)) + { + /* Process locked */ + __HAL_LOCK(hcan); + + if(hcan->State == HAL_CAN_STATE_BUSY_TX) + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX_RX; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_RX; + } + + /* Set CAN error code to none */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Enable Error warning Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG); + + /* Enable Error passive Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV); + + /* Enable Bus-off Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF); + + /* Enable Last error code Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC); + + /* Enable Error Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR); + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + if(FIFONumber == CAN_FIFO0) + { + /* Enable FIFO 0 message pending Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP0); + } + else + { + /* Enable FIFO 1 message pending Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP1); + } + + } + else + { + return HAL_BUSY; + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Enters the Sleep (low power) mode. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan) +{ + uint32_t tickstart = 0; + + /* Process locked */ + __HAL_LOCK(hcan); + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY; + + /* Request Sleep mode */ + hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); + + /* Sleep mode status */ + if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK) + { + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_ERROR; + } + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait the acknowledge */ + while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK) + { + if((HAL_GetTick() - tickstart) > HAL_CAN_DEFAULT_TIMEOUT) + { + hcan->State = HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } + } + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral + * is in the normal mode. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan) +{ + uint32_t tickstart = 0; + + /* Process locked */ + __HAL_LOCK(hcan); + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY; + + /* Wake up request */ + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP; + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Sleep mode status */ + while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK) + { + if((HAL_GetTick() - tickstart) > HAL_CAN_DEFAULT_TIMEOUT) + { + hcan->State= HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } + } + if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK) + { + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_ERROR; + } + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Handles CAN interrupt request + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) +{ + /* Check End of transmission flag */ + if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME)) + { + if((__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0)) || + (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1)) || + (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2))) + { + /* Call transmit function */ + CAN_Transmit_IT(hcan); + } + } + + /* Check End of reception flag for FIFO0 */ + if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0)) && + (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0) != 0)) + { + /* Call receive function */ + CAN_Receive_IT(hcan, CAN_FIFO0); + } + + /* Check End of reception flag for FIFO1 */ + if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1)) && + (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1) != 0)) + { + /* Call receive function */ + CAN_Receive_IT(hcan, CAN_FIFO1); + } + + /* Check Error Warning Flag */ + if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR))) + { + /* Set CAN error code to EWG error */ + hcan->ErrorCode |= HAL_CAN_ERROR_EWG; + /* No need for clear of Error Warning Flag as read-only */ + } + + /* Check Error Passive Flag */ + if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR))) + { + /* Set CAN error code to EPV error */ + hcan->ErrorCode |= HAL_CAN_ERROR_EPV; + /* No need for clear of Error Passive Flag as read-only */ + } + + /* Check Bus-Off Flag */ + if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR))) + { + /* Set CAN error code to BOF error */ + hcan->ErrorCode |= HAL_CAN_ERROR_BOF; + /* No need for clear of Bus-Off Flag as read-only */ + } + + /* Check Last error code Flag */ + if((!HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR))) + { + switch(hcan->Instance->ESR & CAN_ESR_LEC) + { + case(CAN_ESR_LEC_0): + /* Set CAN error code to STF error */ + hcan->ErrorCode |= HAL_CAN_ERROR_STF; + break; + case(CAN_ESR_LEC_1): + /* Set CAN error code to FOR error */ + hcan->ErrorCode |= HAL_CAN_ERROR_FOR; + break; + case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0): + /* Set CAN error code to ACK error */ + hcan->ErrorCode |= HAL_CAN_ERROR_ACK; + break; + case(CAN_ESR_LEC_2): + /* Set CAN error code to BR error */ + hcan->ErrorCode |= HAL_CAN_ERROR_BR; + break; + case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0): + /* Set CAN error code to BD error */ + hcan->ErrorCode |= HAL_CAN_ERROR_BD; + break; + case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1): + /* Set CAN error code to CRC error */ + hcan->ErrorCode |= HAL_CAN_ERROR_CRC; + break; + default: + break; + } + + /* Clear Last error code Flag */ + hcan->Instance->ESR &= ~(CAN_ESR_LEC); + } + + /* Call the Error call Back in case of Errors */ + if(hcan->ErrorCode != HAL_CAN_ERROR_NONE) + { + /* Set the CAN state ready to be able to start again the process */ + hcan->State = HAL_CAN_STATE_READY; + /* Call Error callback function */ + HAL_CAN_ErrorCallback(hcan); + } +} + +/** + * @brief Transmission complete callback in non blocking mode + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Transmission complete callback in non blocking mode + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Error CAN callback. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions + * @brief CAN Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Error functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to : + (+) Check the CAN state. + (+) Check CAN Errors detected during interrupt process + +@endverbatim + * @{ + */ + +/** + * @brief return the CAN state + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL state + */ +HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan) +{ + /* Return CAN state */ + return hcan->State; +} + +/** + * @brief Return the CAN error code + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval CAN Error Code + */ +uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan) +{ + return hcan->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup CAN_Private_Functions CAN Private Functions + * @brief CAN Frame message Rx/Tx functions + * + * @{ + */ + +/** + * @brief Initiates and transmits a CAN frame message. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan) +{ + /* Disable Transmit mailbox empty Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME); + + if(hcan->State == HAL_CAN_STATE_BUSY_TX) + { + /* Disable Error warning Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG); + + /* Disable Error passive Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV); + + /* Disable Bus-off Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF); + + /* Disable Last error code Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC); + + /* Disable Error Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR); + } + + if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_RX; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_READY; + } + + /* Transmission complete callback */ + HAL_CAN_TxCpltCallback(hcan); + + return HAL_OK; +} + +/** + * @brief Receives a correct CAN frame. + * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param FIFONumber: Specify the FIFO number + * @retval HAL status + * @retval None + */ +static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) +{ + /* Get the Id */ + hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + if (hcan->pRxMsg->IDE == CAN_ID_STD) + { + hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21); + } + else + { + hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3); + } + + hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + /* Get the DLC */ + hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; + /* Get the FMI */ + hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8); + /* Get the data field */ + hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; + hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8); + hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16); + hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24); + hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; + hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8); + hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16); + hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24); + /* Release the FIFO */ + /* Release FIFO0 */ + if (FIFONumber == CAN_FIFO0) + { + __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0); + + /* Disable FIFO 0 message pending Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP0); + } + /* Release FIFO1 */ + else /* FIFONumber == CAN_FIFO1 */ + { + __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1); + + /* Disable FIFO 1 message pending Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP1); + } + + if(hcan->State == HAL_CAN_STATE_BUSY_RX) + { + /* Disable Error warning Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG); + + /* Disable Error passive Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV); + + /* Disable Bus-off Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF); + + /* Disable Last error code Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC); + + /* Disable Error Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR); + } + + if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) + { + /* Disable CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_READY; + } + + /* Receive complete callback */ + HAL_CAN_RxCpltCallback(hcan); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +#endif /* defined(STM32F072xB) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F091xC) || defined(STM32F098xx) */ + +#endif /* HAL_CAN_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cec.c b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cec.c new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cec.c @@ -0,0 +1,1109 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_cec.c + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief CEC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the High Definition Multimedia Interface + * Consumer Electronics Control Peripheral (CEC). + * + Initialization and de-initialization function + * + IO operation function + * + Peripheral Control function + * + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The CEC HAL driver can be used as follows: + + (#) Declare a CEC_HandleTypeDef handle structure. + (#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API: + (++) Enable the CEC interface clock. + (++) CEC pins configuration: + (+++) Enable the clock for the CEC GPIOs. + (+++) Configure these CEC pins as alternate function pull-up. + (++) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT() + and HAL_CEC_Receive_IT() APIs): + (+++) Configure the CEC interrupt priority. + (+++) Enable the NVIC CEC IRQ handle. + + (#) Program the Signal Free Time (SFT) and SFT option, Tolerance, reception stop in + in case of Bit Rising Error, Error-Bit generation conditions, device logical + address and Listen mode in the hcec Init structure. + + (#) Initialize the CEC registers by calling the HAL_CEC_Init() API. + (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + by calling the customed HAL_CEC_MspInit() API. + + -@@- The specific CEC interrupts (Transmission complete interrupt, + RXNE interrupt and Error Interrupts) will be managed using the macros + __HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit + and receive process. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup CEC CEC HAL Module Driver + * @brief HAL CEC module driver + * @{ + */ +#ifdef HAL_CEC_MODULE_ENABLED + +#if defined(STM32F042x6) || defined(STM32F048xx) ||\ + defined(STM32F051x8) || defined(STM32F058xx) ||\ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) ||\ + defined(STM32F091xC) || defined (STM32F098xx) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup CEC_Private_Constants CEC Private Constants + * @{ + */ +#define CEC_CFGR_FIELDS (CEC_CFGR_SFT | CEC_CFGR_RXTOL | CEC_CFGR_BRESTP \ + | CEC_CFGR_BREGEN | CEC_CFGR_LBPEGEN | CEC_CFGR_SFTOPT \ + | CEC_CFGR_BRDNOGEN | CEC_CFGR_OAR | CEC_CFGR_LSTN) +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup CEC_Private_Functions CEC Private Functions + * @{ + */ +static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec); +static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec); +/** + * @} + */ +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup CEC_Exported_Functions CEC Exported Functions + * @{ + */ + +/** @defgroup CEC_Exported_Functions_Group1 Initialization/de-initialization function + * @brief Initialization and Configuration functions + * +@verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the CEC + (+) The following parameters need to be configured: + (++) SignalFreeTime + (++) Tolerance + (++) BRERxStop (RX stopped or not upon Bit Rising Error) + (++) BREErrorBitGen (Error-Bit generation in case of Bit Rising Error) + (++) LBPEErrorBitGen (Error-Bit generation in case of Long Bit Period Error) + (++) BroadcastMsgNoErrorBitGen (Error-bit generation in case of broadcast message error) + (++) SignalFreeTimeOption (SFT Timer start definition) + (++) OwnAddress (CEC device address) + (++) ListenMode + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the CEC mode according to the specified + * parameters in the CEC_InitTypeDef and creates the associated handle . + * @param hcec: CEC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec) +{ + uint32_t tmpreg = 0x0; + + /* Check the CEC handle allocation */ + if(hcec == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CEC_SIGNALFREETIME(hcec->Init.SignalFreeTime)); + assert_param(IS_CEC_TOLERANCE(hcec->Init.Tolerance)); + assert_param(IS_CEC_BRERXSTOP(hcec->Init.BRERxStop)); + assert_param(IS_CEC_BREERRORBITGEN(hcec->Init.BREErrorBitGen)); + assert_param(IS_CEC_LBPEERRORBITGEN(hcec->Init.LBPEErrorBitGen)); + assert_param(IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(hcec->Init.BroadcastMsgNoErrorBitGen)); + assert_param(IS_CEC_SFTOP(hcec->Init.SignalFreeTimeOption)); + assert_param(IS_CEC_OAR_ADDRESS(hcec->Init.OwnAddress)); + assert_param(IS_CEC_LISTENING_MODE(hcec->Init.ListenMode)); + assert_param(IS_CEC_ADDRESS(hcec->Init.InitiatorAddress)); + + + if(hcec->State == HAL_CEC_STATE_RESET) + { + /* Init the low level hardware : GPIO, CLOCK */ + HAL_CEC_MspInit(hcec); + } + + hcec->State = HAL_CEC_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_CEC_DISABLE(hcec); + + tmpreg = hcec->Init.SignalFreeTime; + tmpreg |= hcec->Init.Tolerance; + tmpreg |= hcec->Init.BRERxStop; + tmpreg |= hcec->Init.BREErrorBitGen; + tmpreg |= hcec->Init.LBPEErrorBitGen; + tmpreg |= hcec->Init.BroadcastMsgNoErrorBitGen; + tmpreg |= hcec->Init.SignalFreeTimeOption; + tmpreg |= (hcec->Init.OwnAddress << CEC_CFGR_OAR_LSB_POS); + tmpreg |= hcec->Init.ListenMode; + + /* Write to CEC Control Register */ + MODIFY_REG(hcec->Instance->CFGR, CEC_CFGR_FIELDS, tmpreg); + + /* Enable the Peripheral */ + __HAL_CEC_ENABLE(hcec); + + hcec->State = HAL_CEC_STATE_READY; + + return HAL_OK; +} + + + +/** + * @brief DeInitializes the CEC peripheral + * @param hcec: CEC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec) +{ + /* Check the CEC handle allocation */ + if(hcec == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance)); + + hcec->State = HAL_CEC_STATE_BUSY; + + /* DeInit the low level hardware */ + HAL_CEC_MspDeInit(hcec); + /* Disable the Peripheral */ + __HAL_CEC_DISABLE(hcec); + + hcec->ErrorCode = HAL_CEC_ERROR_NONE; + hcec->State = HAL_CEC_STATE_RESET; + + /* Process Unlock */ + __HAL_UNLOCK(hcec); + + return HAL_OK; +} + +/** + * @brief CEC MSP Init + * @param hcec: CEC handle + * @retval None + */ + __weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CEC_MspInit can be implemented in the user file + */ +} + +/** + * @brief CEC MSP DeInit + * @param hcec: CEC handle + * @retval None + */ + __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CEC_MspDeInit can be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup CEC_Exported_Functions_Group2 IO operation function + * @brief CEC Transmit/Receive functions + * +@verbatim + =============================================================================== + ##### IO operation function ##### + =============================================================================== + This subsection provides a set of functions allowing to manage the CEC data transfers. + + (#) The CEC handle must contain the initiator (TX side) and the destination (RX side) + logical addresses (4-bit long addresses, 0xF for broadcast messages destination) + + (#) There are two mode of transfer: + (+) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (+) Non Blocking mode: The communication is performed using Interrupts. + These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated CEC IRQ when using Interrupt mode. + The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks + will be executed respectivelly at the end of the transmit or Receive process + The HAL_CEC_ErrorCallback()user callback will be executed when a communication + error is detected + + (#) Blocking mode API s are : + (+) HAL_CEC_Transmit() + (+) HAL_CEC_Receive() + + (#) Non-Blocking mode API s with Interrupt are : + (+) HAL_CEC_Transmit_IT() + (+) HAL_CEC_Receive_IT() + (+) HAL_CEC_IRQHandler() + + (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode: + (+) HAL_CEC_TxCpltCallback() + (+) HAL_CEC_RxCpltCallback() + (+) HAL_CEC_ErrorCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Send data in blocking mode + * @param hcec: CEC handle + * @param DestinationAddress: destination logical address + * @param pData: pointer to input byte data buffer + * @param Size: amount of data to be sent in bytes (without counting the header). + * 0 means only the header is sent (ping operation). + * Maximum TX size is 15 bytes (1 opcode and up to 14 operands). + * @param Timeout: Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout) +{ + uint8_t temp = 0; + uint32_t tempisr = 0; + uint32_t tickstart = 0; + + if((hcec->State == HAL_CEC_STATE_READY) && (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) == RESET)) + { + hcec->ErrorCode = HAL_CEC_ERROR_NONE; + if((pData == NULL ) && (Size > 0)) + { + hcec->State = HAL_CEC_STATE_ERROR; + return HAL_ERROR; + } + + assert_param(IS_CEC_ADDRESS(DestinationAddress)); + assert_param(IS_CEC_MSGSIZE(Size)); + + /* Process Locked */ + __HAL_LOCK(hcec); + + hcec->State = HAL_CEC_STATE_BUSY_TX; + + hcec->TxXferCount = Size; + + /* case no data to be sent, sender is only pinging the system */ + if (Size == 0) + { + /* Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */ + __HAL_CEC_LAST_BYTE_TX_SET(hcec); + } + + /* send header block */ + temp = ((uint32_t)hcec->Init.InitiatorAddress << CEC_INITIATOR_LSB_POS) | DestinationAddress; + hcec->Instance->TXDR = temp; + /* Set TX Start of Message (TXSOM) bit */ + __HAL_CEC_FIRST_BYTE_TX_SET(hcec); + + while (hcec->TxXferCount > 0) + { + hcec->TxXferCount--; + + tickstart = HAL_GetTick(); + while(HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_TXBR)) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + { + hcec->State = HAL_CEC_STATE_TIMEOUT; + /* Process Unlocked */ + __HAL_UNLOCK(hcec); + return HAL_TIMEOUT; + } + } + + /* check whether error occured while waiting for TXBR to be set: + * has Tx underrun occurred ? + * has Tx error occurred ? + * has Tx Missing Acknowledge error occurred ? + * has Arbitration Loss error occurred ? */ + tempisr = hcec->Instance->ISR; + if ((tempisr & (CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE|CEC_ISR_ARBLST)) != 0) + { + /* copy ISR for error handling purposes */ + hcec->ErrorCode = tempisr; + /* clear all error flags by default */ + __HAL_CEC_CLEAR_FLAG(hcec, (CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE|CEC_ISR_ARBLST)); + hcec->State = HAL_CEC_STATE_ERROR; + __HAL_UNLOCK(hcec); + return HAL_ERROR; + } + } + /* TXBR to clear BEFORE writing TXDR register */ + __HAL_CEC_CLEAR_FLAG(hcec,CEC_ISR_TXBR); + if (hcec->TxXferCount == 0) + { + /* if last byte transmission, set TX End of Message (TXEOM) bit */ + __HAL_CEC_LAST_BYTE_TX_SET(hcec); + } + hcec->Instance->TXDR = *pData++; + + /* error check after TX byte write up */ + tempisr = hcec->Instance->ISR; + if ((tempisr & (CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE|CEC_ISR_ARBLST)) != 0) + { + /* copy ISR for error handling purposes */ + hcec->ErrorCode = tempisr; + /* clear all error flags by default */ + __HAL_CEC_CLEAR_FLAG(hcec, (CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE|CEC_ISR_ARBLST)); + hcec->State = HAL_CEC_STATE_ERROR; + __HAL_UNLOCK(hcec); + return HAL_ERROR; + } + } /* end while (while (hcec->TxXferCount > 0)) */ + + + /* if no error up to this point, check that transmission is + * complete, that is wait until TXEOM is reset */ + tickstart = HAL_GetTick(); + + while (HAL_IS_BIT_SET(hcec->Instance->CR, CEC_CR_TXEOM)) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + { + hcec->State = HAL_CEC_STATE_ERROR; + __HAL_UNLOCK(hcec); + return HAL_TIMEOUT; + } + } + } + + /* Final error check once all bytes have been transmitted */ + tempisr = hcec->Instance->ISR; + if ((tempisr & (CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)) != 0) + { + /* copy ISR for error handling purposes */ + hcec->ErrorCode = tempisr; + /* clear all error flags by default */ + __HAL_CEC_CLEAR_FLAG(hcec, (CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)); + hcec->State = HAL_CEC_STATE_ERROR; + __HAL_UNLOCK(hcec); + return HAL_ERROR; + } + + hcec->State = HAL_CEC_STATE_READY; + __HAL_UNLOCK(hcec); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive data in blocking mode. Must be invoked when RXBR has been set. + * @param hcec: CEC handle + * @param pData: pointer to received data buffer. + * @param Timeout: Timeout duration. + * Note that the received data size is not known beforehand, the latter is known + * when the reception is complete and is stored in hcec->RxXferSize. + * hcec->RxXferSize is the sum of opcodes + operands (0 to 14 operands max). + * If only a header is received, hcec->RxXferSize = 0 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout) +{ + uint32_t temp; + uint32_t tickstart = 0; + + if (hcec->State == HAL_CEC_STATE_READY) + { + hcec->ErrorCode = HAL_CEC_ERROR_NONE; + if (pData == NULL ) + { + hcec->State = HAL_CEC_STATE_ERROR; + return HAL_ERROR; + } + + hcec->RxXferSize = 0; + /* Process Locked */ + __HAL_LOCK(hcec); + + + /* Rx loop until CEC_ISR_RXEND is set */ + while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXEND)) + { + tickstart = HAL_GetTick(); + /* Wait for next byte to be received */ + while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXBR)) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + { + hcec->State = HAL_CEC_STATE_TIMEOUT; + __HAL_UNLOCK(hcec); + return HAL_TIMEOUT; + } + } + /* any error so far ? + * has Rx Missing Acknowledge occurred ? + * has Rx Long Bit Period error occurred ? + * has Rx Short Bit Period error occurred ? + * has Rx Bit Rising error occurred ? + * has Rx Overrun error occurred ? */ + temp = (uint32_t) (hcec->Instance->ISR); + if ((temp & (CEC_ISR_RXACKE|CEC_ISR_LBPE|CEC_ISR_SBPE|CEC_ISR_BRE|CEC_ISR_RXOVR)) != 0) + { + /* copy ISR for error handling purposes */ + hcec->ErrorCode = temp; + /* clear all error flags by default */ + __HAL_CEC_CLEAR_FLAG(hcec, (CEC_ISR_RXACKE|CEC_ISR_LBPE|CEC_ISR_SBPE|CEC_ISR_BRE|CEC_ISR_RXOVR)); + hcec->State = HAL_CEC_STATE_ERROR; + __HAL_UNLOCK(hcec); + return HAL_ERROR; + } + } /* while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXBR)) */ + + + /* read received data */ + *pData++ = hcec->Instance->RXDR; + temp = (uint32_t) (hcec->Instance->ISR); + /* end of message ? */ + if ((temp & CEC_ISR_RXEND) != 0) + { + assert_param(IS_CEC_MSGSIZE(hcec->RxXferSize)); + __HAL_CEC_CLEAR_FLAG(hcec,CEC_ISR_RXEND); + hcec->State = HAL_CEC_STATE_READY; + __HAL_UNLOCK(hcec); + return HAL_OK; + } + + /* clear Rx-Byte Received flag */ + __HAL_CEC_CLEAR_FLAG(hcec,CEC_ISR_RXBR); + /* increment payload byte counter */ + hcec->RxXferSize++; + } /* while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXEND)) */ + + /* if the instructions below are executed, it means RXEND was set when RXBR was + * set for the first time: + * the code within the "while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXEND))" + * loop has not been executed and this means a single byte has been sent */ + *pData++ = hcec->Instance->RXDR; + /* only one header is received: RxXferSize is set to 0 (no operand, no opcode) */ + hcec->RxXferSize = 0; + __HAL_CEC_CLEAR_FLAG(hcec,CEC_ISR_RXEND); + + hcec->State = HAL_CEC_STATE_READY; + __HAL_UNLOCK(hcec); + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + + +/** + * @brief Send data in interrupt mode + * @param hcec: CEC handle + * @param DestinationAddress: destination logical address + * @param pData: pointer to input byte data buffer + * @param Size: amount of data to be sent in bytes (without counting the header). + * 0 means only the header is sent (ping operation). + * Maximum TX size is 15 bytes (1 opcode and up to 14 operands). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size) +{ + uint8_t temp = 0; + /* if the IP isn't already busy and if there is no previous transmission + already pending due to arbitration lost */ + if (((hcec->State == HAL_CEC_STATE_READY) || (hcec->State == HAL_CEC_STATE_STANDBY_RX)) + && (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) == RESET)) + { + if((pData == NULL ) && (Size > 0)) + { + hcec->State = HAL_CEC_STATE_ERROR; + return HAL_ERROR; + } + + assert_param(IS_CEC_ADDRESS(DestinationAddress)); + assert_param(IS_CEC_MSGSIZE(Size)); + + /* Process Locked */ + __HAL_LOCK(hcec); + hcec->pTxBuffPtr = pData; + hcec->State = HAL_CEC_STATE_BUSY_TX; + hcec->ErrorCode = HAL_CEC_ERROR_NONE; + + /* Disable Peripheral to write CEC_IER register */ + __HAL_CEC_DISABLE(hcec); + + /* Enable the following two CEC Transmission interrupts as + * well as the following CEC Transmission Errors interrupts: + * Tx Byte Request IT + * End of Transmission IT + * Tx Missing Acknowledge IT + * Tx-Error IT + * Tx-Buffer Underrun IT + * Tx arbitration lost */ + __HAL_CEC_ENABLE_IT(hcec, CEC_IER_TXBRIE|CEC_IER_TXENDIE|CEC_IER_TX_ALL_ERR); + + /* Enable the Peripheral */ + __HAL_CEC_ENABLE(hcec); + + /* initialize the number of bytes to send, + * 0 means only one header is sent (ping operation) */ + hcec->TxXferCount = Size; + + /* Process Unlocked */ + __HAL_UNLOCK(hcec); + + /* in case of no payload (Size = 0), sender is only pinging the system; + * Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */ + if (Size == 0) + { + __HAL_CEC_LAST_BYTE_TX_SET(hcec); + } + + /* send header block */ + temp = ((uint32_t)hcec->Init.InitiatorAddress << CEC_INITIATOR_LSB_POS) | DestinationAddress; + hcec->Instance->TXDR = temp; + /* Set TX Start of Message (TXSOM) bit */ + __HAL_CEC_FIRST_BYTE_TX_SET(hcec); + + return HAL_OK; + } + /* if the IP is already busy or if there is a previous transmission + already pending due to arbitration loss */ + else if ((hcec->State == HAL_CEC_STATE_BUSY_TX) + || (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET)) + { + __HAL_LOCK(hcec); + /* set state to BUSY TX, in case it wasn't set already (case + * of transmission new attempt after arbitration loss) */ + if (hcec->State != HAL_CEC_STATE_BUSY_TX) + { + hcec->State = HAL_CEC_STATE_BUSY_TX; + } + + /* if all data have been sent */ + if(hcec->TxXferCount == 0) + { + /* Disable Peripheral to write CEC_IER register */ + __HAL_CEC_DISABLE(hcec); + + /* Disable the CEC Transmission Interrupts */ + __HAL_CEC_DISABLE_IT(hcec, CEC_IER_TXBRIE|CEC_IER_TXENDIE); + /* Disable the CEC Transmission Error Interrupts */ + __HAL_CEC_DISABLE_IT(hcec, CEC_IER_TX_ALL_ERR); + + /* Enable the Peripheral */ + __HAL_CEC_ENABLE(hcec); + + __HAL_CEC_CLEAR_FLAG(hcec,CEC_ISR_TXBR|CEC_ISR_TXEND); + + hcec->State = HAL_CEC_STATE_READY; + /* Call the Process Unlocked before calling the Tx call back API to give the possibility to + start again the Transmission under the Tx call back API */ + __HAL_UNLOCK(hcec); + + HAL_CEC_TxCpltCallback(hcec); + + return HAL_OK; + } + else + { + if (hcec->TxXferCount == 1) + { + /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */ + __HAL_CEC_LAST_BYTE_TX_SET(hcec); + } + /* clear Tx-Byte request flag */ + __HAL_CEC_CLEAR_FLAG(hcec,CEC_ISR_TXBR); + hcec->Instance->TXDR = *hcec->pTxBuffPtr++; + hcec->TxXferCount--; + + /* Process Unlocked */ + __HAL_UNLOCK(hcec); + + return HAL_OK; + } + } + else + { + return HAL_BUSY; + } +} + + +/** + * @brief Receive data in interrupt mode. + * @param hcec: CEC handle + * @param pData: pointer to received data buffer. + * Note that the received data size is not known beforehand, the latter is known + * when the reception is complete and is stored in hcec->RxXferSize. + * hcec->RxXferSize is the sum of opcodes + operands (0 to 14 operands max). + * If only a header is received, hcec->RxXferSize = 0 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData) +{ + if(hcec->State == HAL_CEC_STATE_READY) + { + if(pData == NULL ) + { + hcec->State = HAL_CEC_STATE_ERROR; + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hcec); + hcec->RxXferSize = 0; + hcec->pRxBuffPtr = pData; + hcec->ErrorCode = HAL_CEC_ERROR_NONE; + /* the IP is moving to a ready to receive state */ + hcec->State = HAL_CEC_STATE_STANDBY_RX; + + /* Disable Peripheral to write CEC_IER register */ + __HAL_CEC_DISABLE(hcec); + + /* Enable the following CEC Reception Error Interrupts: + * Rx overrun + * Rx bit rising error + * Rx short bit period error + * Rx long bit period error + * Rx missing acknowledge */ + __HAL_CEC_ENABLE_IT(hcec, CEC_IER_RX_ALL_ERR); + + /* Process Unlocked */ + __HAL_UNLOCK(hcec); + + /* Enable the following two CEC Reception interrupts: + * Rx Byte Received IT + * End of Reception IT */ + __HAL_CEC_ENABLE_IT(hcec, CEC_IER_RXBRIE|CEC_IER_RXENDIE); + + __HAL_CEC_ENABLE(hcec); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + + + +/** + * @brief This function handles CEC interrupt requests. + * @param hcec: CEC handle + * @retval None + */ +void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) +{ + /* save interrupts register for further error or interrupts handling purposes */ + hcec->ErrorCode = hcec->Instance->ISR; + /* CEC TX missing acknowledge error interrupt occurred -------------------------------------*/ + if((__HAL_CEC_GET_IT(hcec, CEC_ISR_TXACKE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_TXACKEIE) != RESET)) + { + __HAL_CEC_CLEAR_FLAG(hcec, CEC_ISR_TXACKE); + hcec->State = HAL_CEC_STATE_ERROR; + } + + /* CEC transmit error interrupt occured --------------------------------------*/ + if((__HAL_CEC_GET_IT(hcec, CEC_ISR_TXERR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_TXERRIE) != RESET)) + { + __HAL_CEC_CLEAR_FLAG(hcec, CEC_ISR_TXERR); + hcec->State = HAL_CEC_STATE_ERROR; + } + + /* CEC TX underrun error interrupt occured --------------------------------------*/ + if((__HAL_CEC_GET_IT(hcec, CEC_ISR_TXUDR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_TXUDRIE) != RESET)) + { + __HAL_CEC_CLEAR_FLAG(hcec, CEC_ISR_TXUDR); + hcec->State = HAL_CEC_STATE_ERROR; + } + + /* CEC TX arbitration error interrupt occured --------------------------------------*/ + if((__HAL_CEC_GET_IT(hcec, CEC_ISR_ARBLST) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_ARBLSTIE) != RESET)) + { + __HAL_CEC_CLEAR_FLAG(hcec, CEC_ISR_ARBLST); + hcec->State = HAL_CEC_STATE_ERROR; + } + + /* CEC RX overrun error interrupt occured --------------------------------------*/ + if((__HAL_CEC_GET_IT(hcec, CEC_ISR_RXOVR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_RXOVRIE) != RESET)) + { + __HAL_CEC_CLEAR_FLAG(hcec, CEC_ISR_RXOVR); + hcec->State = HAL_CEC_STATE_ERROR; + } + + /* CEC RX bit rising error interrupt occured --------------------------------------*/ + if((__HAL_CEC_GET_IT(hcec, CEC_ISR_BRE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_BREIE) != RESET)) + { + __HAL_CEC_CLEAR_FLAG(hcec, CEC_ISR_BRE); + hcec->State = HAL_CEC_STATE_ERROR; + } + + /* CEC RX short bit period error interrupt occured --------------------------------------*/ + if((__HAL_CEC_GET_IT(hcec, CEC_ISR_SBPE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_SBPEIE) != RESET)) + { + __HAL_CEC_CLEAR_FLAG(hcec, CEC_ISR_SBPE); + hcec->State = HAL_CEC_STATE_ERROR; + } + + /* CEC RX long bit period error interrupt occured --------------------------------------*/ + if((__HAL_CEC_GET_IT(hcec, CEC_ISR_LBPE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_LBPEIE) != RESET)) + { + __HAL_CEC_CLEAR_FLAG(hcec, CEC_ISR_LBPE); + hcec->State = HAL_CEC_STATE_ERROR; + } + + /* CEC RX missing acknowledge error interrupt occured --------------------------------------*/ + if((__HAL_CEC_GET_IT(hcec, CEC_ISR_RXACKE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_RXACKEIE) != RESET)) + { + __HAL_CEC_CLEAR_FLAG(hcec, CEC_ISR_RXACKE); + hcec->State = HAL_CEC_STATE_ERROR; + } + + if ((hcec->ErrorCode & CEC_ISR_ALL_ERROR) != 0) + { + HAL_CEC_ErrorCallback(hcec); + } + + /* CEC RX byte received interrupt ---------------------------------------------------*/ + if((__HAL_CEC_GET_IT(hcec, CEC_ISR_RXBR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_RXBRIE) != RESET)) + { + /* RXBR IT is cleared during HAL_CEC_Transmit_IT processing */ + CEC_Receive_IT(hcec); + } + + /* CEC RX end received interrupt ---------------------------------------------------*/ + if((__HAL_CEC_GET_IT(hcec, CEC_ISR_RXEND) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_RXENDIE) != RESET)) + { + /* RXBR IT is cleared during HAL_CEC_Transmit_IT processing */ + CEC_Receive_IT(hcec); + } + + + /* CEC TX byte request interrupt ------------------------------------------------*/ + if((__HAL_CEC_GET_IT(hcec, CEC_ISR_TXBR) != RESET) &&(__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_TXBRIE) != RESET)) + { + /* TXBR IT is cleared during HAL_CEC_Transmit_IT processing */ + CEC_Transmit_IT(hcec); + } + + /* CEC TX end interrupt ------------------------------------------------*/ + if((__HAL_CEC_GET_IT(hcec, CEC_ISR_TXEND) != RESET) &&(__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_TXENDIE) != RESET)) + { + /* TXEND IT is cleared during HAL_CEC_Transmit_IT processing */ + CEC_Transmit_IT(hcec); + } + +} + + +/** + * @brief Tx Transfer completed callback + * @param hcec: CEC handle + * @retval None + */ + __weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CEC_TxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callback + * @param hcec: CEC handle + * @retval None + */ +__weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CEC_TxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief CEC error callbacks + * @param hcec: CEC handle + * @retval None + */ + __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CEC_ErrorCallback can be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup CEC_Exported_Functions_Group3 Peripheral Control function + * @brief CEC control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control function ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the CEC. + (+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral. +@endverbatim + * @{ + */ + +/** + * @brief return the CEC state + * @param hcec: CEC handle + * @retval HAL state + */ +HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec) +{ + return hcec->State; +} + +/** +* @brief Return the CEC error code +* @param hcec : pointer to a CEC_HandleTypeDef structure that contains + * the configuration information for the specified CEC. +* @retval CEC Error Code +*/ +uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec) +{ + return hcec->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup CEC_Private_Functions CEC Private Functions + * @{ + */ + +/** + * @brief Send data in interrupt mode + * @param hcec: CEC handle. + * Function called under interruption only, once + * interruptions have been enabled by HAL_CEC_Transmit_IT() + * @retval HAL status + */ +static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec) +{ + /* if the IP is already busy or if there is a previous transmission + already pending due to arbitration loss */ + if ((hcec->State == HAL_CEC_STATE_BUSY_TX) + || (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET)) + { + + /* set state to BUSY TX, in case it wasn't set already (case + * of transmission new attempt after arbitration loss) */ + if (hcec->State != HAL_CEC_STATE_BUSY_TX) + { + hcec->State = HAL_CEC_STATE_BUSY_TX; + } + + /* if all data have been sent */ + if(hcec->TxXferCount == 0) + { + /* Disable Peripheral to write CEC_IER register */ + __HAL_CEC_DISABLE(hcec); + + /* Disable the CEC Transmission Interrupts */ + __HAL_CEC_DISABLE_IT(hcec, CEC_IER_TXBRIE|CEC_IER_TXENDIE); + /* Disable the CEC Transmission Error Interrupts */ + __HAL_CEC_DISABLE_IT(hcec, CEC_IER_TX_ALL_ERR); + + /* Enable the Peripheral */ + __HAL_CEC_ENABLE(hcec); + + __HAL_CEC_CLEAR_FLAG(hcec,CEC_ISR_TXBR|CEC_ISR_TXEND); + + hcec->State = HAL_CEC_STATE_READY; + + HAL_CEC_TxCpltCallback(hcec); + + return HAL_OK; + } + else + { + if (hcec->TxXferCount == 1) + { + /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */ + __HAL_CEC_LAST_BYTE_TX_SET(hcec); + } + /* clear Tx-Byte request flag */ + __HAL_CEC_CLEAR_FLAG(hcec,CEC_ISR_TXBR); + hcec->Instance->TXDR = *hcec->pTxBuffPtr++; + hcec->TxXferCount--; + + return HAL_OK; + } + } + else + { + return HAL_BUSY; + } +} + + +/** + * @brief Receive data in interrupt mode. + * @param hcec: CEC handle. + * Function called under interruption only, once + * interruptions have been enabled by HAL_CEC_Receive_IT() + * @retval HAL status + */ +static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec) +{ + uint32_t tempisr; + + /* Three different conditions are tested to carry out the RX IT processing: + * - the IP is in reception stand-by (the IP state is HAL_CEC_STATE_STANDBY_RX) and + * the reception of the first byte is starting + * - a message reception is already on-going (the IP state is HAL_CEC_STATE_BUSY_RX) + * and a new byte is being received + * - a transmission has just been started (the IP state is HAL_CEC_STATE_BUSY_TX) + * but has been interrupted by a new message reception or discarded due to + * arbitration loss: the reception of the first or higher priority message + * (the arbitration winner) is starting */ + if ((hcec->State == HAL_CEC_STATE_STANDBY_RX) + || (hcec->State == HAL_CEC_STATE_BUSY_RX) + || (hcec->State == HAL_CEC_STATE_BUSY_TX)) + { + /* reception is starting */ + hcec->State = HAL_CEC_STATE_BUSY_RX; + tempisr = (uint32_t) (hcec->Instance->ISR); + if ((tempisr & CEC_ISR_RXBR) != 0) + { + /* read received byte */ + *hcec->pRxBuffPtr++ = hcec->Instance->RXDR; + /* if last byte has been received */ + if ((tempisr & CEC_ISR_RXEND) != 0) + { + /* clear IT */ + __HAL_CEC_CLEAR_FLAG(hcec,CEC_ISR_RXBR|CEC_ISR_RXEND); + /* RX interrupts are not disabled at this point. + * Indeed, to disable the IT, the IP must be disabled first + * which resets the TXSOM flag. In case of arbitration loss, + * this leads to a transmission abort. + * Therefore, RX interruptions disabling if so required, + * is done in HAL_CEC_RxCpltCallback */ + + /* IP state is moved to READY. + * If the IP must remain in standby mode to listen + * any new message, it is up to HAL_CEC_RxCpltCallback + * to move it again to HAL_CEC_STATE_STANDBY_RX */ + hcec->State = HAL_CEC_STATE_READY; + + HAL_CEC_RxCpltCallback(hcec); + + return HAL_OK; + } + __HAL_CEC_CLEAR_FLAG(hcec, CEC_ISR_RXBR); + + hcec->RxXferSize++; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @} + */ + +#endif /* defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F051x8) || defined(STM32F058xx) || */ + /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || */ + /* defined(STM32F091xC) || defined (STM32F098xx) */ + +#endif /* HAL_CEC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_comp.c b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_comp.c new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_comp.c @@ -0,0 +1,694 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_comp.c + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief COMP HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the COMP peripheral: + * + Initialization/de-initialization functions + * + I/O operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + @verbatim +================================================================================ + ##### COMP Peripheral features ##### +================================================================================ + + [..] + The STM32F0xx device family integrates up to 2 analog comparators COMP1 and COMP2: + (#) The non inverting input and inverting input can be set to GPIO pins + as shown in table1. COMP Inputs below. + + (#) The COMP output is available using HAL_COMP_GetOutputLevel() + and can be set on GPIO pins. Refer to table 2. COMP Outputs below. + + (#) The COMP output can be redirected to embedded timers (TIM1, TIM2 and TIM3) + Refer to table 3. COMP Outputs redirection to embedded timers below. + + (#) The comparators COMP1 and COMP2 can be combined in window mode. + + (#) The comparators have interrupt capability with wake-up + from Sleep and Stop modes (through the EXTI controller): + (++) COMP1 is internally connected to EXTI Line 21 + (++) COMP2 is internally connected to EXTI Line 22 + From the corresponding IRQ handler, the right interrupt source can be retrieved with the + macro __HAL_COMP_EXTI_GET_FLAG(). Possible values are: + (++) COMP_EXTI_LINE_COMP1_EVENT + (++) COMP_EXTI_LINE_COMP2_EVENT + + +[..] Table 1. COMP Inputs for the STM32F05x and STM32F07x devices + +--------------------------------------------------+ + | | | COMP1 | COMP2 | + |-----------------|----------------|---------------| + | | 1/4 VREFINT | OK | OK | + | | 1/2 VREFINT | OK | OK | + | | 3/4 VREFINT | OK | OK | + | Inverting Input | VREFINT | OK | OK | + | | DAC1 OUT (PA4) | OK | OK | + | | DAC2 OUT (PA5) | OK | OK | + | | IO1 | PA0 | PA2 | + |-----------------|----------------|-------|-------| + | Non Inverting | | PA1 | PA3 | + | Input | | | | + +--------------------------------------------------+ + + [..] Table 2. COMP Outputs for the STM32F05x and STM32F07x devices + +---------------+ + | COMP1 | COMP2 | + |-------|-------| + | PA0 | PA2 | + | PA6 | PA7 | + | PA11 | PA12 | + +---------------+ + + [..] Table 3. COMP Outputs redirection to embedded timers for the STM32F05x and STM32F07x devices + +---------------------------------+ + | COMP1 | COMP2 | + |----------------|----------------| + | TIM1 BKIN | TIM1 BKIN | + | | | + | TIM1 OCREFCLR | TIM1 OCREFCLR | + | | | + | TIM1 IC1 | TIM1 IC1 | + | | | + | TIM2 IC4 | TIM2 IC4 | + | | | + | TIM2 OCREFCLR | TIM2 OCREFCLR | + | | | + | TIM3 IC1 | TIM3 IC1 | + | | | + | TIM3 OCREFCLR | TIM3 OCREFCLR | + +---------------------------------+ + + ##### How to use this driver ##### +================================================================================ + [..] + This driver provides functions to configure and program the Comparators of STM32F05x and STM32F07x devices. + + To use the comparator, perform the following steps: + + (#) Fill in the HAL_COMP_MspInit() to + (++) Configure the comparator input in analog mode using HAL_GPIO_Init() + (++) Configure the comparator output in alternate function mode using HAL_GPIO_Init() to map the comparator + output to the GPIO pin + (++) If required enable the COMP interrupt by configuring and enabling EXTI line in Interrupt mode and + selecting the desired sensitivity level using HAL_GPIO_Init() function. After that enable the comparator + interrupt vector using HAL_NVIC_EnableIRQ() function. + + (#) Configure the comparator using HAL_COMP_Init() function: + (++) Select the inverting input + (++) Select the non inverting input + (++) Select the output polarity + (++) Select the output redirection + (++) Select the hysteresis level + (++) Select the power mode + (++) Select the event/interrupt mode + + (#) Enable the comparator using HAL_COMP_Start() function or HAL_COMP_Start_IT() function for interrupt mode + + (#) Read the comparator output level with HAL_COMP_GetOutputLevel() + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#if defined(STM32F051x8) || defined(STM32F058xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined (STM32F098xx) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup COMP COMP HAL Module Driver + * @brief COMP HAL module driver + * @{ + */ + +#ifdef HAL_COMP_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup COMP_Private_Constants COMP Private Constants + * @{ + */ +/* CSR register reset value */ +#define COMP_CSR_RESET_VALUE ((uint32_t)0x00000000) +/* CSR register masks */ +#define COMP_CSR_RESET_PARAMETERS_MASK ((uint32_t)0x00003FFF) +#define COMP_CSR_UPDATE_PARAMETERS_MASK ((uint32_t)0x00003FFE) +/* CSR COMPx non inverting input mask */ +#define COMP_CSR_COMPxNONINSEL_MASK ((uint16_t)COMP_CSR_COMP1SW1) +/* CSR COMP2 shift */ +#define COMP_CSR_COMP1_SHIFT 0U +#define COMP_CSR_COMP2_SHIFT 16U +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup COMP_Exported_Functions COMP Exported Functions + * @{ + */ + +/** @defgroup COMP_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions to initialize and de-initialize comparators + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the COMP according to the specified + * parameters in the COMP_InitTypeDef and create the associated handle. + * @note If the selected comparator is locked, initialization can't be performed. + * To unlock the configuration, perform a system reset. + * @param hcomp: COMP handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t regshift = COMP_CSR_COMP1_SHIFT; + + /* Check the COMP handle allocation and lock status */ + if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET)) + { + status = HAL_ERROR; + } + else + { + /* Check the parameter */ + assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); + assert_param(IS_COMP_INVERTINGINPUT(hcomp->Init.InvertingInput)); + assert_param(IS_COMP_NONINVERTINGINPUT(hcomp->Init.NonInvertingInput)); + assert_param(IS_COMP_OUTPUT(hcomp->Init.Output)); + assert_param(IS_COMP_OUTPUTPOL(hcomp->Init.OutputPol)); + assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis)); + assert_param(IS_COMP_MODE(hcomp->Init.Mode)); + + if(hcomp->Init.NonInvertingInput == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED) + { + assert_param(IS_COMP_DAC1SWITCH_INSTANCE(hcomp->Instance)); + } + + if(hcomp->Init.WindowMode != COMP_WINDOWMODE_DISABLED) + { + assert_param(IS_COMP_WINDOWMODE_INSTANCE(hcomp->Instance)); + } + + if(hcomp->State == HAL_COMP_STATE_RESET) + { + /* Init SYSCFG and the low level hardware to access comparators */ + __SYSCFG_CLK_ENABLE(); + + HAL_COMP_MspInit(hcomp); + } + + /* Set COMP parameters */ + /* Set COMPxINSEL bits according to hcomp->Init.InvertingInput value */ + /* Set COMPxOUTSEL bits according to hcomp->Init.Output value */ + /* Set COMPxPOL bit according to hcomp->Init.OutputPol value */ + /* Set COMPxHYST bits according to hcomp->Init.Hysteresis value */ + /* Set COMPxMODE bits according to hcomp->Init.Mode value */ + if(hcomp->Instance == COMP2) + { + regshift = COMP_CSR_COMP2_SHIFT; + } + MODIFY_REG(COMP->CSR, + (uint32_t)(COMP_CSR_COMPxINSEL | COMP_CSR_COMPxNONINSEL_MASK | \ + COMP_CSR_COMPxOUTSEL | COMP_CSR_COMPxPOL | \ + COMP_CSR_COMPxHYST | COMP_CSR_COMPxMODE) << regshift, + (hcomp->Init.InvertingInput | \ + hcomp->Init.NonInvertingInput | \ + hcomp->Init.Output | \ + hcomp->Init.OutputPol | \ + hcomp->Init.Hysteresis | \ + hcomp->Init.Mode) << regshift); + + if(hcomp->Init.WindowMode != COMP_WINDOWMODE_DISABLED) + { + COMP->CSR |= COMP_CSR_WNDWEN; + } + + /* Initialize the COMP state*/ + if(hcomp->State == HAL_COMP_STATE_RESET) + { + hcomp->State = HAL_COMP_STATE_READY; + } + } + + return status; +} + +/** + * @brief DeInitializes the COMP peripheral + * @note Deinitialization can't be performed if the COMP configuration is locked. + * To unlock the configuration, perform a system reset. + * @param hcomp: COMP handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t regshift = COMP_CSR_COMP1_SHIFT; + + /* Check the COMP handle allocation and lock status */ + if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET)) + { + status = HAL_ERROR; + } + else + { + /* Check the parameter */ + assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); + + /* Set COMP_CSR register to reset value for the corresponding COMP instance */ + if(hcomp->Instance == COMP2) + { + regshift = COMP_CSR_COMP2_SHIFT; + } + MODIFY_REG(COMP->CSR, + COMP_CSR_RESET_PARAMETERS_MASK << regshift, + COMP_CSR_RESET_VALUE << regshift); + + /* DeInit the low level hardware: SYSCFG, GPIO, CLOCK and NVIC */ + HAL_COMP_MspDeInit(hcomp); + + hcomp->State = HAL_COMP_STATE_RESET; + } + + return status; +} + +/** + * @brief Initializes the COMP MSP. + * @param hcomp: COMP handle + * @retval None + */ +__weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_COMP_MspInit could be implenetd in the user file + */ +} + +/** + * @brief DeInitializes COMP MSP. + * @param hcomp: COMP handle + * @retval None + */ +__weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_COMP_MspDeInit could be implenetd in the user file + */ +} + +/** + * @} + */ + +/** @defgroup COMP_Exported_Functions_Group2 I/O operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the COMP data + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Start the comparator + * @param hcomp: COMP handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t regshift = COMP_CSR_COMP1_SHIFT; + + /* Check the COMP handle allocation and lock status */ + if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET)) + { + status = HAL_ERROR; + } + else + { + /* Check the parameter */ + assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); + + if(hcomp->State == HAL_COMP_STATE_READY) + { + /* Enable the selected comparator */ + if(hcomp->Instance == COMP2) + { + regshift = COMP_CSR_COMP2_SHIFT; + } + SET_BIT(COMP->CSR, (uint32_t)COMP_CSR_COMPxEN << regshift); + + hcomp->State = HAL_COMP_STATE_BUSY; + } + else + { + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief Stop the comparator + * @param hcomp: COMP handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t regshift = COMP_CSR_COMP1_SHIFT; + + /* Check the COMP handle allocation and lock status */ + if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET)) + { + status = HAL_ERROR; + } + else + { + /* Check the parameter */ + assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); + + if(hcomp->State == HAL_COMP_STATE_BUSY) + { + /* Disable the selected comparator */ + if(hcomp->Instance == COMP2) + { + regshift = COMP_CSR_COMP2_SHIFT; + } + CLEAR_BIT(COMP->CSR, (uint32_t)COMP_CSR_COMPxEN << regshift); + + hcomp->State = HAL_COMP_STATE_READY; + } + else + { + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief Enables the interrupt and starts the comparator + * @param hcomp: COMP handle + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t extiline = 0; + + /* Check the parameter */ + assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode)); + + status = HAL_COMP_Start(hcomp); + if(status == HAL_OK) + { + /* Check the Exti Line output configuration */ + extiline = __HAL_COMP_GET_EXTI_LINE(hcomp->Instance); + /* Configure the rising edge */ + if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_RISING) != RESET) + { + __HAL_COMP_EXTI_RISING_IT_ENABLE(extiline); + } + else + { + __HAL_COMP_EXTI_RISING_IT_DISABLE(extiline); + } + /* Configure the falling edge */ + if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_FALLING) != RESET) + { + __HAL_COMP_EXTI_FALLING_IT_ENABLE(extiline); + } + else + { + __HAL_COMP_EXTI_FALLING_IT_DISABLE(extiline); + } + /* Enable Exti interrupt mode */ + __HAL_COMP_EXTI_ENABLE_IT(extiline); + /* Clear COMP Exti pending bit */ + __HAL_COMP_EXTI_CLEAR_FLAG(extiline); + } + + return status; +} + +/** + * @brief Disable the interrupt and Stop the comparator + * @param hcomp: COMP handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Disable the Exti Line interrupt mode */ + __HAL_COMP_EXTI_DISABLE_IT(__HAL_COMP_GET_EXTI_LINE(hcomp->Instance)); + + status = HAL_COMP_Stop(hcomp); + + return status; +} + +/** + * @brief Comparator IRQ Handler + * @param hcomp: COMP handle + * @retval HAL status + */ +void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) +{ + uint32_t extiline = __HAL_COMP_GET_EXTI_LINE(hcomp->Instance); + + /* Check COMP Exti flag */ + if(__HAL_COMP_EXTI_GET_FLAG(extiline) != RESET) + { + /* Clear COMP Exti pending bit */ + __HAL_COMP_EXTI_CLEAR_FLAG(extiline); + + /* COMP trigger user callback */ + HAL_COMP_TriggerCallback(hcomp); + } +} + +/** + * @} + */ + +/** @defgroup COMP_Exported_Functions_Group3 Peripheral Control functions + * @brief management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the COMP data + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Lock the selected comparator configuration. + * @param hcomp: COMP handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t regshift = COMP_CSR_COMP1_SHIFT; + + /* Check the COMP handle allocation and lock status */ + if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET)) + { + status = HAL_ERROR; + } + else + { + /* Check the parameter */ + assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); + + /* Set lock flag */ + hcomp->State |= COMP_STATE_BIT_LOCK; + + /* Set the lock bit corresponding to selected comparator */ + if(hcomp->Instance == COMP2) + { + regshift = COMP_CSR_COMP2_SHIFT; + } + SET_BIT(COMP->CSR, (uint32_t)COMP_CSR_COMPxLOCK << regshift); + } + + return status; +} + +/** + * @brief Return the output level (high or low) of the selected comparator. + * The output level depends on the selected polarity. + * If the polarity is not inverted: + * - Comparator output is low when the non-inverting input is at a lower + * voltage than the inverting input + * - Comparator output is high when the non-inverting input is at a higher + * voltage than the inverting input + * If the polarity is inverted: + * - Comparator output is high when the non-inverting input is at a lower + * voltage than the inverting input + * - Comparator output is low when the non-inverting input is at a higher + * voltage than the inverting input + * @param hcomp: COMP handle + * @retval Returns the selected comparator output level: COMP_OUTPUTLEVEL_LOW or COMP_OUTPUTLEVEL_HIGH. + * + */ +uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp) +{ + uint32_t level=0; + uint32_t regshift = COMP_CSR_COMP1_SHIFT; + + /* Check the parameter */ + assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); + + if(hcomp->Instance == COMP2) + { + regshift = COMP_CSR_COMP2_SHIFT; + } + level = READ_BIT(COMP->CSR, (uint32_t)COMP_CSR_COMPxOUT << regshift); + + if(level != 0) + { + return(COMP_OUTPUTLEVEL_HIGH); + } + return(COMP_OUTPUTLEVEL_LOW); +} + +/** + * @brief Comparator callback. + * @param hcomp: COMP handle + * @retval None + */ +__weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_COMP_TriggerCallback should be implemented in the user file + */ +} + + +/** + * @} + */ + +/** @defgroup COMP_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permit to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the COMP state + * @param hcomp : COMP handle + * @retval HAL state + */ +HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp) +{ + /* Check the COMP handle allocation */ + if(hcomp == NULL) + { + return HAL_COMP_STATE_RESET; + } + + /* Check the parameter */ + assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); + + return hcomp->State; +} +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_COMP_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || defined (STM32F098xx) */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c @@ -0,0 +1,342 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_cortex.c + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief CORTEX HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the CORTEX: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + * @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + + [..] + *** How to configure Interrupts using CORTEX HAL driver *** + =========================================================== + [..] + This section provides functions allowing to configure the NVIC interrupts (IRQ). + The Cortex-M0 exceptions are managed by CMSIS functions. + (#) Enable and Configure the priority of the selected IRQ Channels. + The priority can be 0..3. + + -@- Lower priority values gives higher priority. + -@- Priority Order: + (#@) Lowest priority. + (#@) Lowest hardware priority (IRQn position). + + (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority() + + (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ() + + + [..] + *** How to configure Systick using CORTEX HAL driver *** + ======================================================== + [..] + Setup SysTick Timer for time base + + (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which + is a CMSIS function that: + (++) Configures the SysTick Reload register with value passed as function parameter. + (++) Configures the SysTick IRQ priority to the lowest value (0x03). + (++) Resets the SysTick Counter register. + (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). + (++) Enables the SysTick Interrupt. + (++) Starts the SysTick Counter. + + (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro + __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the + HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined + inside the stm32f0xx_hal_cortex.h file. + + (+) You can change the SysTick IRQ priority by calling the + HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function + call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. + + (+) To adjust the SysTick time base, use the following formula: + + Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) + (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function + (++) Reload Value should not exceed 0xFFFFFF + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup CORTEX CORTEX HAL module driver + * @brief CORTEX CORTEX HAL module driver + * @{ + */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions + * @{ + */ + + +/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] + This section provides the CORTEX HAL driver functions allowing to configure Interrupts + Systick functionalities + +@endverbatim + * @{ + */ + +/** + * @brief Sets the priority of an interrupt. + * @param IRQn: External interrupt number . + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file) + * @param PreemptPriority: The pre-emption priority for the IRQn channel. + * This parameter can be a value between 0 and 3. + * A lower priority value indicates a higher priority + * @param SubPriority: The subpriority level for the IRQ channel. + * with stm32f0xx devices, this parameter is a dummy value and it is ignored, because + * no subpriority supported in Cortex M0 based products. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + NVIC_SetPriority(IRQn,PreemptPriority); +} + +/** + * @brief Enables a device specific interrupt in the NVIC interrupt controller. + * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() + * function should be called before. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); +} + +/** + * @brief Disables a device specific interrupt in the NVIC interrupt controller. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) + * @retval None + */ +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) +{ + /* Disable interrupt */ + NVIC_DisableIRQ(IRQn); +} + +/** + * @brief Initiates a system reset request to reset the MCU. + * @retval None + */ +void HAL_NVIC_SystemReset(void) +{ + /* System Reset */ + NVIC_SystemReset(); +} + +/** + * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. + * Counter is in free running mode to generate periodic interrupts. + * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + return SysTick_Config(TicksNumb); +} +/** + * @} + */ + +/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions + * @brief Cortex control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the CORTEX + (NVIC, SYSTICK) functionalities. + + +@endverbatim + * @{ + */ + + +/** + * @brief Gets the priority of an interrupt. + * @param IRQn: External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) + * @retval None + */ +uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn) +{ + /* Get priority for Cortex-M system or device specific interrupts */ + return NVIC_GetPriority(IRQn); +} + +/** + * @brief Sets Pending bit of an external interrupt. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) + * @retval None + */ +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + /* Set interrupt pending */ + NVIC_SetPendingIRQ(IRQn); +} + +/** + * @brief Gets Pending Interrupt (reads the pending register in the NVIC + * and returns the pending bit for the specified interrupt). + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + /* Return 1 if pending else 0 */ + return NVIC_GetPendingIRQ(IRQn); +} + +/** + * @brief Clears the pending bit of an external interrupt. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) + * @retval None + */ +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + /* Clear pending interrupt */ + NVIC_ClearPendingIRQ(IRQn); +} + +/** + * @brief Configures the SysTick clock source. + * @param CLKSource: specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. + * @retval None + */ +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); + if (CLKSource == SYSTICK_CLKSOURCE_HCLK) + { + SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; + } + else + { + SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; + } +} + +/** + * @brief This function handles SYSTICK interrupt request. + * @retval None + */ +void HAL_SYSTICK_IRQHandler(void) +{ + HAL_SYSTICK_Callback(); +} + +/** + * @brief SYSTICK callback. + * @retval None + */ +__weak void HAL_SYSTICK_Callback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SYSTICK_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_CORTEX_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_crc.c b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_crc.c new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_crc.c @@ -0,0 +1,506 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_crc.c + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief CRC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Cyclic Redundancy Check (CRC) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + Peripheral State functions + * + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + (#) Enable CRC AHB clock using __CRC_CLK_ENABLE(); + (#) Initialize CRC calculator + (++)specify generating polynomial (IP default or non-default one) + (++)specify initialization value (IP default or non-default one) + (++)specify input data format + (++)specify input or output data inversion mode if any + (#) Use HAL_CRC_Accumulate() function to compute the CRC value of the + input data buffer starting with the previously computed CRC as + initialization value + (#) Use HAL_CRC_Calculate() function to compute the CRC value of the + input data buffer starting with the defined initialization value + (default or non-default) to initiate CRC calculation + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup CRC CRC HAL module driver + * @brief CRC HAL module driver. + * @{ + */ + +#ifdef HAL_CRC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup CRC_Private_Functions CRC Private Functions + * @{ + */ +static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength); +static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup CRC_Exported_Functions CRC Exported Functions + * @{ + */ + +/** @defgroup CRC_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions. + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize the CRC according to the specified parameters + in the CRC_InitTypeDef and create the associated handle + (+) DeInitialize the CRC peripheral + (+) Initialize the CRC MSP + (+) DeInitialize CRC MSP + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the CRC according to the specified + * parameters in the CRC_InitTypeDef and creates the associated handle. + * @param hcrc: CRC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) +{ + /* Check the CRC handle allocation */ + if(hcrc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); + + if(hcrc->State == HAL_CRC_STATE_RESET) + { + /* Init the low level hardware */ + HAL_CRC_MspInit(hcrc); + } + + hcrc->State = HAL_CRC_STATE_BUSY; + + /* Extended initialization: if programmable polynomial feature is + applicable to device, set default or non-default generating + polynomial according to hcrc->Init parameters. + If feature is non-applicable to device in use, HAL_CRCEx_Init straight + away reports HAL_OK. */ + if (HAL_CRCEx_Init(hcrc) != HAL_OK) + { + return HAL_ERROR; + } + + /* check whether or not non-default CRC initial value has been + * picked up by user */ + assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse)); + if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE) + { + WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE); + } + else + { + WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue); + } + + + /* set input data inversion mode */ + assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode)); + MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode); + + /* set output data inversion mode */ + assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode)); + MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode); + + /* makes sure the input data format (bytes, halfwords or words stream) + * is properly specified by user */ + assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat)); + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief DeInitializes the CRC peripheral. + * @param hcrc: CRC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) +{ + /* Check the CRC handle allocation */ + if(hcrc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); + + /* Check the CRC peripheral state */ + if(hcrc->State == HAL_CRC_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_BUSY; + + /* DeInit the low level hardware */ + HAL_CRC_MspDeInit(hcrc); + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_RESET; + + /* Process unlocked */ + __HAL_UNLOCK(hcrc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the CRC MSP. + * @param hcrc: CRC handle + * @retval None + */ +__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CRC_MspInit can be implemented in the user file + */ +} + +/** + * @brief DeInitializes the CRC MSP. + * @param hcrc: CRC handle + * @retval None + */ +__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CRC_MspDeInit can be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions + * @brief management functions. + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer + using combination of the previous CRC value and the new one. + + or + + (+) Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer + independently of the previous CRC value. + +@endverbatim + * @{ + */ + +/** + * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer + * starting with the previously computed CRC as initialization value. + * @param hcrc: CRC handle + * @param pBuffer: pointer to the input data buffer, exact input data format is + * provided by hcrc->InputDataFormat. + * @param BufferLength: input data buffer length + * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) + */ +uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index = 0; /* CRC input data buffer index */ + uint32_t temp = 0; /* CRC output (read from hcrc->Instance->DR register) */ + + /* Process locked */ + __HAL_LOCK(hcrc); + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_BUSY; + + switch (hcrc->InputDataFormat) + { + case CRC_INPUTDATA_FORMAT_WORDS: + /* Enter Data to the CRC calculator */ + for(index = 0; index < BufferLength; index++) + { + hcrc->Instance->DR = pBuffer[index]; + } + temp = hcrc->Instance->DR; + break; + + case CRC_INPUTDATA_FORMAT_BYTES: + temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength); + break; + + case CRC_INPUTDATA_FORMAT_HALFWORDS: + temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength); + break; + + default: + break; + } + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcrc); + + /* Return the CRC computed value */ + return temp; +} + + +/** + * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer + * starting with hcrc->Instance->INIT as initialization value. + * @param hcrc: CRC handle + * @param pBuffer: pointer to the input data buffer, exact input data format is + * provided by hcrc->InputDataFormat. + * @param BufferLength: input data buffer length + * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) + */ +uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index = 0; /* CRC input data buffer index */ + uint32_t temp = 0; /* CRC output (read from hcrc->Instance->DR register) */ + + /* Process locked */ + __HAL_LOCK(hcrc); + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_BUSY; + + /* Reset CRC Calculation Unit (hcrc->Instance->INIT is + * written in hcrc->Instance->DR) */ + __HAL_CRC_DR_RESET(hcrc); + + switch (hcrc->InputDataFormat) + { + case CRC_INPUTDATA_FORMAT_WORDS: + /* Enter 32-bit input data to the CRC calculator */ + for(index = 0; index < BufferLength; index++) + { + hcrc->Instance->DR = pBuffer[index]; + } + temp = hcrc->Instance->DR; + break; + + case CRC_INPUTDATA_FORMAT_BYTES: + /* Specific 8-bit input data handling */ + temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength); + break; + + case CRC_INPUTDATA_FORMAT_HALFWORDS: + /* Specific 16-bit input data handling */ + temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength); + break; + + default: + break; + } + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcrc); + + /* Return the CRC computed value */ + return temp; +} +/** + * @} + */ + +/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions + * @brief Peripheral State functions. + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the CRC state. + * @param hcrc: CRC handle + * @retval HAL state + */ +HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc) +{ + return hcrc->State; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup CRC_Private_Functions CRC Private Functions + * @{ + */ +/** + * @brief Enter 8-bit input data to the CRC calculator. + * Specific data handling to optimize processing time. + * @param hcrc: CRC handle + * @param pBuffer: pointer to the input data buffer + * @param BufferLength: input data buffer length + * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) + */ +static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength) +{ + uint32_t i = 0; /* input data buffer index */ + + /* Processing time optimization: 4 bytes are entered in a row with a single word write, + * last bytes must be carefully fed to the CRC calculator to ensure a correct type + * handling by the IP */ + for(i = 0; i < (BufferLength/4); i++) + { + hcrc->Instance->DR = ((uint32_t)pBuffer[4*i]<<24) | ((uint32_t)pBuffer[4*i+1]<<16) | ((uint32_t)pBuffer[4*i+2]<<8) | (uint32_t)pBuffer[4*i+3]; + } + /* last bytes specific handling */ + if ((BufferLength%4) != 0) + { + if (BufferLength%4 == 1) + { + *(uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i]; + } + if (BufferLength%4 == 2) + { + *(uint16_t*) (&hcrc->Instance->DR) = ((uint16_t)pBuffer[4*i]<<8) | (uint16_t)pBuffer[4*i+1]; + } + if (BufferLength%4 == 3) + { + *(uint16_t*) (&hcrc->Instance->DR) = ((uint16_t)pBuffer[4*i]<<8) | (uint16_t)pBuffer[4*i+1]; + *(uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i+2]; + } + } + + /* Return the CRC computed value */ + return hcrc->Instance->DR; +} + + + +/** + * @brief Enter 16-bit input data to the CRC calculator. + * Specific data handling to optimize processing time. + * @param hcrc: CRC handle + * @param pBuffer: pointer to the input data buffer + * @param BufferLength: input data buffer length + * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) + */ +static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength) +{ + uint32_t i = 0; /* input data buffer index */ + + /* Processing time optimization: 2 HalfWords are entered in a row with a single word write, + * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure + * a correct type handling by the IP */ + for(i = 0; i < (BufferLength/2); i++) + { + hcrc->Instance->DR = (pBuffer[2*i]<<16) | pBuffer[2*i+1]; + } + if ((BufferLength%2) != 0) + { + *(uint16_t*) (&hcrc->Instance->DR) = pBuffer[2*i]; + } + + /* Return the CRC computed value */ + return hcrc->Instance->DR; +} +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_CRC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_crc_ex.c b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_crc_ex.c new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_crc_ex.c @@ -0,0 +1,275 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_crc_ex.c + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Extended CRC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the CRC peripheral: + * + Extended initialization functions + * + @verbatim +================================================================================ + ##### Product specific features ##### +================================================================================ + + ##### How to use this driver ##### +================================================================================ + [..] + (+) Extended initialization + (+) Set or not user-defined generating + polynomial other than default one + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup CRCEx CRCEx Extended HAL Module Driver + * @brief CRC Extended HAL module driver + * @{ + */ + +#ifdef HAL_CRC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup CRCEx_Exported_Functions CRCEx Exported Functions + * @{ + */ + +/** @defgroup CRCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions + * @brief Extended Initialization and Configuration functions. + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize the CRC generating polynomial: if programmable polynomial + feature is applicable to device, set default or non-default generating + polynomial according to hcrc->Init.DefaultPolynomialUse parameter. + If feature is non-applicable to device in use, HAL_CRCEx_Init straight + away reports HAL_OK. + (+) Set the generating polynomial + +@endverbatim + * @{ + */ + + +/** + * @brief Extended initialization to set generating polynomial + * @param hcrc: CRC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRCEx_Init(CRC_HandleTypeDef *hcrc) +{ +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined (STM32F098xx) + /* check whether or not non-default generating polynomial has been + * picked up by user */ + assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse)); + if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE) + { + /* initialize IP with default generating polynomial */ + WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY); + MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B); + } + else + { + /* initialize CRC IP with generating polynomial defined by user */ + if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK) + { + return HAL_ERROR; + } + } +#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined (STM32F098xx) */ + + return HAL_OK; +} + +/** + * @brief Set the Reverse Input data mode. + * @param hcrc: CRC handle + * @param InputReverseMode: Input Data inversion mode + * This parameter can be one of the following values: + * @arg CRC_INPUTDATA_NOINVERSION: no change in bit order (default value) + * @arg CRC_INPUTDATA_INVERSION_BYTE: Byte-wise bit reversal + * @arg CRC_INPUTDATA_INVERSION_HALFWORD: HalfWord-wise bit reversal + * @arg CRC_INPUTDATA_INVERSION_WORD: Word-wise bit reversal + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode) +{ + /* Check the parameters */ + assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode)); + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_BUSY; + + /* set input data inversion mode */ + MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode); + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Set the Reverse Output data mode. + * @param hcrc: CRC handle + * @param OutputReverseMode: Output Data inversion mode + * This parameter can be one of the following values: + * @arg CRC_OUTPUTDATA_INVERSION_DISABLED: no CRC inversion (default value) + * @arg CRC_OUTPUTDATA_INVERSION_ENABLED: bit-level inversion (e.g for a 8-bit CRC: 0xB5 becomes 0xAD) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode) +{ + /* Check the parameters */ + assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode)); + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_BUSY; + + /* set output data inversion mode */ + MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode); + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F091xC) || defined (STM32F098xx) +/** + * @brief Initializes the CRC polynomial if different from default one. + * @param hcrc: CRC handle + * @param Pol: CRC generating polynomial (7, 8, 16 or 32-bit long) + * This parameter is written in normal representation, e.g. + * for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65 + * for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021 + * @param PolyLength: CRC polynomial length + * This parameter can be one of the following values: + * @arg CRC_POLYLENGTH_7B: 7-bit long CRC (generating polynomial of degree 7) + * @arg CRC_POLYLENGTH_8B: 8-bit long CRC (generating polynomial of degree 8) + * @arg CRC_POLYLENGTH_16B: 16-bit long CRC (generating polynomial of degree 16) + * @arg CRC_POLYLENGTH_32B: 32-bit long CRC (generating polynomial of degree 32) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength) +{ + uint32_t msb = 31; /* polynomial degree is 32 at most, so msb is initialized to max value */ + + /* Check the parameters */ + assert_param(IS_CRC_POL_LENGTH(PolyLength)); + + /* check polynomial definition vs polynomial size: + * polynomial length must be aligned with polynomial + * definition. HAL_ERROR is reported if Pol degree is + * larger than that indicated by PolyLength. + * Look for MSB position: msb will contain the degree of + * the second to the largest polynomial member. E.g., for + * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */ + while (((Pol & (1U << msb)) == 0) && (msb-- > 0)) + {} + + switch (PolyLength) + { + case CRC_POLYLENGTH_7B: + if (msb >= HAL_CRC_LENGTH_7B) + { + return HAL_ERROR; + } + break; + case CRC_POLYLENGTH_8B: + if (msb >= HAL_CRC_LENGTH_8B) + { + return HAL_ERROR; + } + break; + case CRC_POLYLENGTH_16B: + if (msb >= HAL_CRC_LENGTH_16B) + { + return HAL_ERROR; + } + break; + case CRC_POLYLENGTH_32B: + /* no polynomial definition vs. polynomial length issue possible */ + break; + default: + break; + } + + /* set generating polynomial */ + WRITE_REG(hcrc->Instance->POL, Pol); + + /* set generating polynomial size */ + MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength); + + /* Return function status */ + return HAL_OK; +} +#endif /* #if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F091xC) || defined (STM32F098xx) */ + +/** + * @} + */ + + +/** + * @} + */ + + +#endif /* HAL_CRC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dac.c b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dac.c new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dac.c @@ -0,0 +1,684 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_dac.c + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief DAC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Digital to Analog Converter (DAC) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Errors functions + * + * + @verbatim + ============================================================================== + ##### DAC Peripheral features ##### + ============================================================================== + [..] + *** DAC Channels *** + ==================== + [..] + STM32F0 devices integrates no, one or two 12-bit Digital Analog Converters. + STM32F05x devices have one converter (channel1) + STM32F07x & STM32F09x devices have two converters (i.e. channel1 & channel2) + + When 2 converters are present (i.e. channel1 & channel2) they + can be used independently or simultaneously (dual mode): + (#) DAC channel1 with DAC_OUT1 (PA4) as output + (#) DAC channel2 with DAC_OUT2 (PA5) as output + + *** DAC Triggers *** + ==================== + [..] + Digital to Analog conversion can be non-triggered using DAC_Trigger_None + and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register. + [..] + Digital to Analog conversion can be triggered by: + (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9. + The used pin (GPIOx_Pin9) must be configured in input mode. + + (#) Timers TRGO: TIM2, TIM3, TIM6, and TIM15 + (DAC_Trigger_T2_TRGO, DAC_Trigger_T3_TRGO...) + + (#) Software using DAC_Trigger_Software + + *** DAC Buffer mode feature *** + =============================== + [..] + Each DAC channel integrates an output buffer that can be used to + reduce the output impedance, and to drive external loads directly + without having to add an external operational amplifier. + To enable, the output buffer use + sConfig.DAC_OutputBuffer = DAC_OutputBuffer_Enable; + [..] + (@) Refer to the device datasheet for more details about output + impedance value with and without output buffer. + + *** DAC wave generation feature *** + =================================== + [..] + Both DAC channels can be used to generate + (#) Noise wave + (#) Triangle wave + + *** DAC data format *** + ======================= + [..] + The DAC data format can be: + (#) 8-bit right alignment using DAC_ALIGN_8B_R + (#) 12-bit left alignment using DAC_ALIGN_12B_L + (#) 12-bit right alignment using DAC_ALIGN_12B_R + + *** DAC data value to voltage correspondence *** + ================================================ + [..] + The analog output voltage on each DAC channel pin is determined + by the following equation: + DAC_OUTx = VREF+ * DOR / 4095 + with DOR is the Data Output Register + VEF+ is the input voltage reference (refer to the device datasheet) + e.g. To set DAC_OUT1 to 0.7V, use + Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V + + *** DMA requests *** + ===================== + [..] + A DMA1 request can be generated when an external trigger (but not + a software trigger) occurs if DMA1 requests are enabled using + HAL_DAC_Start_DMA() + [..] + DMA1 requests are mapped as following: + (#) DAC channel1 : mapped on DMA1 channel3 which must be + already configured + (#) DAC channel2 : mapped on DMA1 channel4 which must be + already configured + + -@- For Dual mode and specific signal (Triangle and noise) generation please + refer to Extension Features Driver description + STM32F0 devices with one channel (one converting capability) does not + support Dual mode and specific signal (Triangle and noise) generation. + + ##### How to use this driver ##### + ============================================================================== + [..] + (+) DAC APB clock must be enabled to get write access to DAC + registers using HAL_DAC_Init() + (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode. + (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function. + (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA functions + + *** Polling mode IO operation *** + ================================= + [..] + (+) Start the DAC peripheral using HAL_DAC_Start() + (+) To read the DAC last data output value value, use the HAL_DAC_GetValue() function. + (+) Stop the DAC peripheral using HAL_DAC_Stop() + + *** DMA mode IO operation *** + ============================== + [..] + (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length + of data to be transfered at each end of conversion + (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DAC_ConvCpltCallbackCh2() + function is executed and user can add his own code by customization of function pointer + HAL_DAC_ConvCpltCallbackCh1 or HAL_DAC_ConvCpltCallbackCh2 + (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can + add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1 + (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA() + + *** DAC HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in DAC HAL driver. + + (+) __HAL_DAC_ENABLE : Enable the DAC peripheral + (+) __HAL_DAC_DISABLE : Disable the DAC peripheral + (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags + (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status + + [..] + (@) You can refer to the DAC HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup DAC DAC HAL module driver + * @brief DAC driver modules + * @{ + */ + +#ifdef HAL_DAC_MODULE_ENABLED + +#if defined(STM32F051x8) || defined(STM32F058xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined (STM32F098xx) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup DAC_Exported_Functions DAC Exported Functions + * @{ + */ + +/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the DAC. + (+) De-initialize the DAC. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the DAC peripheral according to the specified parameters + * in the DAC_InitStruct. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac) +{ + /* Check DAC handle */ + if(hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ + assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance)); + + if(hdac->State == HAL_DAC_STATE_RESET) + { + /* Init the low level hardware */ + HAL_DAC_MspInit(hdac); + } + + /* Initialize the DAC state*/ + hdac->State = HAL_DAC_STATE_BUSY; + + /* Set DAC error code to none */ + hdac->ErrorCode = HAL_DAC_ERROR_NONE; + + /* Initialize the DAC state*/ + hdac->State = HAL_DAC_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Deinitializes the DAC peripheral registers to their default reset values. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac) +{ + /* Check DAC handle */ + if(hdac == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance)); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_BUSY; + + /* DeInit the low level hardware */ + HAL_DAC_MspDeInit(hdac); + + /* Set DAC error code to none */ + hdac->ErrorCode = HAL_DAC_ERROR_NONE; + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdac); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the DAC MSP. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DAC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the DAC MSP. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DAC_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup DAC_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Start conversion. + (+) Stop conversion. + (+) Start conversion and enable DMA transfer. + (+) Stop conversion and disable DMA transfer. + (+) Get result of conversion. + +@endverbatim + * @{ + */ + +/** + * @brief Enables DAC and starts conversion of channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) +{ + /* Note : This function is defined into this file for library reference. */ + /* Function content is located into file stm32f0xx_hal_dac_ex.c */ + + /* Return error status as not implemented here */ + return HAL_ERROR; +} + +/** + * @brief Disables DAC and stop conversion of channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + + /* Disable the Peripheral */ + __HAL_DAC_DISABLE(hdac, Channel); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Enables DAC and starts conversion of channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @param pData: The destination peripheral Buffer address. + * @param Length: The length of data to be transferred from memory to DAC peripheral + * @param Alignment: Specifies the data alignment for DAC channel. + * This parameter can be one of the following values: + * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected + * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected + * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment) +{ + /* Note : This function is defined into this file for library reference. */ + /* Function content is located into file stm32f0xx_hal_dac_ex.c */ + + /* Return error status as not implemented here */ + return HAL_ERROR; +} + +/** + * @brief Disables DAC and stop conversion of channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + + /* Disable the selected DAC channel DMA request */ + hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel); + + /* Disable the Peripharal */ + __HAL_DAC_DISABLE(hdac, Channel); + + /* Disable the DMA Channel */ + /* Channel1 is used */ + if (Channel == DAC_CHANNEL_1) + { + status = HAL_DMA_Abort(hdac->DMA_Handle1); + } + else /* Channel2 is used for */ + { + status = HAL_DMA_Abort(hdac->DMA_Handle2); + } + + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; + + /* Return function status */ + return status; +} + +/** + * @brief Conversion complete callback in non blocking mode for Channel1 + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DAC_ConvCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Conversion half DMA transfer callback in non blocking mode for Channel1 + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file + */ +} + +/** + * @brief Error DAC callback for Channel1. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DAC_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief DMA underrun DAC callback for channel1. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Configure channels. + (+) Set the specified data holding register value for DAC channel. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the selected DAC channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param sConfig: DAC configuration structure. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel) +{ + /* Note : This function is defined into this file for library reference. */ + /* Function content is located into file stm32f0xx_hal_dac_ex.c */ + + /* Return error status as not implemented here */ + return HAL_ERROR; +} + +/** + * @brief Set the specified data holding register value for DAC channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @param Alignment: Specifies the data alignment. + * This parameter can be one of the following values: + * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected + * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected + * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected + * @param Data: Data to be loaded in the selected data holding register. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + assert_param(IS_DAC_ALIGN(Alignment)); + assert_param(IS_DAC_DATA(Data)); + + tmp = (uint32_t)hdac->Instance; + if(Channel == DAC_CHANNEL_1) + { + tmp += __HAL_DHR12R1_ALIGNEMENT(Alignment); + } + else + { + tmp += __HAL_DHR12R2_ALIGNEMENT(Alignment); + } + + /* Set the DAC channel1 selected data holding register */ + *(__IO uint32_t *) tmp = Data; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Returns the last data output value of the selected DAC channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @retval The selected DAC channel data output value. + */ +__weak uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel) +{ + /* Note : This function is defined into this file for library reference. */ + /* Function content is located into file stm32f0xx_hal_dac_ex.c */ + + /* Return error status as not implemented here */ + return HAL_ERROR; +} + +/** + * @} + */ + +/** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Errors functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the DAC state. + (+) Check the DAC Errors. + +@endverbatim + * @{ + */ + +/** + * @brief return the DAC state + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval HAL state + */ +HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac) +{ + /* Return DAC state */ + return hdac->State; +} + + +/** + * @brief Return the DAC error code + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval DAC Error Code + */ +uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac) +{ + return hdac->ErrorCode; +} + +/** + * @brief Handles DAC interrupt request + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) +{ + /* Note : This function is defined into this file for library reference. */ + /* Function content is located into file stm32f0xx_hal_dac_ex.c */ +} + +/** + * @} + */ + + +/** + * @} + */ +#endif /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#endif /* HAL_DAC_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dac_ex.c b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dac_ex.c new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dac_ex.c @@ -0,0 +1,1082 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_dac_ex.c + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief DAC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of DAC extension peripheral: + * + Extended features functions + * + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (+) When Dual mode is enabled (i.e DAC Channel1 and Channel2 are used simultaneously) : + Use HAL_DACEx_DualGetValue() to get digital data to be converted and use + HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2. + (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal. + (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup DACEx DACEx Extended HAL module driver + * @brief DACEx driver module + * @{ + */ + +#ifdef HAL_DAC_MODULE_ENABLED + +#if defined(STM32F051x8) || defined(STM32F058xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup DACEx_Private_Functions DACEx Private Functions + * @{ + */ +static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma); +static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma); +static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/** @defgroup DACEx_Exported_Functions DACEx Exported Functions + * @{ + */ + +/** @defgroup DACEx_Exported_Functions_Group1 Extended features functions + * @brief Extended features functions + * +@verbatim + ============================================================================== + ##### Extended features functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Start conversion. + (+) Stop conversion. + (+) Start conversion and enable DMA transfer. + (+) Stop conversion and disable DMA transfer. + (+) Get result of conversion. + (+) Get result of dual mode conversion. + +@endverbatim + * @{ + */ + +#endif /* STM32F051x8 STM32F058xx */ + /* STM32F071xB STM32F072xB STM32F078xx */ + /* STM32F091xC STM32F098xx */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +/** + * @brief Configures the selected DAC channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param sConfig: DAC configuration structure. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + + /* Check the DAC parameters */ + assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger)); + assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer)); + assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger)); + assert_param(IS_DAC_CHANNEL(Channel)); + + /* Process locked */ + __HAL_LOCK(hdac); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_BUSY; + + /* Get the DAC CR value */ + tmpreg1 = DAC->CR; + /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ + tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel); + /* Configure for the selected DAC channel: buffer output, trigger */ + /* Set TSELx and TENx bits according to DAC_Trigger value */ + /* Set BOFFx bit according to DAC_OutputBuffer value */ + tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer); + /* Calculate CR register value depending on DAC_Channel */ + tmpreg1 |= tmpreg2 << Channel; + /* Write to DAC CR */ + DAC->CR = tmpreg1; + /* Disable wave generation */ + DAC->CR &= ~(DAC_CR_WAVE1 << Channel); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hdac); + + /* Return function status */ + return HAL_OK; +} + +#endif /* STM32F071xB STM32F072xB STM32F078xx */ + /* STM32F091xC STM32F098xx */ + +#if defined (STM32F051x8) || defined (STM32F058xx) + +/** + * @brief Configures the selected DAC channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param sConfig: DAC configuration structure. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + + /* Check the DAC parameters */ + assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger)); + assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer)); + assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger)); + assert_param(IS_DAC_CHANNEL(Channel)); + + /* Process locked */ + __HAL_LOCK(hdac); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_BUSY; + + /* Get the DAC CR value */ + tmpreg1 = DAC->CR; + /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ + // tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel); + tmpreg1 &= ~(((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel); + /* Configure for the selected DAC channel: buffer output, trigger */ + /* Set TSELx and TENx bits according to DAC_Trigger value */ + /* Set BOFFx bit according to DAC_OutputBuffer value */ + tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer); + /* Calculate CR register value depending on DAC_Channel */ + tmpreg1 |= tmpreg2 << Channel; + /* Write to DAC CR */ + DAC->CR = tmpreg1; + /* Disable wave generation */ + // DAC->CR &= ~(DAC_CR_WAVE1 << Channel); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hdac); + + /* Return function status */ + return HAL_OK; +} + +#endif /* STM32F051x8 STM32F058xx */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) +/* DAC 1 has 2 channels 1 & 2 */ + +/** + * @brief Returns the last data output value of the selected DAC channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @retval The selected DAC channel data output value. + */ +uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + + /* Returns the DAC channel data output register value */ + if(Channel == DAC_CHANNEL_1) + { + return hdac->Instance->DOR1; + } + else + { + return hdac->Instance->DOR2; + } +} + +#endif /* STM32F071xB STM32F072xB STM32F078xx */ + /* STM32F091xC STM32F098xx */ + +#if defined (STM32F051x8) || defined (STM32F058xx) + +/* DAC 1 has 1 channels */ + +/** + * @brief Returns the last data output value of the selected DAC channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @retval The selected DAC channel data output value. + */ +uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + + /* Returns the DAC channel data output register value */ + return hdac->Instance->DOR1; +} + + + +#endif /* STM32F051x8 STM32F058xx */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +/** + * @brief Enables DAC and starts conversion of channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) +{ + uint32_t tmp1 = 0, tmp2 = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + + /* Process locked */ + __HAL_LOCK(hdac); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_BUSY; + + /* Enable the Peripharal */ + __HAL_DAC_ENABLE(hdac, Channel); + + if(Channel == DAC_CHANNEL_1) + { + tmp1 = hdac->Instance->CR & DAC_CR_TEN1; + tmp2 = hdac->Instance->CR & DAC_CR_TSEL1; + /* Check if software trigger enabled */ + if((tmp1 == DAC_CR_TEN1) && (tmp2 == DAC_CR_TSEL1)) + { + /* Enable the selected DAC software conversion */ + hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1; + } + } + else + { + tmp1 = hdac->Instance->CR & DAC_CR_TEN2; + tmp2 = hdac->Instance->CR & DAC_CR_TSEL2; + /* Check if software trigger enabled */ + if((tmp1 == DAC_CR_TEN2) && (tmp2 == DAC_CR_TSEL2)) + { + /* Enable the selected DAC software conversion*/ + hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG2; + } + } + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hdac); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Enables DAC and starts conversion of channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @param pData: The destination peripheral Buffer address. + * @param Length: The length of data to be transferred from memory to DAC peripheral + * @param Alignment: Specifies the data alignment for DAC channel. + * This parameter can be one of the following values: + * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected + * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected + * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + assert_param(IS_DAC_ALIGN(Alignment)); + + /* Process locked */ + __HAL_LOCK(hdac); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_BUSY; + + if(Channel == DAC_CHANNEL_1) + { + /* Set the DMA transfer complete callback for channel1 */ + hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1; + + /* Set the DMA half transfer complete callback for channel1 */ + hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1; + + /* Set the DMA error callback for channel1 */ + hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1; + + /* Enable the selected DAC channel1 DMA request */ + hdac->Instance->CR |= DAC_CR_DMAEN1; + + /* Case of use of channel 1 */ + switch(Alignment) + { + case DAC_ALIGN_12B_R: + /* Get DHR12R1 address */ + tmpreg = (uint32_t)&hdac->Instance->DHR12R1; + break; + case DAC_ALIGN_12B_L: + /* Get DHR12L1 address */ + tmpreg = (uint32_t)&hdac->Instance->DHR12L1; + break; + case DAC_ALIGN_8B_R: + /* Get DHR8R1 address */ + tmpreg = (uint32_t)&hdac->Instance->DHR8R1; + break; + default: + break; + } + } + else + { + /* Set the DMA transfer complete callback for channel2 */ + hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2; + + /* Set the DMA half transfer complete callback for channel2 */ + hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2; + + /* Set the DMA error callback for channel2 */ + hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2; + + /* Enable the selected DAC channel2 DMA request */ + hdac->Instance->CR |= DAC_CR_DMAEN2; + + /* Case of use of channel 2 */ + switch(Alignment) + { + case DAC_ALIGN_12B_R: + /* Get DHR12R2 address */ + tmpreg = (uint32_t)&hdac->Instance->DHR12R2; + break; + case DAC_ALIGN_12B_L: + /* Get DHR12L2 address */ + tmpreg = (uint32_t)&hdac->Instance->DHR12L2; + break; + case DAC_ALIGN_8B_R: + /* Get DHR8R2 address */ + tmpreg = (uint32_t)&hdac->Instance->DHR8R2; + break; + default: + break; + } + } + + /* Enable the DMA channel */ + if(Channel == DAC_CHANNEL_1) + { + /* Enable the DAC DMA underrun interrupt */ + __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1); + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); + } + else + { + /* Enable the DAC DMA underrun interrupt */ + __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2); + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length); + } + + /* Enable the Peripharal */ + __HAL_DAC_ENABLE(hdac, Channel); + + /* Process Unlocked */ + __HAL_UNLOCK(hdac); + + /* Return function status */ + return HAL_OK; +} + + + +#endif /* STM32F071xB STM32F072xB STM32F078xx */ + /* STM32F091xC STM32F098xx */ + +#if defined (STM32F051x8) || defined (STM32F058xx) + +HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) +{ + uint32_t tmp1 = 0, tmp2 = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + + /* Process locked */ + __HAL_LOCK(hdac); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_BUSY; + + /* Enable the Peripharal */ + __HAL_DAC_ENABLE(hdac, Channel); + + if(Channel == DAC_CHANNEL_1) + { + tmp1 = hdac->Instance->CR & DAC_CR_TEN1; + tmp2 = hdac->Instance->CR & DAC_CR_TSEL1; + /* Check if software trigger enabled */ + if((tmp1 == DAC_CR_TEN1) && (tmp2 == DAC_CR_TSEL1)) + { + /* Enable the selected DAC software conversion */ + hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1; + } + } + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hdac); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Enables DAC and starts conversion of channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @param pData: The destination peripheral Buffer address. + * @param Length: The length of data to be transferred from memory to DAC peripheral + * @param Alignment: Specifies the data alignment for DAC channel. + * This parameter can be one of the following values: + * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected + * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected + * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + assert_param(IS_DAC_ALIGN(Alignment)); + + /* Process locked */ + __HAL_LOCK(hdac); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_BUSY; + + /* Set the DMA transfer complete callback for channel1 */ + hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1; + + /* Set the DMA half transfer complete callback for channel1 */ + hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1; + + /* Set the DMA error callback for channel1 */ + hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1; + + /* Enable the selected DAC channel1 DMA request */ + hdac->Instance->CR |= DAC_CR_DMAEN1; + + /* Case of use of channel 1 */ + switch(Alignment) + { + case DAC_ALIGN_12B_R: + /* Get DHR12R1 address */ + tmpreg = (uint32_t)&hdac->Instance->DHR12R1; + break; + case DAC_ALIGN_12B_L: + /* Get DHR12L1 address */ + tmpreg = (uint32_t)&hdac->Instance->DHR12L1; + break; + case DAC_ALIGN_8B_R: + /* Get DHR8R1 address */ + tmpreg = (uint32_t)&hdac->Instance->DHR8R1; + break; + default: + break; + } + + /* Enable the DMA channel */ + /* Enable the DAC DMA underrun interrupt */ + __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1); + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); + + /* Enable the DAC DMA underrun interrupt */ + __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1); + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); + + /* Enable the Peripharal */ + __HAL_DAC_ENABLE(hdac, Channel); + + /* Process Unlocked */ + __HAL_UNLOCK(hdac); + + /* Return function status */ + return HAL_OK; +} + +#endif /* STM32F051x8 STM32F058xx */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) +/* DAC channel 2 is available on top of DAC channel 1 */ + +/** + * @brief Handles DAC interrupt request + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) +{ + /* Check Overrun flag */ + if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1)) + { + /* Change DAC state to error state */ + hdac->State = HAL_DAC_STATE_ERROR; + + /* Set DAC error code to chanel1 DMA underrun error */ + hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1; + + /* Clear the underrun flag */ + __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1); + + /* Disable the selected DAC channel1 DMA request */ + hdac->Instance->CR &= ~DAC_CR_DMAEN1; + + /* Error callback */ + HAL_DAC_DMAUnderrunCallbackCh1(hdac); + } + else + { + /* Change DAC state to error state */ + hdac->State = HAL_DAC_STATE_ERROR; + + /* Set DAC error code to channel2 DMA underrun error */ + hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH2; + + /* Clear the underrun flag */ + __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2); + + /* Disable the selected DAC channel1 DMA request */ + hdac->Instance->CR &= ~DAC_CR_DMAEN2; + + /* Error callback */ + HAL_DACEx_DMAUnderrunCallbackCh2(hdac); + } +} + +#endif /* STM32F071xB STM32F072xB STM32F078xx */ + /* STM32F091xC STM32F098xx */ + +#if defined (STM32F051x8) || defined (STM32F058xx) +/* DAC channel 2 is NOT available. Only DAC channel 1 is available */ + +/** + * @brief Handles DAC interrupt request + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) +{ + /* Check Overrun flag */ + if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1)) + { + /* Change DAC state to error state */ + hdac->State = HAL_DAC_STATE_ERROR; + + /* Set DAC error code to chanel1 DMA underrun error */ + hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1; + + /* Clear the underrun flag */ + __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1); + + /* Disable the selected DAC channel1 DMA request */ + hdac->Instance->CR &= ~DAC_CR_DMAEN1; + + /* Error callback */ + HAL_DAC_DMAUnderrunCallbackCh1(hdac); + } +} + +#endif /* STM32F051x8 STM32F058xx */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +/** + * @brief Returns the last data output value of the selected DAC channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval The selected DAC channel data output value. + */ +uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac) +{ + uint32_t tmp = 0; + + tmp |= hdac->Instance->DOR1; + + /* DAC channel 2 is present in DAC 1 */ + tmp |= hdac->Instance->DOR2 << 16; + + /* Returns the DAC channel data output register value */ + return tmp; +} + +#endif /* STM32F071xB STM32F072xB STM32F078xx */ + /* STM32F091xC STM32F098xx */ + +#if defined (STM32F051x8) || defined (STM32F058xx) + +/** + * @brief Returns the last data output value of the selected DAC channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval The selected DAC channel data output value. + */ +uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac) +{ + uint32_t tmp = 0; + + tmp |= hdac->Instance->DOR1; + + /* Returns the DAC channel data output register value */ + return tmp; +} + +#endif /* STM32F051x8 STM32F058xx */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +/** + * @brief Enables or disables the selected DAC channel wave generation. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * DAC_CHANNEL_1 / DAC_CHANNEL_2 + * @param Amplitude: Select max triangle amplitude. + * This parameter can be one of the following values: + * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1 + * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3 + * @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7 + * @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15 + * @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31 + * @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63 + * @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127 + * @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255 + * @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511 + * @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023 + * @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047 + * @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)); + + /* Process locked */ + __HAL_LOCK(hdac); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_BUSY; + + /* Enable the selected wave generation for the selected DAC channel */ + hdac->Instance->CR |= (DAC_WAVE_TRIANGLE | Amplitude) << Channel; + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hdac); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Enables or disables the selected DAC channel wave generation. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * DAC_CHANNEL_1 / DAC_CHANNEL_2 + * @param Amplitude: Unmask DAC channel LFSR for noise wave generation. + * This parameter can be one of the following values: + * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation + * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)); + + /* Process locked */ + __HAL_LOCK(hdac); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_BUSY; + + /* Enable the selected wave generation for the selected DAC channel */ + hdac->Instance->CR |= (DAC_WAVE_NOISE | Amplitude) << Channel; + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hdac); + + /* Return function status */ + return HAL_OK; +} + +#endif /* STM32F071xB STM32F072xB STM32F078xx */ + /* STM32F091xC STM32F098xx */ + +#if defined(STM32F051x8) || defined(STM32F058xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +/** + * @brief Set the specified data holding register value for dual DAC channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Alignment: Specifies the data alignment for dual channel DAC. + * This parameter can be one of the following values: + * DAC_ALIGN_8B_R: 8bit right data alignment selected + * DAC_ALIGN_12B_L: 12bit left data alignment selected + * DAC_ALIGN_12B_R: 12bit right data alignment selected + * @param Data1: Data for DAC Channel2 to be loaded in the selected data holding register. + * @param Data2: Data for DAC Channel1 to be loaded in the selected data holding register. + * @note In dual mode, a unique register access is required to write in both + * DAC channels at the same time. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2) +{ + uint32_t data = 0, tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(Alignment)); + assert_param(IS_DAC_DATA(Data1)); + assert_param(IS_DAC_DATA(Data2)); + + /* Calculate and set dual DAC data holding register value */ + if (Alignment == DAC_ALIGN_8B_R) + { + data = ((uint32_t)Data2 << 8) | Data1; + } + else + { + data = ((uint32_t)Data2 << 16) | Data1; + } + + tmp = (uint32_t)hdac->Instance; + tmp += __HAL_DHR12RD_ALIGNEMENT(Alignment); + + /* Set the dual DAC selected data holding register */ + *(__IO uint32_t *)tmp = data; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DACEx_Private_Functions + * @{ + */ + +/** + * @brief DMA conversion complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + HAL_DAC_ConvCpltCallbackCh1(hdac); + + hdac->State= HAL_DAC_STATE_READY; +} + +/** + * @brief DMA half transfer complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + /* Conversion complete callback */ + HAL_DAC_ConvHalfCpltCallbackCh1(hdac); +} + +/** + * @brief DMA error callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Set DAC error code to DMA error */ + hdac->ErrorCode |= HAL_DAC_ERROR_DMA; + + HAL_DAC_ErrorCallbackCh1(hdac); + + hdac->State= HAL_DAC_STATE_READY; +} +/** + * @} + */ +#endif /* STM32F051x8 STM32F058xx */ + /* STM32F071xB STM32F072xB STM32F078xx */ + /* STM32F091xC STM32F098xx */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +/** @addtogroup DACEx_Exported_Functions + * @{ + */ + +/** @addtogroup DACEx_Exported_Functions_Group1 + * @brief Extended features functions + * @{ + */ +/** + * @brief Conversion complete callback in non blocking mode for Channel2 + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DAC_ConvCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Conversion half DMA transfer callback in non blocking mode for Channel2 + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DAC_ConvHalfCpltCallbackCh2 could be implemented in the user file + */ +} + +/** + * @brief Error DAC callback for Channel2. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DAC_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief DMA underrun DAC callback for channel2. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DAC_DMAUnderrunCallbackCh2 could be implemented in the user file + */ +} + +/** + * @brief DMA conversion complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + HAL_DACEx_ConvCpltCallbackCh2(hdac); + + hdac->State= HAL_DAC_STATE_READY; +} + +/** + * @brief DMA half transfer complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + /* Conversion complete callback */ + HAL_DACEx_ConvHalfCpltCallbackCh2(hdac); +} + +/** + * @brief DMA error callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Set DAC error code to DMA error */ + hdac->ErrorCode |= HAL_DAC_ERROR_DMA; + + HAL_DACEx_ErrorCallbackCh2(hdac); + + hdac->State= HAL_DAC_STATE_READY; +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* STM32F071xB STM32F072xB STM32F078xx */ + /* STM32F091xC STM32F098xx */ + +#endif /* HAL_DAC_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c @@ -0,0 +1,703 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_dma.c + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief DMA HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the Direct Memory Access (DMA) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and errors functions + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable and configure the peripheral to be connected to the DMA Channel + (except for internal SRAM / FLASH memories: no initialization is + necessary) please refer to Reference manual for connection between peripherals + and DMA requests . + + (#) For a given Channel, program the required configuration through the following parameters: + Transfer Direction, Source and Destination data formats, + Circular or Normal mode, Channel Priority level, Source and Destination Increment mode, + using HAL_DMA_Init() function. + + (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error + detection. + + (#) Use HAL_DMA_Abort() function to abort the current transfer + + -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. + *** Polling mode IO operation *** + ================================= + [..] + (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source + address and destination address and the Length of data to be transferred + (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this + case a fixed Timeout can be configured by User depending from his application. + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() + (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() + (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of + Source address and destination address and the Length of data to be transferred. + In this case the DMA interrupt is configured + (+) Use HAL_DMAy_Channelx_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine + (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can + add his own function by customization of function pointer XferCpltCallback and + XferErrorCallback (i.e a member of DMA handle structure). + + *** DMA HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in DMA HAL driver. + + (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel. + (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel. + (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags. + (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags. + (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts. + (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts. + (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not. + + [..] + (@) You can refer to the DMA HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup DMA DMA + * @brief DMA HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup DMA_Private_Constants DMA Private Constants + * @{ + */ +#define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */ +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup DMA_Private_Functions DMA Private Functions + * @{ + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to initialize the DMA Channel source + and destination addresses, incrementation and data sizes, transfer direction, + circular/normal mode selection, memory-to-memory mode selection and Channel priority value. + [..] + The HAL_DMA_Init() function follows the DMA configuration procedures as described in + reference manual. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the DMA according to the specified + * parameters in the DMA_InitTypeDef and create the associated handle. + * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) +{ + uint32_t tmp = 0; + + /* Check the DMA handle allocation */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); + assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); + assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); + assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); + assert_param(IS_DMA_MODE(hdma->Init.Mode)); + assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Get the CR register value */ + tmp = hdma->Instance->CCR; + + /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */ + tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ + DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ + DMA_CCR_DIR)); + + /* Prepare the DMA Channel configuration */ + tmp |= hdma->Init.Direction | + hdma->Init.PeriphInc | hdma->Init.MemInc | + hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + hdma->Init.Mode | hdma->Init.Priority; + + /* Write to DMA Channel CR register */ + hdma->Instance->CCR = tmp; + + /* Initialise the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the DMA state*/ + hdma->State = HAL_DMA_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the DMA peripheral + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) +{ + /* Check the DMA handle allocation */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + /* Check the DMA peripheral state */ + if(hdma->State == HAL_DMA_STATE_BUSY) + { + return HAL_ERROR; + } + + /* Disable the selected DMA Channelx */ + __HAL_DMA_DISABLE(hdma); + + /* Reset DMA Channel control register */ + hdma->Instance->CCR = 0; + + /* Reset DMA Channel Number of Data to Transfer register */ + hdma->Instance->CNDTR = 0; + + /* Reset DMA Channel peripheral address register */ + hdma->Instance->CPAR = 0; + + /* Reset DMA Channel memory address register */ + hdma->Instance->CMAR = 0; + + /* Clear all flags */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + + /* Initialise the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the DMA state */ + hdma->State = HAL_DMA_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions + * @brief I/O operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the source, destination address and data length and Start DMA transfer + (+) Configure the source, destination address and data length and + Start DMA transfer with interrupt + (+) Abort DMA transfer + (+) Poll for transfer complete + (+) Handle DMA interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Starts the DMA Transfer. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param SrcAddress: The source memory Buffer address + * @param DstAddress: The destination memory Buffer address + * @param DataLength: The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + /* Process locked */ + __HAL_LOCK(hdma); + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + + /* Configure the source, destination address and the data length */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + + return HAL_OK; +} + +/** + * @brief Start the DMA Transfer with interrupt enabled. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param SrcAddress: The source memory Buffer address + * @param DstAddress: The destination memory Buffer address + * @param DataLength: The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + /* Process locked */ + __HAL_LOCK(hdma); + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + + /* Configure the source, destination address and the data length */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the transfer complete interrupt */ + __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC); + + /* Enable the Half transfer complete interrupt */ + __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT); + + /* Enable the transfer Error interrupt */ + __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE); + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + + return HAL_OK; +} + +/** + * @brief Aborts the DMA Transfer. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * + * @note After disabling a DMA Channel, a check for wait until the DMA Channel is + * effectively disabled is added. If a Channel is disabled + * while a data transfer is ongoing, the current data will be transferred + * and the Channel will be effectively disabled only after the transfer of + * this single data is finished. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) +{ + uint32_t tickstart = 0x00; + + /* Disable the channel */ + __HAL_DMA_DISABLE(hdma); + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Check if the DMA Channel is effectively disabled */ + while((hdma->Instance->CCR & DMA_CCR_EN) != 0) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update error code */ + SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_TIMEOUT; + } + } + /* Change the DMA state*/ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} + +/** + * @brief Polling for transfer complete. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param CompleteLevel: Specifies the DMA level complete. + * @param Timeout: Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout) +{ + uint32_t temp; + uint32_t tickstart = 0x00; + + /* Get the level transfer complete flag */ + if(CompleteLevel == HAL_DMA_FULL_TRANSFER) + { + /* Transfer Complete flag */ + temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma); + } + else + { + /* Half Transfer Complete flag */ + temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma); + } + + /* Get timeout */ + tickstart = HAL_GetTick(); + + while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET) + { + if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)) + { + /* Clear the transfer error flags */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + + /* Update error code */ + SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE); + + /* Change the DMA state */ + hdma->State= HAL_DMA_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + { + /* Update error code */ + SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_TIMEOUT; + } + } + } + + if(CompleteLevel == HAL_DMA_FULL_TRANSFER) + { + /* Clear the transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); + + /* The selected Channelx EN bit is cleared (DMA is disabled and + all transfers are complete) */ + hdma->State = HAL_DMA_STATE_READY; + + } + else + { + /* Clear the half transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + + /* The selected Channelx EN bit is cleared (DMA is disabled and + all transfers of half buffer are complete) */ + hdma->State = HAL_DMA_STATE_READY_HALF; + } + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} + +/** + * @brief Handles DMA interrupt request. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval None + */ +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) +{ + /* Transfer Error Interrupt management ***************************************/ + if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET) + { + /* Disable the transfer error interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE); + + /* Clear the transfer error flag */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + + /* Update error code */ + SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if (hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } + } + + /* Half Transfer Complete Interrupt management ******************************/ + if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET) + { + /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) + { + /* Disable the half transfer interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); + } + /* Clear the half transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_READY_HALF; + + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + } + + /* Transfer Complete Interrupt management ***********************************/ + if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET) + { + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) + { + /* Disable the transfer complete interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC); + } + /* Clear the transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); + + /* Update error code */ + SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_NONE); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if(hdma->XferCpltCallback != NULL) + { + /* Transfer complete callback */ + hdma->XferCpltCallback(hdma); + } + } + } +} + +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the DMA state + (+) Get error code + +@endverbatim + * @{ + */ + +/** + * @brief Returns the DMA state. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL state + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) +{ + return hdma->State; +} + +/** + * @brief Return the DMA error code + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval DMA Error Code + */ +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) +{ + return hdma->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DMA_Private_Functions DMA Private Functions + * @{ + */ + +/** + * @brief Sets the DMA Transfer parameter. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param SrcAddress: The source memory Buffer address + * @param DstAddress: The destination memory Buffer address + * @param DataLength: The length of data to be transferred from source to destination + * @retval HAL status + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + /* Configure DMA Channel data length */ + hdma->Instance->CNDTR = DataLength; + + /* Peripheral to Memory */ + if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Configure DMA Channel destination address */ + hdma->Instance->CPAR = DstAddress; + + /* Configure DMA Channel source address */ + hdma->Instance->CMAR = SrcAddress; + } + /* Memory to Peripheral */ + else + { + /* Configure DMA Channel source address */ + hdma->Instance->CPAR = SrcAddress; + + /* Configure DMA Channel destination address */ + hdma->Instance->CMAR = DstAddress; + } +} + +/** + * @} + */ + +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c @@ -0,0 +1,686 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_flash.c + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the internal FLASH memory: + * + Program operations functions + * + Memory Control functions + * + Peripheral State functions + * + @verbatim + ============================================================================== + ##### FLASH peripheral features ##### + ============================================================================== + + [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses + to the Flash memory. It implements the erase and program Flash memory operations + and the read and write protection mechanisms. + + [..] The Flash memory interface accelerates code execution with a system of instruction + prefetch. + + [..] The FLASH main features are: + (+) Flash memory read operations + (+) Flash memory program/erase operations + (+) Read / write protections + (+) Prefetch on I-Code + (+) Option Bytes programming + + ##### How to use this driver ##### + ============================================================================== + [..] + This driver provides functions and macros to configure and program the FLASH + memory of all STM32F0xx devices. These functions are split in 3 groups: + + (#) FLASH Memory I/O Programming functions: this group includes all needed + functions to erase and program the main memory: + (++) Lock and Unlock the FLASH interface + (++) Erase function: Erase page, erase all pages + (++) Program functions: half word and word + + (#) Option Bytes Programming functions: this group includes all needed + functions to manage the Option Bytes: + (++) Lock and Unlock the Option Bytes + (++) Erase Option Bytes + (++) Set/Reset the write protection + (++) Set the Read protection Level + (++) Program the user Option Bytes + (++) Program the data Option Bytes + (++) Launch the Option Bytes loader + + (#) Interrupts and flags management functions : this group + includes all needed functions to: + (++) Handle FLASH interrupts + (++) Wait for last FLASH operation according to its status + (++) Get error flag status + + [..] In addition to these function, this driver includes a set of macros allowing + to handle the following operations: + + (+) Set the latency + (+) Enable/Disable the prefetch buffer + (+) Enable/Disable the FLASH interrupts + (+) Monitor the FLASH flags status + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup FLASH FLASH HAL module driver + * @brief FLASH HAL module driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/** @defgroup FLASH_Private_Variables FLASH Private Variables + * @{ + */ +/* Variables used for Erase pages under interruption*/ +FLASH_ProcessTypeDef pFlash; +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/** @defgroup FLASH_Private_Functions FLASH Private Functions + * @{ + */ +/* Erase operations */ +void FLASH_PageErase(uint32_t PageAddress); + +/* Program operations */ +static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data); + +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); +static void FLASH_SetErrorCode(void); + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup FLASH_Exported_Functions FLASH Exported Functions + * @{ + */ + +/** @defgroup FLASH_Exported_Functions_Group1 I/O operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the FLASH + program operations (write/erase). + +@endverbatim + * @{ + */ + +/** + * @brief Program halfword, word or double word at a specified address + * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface + * + * @note If an erase and a program operations are requested simultaneously, + * the erase operation is performed before the program one. + * + * @param TypeProgram: Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param Address: Specifies the address to be programmed. + * @param Data: Specifies the data to be programmed + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) +{ + HAL_StatusTypeDef status = HAL_ERROR; + uint8_t index = 0; + uint8_t nbiterations = 0; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_TYPEPROGRAM(TypeProgram)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + if(TypeProgram == TYPEPROGRAM_HALFWORD) + { + /* Program halfword (16-bit) at a specified address. */ + nbiterations = 1; + } + else if(TypeProgram == TYPEPROGRAM_WORD) + { + /* Program word (32-bit = 2*16-bit) at a specified address. */ + nbiterations = 2; + } + else + { + /* Program double word (64-bit = 4*16-bit) at a specified address. */ + nbiterations = 4; + } + + for (index = 0; index < nbiterations; index++) + { + FLASH_Program_HalfWord((Address + (2*index)), (uint16_t)(Data >> (16*index))); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + + /* Check FLASH End of Operation flag */ + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + } + + /* If the program operation is completed, disable the PG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PG); + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Program halfword, word or double word at a specified address with interrupt enabled. + * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface + * + * @note If an erase and a program operations are requested simultaneously, + * the erase operation is performed before the program one. + * + * @param TypeProgram: Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param Address: Specifies the address to be programmed. + * @param Data: Specifies the data to be programmed + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_TYPEPROGRAM(TypeProgram)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + + /* Enable End of FLASH Operation and Error source interrupts */ + __HAL_FLASH_ENABLE_IT((FLASH_IT_EOP | FLASH_IT_ERR)); + + pFlash.Address = Address; + pFlash.Data = Data; + + if(TypeProgram == TYPEPROGRAM_HALFWORD) + { + pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD; + /*Program halfword (16-bit) at a specified address.*/ + pFlash.DataRemaining = 1; + } + else if(TypeProgram == TYPEPROGRAM_WORD) + { + pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD; + /*Program word (32-bit : 2*16-bit) at a specified address.*/ + pFlash.DataRemaining = 2; + } + else + { + pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD; + /*Program double word (64-bit : 4*16-bit) at a specified address.*/ + pFlash.DataRemaining = 4; + } + + /*Program halfword (16-bit) at a specified address.*/ + FLASH_Program_HalfWord(Address, (uint16_t)Data); + + return status; +} + +/** + * @brief This function handles FLASH interrupt request. + * @retval None + */ +void HAL_FLASH_IRQHandler(void) +{ + uint32_t addresstmp; + /* If the operation is completed, disable the PG, PER and MER Bits */ + CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER)); + + /* Check FLASH End of Operation flag */ + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + + if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) + { + /* Nb of pages to erased can be decreased */ + pFlash.DataRemaining--; + + /* Indicate user which page address has been erased*/ + HAL_FLASH_EndOfOperationCallback(pFlash.Address); + + /* Check if there are still pages to erase*/ + if(pFlash.DataRemaining != 0) + { + /* Increment page address to next page */ + pFlash.Address += FLASH_PAGE_SIZE; + addresstmp = pFlash.Address; + FLASH_PageErase(addresstmp); + } + else + { + /*No more pages to Erase*/ + + /*Reset Address and stop Erase pages procedure*/ + pFlash.Address = 0xFFFFFFFF; + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + } + else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) + { + /*MassErase ended. Return the selected bank*/ + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(0); + + /* Stop Mass Erase procedure*/ + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + else + { + /* Nb of 16-bit data to program can be decreased */ + pFlash.DataRemaining--; + + /* Check if there are still 16-bit data to program */ + if(pFlash.DataRemaining != 0) + { + /* Increment address to 16-bit */ + pFlash.Address += 2; + addresstmp = pFlash.Address; + + /* Shift to have next 16-bit data */ + pFlash.Data = (pFlash.Data >> 16); + + /*Program halfword (16-bit) at a specified address.*/ + FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data); + } + else + { + /*Program ended. Return the selected address*/ + /* FLASH EOP interrupt user callback */ + if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD) + { + HAL_FLASH_EndOfOperationCallback(pFlash.Address); + } + else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD) + { + HAL_FLASH_EndOfOperationCallback(pFlash.Address-2); + } + else + { + HAL_FLASH_EndOfOperationCallback(pFlash.Address-6); + } + + /* Reset Address and stop Program procedure*/ + pFlash.Address = 0xFFFFFFFF; + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + } + } + + /* Check FLASH operation error flags */ + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR)) + { + /*Save the Error code*/ + FLASH_SetErrorCode(); + + /* FLASH error interrupt user callback */ + HAL_FLASH_OperationErrorCallback(pFlash.Address); + + /* Clear FLASH error pending bits */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR); + + /* Reset address and stop the procedure ongoing*/ + pFlash.Address = 0xFFFFFFFF; + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + + if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE) + { + /* Disable End of FLASH Operation and Error source interrupts */ + __HAL_FLASH_DISABLE_IT((FLASH_IT_EOP | FLASH_IT_ERR)); + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } +} + + +/** + * @brief FLASH end of operation interrupt callback + * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure + * - Mass Erase: No return value expected + * - Pages Erase: Address of the page which has been erased + * - Program: Address which was selected for data program + * @retval none + */ +__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FLASH_EndOfOperationCallback could be implemented in the user file + */ +} + +/** + * @brief FLASH operation error interrupt callback + * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure + * - Mass Erase: No return value expected + * - Pages Erase: Address of the page which returned an error + * - Program: Address which was selected for data program + * @retval none + */ +__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FLASH_OperationErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions + * @brief management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the FLASH + memory operations. + +@endverbatim + * @{ + */ + +/** + * @brief Unlock the FLASH control register access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Unlock(void) +{ + if((READ_BIT(FLASH->CR, FLASH_CR_LOCK)) != RESET) + { + /* Authorize the FLASH Registers access */ + WRITE_REG(FLASH->KEYR, FLASH_FKEY1); + WRITE_REG(FLASH->KEYR, FLASH_FKEY2); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Locks the FLASH control register access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Lock(void) +{ + /* Set the LOCK Bit to lock the FLASH Registers access */ + SET_BIT(FLASH->CR, FLASH_CR_LOCK); + + return HAL_OK; +} + + +/** + * @brief Unlock the FLASH Option Control Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) +{ + if((READ_BIT(FLASH->CR, FLASH_CR_OPTWRE)) == RESET) + { + /* Authorizes the Option Byte register programming */ + WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1); + WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Lock the FLASH Option Control Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) +{ + /* Clear the OPTWRE Bit to lock the FLASH Option Byte Registers access */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTWRE); + + return HAL_OK; +} + +/** + * @brief Launch the option byte loading. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) +{ + /* Set the bit to force the option byte reloading */ + SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH); + + /* Wait for last operation to be completed */ + return(FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE)); +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral Errors functions ##### + =============================================================================== + [..] + This subsection permit to get in run-time Errors of the FLASH peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Get the specific FLASH error flag. + * @retval FLASH_ErrorCode: The returned value can be: + * @arg FLASH_ERROR_PG: FLASH Programming error flag + * @arg FLASH_ERROR_WRP: FLASH Write protected error flag + */ +FLASH_ErrorTypeDef HAL_FLASH_GetError(void) +{ + return pFlash.ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup FLASH_Private_Functions + * @{ + */ +/** + * @brief Erase the specified FLASH memory page + * @param PageAddress: FLASH page to erase + * The value of this parameter depend on device used within the same series + * + * @retval None + */ +void FLASH_PageErase(uint32_t PageAddress) +{ + /* Clear pending flags (if any) */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR); + + /* Proceed to erase the page */ + SET_BIT(FLASH->CR, FLASH_CR_PER); + WRITE_REG(FLASH->AR, PageAddress); + SET_BIT(FLASH->CR, FLASH_CR_STRT); +} + +/** + * @brief Program a half-word (16-bit) at a specified address. + * @param Address: specifies the address to be programmed. + * @param Data: specifies the data to be programmed. + * @retval None + */ +static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) +{ + /* Clear pending flags (if any) */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR); + + /* Proceed to program the new data */ + SET_BIT(FLASH->CR, FLASH_CR_PG); + + *(__IO uint16_t*)Address = Data; +} + +/** + * @brief Wait for a FLASH operation to complete. + * @param Timeout: maximum flash operationtimeout + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) +{ + /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. + Even if the FLASH operation fails, the BUSY flag will be reset and an error + flag will be set */ + + uint32_t tickstart = HAL_GetTick(); + + while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + { + return HAL_TIMEOUT; + } + } + } + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) + { + /*Save the error code*/ + FLASH_SetErrorCode(); + return HAL_ERROR; + } + + /* If there is an error flag set */ + return HAL_OK; + +} + +/** + * @brief Set the specific FLASH error flag. + * @retval None + */ +static void FLASH_SetErrorCode(void) +{ + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) + { + pFlash.ErrorCode = FLASH_ERROR_WRP; + } + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) + { + pFlash.ErrorCode |= FLASH_ERROR_PG; + } +} + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c @@ -0,0 +1,863 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_flash_ex.c + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Extended FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the FLASH peripheral: + * + Extended Initialization/de-initialization functions + * + Extended I/O operation functions + * + Extended Peripheral Control functions + * + Extended Peripheral State functions + * + @verbatim + ============================================================================== + ##### Flash peripheral extended features ##### + ============================================================================== + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure and program the FLASH memory + of all STM32F0xxx devices. It includes + + (+) Set/Reset the write protection + (+) Program the user Option Bytes + (+) Get the Read protection Level + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup FLASHEx FLASHEx Extended HAL module driver + * @brief FLASH Extended HAL module driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @addtogroup FLASHEx_Private_Constants FLASHEx Private Constants + * @{ + */ +#define HAL_FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup FLASHEx_Private_Variables FLASHEx Private Variables + * @{ + */ + +/* Variables used for Erase pages under interruption*/ +extern FLASH_ProcessTypeDef pFlash; + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup FLASHEx_Private_Functions FLASHEx Private Functions + * @{ + */ + +/* Erase operations */ +extern void FLASH_PageErase(uint32_t PageAddress); +static void FLASH_MassErase(void); + +/* Option bytes control */ +static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage); +static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage); +static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel); +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig); +static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data); +static uint32_t FLASH_OB_GetWRP(void); +static FlagStatus FLASH_OB_GetRDP(void); +static uint8_t FLASH_OB_GetUser(void); + +/** + * @} + */ + +/** @defgroup FLASHEx_Extern_Functions FLASHEx Extern Functions + * @{ + */ +/* Private functions ---------------------------------------------------------*/ +extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); + +/** + * @} + */ + +/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions + * @{ + */ + +/** @defgroup FLASHEx_Exported_Functions_Group2 Extended I/O operation functions + * @brief Extended I/O operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ +/** + * @brief Perform a mass erase or erase the specified FLASH memory pages + * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface + * @param[in] pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @param[out] PageError: pointer to variable that + * contains the configuration information on faulty page in case of error + * (0xFFFFFFFF means that all the pages have been correctly erased) + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) +{ + HAL_StatusTypeDef status = HAL_ERROR; + uint32_t address = 0; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_TYPEERASE(pEraseInit->TypeErase)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + if (pEraseInit->TypeErase == TYPEERASE_MASSERASE) + { + /*Mass erase to be done*/ + FLASH_MassErase(); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + + /* Check FLASH End of Operation flag */ + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + } + + /* If the erase operation is completed, disable the MER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_MER); + } + else + { + /* Check the parameters */ + assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); + assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages)); + + /*Initialization of PageError variable*/ + *PageError = 0xFFFFFFFF; + + /* Erase by page by page to be done*/ + for(address = pEraseInit->PageAddress; + address < (pEraseInit->PageAddress + (pEraseInit->NbPages)*FLASH_PAGE_SIZE); + address += FLASH_PAGE_SIZE) + { + FLASH_PageErase(address); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + + /* Check FLASH End of Operation flag */ + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + } + + /* If the erase operation is completed, disable the PER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PER); + + if (status != HAL_OK) + { + /* In case of error, stop erase procedure and return the faulty address */ + *PageError = address; + break; + } + } + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled + * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface + * @param pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_TYPEERASE(pEraseInit->TypeErase)); + + /* Enable End of FLASH Operation and Error source interrupts */ + __HAL_FLASH_ENABLE_IT((FLASH_IT_EOP | FLASH_IT_ERR)); + + if (pEraseInit->TypeErase == TYPEERASE_MASSERASE) + { + /*Mass erase to be done*/ + pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE; + FLASH_MassErase(); + } + else + { + /* Erase by page to be done*/ + + /* Check the parameters */ + assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); + assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages)); + + pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE; + pFlash.DataRemaining = pEraseInit->NbPages; + pFlash.Address = pEraseInit->PageAddress; + + /*Erase 1st page and wait for IT*/ + FLASH_PageErase(pEraseInit->PageAddress); + } + + return status; +} + +/** + * @} + */ + +/** @defgroup FLASHEx_Exported_Functions_Group3 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the FLASH + memory operations. + +@endverbatim + * @{ + */ +/** + * @brief Erases the FLASH option bytes. + * @note This functions erases all option bytes except the Read protection (RDP). + * The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + * The function HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes + * The function HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes + * (system reset will occur) + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_FLASHEx_OBErase(void) +{ + uint8_t rdptmp = OB_RDP_LEVEL_0; + HAL_StatusTypeDef status = HAL_ERROR; + FLASH_OBProgramInitTypeDef optionsbytes; + + /* Get the actual read protection Option Byte value */ + HAL_FLASHEx_OBGetConfig(&optionsbytes); + if(optionsbytes.RDPLevel != RESET) + { + rdptmp = OB_RDP_LEVEL_1; + } + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + + /* Clear pending flags (if any) */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR); + + if(status == HAL_OK) + { + /* If the previous operation is completed, proceed to erase the option bytes */ + SET_BIT(FLASH->CR, FLASH_CR_OPTER); + SET_BIT(FLASH->CR, FLASH_CR_STRT); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the OPTER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER); + + if(status == HAL_OK) + { + /* Restore the last read protection Option Byte value */ + optionsbytes.OptionType = OPTIONBYTE_RDP; + optionsbytes.RDPLevel = rdptmp; + status = HAL_FLASHEx_OBProgram(&optionsbytes); + } + } + + /* Return the erase status */ + return status; +} + +/** + * @brief Program option bytes + * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + * The function HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes + * The function HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes + * (system reset will occur) + * + * @param pOBInit: pointer to an FLASH_OBInitStruct structure that + * contains the configuration information for the programming. + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Check the parameters */ + assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); + + /* Write protection configuration */ + if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) + { + assert_param(IS_WRPSTATE(pOBInit->WRPState)); + if (pOBInit->WRPState == WRPSTATE_ENABLE) + { + /* Enable of Write protection on the selected page */ + status = FLASH_OB_EnableWRP(pOBInit->WRPPage); + } + else + { + /* Disable of Write protection on the selected page */ + status = FLASH_OB_DisableWRP(pOBInit->WRPPage); + } + } + + /* Read protection configuration */ + if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP) + { + status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel); + } + + /* USER configuration */ + if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER) + { + status = FLASH_OB_UserConfig(pOBInit->USERConfig); + } + + /* DATA configuration*/ + if((pOBInit->OptionType & OPTIONBYTE_DATA) == OPTIONBYTE_DATA) + { + status = FLASH_OB_ProgramData(pOBInit->DATAAddress, pOBInit->DATAData); + } + + return status; +} + +/** + * @brief Get the Option byte configuration + * @param pOBInit: pointer to an FLASH_OBInitStruct structure that + * contains the configuration information for the programming. + * + * @retval None + */ +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) +{ + pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER; + + /*Get WRP*/ + pOBInit->WRPPage = FLASH_OB_GetWRP(); + + /*Get RDP Level*/ + pOBInit->RDPLevel = FLASH_OB_GetRDP(); + + /*Get USER*/ + pOBInit->USERConfig = FLASH_OB_GetUser(); +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions + * @{ + */ + +/** + * @brief Mass erase of FLASH memory + * @retval None + */ +static void FLASH_MassErase(void) +{ + /* Clear pending flags (if any) */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR); + + /* Proceed to erase all sectors */ + SET_BIT(FLASH->CR, FLASH_CR_MER); + SET_BIT(FLASH->CR, FLASH_CR_STRT); +} + +/** + * @brief Enable the write protection of the desired pages + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase the flash page i if CortexM4 + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * + * @param WriteProtectPage: specifies the page(s) to be write protected. + * The value of this parameter depend on device used within the same series + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) +{ + HAL_StatusTypeDef status = HAL_OK; +#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || \ + defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx) + uint16_t WRP0_Data = 0xFFFF; +#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx) + uint16_t WRP1_Data = 0xFFFF; +#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */ +#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F058xx */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF; +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */ + + /* Check the parameters */ + assert_param(IS_OB_WRP(WriteProtectPage)); + + WriteProtectPage = (uint32_t)(~WriteProtectPage); +#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || \ + defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx) + WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK); +#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx) + WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8); +#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */ +#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F058xx */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK); + WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8); + WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16); +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO63MASK) >> 24); +#endif /* STM32F071xB || STM32F072xB || STM32F078xx */ +#if defined(STM32F091xC) || defined(STM32F098xx) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24); +#endif /* STM32F091xC || STM32F098xx */ +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */ + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + + /* Clear pending flags (if any) */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR); + + if(status == HAL_OK) + { + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + + if(WRP0_Data != 0xFF) + { + OB->WRP0 &= WRP0_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + } + +#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + if((status == HAL_OK) && (WRP1_Data != 0xFF)) + { + OB->WRP1 &= WRP1_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + } +#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx || STM32F071xB || + STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + if((status == HAL_OK) && (WRP2_Data != 0xFF)) + { + OB->WRP2 &= WRP2_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + } + + if((status == HAL_OK) && (WRP3_Data != 0xFF)) + { + OB->WRP3 &= WRP3_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + } +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */ + + /* if the program operation is completed, disable the OPTPG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + } + + return status; + +} + +/** + * @brief Disable the write protection of the desired pages + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase the flash page i if CortexM4 + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * + * @param WriteProtectPage: specifies the page(s) to be write unprotected. + * The value of this parameter depend on device used within the same series + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) +{ + HAL_StatusTypeDef status = HAL_OK; +#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || \ + defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx) + uint16_t WRP0_Data = 0xFFFF; +#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx) + uint16_t WRP1_Data = 0xFFFF; +#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */ +#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F058xx */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF; +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */ + + /* Check the parameters */ + assert_param(IS_OB_WRP(WriteProtectPage)); + +#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || \ + defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx) + WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK); +#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx) + WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8); +#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */ +#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F058xx */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK); + WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8); + WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16); +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO63MASK) >> 24); +#endif /* STM32F071xB || STM32F072xB || STM32F078xx */ +#if defined(STM32F091xC) || defined(STM32F098xx) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24); +#endif /* STM32F091xC || STM32F098xx */ +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */ + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + + /* Clear pending flags (if any) */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR); + + if(status == HAL_OK) + { + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + + if(WRP0_Data != 0xFF) + { + OB->WRP0 |= WRP0_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + } + +#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + if((status == HAL_OK) && (WRP1_Data != 0xFF)) + { + OB->WRP1 |= WRP1_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + } +#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx || STM32F071xB || + STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + if((status == HAL_OK) && (WRP2_Data != 0xFF)) + { + OB->WRP2 |= WRP2_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + } + + if((status == HAL_OK) && (WRP3_Data != 0xFF)) + { + OB->WRP3 |= WRP3_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + } +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */ + + /* if the program operation is completed, disable the OPTPG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + } + + return status; +} + +/** + * @brief Set the read protection level. + * @param ReadProtectLevel: specifies the read protection level. + * This parameter can be one of the following values: + * @arg OB_RDP_LEVEL_0: No protection + * @arg OB_RDP_LEVEL_1: Read protection of the memory + * @arg OB_RDP_LEVEL_2: Full chip protection + * + * @note Warning: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 + * + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_RDP_LEVEL(ReadProtectLevel)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + + /* Clear pending flags (if any) */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR); + + if(status == HAL_OK) + { + /* Enable the Option Bytes Programming operation */ + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + + WRITE_REG(OB->RDP, ReadProtectLevel); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + + /* if the program operation is completed, disable the OPTPG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + } + + return status; +} + +/** + * @brief Program the FLASH User Option Byte. + * @note Programming of the OB should be performed only after an erase (otherwise PGERR occurs) + * @param UserConfig: The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), BOOT1(Bit4), + * VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6). + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_WDG_SOURCE((UserConfig&OB_WDG_SW))); + assert_param(IS_OB_STOP_SOURCE((UserConfig&OB_STOP_NO_RST))); + assert_param(IS_OB_STDBY_SOURCE((UserConfig&OB_STDBY_NO_RST))); + assert_param(IS_OB_BOOT1((UserConfig&OB_BOOT1_SET))); + assert_param(IS_OB_VDDA_ANALOG((UserConfig&OB_VDDA_ANALOG_ON))); + assert_param(IS_OB_SRAM_PARITY((UserConfig&OB_RAM_PARITY_CHECK_RESET))); +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F091xC) || defined(STM32F098xx) + assert_param(IS_OB_BOOT_SEL((UserConfig&OB_BOOT_SEL_SET))); + assert_param(IS_OB_BOOT0((UserConfig&OB_BOOT0_SET))); +#endif /* STM32F042x6 || STM32F048xx || STM32F091xC || STM32F098xx */ + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + + /* Clear pending flags (if any) */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR); + + if(status == HAL_OK) + { + /* Enable the Option Bytes Programming operation */ + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F091xC) || defined(STM32F098xx) + OB->USER = UserConfig; +#else + OB->USER = (UserConfig | 0x88); +#endif /* STM32F042x6 || STM32F048xx || STM32F091xC || STM32F098xx */ + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + + /* if the program operation is completed, disable the OPTPG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + } + + return status; +} + +/** + * @brief Programs a half word at a specified Option Byte Data address. + * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + * The function HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes + * The function HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes + * (system reset will occur) + * Programming of the OB should be performed only after an erase (otherwise PGERR occurs) + * @param Address: specifies the address to be programmed. + * This parameter can be 0x1FFFF804 or 0x1FFFF806. + * @param Data: specifies the data to be programmed. + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Check the parameters */ + assert_param(IS_OB_DATA_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + + /* Clear pending flags (if any) */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR); + + if(status == HAL_OK) + { + /* Enables the Option Bytes Programming operation */ + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + *(__IO uint16_t*)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + + /* If the program operation is completed, disable the OPTPG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + } + /* Return the Option Byte Data Program Status */ + return status; +} + +/** + * @brief Return the FLASH Write Protection Option Bytes value. + * @retval The FLASH Write Protection Option Bytes value + */ +static uint32_t FLASH_OB_GetWRP(void) +{ + /* Return the FLASH write protection Register value */ + return (uint32_t)(READ_REG(FLASH->WRPR)); +} + +/** + * @brief Returns the FLASH Read Protection level. + * @retval FLASH ReadOut Protection Status: + * - SET, when OB_RDP_Level_1 or OB_RDP_Level_2 is set + * - RESET, when OB_RDP_Level_0 is set + */ +static FlagStatus FLASH_OB_GetRDP(void) +{ + FlagStatus readstatus = RESET; + + if ((uint8_t)READ_BIT(FLASH->OBR, FLASH_OBR_RDPRT1) != RESET) + { + readstatus = SET; + } + + return readstatus; +} + +/** + * @brief Return the FLASH User Option Byte value. + * @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), BOOT1(Bit4), + * VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6). + */ +static uint8_t FLASH_OB_GetUser(void) +{ + /* Return the User Option Byte */ + return (uint8_t)(READ_REG(FLASH->OBR) >> 8); +} + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c @@ -0,0 +1,574 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_gpio.c + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief GPIO HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (GPIO) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + @verbatim + ============================================================================== + ##### GPIO Peripheral features ##### + ============================================================================== + [..] + Each port bit of the general-purpose I/O (GPIO) ports can be individually + configured by software in several modes: + (+) Input mode + (+) Analog mode + (+) Output mode + (+) Alternate function mode + (+) External interrupt/event lines + + [..] + During and just after reset, the alternate functions and external interrupt + lines are not active and the I/O ports are configured in input floating mode. + + [..] + All GPIO pins have weak internal pull-up and pull-down resistors, which can be + activated or not. + + [..] + In Output or Alternate mode, each IO can be configured on open-drain or push-pull + type and the IO speed can be selected depending on the VDD value. + + [..] + The microcontroller IO pins are connected to onboard peripherals/modules through a + multiplexer that allows only one peripheral s alternate function (AF) connected + to an IO pin at a time. In this way, there can be no conflict between peripherals + sharing the same IO pin. + + [..] + All ports have external interrupt/event capability. To use external interrupt + lines, the port must be configured in input mode. All available GPIO pins are + connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. + + [..] + The external interrupt/event controller consists of up to 23 edge detectors + (16 lines are connected to GPIO) for generating event/interrupt requests (each + input line can be independently configured to select the type (interrupt or event) + and the corresponding trigger event (rising or falling or both). Each line can + also be masked independently. + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the GPIO AHB clock using the following function : __GPIOx_CLK_ENABLE(). + + (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). + (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure + (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef + structure. + (++) In case of Output or alternate function mode selection: the speed is + configured through "Speed" member from GPIO_InitTypeDef structure, + the speed is configurable: 2 MHz, 10 MHz and 50 MHz. + (++) If alternate mode is selected, the alternate function connected to the IO + is configured through "Alternate" member from GPIO_InitTypeDef structure + (++) Analog mode is required when a pin is to be used as ADC channel + or DAC output. + (++) In case of external interrupt/event selection the "Mode" member from + GPIO_InitTypeDef structure select the type (interrupt or event) and + the corresponding trigger event (rising or falling or both). + + (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority + mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using + HAL_NVIC_EnableIRQ(). + + (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). + + (#) To set/reset the level of a pin configured in output mode use + HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). + + (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). + + (#) During and just after reset, the alternate functions are not + active and the GPIO pins are configured in input floating mode (except JTAG + pins). + + (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose + (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has + priority over the GPIO function. + + (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as + general purpose PD0 and PD1, respectively, when the HSE oscillator is off. + The HSE has priority over the GPIO function. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIO GPIO HAL module driver + * @brief GPIO HAL module driver + * @{ + */ + +#ifdef HAL_GPIO_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup GPIO_Private_Define GPIO Private Define + * @{ + */ +#define GPIO_MODE ((uint32_t)0x00000003) +#define EXTI_MODE ((uint32_t)0x10000000) +#define GPIO_MODE_IT ((uint32_t)0x00010000) +#define GPIO_MODE_EVT ((uint32_t)0x00020000) +#define RISING_EDGE ((uint32_t)0x00100000) +#define FALLING_EDGE ((uint32_t)0x00200000) +#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010) + +#define GPIO_NUMBER ((uint32_t)16) + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exporte functions ---------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init. + * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family + * @note GPIOD is only available on STM32F05xx, STM32F07xx and STM32F09xx + * @note GPIOE is only available on STM32F07xx and STM32F09xx + * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + uint32_t position; + uint32_t ioposition = 0x00; + uint32_t iocurrent = 0x00; + uint32_t temp = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Configure the port pins */ + for (position = 0; position < GPIO_NUMBER; position++) + { + /* Get the IO position */ + ioposition = ((uint32_t)0x01) << position; + /* Get the current IO position */ + iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; + + if (iocurrent == ioposition) + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Alternate function mode selection */ + if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + { + /* Check the Alternate function parameter */ + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3]; + temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; + temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4)); + GPIOx->AFR[position >> 3] = temp; + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + temp &= ~(GPIO_MODER_MODER0 << (position * 2)); + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2)); + GPIOx->MODER = temp; + + /* In case of Output or Alternate function mode selection */ + if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || + (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); + temp |= (GPIO_Init->Speed << (position * 2)); + GPIOx->OSPEEDR = temp; + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + temp &= ~(GPIO_OTYPER_OT_0 << position) ; + temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position); + GPIOx->OTYPER = temp; + } + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2)); + temp |= ((GPIO_Init->Pull) << (position * 2)); + GPIOx->PUPDR = temp; + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) + { + /* Enable SYSCFG Clock */ + __SYSCFG_CLK_ENABLE(); + + temp = SYSCFG->EXTICR[position >> 2]; + temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03))); + temp |= (GET_GPIO_INDEX(GPIOx) << (4 * (position & 0x03))); + SYSCFG->EXTICR[position >> 2] = temp; + + /* Clear EXTI line configuration */ + temp = EXTI->IMR; + temp &= ~((uint32_t)iocurrent); + if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) + { + temp |= iocurrent; + } + EXTI->IMR = temp; + + temp = EXTI->EMR; + temp &= ~((uint32_t)iocurrent); + if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) + { + temp |= iocurrent; + } + EXTI->EMR = temp; + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR; + temp &= ~((uint32_t)iocurrent); + if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) + { + temp |= iocurrent; + } + EXTI->RTSR = temp; + + temp = EXTI->FTSR; + temp &= ~((uint32_t)iocurrent); + if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) + { + temp |= iocurrent; + } + EXTI->FTSR = temp; + } + else + { + temp = SYSCFG->EXTICR[position >> 2]; + temp &= (((uint32_t)0x0F) << (4 * (position & 0x03))); + if(temp == (GET_GPIO_INDEX(GPIOx) << (4 * (position & 0x03)))) + { + /* Configure the External Interrupt or event for the current IO */ + temp = ((uint32_t)0x0F) << (4 * (position & 0x03)); + SYSCFG->EXTICR[position >> 2] &= ~temp; + + /* Clear EXTI line configuration */ + EXTI->IMR &= ~((uint32_t)iocurrent); + EXTI->EMR &= ~((uint32_t)iocurrent); + + /* Clear Rising Falling edge configuration */ + EXTI->RTSR &= ~((uint32_t)iocurrent); + EXTI->FTSR &= ~((uint32_t)iocurrent); + } + } + } + } +} + +/** + * @brief De-initializes the GPIOx peripheral registers to their default reset values. + * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family + * @note GPIOD is only available on STM32F05xx, STM32F07xx and STM32F09xx + * @note GPIOE is only available on STM32F07xx and STM32F09xx + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + uint32_t position; + uint32_t ioposition = 0x00; + uint32_t iocurrent = 0x00; + uint32_t tmp = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + + /* Configure the port pins */ + for (position = 0; position < GPIO_NUMBER; position++) + { + /* Get the IO position */ + ioposition = ((uint32_t)0x01) << position; + /* Get the current IO position */ + iocurrent = (GPIO_Pin) & ioposition; + + if (iocurrent == ioposition) + { + /*------------------------- GPIO Mode Configuration --------------------*/ + /* Configure IO Direction in Input Floting Mode */ + GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2)); + + /* Configure the default Alternate Function in current IO */ + GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; + + /* Configure the default value for IO Speed */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); + + /* Configure the default value IO Output Type */ + GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ; + + /* Deactivate the Pull-up oand Pull-down resistor for the current IO */ + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2)); + + /*------------------------- EXTI Mode Configuration --------------------*/ + /* Clear the External Interrupt or Event for the current IO */ + + tmp = SYSCFG->EXTICR[position >> 2]; + tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03))); + if(tmp == (GET_GPIO_INDEX(GPIOx) << (4 * (position & 0x03)))) + { + tmp = ((uint32_t)0x0F) << (4 * (position & 0x03)); + SYSCFG->EXTICR[position >> 2] &= ~tmp; + + /* Clear EXTI line configuration */ + EXTI->IMR &= ~((uint32_t)iocurrent); + EXTI->EMR &= ~((uint32_t)iocurrent); + + /* Clear Rising Falling edge configuration */ + EXTI->RTSR &= ~((uint32_t)iocurrent); + EXTI->FTSR &= ~((uint32_t)iocurrent); + } + } + } +} + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions + * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Reads the specified input port pin. + * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family + * @note GPIOD is only available on STM32F05xx, STM32F07xx and STM32F09xx + * @note GPIOE is only available on STM32F07xx and STM32F09xx + * @param GPIO_Pin: specifies the port bit to read. + * This parameter can be GPIO_PIN_x where x can be (0..15). + * @retval The input port pin value. + */ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + GPIO_PinState bitstatus; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) + { + bitstatus = GPIO_PIN_SET; + } + else + { + bitstatus = GPIO_PIN_RESET; + } + return bitstatus; + } + +/** + * @brief Sets or clears the selected data port bit. + * @note This function uses GPIOx_BSRR register to allow atomic read/modify + * accesses. In this way, there is no risk of an IRQ occurring between + * the read and the modify access. + * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family + * @note GPIOD is only available on STM32F05xx, STM32F07xx and STM32F09xx + * @note GPIOE is only available on STM32F07xx and STM32F09xx + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * @param PinState: specifies the value to be written to the selected bit. + * This parameter can be one of the GPIO_PinState enum values: + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if (PinState != GPIO_PIN_RESET) + { + GPIOx->BSRR = (uint32_t)GPIO_Pin; + } + else + { + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ; + } +} + +/** + * @brief Toggles the specified GPIO pin + * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family + * @note GPIOD is only available on STM32F05xx, STM32F07xx and STM32F09xx + * @note GPIOE is only available on STM32F07xx and STM32F09xx + * @param GPIO_Pin: specifies the pins to be toggled. + * @retval None + */ +void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->ODR ^= GPIO_Pin; +} + +/** +* @brief Locks GPIO Pins configuration registers. +* @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, +* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. +* @note The configuration of the locked GPIO pins can no longer be modified +* until the next reset. +* @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family +* @note GPIOD is only available on STM32F05xx, STM32F07xx and STM32F09xx +* @note GPIOE is only available on STM32F07xx and STM32F09xx +* @param GPIO_Pin: specifies the port bit to be locked. +* This parameter can be any combination of GPIO_Pin_x where x can be (0..15). +* @retval None +*/ +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + __IO uint32_t tmp = GPIO_LCKR_LCKK; + + /* Check the parameters */ + assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Apply lock key write sequence */ + tmp |= GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Read LCKK bit*/ + tmp = GPIOx->LCKR; + + if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET) + { + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief This function handles EXTI interrupt request. + * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) +{ + /* EXTI line interrupt detected */ + if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) + { + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); + HAL_GPIO_EXTI_Callback(GPIO_Pin); + } +} + +/** + * @brief EXTI line detection callbacks. + * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_GPIO_EXTI_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + + +/** + * @} + */ + +#endif /* HAL_GPIO_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c @@ -0,0 +1,4101 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_i2c.c + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief I2C HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Inter Integrated Circuit (I2C) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The I2C HAL driver can be used as follows: + + (#) Declare a I2C_HandleTypeDef handle structure, for example: + I2C_HandleTypeDef hi2c; + + (#)Initialize the I2C low level resources by implement the HAL_I2C_MspInit ()API: + (++) Enable the I2Cx interface clock + (++) I2C pins configuration + (+++) Enable the clock for the I2C GPIOs + (+++) Configure I2C pins as alternate function open-drain + (++) NVIC configuration if you need to use interrupt process + (+++) Configure the I2Cx interrupt priority + (+++) Enable the NVIC I2C IRQ Channel + (++) DMA Configuration if you need to use DMA process + (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel + (+++) Enable the DMAx interface clock using + (+++) Configure the DMA handle parameters + (+++) Configure the DMA Tx or Rx channel + (+++) Associate the initilalized DMA handle to the hi2c DMA Tx or Rx handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx channel + + (#) Configure the Communication Clock Timing, Own Address1, Master Adressing Mode, Dual Addressing mode, + Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure. + + (#) Initialize the I2C registers by calling the HAL_I2C_Init() API: + (++) These API s configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + by calling the customed HAL_I2C_MspInit(&hi2c) API. + + (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() + + (#) For I2C IO and IO MEM operations, three modes of operations are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit() + (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() + (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() + (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() + + *** Polling mode IO MEM operation *** + ===================================== + [..] + (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write() + (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read() + + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Transmit in master mode an amount of data in non blocking mode using HAL_I2C_Master_Transmit_IT() + (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback + (+) Receive in master mode an amount of data in non blocking mode using HAL_I2C_Master_Receive_IT() + (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback + (+) Transmit in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Transmit_IT() + (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback + (+) Receive in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Receive_IT() + (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback + + *** Interrupt mode IO MEM operation *** + ======================================= + [..] + (+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using + HAL_I2C_Mem_Write_IT() + (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback + (+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using + HAL_I2C_Mem_Read_IT() + (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback + + *** DMA mode IO operation *** + ============================== + [..] + (+) Transmit in master mode an amount of data in non blocking mode (DMA) using + HAL_I2C_Master_Transmit_DMA() + (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback + (+) Receive in master mode an amount of data in non blocking mode (DMA) using + HAL_I2C_Master_Receive_DMA() + (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback + (+) Transmit in slave mode an amount of data in non blocking mode (DMA) using + HAL_I2C_Slave_Transmit_DMA() + (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback + (+) Receive in slave mode an amount of data in non blocking mode (DMA) using + HAL_I2C_Slave_Receive_DMA() + (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback + + *** DMA mode IO MEM operation *** + ================================= + [..] + (+) Write an amount of data in no-blocking mode with DMA to a specific memory address using + HAL_I2C_Mem_Write_DMA() + (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback + (+) Read an amount of data in no-blocking mode with DMA from a specific memory address using + HAL_I2C_Mem_Read_DMA() + (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback + + + *** I2C HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in I2C HAL driver. + + (+) __HAL_I2C_ENABLE: Enable the I2C peripheral + (+) __HAL_I2C_DISABLE: Disable the I2C peripheral + (+) __HAL_I2C_GET_FLAG : Checks whether the specified I2C flag is set or not + (+) __HAL_I2C_CLEAR_FLAG : Clears the specified I2C pending flag + (+) __HAL_I2C_ENABLE_IT: Enables the specified I2C interrupt + (+) __HAL_I2C_DISABLE_IT: Disables the specified I2C interrupt + + [..] + (@) You can refer to the I2C HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup I2C I2C HAL module driver + * @brief I2C HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup I2C_Private_Define I2C Private Define + * @{ + */ +#define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /*Instance)); + assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); + assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); + assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); + assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); + assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); + assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); + assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); + + if(hi2c->State == HAL_I2C_STATE_RESET) + { + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_I2C_MspInit(hi2c); + } + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ + /* Configure I2Cx: Frequency range */ + hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; + + /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ + /* Configure I2Cx: Own Address1 and ack own address1 mode */ + hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; + if(hi2c->Init.OwnAddress1 != 0) + { + if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + { + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); + } + else /* I2C_ADDRESSINGMODE_10BIT */ + { + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); + } + } + + /*---------------------------- I2Cx CR2 Configuration ----------------------*/ + /* Configure I2Cx: Addressing Master mode */ + if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + hi2c->Instance->CR2 = (I2C_CR2_ADD10); + } + /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ + hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); + + /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ + /* Configure I2Cx: Dual mode and Own Address2 */ + hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8)); + + /*---------------------------- I2Cx CR1 Configuration ----------------------*/ + /* Configure I2Cx: Generalcall and NoStretch mode */ + hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); + + /* Enable the selected I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the I2C peripheral. + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) +{ + /* Check the I2C handle allocation */ + if(hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the I2C Peripheral Clock */ + __HAL_I2C_DISABLE(hi2c); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_I2C_MspDeInit(hi2c); + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief I2C MSP Init. + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ + __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2C_MspInit could be implemented in the user file + */ +} + +/** + * @brief I2C MSP DeInit + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ + __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2C_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the I2C data + transfers. + + (#) There is two mode of transfer: + (++) Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode : The communication is performed using Interrupts + or DMA. These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + + (#) Blocking mode functions are : + (++) HAL_I2C_Master_Transmit() + (++) HAL_I2C_Master_Receive() + (++) HAL_I2C_Slave_Transmit() + (++) HAL_I2C_Slave_Receive() + (++) HAL_I2C_Mem_Write() + (++) HAL_I2C_Mem_Read() + (++) HAL_I2C_IsDeviceReady() + + (#) No-Blocking mode functions with Interrupt are : + (++) HAL_I2C_Master_Transmit_IT() + (++) HAL_I2C_Master_Receive_IT() + (++) HAL_I2C_Slave_Transmit_IT() + (++) HAL_I2C_Slave_Receive_IT() + (++) HAL_I2C_Mem_Write_IT() + (++) HAL_I2C_Mem_Read_IT() + + (#) No-Blocking mode functions with DMA are : + (++) HAL_I2C_Master_Transmit_DMA() + (++) HAL_I2C_Master_Receive_DMA() + (++) HAL_I2C_Slave_Transmit_DMA() + (++) HAL_I2C_Slave_Receive_DMA() + (++) HAL_I2C_Mem_Write_DMA() + (++) HAL_I2C_Mem_Read_DMA() + + (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode: + (++) HAL_I2C_MemTxCpltCallback() + (++) HAL_I2C_MemRxCpltCallback() + (++) HAL_I2C_MasterTxCpltCallback() + (++) HAL_I2C_MasterRxCpltCallback() + (++) HAL_I2C_SlaveTxCpltCallback() + (++) HAL_I2C_SlaveRxCpltCallback() + (++) HAL_I2C_ErrorCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Transmits in master mode an amount of data in blocking mode. + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress: Target device address + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t sizetmp = 0; + + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_MASTER_BUSY_TX; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Send Slave Address */ + /* Set NBYTES to write and reload if size > 255 and generate RESTART */ + /* Size > 255, need to set RELOAD bit */ + if(Size > 255) + { + I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + sizetmp = 255; + } + else + { + I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); + sizetmp = Size; + } + + do + { + /* Wait until TXIS flag is set */ + if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + /* Write data to TXDR */ + hi2c->Instance->TXDR = (*pData++); + sizetmp--; + Size--; + + if((sizetmp == 0)&&(Size!=0)) + { + /* Wait until TXE flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if(Size > 255) + { + I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + sizetmp = 255; + } + else + { + I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + sizetmp = Size; + } + } + + }while(Size > 0); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set */ + if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + __HAL_I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives in master mode an amount of data in blocking mode. + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress: Target device address + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t sizetmp = 0; + + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_MASTER_BUSY_RX; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Send Slave Address */ + /* Set NBYTES to write and reload if size > 255 and generate RESTART */ + /* Size > 255, need to set RELOAD bit */ + if(Size > 255) + { + I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); + sizetmp = 255; + } + else + { + I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + sizetmp = Size; + } + + do + { + /* Wait until RXNE flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Write data to RXDR */ + (*pData++) =hi2c->Instance->RXDR; + sizetmp--; + Size--; + + if((sizetmp == 0)&&(Size!=0)) + { + /* Wait until TCR flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if(Size > 255) + { + I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + sizetmp = 255; + } + else + { + I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + sizetmp = Size; + } + } + + }while(Size > 0); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set */ + if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + __HAL_I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmits in slave mode an amount of data in blocking mode. + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_RX; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Wait until ADDR flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_TIMEOUT; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + + /* If 10bit addressing mode is selected */ + if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + /* Wait until ADDR flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_TIMEOUT; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + } + + /* Wait until DIR flag is set Transmitter mode */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_TIMEOUT; + } + + do + { + /* Wait until TXIS flag is set */ + if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Read data from TXDR */ + hi2c->Instance->TXDR = (*pData++); + Size--; + }while(Size > 0); + + /* Wait until STOP flag is set */ + if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Normal use case for Transmitter mode */ + /* A NACK is generated to confirm the end of transfer */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Clear STOP flag */ + __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF); + + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_TIMEOUT; + } + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in blocking mode + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_RX; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Wait until ADDR flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_TIMEOUT; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + + /* Wait until DIR flag is reset Receiver mode */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_TIMEOUT; + } + + while(Size > 0) + { + /* Wait until RXNE flag is set */ + if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) + { + return HAL_TIMEOUT; + } + else + { + return HAL_ERROR; + } + } + + /* Read data from RXDR */ + (*pData++) = hi2c->Instance->RXDR; + Size--; + } + + /* Wait until STOP flag is set */ + if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Clear STOP flag */ + __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF); + + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_TIMEOUT; + } + + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in no-blocking mode with Interrupt + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress: Target device address + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_MASTER_BUSY_TX; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + if(Size > 255) + { + hi2c->XferSize = 255; + } + else + { + hi2c->XferSize = Size; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if size > 255 and generate RESTART */ + if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) + { + I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + } + else + { + I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_TXI ); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in no-blocking mode with Interrupt + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress: Target device address + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_MASTER_BUSY_RX; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + if(Size > 255) + { + hi2c->XferSize = 255; + } + else + { + hi2c->XferSize = Size; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if size > 255 and generate RESTART */ + if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) + { + I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); + } + else + { + I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI ); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in no-blocking mode with Interrupt + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_TX; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + hi2c->pBuffPtr = pData; + hi2c->XferSize = Size; + hi2c->XferCount = Size; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_TXI ); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in no-blocking mode with Interrupt + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_RX; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + hi2c->pBuffPtr = pData; + hi2c->XferSize = Size; + hi2c->XferCount = Size; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in no-blocking mode with DMA + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress: Target device address + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_MASTER_BUSY_TX; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + if(Size > 255) + { + hi2c->XferSize = 255; + } + else + { + hi2c->XferSize = Size; + } + + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + + /* Send Slave Address */ + /* Set NBYTES to write and reload if size > 255 and generate RESTART */ + if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) + { + I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + } + else + { + I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); + } + + /* Wait until TXIS flag is set */ + if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in no-blocking mode with DMA + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress: Target device address + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_MASTER_BUSY_RX; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + if(Size > 255) + { + hi2c->XferSize = 255; + } + else + { + hi2c->XferSize = Size; + } + + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + + /* Send Slave Address */ + /* Set NBYTES to write and reload if size > 255 and generate RESTART */ + if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) + { + I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); + } + else + { + I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + } + + /* Wait until RXNE flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE) != HAL_OK) + { + return HAL_TIMEOUT; + } + + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in no-blocking mode with DMA + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_TX; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = Size; + + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Wait until ADDR flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_TIMEOUT; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + + /* If 10bits addressing mode is selected */ + if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + /* Wait until ADDR flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_TIMEOUT; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + } + + /* Wait until DIR flag is set Transmitter mode */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, I2C_TIMEOUT_BUSY) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_TIMEOUT; + } + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in no-blocking mode with DMA + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_RX; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + hi2c->pBuffPtr = pData; + hi2c->XferSize = Size; + hi2c->XferCount = Size; + + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, Size); + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Wait until ADDR flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_TIMEOUT; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + + /* Wait until DIR flag is set Receiver mode */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, I2C_TIMEOUT_DIR) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_TIMEOUT; + } + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Write an amount of data in blocking mode to a specific memory address + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress: Target device address + * @param MemAddress: Internal memory address + * @param MemAddSize: Size of internal memory address + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t Sizetmp = 0; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Send Slave Address and Memory Address */ + if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + + /* Set NBYTES to write and reload if size > 255 */ + /* Size > 255, need to set RELOAD bit */ + if(Size > 255) + { + I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + Sizetmp = 255; + } + else + { + I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + Sizetmp = Size; + } + + do + { + /* Wait until TXIS flag is set */ + if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Write data to DR */ + hi2c->Instance->TXDR = (*pData++); + Sizetmp--; + Size--; + + if((Sizetmp == 0)&&(Size!=0)) + { + /* Wait until TCR flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + + if(Size > 255) + { + I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + Sizetmp = 255; + } + else + { + I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + Sizetmp = Size; + } + } + + }while(Size > 0); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + __HAL_I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in blocking mode from a specific memory address + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress: Target device address + * @param MemAddress: Internal memory address + * @param MemAddSize: Size of internal memory address + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t Sizetmp = 0; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Send Slave Address and Memory Address */ + if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if size > 255 and generate RESTART */ + /* Size > 255, need to set RELOAD bit */ + if(Size > 255) + { + I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); + Sizetmp = 255; + } + else + { + I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + Sizetmp = Size; + } + + do + { + /* Wait until RXNE flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Read data from RXDR */ + (*pData++) = hi2c->Instance->RXDR; + + /* Decrement the Size counter */ + Sizetmp--; + Size--; + + if((Sizetmp == 0)&&(Size!=0)) + { + /* Wait until TCR flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if(Size > 255) + { + I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + Sizetmp = 255; + } + else + { + I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + Sizetmp = Size; + } + } + + }while(Size > 0); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + __HAL_I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Write an amount of data in no-blocking mode with Interrupt to a specific memory address + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress: Target device address + * @param MemAddress: Internal memory address + * @param MemAddSize: Size of internal memory address + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + if(Size > 255) + { + hi2c->XferSize = 255; + } + else + { + hi2c->XferSize = Size; + } + + /* Send Slave Address and Memory Address */ + if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + + /* Set NBYTES to write and reload if size > 255 */ + /* Size > 255, need to set RELOAD bit */ + if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) + { + I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_TXI ); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in no-blocking mode with Interrupt from a specific memory address + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress: Target device address + * @param MemAddress: Internal memory address + * @param MemAddSize: Size of internal memory address + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX; + + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + if(Size > 255) + { + hi2c->XferSize = 255; + } + else + { + hi2c->XferSize = Size; + } + + /* Send Slave Address and Memory Address */ + if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + + /* Set NBYTES to write and reload if size > 255 and generate RESTART */ + /* Size > 255, need to set RELOAD bit */ + if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) + { + I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); + } + else + { + I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_RXI ); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Write an amount of data in no-blocking mode with DMA to a specific memory address + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress: Target device address + * @param MemAddress: Internal memory address + * @param MemAddSize: Size of internal memory address + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + if(Size > 255) + { + hi2c->XferSize = 255; + } + else + { + hi2c->XferSize = Size; + } + + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMemTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + + /* Send Slave Address and Memory Address */ + if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if size > 255 */ + if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) + { + I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + + /* Wait until TXIS flag is set */ + if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Reads an amount of data in no-blocking mode with DMA from a specific memory address. + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress: Target device address + * @param MemAddress: Internal memory address + * @param MemAddSize: Size of internal memory address + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be read + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX; + + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + if(Size > 255) + { + hi2c->XferSize = 255; + } + else + { + hi2c->XferSize = Size; + } + + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMemReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + + /* Send Slave Address and Memory Address */ + if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + + /* Set NBYTES to write and reload if size > 255 and generate RESTART */ + if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) + { + I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); + } + else + { + I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + } + + /* Wait until RXNE flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Checks if target device is ready for communication. + * @note This function is used with Memory devices + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress: Target device address + * @param Trials: Number of trials + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) +{ + uint32_t tickstart = 0; + + __IO uint32_t I2C_Trials = 0; + + if(hi2c->State == HAL_I2C_STATE_READY) + { + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + do + { + /* Generate Start */ + hi2c->Instance->CR2 = __HAL_I2C_GENERATE_START(hi2c->Init.AddressingMode,DevAddress); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set or a NACK flag is set*/ + tickstart = HAL_GetTick(); + while((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT)) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + { + /* Device is ready */ + hi2c->State = HAL_I2C_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + } + + /* Check if the NACKF flag has not been set */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) + { + /* Wait until STOPF flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Device is ready */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + /* Wait until STOPF flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Clear STOP Flag, auto generated with autoend*/ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + + /* Check if the maximum allowed number of trials has been reached */ + if (I2C_Trials++ == Trials) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + + /* Wait until STOPF flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + }while(I2C_Trials < Trials); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief This function handles I2C event interrupt request. + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + /* I2C in mode Transmitter ---------------------------------------------------*/ + if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI | I2C_IT_ADDRI)) == SET)) + { + /* Slave mode selected */ + if (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_TX) + { + I2C_SlaveTransmit_ISR(hi2c); + } + } + + if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI)) == SET)) + { + /* Master mode selected */ + if ((hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MEM_BUSY_TX)) + { + I2C_MasterTransmit_ISR(hi2c); + } + } + + /* I2C in mode Receiver ----------------------------------------------------*/ + if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_RXI | I2C_IT_ADDRI)) == SET)) + { + /* Slave mode selected */ + if (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_RX) + { + I2C_SlaveReceive_ISR(hi2c); + } + } + if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_RXI)) == SET)) + { + /* Master mode selected */ + if ((hi2c->State == HAL_I2C_STATE_MASTER_BUSY_RX) || (hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX)) + { + I2C_MasterReceive_ISR(hi2c); + } + } +} + +/** + * @brief This function handles I2C error interrupt request. + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + /* I2C Bus error interrupt occurred ------------------------------------*/ + if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BERR) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERRI) == SET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); + } + + /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ + if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_OVR) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERRI) == SET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; + + /* Clear OVR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); + } + + /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ + if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ARLO) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERRI) == SET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); + } + + /* Call the Error Callback in case of Error detected */ + if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + hi2c->State = HAL_I2C_STATE_READY; + + HAL_I2C_ErrorCallback(hi2c); + } +} + +/** + * @brief Master Tx Transfer completed callbacks. + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ + __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2C_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Master Rx Transfer completed callbacks. + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2C_TxCpltCallback could be implemented in the user file + */ +} + +/** @brief Slave Tx Transfer completed callbacks. + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ + __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2C_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave Rx Transfer completed callbacks. + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2C_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Memory Tx Transfer completed callbacks. + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ + __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2C_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Memory Rx Transfer completed callbacks. + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2C_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief I2C error callbacks. + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ + __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2C_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection permit to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the I2C state. + * @param hi2c : I2C handle + * @retval HAL state + */ +HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) +{ + return hi2c->State; +} + +/** +* @brief Return the I2C error code +* @param hi2c : pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. +* @retval I2C Error Code +*/ +uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) +{ + return hi2c->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup I2C_Private_Functions + * @{ + */ + +/** + * @brief Handle Interrupt Flags Master Transmit Mode + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_MasterTransmit_ISR(I2C_HandleTypeDef *hi2c) +{ + uint16_t DevAddress; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); + hi2c->XferSize--; + hi2c->XferCount--; + } + else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) + { + if((hi2c->XferSize == 0)&&(hi2c->XferCount!=0)) + { + DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); + + if(hi2c->XferCount > 255) + { + I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + hi2c->XferSize = 255; + } + else + { + I2C_TransferConfig(hi2c,DevAddress,hi2c->XferCount, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + hi2c->XferSize = hi2c->XferCount; + } + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Wrong size Status regarding TCR flag event */ + hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE; + HAL_I2C_ErrorCallback(hi2c); + } + } + else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) + { + if(hi2c->XferCount == 0) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Wrong size Status regarding TCR flag event */ + hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE; + HAL_I2C_ErrorCallback(hi2c); + } + } + else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + { + /* Disable ERR, TC, STOP, NACK, TXI interrupt */ + __HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_TXI ); + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + __HAL_I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_TX) + { + HAL_I2C_MemTxCpltCallback(hi2c); + } + else + { + HAL_I2C_MasterTxCpltCallback(hi2c); + } + } + else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + HAL_I2C_ErrorCallback(hi2c); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Handle Interrupt Flags Master Receive Mode + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_MasterReceive_ISR(I2C_HandleTypeDef *hi2c) +{ + uint16_t DevAddress; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from RXDR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + hi2c->XferSize--; + hi2c->XferCount--; + } + else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) + { + if((hi2c->XferSize == 0)&&(hi2c->XferCount!=0)) + { + DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); + + if(hi2c->XferCount > 255) + { + I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + hi2c->XferSize = 255; + } + else + { + I2C_TransferConfig(hi2c,DevAddress,hi2c->XferCount, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + hi2c->XferSize = hi2c->XferCount; + } + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Wrong size Status regarding TCR flag event */ + hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE; + HAL_I2C_ErrorCallback(hi2c); + } + } + else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) + { + if(hi2c->XferCount == 0) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Wrong size Status regarding TCR flag event */ + hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE; + HAL_I2C_ErrorCallback(hi2c); + } + } + else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + { + /* Disable ERR, TC, STOP, NACK, TXI interrupt */ + __HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_RXI ); + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + __HAL_I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX) + { + HAL_I2C_MemRxCpltCallback(hi2c); + } + else + { + HAL_I2C_MasterRxCpltCallback(hi2c); + } + } + else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + HAL_I2C_ErrorCallback(hi2c); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + +} + +/** + * @brief Handle Interrupt Flags Slave Transmit Mode + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_SlaveTransmit_ISR(I2C_HandleTypeDef *hi2c) +{ + /* Process locked */ + __HAL_LOCK(hi2c); + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) != RESET) + { + /* Check that I2C transfer finished */ + /* if yes, normal usecase, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0*/ + /* So clear Flag NACKF only */ + if(hi2c->XferCount == 0) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + } + else + { + /* if no, error usecase, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Error callback to prevent upper layer */ + HAL_I2C_ErrorCallback(hi2c); + } + } + else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + /* Check first if STOPF is set */ + /* to prevent a Write Data in TX buffer */ + /* which is stuck in TXDR until next */ + /* communication with Master */ + else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + { + /* Disable ERRI, TCI, STOPI, NACKI, ADDRI, RXI, TXI interrupt */ + __HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI ); + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + HAL_I2C_SlaveTxCpltCallback(hi2c); + } + else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET) + { + /* Write data to TXDR only if XferCount not reach "0" */ + /* A TXIS flag can be set, during STOP treatment */ + if(hi2c->XferCount > 0) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Handle Interrupt Flags Slave Receive Mode + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_SlaveReceive_ISR(I2C_HandleTypeDef *hi2c) +{ + /* Process Locked */ + __HAL_LOCK(hi2c); + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) != RESET) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + HAL_I2C_ErrorCallback(hi2c); + } + else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from RXDR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + hi2c->XferSize--; + hi2c->XferCount--; + } + else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + { + /* Disable ERRI, TCI, STOPI, NACKI, ADDRI, RXI, TXI interrupt */ + __HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_RXI ); + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + HAL_I2C_SlaveRxCpltCallback(hi2c); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for write request. + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress: Target device address + * @param MemAddress: Internal memory address + * @param MemAddSize: Size of internal memory address + * @param Timeout: Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout) +{ + I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + + /* Wait until TXIS flag is set */ + if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* If Memory address size is 8Bit */ + if(MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->TXDR = __HAL_I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->TXDR = __HAL_I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXIS flag is set */ + if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Send LSB of Memory Address */ + hi2c->Instance->TXDR = __HAL_I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait until TCR flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + +return HAL_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for read request. + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress: Target device address + * @param MemAddress: Internal memory address + * @param MemAddSize: Size of internal memory address + * @param Timeout: Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout) +{ + I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); + + /* Wait until TXIS flag is set */ + if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* If Memory address size is 8Bit */ + if(MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->TXDR = __HAL_I2C_MEM_ADD_LSB(MemAddress); + } + /* If Mememory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->TXDR = __HAL_I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXIS flag is set */ + if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Send LSB of Memory Address */ + hi2c->Instance->TXDR = __HAL_I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait until TC flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + return HAL_OK; +} + +/** + * @brief DMA I2C master transmit process complete callback. + * @param hdma: DMA handle + * @retval None + */ +static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) +{ + uint16_t DevAddress; + I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + /* Check if last DMA request was done with RELOAD */ + /* Set NBYTES to write and reload if size > 255 */ + if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) + { + /* Wait until TCR flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + } + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Check if Errors has been detected during transfer */ + if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + else + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + } + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + __HAL_I2C_RESET_CR2(hi2c); + + hi2c->XferCount = 0; + + hi2c->State = HAL_I2C_STATE_READY; + HAL_I2C_ErrorCallback(hi2c); + } + else + { + hi2c->pBuffPtr += hi2c->XferSize; + hi2c->XferCount -= hi2c->XferSize; + if(hi2c->XferCount > 255) + { + hi2c->XferSize = 255; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + + /* Send Slave Address */ + /* Set NBYTES to write and reload if size > 255 */ + if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) + { + I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + + /* Wait until TXIS flag is set */ + if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK) + { + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + else + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + } + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + __HAL_I2C_RESET_CR2(hi2c); + + hi2c->XferCount = 0; + + hi2c->State = HAL_I2C_STATE_READY; + HAL_I2C_ErrorCallback(hi2c); + } + else + { + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + } + else + { + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + else + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + } + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + __HAL_I2C_RESET_CR2(hi2c); + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + hi2c->XferCount = 0; + + hi2c->State = HAL_I2C_STATE_READY; + + /* Check if Errors has been detected during transfer */ + if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + HAL_I2C_ErrorCallback(hi2c); + } + else + { + HAL_I2C_MasterTxCpltCallback(hi2c); + } + } +} + +/** + * @brief DMA I2C slave transmit process complete callback. + * @param hdma: DMA handle + * @retval None + */ +static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + /* Wait until STOP flag is set */ + if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Normal Use case, a AF is generated by master */ + /* to inform slave the end of transfer */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + else + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + } + } + + /* Clear STOP flag */ + __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF); + + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY) != HAL_OK) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + } + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + hi2c->XferCount = 0; + + hi2c->State = HAL_I2C_STATE_READY; + + /* Check if Errors has been detected during transfer */ + if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + HAL_I2C_ErrorCallback(hi2c); + } + else + { + HAL_I2C_SlaveTxCpltCallback(hi2c); + } +} + +/** + * @brief DMA I2C master receive process complete callback + * @param hdma: DMA handle + * @retval None + */ +static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + uint16_t DevAddress; + + /* Check if last DMA request was done with RELOAD */ + /* Set NBYTES to write and reload if size > 255 */ + if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) + { + /* Wait until TCR flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + } + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Check if Errors has been detected during transfer */ + if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + else + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + } + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + __HAL_I2C_RESET_CR2(hi2c); + + hi2c->XferCount = 0; + + hi2c->State = HAL_I2C_STATE_READY; + HAL_I2C_ErrorCallback(hi2c); + } + else + { + hi2c->pBuffPtr += hi2c->XferSize; + hi2c->XferCount -= hi2c->XferSize; + if(hi2c->XferCount > 255) + { + hi2c->XferSize = 255; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); + + /* Send Slave Address */ + /* Set NBYTES to write and reload if size > 255 */ + if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) + { + I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + + /* Wait until RXNE flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE) != HAL_OK) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + } + + /* Check if Errors has been detected during transfer */ + if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + else + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + } + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + __HAL_I2C_RESET_CR2(hi2c); + + hi2c->XferCount = 0; + + hi2c->State = HAL_I2C_STATE_READY; + + HAL_I2C_ErrorCallback(hi2c); + } + else + { + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + } + } + else + { + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + else + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + } + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + __HAL_I2C_RESET_CR2(hi2c); + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + hi2c->XferCount = 0; + + hi2c->State = HAL_I2C_STATE_READY; + + /* Check if Errors has been detected during transfer */ + if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + HAL_I2C_ErrorCallback(hi2c); + } + else + { + HAL_I2C_MasterRxCpltCallback(hi2c); + } + } +} + +/** + * @brief DMA I2C slave receive process complete callback. + * @param hdma: DMA handle + * @retval None + */ +static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + /* Wait until STOPF flag is reset */ + if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + else + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + } + } + + /* Clear STOPF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY) != HAL_OK) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + } + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + hi2c->XferCount = 0; + + hi2c->State = HAL_I2C_STATE_READY; + + /* Check if Errors has been detected during transfer */ + if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + HAL_I2C_ErrorCallback(hi2c); + } + else + { + HAL_I2C_SlaveRxCpltCallback(hi2c); + } +} + +/** + * @brief DMA I2C Memory Write process complete callback + * @param hdma : DMA handle + * @retval None + */ +static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma) +{ + uint16_t DevAddress; + I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Check if last DMA request was done with RELOAD */ + /* Set NBYTES to write and reload if size > 255 */ + if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) + { + /* Wait until TCR flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + } + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Check if Errors has been detected during transfer */ + if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + else + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + } + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + __HAL_I2C_RESET_CR2(hi2c); + + hi2c->XferCount = 0; + + hi2c->State = HAL_I2C_STATE_READY; + HAL_I2C_ErrorCallback(hi2c); + } + else + { + hi2c->pBuffPtr += hi2c->XferSize; + hi2c->XferCount -= hi2c->XferSize; + if(hi2c->XferCount > 255) + { + hi2c->XferSize = 255; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + + /* Send Slave Address */ + /* Set NBYTES to write and reload if size > 255 */ + if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) + { + I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + + /* Wait until TXIS flag is set */ + if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK) + { + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + else + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + } + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + __HAL_I2C_RESET_CR2(hi2c); + + hi2c->XferCount = 0; + + hi2c->State = HAL_I2C_STATE_READY; + HAL_I2C_ErrorCallback(hi2c); + } + else + { + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + } + else + { + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + else + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + } + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + __HAL_I2C_RESET_CR2(hi2c); + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + hi2c->XferCount = 0; + + hi2c->State = HAL_I2C_STATE_READY; + + /* Check if Errors has been detected during transfer */ + if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + HAL_I2C_ErrorCallback(hi2c); + } + else + { + HAL_I2C_MemTxCpltCallback(hi2c); + } + } +} + +/** + * @brief DMA I2C Memory Read process complete callback + * @param hdma: DMA handle + * @retval None + */ +static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + uint16_t DevAddress; + + /* Check if last DMA request was done with RELOAD */ + /* Set NBYTES to write and reload if size > 255 */ + if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) + { + /* Wait until TCR flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + } + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Check if Errors has been detected during transfer */ + if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + else + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + } + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + __HAL_I2C_RESET_CR2(hi2c); + + hi2c->XferCount = 0; + + hi2c->State = HAL_I2C_STATE_READY; + HAL_I2C_ErrorCallback(hi2c); + } + else + { + hi2c->pBuffPtr += hi2c->XferSize; + hi2c->XferCount -= hi2c->XferSize; + if(hi2c->XferCount > 255) + { + hi2c->XferSize = 255; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); + + /* Send Slave Address */ + /* Set NBYTES to write and reload if size > 255 */ + if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) + { + I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + + /* Wait until RXNE flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE) != HAL_OK) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + } + + /* Check if Errors has been detected during transfer */ + if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + else + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + } + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + __HAL_I2C_RESET_CR2(hi2c); + + hi2c->XferCount = 0; + + hi2c->State = HAL_I2C_STATE_READY; + HAL_I2C_ErrorCallback(hi2c); + } + else + { + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + } + } + else + { + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + else + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + } + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + __HAL_I2C_RESET_CR2(hi2c); + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + hi2c->XferCount = 0; + + hi2c->State = HAL_I2C_STATE_READY; + + /* Check if Errors has been detected during transfer */ + if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + HAL_I2C_ErrorCallback(hi2c); + } + else + { + HAL_I2C_MemRxCpltCallback(hi2c); + } + } +} + +/** + * @brief DMA I2C communication error callback. + * @param hdma : DMA handle + * @retval None + */ +static void I2C_DMAError(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Disable Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + hi2c->XferCount = 0; + + hi2c->State = HAL_I2C_STATE_READY; + + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + HAL_I2C_ErrorCallback(hi2c); +} + +/** + * @brief This function handles I2C Communication Timeout. + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Flag: specifies the I2C flag to check. + * @param Status: The new Flag status (SET or RESET). + * @param Timeout: Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + + /* Wait until flag is set */ + if(Status == RESET) + { + while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + { + hi2c->State= HAL_I2C_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + } + } + else + { + while(__HAL_I2C_GET_FLAG(hi2c, Flag) != RESET) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + { + hi2c->State= HAL_I2C_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag. + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout: Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) + { + /* Check if a NACK is detected */ + if(I2C_IsAcknowledgeFailed(hi2c, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout: Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout) +{ + uint32_t tickstart = 0x00; + tickstart = HAL_GetTick(); + + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + /* Check if a NACK is detected */ + if(I2C_IsAcknowledgeFailed(hi2c, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout: Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout) +{ + uint32_t tickstart = 0x00; + tickstart = HAL_GetTick(); + + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + { + /* Check if a STOPF is detected */ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + __HAL_I2C_RESET_CR2(hi2c); + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + /* Check for the Timeout */ + if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief This function handles Acknowledge failed detection during an I2C Communication. + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout: Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout) +{ + uint32_t tickstart = 0x00; + tickstart = HAL_GetTick(); + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + /* Generate stop if necessary only in case of I2C peripheral in MASTER mode */ + if((hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MEM_BUSY_TX) + || (hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX)) + { + /* No need to generate the STOP condition if AUTOEND mode is enabled */ + /* Generate the STOP condition only in case of SOFTEND mode is enabled */ + if((hi2c->Instance->CR2 & I2C_AUTOEND_MODE) != I2C_AUTOEND_MODE) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + } + } + + /* Wait until STOP Flag is reset */ + /* AutoEnd should be initiate after AF */ + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + { + hi2c->State= HAL_I2C_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + } + + /* Clear NACKF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + __HAL_I2C_RESET_CR2(hi2c); + + hi2c->ErrorCode = HAL_I2C_ERROR_AF; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + return HAL_OK; +} + +/** + * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). + * @param hi2c: I2C handle. + * @param DevAddress: specifies the slave address to be programmed. + * @param Size: specifies the number of bytes to be programmed. + * This parameter must be a value between 0 and 255. + * @param Mode: new state of the I2C START condition generation. + * This parameter can be one of the following values: + * @arg I2C_RELOAD_MODE: Enable Reload mode . + * @arg I2C_AUTOEND_MODE: Enable Automatic end mode. + * @arg I2C_SOFTEND_MODE: Enable Software end mode. + * @param Request: new state of the I2C START condition generation. + * This parameter can be one of the following values: + * @arg I2C_NO_STARTSTOP: Don't Generate stop and start condition. + * @arg I2C_GENERATE_STOP: Generate stop condition (Size should be set to 0). + * @arg I2C_GENERATE_START_READ: Generate Restart for read request. + * @arg I2C_GENERATE_START_WRITE: Generate Restart for write request. + * @retval None + */ +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_TRANSFER_MODE(Mode)); + assert_param(IS_TRANSFER_REQUEST(Request)); + + /* Get the CR2 register value */ + tmpreg = hi2c->Instance->CR2; + + /* clear tmpreg specific bits */ + tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP)); + + /* update tmpreg */ + tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request); + + /* update CR2 register */ + hi2c->Instance->CR2 = tmpreg; +} + +/** + * @} + */ + +#endif /* HAL_I2C_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c @@ -0,0 +1,291 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_i2c_ex.c + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief I2C Extension HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of I2C extension peripheral: + * + Extension features functions + * + @verbatim + ============================================================================== + ##### I2C peripheral extension features ##### + ============================================================================== + + [..] Comparing to other previous devices, the I2C interface for STM32F0XX + devices contains the following additional features + + (+) Possibility to disable or enable Analog Noise Filter + (+) Use of a configured Digital Noise Filter + (+) Disable or enable wakeup from Stop mode + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure Noise Filter + (#) Configure I2C Analog noise filter using the function HAL_I2CEx_AnalogFilter_Config() + (#) Configure I2C Digital noise filter using the function HAL_I2CEx_DigitalFilter_Config() + (#) Configure the enabling or disabling of I2C Wake Up Mode using the functions : + (++) HAL_I2CEx_EnableWakeUp() + (++) HAL_I2CEx_DisableWakeUp() + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup I2CEx I2CEx Extended HAL module driver + * @brief I2C Extended HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup I2CEx_Exported_Functions I2CEx Exported Functions + * @{ + */ + +/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions + * @brief Extended features functions + * +@verbatim + =============================================================================== + ##### Extension features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Noise Filters + +@endverbatim + * @{ + */ + +/** + * @brief Configures I2C Analog noise filter. + * @param hi2c : pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param AnalogFilter : new state of the Analog filter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_AnalogFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); + + if((hi2c->State == HAL_I2C_STATE_BUSY) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_RX) + || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_RX)) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Reset I2Cx ANOFF bit */ + hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); + + /* Set analog filter bit*/ + hi2c->Instance->CR1 |= AnalogFilter; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Configures I2C Digital noise filter. + * @param hi2c : pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param DigitalFilter : Coefficient of digital noise filter between 0x00 and 0x0F. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_DigitalFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); + + if((hi2c->State == HAL_I2C_STATE_BUSY) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_RX) + || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_RX)) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Get the old register value */ + tmpreg = hi2c->Instance->CR1; + + /* Reset I2Cx DNF bits [11:8] */ + tmpreg &= ~(I2C_CR1_DFN); + + /* Set I2Cx DNF coefficient */ + tmpreg |= DigitalFilter << 8; + + /* Store the new register value */ + hi2c->Instance->CR1 = tmpreg; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Enables I2C wakeup from stop mode. + * @param hi2c : pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + + if((hi2c->State == HAL_I2C_STATE_BUSY) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_RX) + || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_RX)) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Enable wakeup from stop mode */ + hi2c->Instance->CR1 |= I2C_CR1_WUPEN; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + + +/** + * @brief Disables I2C wakeup from stop mode. + * @param hi2c : pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + + if((hi2c->State == HAL_I2C_STATE_BUSY) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_RX) + || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_RX)) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Enable wakeup from stop mode */ + hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN); + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_I2C_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2s.c b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2s.c new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2s.c @@ -0,0 +1,1383 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_i2s.c + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief I2S HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Integrated Interchip Sound (I2S) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and Errors functions + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The I2S HAL driver can be used as follow: + + (#) Declare a I2S_HandleTypeDef handle structure. + (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API: + (##) Enable the SPIx interface clock. + (##) I2S pins configuration: + (+++) Enable the clock for the I2S GPIOs. + (+++) Configure these I2S pins as alternate function pull-up. + (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT() + and HAL_I2S_Receive_IT() APIs). + (+++) Configure the I2Sx interrupt priority. + (+++) Enable the NVIC I2S IRQ handle. + (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA() + and HAL_I2S_Receive_DMA() APIs: + (+++) Declare a DMA handle structure for the Tx/Rx Channel. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx Channel. + (+++) Associate the initilalized DMA handle to the I2S DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the + DMA Tx/Rx Channel. + + (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity + using HAL_I2S_Init() function. + + -@- The specific I2S interrupts (Transmission complete interrupt, + RXNE interrupt and Error Interrupts) will be managed using the macros + __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process. + -@- Make sure that either: + (+@) External clock source is configured after setting correctly + the define constant EXTERNAL_CLOCK_VALUE in the stm32f0xx_hal_conf.h file. + + (#) Three mode of operations are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Send an amount of data in blocking mode using HAL_I2S_Transmit() + (+) Receive an amount of data in blocking mode using HAL_I2S_Receive() + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT() + (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback + (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_TxCpltCallback + (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT() + (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback + (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_RxCpltCallback + (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2S_ErrorCallback + + *** DMA mode IO operation *** + ============================== + [..] + (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA() + (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback + (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_TxCpltCallback + (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA() + (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback + (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_RxCpltCallback + (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2S_ErrorCallback + (+) Pause the DMA Transfer using HAL_I2S_DMAPause() + (+) Resume the DMA Transfer using HAL_I2S_DMAResume() + (+) Stop the DMA Transfer using HAL_I2S_DMAStop() + + *** I2S HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in USART HAL driver. + + (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode) + (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode) + (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts + (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts + (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not + + [..] + (@) You can refer to the I2S HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup I2S I2S HAL module driver + * @brief I2S HAL module driver + * @{ + */ + +#ifdef HAL_I2S_MODULE_ENABLED + +#if defined(STM32F031x6) || defined(STM32F038xx) || \ + defined(STM32F051x8) || defined(STM32F058xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F042x6) || defined(STM32F048xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma); +static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma); +static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma); +static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma); +static void I2S_DMAError(DMA_HandleTypeDef *hdma); +static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s); +static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s); +static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout); + +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup I2S_Exported_Functions I2S Exported Functions + * @{ + */ + +/** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + de-initialiaze the I2Sx peripheral in simplex mode: + + (+) User must Implement HAL_I2S_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + + (+) Call the function HAL_I2S_Init() to configure the selected device with + the selected configuration: + (++) Mode + (++) Standard + (++) Data Format + (++) MCLK Output + (++) Audio frequency + (++) Polarity + + (+) Call the function HAL_I2S_DeInit() to restore the default configuration + of the selected I2Sx periperal. + @endverbatim + * @{ + */ + +/** + * @brief Initializes the I2S according to the specified parameters + * in the I2S_InitTypeDef and create the associated handle. + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) +{ + uint32_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; + uint32_t tmp = 0, i2sclk = 0; + + /* Check the I2S handle allocation */ + if(hi2s == NULL) + { + return HAL_ERROR; + } + + /* Check the I2S parameters */ + assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance)); + assert_param(IS_I2S_MODE(hi2s->Init.Mode)); + assert_param(IS_I2S_STANDARD(hi2s->Init.Standard)); + assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat)); + assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput)); + assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq)); + assert_param(IS_I2S_CPOL(hi2s->Init.CPOL)); + + if(hi2s->State == HAL_I2S_STATE_RESET) + { + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_I2S_MspInit(hi2s); + } + + hi2s->State = HAL_I2S_STATE_BUSY; + + /*----------------------- SPIx I2SCFGR & I2SPR Configuration ---------------*/ + /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ + hi2s->Instance->I2SCFGR &= (uint16_t)(~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \ + SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \ + SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD)); + hi2s->Instance->I2SPR = 0x0002; + + /* Get the I2SCFGR register value */ + tmpreg = hi2s->Instance->I2SCFGR; + + /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ + if(hi2s->Init.AudioFreq == I2S_AUDIOFREQ_DEFAULT) + { + i2sodd = (uint16_t)0; + i2sdiv = (uint16_t)2; + } + /* If the requested audio frequency is not the default, compute the prescaler */ + else + { + /* Check the frame length (For the Prescaler computing) *******************/ + if(hi2s->Init.DataFormat == I2S_DATAFORMAT_16B) + { + /* Packet length is 16 bits */ + packetlength = 1; + } + else + { + /* Packet length is 32 bits */ + packetlength = 2; + } + + /* Get I2S source Clock frequency ****************************************/ + i2sclk = HAL_RCC_GetSysClockFreq(); + + /* Compute the Real divider depending on the MCLK output state, with a floating point */ + if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE) + { + /* MCLK output is enabled */ + tmp = (uint32_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5); + } + else + { + /* MCLK output is disabled */ + tmp = (uint32_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5); + } + + /* Remove the flatting point */ + tmp = tmp / 10; + + /* Check the parity of the divider */ + i2sodd = (uint32_t)(tmp & (uint32_t)1); + + /* Compute the i2sdiv prescaler */ + i2sdiv = (uint32_t)((tmp - i2sodd) / 2); + + /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ + i2sodd = (uint32_t) (i2sodd << 8); + } + + /* Test if the divider is 1 or 0 or greater than 0xFF */ + if((i2sdiv < 2) || (i2sdiv > 0xFF)) + { + /* Set the default values */ + i2sdiv = 2; + i2sodd = 0; + } + + /* Write to SPIx I2SPR register the computed value */ + hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput)); + + /* Configure the I2S with the I2S_InitStruct values */ + tmpreg |= (uint32_t)(SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | hi2s->Init.Standard | hi2s->Init.DataFormat | hi2s->Init.CPOL); + + /* Write to SPIx I2SCFGR */ + hi2s->Instance->I2SCFGR = tmpreg; + + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->State= HAL_I2S_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the I2S peripheral + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) +{ + /* Check the I2S handle allocation */ + if(hi2s == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance)); + + hi2s->State = HAL_I2S_STATE_BUSY; + + /* Disable the I2S Peripheral Clock */ + __HAL_I2S_DISABLE(hi2s); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + HAL_I2S_MspDeInit(hi2s); + + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->State = HAL_I2S_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hi2s); + + return HAL_OK; +} + +/** + * @brief I2S MSP Init + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ + __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_MspInit could be implemented in the user file + */ +} + +/** + * @brief I2S MSP DeInit + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ + __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup I2S_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the I2S data + transfers. + + (#) There are two modes of transfer: + (++) Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode : The communication is performed using Interrupts + or DMA. These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + + (#) Blocking mode functions are : + (++) HAL_I2S_Transmit() + (++) HAL_I2S_Receive() + + (#) No-Blocking mode functions with Interrupt are : + (++) HAL_I2S_Transmit_IT() + (++) HAL_I2S_Receive_IT() + + (#) No-Blocking mode functions with DMA are : + (++) HAL_I2S_Transmit_DMA() + (++) HAL_I2S_Receive_DMA() + + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (++) HAL_I2S_TxCpltCallback() + (++) HAL_I2S_RxCpltCallback() + (++) HAL_I2S_ErrorCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Transmit an amount of data in blocking mode + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param pData: a 16-bit pointer to data buffer. + * @param Size: number of data sample to be sent: + * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @param Timeout: Timeout duration + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * between Master and Slave(example: audio streaming). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout) +{ + if((pData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2s); + + if(hi2s->State == HAL_I2S_STATE_READY) + { + if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ + ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) + { + hi2s->TxXferSize = (Size << 1); + hi2s->TxXferCount = (Size << 1); + } + else + { + hi2s->TxXferSize = Size; + hi2s->TxXferCount = Size; + } + + /* Set state and reset error code */ + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->State = HAL_I2S_STATE_BUSY_TX; + hi2s->pTxBuffPtr = pData; + + /* Check if the I2S is already enabled */ + if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + + while(hi2s->TxXferCount > 0) + { + /* Wait until TXE flag is set */ + if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + hi2s->Instance->DR = (*hi2s->pTxBuffPtr++); + hi2s->TxXferCount--; + } + + /* Wait until TXE flag is set, to confirm the end of the transcation */ + if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + /* Wait until Busy flag is reset */ + if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + hi2s->State = HAL_I2S_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + + return HAL_OK; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in blocking mode + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param pData: a 16-bit pointer to data buffer. + * @param Size: number of data sample to be sent: + * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @param Timeout: Timeout duration + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * between Master and Slave(example: audio streaming). + * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate + * in continouse way and as the I2S is not disabled at the end of the I2S transaction. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout) +{ + if((pData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2s); + + if(hi2s->State == HAL_I2S_STATE_READY) + { + if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ + ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) + { + hi2s->RxXferSize = (Size << 1); + hi2s->RxXferCount = (Size << 1); + } + else + { + hi2s->RxXferSize = Size; + hi2s->RxXferCount = Size; + } + + /* Set state and reset error code */ + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->State = HAL_I2S_STATE_BUSY_RX; + hi2s->pRxBuffPtr = pData; + + /* Check if the I2S is already enabled */ + if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + + /* Receive data */ + while(hi2s->RxXferCount > 0) + { + /* Wait until RXNE flag is set */ + if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR; + hi2s->RxXferCount--; + } + + hi2s->State = HAL_I2S_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + + return HAL_OK; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + return HAL_BUSY; + } +} + +/** + * @brief Transmit an amount of data in non-blocking mode with Interrupt + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param pData: a 16-bit pointer to data buffer. + * @param Size: number of data sample to be sent: + * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * between Master and Slave(example: audio streaming). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) +{ + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2s); + + if(hi2s->State == HAL_I2S_STATE_READY) + { + hi2s->pTxBuffPtr = pData; + hi2s->State = HAL_I2S_STATE_BUSY_TX; + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + + if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ + ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) + { + hi2s->TxXferSize = (Size << 1); + hi2s->TxXferCount = (Size << 1); + } + else + { + hi2s->TxXferSize = Size; + hi2s->TxXferCount = Size; + } + + /* Enable TXE and ERR interrupt */ + __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + + /* Check if the I2S is already enabled */ + if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + + return HAL_OK; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in non-blocking mode with Interrupt + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param pData: a 16-bit pointer to the Receive data buffer. + * @param Size: number of data sample to be sent: + * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * between Master and Slave(example: audio streaming). + * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation + * between Master and Slave otherwise the I2S interrupt should be optimized. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) +{ + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2s); + + if(hi2s->State == HAL_I2S_STATE_READY) + { + hi2s->pRxBuffPtr = pData; + hi2s->State = HAL_I2S_STATE_BUSY_RX; + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + + if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ + ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) + { + hi2s->RxXferSize = (Size << 1); + hi2s->RxXferCount = (Size << 1); + } + else + { + hi2s->RxXferSize = Size; + hi2s->RxXferCount = Size; + } + + /* Enable TXE and ERR interrupt */ + __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); + + /* Check if the I2S is already enabled */ + if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + + return HAL_OK; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + return HAL_BUSY; + } +} + +/** + * @brief Transmit an amount of data in non-blocking mode with DMA + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param pData: a 16-bit pointer to the Transmit data buffer. + * @param Size: number of data sample to be sent: + * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * between Master and Slave(example: audio streaming). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) +{ + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2s); + + if(hi2s->State == HAL_I2S_STATE_READY) + { + hi2s->pTxBuffPtr = pData; + hi2s->State = HAL_I2S_STATE_BUSY_TX; + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + + if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ + ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) + { + hi2s->TxXferSize = (Size << 1); + hi2s->TxXferCount = (Size << 1); + } + else + { + hi2s->TxXferSize = Size; + hi2s->TxXferCount = Size; + } + + /* Set the I2S Tx DMA Half transfert complete callback */ + hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt; + + /* Set the I2S Tx DMA transfert complete callback */ + hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt; + + /* Set the DMA error callback */ + hi2s->hdmatx->XferErrorCallback = I2S_DMAError; + + /* Enable the Tx DMA Channel */ + HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize); + + /* Check if the I2S is already enabled */ + if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + + /* Check if the I2S Tx request is already enabled */ + if((hi2s->Instance->CR2 & SPI_CR2_TXDMAEN) != SPI_CR2_TXDMAEN) + { + /* Enable Tx DMA Request */ + hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + + return HAL_OK; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in non-blocking mode with DMA + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param pData: a 16-bit pointer to the Receive data buffer. + * @param Size: number of data sample to be sent: + * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * between Master and Slave(example: audio streaming). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) +{ + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2s); + + if(hi2s->State == HAL_I2S_STATE_READY) + { + hi2s->pRxBuffPtr = pData; + hi2s->State = HAL_I2S_STATE_BUSY_RX; + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + + if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ + ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) + { + hi2s->RxXferSize = (Size << 1); + hi2s->RxXferCount = (Size << 1); + } + else + { + hi2s->RxXferSize = Size; + hi2s->RxXferCount = Size; + } + + + /* Set the I2S Rx DMA Half transfert complete callback */ + hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt; + + /* Set the I2S Rx DMA transfert complete callback */ + hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt; + + /* Set the DMA error callback */ + hi2s->hdmarx->XferErrorCallback = I2S_DMAError; + + /* Check if Master Receiver mode is selected */ + if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX) + { + /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read + access to the SPI_SR register. */ + __HAL_I2S_CLEAR_OVRFLAG(hi2s); + } + + /* Enable the Rx DMA Channel */ + HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize); + + /* Check if the I2S is already enabled */ + if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + + /* Check if the I2S Rx request is already enabled */ + if((hi2s->Instance->CR2 &SPI_CR2_RXDMAEN) != SPI_CR2_RXDMAEN) + { + /* Enable Rx DMA Request */ + hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + + return HAL_OK; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + return HAL_BUSY; + } +} + +/** + * @brief Pauses the audio stream playing from the Media. + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s) +{ + /* Process Locked */ + __HAL_LOCK(hi2s); + + if(hi2s->State == HAL_I2S_STATE_BUSY_TX) + { + /* Disable the I2S DMA Tx request */ + hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_TXDMAEN); + } + else if(hi2s->State == HAL_I2S_STATE_BUSY_RX) + { + /* Disable the I2S DMA Rx request */ + hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_RXDMAEN); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + + return HAL_OK; +} + +/** + * @brief Resumes the audio stream playing from the Media. + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s) +{ + /* Process Locked */ + __HAL_LOCK(hi2s); + + if(hi2s->State == HAL_I2S_STATE_BUSY_TX) + { + /* Enable the I2S DMA Tx request */ + hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN; + } + else if(hi2s->State == HAL_I2S_STATE_BUSY_RX) + { + /* Enable the I2S DMA Rx request */ + hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN; + } + + /* If the I2S peripheral is still not enabled, enable it */ + if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + + return HAL_OK; +} + +/** + * @brief Resumes the audio stream playing from the Media. + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s) +{ + /* Process Locked */ + __HAL_LOCK(hi2s); + + /* Disable the I2S Tx/Rx DMA requests */ + hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_TXDMAEN); + hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_RXDMAEN); + + /* Disable the I2S DMA channel */ + __HAL_DMA_DISABLE(hi2s->hdmatx); + __HAL_DMA_DISABLE(hi2s->hdmarx); + + /* Abort the I2S DMA tx channel */ + if(hi2s->hdmatx != NULL) + { + HAL_DMA_Abort(hi2s->hdmatx); + } + /* Abort the I2S DMA rx channel */ + if(hi2s->hdmarx != NULL) + { + HAL_DMA_Abort(hi2s->hdmarx); + } + + /* Disable I2S peripheral */ + __HAL_I2S_DISABLE(hi2s); + + hi2s->State = HAL_I2S_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + + return HAL_OK; +} + +/** + * @brief This function handles I2S interrupt request. + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) +{ + uint32_t i2ssr = hi2s->Instance->SR; + + /* I2S in mode Receiver ------------------------------------------------*/ + if(((i2ssr & I2S_FLAG_OVR) != I2S_FLAG_OVR) && + ((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET)) + { + I2S_Receive_IT(hi2s); + return; + } + + /* I2S in mode Tramitter -----------------------------------------------*/ + if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET)) + { + I2S_Transmit_IT(hi2s); + return; + } + + /* I2S Overrun error interrupt occured ---------------------------------*/ + if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) + { + /* Disable RXNE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); + + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; + + /* Set the error code and execute error callback*/ + hi2s->ErrorCode |= HAL_I2S_ERROR_OVR; + HAL_I2S_ErrorCallback(hi2s); + } + + /* I2S Underrun error interrupt occured --------------------------------*/ + if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) + { + /* Disable TXE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; + + /* Set the error code and execute error callback*/ + hi2s->ErrorCode |= HAL_I2S_ERROR_UDR; + HAL_I2S_ErrorCallback(hi2s); + } +} + +/** + * @brief Tx Transfer Half completed callbacks + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ + __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_TxHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Tx Transfer completed callbacks + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ + __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Transfer half completed callbacks + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief I2S error callbacks + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ + __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the I2S state + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval HAL state + */ +HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s) +{ + return hi2s->State; +} + +/** + * @brief Return the I2S error code + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval I2S Error Code + */ +HAL_I2S_ErrorTypeDef HAL_I2S_GetError(I2S_HandleTypeDef *hi2s) +{ + return hi2s->ErrorCode; +} +/** + * @} + */ + +/** + * @} + */ + + +/** @defgroup I2S_Private_Functions I2S Private Functions + * @{ + */ +/** + * @brief DMA I2S transmit process complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma) +{ + I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) + { + /* Disable Tx DMA Request */ + hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_TXDMAEN); + + hi2s->TxXferCount = 0; + hi2s->State = HAL_I2S_STATE_READY; + } + HAL_I2S_TxCpltCallback(hi2s); +} + +/** + * @brief DMA I2S transmit process half complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma) +{ + I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + HAL_I2S_TxHalfCpltCallback(hi2s); +} + +/** + * @brief DMA I2S receive process complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma) +{ + I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) + { + /* Disable Rx DMA Request */ + hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_RXDMAEN); + hi2s->RxXferCount = 0; + hi2s->State = HAL_I2S_STATE_READY; + } + HAL_I2S_RxCpltCallback(hi2s); +} + +/** + * @brief DMA I2S receive process half complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma) +{ + I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + HAL_I2S_RxHalfCpltCallback(hi2s); +} + +/** + * @brief DMA I2S communication error callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void I2S_DMAError(DMA_HandleTypeDef *hdma) +{ + I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Disable Rx and Tx DMA Request */ + hi2s->Instance->CR2 &= (uint16_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN)); + hi2s->TxXferCount = 0; + hi2s->RxXferCount = 0; + + hi2s->State= HAL_I2S_STATE_READY; + + /* Set the error code and execute error callback*/ + hi2s->ErrorCode |= HAL_I2S_ERROR_DMA; + HAL_I2S_ErrorCallback(hi2s); +} + +/** + * @brief Transmit an amount of data in non-blocking mode with Interrupt + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s) +{ + /* Transmit data */ + hi2s->Instance->DR = (*hi2s->pTxBuffPtr++); + hi2s->TxXferCount--; + + if(hi2s->TxXferCount == 0) + { + /* Disable TXE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + + hi2s->State = HAL_I2S_STATE_READY; + HAL_I2S_TxCpltCallback(hi2s); + } +} + +/** +* @brief Receive an amount of data in non-blocking mode with Interrupt +* @param hi2s: I2S handle + * @retval None +*/ +static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s) +{ + /* Receive data */ + (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR; + hi2s->RxXferCount--; + + if(hi2s->RxXferCount == 0) + { + /* Disable RXNE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); + + hi2s->State = HAL_I2S_STATE_READY; + HAL_I2S_RxCpltCallback(hi2s); + } +} + + +/** + * @brief This function handles I2S Communication Timeout. + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param Flag: Flag checked + * @param State: Value of the flag expected + * @param Timeout: Duration of the timeout + * @retval HAL status + */ +static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + + /* Wait until flag is set */ + if(State == RESET) + { + while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + { + /* Set the I2S State ready */ + hi2s->State= HAL_I2S_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + + return HAL_TIMEOUT; + } + } + } + } + else + { + while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + { + /* Set the I2S State ready */ + hi2s->State= HAL_I2S_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + + return HAL_TIMEOUT; + } + } + } + } + return HAL_OK; +} + +/** + * @} + */ + +#endif /* defined(STM32F031x6) || defined(STM32F038xx) || */ + /* defined(STM32F051x8) || defined(STM32F058xx) || */ + /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || */ + /* defined(STM32F042x6) || defined(STM32F048xx) || */ + /* defined(STM32F091xC) || defined(STM32F098xx) */ + +#endif /* HAL_I2S_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_irda.c b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_irda.c new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_irda.c @@ -0,0 +1,1361 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_irda.c + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief IRDA HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the IrDA (Infrared Data Association) Peripheral + * (IRDA) + * + Initialization and de-initialization function + * + IO operation function + * + Peripheral Control function + * + * + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The IRDA HAL driver can be used as follows: + + (#) Declare a IRDA_HandleTypeDef handle structure. + (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API: + (##) Enable the USARTx interface clock. + (##) IRDA pins configuration: + (+++) Enable the clock for the IRDA GPIOs. + (+++) Configure these IRDA pins as alternate function pull-up. + (##) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT() + and HAL_IRDA_Receive_IT() APIs): + (+++) Configure the USARTx interrupt priority. + (+++) Enable the NVIC USART IRQ handle. + (##) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA() + and HAL_IRDA_Receive_DMA() APIs): + (+++) Declare a DMA handle structure for the Tx/Rx channel. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx channel. + (+++) Associate the initilalized DMA handle to the IRDA DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. + + (#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter), + the normal or low power mode and the clock prescaler in the hirda Init structure. + + (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API: + (++) This API configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc) + by calling the customed HAL_IRDA_MspInit() API. + + -@@- The specific IRDA interrupts (Transmission complete interrupt, + RXNE interrupt and Error Interrupts) will be managed using the macros + __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process. + + (#) Three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit() + (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive() + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Send an amount of data in non blocking mode using HAL_IRDA_Transmit_IT() + (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_IRDA_TxCpltCallback + (+) Receive an amount of data in non blocking mode using HAL_IRDA_Receive_IT() + (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_IRDA_RxCpltCallback + (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_IRDA_ErrorCallback + + *** DMA mode IO operation *** + ============================== + [..] + (+) Send an amount of data in non blocking mode (DMA) using HAL_IRDA_Transmit_DMA() + (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_IRDA_TxCpltCallback + (+) Receive an amount of data in non blocking mode (DMA) using HAL_IRDA_Receive_DMA() + (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_IRDA_RxCpltCallback + (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_IRDA_ErrorCallback + + *** IRDA HAL driver macros list *** + ==================================== + [..] + Below the list of most used macros in IRDA HAL driver. + + (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral + (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral + (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not + (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag + (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt + (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt + + [..] + (@) You can refer to the IRDA HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup IRDA IRDA HAL module driver + * @brief HAL IRDA module driver + * @{ + */ +#ifdef HAL_IRDA_MODULE_ENABLED + +#if !defined(STM32F030x6) && !defined(STM32F030x8) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup IRDA_Private_Constants IRDA Private Constants + * @{ + */ +#define TEACK_REACK_TIMEOUT 1000 +#define IRDA_TXDMA_TIMEOUTVALUE 22000 +#define IRDA_TIMEOUT_VALUE 22000 +#define IRDA_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE \ + | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup IRDA_Private_Functions IRDA Private Functions + * @{ + */ +static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void IRDA_DMAError(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda); +static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda); +static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout); +static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda); +static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda); +static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda); +/** + * @} + */ +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup IRDA_Exported_Functions IRDA Exported Functions + * @{ + */ + +/** @defgroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and Configuration functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USARTx + in IRDA mode. + (+) For the asynchronous mode only these parameters can be configured: + (++) Baud Rate + (++) Word Length + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + Depending on the frame length defined by the M bit (8-bits or 9-bits) + or by the M1 and M0 bits (7-bit, 8-bit or 9-bit), + the possible IRDA frame formats are as listed in the following table: + +---------------------------------------------------------------+ + | M bit | PCE bit | IRDA frame | + |-----------|-----------|---------------------------------------| + | 0 | 0 | | SB | 8-bit data | STB | | + |-----------|-----------|---------------------------------------| + | 0 | 1 | | SB | 7-bit data | PB | STB | | + |-----------|-----------|---------------------------------------| + | 1 | 0 | | SB | 9-bit data | STB | | + |-----------|-----------|---------------------------------------| + | 1 | 1 | | SB | 8-bit data | PB | STB | | + +---------------------------------------------------------------+ + | M1M0 bits | PCE bit | IRDA frame | + |-----------------------|---------------------------------------| + | 10 | 0 | | SB | 7-bit data | STB | | + |-----------|-----------|---------------------------------------| + | 10 | 1 | | SB | 6-bit data | PB | STB | | + +---------------------------------------------------------------+ + + (++) Power mode + (++) Prescaler setting + (++) Receiver/transmitter modes + + [..] + The HAL_IRDA_Init() function follows IRDA configuration procedures + (details for the procedures are available in reference manual). + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the IRDA mode according to the specified + * parameters in the IRDA_InitTypeDef and creates the associated handle . + * @param hirda: IRDA handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda) +{ + /* Check the IRDA handle allocation */ + if(hirda == NULL) + { + return HAL_ERROR; + } + + /* Check the USART/UART associated to the IRDA handle */ + assert_param(IS_IRDA_INSTANCE(hirda->Instance)); + + if(hirda->State == HAL_IRDA_STATE_RESET) + { + /* Init the low level hardware : GPIO, CLOCK */ + HAL_IRDA_MspInit(hirda); + } + + hirda->State = HAL_IRDA_STATE_BUSY; + + /* Disable the Peripheral to update the configuration registers */ + __HAL_IRDA_DISABLE(hirda); + + /* Set the IRDA Communication parameters */ + if (IRDA_SetConfig(hirda) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* In IRDA mode, the following bits must be kept cleared: + - LINEN, STOP and CLKEN bits in the USART_CR2 register, + - SCEN and HDSEL bits in the USART_CR3 register.*/ + hirda->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP); + hirda->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL); + + /* set the UART/USART in IRDA mode */ + hirda->Instance->CR3 |= USART_CR3_IREN; + + /* Enable the Peripheral */ + __HAL_IRDA_ENABLE(hirda); + + /* TEACK and/or REACK to check before moving hirda->State to Ready */ + return (IRDA_CheckIdleState(hirda)); +} + +/** + * @brief DeInitializes the IRDA peripheral + * @param hirda: IRDA handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) +{ + /* Check the IRDA handle allocation */ + if(hirda == NULL) + { + return HAL_ERROR; + } + + /* Check the USART/UART associated to the IRDA handle */ + assert_param(IS_IRDA_INSTANCE(hirda->Instance)); + + hirda->State = HAL_IRDA_STATE_BUSY; + + /* DeInit the low level hardware */ + HAL_IRDA_MspDeInit(hirda); + /* Disable the Peripheral */ + __HAL_IRDA_DISABLE(hirda); + + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + hirda->State = HAL_IRDA_STATE_RESET; + + /* Process Unlock */ + __HAL_UNLOCK(hirda); + + return HAL_OK; +} + +/** + * @brief IRDA MSP Init + * @param hirda: IRDA handle + * @retval None + */ + __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_IRDA_MspInit can be implemented in the user file + */ +} + +/** + * @brief IRDA MSP DeInit + * @param hirda: IRDA handle + * @retval None + */ + __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_IRDA_MspDeInit can be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup IRDA_Exported_Functions_Group2 IO operation functions + * @brief IRDA Transmit and Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the IRDA data transfers. + + [..] + IrDA is a half duplex communication protocol. If the Transmitter is busy, any data + on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver + is busy, data on the TX from the USART to IrDA will not be encoded by IrDA. + While receiving data, transmission should be avoided as the data to be transmitted + could be corrupted. + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) Non Blocking mode: The communication is performed using Interrupts + or DMA, these API s return the HAL status. + The end of the data processing will be indicated through the + dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks + will be executed respectivelly at the end of the Transmit or Receive process + The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected + + (#) Blocking mode API s are : + (++) HAL_IRDA_Transmit() + (++) HAL_IRDA_Receive() + + (#) Non Blocking mode API s with Interrupt are : + (++) HAL_IRDA_Transmit_IT() + (++) HAL_IRDA_Receive_IT() + (++) HAL_IRDA_IRQHandler() + (++) IRDA_Transmit_IT() + (++) IRDA_Receive_IT() + + (#) Non Blocking mode functions with DMA are : + (++) HAL_IRDA_Transmit_DMA() + (++) HAL_IRDA_Receive_DMA() + + (#) A set of Transfer Complete Callbacks are provided in Non Blocking mode: + (++) HAL_IRDA_TxCpltCallback() + (++) HAL_IRDA_RxCpltCallback() + (++) HAL_IRDA_ErrorCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Send an amount of data in blocking mode + * @param hirda: IRDA handle + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @param Timeout: Duration of the timeout + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint16_t* tmp; + + if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX)) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hirda); + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + + if(hirda->State == HAL_IRDA_STATE_BUSY_RX) + { + hirda->State = HAL_IRDA_STATE_BUSY_TX_RX; + } + else + { + hirda->State = HAL_IRDA_STATE_BUSY_TX; + } + + hirda->TxXferSize = Size; + hirda->TxXferCount = Size; + while(hirda->TxXferCount > 0) + { + hirda->TxXferCount--; + + if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) + { + tmp = (uint16_t*) pData; + hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF); + pData += 2; + } + else + { + hirda->Instance->TDR = (*pData++ & (uint8_t)0xFF); + } + } + + if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) + { + hirda->State = HAL_IRDA_STATE_BUSY_RX; + } + else + { + hirda->State = HAL_IRDA_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in blocking mode + * @param hirda: IRDA handle + * @param pData: pointer to data buffer + * @param Size: amount of data to be received + * @param Timeout: Duration of the timeout + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint16_t* tmp; + uint16_t uhMask; + + if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX)) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hirda); + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + + if(hirda->State == HAL_IRDA_STATE_BUSY_TX) + { + hirda->State = HAL_IRDA_STATE_BUSY_TX_RX; + } + else + { + hirda->State = HAL_IRDA_STATE_BUSY_RX; + } + + hirda->RxXferSize = Size; + hirda->RxXferCount = Size; + + /* Computation of the mask to apply to the RDR register + of the UART associated to the IRDA */ + __HAL_IRDA_MASK_COMPUTATION(hirda); + uhMask = hirda->Mask; + + /* Check data remaining to be received */ + while(hirda->RxXferCount > 0) + { + hirda->RxXferCount--; + + if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) + { + tmp = (uint16_t*) pData ; + *tmp = (uint16_t)(hirda->Instance->RDR & uhMask); + pData +=2; + } + else + { + *pData++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask); + } + } + + if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) + { + hirda->State = HAL_IRDA_STATE_BUSY_TX; + } + else + { + hirda->State = HAL_IRDA_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Send an amount of data in interrupt mode + * @param hirda: IRDA handle + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) +{ + if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX)) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hirda); + + hirda->pTxBuffPtr = pData; + hirda->TxXferSize = Size; + hirda->TxXferCount = Size; + + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + if(hirda->State == HAL_IRDA_STATE_BUSY_RX) + { + hirda->State = HAL_IRDA_STATE_BUSY_TX_RX; + } + else + { + hirda->State = HAL_IRDA_STATE_BUSY_TX; + } + + /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR); + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + /* Enable the IRDA Transmit Data Register Empty Interrupt */ + __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TXE); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in interrupt mode + * @param hirda: IRDA handle + * @param pData: pointer to data buffer + * @param Size: amount of data to be received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) +{ + if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX)) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hirda); + + hirda->pRxBuffPtr = pData; + hirda->RxXferSize = Size; + hirda->RxXferCount = Size; + + /* Computation of the mask to apply to the RDR register + of the UART associated to the IRDA */ + __HAL_IRDA_MASK_COMPUTATION(hirda); + + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + if(hirda->State == HAL_IRDA_STATE_BUSY_TX) + { + hirda->State = HAL_IRDA_STATE_BUSY_TX_RX; + } + else + { + hirda->State = HAL_IRDA_STATE_BUSY_RX; + } + + /* Enable the IRDA Parity Error Interrupt */ + __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_PE); + + /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR); + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + /* Enable the IRDA Data Register not empty Interrupt */ + __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_RXNE); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Send an amount of data in DMA mode + * @param hirda: IRDA handle + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) +{ + uint32_t *tmp; + + if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX)) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hirda); + + hirda->pTxBuffPtr = pData; + hirda->TxXferSize = Size; + hirda->TxXferCount = Size; + + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + + if(hirda->State == HAL_IRDA_STATE_BUSY_RX) + { + hirda->State = HAL_IRDA_STATE_BUSY_TX_RX; + } + else + { + hirda->State = HAL_IRDA_STATE_BUSY_TX; + } + + /* Set the IRDA DMA transfer complete callback */ + hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt; + + /* Set the DMA error callback */ + hirda->hdmatx->XferErrorCallback = IRDA_DMAError; + + /* Enable the IRDA transmit DMA channel */ + tmp = (uint32_t*)&pData; + HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t*)tmp, (uint32_t)&hirda->Instance->TDR, Size); + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the IRDA CR3 register */ + hirda->Instance->CR3 |= USART_CR3_DMAT; + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in DMA mode + * @param hirda: IRDA handle + * @param pData: pointer to data buffer + * @param Size: amount of data to be received + * @note When the IRDA parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) +{ + uint32_t *tmp; + + if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX)) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hirda); + + hirda->pRxBuffPtr = pData; + hirda->RxXferSize = Size; + + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + if(hirda->State == HAL_IRDA_STATE_BUSY_TX) + { + hirda->State = HAL_IRDA_STATE_BUSY_TX_RX; + } + else + { + hirda->State = HAL_IRDA_STATE_BUSY_RX; + } + + /* Set the IRDA DMA transfer complete callback */ + hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt; + + /* Set the DMA error callback */ + hirda->hdmarx->XferErrorCallback = IRDA_DMAError; + + /* Enable the DMA channel */ + tmp = (uint32_t*)&pData; + HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, *(uint32_t*)tmp, Size); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the IRDA CR3 register */ + hirda->Instance->CR3 |= USART_CR3_DMAR; + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief This function handles IRDA interrupt request. + * @param hirda: IRDA handle + * @retval None + */ +void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) +{ + /* IRDA parity error interrupt occurred -------------------------------------*/ + if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_PE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_PE) != RESET)) + { + __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF); + + hirda->ErrorCode |= HAL_IRDA_ERROR_PE; + /* Set the IRDA state ready to be able to start again the process */ + hirda->State = HAL_IRDA_STATE_READY; + } + + /* IRDA frame error interrupt occured --------------------------------------*/ + if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_FE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET)) + { + __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF); + + hirda->ErrorCode |= HAL_IRDA_ERROR_FE; + /* Set the IRDA state ready to be able to start again the process */ + hirda->State = HAL_IRDA_STATE_READY; + } + + /* IRDA noise error interrupt occured --------------------------------------*/ + if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_NE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET)) + { + __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF); + + hirda->ErrorCode |= HAL_IRDA_ERROR_NE; + /* Set the IRDA state ready to be able to start again the process */ + hirda->State = HAL_IRDA_STATE_READY; + } + + /* IRDA Over-Run interrupt occured -----------------------------------------*/ + if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_ORE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET)) + { + __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF); + + hirda->ErrorCode |= HAL_IRDA_ERROR_ORE; + /* Set the IRDA state ready to be able to start again the process */ + hirda->State = HAL_IRDA_STATE_READY; + } + + /* Call IRDA Error Call back function if need be --------------------------*/ + if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE) + { + HAL_IRDA_ErrorCallback(hirda); + } + + /* IRDA in mode Receiver ---------------------------------------------------*/ + if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_RXNE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_RXNE) != RESET)) + { + IRDA_Receive_IT(hirda); + /* Clear RXNE interrupt flag */ + __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST); + } + + + /* IRDA in mode Transmitter ------------------------------------------------*/ + if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_TXE) != RESET) &&(__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TXE) != RESET)) + { + IRDA_Transmit_IT(hirda); + } + + /* IRDA in mode Transmitter (transmission end) -----------------------------*/ + if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_TC) != RESET) &&(__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TC) != RESET)) + { + IRDA_EndTransmit_IT(hirda); + } + +} +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup IRDA_Private_Functions IRDA Private Functions + * @{ + */ + +/** + * @brief DMA IRDA Tx transfer completed callback + * @param hdma: DMA handle + * @retval None + */ +static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + hirda->TxXferCount = 0; + + /* Disable the DMA transfer for transmit request by resetting the DMAT bit + in the IRDA CR3 register */ + hirda->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAT); + + /* Enable the IRDA Transmit Complete Interrupt */ + __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC); +} + +/** + * @brief DMA IRDA Rx Transfer completed callback + * @param hdma: DMA handle + * @retval None + */ +static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + hirda->RxXferCount = 0; + + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the IRDA CR3 register */ + hirda->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAR); + + if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) + { + hirda->State = HAL_IRDA_STATE_BUSY_TX; + } + else + { + hirda->State = HAL_IRDA_STATE_READY; + } + + HAL_IRDA_RxCpltCallback(hirda); +} + +/** + * @brief DMA IRDA communication error callback + * @param hdma: DMA handle + * @retval None + */ +static void IRDA_DMAError(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + hirda->RxXferCount = 0; + hirda->TxXferCount = 0; + hirda->State= HAL_IRDA_STATE_READY; + hirda->ErrorCode |= HAL_IRDA_ERROR_DMA; + HAL_IRDA_ErrorCallback(hirda); +} +/** + * @} + */ + +/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions + * @{ + */ + +/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions + * @{ + */ + +/** + * @brief Tx Transfer completed callback + * @param hirda: irda handle + * @retval None + */ + __weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_IRDA_TxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callback + * @param hirda: irda handle + * @retval None + */ +__weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_IRDA_TxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief IRDA error callback + * @param hirda: IRDA handle + * @retval None + */ + __weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_IRDA_ErrorCallback can be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup IRDA_Private_Functions IRDA Private Functions + * @{ + */ + +/** + * @brief Receive an amount of data in non blocking mode. + * Function called under interruption only, once + * interruptions have been enabled by HAL_IRDA_Transmit_IT() + * @param hirda: IRDA handle + * @retval HAL status + */ +static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) +{ + uint16_t* tmp; + + if((hirda->State == HAL_IRDA_STATE_BUSY_TX) || (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)) + { + + if(hirda->TxXferCount == 0) + { + /* Disable the IRDA Transmit Data Register Empty Interrupt */ + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE); + + /* Enable the IRDA Transmit Complete Interrupt */ + __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC); + + return HAL_OK; + } + else + { + if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) + { + tmp = (uint16_t*) hirda->pTxBuffPtr; + hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF); + hirda->pTxBuffPtr += 2; + } + else + { + hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0xFF); + } + hirda->TxXferCount--; + + return HAL_OK; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Wraps up transmission in non blocking mode. + * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval HAL status + */ +static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda) +{ + /* Disable the IRDA Transmit Complete Interrupt */ + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TC); + + /* Check if a receive process is ongoing or not */ + if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) + { + hirda->State = HAL_IRDA_STATE_BUSY_RX; + } + else + { + /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); + + hirda->State = HAL_IRDA_STATE_READY; + } + + HAL_IRDA_TxCpltCallback(hirda); + + return HAL_OK; +} + + +/** + * @brief Receive an amount of data in non blocking mode. + * Function called under interruption only, once + * interruptions have been enabled by HAL_IRDA_Receive_IT() + * @param hirda: IRDA handle + * @retval HAL status + */ +static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) +{ + uint16_t* tmp; + uint16_t uhMask = hirda->Mask; + + if ((hirda->State == HAL_IRDA_STATE_BUSY_RX) || (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)) + { + + if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) + { + tmp = (uint16_t*) hirda->pRxBuffPtr ; + *tmp = (uint16_t)(hirda->Instance->RDR & uhMask); + hirda->pRxBuffPtr +=2; + } + else + { + *hirda->pRxBuffPtr++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask); + } + + if(--hirda->RxXferCount == 0) + { + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE); + + if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) + { + hirda->State = HAL_IRDA_STATE_BUSY_TX; + } + else + { + /* Disable the IRDA Parity Error Interrupt */ + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE); + + /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); + + hirda->State = HAL_IRDA_STATE_READY; + } + + HAL_IRDA_RxCpltCallback(hirda); + + return HAL_OK; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @} + */ + +/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions + * @{ + */ + +/** @defgroup IRDA_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief IRDA control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the IRDA. + (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state of the IRDA peripheral. + (+) IRDA_SetConfig() API is used to configure the IRDA communications parameters. +@endverbatim + * @{ + */ + +/** + * @brief return the IRDA state + * @param hirda: irda handle + * @retval HAL state + */ +HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda) +{ + return hirda->State; +} + +/** +* @brief Return the IRDA error code +* @param hirda : pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA. +* @retval IRDA Error Code +*/ +uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda) +{ + return hirda->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup IRDA_Private_Functions IRDA Private Functions + * @{ + */ + +/** + * @brief Configure the IRDA peripheral + * @param hirda: irda handle + * @retval None + */ +static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) +{ + uint32_t tmpreg = 0x00000000; + IRDA_ClockSourceTypeDef clocksource = IRDA_CLOCKSOURCE_UNDEFINED; + HAL_StatusTypeDef ret = HAL_OK; + + /* Check the communication parameters */ + assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate)); + assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength)); + assert_param(IS_IRDA_PARITY(hirda->Init.Parity)); + assert_param(IS_IRDA_TX_RX_MODE(hirda->Init.Mode)); + assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler)); + assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode)); + + /*-------------------------- USART CR1 Configuration -----------------------*/ + /* Configure the IRDA Word Length, Parity and transfer Mode: + Set the M bits according to hirda->Init.WordLength value + Set PCE and PS bits according to hirda->Init.Parity value + Set TE and RE bits according to hirda->Init.Mode value */ + tmpreg = (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode ; + + MODIFY_REG(hirda->Instance->CR1, IRDA_CR1_FIELDS, tmpreg); + + /*-------------------------- USART CR3 Configuration -----------------------*/ + MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode); + + /*-------------------------- USART GTPR Configuration ----------------------*/ + MODIFY_REG(hirda->Instance->GTPR, USART_GTPR_PSC, hirda->Init.Prescaler); + + /*-------------------------- USART BRR Configuration -----------------------*/ + __HAL_IRDA_GETCLOCKSOURCE(hirda, clocksource); + switch (clocksource) + { + case IRDA_CLOCKSOURCE_PCLK1: + hirda->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK1Freq() / hirda->Init.BaudRate); + break; + case IRDA_CLOCKSOURCE_HSI: + hirda->Instance->BRR = (uint16_t)(HSI_VALUE / hirda->Init.BaudRate); + break; + case IRDA_CLOCKSOURCE_SYSCLK: + hirda->Instance->BRR = (uint16_t)(HAL_RCC_GetSysClockFreq() / hirda->Init.BaudRate); + break; + case IRDA_CLOCKSOURCE_LSE: + hirda->Instance->BRR = (uint16_t)(LSE_VALUE / hirda->Init.BaudRate); + break; + case IRDA_CLOCKSOURCE_UNDEFINED: + default: + ret = HAL_ERROR; + break; + } + + return ret; +} + +/** + * @brief Check the IRDA Idle State + * @param hirda: IRDA handle + * @retval HAL status + */ +static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda) +{ + + /* Initialize the IRDA ErrorCode */ + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + + /* Check if the Transmitter is enabled */ + if((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + { + /* Wait until TEACK flag is set */ + if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, TEACK_REACK_TIMEOUT) != HAL_OK) + { + /* Timeout Occured */ + return HAL_TIMEOUT; + } + } + /* Check if the Receiver is enabled */ + if((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + { + if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, TEACK_REACK_TIMEOUT) != HAL_OK) + { + /* Timeout Occured */ + return HAL_TIMEOUT; + } + } + + /* Initialize the IRDA state*/ + hirda->State= HAL_IRDA_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_OK; +} + +/** + * @brief Handle IRDA Communication Timeout. + * @param hirda: IRDA handle + * @param Flag: specifies the IRDA flag to check. + * @param Status: the flag status (SET or RESET). The function is locked in a while loop as long as the flag remains set to Status. + * @param Timeout: Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + + /* Wait until flag is set */ + if(Status == RESET) + { + while(__HAL_IRDA_GET_FLAG(hirda, Flag) == RESET) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE); + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE); + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE); + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); + + hirda->State= HAL_IRDA_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_TIMEOUT; + } + } + } + } + else + { + while(__HAL_IRDA_GET_FLAG(hirda, Flag) != RESET) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE); + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE); + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE); + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); + + hirda->State= HAL_IRDA_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_TIMEOUT; + } + } + } + } + return HAL_OK; +} + +/** + * @} + */ + +#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */ + +#endif /* HAL_IRDA_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_iwdg.c b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_iwdg.c new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_iwdg.c @@ -0,0 +1,416 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_iwdg.c + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief IWDG HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the IWDG peripheral: + * + Initialization and Configuration functions + * + IO operation functions + * + Peripheral State functions + * + @verbatim + =============================================================================== + ##### IWDG Specific features ##### + =============================================================================== + [..] + (+) The IWDG can be started by either software or hardware (configurable + through option byte). + (+) The IWDG is clocked by its own dedicated Low-Speed clock (LSI) and + thus stays active even if the main clock fails. + (+) Once the IWDG is started, the LSI is forced ON and cannot be disabled + (LSI cannot be disabled too), and the counter starts counting down from + the reset value of 0xFFF. When it reaches the end of count value (0x000) + a system reset is generated. + (+) The IWDG counter should be refreshed at regular intervals, otherwise the + watchdog generates an MCU reset when the counter reaches 0. + (+) The IWDG is implemented in the VDD voltage domain that is still functional + in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY). + (+) IWDGRST flag in RCC_CSR register can be used to inform when an IWDG + reset occurs. + (+) Min-max timeout value @41KHz (LSI): ~0.1ms / ~25.5s + The IWDG timeout may vary due to LSI frequency dispersion. STM32F0x + devices provide the capability to measure the LSI frequency (LSI clock + connected internally to TIM16 CH1 input capture). The measured value + can be used to have an IWDG timeout with an acceptable accuracy. + For more information, please refer to the STM32F0x Reference manual. + + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + (#) if Window option is disabled + (++) Use IWDG using HAL_IWDG_Init() function to : + (+++) Enable write access to IWDG_PR, IWDG_RLR. + (+++) Configure the IWDG prescaler, counter reload value. + This reload value will be loaded in the IWDG counter each time the counter + is reloaded, then the IWDG will start counting down from this value. + (++) Use IWDG using HAL_IWDG_Start() function to : + (+++) Reload IWDG counter with value defined in the IWDG_RLR register. + (+++) Start the IWDG, when the IWDG is used in software mode (no need + to enable the LSI, it will be enabled by hardware). + (++) Then the application program must refresh the IWDG counter at regular + intervals during normal operation to prevent an MCU reset, using + HAL_IWDG_Refresh() function. + (#) if Window option is enabled: + (++) Use IWDG using HAL_IWDG_Start() function to enable IWDG downcounter + (++) Use IWDG using HAL_IWDG_Init() function to : + (+++) Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers. + (+++) Configure the IWDG prescaler, reload value and window value. + (++) Then the application program must refresh the IWDG counter at regular + intervals during normal operation to prevent an MCU reset, using + HAL_IWDG_Refresh() function. + + *** IWDG HAL driver macros list *** + ==================================== + [..] + Below the list of most used macros in IWDG HAL driver. + + (+) __HAL_IWDG_START: Enable the IWDG peripheral + (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in the reload register + (+) __HAL_IWDG_ENABLE_WRITE_ACCESS : Enable write access to IWDG_PR and IWDG_RLR registers + (+) __HAL_IWDG_DISABLE_WRITE_ACCESS : Disable write access to IWDG_PR and IWDG_RLR registers + (+) __HAL_IWDG_GET_FLAG: Get the selected IWDG's flag status + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup IWDG IWDG HAL module driver + * @brief IWDG HAL module driver. + * @{ + */ + +#ifdef HAL_IWDG_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup IWDG_Private_Defines IWDG Private Defines + * @{ + */ + +#define HAL_IWDG_DEFAULT_TIMEOUT (uint32_t)1000 + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup IWDG_Exported_Functions IWDG Exported Functions + * @{ + */ + +/** @defgroup IWDG_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions. + * +@verbatim + =============================================================================== + ##### Initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize the IWDG according to the specified parameters + in the IWDG_InitTypeDef and create the associated handle + (+) Manage Window option + (+) Initialize the IWDG MSP + (+) DeInitialize IWDG MSP + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the IWDG according to the specified + * parameters in the IWDG_InitTypeDef and creates the associated handle. + * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains + * the configuration information for the specified IWDG module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) +{ + uint32_t tickstart = 0; + + /* Check the IWDG handle allocation */ + if(hiwdg == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance)); + assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler)); + assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload)); + assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window)); + + /* Check pending flag, if previous update not done, return error */ + if((__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_PVU) != RESET) + &&(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET) + &&(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_WVU) != RESET)) + { + return HAL_ERROR; + } + + if(hiwdg->State == HAL_IWDG_STATE_RESET) + { + /* Init the low level hardware */ + HAL_IWDG_MspInit(hiwdg); + } + + /* Change IWDG peripheral state */ + hiwdg->State = HAL_IWDG_STATE_BUSY; + + /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers */ + /* by writing 0x5555 in KR */ + __HAL_IWDG_ENABLE_WRITE_ACCESS(hiwdg); + + /* Write to IWDG registers the IWDG_Prescaler & IWDG_Reload values to work with */ + MODIFY_REG(hiwdg->Instance->PR, IWDG_PR_PR, hiwdg->Init.Prescaler); + MODIFY_REG(hiwdg->Instance->RLR, IWDG_RLR_RL, hiwdg->Init.Reload); + + /* check if window option is enabled */ + if (((hiwdg->Init.Window) != IWDG_WINDOW_DISABLE) || ((hiwdg->Instance->WINR) != IWDG_WINDOW_DISABLE)) + { + tickstart = HAL_GetTick(); + + /* Wait for register to be updated */ + while((uint32_t)(hiwdg->Instance->SR) != RESET) + { + if((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT) + { + /* Set IWDG state */ + hiwdg->State = HAL_IWDG_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + + /* Write to IWDG WINR the IWDG_Window value to compare with */ + MODIFY_REG(hiwdg->Instance->WINR, IWDG_WINR_WIN, hiwdg->Init.Window); + + } + /* Change IWDG peripheral state */ + hiwdg->State = HAL_IWDG_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the IWDG MSP. + * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains + * the configuration information for the specified IWDG module. + * @retval None + */ +__weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_IWDG_MspInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Start the IWDG. + (+) Refresh the IWDG. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the IWDG. + * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains + * the configuration information for the specified IWDG module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg) +{ + uint32_t tickstart = 0; + + /* Process Locked */ + __HAL_LOCK(hiwdg); + + /* Change IWDG peripheral state */ + hiwdg->State = HAL_IWDG_STATE_BUSY; + + /* Reload IWDG counter with value defined in the RLR register */ + if ((hiwdg->Init.Window) == IWDG_WINDOW_DISABLE) + { + __HAL_IWDG_RELOAD_COUNTER(hiwdg); + } + + /* Enable the IWDG peripheral */ + __HAL_IWDG_START(hiwdg); + + tickstart = HAL_GetTick(); + + /* Wait until PVU, RVU, WVU flag are RESET */ + while( (__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_PVU) != RESET) + &&(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET) + &&(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_WVU) != RESET) ) + { + if((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT) + { + /* Set IWDG state */ + hiwdg->State = HAL_IWDG_STATE_TIMEOUT; + + /* Process unlocked */ + __HAL_UNLOCK(hiwdg); + + return HAL_TIMEOUT; + } + } + + /* Change IWDG peripheral state */ + hiwdg->State = HAL_IWDG_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hiwdg); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Refreshes the IWDG. + * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains + * the configuration information for the specified IWDG module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) + { + uint32_t tickstart = 0; + + /* Process Locked */ + __HAL_LOCK(hiwdg); + + /* Change IWDG peripheral state */ + hiwdg->State = HAL_IWDG_STATE_BUSY; + + tickstart = HAL_GetTick(); + + /* Wait until RVU flag is RESET */ + while(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET) + { + if((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT) + { + /* Set IWDG state */ + hiwdg->State = HAL_IWDG_STATE_TIMEOUT; + + /* Process unlocked */ + __HAL_UNLOCK(hiwdg); + + return HAL_TIMEOUT; + } + } + + /* Reload IWDG counter with value defined in the reload register */ + __HAL_IWDG_RELOAD_COUNTER(hiwdg); + + /* Change IWDG peripheral state */ + hiwdg->State = HAL_IWDG_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hiwdg); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup IWDG_Exported_Functions_Group3 Peripheral State functions + * @brief Peripheral State functions. + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the IWDG state. + * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains + * the configuration information for the specified IWDG module. + * @retval HAL state + */ +HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg) +{ + return hiwdg->State; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_IWDG_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_msp_template.c b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_msp_template.c new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_msp_template.c @@ -0,0 +1,129 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_msp_template.c + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief HAL MSP module. + * This file template is located in the HAL folder and should be copied + * to the user folder. + * + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + This file is generated automatically by MicroXplorer and eventually modified + by the user + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup HAL_MSP HAL MSP module driver + * @brief HAL MSP module. + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup HAL_MSP_Private_Functions HAL MSP Private Functions + * @{ + */ + +/** + * @brief Initializes the Global MSP. + * @retval None + */ +void HAL_MspInit(void) +{ + /* NOTE : This function is generated automatically by MicroXplorer and eventually + modified by the user + */ +} + +/** + * @brief DeInitializes the Global MSP. + * @retval None + */ +void HAL_MspDeInit(void) +{ + /* NOTE : This function is generated automatically by MicroXplorer and eventually + modified by the user + */ +} + +/** + * @brief Initializes the PPP MSP. + * @retval None + */ +void HAL_PPP_MspInit(void) +{ + /* NOTE : This function is generated automatically by MicroXplorer and eventually + modified by the user + */ +} + +/** + * @brief DeInitializes the PPP MSP. + * @retval None + */ +void HAL_PPP_MspDeInit(void) +{ + /* NOTE : This function is generated automatically by MicroXplorer and eventually + modified by the user + */ +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.c b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.c new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.c @@ -0,0 +1,1360 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_pcd.c + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief PCD HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the USB Peripheral Controller: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The PCD HAL driver can be used as follows: + + (#) Declare a PCD_HandleTypeDef handle structure, for example: + PCD_HandleTypeDef hpcd; + + (#) Fill parameters of Init structure in HCD handle + + (#) Call HAL_PCD_Init() API to initialize the HCD peripheral (Core, Device core, ...) + + (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API: + (##) Enable the PCD/USB Low Level interface clock using + (+++) __USB_CLK_ENABLE); + + (##) Initialize the related GPIO clocks + (##) Configure PCD pin-out + (##) Configure PCD NVIC interrupt + + (#)Associate the Upper USB device stack to the HAL PCD Driver: + (##) hpcd.pData = pdev; + + (#)Enable HCD transmission and reception: + (##) HAL_PCD_Start(); + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +#ifdef HAL_PCD_MODULE_ENABLED + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup PCD PCD HAL module driver + * @brief PCD HAL module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup PCD_Private_Define PCD Private Define + * @{ + */ +#define BTABLE_ADDRESS (0x000) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup PCD_Private_Functions PCD Private Functions + * @{ + */ +static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd); +void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); +void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); +/** + * @} + */ +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup PCD_Exported_Functions PCD Exported Functions + * @{ + */ + +/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the PCD according to the specified + * parameters in the PCD_InitTypeDef and create the associated handle. + * @param hpcd: PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) +{ + uint32_t i = 0; + + uint32_t wInterrupt_Mask = 0; + + /* Check the PCD handle allocation */ + if(hpcd == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); + + hpcd->State = PCD_BUSY; + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_PCD_MspInit(hpcd); + + /* Init endpoints structures */ + for (i = 0; i < hpcd->Init.dev_endpoints ; i++) + { + /* Init ep structure */ + hpcd->IN_ep[i].is_in = 1; + hpcd->IN_ep[i].num = i; + /* Control until ep is actvated */ + hpcd->IN_ep[i].type = PCD_EP_TYPE_CTRL; + hpcd->IN_ep[i].maxpacket = 0; + hpcd->IN_ep[i].xfer_buff = 0; + hpcd->IN_ep[i].xfer_len = 0; + } + + for (i = 0; i < hpcd->Init.dev_endpoints ; i++) + { + hpcd->OUT_ep[i].is_in = 0; + hpcd->OUT_ep[i].num = i; + /* Control until ep is activated */ + hpcd->OUT_ep[i].type = PCD_EP_TYPE_CTRL; + hpcd->OUT_ep[i].maxpacket = 0; + hpcd->OUT_ep[i].xfer_buff = 0; + hpcd->OUT_ep[i].xfer_len = 0; + } + + /* Init Device */ + /*CNTR_FRES = 1*/ + hpcd->Instance->CNTR = USB_CNTR_FRES; + + /*CNTR_FRES = 0*/ + hpcd->Instance->CNTR = 0; + + /*Clear pending interrupts*/ + hpcd->Instance->ISTR = 0; + + /*Set Btable Adress*/ + hpcd->Instance->BTABLE = BTABLE_ADDRESS; + + /*set wInterrupt_Mask global variable*/ + wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \ + | USB_CNTR_ESOFM | USB_CNTR_RESETM; + + /*Set interrupt mask*/ + hpcd->Instance->CNTR = wInterrupt_Mask; + + hpcd->USB_Address = 0; + hpcd->State= PCD_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the PCD peripheral + * @param hpcd: PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) +{ + /* Check the PCD handle allocation */ + if(hpcd == NULL) + { + return HAL_ERROR; + } + + hpcd->State = PCD_BUSY; + + /* Stop Device */ + HAL_PCD_Stop(hpcd); + + /* DeInit the low level hardware */ + HAL_PCD_MspDeInit(hpcd); + + hpcd->State = PCD_READY; + + return HAL_OK; +} + +/** + * @brief Initializes the PCD MSP. + * @param hpcd: PCD handle + * @retval None + */ +__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes PCD MSP. + * @param hpcd: PCD handle + * @retval None + */ +__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup PCD_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the PCD data + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Start The USB OTG Device. + * @param hpcd: PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) +{ + /* Enabling DP Pull-Down bit to Connect internal pull-up on USB DP line */ + hpcd->Instance->BCDR |= USB_BCDR_DPPU; + + return HAL_OK; +} + +/** + * @brief Stop The USB OTG Device. + * @param hpcd: PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) +{ + __HAL_LOCK(hpcd); + + /* disable all interrupts and force USB reset */ + hpcd->Instance->CNTR = USB_CNTR_FRES; + + /* clear interrupt status register */ + hpcd->Instance->ISTR = 0; + + /* switch-off device */ + hpcd->Instance->CNTR = (USB_CNTR_FRES | USB_CNTR_PDWN); + + __HAL_UNLOCK(hpcd); + return HAL_OK; +} +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup PCD_Private_Functions PCD Private Functions + * @{ + */ +/** + * @brief This function handles PCD Endpoint interrupt request. + * @param hpcd: PCD handle + * @retval HAL status + */ +static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) +{ + PCD_EPTypeDef *ep; + uint16_t count=0; + uint8_t EPindex; + __IO uint16_t wIstr; + __IO uint16_t wEPVal = 0; + + /* stay in loop while pending interrupts */ + while (((wIstr = hpcd->Instance->ISTR) & USB_ISTR_CTR) != 0) + { + /* extract highest priority endpoint number */ + EPindex = (uint8_t)(wIstr & USB_ISTR_EP_ID); + + if (EPindex == 0) + { + /* Decode and service control endpoint interrupt */ + + /* DIR bit = origin of the interrupt */ + if ((wIstr & USB_ISTR_DIR) == 0) + { + /* DIR = 0 */ + + /* DIR = 0 => IN int */ + /* DIR = 0 implies that (EP_CTR_TX = 1) always */ + PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0); + ep = &hpcd->IN_ep[0]; + + ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); + ep->xfer_buff += ep->xfer_count; + + /* TX COMPLETE */ + HAL_PCD_DataInStageCallback(hpcd, 0); + + + if((hpcd->USB_Address > 0)&& ( ep->xfer_len == 0)) + { + hpcd->Instance->DADDR = (hpcd->USB_Address | USB_DADDR_EF); + hpcd->USB_Address = 0; + } + + } + else + { + /* DIR = 1 */ + + /* DIR = 1 & CTR_RX => SETUP or OUT int */ + /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */ + ep = &hpcd->OUT_ep[0]; + wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0); + + if ((wEPVal & USB_EP_SETUP) != 0) + { + /* Get SETUP Packet*/ + ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); + PCD_ReadPMA(hpcd->Instance, (uint8_t*)hpcd->Setup ,ep->pmaadress , ep->xfer_count); + /* SETUP bit kept frozen while CTR_RX = 1*/ + PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); + + /* Process SETUP Packet*/ + HAL_PCD_SetupStageCallback(hpcd); + } + + else if ((wEPVal & USB_EP_CTR_RX) != 0) + { + PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); + /* Get Control Data OUT Packet*/ + ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); + + if (ep->xfer_count != 0) + { + PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count); + ep->xfer_buff+=ep->xfer_count; + } + + /* Process Control Data OUT Packet*/ + HAL_PCD_DataOutStageCallback(hpcd, 0); + + PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); + PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); + } + } + } + else + { + + /* Decode and service non control endpoints interrupt */ + + /* process related endpoint register */ + wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, EPindex); + if ((wEPVal & USB_EP_CTR_RX) != 0) + { + /* clear int flag */ + PCD_CLEAR_RX_EP_CTR(hpcd->Instance, EPindex); + ep = &hpcd->OUT_ep[EPindex]; + + /* OUT double Buffering*/ + if (ep->doublebuffer == 0) + { + count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); + if (count != 0) + { + PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count); + } + } + else + { + if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) + { + /*read from endpoint BUF0Addr buffer*/ + count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); + if (count != 0) + { + PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count); + } + } + else + { + /*read from endpoint BUF1Addr buffer*/ + count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); + if (count != 0) + { + PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count); + } + } + PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT); + } + /*multi-packet on the NON control OUT endpoint*/ + ep->xfer_count+=count; + ep->xfer_buff+=count; + + if ((ep->xfer_len == 0) || (count < ep->maxpacket)) + { + /* RX COMPLETE */ + HAL_PCD_DataOutStageCallback(hpcd, ep->num); + } + else + { + HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); + } + + } /* if((wEPVal & EP_CTR_RX) */ + + if ((wEPVal & USB_EP_CTR_TX) != 0) + { + ep = &hpcd->IN_ep[EPindex]; + + /* clear int flag */ + PCD_CLEAR_TX_EP_CTR(hpcd->Instance, EPindex); + + /* IN double Buffering*/ + if (ep->doublebuffer == 0) + { + ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); + if (ep->xfer_count != 0) + { + PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count); + } + } + else + { + if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_TX) + { + /*read from endpoint BUF0Addr buffer*/ + ep->xfer_count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); + if (ep->xfer_count != 0) + { + PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, ep->xfer_count); + } + } + else + { + /*read from endpoint BUF1Addr buffer*/ + ep->xfer_count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); + if (ep->xfer_count != 0) + { + PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, ep->xfer_count); + } + } + PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN); + } + /*multi-packet on the NON control IN endpoint*/ + ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); + ep->xfer_buff+=ep->xfer_count; + + /* Zero Length Packet? */ + if (ep->xfer_len == 0) + { + /* TX COMPLETE */ + HAL_PCD_DataInStageCallback(hpcd, ep->num); + } + else + { + HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); + } + } + } + } + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup PCD_Exported_Functions + * @{ + */ + +/** @defgroup PCD_Exported_Functions_Group2 IO operation functions + * @{ + */ + +/** + * @brief This function handles PCD interrupt request. + * @param hpcd: PCD handle + * @retval HAL status + */ +void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) +{ + uint32_t wInterrupt_Mask = 0; + + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_CTR)) + { + /* servicing of the endpoint correct transfer interrupt */ + /* clear of the CTR flag into the sub */ + PCD_EP_ISR_Handler(hpcd); + } + + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_RESET)) + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET); + HAL_PCD_ResetCallback(hpcd); + HAL_PCD_SetAddress(hpcd, 0); + } + + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_PMAOVR)) + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR); + } + + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ERR)) + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR); + } + + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP)) + { + + hpcd->Instance->CNTR &= ~(USB_CNTR_LPMODE); + + /*set wInterrupt_Mask global variable*/ + wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \ + | USB_CNTR_ESOFM | USB_CNTR_RESETM; + + /*Set interrupt mask*/ + hpcd->Instance->CNTR = wInterrupt_Mask; + + HAL_PCD_ResumeCallback(hpcd); + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP); + } + + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SUSP)) + { + /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */ + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP); + + /* Force low-power mode in the macrocell */ + hpcd->Instance->CNTR |= USB_CNTR_FSUSP; + hpcd->Instance->CNTR |= USB_CNTR_LPMODE; + + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP) == 0) + { + HAL_PCD_SuspendCallback(hpcd); + } + } + + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SOF)) + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF); + HAL_PCD_SOFCallback(hpcd); + } + + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ESOF)) + { + /* clear ESOF flag in ISTR */ + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF); + } +} + +/** + * @brief Data out stage callbacks + * @param hpcd: PCD handle + * @param epnum: endpoint number + * @retval None + */ + __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_DataOutStageCallback could be implemented in the user file + */ +} + +/** + * @brief Data IN stage callbacks + * @param hpcd: PCD handle + * @param epnum: endpoint number + * @retval None + */ + __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_DataInStageCallback could be implemented in the user file + */ +} +/** + * @brief Setup stage callback + * @param hpcd: ppp handle + * @retval None + */ + __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_SetupStageCallback could be implemented in the user file + */ +} + +/** + * @brief USB Start Of Frame callbacks + * @param hpcd: PCD handle + * @retval None + */ + __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_SOFCallback could be implemented in the user file + */ +} + +/** + * @brief USB Reset callbacks + * @param hpcd: PCD handle + * @retval None + */ + __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_ResetCallback could be implemented in the user file + */ +} + +/** + * @brief Suspend event callbacks + * @param hpcd: PCD handle + * @retval None + */ + __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_SuspendCallback could be implemented in the user file + */ +} + +/** + * @brief Resume event callbacks + * @param hpcd: PCD handle + * @retval None + */ + __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_ResumeCallback could be implemented in the user file + */ +} + +/** + * @brief Incomplete ISO OUT callbacks + * @param hpcd: PCD handle + * @param epnum: endpoint number + * @retval None + */ + __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file + */ +} + +/** + * @brief Incomplete ISO IN callbacks + * @param hpcd: PCD handle + * @param epnum: endpoint number + * @retval None + */ + __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file + */ +} + +/** + * @brief Connection event callbacks + * @param hpcd: PCD handle + * @retval None + */ + __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_ConnectCallback could be implemented in the user file + */ +} + +/** + * @brief Disconnection event callbacks + * @param hpcd: ppp handle + * @retval None + */ + __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_DisconnectCallback could be implemented in the user file + */ +} +/** + * @} + */ + +/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions + * @brief management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the PCD data + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Send an amount of data in blocking mode + * @param hpcd: PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) +{ + __HAL_LOCK(hpcd); + + /* Enabling DP Pull-Down bit to Connect internal pull-up on USB DP line */ + hpcd->Instance->BCDR |= USB_BCDR_DPPU; + + __HAL_UNLOCK(hpcd); + return HAL_OK; +} + +/** + * @brief Send an amount of data in blocking mode + * @param hpcd: PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) +{ + __HAL_LOCK(hpcd); + + /* Disable DP Pull-Down bit*/ + hpcd->Instance->BCDR &= ~(USB_BCDR_DPPU); + + __HAL_UNLOCK(hpcd); + return HAL_OK; +} + +/** + * @brief Set the USB Device address + * @param hpcd: PCD handle + * @param address: new device address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) +{ + __HAL_LOCK(hpcd); + + if(address == 0) + { + /* set device address and enable function */ + hpcd->Instance->DADDR = USB_DADDR_EF; + } + else /* USB Address will be applied later */ + { + hpcd->USB_Address = address; + } + + __HAL_UNLOCK(hpcd); + return HAL_OK; +} +/** + * @brief Open and configure an endpoint + * @param hpcd: PCD handle + * @param ep_addr: endpoint address + * @param ep_mps: endpoint max packert size + * @param ep_type: endpoint type + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) +{ + HAL_StatusTypeDef ret = HAL_OK; + PCD_EPTypeDef *ep; + + if ((ep_addr & 0x80) == 0x80) + { + ep = &hpcd->IN_ep[ep_addr & 0x7F]; + } + else + { + ep = &hpcd->OUT_ep[ep_addr & 0x7F]; + } + ep->num = ep_addr & 0x7F; + + ep->is_in = (0x80 & ep_addr) != 0; + ep->maxpacket = ep_mps; + ep->type = ep_type; + + __HAL_LOCK(hpcd); + +/* initialize Endpoint */ + switch (ep->type) + { + case PCD_EP_TYPE_CTRL: + PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_CONTROL); + break; + case PCD_EP_TYPE_BULK: + PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_BULK); + break; + case PCD_EP_TYPE_INTR: + PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_INTERRUPT); + break; + case PCD_EP_TYPE_ISOC: + PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_ISOCHRONOUS); + break; + } + + PCD_SET_EP_ADDRESS(hpcd->Instance, ep->num, ep->num); + + if (ep->doublebuffer == 0) + { + if (ep->is_in) + { + /*Set the endpoint Transmit buffer address */ + PCD_SET_EP_TX_ADDRESS(hpcd->Instance, ep->num, ep->pmaadress); + PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num); + /* Configure NAK status for the Endpoint*/ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK); + } + else + { + /*Set the endpoint Receive buffer address */ + PCD_SET_EP_RX_ADDRESS(hpcd->Instance, ep->num, ep->pmaadress); + /*Set the endpoint Receive buffer counter*/ + PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, ep->maxpacket); + PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num); + /* Configure VALID status for the Endpoint*/ + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID); + } + } + /*Double Buffer*/ + else + { + /*Set the endpoint as double buffered*/ + PCD_SET_EP_DBUF(hpcd->Instance, ep->num); + /*Set buffer address for double buffered mode*/ + PCD_SET_EP_DBUF_ADDR(hpcd->Instance, ep->num,ep->pmaaddr0, ep->pmaaddr1); + + if (ep->is_in==0) + { + /* Clear the data toggle bits for the endpoint IN/OUT*/ + PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num); + PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num); + + /* Reset value of the data toggle bits for the endpoint out*/ + PCD_TX_DTOG(hpcd->Instance, ep->num); + + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID); + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS); + } + else + { + /* Clear the data toggle bits for the endpoint IN/OUT*/ + PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num); + PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num); + PCD_RX_DTOG(hpcd->Instance, ep->num); + /* Configure DISABLE status for the Endpoint*/ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS); + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS); + } + } + + __HAL_UNLOCK(hpcd); + return ret; +} + + +/** + * @brief Deactivate an endpoint + * @param hpcd: PCD handle + * @param ep_addr: endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + PCD_EPTypeDef *ep; + + if ((ep_addr & 0x80) == 0x80) + { + ep = &hpcd->IN_ep[ep_addr & 0x7F]; + } + else + { + ep = &hpcd->OUT_ep[ep_addr & 0x7F]; + } + ep->num = ep_addr & 0x7F; + + ep->is_in = (0x80 & ep_addr) != 0; + + __HAL_LOCK(hpcd); + + if (ep->doublebuffer == 0) + { + if (ep->is_in) + { + PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num); + /* Configure DISABLE status for the Endpoint*/ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS); + } + else + { + PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num); + /* Configure DISABLE status for the Endpoint*/ + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS); + } + } + /*Double Buffer*/ + else + { + if (ep->is_in==0) + { + /* Clear the data toggle bits for the endpoint IN/OUT*/ + PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num); + PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num); + + /* Reset value of the data toggle bits for the endpoint out*/ + PCD_TX_DTOG(hpcd->Instance, ep->num); + + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS); + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS); + } + else + { + /* Clear the data toggle bits for the endpoint IN/OUT*/ + PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num); + PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num); + PCD_RX_DTOG(hpcd->Instance, ep->num); + /* Configure DISABLE status for the Endpoint*/ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS); + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS); + } + } + + __HAL_UNLOCK(hpcd); + return HAL_OK; +} + + +/** + * @brief Receive an amount of data + * @param hpcd: PCD handle + * @param ep_addr: endpoint address + * @param pBuf: pointer to the reception buffer + * @param len: amount of data to be received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) +{ + + PCD_EPTypeDef *ep; + + ep = &hpcd->OUT_ep[ep_addr & 0x7F]; + + /*setup and start the Xfer */ + ep->xfer_buff = pBuf; + ep->xfer_len = len; + ep->xfer_count = 0; + ep->is_in = 0; + ep->num = ep_addr & 0x7F; + + __HAL_LOCK(hpcd); + + /* Multi packet transfer*/ + if (ep->xfer_len > ep->maxpacket) + { + len=ep->maxpacket; + ep->xfer_len-=len; + } + else + { + len=ep->xfer_len; + ep->xfer_len =0; + } + + /* configure and validate Rx endpoint */ + if (ep->doublebuffer == 0) + { + /*Set RX buffer count*/ + PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, len); + } + else + { + /*Set the Double buffer counter*/ + PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len); + } + + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID); + + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +/** + * @brief Get Received Data Size + * @param hpcd: PCD handle + * @param ep_addr: endpoint address + * @retval Data Size + */ +uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + return hpcd->OUT_ep[ep_addr & 0x7F].xfer_count; +} +/** + * @brief Send an amount of data + * @param hpcd: PCD handle + * @param ep_addr: endpoint address + * @param pBuf: pointer to the transmission buffer + * @param len: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) +{ + PCD_EPTypeDef *ep; + uint16_t pmabuffer = 0; + + ep = &hpcd->IN_ep[ep_addr & 0x7F]; + + /*setup and start the Xfer */ + ep->xfer_buff = pBuf; + ep->xfer_len = len; + ep->xfer_count = 0; + ep->is_in = 1; + ep->num = ep_addr & 0x7F; + + __HAL_LOCK(hpcd); + + /*Multi packet transfer*/ + if (ep->xfer_len > ep->maxpacket) + { + len=ep->maxpacket; + ep->xfer_len-=len; + } + else + { + len=ep->xfer_len; + ep->xfer_len =0; + } + + /* configure and validate Tx endpoint */ + if (ep->doublebuffer == 0) + { + PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, len); + PCD_SET_EP_TX_CNT(hpcd->Instance, ep->num, len); + } + else + { + /*Set the Double buffer counter*/ + PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len); + + /*Write the data to the USB endpoint*/ + if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX) + { + pmabuffer = ep->pmaaddr1; + } + else + { + pmabuffer = ep->pmaaddr0; + } + PCD_WritePMA(hpcd->Instance, ep->xfer_buff, pmabuffer, len); + PCD_FreeUserBuffer(hpcd->Instance, ep->num, ep->is_in); + } + + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID); + + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +/** + * @brief Set a STALL condition over an endpoint + * @param hpcd: PCD handle + * @param ep_addr: endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + PCD_EPTypeDef *ep; + + __HAL_LOCK(hpcd); + + if ((0x80 & ep_addr) == 0x80) + { + ep = &hpcd->IN_ep[ep_addr & 0x7F]; + } + else + { + ep = &hpcd->OUT_ep[ep_addr]; + } + + ep->is_stall = 1; + ep->num = ep_addr & 0x7F; + ep->is_in = ((ep_addr & 0x80) == 0x80); + + if (ep->num == 0) + { + /* This macro sets STALL status for RX & TX*/ + PCD_SET_EP_TXRX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_STALL, USB_EP_TX_STALL); + } + else + { + if (ep->is_in) + { + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num , USB_EP_TX_STALL); + } + else + { + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num , USB_EP_RX_STALL); + } + } + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +/** + * @brief Clear a STALL condition over in an endpoint + * @param hpcd: PCD handle + * @param ep_addr: endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + PCD_EPTypeDef *ep; + + if ((0x80 & ep_addr) == 0x80) + { + ep = &hpcd->IN_ep[ep_addr & 0x7F]; + } + else + { + ep = &hpcd->OUT_ep[ep_addr]; + } + + ep->is_stall = 0; + ep->num = ep_addr & 0x7F; + ep->is_in = ((ep_addr & 0x80) == 0x80); + + __HAL_LOCK(hpcd); + + if (ep->is_in) + { + PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num); + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID); + } + else + { + PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num); + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID); + } + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +/** + * @brief Flush an endpoint + * @param hpcd: PCD handle + * @param ep_addr: endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + return HAL_OK; +} + +/** + * @brief HAL_PCD_ActiveRemoteWakeup : active remote wakeup signalling + * @param hpcd: PCD handle + * @retval status + */ +HAL_StatusTypeDef HAL_PCD_ActiveRemoteWakeup(PCD_HandleTypeDef *hpcd) +{ + hpcd->Instance->CNTR |= USB_CNTR_RESUME; + return HAL_OK; +} + +/** + * @brief HAL_PCD_DeActiveRemoteWakeup : de-active remote wakeup signalling + * @param hpcd: PCD handle + * @retval status + */ +HAL_StatusTypeDef HAL_PCD_DeActiveRemoteWakeup(PCD_HandleTypeDef *hpcd) +{ + hpcd->Instance->CNTR &= ~(USB_CNTR_RESUME); + return HAL_OK; +} +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup PCD_Private_Functions + * @{ + */ +/** + * @brief Copy a buffer from user memory area to packet memory area (PMA) + * @param USBx: USB peripheral instance register address. + * @param pbUsrBuf: pointer to user memory area. + * @param wPMABufAddr: address into PMA. + * @param wNBytes: no. of bytes to be copied. + * @retval None + */ +void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) +{ + uint32_t n = (wNBytes + 1) >> 1; + uint32_t i; + uint16_t temp1, temp2; + uint16_t *pdwVal; + pdwVal = (uint16_t *)(wPMABufAddr + (uint32_t)USBx + 0x400); + + for (i = n; i != 0; i--) + { + temp1 = (uint16_t) * pbUsrBuf; + pbUsrBuf++; + temp2 = temp1 | (uint16_t) * pbUsrBuf << 8; + *pdwVal++ = temp2; + pbUsrBuf++; + } +} + +/** + * @brief Copy a buffer from user memory area to packet memory area (PMA) + * @param USBx: USB peripheral instance register address. + * @param pbUsrBuf = pointer to user memory area. + * @param wPMABufAddr: address into PMA. + * @param wNBytes: no. of bytes to be copied. + * @retval None + */ +void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) +{ + uint32_t n = (wNBytes + 1) >> 1; + uint32_t i; + uint16_t *pdwVal; + pdwVal = (uint16_t *)(wPMABufAddr + (uint32_t)USBx + 0x400); + for (i = n; i != 0; i--) + { + *(uint16_t*)pbUsrBuf++ = *pdwVal++; + pbUsrBuf++; + } +} +/** + * @} + */ + +/** @addtogroup PCD_Exported_Functions + * @{ + */ + +/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permit to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the PCD state + * @param hpcd : PCD handle + * @retval HAL state + */ +PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) +{ + return hpcd->State; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* STM32F042x6 || STM32F072xB || STM32F078xx */ + +#endif /* HAL_PCD_MODULE_ENABLED */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd_ex.c b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd_ex.c new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd_ex.c @@ -0,0 +1,153 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_pcd_ex.c + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Extended PCD HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the USB Peripheral Controller: + * + Configuration of the PMA for EP + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +#ifdef HAL_PCD_MODULE_ENABLED + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup PCDEx PCDEx Extended HAL module driver + * @brief PCDEx PCDEx Extended HAL module driver + * @{ + */ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions + * @{ + */ + +/** @defgroup PCDEx_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Peripheral extended features methods ##### + =============================================================================== +@endverbatim + * @{ + */ + +/** + * @brief Configure PMA for EP + * @param hpcd: PCD handle + * @param ep_addr: endpoint address + * @param ep_kind: endpoint Kind + * @arg USB_SNG_BUF: Single Buffer used + * @arg USB_DBL_BUF: Double Buffer used + * @param pmaadress: EP address in The PMA: In case of single buffer endpoint + * this parameter is 16-bit value providing the address + * in PMA allocated to endpoint. + * In case of double buffer endpoint this parameter + * is a 32-bit value providing the endpoint buffer 0 address + * in the LSB part of 32-bit value and endpoint buffer 1 address + * in the MSB part of 32-bit value. + * @retval : status + */ + +HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, + uint16_t ep_addr, + uint16_t ep_kind, + uint32_t pmaadress) + +{ + PCD_EPTypeDef *ep; + + /* initialize ep structure*/ + if ((0x80 & ep_addr) == 0x80) + { + ep = &hpcd->IN_ep[ep_addr & 0x7F]; + } + else + { + ep = &hpcd->OUT_ep[ep_addr]; + } + + /* Here we check if the endpoint is single or double Buffer*/ + if (ep_kind == PCD_SNG_BUF) + { + /*Single Buffer*/ + ep->doublebuffer = 0; + /*Configure te PMA*/ + ep->pmaadress = (uint16_t)pmaadress; + } + else /*USB_DBL_BUF*/ + { + /*Double Buffer Endpoint*/ + ep->doublebuffer = 1; + /*Configure the PMA*/ + ep->pmaaddr0 = pmaadress & 0xFFFF; + ep->pmaaddr1 = (pmaadress & 0xFFFF0000) >> 16; + } + + return HAL_OK; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32F042x6 || STM32F072xB || STM32F078xx */ + +#endif /* HAL_PCD_MODULE_ENABLED */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_ppp.c b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_ppp.c new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_ppp.c @@ -0,0 +1,501 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_ppp.c + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief PPP HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the PPP peripheral: + * + Initialization/de-initialization functions + * + I/O operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + @verbatim +================================================================================ + ##### Product specific features integration ##### +================================================================================ + + [..] This section can contain: + (#) Description of the product specific implementation; all features + that is specific to this IP: separate clock for RTC/LCD/IWDG/ADC, + power domain (backup domain for the RTC)... + (#) IP main features, only when needed and not mandatory for all IPs, + ex. for xWDG, GPIO, COMP... + + [..] You can add as much sections as needed. + + [..] You can add as much sections as needed. + + ##### How to use this driver ##### +================================================================================ + [..] + (#) Add here ALL NEEDED STEPS (i.e. list of functions and parameters) + TO INITIALIZE AND USE THE PERIPHERAL. Following the listed steps, + user should be able to make the peripheral working without any + additional information from other resources (ex. product Reference + Manual, HAL User Manual...). + + Basically, it should be the same as we provide in the examples. + + (#) Exception can be made for system IPs (there is no standard order + of API usage) for which the description of API usage will be made + in each function group. These IPs are: PWR, RCC and FLASH + In this case, this section should contain the following note: + "Refer to the description within the different function groups below" + + (+) + + (+) + + (+) + + (+) + + (+) + + (+) + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup PPP PPP HAL module driver + * @brief PPP HAL module driver + * @{ + */ + +#ifdef HAL_PPP_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup PPP_Exported_Functions PPP Exported Functions + * @{ + */ + +/** @defgroup PPP_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the PPP according to the specified + * parameters in the PPP_InitTypeDef and create the associated handle. + * @param hppp: PPP handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PPP_Init(PPP_HandleTypeDef *hppp) +{ + + /* Check the parameters */ + assert_param(IS_PPP_CONFIGx(hppp->Config.Config1)); + + /* Check the PPP handle allocation */ + if(hppp == NULL) + { + return HAL_ERROR; + } + + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_PPP_MspInit(hppp); + + /* Set PPP parameters */ + + /* Enable the Peripharal */ + + /* Initialize the PPP state*/ + hppp->State = HAL_PPP_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the PPP peripheral + * @param hppp: PPP handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PPP_DeInit(PPP_HandleTypeDef *hppp) +{ + /* Check the PPP peripheral state */ + if(hppp->State == HAL_PPP_STATE_BUSY) + { + return HAL_ERROR; + } + + hppp->State = HAL_PPP_STATE_BUSY; + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_PPP_MspDeInit(hppp); + + hppp->State = HAL_PPP_STATE_DISABLED; + return HAL_OK; +} + +/** + * @brief Initializes the PPP MSP. + * @param hppp: PPP handle + * @retval None + */ +__weak void HAL_PPP_MspInit(PPP_HandleTypeDef *hppp) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PPP_MspInit could be implenetd in the user file + */ +} + +/** + * @brief DeInitializes PPP MSP. + * @param hppp: PPP handle + * @retval None + */ +__weak void HAL_PPP_MspDeInit(PPP_HandleTypeDef *hppp) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PPP_MspDeInit could be implenetd in the user file + */ +} + +/** + * @} + */ + +/** @defgroup PPP_Exported_Functions_Group2 I/O operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the PPP data + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Send an amount of data in blocking mode + * @param hppp: PPP handle + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PPP_Transmit(PPP_HandleTypeDef *hppp, uint8_t *pData, uint16_t Size) +{ + /* Process Locked */ + __HAL_LOCK(hppp); + + hppp->State = HAL_PPP_STATE_BUSY; + /* PPP processing... */ + hppp->State = HAL_PPP_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hppp); + + return HAL_OK; +} + +/** + * @brief Receive an amount of data in blocking mode + * @param hppp: PPP handle + * @param pData: pointer to data buffer + * @param Size: amount of data to be received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PPP_Receive(PPP_HandleTypeDef *hppp, uint8_t *pData, uint16_t Size) +{ + /* Process Locked */ + __HAL_LOCK(hppp); + + hppp->State = HAL_PPP_STATE_BUSY; + /* PPP processing... */ + hppp->State = HAL_PPP_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hppp); + + return HAL_OK; +} + +/** + * @brief Send an amount of data in non blocking mode + * @param hppp: PPP handle + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PPP_Transmit_IT(PPP_HandleTypeDef *hppp, uint8_t *pData, uint16_t Size) +{ + /* Process Locked */ + __HAL_LOCK(hppp); + + hppp->State = HAL_PPP_STATE_BUSY; + /* PPP processing... */ + hppp->State = HAL_PPP_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hppp); + + return HAL_OK; +} + +/** + * @brief Receive an amount of data in non blocking mode + * @param hppp: PPP handle + * @param pData: pointer to data buffer + * @param Size: amount of data to be received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PPP_Receive_IT(PPP_HandleTypeDef *hppp, uint8_t *pData, uint16_t Size) +{ + /* Process Locked */ + __HAL_LOCK(hppp); + + hppp->State = HAL_PPP_STATE_BUSY; + /* PPP processing... */ + hppp->State = HAL_PPP_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hppp); + + return HAL_OK; +} + +/** + * @brief This function handles PPP interrupt request. + * @param hppp: PPP handle + * @retval HAL status + */ +void HAL_PPP_IRQHandler(PPP_HandleTypeDef *hppp) +{ + /* PPP in mode Tramitter ---------------------------------------------------*/ + if (__HAL_PPP_GET_IT(hppp, PPP_IT_TC) != RESET) + { + __HAL_PPP_CLEAR_IT(hppp, PPP_IT_TC); + HAL_PPP_Transmit_IT(hppp, NULL, 0); + } + + /* PPP in mode Receiver ----------------------------------------------------*/ + if (__HAL_PPP_GET_IT(hppp, PPP_IT_RXNE) != RESET) + { + __HAL_PPP_CLEAR_IT(hppp, PPP_IT_RXNE); + HAL_PPP_Receive_IT(hppp, NULL, 0); + } +} + +/** + * @brief Tx Transfer completed callbacks + * @param hppp: ppp handle + * @retval None + */ + __weak void HAL_PPP_TxCpltCallback(PPP_HandleTypeDef *hppp) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PPP_TxCpltCallback could be implenetd in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks + * @param hppp: PPP handle + * @retval None + */ +__weak void HAL_PPP_RxCpltCallback(PPP_HandleTypeDef *hppp) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PPP_TxCpltCallback could be implenetd in the user file + */ +} + +/** + * @brief Send an amount of data in non blocking mode + * @param hppp: ppp handle + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PPP_Transmit_DMA(PPP_HandleTypeDef *hppp, uint8_t *pData, uint16_t Size) +{ + /* Check the PPP peripheral state */ + if(hppp->State == HAL_PPP_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hppp); + + hppp->State = HAL_PPP_STATE_BUSY; + /* PPP processing... */ + hppp->State = HAL_PPP_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hppp); + + return HAL_OK; +} + +/** + * @brief Receive an amount of data in non blocking mode + * @param hppp: PPP handle + * @param pData: pointer to data buffer + * @param Size: amount of data to be received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PPP_Receive_DMA(PPP_HandleTypeDef *hppp, uint8_t *pData, uint16_t Size) +{ + /* Check the PPP peripheral state */ + if(hppp->State == HAL_PPP_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hppp); + + hppp->State = HAL_PPP_STATE_BUSY; + /* PPP processing... */ + hppp->State = HAL_PPP_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hppp); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup PPP_Exported_Functions_Group3 Peripheral Control functions + * @brief management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the PPP data + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Configures PPP features and fonctionality. + * @param hppp: PPP handle + * @param control: Specifies which PPP_InitTypeDef structure’s field will be affected + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PPP_Ctl(PPP_HandleTypeDef *hppp, PPP_ControlTypeDef control, uint16_t *args) +{ + if(hppp->State == HAL_PPP_STATE_BUSY) + { + return HAL_BUSY; + } + + hppp->State = HAL_PPP_STATE_BUSY; + + /* Update the PPP features and fonctionality */ + /* ... */ + + hppp->State = HAL_PPP_STATE_READY; + + return HAL_OK; +} +/** + * @} + */ + +/** @defgroup PPP_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permit to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the PPP state + * @param hppp : PPP handle + * @retval HAL state + */ +HAL_PPP_StateTypeDef HAL_PPP_GetState(PPP_HandleTypeDef *hppp) +{ + return hppp->State; +} +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PPP_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c @@ -0,0 +1,430 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_pwr.c + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * + Initialization/de-initialization function + * + Peripheral Control function + * + @verbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup PWR PWR HAL module Driver + * @brief PWR HAL module driver + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + After reset, the backup domain (RTC registers, RTC backup data + registers) is protected against possible unwanted + write accesses. + To enable access to the RTC Domain and RTC registers, proceed as follows: + (+) Enable the Power Controller (PWR) APB1 interface clock using the + __PWR_CLK_ENABLE() macro. + (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the PWR peripheral registers to their default reset values. + * @retval None + */ +void HAL_PWR_DeInit(void) +{ + __PWR_FORCE_RESET(); + __PWR_RELEASE_RESET(); +} + +/** + * @brief Enables access to the backup domain (RTC registers, RTC + * backup data registers). + * @note If the HSE divided by 32 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @retval None + */ +void HAL_PWR_EnableBkUpAccess(void) +{ + PWR->CR |= (uint32_t)PWR_CR_DBP; +} + +/** + * @brief Disables access to the backup domain (RTC registers, RTC + * backup data registers). + * @note If the HSE divided by 32 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @retval None + */ +void HAL_PWR_DisableBkUpAccess(void) +{ + PWR->CR &= ~((uint32_t)PWR_CR_DBP); +} + +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions + * @brief Low Power modes configuration functions + * +@verbatim + + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + + *** WakeUp pin configuration *** + ================================ + [..] + (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is + forced in input pull down configuration and is active on rising edges. + (+) There are two WakeUp pins, and up to eight Wakeup pins on STM32F07x & STM32F09x devices. + (++)WakeUp Pin 1 on PA.00. + (++)WakeUp Pin 2 on PC.13. + (++)WakeUp Pin 3 on PE.06.(STM32F07x/STM32F09x) + (++)WakeUp Pin 4 on PA.02.(STM32F07x/STM32F09x) + (++)WakeUp Pin 5 on PC.05.(STM32F07x/STM32F09x) + (++)WakeUp Pin 6 on PB.05.(STM32F07x/STM32F09x) + (++)WakeUp Pin 7 on PB.15.(STM32F07x/STM32F09x) + (++)WakeUp Pin 8 on PF.02.(STM32F07x/STM32F09x) + + *** Low Power modes configuration *** + ===================================== + [..] + The devices feature 3 low-power modes: + (+) Sleep mode: Cortex-M0 core stopped, peripherals kept running. + (+) Stop mode: all clocks are stopped, regulator running, regulator + in low power mode + (+) Standby mode: 1.2V domain powered off (mode not available on STM32F0x8 devices). + + *** Sleep mode *** + ================== + [..] + (+) Entry: + The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx) + functions with + (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + + (+) Exit: + (++) Any peripheral interrupt acknowledged by the nested vectored interrupt + controller (NVIC) can wake up the device from Sleep mode. + + *** Stop mode *** + ================= + [..] + In Stop mode, all clocks in the 1.8V domain are stopped, the PLL, the HSI, + and the HSE RC oscillators are disabled. Internal SRAM and register contents + are preserved. + The voltage regulator can be configured either in normal or low-power mode. + To minimize the consumption. + + (+) Entry: + The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPENTRY_WFI ) + function with: + (++) Main regulator ON. + (++) Low Power regulator ON. + (++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction + (++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction + (+) Exit: + (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode. + (++) Some specific communication peripherals (CEC, USART, I2C) interrupts, + when programmed in wakeup mode (the peripheral must be + programmed in wakeup mode and the corresponding interrupt vector + must be enabled in the NVIC) + + *** Standby mode *** + ==================== + [..] + The Standby mode allows to achieve the lowest power consumption. It is based + on the Cortex-M0 deep sleep mode, with the voltage regulator disabled. + The 1.8V domain is consequently powered off. The PLL, the HSI oscillator and + the HSE oscillator are also switched off. SRAM and register contents are lost + except for the RTC registers, RTC backup registers and Standby circuitry. + The voltage regulator is OFF. + + (+) Entry: + (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. + (+) Exit: + (++) WKUP pin rising edge, RTC alarm (Alarm A), RTC wakeup, + tamper event, time-stamp event, external reset in NRST pin, IWDG reset. + + *** Auto-wakeup (AWU) from low-power mode *** + ============================================= + [..] + The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC + Wakeup event, a tamper event, a time-stamp event, or a comparator event, + without depending on an external interrupt (Auto-wakeup mode). + + (+) RTC auto-wakeup (AWU) from the Stop and Standby modes + + (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to + configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. + + (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it + is necessary to configure the RTC to detect the tamper or time stamp event using the + HAL_RTC_SetTimeStamp_IT() or HAL_RTC_SetTamper_IT() functions. + + (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to + configure the RTC to generate the RTC WakeUp event using the HAL_RTC_SetWakeUpTimer_IT() function. + + (+) Comparator auto-wakeup (AWU) from the Stop mode + + (++) To wake up from the Stop mode with a comparator wakeup event, it is necessary to: + (+++) Configure the EXTI Line associated with the comparator (example EXTI Line 22 for comparator 2) + to be sensitive to to the selected edges (falling, rising or falling + and rising) (Interrupt or Event modes) using the EXTI_Init() function. + (+++) Configure the comparator to generate the event. +@endverbatim + * @{ + */ + +/** + * @brief Enables the WakeUp PINx functionality. + * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable. + * This parameter can be value of : + * @ref PWREx_WakeUp_Pins + * @retval None + */ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) +{ + /* Check the parameters */ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + PWR->CSR |= (PWR_CSR_EWUP1 << (uint8_t)WakeUpPinx); +} + +/** + * @brief Disables the WakeUp PINx functionality. + * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable. + * This parameter can be values of : + * @ref PWREx_WakeUp_Pins + * @retval None + */ +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) +{ + /* Check the parameters */ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + PWR->CSR &= ~(PWR_CSR_EWUP1 << (uint8_t)WakeUpPinx); +} + +/** + * @brief Enters Sleep mode. + * @note In Sleep mode, all I/O pins keep the same state as in Run mode. + * @param Regulator: Specifies the regulator state in SLEEP mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON + * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON + * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction. + * When WFI entry is used, tick interrupt have to be disabled if not desired as + * the interrupt wake up source. + * This parameter can be one of the following values: + * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + * @retval None + */ +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(Regulator)); + assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); + + /* Select the regulator state in SLEEP mode ---------------------------------*/ + tmpreg = PWR->CR; + + /* Clear PDDS and LPDS bits */ + tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS); + + /* Set LPDS bit according to Regulator value */ + tmpreg |= Regulator; + + /* Store the new value */ + PWR->CR = tmpreg; + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + + /* Select SLEEP mode entry -------------------------------------------------*/ + if(SLEEPEntry == PWR_SLEEPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } +} + +/** + * @brief Enters STOP mode. + * @note In Stop mode, all I/O pins keep the same state as in Run mode. + * @note When exiting Stop mode by issuing an interrupt or a wakeup event, + * the HSI RC oscillator is selected as system clock. + * @note When the voltage regulator operates in low power mode, an additional + * startup delay is incurred when waking up from Stop mode. + * By keeping the internal regulator ON during Stop mode, the consumption + * is higher although the startup time is reduced. + * @param Regulator: Specifies the regulator state in STOP mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_ON: STOP mode with regulator ON + * @arg PWR_LOWPOWERREGULATOR_ON: STOP mode with low power regulator ON + * @param STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPENTRY_WFI:Enter STOP mode with WFI instruction + * @arg PWR_STOPENTRY_WFE: Enter STOP mode with WFE instruction + * @retval None + */ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(Regulator)); + assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + + /* Select the regulator state in STOP mode ---------------------------------*/ + tmpreg = PWR->CR; + + /* Clear PDDS and LPDS bits */ + tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS); + + /* Set LPDS bit according to Regulator value */ + tmpreg |= Regulator; + + /* Store the new value */ + PWR->CR = tmpreg; + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* Select STOP mode entry --------------------------------------------------*/ + if(STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } + + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Enters STANDBY mode. + * @note In Standby mode, all I/O pins are high impedance except for: + * - Reset pad (still available) + * - RTC alternate function pins if configured for tamper, time-stamp, RTC + * Alarm out, or RTC clock calibration out. + * - WKUP pins if enabled. + * STM32F0x8 devices, the Stop mode is available, but it is + * aningless to distinguish between voltage regulator in Low power + * mode and voltage regulator in Run mode because the regulator + * not used and the core is supplied directly from an external source. + * Consequently, the Standby mode is not available on those devices. + * @retval None + */ +void HAL_PWR_EnterSTANDBYMode(void) +{ + /* Select STANDBY mode */ + PWR->CR |= (uint32_t)PWR_CR_PDDS; + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* This option is used to ensure that store operations are completed */ +#if defined ( __CC_ARM) + __force_stores(); +#endif + /* Request Wait For Interrupt */ + __WFI(); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c @@ -0,0 +1,293 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_pwr_ex.c + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Extended PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * + Extended Initialization and de-initialization functions + * + Extended Peripheral Control functions + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup PWREx PWREx Extended HAL module driver + * @brief PWREx HAL module driver + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup PWREx_Private_Constants PWREx Private Constants + * @{ + */ +#define PVD_MODE_IT ((uint32_t)0x00010000) +#define PVD_MODE_EVT ((uint32_t)0x00020000) +#define PVD_RISING_EDGE ((uint32_t)0x00000001) +#define PVD_FALLING_EDGE ((uint32_t)0x00000002) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Functions PWREx Exported Functions + * @{ + */ + +/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended Control Functions + * @brief Extended Peripheral Control functions + * +@verbatim + + =============================================================================== + ##### Peripheral extended control functions ##### + =============================================================================== + + *** PVD configuration *** + ========================= + [..] + (+) The PVD is used to monitor the VDD power supply by comparing it to a + threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). + (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower + than the PVD threshold. This event is internally connected to the EXTI + line16 and can generate an interrupt if enabled. This is done through + HAL_PWR_PVDConfig(), HAL_PWR_EnablePVD() functions. + (+) The PVD is stopped in Standby mode. + -@- PVD is not available on STM32F030x4/x6/x8 + + *** VDDIO2 Monitor Configuration *** + ==================================== + [..] + (+) VDDIO2 monitor is used to monitor the VDDIO2 power supply by comparing it + to VREFInt Voltage + (+) This monitor is internally connected to the EXTI line31 + and can generate an interrupt if enabled. This is done through + HAL_PWR_EnableVddio2Monitor() function. + -@- VDDIO2 is available on STM32F07x/09x/04x + +@endverbatim + * @{ + */ + +#if defined (STM32F031x6) || defined (STM32F051x8) || \ + defined (STM32F071xB) || defined (STM32F091xC) || \ + defined (STM32F042x6) || defined (STM32F072xB) +/** + * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). + * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration + * information for the PVD. + * @note Refer to the electrical characteristics of your device datasheet for + * more details about the voltage threshold corresponding to each + * detection level. + * @retval None + */ +void HAL_PWR_PVDConfig(PWR_PVDTypeDef *sConfigPVD) +{ + /* Check the parameters */ + assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); + assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); + + /* Set PLS[7:5] bits according to PVDLevel value */ + MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); + + /* Clear any previous config. Keep it clear if no event or IT mode is selected */ + __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); + __HAL_PWR_PVD_EXTI_DISABLE_IT(); + __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER(); + + /* Configure interrupt mode */ + if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) + { + __HAL_PWR_PVD_EXTI_ENABLE_IT(); + } + + /* Configure event mode */ + if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) + { + __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); + } + + /* Configure the edge */ + if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) + { + __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER(); + } + + if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) + { + __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER(); + } +} + +/** + * @brief Enables the Power Voltage Detector(PVD). + * @retval None + */ +void HAL_PWR_EnablePVD(void) +{ + PWR->CR |= (uint32_t)PWR_CR_PVDE; +} + +/** + * @brief Disables the Power Voltage Detector(PVD). + * @retval None + */ +void HAL_PWR_DisablePVD(void) +{ + PWR->CR &= ~((uint32_t)PWR_CR_PVDE); +} + +/** + * @brief This function handles the PWR PVD interrupt request. + * @note This API should be called under the PVD_IRQHandler() or PVD_VDDIO2_IRQHandler(). + * @retval None + */ +void HAL_PWR_PVD_IRQHandler(void) +{ + /* Check PWR exti flag */ + if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) + { + /* PWR PVD interrupt user callback */ + HAL_PWR_PVDCallback(); + + /* Clear PWR Exti pending bit */ + __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); + } +} + +/** + * @brief PWR PVD interrupt callback + * @retval None + */ +__weak void HAL_PWR_PVDCallback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PWR_PVDCallback could be implemented in the user file + */ +} + +#endif /* defined (STM32F031x6) || defined (STM32F051x8) || */ + /* defined (STM32F071xB) || defined (STM32F091xC) || */ + /* defined (STM32F042x6) || defined (STM32F072xB) */ + +#if defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) +/** + * @brief Enable VDDIO2 monitor: enable Exti 31 and falling edge detection. + * @param None + * @note If Exti 31 is enable correlty and VDDIO2 voltage goes below Vrefint, + an interrupt is generated Irq line 1. + NVIS has to be enable by user. + * @retval None + */ +void HAL_PWR_EnableVddio2Monitor(void) +{ + __HAL_PWR_VDDIO2_EXTI_ENABLE_IT(); + __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER(); +} + +/** + * @brief Disable the Vddio2 Monitor. + * @retval None + */ +void HAL_PWR_DisableVddio2Monitor(void) +{ + __HAL_PWR_VDDIO2_EXTI_DISABLE_IT(); + __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER(); + +} + +/** + * @brief This function handles the PWR Vddio2 monitor interrupt request. + * @note This API should be called under the VDDIO2_IRQHandler() PVD_VDDIO2_IRQHandler(). + * @retval None + */ +void HAL_PWR_Vddio2Monitor_IRQHandler(void) +{ + /* Check PWR exti flag */ + if(__HAL_PWR_VDDIO2_EXTI_GET_FLAG() != RESET) + { + /* PWR Vddio2 monitor interrupt user callback */ + HAL_PWR_Vddio2MonitorCallback(); + + /* Clear PWR Exti pending bit */ + __HAL_PWR_VDDIO2_EXTI_CLEAR_FLAG(); + } +} + +/** + * @brief PWR Vddio2 Monitor interrupt callback + * @retval None + */ +__weak void HAL_PWR_Vddio2MonitorCallback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PWR_Vddio2MonitorCallback could be implemented in the user file + */ +} + +#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c @@ -0,0 +1,610 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_rcc.c + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Reset and Clock Control (RCC) peripheral: + * + Initialization/de-initialization function + * + Peripheral Control function + * + @verbatim + ============================================================================== + ##### RCC specific features ##### + ============================================================================== + [..] + After reset the device is running from Internal High Speed oscillator + (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is disabled, + and all peripherals are off except internal SRAM, Flash and JTAG. + (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses; + all peripherals mapped on these busses are running at HSI speed. + (+) The clock for all peripherals is switched off, except the SRAM and FLASH. + (+) All GPIOs are in input floating state, except the JTAG pins which + are assigned to be used for debug purpose. + + [..] + Once the device started from reset, the user application has to: + (+) Configure the clock source to be used to drive the System clock + (if the application needs higher frequency/performance) + (+) Configure the System clock frequency and Flash settings + (+) Configure the AHB and APB busses prescalers + (+) Enable the clock for the peripheral(s) to be used + (+) Configure the clock source(s) for peripherals which clocks are not + derived from the System clock (RTC, ADC, I2C, USART, TIM, USB FS, etc..) + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup RCC RCC HAL module driver + * @brief RCC HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup RCC_Private_Define RCC Private Define + * @{ + */ +#define RCC_CFGR_HPRE_BITNUMBER 4 +#define RCC_CFGR_PPRE_BITNUMBER 8 +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup RCC_Private_Macros RCC Private Macros + * @{ + */ +#define __MCO_CLK_ENABLE() __GPIOA_CLK_ENABLE() +#define MCO_GPIO_PORT GPIOA +#define MCO_PIN GPIO_PIN_8 +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup RCC_Private_Variables RCC Private Variables + * @{ + */ +const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_Exported_Functions_Group1 Initialization/de-initialization function + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization function ##### + =============================================================================== + [..] + This section provide functions allowing to configure the internal/external oscillators + (HSE, HSI, HSI14, HSI48, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, + AHB and APB1). + + [..] Internal/external clock and PLL configuration + (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through + the PLL as System clock source. + The HSI clock can be used also to clock the USART and I2C peripherals. + + (#) HSI14 (high-speed internal), 14 MHz factory-trimmed RC used directly to clock + the ADC peripheral. + + (#) LSI (low-speed internal), 40 KHz low consumption RC used as IWDG and/or RTC + clock source. + + (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or + through the PLL as System clock source. Can be used also as RTC clock source. + + (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. + + (#) PLL (clocked by HSI, HSI48 or HSE), featuring different output clocks: + (++) The first output is used to generate the high speed system clock (up to 48 MHz) + (++) The second output is used to generate the clock for the USB FS (48 MHz) + (++) The third output may be used to generate the clock for the TIM, I2C and USART + peripherals (up to 48 MHz) + + (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE() + and if a HSE clock failure occurs(HSE used directly or through PLL as System + clock source), the System clockis automatically switched to HSI and an interrupt + is generated if enabled. The interrupt is linked to the Cortex-M0 NMI + (Non-Maskable Interrupt) exception vector. + + (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSE, LSI, LSE or PLL + clock (divided by 2) output on pin (such as PA8 pin). + + [..] System, AHB and APB busses clocks configuration + (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, + HSE and PLL. + The AHB clock (HCLK) is derived from System clock through configurable + prescaler and used to clock the CPU, memory and peripherals mapped + on AHB bus (DMA, GPIO...). APB1 (PCLK1) clock is derived + from AHB clock through configurable prescalers and used to clock + the peripherals mapped on these busses. You can use + "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. + + (#) All the peripheral clocks are derived from the System clock (SYSCLK) except: + (++) The FLASH program/erase clock which is always HSI 8MHz clock. + (++) The USB 48 MHz clock which is derived from the PLL VCO clock. + (++) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE. + (++) The I2C clock which can be derived as well from HSI 8MHz clock. + (++) The ADC clock which is derived from PLL output. + (++) The RTC clock which is derived from the LSE, LSI or 1 MHz HSE_RTC + (HSE divided by a programmable prescaler). The System clock (SYSCLK) + frequency must be higher or equal to the RTC clock frequency. + (++) IWDG clock which is always the LSI clock. + + (#) For the STM32F0xx devices, the maximum frequency of the SYSCLK, HCLK and PCLK1 is 48 MHz, + Depending on the SYSCLK frequency, the flash latency should be adapted accordingly: + +-----------------------------------------------+ + | Latency | SYSCLK clock frequency (MHz) | + |---------------|-------------------------------| + |0WS(1CPU cycle)| 0 < SYSCLK <= 24 | + |---------------|-------------------------------| + |1WS(2CPU cycle)| 24 < SYSCLK <= 48 | + +-----------------------------------------------+ + + (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and + prefetch is disabled. + +@endverbatim + * @{ + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as system clock source + * - HSE and PLL OFF + * - AHB, APB1 prescaler set to 1. + * - CSS, MCO OFF + * - All interrupts disabled + * @note This function doesn't modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval None + */ +void HAL_RCC_DeInit(void) +{ + /* Set HSION bit, HSITRIM[4:0] bits to the reset value*/ + SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4); + + /* Reset SW[1:0], HPRE[3:0], PPRE[2:0] and MCOSEL[2:0] bits */ + CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE | RCC_CFGR_MCO); + + /* Reset HSEON, CSSON, PLLON bits */ + CLEAR_BIT(RCC->CR, RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON); + + /* Reset HSEBYP bit */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); + + /* Reset CFGR register */ + CLEAR_REG(RCC->CFGR); + + /* Reset CFGR2 register */ + CLEAR_REG(RCC->CFGR2); + + /* Reset CFGR3 register */ + CLEAR_REG(RCC->CFGR3); + + /* Disable all interrupts */ + CLEAR_REG(RCC->CIR); +} + +/** + * @brief Initializes the RCC Oscillators according to the specified parameters in the + * RCC_OscInitTypeDef. + * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC Oscillators. + * @note The PLL is not disabled when used as system clock. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + /* Note : This function is defined into this file for library reference. */ + /* Function content is located into file stm32f0xx_hal_rcc_ex.c to */ + /* handle the possible oscillators present in STM32F0xx devices */ + + /* Return error status as not implemented here */ + return HAL_ERROR; +} + +/** + * @brief Initializes the CPU, AHB and APB busses clocks according to the specified + * parameters in the RCC_ClkInitStruct. + * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC peripheral. + * @param FLatency: FLASH Latency + * This parameter can be one of the following values: + * @arg FLASH_LATENCY_0: FLASH 0 Latency cycle + * @arg FLASH_LATENCY_1: FLASH 1 Latency cycle + * + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * and updated by HAL_RCC_GetHCLKFreq() function called within this function + * + * @note The HSI is used (enabled by hardware) as system clock source after + * startup from Reset, wake-up from STOP and STANDBY mode, or in case + * of failure of the HSE used directly or indirectly as system clock + * (if the Clock Security System CSS is enabled). + * + * @note A switch from one clock source to another occurs only if the target + * clock source is ready (clock stable after startup delay or PLL locked). + * If a clock source which is not yet ready is selected, the switch will + * occur when the clock source will be ready. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + /* Note : This function is defined into this file for library reference. */ + /* Function content is located into file stm32f0xx_hal_rcc_ex.c to */ + /* handle the possible oscillators present in STM32F0xx devices */ + + /* Return error status as not implemented here */ + return HAL_ERROR; +} + +/** + * @} + */ + +/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control function + * @brief RCC clocks control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control function ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + +@endverbatim + * @{ + */ + +/** + * @brief Selects the clock source to output on MCO pin(such as PA8). + * @note MCO pin (such as PA8) should be configured in alternate function mode. + * @param RCC_MCOx: specifies the output direction for the clock source. + * This parameter can be one of the following values: + * @arg RCC_MCO: Clock source to output on MCO pin(such as PA8). + * @param RCC_MCOSource: specifies the clock source to output. + * This parameter can be one of the following values: + * @arg RCC_MCOSOURCE_LSI: LSI clock selected as MCO source + * @arg RCC_MCOSOURCE_HSI: HSI clock selected as MCO source + * @arg RCC_MCOSOURCE_LSE: LSE clock selected as MCO source + * @arg RCC_MCOSOURCE_HSE: HSE clock selected as MCO source + * @arg RCC_MCOSOURCE_PLLCLK_NODIV: main PLL clock not divided selected as MCO source (not applicable to STM32F05x devices) + * @arg RCC_MCOSOURCE_PLLCLK_DIV2: main PLL clock divided by 2 selected as MCO source + * @arg RCC_MCOSOURCE_SYSCLK: System clock (SYSCLK) selected as MCO source + * @param RCC_MCODiv: specifies the MCOx prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCO_NODIV: no division applied to MCO clock + * @retval None + */ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) +{ + GPIO_InitTypeDef gpio; + /* Check the parameters */ + assert_param(IS_RCC_MCO(RCC_MCOx)); + assert_param(IS_RCC_MCODIV(RCC_MCODiv)); + /* RCC_MCO */ + assert_param(IS_RCC_MCOSOURCE(RCC_MCOSource)); + + /* MCO Clock Enable */ + __MCO_CLK_ENABLE(); + + /* Configue the MCO pin in alternate function mode */ + gpio.Pin = MCO_PIN; + gpio.Mode = GPIO_MODE_AF_PP; + gpio.Speed = GPIO_SPEED_HIGH; + gpio.Pull = GPIO_NOPULL; + gpio.Alternate = GPIO_AF0_MCO; + HAL_GPIO_Init(MCO_GPIO_PORT, &gpio); + + /* Configure the MCO clock source */ + __HAL_RCC_MCO_CONFIG(RCC_MCOSource, RCC_MCODiv); +} + +/** + * @brief Enables the Clock Security System. + * @note If a failure is detected on the HSE oscillator clock, this oscillator + * is automatically disabled and an interrupt is generated to inform the + * software about the failure (Clock Security System Interrupt, CSSI), + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M0 NMI (Non-Maskable Interrupt) exception vector. + * @retval None + */ +void HAL_RCC_EnableCSS(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSSON); +} + +/** + * @brief Disables the Clock Security System. + * @retval None + */ +void HAL_RCC_DisableCSS(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_CSSON); +} + +/** + * @brief Returns the SYSCLK frequency + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note If SYSCLK source is HSI, function returns a value based on HSI_VALUE(*) + * @note If SYSCLK source is HSI48, function returns a value based on HSI48_VALUE(*) + * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE + * divided by PREDIV factor(**) + * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE + * divided by PREDIV factor(**) or depending on STM32F0xx devices either a value based + * on HSI_VALUE divided by 2 or HSI_VALUE divided by PREDIV factor(*) multiplied by the + * PLL factor . + * @note (*) HSI_VALUE & HSI48_VALUE are constants defined in stm32f0xx_hal_conf.h file + * (default values 8 MHz and 48MHz). + * @note (**) HSE_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @note This function can be used by the user application to compute the + * baudrate for the communication peripherals or configure other parameters. + * + * @note Each time SYSCLK changes, this function must be called to update the + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @retval SYSCLK frequency + */ +__weak uint32_t HAL_RCC_GetSysClockFreq(void) +{ + /* Note : This function is defined into this file for library reference. */ + /* Function content is located into file stm32f0xx_hal_rcc_ex.c to */ + /* handle the possible oscillators present in STM32F0xx devices */ + + /* Return error status as not implemented here */ + return HAL_ERROR; +} + +/** + * @brief Returns the HCLK frequency + * @note Each time HCLK changes, this function must be called to update the + * right HCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * and updated within this function + * + * @retval HCLK frequency + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER]; + return SystemCoreClock; +} + +/** + * @brief Returns the PCLK1 frequency + * @note Each time PCLK1 changes, this function must be called to update the + * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK1 frequency + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE)>> RCC_CFGR_PPRE_BITNUMBER]); +} + +/** + * @brief Configures the RCC_OscInitStruct according to the internal + * RCC configuration registers. + * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + /* Set all possible values for the Oscillator type parameter ---------------*/ + RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; + + /* Get the HSE configuration -----------------------------------------------*/ + if((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP) + { + RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; + } + else if((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON) + { + RCC_OscInitStruct->HSEState = RCC_HSE_ON; + } + else + { + RCC_OscInitStruct->HSEState = RCC_HSE_OFF; + } + + /* Get the HSI configuration -----------------------------------------------*/ + if((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION) + { + RCC_OscInitStruct->HSIState = RCC_HSI_ON; + } + else + { + RCC_OscInitStruct->HSIState = RCC_HSI_OFF; + } + + RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_BitNumber); + + /* Get the LSE configuration -----------------------------------------------*/ + if((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) + { + RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; + } + else if((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) + { + RCC_OscInitStruct->LSEState = RCC_LSE_ON; + } + else + { + RCC_OscInitStruct->LSEState = RCC_LSE_OFF; + } + + /* Get the LSI configuration -----------------------------------------------*/ + if((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION) + { + RCC_OscInitStruct->LSIState = RCC_LSI_ON; + } + else + { + RCC_OscInitStruct->LSIState = RCC_LSI_OFF; + } + + /* Get the PLL configuration -----------------------------------------------*/ + if((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON) + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; + } + else + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; + } + RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC); + RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL); + RCC_OscInitStruct->PLL.PREDIV = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV); + + /* Get the HSI14 configuration -----------------------------------------------*/ + if((RCC->CR2 & RCC_CR2_HSI14ON) == RCC_CR2_HSI14ON) + { + RCC_OscInitStruct->HSI14State = RCC_HSI_ON; + } + else + { + RCC_OscInitStruct->HSI14State = RCC_HSI_OFF; + } + + RCC_OscInitStruct->HSI14CalibrationValue = (uint32_t)((RCC->CR2 & RCC_CR2_HSI14TRIM) >> RCC_CR2_HSI14TRIM_BitNumber); + + /* Get the HSI48 configuration if any-----------------------------------------*/ + RCC_OscInitStruct->HSI48State = __HAL_RCC_GET_HSI48_STATE(); +} + +/** + * @brief Get the RCC_ClkInitStruct according to the internal + * RCC configuration registers. + * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that + * contains the current clock configuration. + * @param pFLatency: Pointer on the Flash Latency. + * @retval None + */ +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) +{ + /* Set all possible values for the Clock type parameter --------------------*/ + RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1; + + /* Get the SYSCLK configuration --------------------------------------------*/ + RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); + + /* Get the HCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); + + /* Get the APB1 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE); + + /* Get the Flash Wait State (Latency) configuration ------------------------*/ + *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); +} + +/** + * @brief This function handles the RCC CSS interrupt request. + * @note This API should be called under the NMI_Handler(). + * @retval None + */ +void HAL_RCC_NMI_IRQHandler(void) +{ + /* Check RCC CSSF flag */ + if(__HAL_RCC_GET_IT(RCC_IT_CSS)) + { + /* RCC Clock Security System interrupt user callback */ + HAL_RCC_CCSCallback(); + + /* Clear RCC CSS pending bit */ + __HAL_RCC_CLEAR_IT(RCC_IT_CSS); + } +} + +/** + * @brief RCC Clock Security System interrupt callback + * @retval none + */ +__weak void HAL_RCC_CCSCallback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RCC_CCSCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c @@ -0,0 +1,1406 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_rcc_ex.c + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Extended RCC HAL module driver + * This file provides firmware functions to manage the following + * functionalities RCC extension peripheral: + * + Extended Clock Source configuration functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + + For CRS, RCC Extention HAL driver can be used as follows: + + (#) In System clock config, HSI48 need to be enabled + + (#] Enable CRS clock in IP MSP init which will use CRS functions + + (#) Call CRS functions like this + (##) Prepare synchronization configuration necessary for HSI48 calibration + (+++) Default values can be set for frequency Error Measurement (reload and error limit) + and also HSI48 oscillator smooth trimming. + (+++) Macro __HAL_RCC_CRS_CALCULATE_RELOADVALUE can be also used to calculate + directly reload value with target and sychronization frequencies values + (##) Call function HAL_RCCEx_CRSConfig which + (+++) Reset CRS registers to their default values. + (+++) Configure CRS registers with synchronization configuration + (+++) Enable automatic calibration and frequency error counter feature + + (##) A polling function is provided to wait for complete Synchronization + (+++) Call function HAL_RCCEx_CRSWaitSynchronization() + (+++) According to CRS status, user can decide to adjust again the calibration or continue + application if synchronization is OK + + (#) User can retrieve information related to synchronization in calling function + HAL_RCCEx_CRSGetSynchronizationInfo() + + (#) Regarding synchronization status and synchronization information, user can try a new calibration + in changing synchronization configuration and call again HAL_RCCEx_CRSConfig. + Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value), + it means that the actual frequency is lower than the target (and so, that the TRIM value should be + incremented), while when it is detected during the upcounting phase it means that the actual frequency + is higher (and that the TRIM value should be decremented). + + (#) To use IT mode, user needs to handle it in calling different macros available to do it + (__HAL_RCC_CRS_XXX_IT). Interuptions will go through RCC Handler (RCC_IRQn/RCC_CRS_IRQHandler) + (++) Call function HAL_RCCEx_CRSConfig() + (++) Enable RCC_IRQn (thnaks to NVIC functions) + (++) Enable CRS IT (__HAL_RCC_CRS_ENABLE_IT) + (++) Implement CRS status management in RCC_CRS_IRQHandler + + (#) To force a SYNC EVENT, user can use function HAL_RCCEx_CRSSoftwareSynchronizationGenerate(). Function can be + called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler) + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup RCCEx RCCEx Extended HAL module driver + * @brief RCC Extension HAL module driver. + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Define RCCEx Private Define + * @{ + */ +#define HSI48_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ + +/* Bit position in register */ +#define CRS_CFGR_FELIM_BITNUMBER 16 +#define CRS_CR_TRIM_BITNUMBER 8 +#define CRS_ISR_FECAP_BITNUMBER 16 +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Variables RCCEx Private Variables + * @{ + */ +const uint8_t PLLMULFactorTable[16] = { 2, 3, 4, 5, 6, 7, 8, 9, + 10, 11, 12, 13, 14, 15, 16, 16}; +const uint8_t PredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8, + 9,10, 11, 12, 13, 14, 15, 16}; +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions + * @{ + */ + +/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions + * @brief Extended RCC clocks control functions + * +@verbatim + =============================================================================== + ##### Extended Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + [..] + (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to + select the RTC clock source; in this case the Backup domain will be reset in + order to modify the RTC Clock source, as consequence RTC registers (including + the backup registers) and RCC_BDCR register are set to their reset values. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the RCC Oscillators according to the specified parameters in the + * RCC_OscInitTypeDef. + * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC Oscillators. + * @note The PLL is not disabled when used as system clock. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + /*------------------------------- HSE Configuration ------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) || + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState != RCC_HSE_ON)) + { + return HAL_ERROR; + } + } + else + { + /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/ + __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF); + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait till HSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + { + if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG((uint8_t)RCC_OscInitStruct->HSEState); + + /* Check the HSE State */ + if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + { + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait till HSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + { + if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait till HSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + { + if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) || + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI))) + { + /* When the HSI is used as system clock it is not allowed to be disabled */ + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + { + return HAL_ERROR; + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + } + else + { + /* Check the HSI State */ + if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + { + if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + { + if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + { + if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + { + if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + { + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Enable Power Clock */ + __PWR_CLK_ENABLE(); + + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while((PWR->CR & PWR_CR_DBP) == RESET) + { + if((HAL_GetTick() - tickstart) > DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/ + __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF); + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + { + if((HAL_GetTick() - tickstart) > LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + /* Check the LSE State */ + if(RCC_OscInitStruct->LSEState == RCC_LSE_ON) + { + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if((HAL_GetTick() - tickstart) > LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + { + if((HAL_GetTick() - tickstart) > LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + + /*----------------------------- HSI14 Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI14(RCC_OscInitStruct->HSI14State)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSI14CalibrationValue)); + + /* Check the HSI14 State */ + if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ON) + { + /* Disable ADC control of the Internal High Speed oscillator HSI14 */ + __HAL_RCC_HSI14ADC_DISABLE(); + + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI14_ENABLE(); + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET) + { + if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */ + __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue); + } + else if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ADC_CONTROL) + { + /* Enable ADC control of the Internal High Speed oscillator HSI14 */ + __HAL_RCC_HSI14ADC_ENABLE(); + + /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */ + __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue); + } + else + { + /* Disable ADC control of the Internal High Speed oscillator HSI14 */ + __HAL_RCC_HSI14ADC_DISABLE(); + + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI14_DISABLE(); + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET) + { + if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + /*----------------------------- HSI48 Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); + + /* When the HSI48 is used as system clock it is not allowed to be disabled */ + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI48) || + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI48))) + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) && (RCC_OscInitStruct->HSI48State != RCC_HSI48_ON)) + { + return HAL_ERROR; + } + } + else + { + /* Check the HSI State */ + if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF) + { + /* Enable the Internal High Speed oscillator (HSI48). */ + __HAL_RCC_HSI48_ENABLE(); + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET) + { + if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal High Speed oscillator (HSI48). */ + __HAL_RCC_HSI48_DISABLE(); + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) + { + if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + { + /* Check if the PLL is used as system clock or not */ + if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + { + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + { + /* Check the parameters */ + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV)); + assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the main PLL clock source, predivider and multiplication factor. */ + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + RCC_OscInitStruct->PLL.PREDIV, + RCC_OscInitStruct->PLL.PLLMUL); + + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + else + { + return HAL_ERROR; + } + } + return HAL_OK; +} + +/** + * @brief Initializes the CPU, AHB and APB busses clocks according to the specified + * parameters in the RCC_ClkInitStruct. + * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC peripheral. + * @param FLatency: FLASH Latency + * This parameter can be one of the following values: + * @arg FLASH_LATENCY_0: FLASH 0 Latency cycle + * @arg FLASH_LATENCY_1: FLASH 1 Latency cycle + * + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * and updated by HAL_RCC_GetHCLKFreq() function called within this function + * + * @note The HSI is used (enabled by hardware) as system clock source after + * startup from Reset, wake-up from STOP and STANDBY mode, or in case + * of failure of the HSE used directly or indirectly as system clock + * (if the Clock Security System CSS is enabled). + * + * @note A switch from one clock source to another occurs only if the target + * clock source is ready (clock stable after startup delay or PLL locked). + * If a clock source which is not yet ready is selected, the switch will + * occur when the clock source will be ready. + * @retval None + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); + assert_param(IS_FLASH_LATENCY(FLatency)); + + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) of the device. */ + + /* Increasing the CPU frequency */ + if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY)) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) + { + return HAL_ERROR; + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { + assert_param(IS_RCC_SYSCLK_DIV(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + /* Check the HSE ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + { + return HAL_ERROR; + } + } + /* PLL is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + /* Check the PLL ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + return HAL_ERROR; + } + } +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + /* HSI48 is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48) + { + /* Check the HSI48 ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET) + { + return HAL_ERROR; + } + } +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + { + return HAL_ERROR; + } + } + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); + + /* Get timeout */ + tickstart = HAL_GetTick(); + + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) + { + if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + { + if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48) + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI48) + { + if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + else + { + while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) + { + if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /* Decreasing the CPU frequency */ + else + { + /*-------------------------- HCLK Configuration --------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { + assert_param(IS_RCC_SYSCLK_DIV(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + /* Check the HSE ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + { + return HAL_ERROR; + } + } + /* PLL is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + /* Check the PLL ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + return HAL_ERROR; + } + } +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + /* HSI48 is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48) + { + /* Check the HSI48 ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET) + { + return HAL_ERROR; + } + } +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + { + return HAL_ERROR; + } + } + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); + + /* Get timeout */ + tickstart = HAL_GetTick(); + + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) + { + if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + { + if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48) + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI48) + { + if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + else + { + while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) + { + if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) + { + return HAL_ERROR; + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + assert_param(IS_RCC_HCLK_DIV(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider); + } + + /* Configure the source of time base considering new system clocks settings*/ + HAL_InitTick (TICK_INT_PRIORITY); + + return HAL_OK; +} + +/** + * @brief Returns the SYSCLK frequency + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note If SYSCLK source is HSI, function returns a value based on HSI_VALUE(*) + * @note If SYSCLK source is HSI48, function returns a value based on HSI48_VALUE(*) + * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE + * divided by PREDIV factor(**) + * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE + * divided by PREDIV factor(**) or depending on STM32F0xx devices either a value based + * on HSI_VALUE divided by 2 or HSI_VALUE divided by PREDIV factor(*) multiplied by the + * PLL factor . + * @note (*) HSI_VALUE & HSI48_VALUE are constants defined in stm32f0xx_hal_conf.h file + * (default values 8 MHz and 48MHz). + * @note (**) HSE_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @note This function can be used by the user application to compute the + * baudrate for the communication peripherals or configure other parameters. + * + * @note Each time SYSCLK changes, this function must be called to update the + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + uint32_t tmpreg = 0, prediv = 0, pllmul = 0, pllclk = 0; + uint32_t sysclockfreq = 0; + + tmpreg = RCC->CFGR; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (tmpreg & RCC_CFGR_SWS) + { + case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ + sysclockfreq = HSE_VALUE; + break; + + case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */ + pllmul = PLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER]; + prediv = PredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_BITNUMBER]; + if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ + pllclk = (HSE_VALUE/prediv) * pllmul; + } +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + else if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSI48) + { + /* HSI48 used as PLL clock source : PLLCLK = HSI48/PREDIV * PLLMUL */ + pllclk = (HSI48_VALUE/prediv) * pllmul; + } +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + else + { +#if defined(STM32F042x6) || defined(STM32F048xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */ + pllclk = (HSI_VALUE/prediv) * pllmul; +#else + /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ + pllclk = (HSI_VALUE >> 1) * pllmul; +#endif /* STM32F042x6 || STM32F048xx || STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + } + sysclockfreq = pllclk; + break; + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + case RCC_SYSCLKSOURCE_STATUS_HSI48: /* HSI48 used as system clock source */ + sysclockfreq = HSI48_VALUE; + break; +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + + case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + default: + sysclockfreq = HSI_VALUE; + break; + } + return sysclockfreq; +} + +/** + * @brief Initializes the RCC extended peripherals clocks according to the specified + * parameters in the RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains the configuration information for the Extended Peripherals clocks + * (USART, RTC, I2C, CEC and USB). + * + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including + * the backup registers) and RCC_BDCR register are set to their reset values. + * + * @retval None + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tickstart = 0; + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLK(PeriphClkInit->PeriphClockSelection)); + + /*---------------------------- RTC configuration -------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + { + /* Enable Power Clock*/ + __PWR_CLK_ENABLE(); + + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while((PWR->CR & PWR_CR_DBP) == RESET) + { + if((HAL_GetTick() - tickstart) > DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Reset the Backup domain only if the RTC Clock source selction is modified */ + if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpreg; + } + + /* If LSE is selected as RTC clock source, wait for LSE reactivation */ + if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) + { + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if((HAL_GetTick() - tickstart) > LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + } + + /*------------------------------- USART1 Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) + { + /* Check the parameters */ + assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); + + /* Configure the USART1 clock source */ + __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); + } + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + /*----------------------------- USART2 Configuration --------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) + { + /* Check the parameters */ + assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); + + /* Configure the USART2 clock source */ + __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); + } +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F091xC) || defined(STM32F098xx) + /*----------------------------- USART3 Configuration --------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) + { + /* Check the parameters */ + assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); + + /* Configure the USART3 clock source */ + __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); + } +#endif /* STM32F091xC || STM32F098xx */ + + /*------------------------------ I2C1 Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); + + /* Configure the I2C1 clock source */ + __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); + } + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) + /*------------------------------ USB Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) + { + /* Check the parameters */ + assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection)); + + /* Configure the USB clock source */ + __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); + } +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || \ + defined(STM32F051x8) || defined(STM32F058xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + /*------------------------------ CEC clock Configuration -------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) + { + /* Check the parameters */ + assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); + + /* Configure the CEC clock source */ + __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); + } +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + + return HAL_OK; +} + +/** + * @brief Get the RCC_ClkInitStruct according to the internal + * RCC configuration registers. + * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * returns the configuration information for the Extended Peripherals clocks + * (USART, RTC, I2C, CEC and USB). + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + /* Set all possible values for the extended clock type parameter------------*/ + /* Common part first */ + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC; + /* Get the RTC configuration --------------------------------------------*/ + PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE(); + /* Get the USART1 configuration --------------------------------------------*/ + PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); + /* Get the I2C1 clock source -----------------------------------------------*/ + PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART2; + /* Get the USART2 clock source ---------------------------------------------*/ + PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F091xC) || defined(STM32F098xx) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART3; + /* Get the USART3 clock source ---------------------------------------------*/ + PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); +#endif /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB; + /* Get the USB clock source ---------------------------------------------*/ + PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || \ + defined(STM32F051x8) || defined(STM32F058xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_CEC; + /* Get the CEC clock source ------------------------------------------------*/ + PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE(); +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +} + +#if defined(STM32F042x6) || defined(STM32F048xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) +/** + * @brief Start automatic synchronization using polling mode + * @param pInit Pointer on RCC_CRSInitTypeDef structure + * @retval None + */ +void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) +{ + /* Check the parameters */ + assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler)); + assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source)); + assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity)); + assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue)); + assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue)); + assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue)); + + + /* CONFIGURATION */ + + /* Before configuration, reset CRS registers to their default values*/ + __CRS_FORCE_RESET(); + __CRS_RELEASE_RESET(); + + /* Configure Synchronization input */ + /* Clear SYNCDIV[2:0], SYNCSRC[1:0] & SYNCSPOL bits */ + CRS->CFGR &= ~(CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL); + + /* Set the CRS_CFGR_SYNCDIV[2:0] bits according to Prescaler value */ + CRS->CFGR |= pInit->Prescaler; + + /* Set the SYNCSRC[1:0] bits according to Source value */ + CRS->CFGR |= pInit->Source; + + /* Set the SYNCSPOL bits according to Polarity value */ + CRS->CFGR |= pInit->Polarity; + + /* Configure Frequency Error Measurement */ + /* Clear RELOAD[15:0] & FELIM[7:0] bits*/ + CRS->CFGR &= ~(CRS_CFGR_RELOAD | CRS_CFGR_FELIM); + + /* Set the RELOAD[15:0] bits according to ReloadValue value */ + CRS->CFGR |= pInit->ReloadValue; + + /* Set the FELIM[7:0] bits according to ErrorLimitValue value */ + CRS->CFGR |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_BITNUMBER); + + /* Adjust HSI48 oscillator smooth trimming */ + /* Clear TRIM[5:0] bits */ + CRS->CR &= ~CRS_CR_TRIM; + + /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */ + CRS->CR |= (pInit->HSI48CalibrationValue << CRS_CR_TRIM_BITNUMBER); + + + /* START AUTOMATIC SYNCHRONIZATION*/ + + /* Enable Automatic trimming */ + __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB(); + + /* Enable Frequency error counter */ + __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER(); + +} + +/** + * @brief Generate the software synchronization event + * @retval None + */ +void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void) +{ + CRS->CR |= CRS_CR_SWSYNC; +} + + +/** + * @brief Function to return synchronization info + * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure + * @retval None + */ +void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo) +{ + /* Check the parameter */ + assert_param(pSynchroInfo != NULL); + + /* Get the reload value */ + pSynchroInfo->ReloadValue = (uint32_t)(CRS->CFGR & CRS_CFGR_RELOAD); + + /* Get HSI48 oscillator smooth trimming */ + pSynchroInfo->HSI48CalibrationValue = (uint32_t)((CRS->CR & CRS_CR_TRIM) >> CRS_CR_TRIM_BITNUMBER); + + /* Get Frequency error capture */ + pSynchroInfo->FreqErrorCapture = (uint32_t)((CRS->ISR & CRS_ISR_FECAP) >> CRS_ISR_FECAP_BITNUMBER); + + /* Get FFrequency error direction */ + pSynchroInfo->FreqErrorDirection = (uint32_t)(CRS->ISR & CRS_ISR_FEDIR); + + +} + +/** +* @brief This function handles CRS Synchronization Timeout. +* @param Timeout: Duration of the timeout +* @note Timeout is based on the maximum time to receive a SYNC event based on synchronization +* frequency. +* @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned. +* @retval Combination of Synchronization status +* This parameter can be a combination of the following values: +* @arg RCC_CRS_TIMEOUT +* @arg RCC_CRS_SYNCOK +* @arg RCC_CRS_SYNCWARM +* @arg RCC_CRS_SYNCERR +* @arg RCC_CRS_SYNCMISS +* @arg RCC_CRS_TRIMOV +*/ +RCC_CRSStatusTypeDef HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) +{ + RCC_CRSStatusTypeDef crsstatus = RCC_CRS_NONE; + uint32_t tickstart = 0; + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Check that if one of CRS flags have been set */ + while(RCC_CRS_NONE == crsstatus) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + { + crsstatus = RCC_CRS_TIMEOUT; + } + } + /* Check CRS SYNCOK flag */ + if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK)) + { + /* CRS SYNC event OK */ + crsstatus |= RCC_CRS_SYNCOK; + + /* Clear CRS SYNC event OK bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK); + } + + /* Check CRS SYNCWARN flag */ + if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN)) + { + /* CRS SYNC warning */ + crsstatus |= RCC_CRS_SYNCWARM; + + /* Clear CRS SYNCWARN bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN); + } + + /* Check CRS TRIM overflow flag */ + if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF)) + { + /* CRS SYNC Error */ + crsstatus |= RCC_CRS_TRIMOV; + + /* Clear CRS Error bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF); + } + + /* Check CRS Error flag */ + if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR)) + { + /* CRS SYNC Error */ + crsstatus |= RCC_CRS_SYNCERR; + + /* Clear CRS Error bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR); + } + + /* Check CRS SYNC Missed flag */ + if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS)) + { + /* CRS SYNC Missed */ + crsstatus |= RCC_CRS_SYNCMISS; + + /* Clear CRS SYNC Missed bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS); + } + + /* Check CRS Expected SYNC flag */ + if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC)) + { + /* frequency error counter reached a zero value */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC); + } + } + + return crsstatus; +} + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rtc.c b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rtc.c new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rtc.c @@ -0,0 +1,1365 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_rtc.c + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief RTC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Real-Time Clock (RTC) peripheral: + * + Initialization + * + Calendar (Time and Date) configuration + * + Alarm A configuration + * + Backup Data Registers configuration + * + Interrupts and flags management + * + @verbatim + + =============================================================================== + ##### RTC Operating Condition ##### + =============================================================================== + [..] The real-time clock (RTC) and the RTC backup registers can be powered + from the VBAT voltage when the main VDD supply is powered off. + To retain the content of the RTC backup registers and supply the RTC + when VDD is turned off, VBAT pin can be connected to an optional + standby voltage supplied by a battery or by another source. + + [..] To allow the RTC to operate even when the main digital supply (VDD) + is turned off, the VBAT pin powers the following blocks: + (#) The RTC + (#) The LSE oscillator + (#) PC13 to PC15 I/Os (when available) + + [..] When the backup domain is supplied by VDD (analog switch connected + to VDD), the following functions are available: + (#) PC14 and PC15 can be used as either GPIO or LSE pins + (#) PC13 can be used as a GPIO or as the RTC_OUT pin + + [..] When the backup domain is supplied by VBAT (analog switch connected + to VBAT because VDD is not present), the following functions are available: + (#) PC14 and PC15 can be used as LSE pins only + (#) PC13 can be used as the RTC_OUT pin + + ##### Backup Domain Reset ##### + =============================================================================== + [..] The backup domain reset sets all RTC registers and the RCC_BDCR + register to their reset values. + A backup domain reset is generated when one of the following events + occurs: + (#) Software reset, triggered by setting the BDRST bit in the + RCC Backup domain control register (RCC_BDCR). + (#) VDD or VBAT power on, if both supplies have previously been + powered off. + + ##### Backup Domain Access ##### + =================================================================== + [..] After reset, the backup domain (RTC registers, RTC backup data + registers and backup SRAM) is protected against possible unwanted write + accesses. + + [..] To enable access to the RTC Domain and RTC registers, proceed as follows: + (#) Enable the Power Controller (PWR) APB1 interface clock using the + __PWR_CLK_ENABLE() function. + (#) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. + (#) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function. + (#) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function. + + + ##### How to use RTC Driver ##### + =================================================================== + [..] + (+) Enable the RTC domain access (see description in the section above). + (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour + format using the HAL_RTC_Init() function. + + *** Time and Date configuration *** + =================================== + [..] + (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime() + and HAL_RTC_SetDate() functions. + (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions. + + *** Alarm configuration *** + =========================== + [..] + (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function. + You can also configure the RTC Alarm with interrupt mode using the + HAL_RTC_SetAlarm_IT() function. + (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function. + + + ##### RTC and low power modes ##### + =================================================================== + [..] The MCU can be woken up from a low power mode by an RTC alternate + function. + [..] The RTC alternate functions are the RTC alarm (Alarm A), + RTC wakeup, RTC tamper event detection and RTC time stamp event detection. + These RTC alternate functions can wake up the system from the Stop and + Standby low power modes. + [..] The system can also wake up from low power modes without depending + on an external interrupt (Auto-wakeup mode), by using the RTC alarm + or the RTC wakeup events. + [..] The RTC provides a programmable time base for waking up from the + Stop or Standby mode at regular intervals. + Wakeup from STOP and Standby modes is possible only when the RTC clock source + is LSE or LSI. + + @endverbatim + + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup RTC RTC HAL module driver + * @brief RTC HAL module driver + * @{ + */ + +#ifdef HAL_RTC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup RTC_Exported_Functions RTC Exported Functions + * @{ + */ + +/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provide functions allowing to initialize and configure the + RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable + RTC registers Write protection, enter and exit the RTC initialization mode, + RTC registers synchronization check and reference clock detection enable. + (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. + It is split into 2 programmable prescalers to minimize power consumption. + (++) A 7-bit asynchronous prescaler and A 15-bit synchronous prescaler. + (++) When both prescalers are used, it is recommended to configure the + asynchronous prescaler to a high value to minimize consumption. + (#) All RTC registers are Write protected. Writing to the RTC registers + is enabled by writing a key into the Write Protection register, RTC_WPR. + (#) To Configure the RTC Calendar, user application should enter + initialization mode. In this mode, the calendar counter is stopped + and its value can be updated. When the initialization sequence is + complete, the calendar restarts counting after 4 RTCCLK cycles. + (#) To read the calendar through the shadow registers after Calendar + initialization, calendar update or after wakeup from low power modes + the software must first clear the RSF flag. The software must then + wait until it is set again before reading the calendar, which means + that the calendar registers have been correctly copied into the + RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function + implements the above software sequence (RSF clear and RSF check). + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the RTC peripheral + * @param hrtc: RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) +{ + /* Check the RTC peripheral state */ + if(hrtc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); + assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat)); + assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv)); + assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv)); + assert_param(IS_RTC_OUTPUT(hrtc->Init.OutPut)); + assert_param(IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity)); + assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType)); + + if(hrtc->State == HAL_RTC_STATE_RESET) + { + /* Initialize RTC MSP */ + HAL_RTC_MspInit(hrtc); + } + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Set Initialization mode */ + if(RTC_EnterInitMode(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + + return HAL_ERROR; + } + else + { + /* Clear RTC_CR FMT, OSEL and POL Bits */ + hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL)); + /* Set RTC_CR register */ + hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity); + + /* Configure the RTC PRER */ + hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv); + hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16); + + /* Exit Initialization mode */ + hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; + + hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_ALARMOUTTYPE; + hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + return HAL_OK; + } +} + +/** + * @brief DeInitializes the RTC peripheral + * @param hrtc: RTC handle + * @note This function doesn't reset the RTC Backup Data registers. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) +{ + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Set Initialization mode */ + if(RTC_EnterInitMode(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + + return HAL_ERROR; + } + else + { + /* Reset TR, DR and CR registers */ + hrtc->Instance->TR = (uint32_t)0x00000000; + hrtc->Instance->DR = (uint32_t)0x00002101; + /* Reset all RTC CR register bits */ + hrtc->Instance->CR &= (uint32_t)0x00000000; + hrtc->Instance->PRER = (uint32_t)0x007F00FF; + hrtc->Instance->ALRMAR = (uint32_t)0x00000000; + hrtc->Instance->SHIFTR = (uint32_t)0x00000000; + hrtc->Instance->CALR = (uint32_t)0x00000000; + hrtc->Instance->ALRMASSR = (uint32_t)0x00000000; + + /* Reset ISR register and exit initialization mode */ + hrtc->Instance->ISR = (uint32_t)0x00000000; + + /* Reset Tamper and alternate functions configuration register */ + hrtc->Instance->TAFCR = 0x00000000; + + /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) + { + if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_ERROR; + + return HAL_ERROR; + } + } + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* De-Initialize RTC MSP */ + HAL_RTC_MspDeInit(hrtc); + + hrtc->State = HAL_RTC_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Initializes the RTC MSP. + * @param hrtc: RTC handle + * @retval None + */ +__weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RTC_MspInit could be implenetd in the user file + */ +} + +/** + * @brief DeInitializes the RTC MSP. + * @param hrtc: RTC handle + * @retval None + */ +__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RTC_MspDeInit could be implenetd in the user file + */ +} + +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions + * @brief RTC Time and Date functions + * +@verbatim + =============================================================================== + ##### RTC Time and Date functions ##### + =============================================================================== + + [..] This section provide functions allowing to configure Time and Date features + +@endverbatim + * @{ + */ + +/** + * @brief Sets RTC current time. + * @param hrtc: RTC handle + * @param sTime: Pointer to Time structure + * @param Format: Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg Format_BIN: Binary data format + * @arg Format_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving)); + assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + if(Format == FORMAT_BIN) + { + if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + { + assert_param(IS_RTC_HOUR12(sTime->Hours)); + assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); + } + else + { + sTime->TimeFormat = 0x00; + assert_param(IS_RTC_HOUR24(sTime->Hours)); + } + assert_param(IS_RTC_MINUTES(sTime->Minutes)); + assert_param(IS_RTC_SECONDS(sTime->Seconds)); + + tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16) | \ + ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8) | \ + ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \ + (((uint32_t)sTime->TimeFormat) << 16)); + } + else + { + if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + { + tmpreg = RTC_Bcd2ToByte(sTime->Hours); + assert_param(IS_RTC_HOUR12(tmpreg)); + assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); + } + else + { + sTime->TimeFormat = 0x00; + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours))); + } + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds))); + tmpreg = (((uint32_t)(sTime->Hours) << 16) | \ + ((uint32_t)(sTime->Minutes) << 8) | \ + ((uint32_t)sTime->Seconds) | \ + ((uint32_t)(sTime->TimeFormat) << 16)); + } + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Set Initialization mode */ + if(RTC_EnterInitMode(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + else + { + /* Set the RTC_TR register */ + hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); + + /* Clear the bits to be configured */ + hrtc->Instance->CR &= (uint32_t)~RTC_CR_BCK; + + /* Configure the RTC_CR register */ + hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation); + + /* Exit Initialization mode */ + hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; + + /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) + { + if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY; + + __HAL_UNLOCK(hrtc); + + return HAL_OK; + } +} + +/** + * @brief Gets RTC current time. + * @param hrtc: RTC handle + * @param sTime: Pointer to Time structure + * @param Format: Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg Format_BIN: Binary data format + * @arg Format_BCD: BCD data format + * @note Call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values + * in the higher-order calendar shadow registers. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Get subseconds values from the correspondent registers*/ + sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR); + + /* Get the TR register */ + tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK); + + /* Fill the structure fields with the read parameters */ + sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16); + sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8); + sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU)); + sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16); + + /* Check the input parameters format */ + if(Format == FORMAT_BIN) + { + /* Convert the time structure parameters to Binary format */ + sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours); + sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes); + sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds); + } + + return HAL_OK; +} + +/** + * @brief Sets RTC current date. + * @param hrtc: RTC handle + * @param sDate: Pointer to date structure + * @param Format: specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg Format_BIN: Binary data format + * @arg Format_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) +{ + uint32_t datetmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + if((Format == FORMAT_BIN) && ((sDate->Month & 0x10) == 0x10)) + { + sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10)) + (uint8_t)0x0A); + } + + assert_param(IS_RTC_WEEKDAY(sDate->WeekDay)); + + if(Format == FORMAT_BIN) + { + assert_param(IS_RTC_YEAR(sDate->Year)); + assert_param(IS_RTC_MONTH(sDate->Month)); + assert_param(IS_RTC_DATE(sDate->Date)); + + datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16) | \ + ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8) | \ + ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \ + ((uint32_t)sDate->WeekDay << 13)); + } + else + { + assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year))); + datetmpreg = RTC_Bcd2ToByte(sDate->Month); + assert_param(IS_RTC_MONTH(datetmpreg)); + datetmpreg = RTC_Bcd2ToByte(sDate->Date); + assert_param(IS_RTC_DATE(datetmpreg)); + + datetmpreg = ((((uint32_t)sDate->Year) << 16) | \ + (((uint32_t)sDate->Month) << 8) | \ + ((uint32_t)sDate->Date) | \ + (((uint32_t)sDate->WeekDay) << 13)); + } + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Set Initialization mode */ + if(RTC_EnterInitMode(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Set RTC state*/ + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + else + { + /* Set the RTC_DR register */ + hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK); + + /* Exit Initialization mode */ + hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; + + /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) + { + if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY ; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; + } +} + +/** + * @brief Gets RTC current date. + * @param hrtc: RTC handle + * @param sDate: Pointer to Date structure + * @param Format: Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg Format_BIN : Binary data format + * @arg Format_BCD : BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) +{ + uint32_t datetmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Get the DR register */ + datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK); + + /* Fill the structure fields with the read parameters */ + sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16); + sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8); + sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU)); + sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13); + + /* Check the input parameters format */ + if(Format == FORMAT_BIN) + { + /* Convert the date structure parameters to Binary format */ + sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year); + sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month); + sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date); + } + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions + * @brief RTC Alarm functions + * +@verbatim + =============================================================================== + ##### RTC Alarm functions ##### + =============================================================================== + + [..] This section provide functions allowing to configure Alarm feature + +@endverbatim + * @{ + */ +/** + * @brief Sets the specified RTC Alarm. + * @param hrtc: RTC handle + * @param sAlarm: Pointer to Alarm structure + * @param Format: Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg Format_BIN: Binary data format + * @arg Format_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) +{ + uint32_t tickstart = 0; + uint32_t tmpreg = 0, subsecondtmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + assert_param(IS_ALARM(sAlarm->Alarm)); + assert_param(IS_ALARM_MASK(sAlarm->AlarmMask)); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel)); + assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds)); + assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + if(Format == FORMAT_BIN) + { + if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + { + assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours)); + assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); + } + else + { + sAlarm->AlarmTime.TimeFormat = 0x00; + assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); + } + assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); + assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); + + if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay)); + } + else + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); + } + + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \ + ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + ((uint32_t)sAlarm->AlarmMask)); + } + else + { + if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + { + tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours); + assert_param(IS_RTC_HOUR12(tmpreg)); + assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); + } + else + { + sAlarm->AlarmTime.TimeFormat = 0x00; + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); + } + + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); + + if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + { + tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); + } + else + { + tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); + } + + tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \ + ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \ + ((uint32_t) sAlarm->AlarmTime.Seconds) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ + ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \ + ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + ((uint32_t)sAlarm->AlarmMask)); + } + + /* Configure the Alarm A Sub Second registers */ + subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask)); + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Disable the Alarm A interrupt */ + __HAL_RTC_ALARMA_DISABLE(hrtc); + + /* In case of interrupt mode is used, the interrupt source must disabled */ + __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA); + + tickstart = HAL_GetTick(); + + /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */ + while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET) + { + if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + + hrtc->Instance->ALRMAR = (uint32_t)tmpreg; + /* Configure the Alarm A Sub Second register */ + hrtc->Instance->ALRMASSR = subsecondtmpreg; + /* Configure the Alarm state: Enable Alarm */ + __HAL_RTC_ALARMA_ENABLE(hrtc); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Sets the specified RTC Alarm with Interrupt + * @param hrtc: RTC handle + * @param sAlarm: Pointer to Alarm structure + * @param Format: Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg Format_BIN: Binary data format + * @arg Format_BCD: BCD data format + * @note The Alarm register can only be written when the corresponding Alarm + * is disabled (Use the HAL_RTC_DeactivateAlarm()). + * @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) +{ + uint32_t tickstart = 0; + uint32_t tmpreg = 0, subsecondtmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + assert_param(IS_ALARM(sAlarm->Alarm)); + assert_param(IS_ALARM_MASK(sAlarm->AlarmMask)); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel)); + assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds)); + assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + if(Format == FORMAT_BIN) + { + if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + { + assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours)); + assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); + } + else + { + sAlarm->AlarmTime.TimeFormat = 0x00; + assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); + } + assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); + assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); + + if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay)); + } + else + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); + } + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \ + ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + ((uint32_t)sAlarm->AlarmMask)); + } + else + { + if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + { + tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours); + assert_param(IS_RTC_HOUR12(tmpreg)); + assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); + } + else + { + sAlarm->AlarmTime.TimeFormat = 0x00; + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); + } + + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); + + if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + { + tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); + } + else + { + tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); + } + tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \ + ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \ + ((uint32_t) sAlarm->AlarmTime.Seconds) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ + ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \ + ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + ((uint32_t)sAlarm->AlarmMask)); + } + /* Configure the Alarm A Sub Second registers */ + subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask)); + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Disable the Alarm A interrupt */ + __HAL_RTC_ALARMA_DISABLE(hrtc); + + /* Clear flag alarm A */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); + + tickstart = HAL_GetTick(); + + /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */ + while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET) + { + if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + + hrtc->Instance->ALRMAR = (uint32_t)tmpreg; + /* Configure the Alarm A Sub Second register */ + hrtc->Instance->ALRMASSR = subsecondtmpreg; + /* Configure the Alarm state: Enable Alarm */ + __HAL_RTC_ALARMA_ENABLE(hrtc); + /* Configure the Alarm interrupt */ + __HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA); + + /* RTC Alarm Interrupt Configuration: EXTI configuration */ + __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT); + + EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT; + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Deactive the specified RTC Alarm + * @param hrtc: RTC handle + * @param Alarm: Specifies the Alarm. + * This parameter can be one of the following values: + * @arg ALARM_A : AlarmA + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm) +{ + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param(IS_ALARM(Alarm)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + __HAL_RTC_ALARMA_DISABLE(hrtc); + + /* In case of interrupt mode is used, the interrupt source must disabled */ + __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA); + + tickstart = HAL_GetTick(); + + /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ + while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET) + { + if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Gets the RTC Alarm value and masks. + * @param hrtc: RTC handle + * @param sAlarm: Pointer to Date structure + * @param Alarm: Specifies the Alarm + * This parameter can be one of the following values: + * @arg ALARM_A: AlarmA + * @param Format: Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg Format_BIN: Binary data format + * @arg Format_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format) +{ + uint32_t tmpreg = 0, subsecondtmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + assert_param(IS_ALARM(Alarm)); + + sAlarm->Alarm = RTC_ALARM_A; + + tmpreg = (uint32_t)(hrtc->Instance->ALRMAR); + subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR ) & RTC_ALRMASSR_SS); + + /* Fill the structure with the read parameters */ + sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16); + sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8); + sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU)); + sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16); + sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg; + sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24); + sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); + sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL); + + if(Format == FORMAT_BIN) + { + sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours); + sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes); + sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds); + sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); + } + + return HAL_OK; +} + +/** + * @brief This function handles Alarm interrupt request. + * @param hrtc: RTC handle + * @retval None + */ +void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc) +{ + if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRA)) + { + /* Get the status of the Interrupt */ + if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRA) != (uint32_t)RESET) + { + /* AlarmA callback */ + HAL_RTC_AlarmAEventCallback(hrtc); + + /* Clear the Alarm interrupt pending bit */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRAF); + } + } + + /* Clear the EXTI's line Flag for RTC Alarm */ + __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; +} + +/** + * @brief Alarm A callback. + * @param hrtc: RTC handle + * @retval None + */ +__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RTC_AlarmAEventCallback could be implemented in the user file + */ +} + +/** + * @brief This function handles AlarmA Polling request. + * @param hrtc: RTC handle + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + uint32_t tickstart = 0; + + /* Get Timeout value */ + tickstart = HAL_GetTick(); + + while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + } + + /* Clear the Alarm interrupt pending bit */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Wait for RTC Time and Date Synchronization + +@endverbatim + * @{ + */ + +/** + * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are + * synchronized with RTC APB clock. + * @note The RTC Resynchronization mode is write protected, use the + * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. + * @note To read the calendar through the shadow registers after Calendar + * initialization, calendar update or after wakeup from low power modes + * the software must first clear the RSF flag. + * The software must then wait until it is set again before reading + * the calendar, which means that the calendar registers have been + * correctly copied into the RTC_TR and RTC_DR shadow registers. + * @param hrtc: RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc) +{ + uint32_t tickstart = 0; + + /* Clear RSF flag */ + hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK; + + tickstart = HAL_GetTick(); + + /* Wait the registers to be synchronised */ + while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET) + { + if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Get RTC state + +@endverbatim + * @{ + */ +/** + * @brief Returns the Alarm state. + * @param hrtc: RTC handle + * @retval HAL state + */ +HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc) +{ + return hrtc->State; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup RTC_Private_Functions RTC Private Functions + * @{ + */ + +/** + * @brief Enters the RTC Initialization mode. + * @note The RTC Initialization mode is write protected, use the + * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. + * @param hrtc: RTC handle + * @retval An ErrorStatus enumeration value: + * - HAL_OK : RTC is in Init mode + * - HAL_TIMEOUT : RTC is not in Init mode and in Timeout + */ +HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc) +{ + uint32_t tickstart = 0; + + /* Check if the Initialization mode is set */ + if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) + { + /* Set the Initialization mode */ + hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK; + + tickstart = HAL_GetTick(); + + /* Wait till RTC is in INIT state and if Time out is reached exit */ + while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) + { + if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + return HAL_OK; +} + + +/** + * @brief Converts a 2 digit decimal to BCD format. + * @param Value: Byte to be converted + * @retval Converted byte + */ +uint8_t RTC_ByteToBcd2(uint8_t Value) +{ + uint32_t bcdhigh = 0; + + while(Value >= 10) + { + bcdhigh++; + Value -= 10; + } + + return ((uint8_t)(bcdhigh << 4) | Value); +} + +/** + * @brief Converts from 2 digit BCD to Binary. + * @param Value: BCD value to be converted + * @retval Converted word + */ +uint8_t RTC_Bcd2ToByte(uint8_t Value) +{ + uint32_t tmp = 0; + tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; + return (tmp + (Value & (uint8_t)0x0F)); +} + +/** + * @} + */ + +#endif /* HAL_RTC_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rtc_ex.c b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rtc_ex.c new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rtc_ex.c @@ -0,0 +1,1540 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_rtc_ex.c + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Extended RTC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Real Time Clock (RTC) Extension peripheral: + * + TimeStamp configuration + * + Tampers configuration + * + WakeUp Timer configuration + * + RTC Tamper and TimeStamp Pins Selection + * + Extension Control functions + * + Extension RTC features functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (+) Enable the RTC domain access (see description in the section above). + (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour + format using the HAL_RTC_Init() function. + + *** RTC Wakeup configuration *** + ================================ + [..] + (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer() + function. You can also configure the RTC Wakeup timer with interrupt mode + using the HAL_RTCEx_SetWakeUpTimer_IT() function. + (+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer() + function. + + *** TimeStamp configuration *** + =============================== + [..] + (+) Configure the RTC_AF trigger and enables the RTC TimeStamp using the + HAL_RTCEx_SetTimeStamp() function. You can also configure the RTC TimeStamp with + interrupt mode using the HAL_RTCEx_SetTimeStamp_IT() function. + (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp() + function. + + *** Tamper configuration *** + ============================ + [..] + (+) Enable the RTC Tamper and Configure the Tamper filter count, trigger Edge + or Level according to the Tamper filter (if equal to 0 Edge else Level) + value, sampling frequency, precharge or discharge and Pull-UP using the + HAL_RTCEx_SetTamper() function. You can configure RTC Tamper with interrupt + mode using HAL_RTCEx_SetTamper_IT() function. + + *** Backup Data Registers configuration *** + =========================================== + [..] + (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite() + function. + (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead() + function. + + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup RTCEx RTCEx Extended HAL module driver + * @brief RTCEx Extended HAL module driver + * @{ + */ + +#ifdef HAL_RTC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions + * @{ + */ + + +/** @defgroup RTCEx_Exported_Functions_Group1 RTC TimeStamp and Tamper functions + * @brief RTC TimeStamp and Tamper functions + * +@verbatim + =============================================================================== + ##### RTC TimeStamp and Tamper functions ##### + =============================================================================== + + [..] This section provide functions allowing to configure TimeStamp feature + +@endverbatim + * @{ + */ + +/** + * @brief Sets TimeStamp. + * @note This API must be called before enabling the TimeStamp feature. + * @param hrtc: RTC handle + * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is + * activated. + * This parameter can be one of the following: + * @arg TimeStampEdge_Rising: the Time stamp event occurs on the + * rising edge of the related pin. + * @arg TimeStampEdge_Falling: the Time stamp event occurs on the + * falling edge of the related pin. + * @param RTC_TimeStampPin: specifies the RTC TimeStamp Pin. + * This parameter can be one of the following values: + * @arg RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge)); + assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Get the RTC_CR register and clear the bits to be configured */ + tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); + + tmpreg|= TimeStampEdge; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Configure the Time Stamp TSEDGE and Enable bits */ + hrtc->Instance->CR = (uint32_t)tmpreg; + + __HAL_RTC_TIMESTAMP_ENABLE(hrtc); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Sets TimeStamp with Interrupt. + * @param hrtc: RTC handle + * @note This API must be called before enabling the TimeStamp feature. + * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is + * activated. + * This parameter can be one of the following: + * @arg TimeStampEdge_Rising: the Time stamp event occurs on the + * rising edge of the related pin. + * @arg TimeStampEdge_Falling: the Time stamp event occurs on the + * falling edge of the related pin. + * @param RTC_TimeStampPin: Specifies the RTC TimeStamp Pin. + * This parameter can be one of the following values: + * @arg RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge)); + assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Get the RTC_CR register and clear the bits to be configured */ + tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); + + tmpreg |= TimeStampEdge; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Configure the Time Stamp TSEDGE and Enable bits */ + hrtc->Instance->CR = (uint32_t)tmpreg; + + __HAL_RTC_TIMESTAMP_ENABLE(hrtc); + + /* Enable IT timestamp */ + __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS); + + /* RTC timestamp Interrupt Configuration: EXTI configuration */ + __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT); + + EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT; + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Deactivates TimeStamp. + * @param hrtc: RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) +{ + uint32_t tmpreg = 0; + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* In case of interrupt mode is used, the interrupt source must disabled */ + __HAL_RTC_TIMESTAMP_DISABLE_IT(hrtc, RTC_IT_TS); + + /* Get the RTC_CR register and clear the bits to be configured */ + tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); + + /* Configure the Time Stamp TSEDGE and Enable bits */ + hrtc->Instance->CR = (uint32_t)tmpreg; + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Gets the RTC TimeStamp value. + * @param hrtc: RTC handle + * @param sTimeStamp: Pointer to Time structure + * @param sTimeStampDate: Pointer to Date structure + * @param Format: specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg Format_BIN: Binary data format + * @arg Format_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format) +{ + uint32_t tmptime = 0, tmpdate = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Get the TimeStamp time and date registers values */ + tmptime = (uint32_t)(hrtc->Instance->TSTR & RTC_TR_RESERVED_MASK); + tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK); + + /* Fill the Time structure fields with the read parameters */ + sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16); + sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8); + sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU)); + sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16); + sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR; + + /* Fill the Date structure fields with the read parameters */ + sTimeStampDate->Year = 0; + sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8); + sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU)); + sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13); + + /* Check the input parameters format */ + if(Format == FORMAT_BIN) + { + /* Convert the TimeStamp structure parameters to Binary format */ + sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours); + sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes); + sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds); + + /* Convert the DateTimeStamp structure parameters to Binary format */ + sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month); + sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date); + sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay); + } + + /* Clear the TIMESTAMP Flag */ + __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF); + + return HAL_OK; +} + +/** + * @brief Sets Tamper + * @note By calling this API we disable the tamper interrupt for all tampers. + * @param hrtc: RTC handle + * @param sTamper: Pointer to Tamper Structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_TAMPER(sTamper->Tamper)); + assert_param(IS_TAMPER_TRIGGER(sTamper->Trigger)); + assert_param(IS_TAMPER_FILTER(sTamper->Filter)); + assert_param(IS_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); + assert_param(IS_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); + assert_param(IS_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); + assert_param(IS_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE) + { + sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1); + } + + tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->Filter |\ + (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration |\ + (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection); + + hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAFCR_TAMPTS |\ + (uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH |\ + (uint32_t)RTC_TAFCR_TAMPPUDIS | (uint32_t)RTC_TAFCR_TAMPIE); + + hrtc->Instance->TAFCR |= tmpreg; + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Sets Tamper with interrupt. + * @note By calling this API we force the tamper interrupt for all tampers. + * @param hrtc: RTC handle + * @param sTamper: Pointer to RTC Tamper. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_TAMPER(sTamper->Tamper)); + assert_param(IS_TAMPER_TRIGGER(sTamper->Trigger)); + assert_param(IS_TAMPER_FILTER(sTamper->Filter)); + assert_param(IS_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); + assert_param(IS_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); + assert_param(IS_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); + assert_param(IS_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Configure the tamper trigger */ + if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE) + { + sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1); + } + + tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->Filter |\ + (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration |\ + (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection); + + hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAFCR_TAMPTS |\ + (uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH |\ + (uint32_t)RTC_TAFCR_TAMPPUDIS); + + hrtc->Instance->TAFCR |= tmpreg; + + /* Configure the Tamper Interrupt in the RTC_TAFCR */ + hrtc->Instance->TAFCR |= (uint32_t)RTC_TAFCR_TAMPIE; + + /* RTC Tamper Interrupt Configuration: EXTI configuration */ + __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT); + + EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT; + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Deactivates Tamper. + * @param hrtc: RTC handle + * @param Tamper: Selected tamper pin. + * This parameter can be any combination of RTC_TAMPER_1, RTC_TAMPER_2 and RTC_TAMPER_3. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper) +{ + assert_param(IS_TAMPER(Tamper)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the selected Tamper pin */ + hrtc->Instance->TAFCR &= (uint32_t)~Tamper; + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief This function handles TimeStamp interrupt request. + * @param hrtc: RTC handle + * @retval None + */ +void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) +{ + if(__HAL_RTC_TIMESTAMP_GET_IT(hrtc, RTC_IT_TS)) + { + /* Get the status of the Interrupt */ + if((uint32_t)(hrtc->Instance->CR & RTC_IT_TS) != (uint32_t)RESET) + { + /* TIMESTAMP callback */ + HAL_RTCEx_TimeStampEventCallback(hrtc); + + /* Clear the TIMESTAMP interrupt pending bit */ + __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc,RTC_FLAG_TSF); + } + } + + /* Get the status of the Interrupt */ + if(__HAL_RTC_TAMPER_GET_IT(hrtc,RTC_IT_TAMP1)) + { + /* Get the TAMPER Interrupt enable bit and pending bit */ + if(((hrtc->Instance->TAFCR & (RTC_TAFCR_TAMPIE))) != (uint32_t)RESET) + { + /* Tamper callback */ + HAL_RTCEx_Tamper1EventCallback(hrtc); + + /* Clear the Tamper interrupt pending bit */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F); + } + } + + /* Get the status of the Interrupt */ + if(__HAL_RTC_TAMPER_GET_IT(hrtc, RTC_IT_TAMP2)) + { + /* Get the TAMPER Interrupt enable bit and pending bit */ + if(((hrtc->Instance->TAFCR & RTC_TAFCR_TAMPIE)) != (uint32_t)RESET) + { + /* Tamper callback */ + HAL_RTCEx_Tamper2EventCallback(hrtc); + + /* Clear the Tamper interrupt pending bit */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F); + } + } + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) + /* Get the status of the Interrupt */ + if(__HAL_RTC_TAMPER_GET_IT(hrtc, RTC_IT_TAMP3)) + { + /* Get the TAMPER Interrupt enable bit and pending bit */ + if(((hrtc->Instance->TAFCR & RTC_TAFCR_TAMPIE)) != (uint32_t)RESET) + { + /* Tamper callback */ + HAL_RTCEx_Tamper3EventCallback(hrtc); + + /* Clear the Tamper interrupt pending bit */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F); + } + } +#endif + + /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */ + __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; +} + +/** + * @brief TimeStamp callback. + * @param hrtc: RTC handle + * @retval None + */ +__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file + */ +} + +/** + * @brief Tamper 1 callback. + * @param hrtc: RTC handle + * @retval None + */ +__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file + */ +} + +/** + * @brief Tamper 2 callback. + * @param hrtc: RTC handle + * @retval None + */ +__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file + */ +} + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) +/** + * @brief Tamper 3 callback. + * @param hrtc: RTC handle + * @retval None + */ +__weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file + */ +} +#endif + +/** + * @brief This function handles TimeStamp polling request. + * @param hrtc: RTC handle + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + uint32_t tickstart = 0; + + /* Get Timeout value */ + tickstart = HAL_GetTick(); + + while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET) + { + if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET) + { + /* Clear the TIMESTAMP OverRun Flag */ + __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF); + + /* Change TIMESTAMP state */ + hrtc->State = HAL_RTC_STATE_ERROR; + + return HAL_ERROR; + } + + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + } + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + return HAL_OK; +} + +/** + * @brief This function handles Tamper1 Polling. + * @param hrtc: RTC handle + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + uint32_t tickstart = 0; + + /* Get Timeout value */ + tickstart = HAL_GetTick(); + + /* Get the status of the Interrupt */ + while(__HAL_RTC_TAMPER_GET_FLAG(hrtc,RTC_FLAG_TAMP1F)== RESET) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + } + + /* Clear the Tamper Flag */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + return HAL_OK; +} + +/** + * @brief This function handles Tamper2 Polling. + * @param hrtc: RTC handle + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + uint32_t tickstart = 0; + + /* Get Timeout value */ + tickstart = HAL_GetTick(); + + /* Get the status of the Interrupt */ + while(__HAL_RTC_TAMPER_GET_FLAG(hrtc,RTC_FLAG_TAMP2F) == RESET) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + } + + /* Clear the Tamper Flag */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP2F); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + return HAL_OK; +} + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) +/** + * @brief This function handles Tamper3 Polling. + * @param hrtc: RTC handle + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + uint32_t tickstart = 0; + + /* Get Timeout value */ + tickstart = HAL_GetTick(); + + /* Get the status of the Interrupt */ + while(__HAL_RTC_TAMPER_GET_FLAG(hrtc,RTC_FLAG_TAMP3F) == RESET) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + } + + /* Clear the Tamper Flag */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP3F); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + return HAL_OK; +} +#endif + +/** + * @} + */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) +/** @defgroup RTCEx_Exported_Functions_Group2 RTC Wake-up functions + * @brief RTC Wake-up functions + * +@verbatim + =============================================================================== + ##### RTC Wake-up functions ##### + =============================================================================== + + [..] This section provide functions allowing to configure Wake-up feature + +@endverbatim + * @{ + */ + +/** + * @brief Sets wake up timer. + * @param hrtc: RTC handle + * @param WakeUpCounter: Wake up counter + * @param WakeUpClock: Wake up clock + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) +{ + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param(IS_WAKEUP_CLOCK(WakeUpClock)); + assert_param(IS_WAKEUP_COUNTER(WakeUpCounter)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); + + tickstart = HAL_GetTick(); + + /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ + while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) + { + if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + + /* Clear the Wakeup Timer clock source bits in CR register */ + hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL; + + /* Configure the clock source */ + hrtc->Instance->CR |= (uint32_t)WakeUpClock; + + /* Configure the Wakeup Timer counter */ + hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; + + /* Enable the Wakeup Timer */ + __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Sets wake up timer with interrupt + * @param hrtc: RTC handle + * @param WakeUpCounter: wake up counter + * @param WakeUpClock: wake up clock + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) +{ + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param(IS_WAKEUP_CLOCK(WakeUpClock)); + assert_param(IS_WAKEUP_COUNTER(WakeUpCounter)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); + + tickstart = HAL_GetTick(); + + /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ + while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) + { + if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + + /* Configure the Wakeup Timer counter */ + hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; + + /* Clear the Wakeup Timer clock source bits in CR register */ + hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL; + + /* Configure the clock source */ + hrtc->Instance->CR |= (uint32_t)WakeUpClock; + + /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */ + __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_WAKEUPTIMER_EVENT); + + EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT; + + /* Configure the Interrupt in the RTC_CR register */ + __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT); + + /* Enable the Wakeup Timer */ + __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Deactivates wake up timer counter. + * @param hrtc: RTC handle + * @retval HAL status + */ +uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) +{ + uint32_t tickstart = 0; + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Disable the Wakeup Timer */ + __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); + + /* In case of interrupt mode is used, the interrupt source must disabled */ + __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT); + + tickstart = HAL_GetTick(); + + /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ + while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) + { + if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Gets wake up timer counter. + * @param hrtc: RTC handle + * @retval Counter value + */ +uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc) +{ + /* Get the counter value */ + return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT)); +} + +/** + * @brief This function handles Wake Up Timer interrupt request. + * @param hrtc: RTC handle + * @retval None + */ +void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) +{ + if(__HAL_RTC_WAKEUPTIMER_GET_IT(hrtc, RTC_IT_WUT)) + { + /* Get the status of the Interrupt */ + if((uint32_t)(hrtc->Instance->CR & RTC_IT_WUT) != (uint32_t)RESET) + { + /* WAKEUPTIMER callback */ + HAL_RTCEx_WakeUpTimerEventCallback(hrtc); + + /* Clear the WAKEUPTIMER interrupt pending bit */ + __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); + } + } + + /* Clear the EXTI's line Flag for RTC WakeUpTimer */ + __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_WAKEUPTIMER_EVENT); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; +} + +/** + * @brief Wake Up Timer callback. + * @param hrtc: RTC handle + * @retval None + */ +__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file + */ +} + +/** + * @brief This function handles Wake Up Timer Polling. + * @param hrtc: RTC handle + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + uint32_t tickstart = 0; + + /* Get Timeout value */ + tickstart = HAL_GetTick(); + + while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + return HAL_TIMEOUT; + } + } + } + + /* Clear the WAKEUPTIMER Flag */ + __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + return HAL_OK; +} + +/** + * @} + */ +#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */ + +/** @defgroup RTCEx_Exported_Functions_Group3 Extension Peripheral Control functions + * @brief Extension Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extension Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Writes a data in a specified RTC Backup data register + (+) Read a data in a specified RTC Backup data register + (+) Sets the Coarse calibration parameters. + (+) Deactivates the Coarse calibration parameters + (+) Sets the Smooth calibration parameters. + (+) Configures the Synchronization Shift Control Settings. + (+) Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + (+) Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + (+) Enables the RTC reference clock detection. + (+) Disable the RTC reference clock detection. + (+) Enables the Bypass Shadow feature. + (+) Disables the Bypass Shadow feature. + +@endverbatim + * @{ + */ + +#if !defined(STM32F030x6) && !defined(STM32F030x8) +/** + * @brief Writes a data in a specified RTC Backup data register. + * @param hrtc: RTC handle + * @param BackupRegister: RTC Backup data Register number. + * This parameter can be: RTC_BKP_DRx where x can be from 0 to 4 to + * specify the register. + * @param Data: Data to be written in the specified RTC Backup data register. + * @retval None + */ +void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data) +{ + uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_RTC_BKP(BackupRegister)); + + tmp = (uint32_t)&(hrtc->Instance->BKP0R); + tmp += (BackupRegister * 4); + + /* Write the specified register */ + *(__IO uint32_t *)tmp = (uint32_t)Data; +} + +/** + * @brief Reads data from the specified RTC Backup data Register. + * @param hrtc: RTC handle + * @param BackupRegister: RTC Backup data Register number. + * This parameter can be: RTC_BKP_DRx where x can be from 0 to 4 to + * specify the register. + * @retval Read value + */ +uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) +{ + uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_RTC_BKP(BackupRegister)); + + tmp = (uint32_t)&(hrtc->Instance->BKP0R); + tmp += (BackupRegister * 4); + + /* Read the specified register */ + return (*(__IO uint32_t *)tmp); +} +#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */ + +/** + * @brief Sets the Smooth calibration parameters. + * @param hrtc: RTC handle + * @param SmoothCalibPeriod: Select the Smooth Calibration Period. + * This parameter can be can be one of the following values : + * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration periode is 32s. + * @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration periode is 16s. + * @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibartion periode is 8s. + * @param SmoothCalibPlusPulses: Select to Set or reset the CALP bit. + * This parameter can be one of the following values: + * @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK puls every 2*11 pulses. + * @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added. + * @param SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits. + * This parameter can be one any value from 0 to 0x000001FF. + * @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses + * must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field + * SmouthCalibMinusPulsesValue mut be equal to 0. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue) +{ + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod)); + assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses)); + assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmouthCalibMinusPulsesValue)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* check if a calibration is pending*/ + if((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET) + { + tickstart = HAL_GetTick(); + + /* check if a calibration is pending*/ + while((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET) + { + if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + } + + /* Configure the Smooth calibration settings */ + hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmouthCalibMinusPulsesValue); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Configures the Synchronization Shift Control Settings. + * @note When REFCKON is set, firmware must not write to Shift control register. + * @param hrtc: RTC handle + * @param ShiftAdd1S: Select to add or not 1 second to the time calendar. + * This parameter can be one of the following values : + * @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar. + * @arg RTC_SHIFTADD1S_RESET: No effect. + * @param ShiftSubFS: Select the number of Second Fractions to substitute. + * This parameter can be one any value from 0 to 0x7FFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS) +{ + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S)); + assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + tickstart = HAL_GetTick(); + + /* Wait until the shift is completed*/ + while((hrtc->Instance->ISR & RTC_ISR_SHPF) != RESET) + { + if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + + /* Check if the reference clock detection is disabled */ + if((hrtc->Instance->CR & RTC_CR_REFCKON) == RESET) + { + /* Configure the Shift settings */ + hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S); + + /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) + { + if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + } + } + else + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + * @param hrtc: RTC handle + * @param CalibOutput : Select the Calibration output Selection . + * This parameter can be one of the following values: + * @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz. + * @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32_t CalibOutput) +{ + /* Check the parameters */ + assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Clear flags before config */ + hrtc->Instance->CR &= (uint32_t)~RTC_CR_COSEL; + + /* Configure the RTC_CR register */ + hrtc->Instance->CR |= (uint32_t)CalibOutput; + + __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + * @param hrtc: RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(hrtc); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Enables the RTC reference clock detection. + * @param hrtc: RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Set Initialization mode */ + if(RTC_EnterInitMode(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Set RTC state*/ + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + else + { + __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc); + + /* Exit Initialization mode */ + hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Disable the RTC reference clock detection. + * @param hrtc: RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Set Initialization mode */ + if(RTC_EnterInitMode(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Set RTC state*/ + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + else + { + __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc); + + /* Exit Initialization mode */ + hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Enables the Bypass Shadow feature. + * @param hrtc: RTC handle + * @note When the Bypass Shadow is enabled the calendar value are taken + * directly from the Calendar counter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Set the BYPSHAD bit */ + hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD; + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Disables the Bypass Shadow feature. + * @param hrtc: RTC handle + * @note When the Bypass Shadow is enabled the calendar value are taken + * directly from the Calendar counter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Reset the BYPSHAD bit */ + hrtc->Instance->CR &= (uint8_t)~RTC_CR_BYPSHAD; + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_RTC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_smartcard.c b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_smartcard.c new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_smartcard.c @@ -0,0 +1,1429 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_smartcard.c + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief SMARTCARD HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the SMARTCARD peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and Errors functions + * + Peripheral Control functions + * + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The SMARTCARD HAL driver can be used as follows: + + (#) Declare a SMARTCARD_HandleTypeDef handle structure. + (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit ()API: + (++) Enable the USARTx interface clock. + (++) SMARTCARD pins configuration: + (+++) Enable the clock for the SMARTCARD GPIOs. + (+++) Configure these SMARTCARD pins as alternate function pull-up. + (++) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT() + and HAL_SMARTCARD_Receive_IT() APIs): + (+++) Configure the USARTx interrupt priority. + (+++) Enable the NVIC USART IRQ handle. + (++) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA() + and HAL_SMARTCARD_Receive_DMA() APIs): + (+++) Declare a DMA handle structure for the Tx/Rx channel. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx channel. + (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. + + (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly, + the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission + error enabling or disabling in the hsmartcard Init structure. + + (#) If required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, auto-retry counter,...) + in the hsmartcard AdvancedInit structure. + + (#) Initialize the SMARTCARD associated USART registers by calling the HAL_SMARTCARD_Init() API: + (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) by + calling the customed HAL_SMARTCARD_MspInit() API. + + -@@- The specific SMARTCARD interrupts (Transmission complete interrupt, + RXNE interrupt and Error Interrupts) will be managed using the macros + __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process. + + (#) Three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit() + (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive() + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Send an amount of data in non blocking mode using HAL_SMARTCARD_Transmit_IT() + (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback + (+) Receive an amount of data in non blocking mode using HAL_SMARTCARD_Receive_IT() + (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback + (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback + + *** DMA mode IO operation *** + ============================== + [..] + (+) Send an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA() + (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback + (+) Receive an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA() + (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback + (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback + + *** SMARTCARD HAL driver macros list *** + ======================================== + [..] + Below the list of most used macros in SMARTCARD HAL driver. + + (+) __HAL_SMARTCARD_ENABLE: Enable the SMARTCARD peripheral + (+) __HAL_SMARTCARD_DISABLE: Disable the SMARTCARD peripheral + (+) __HAL_SMARTCARD_GET_FLAG : Check whether the specified SMARTCARD flag is set or not + (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag + (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt + (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt + + [..] + (@) You can refer to the SMARTCARD HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup SMARTCARD SMARTCARD HAL module driver + * @brief HAL SMARTCARD module driver + * @{ + */ +#ifdef HAL_SMARTCARD_MODULE_ENABLED + +#if !defined(STM32F030x6) && !defined(STM32F030x8) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants + * @{ + */ +#define TEACK_REACK_TIMEOUT 1000 +#define SMARTCARD_TXDMA_TIMEOUTVALUE 22000 +#define SMARTCARD_TIMEOUT_VALUE 22000 +#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ + USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) +#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL)) +#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN|USART_CR2_CLK_FIELDS|USART_CR2_STOP)) +#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT|USART_CR3_NACK|USART_CR3_SCARCNT)) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup SMARTCARD_Private_Functions SMARTCARD Private Functions + * @{ + */ +static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard); +static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Timeout); +static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard); +static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard); +static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard); +static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard); +static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions + * @{ + */ + +/** @defgroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USART + in Smartcard mode. + [..] + The Smartcard interface is designed to support asynchronous protocol Smartcards as + defined in the ISO 7816-3 standard. + [..] + The USART can provide a clock to the smartcard through the SCLK output. + In smartcard mode, SCLK is not associated to the communication but is simply derived + from the internal peripheral input clock through a 5-bit prescaler. + [..] + (+) For the Smartcard mode only these parameters can be configured: + (++) Baud Rate + (++) Parity: parity should be enabled, + Frame Length is fixed to 8 bits plus parity: + the USART frame format is given in the following table: + +---------------------------------------------------------------+ + | M bit | PCE bit | USART frame | + |---------------------|-----------------------------------------| + | 1 | 1 | | SB | 8 bit data | PB | STB | | + +---------------------------------------------------------------+ + or + +---------------------------------------------------------------+ + | M1M0 bits | PCE bit | USART frame | + |-----------------------|---------------------------------------| + | 01 | 1 | | SB | 8 bit data | PB | STB | | + +---------------------------------------------------------------+ + + (++) Receiver/transmitter modes + (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters) + (++) Prescaler value + (++) Guard bit time + (++) NACK enabling or disabling on transmission error + + (+) The following advanced features can be configured as well: + (++) TX and/or RX pin level inversion + (++) data logical level inversion + (++) RX and TX pins swap + (++) RX overrun detection disabling + (++) DMA disabling on RX error + (++) MSB first on communication line + (++) Time out enabling (and if activated, timeout value) + (++) Block length + (++) Auto-retry counter + + [..] + The HAL_SMARTCARD_Init() API follow respectively the USART (a)synchronous configuration procedures + (details for the procedures are available in reference manual). + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the SMARTCARD mode according to the specified + * parameters in the SMARTCARD_InitTypeDef and creates the associated handle . + * @param hsmartcard: SMARTCARD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Check the SMARTCARD handle allocation */ + if(hsmartcard == NULL) + { + return HAL_ERROR; + } + + /* Check the USART associated to the SmartCard */ + assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance)); + + if(hsmartcard->State == HAL_SMARTCARD_STATE_RESET) + { + /* Init the low level hardware : GPIO, CLOCK */ + HAL_SMARTCARD_MspInit(hsmartcard); + } + + hsmartcard->State = HAL_SMARTCARD_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_SMARTCARD_DISABLE(hsmartcard); + + /* Set the SMARTCARD Communication parameters */ + if (SMARTCARD_SetConfig(hsmartcard) == HAL_ERROR) + { + return HAL_ERROR; + } + + if (hsmartcard->AdvancedInit.AdvFeatureInit != SMARTCARD_ADVFEATURE_NO_INIT) + { + SMARTCARD_AdvFeatureConfig(hsmartcard); + } + + /* In SmartCard mode, the following bits must be kept cleared: + - LINEN in the USART_CR2 register, + - HDSEL and IREN bits in the USART_CR3 register.*/ + hsmartcard->Instance->CR2 &= ~(USART_CR2_LINEN); + hsmartcard->Instance->CR3 &= ~(USART_CR3_HDSEL | USART_CR3_IREN); + + /* set the USART in SMARTCARD mode */ + hsmartcard->Instance->CR3 |= USART_CR3_SCEN; + + /* Enable the Peripheral */ + __HAL_SMARTCARD_ENABLE(hsmartcard); + + /* TEACK and/or REACK to check before moving hsmartcard->State to Ready */ + return (SMARTCARD_CheckIdleState(hsmartcard)); +} + + +/** + * @brief DeInitializes the SMARTCARD peripheral + * @param hsmartcard: SMARTCARD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Check the SMARTCARD handle allocation */ + if(hsmartcard == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance)); + + hsmartcard->State = HAL_SMARTCARD_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_SMARTCARD_DISABLE(hsmartcard); + + hsmartcard->Instance->CR1 = 0x0; + hsmartcard->Instance->CR2 = 0x0; + hsmartcard->Instance->CR3 = 0x0; + hsmartcard->Instance->RTOR = 0x0; + hsmartcard->Instance->GTPR = 0x0; + + /* DeInit the low level hardware */ + HAL_SMARTCARD_MspDeInit(hsmartcard); + + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + hsmartcard->State = HAL_SMARTCARD_STATE_RESET; + + /* Process Unlock */ + __HAL_UNLOCK(hsmartcard); + + return HAL_OK; +} + +/** + * @brief SMARTCARD MSP Init + * @param hsmartcard: SMARTCARD handle + * @retval None + */ + __weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMARTCARD_MspInit can be implemented in the user file + */ +} + +/** + * @brief SMARTCARD MSP DeInit + * @param hsmartcard: SMARTCARD handle + * @retval None + */ + __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMARTCARD_MspDeInit can be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions + * @brief SMARTCARD Transmit and Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the SMARTCARD data transfers. + + [..] + Smartcard is a single wire half duplex communication protocol. + The Smartcard interface is designed to support asynchronous protocol Smartcards as + defined in the ISO 7816-3 standard. The USART should be configured as: + - 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register + - 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register. + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode: The communication is performed using Interrupts + or DMA, These API s return the HAL status. + The end of the data processing will be indicated through the + dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks + will be executed respectivelly at the end of the transmit or Receive process + The HAL_SMARTCARD_ErrorCallback()user callback will be executed when a communication error is detected + + (#) Blocking mode API s are : + (++) HAL_SMARTCARD_Transmit() + (++) HAL_SMARTCARD_Receive() + + (#) Non Blocking mode API s with Interrupt are : + (++) HAL_SMARTCARD_Transmit_IT() + (++) HAL_SMARTCARD_Receive_IT() + (++) HAL_SMARTCARD_IRQHandler() + + (#) Non Blocking mode functions with DMA are : + (++) HAL_SMARTCARD_Transmit_DMA() + (++) HAL_SMARTCARD_Receive_DMA() + + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (++) HAL_SMARTCARD_TxCpltCallback() + (++) HAL_SMARTCARD_RxCpltCallback() + (++) HAL_SMARTCARD_ErrorCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Send an amount of data in blocking mode + * @param hsmartcard: SMARTCARD handle + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @param Timeout : Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX)) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hsmartcard); + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + /* Check if a non-blocking receive process is ongoing or not */ + if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX) + { + hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; + } + else + { + hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX; + } + + hsmartcard->TxXferSize = Size; + hsmartcard->TxXferCount = Size; + while(hsmartcard->TxXferCount > 0) + { + hsmartcard->TxXferCount--; + if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + hsmartcard->Instance->TDR = (*pData++ & (uint8_t)0xFF); + } + if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TC, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + /* Check if a non-blocking receive Process is ongoing or not */ + if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) + { + hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX; + } + else + { + hsmartcard->State = HAL_SMARTCARD_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in blocking mode + * @param hsmartcard: SMARTCARD handle + * @param pData: pointer to data buffer + * @param Size: amount of data to be received + * @param Timeout : Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX)) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hsmartcard); + + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + /* Check if a non-blocking transmit process is ongoing or not */ + if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX) + { + hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; + } + else + { + hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX; + } + + hsmartcard->RxXferSize = Size; + hsmartcard->RxXferCount = Size; + /* Check the remain data to be received */ + while(hsmartcard->RxXferCount > 0) + { + hsmartcard->RxXferCount--; + if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + *pData++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0x00FF); + } + + /* Check if a non-blocking transmit Process is ongoing or not */ + if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) + { + hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX; + } + else + { + hsmartcard->State = HAL_SMARTCARD_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Send an amount of data in interrupt mode + * @param hsmartcard: SMARTCARD handle + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size) +{ + if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX)) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hsmartcard); + + hsmartcard->pTxBuffPtr = pData; + hsmartcard->TxXferSize = Size; + hsmartcard->TxXferCount = Size; + + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + /* Check if a receive process is ongoing or not */ + if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX) + { + hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; + } + else + { + hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX; + } + + /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_ERR); + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + /* Enable the SMARTCARD Transmit Data Register Empty Interrupt */ + __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_TXE); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in interrupt mode + * @param hsmartcard: SMARTCARD handle + * @param pData: pointer to data buffer + * @param Size: amount of data to be received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size) +{ + if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX)) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hsmartcard); + + hsmartcard->pRxBuffPtr = pData; + hsmartcard->RxXferSize = Size; + hsmartcard->RxXferCount = Size; + + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + /* Check if a transmit process is ongoing or not */ + if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX) + { + hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; + } + else + { + hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX; + } + + /* Enable the SMARTCARD Parity Error Interrupt */ + __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_PE); + + /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_ERR); + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + /* Enable the SMARTCARD Data Register not empty Interrupt */ + __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_RXNE); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Send an amount of data in DMA mode + * @param hsmartcard: SMARTCARD handle + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size) +{ + uint32_t *tmp; + + if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX)) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hsmartcard); + + hsmartcard->pTxBuffPtr = pData; + hsmartcard->TxXferSize = Size; + hsmartcard->TxXferCount = Size; + + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + /* Check if a receive process is ongoing or not */ + if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX) + { + hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; + } + else + { + hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX; + } + + /* Set the SMARTCARD DMA transfer complete callback */ + hsmartcard->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt; + + /* Set the SMARTCARD error callback */ + hsmartcard->hdmatx->XferErrorCallback = SMARTCARD_DMAError; + + /* Enable the SMARTCARD transmit DMA channel */ + tmp = (uint32_t*)&pData; + HAL_DMA_Start_IT(hsmartcard->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsmartcard->Instance->TDR, Size); + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the SMARTCARD associated USART CR3 register */ + hsmartcard->Instance->CR3 |= USART_CR3_DMAT; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in DMA mode + * @param hsmartcard: SMARTCARD handle + * @param pData: pointer to data buffer + * @param Size: amount of data to be received + * @note The SMARTCARD-associated USART parity is enabled (PCE = 1), + * the received data contain the parity bit (MSB position) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size) +{ + uint32_t *tmp; + + if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX)) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hsmartcard); + + hsmartcard->pRxBuffPtr = pData; + hsmartcard->RxXferSize = Size; + + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + /* Check if a transmit rocess is ongoing or not */ + if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX) + { + hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; + } + else + { + hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX; + } + + /* Set the SMARTCARD DMA transfer complete callback */ + hsmartcard->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt; + + /* Set the SMARTCARD DMA error callback */ + hsmartcard->hdmarx->XferErrorCallback = SMARTCARD_DMAError; + + /* Enable the DMA channel */ + tmp = (uint32_t*)&pData; + HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, *(uint32_t*)tmp, Size); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the SMARTCARD associated USART CR3 register */ + hsmartcard->Instance->CR3 |= USART_CR3_DMAR; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief SMARTCARD interrupt requests handling. + * @param hsmartcard: SMARTCARD handle + * @retval None + */ +void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* SMARTCARD parity error interrupt occurred -------------------------------------*/ + if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_PE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_PE) != RESET)) + { + __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_PEF); + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_PE; + /* Set the SMARTCARD state ready to be able to start again the process */ + hsmartcard->State = HAL_SMARTCARD_STATE_READY; + } + + /* SMARTCARD frame error interrupt occured --------------------------------------*/ + if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_FE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_ERR) != RESET)) + { + __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_FEF); + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_FE; + /* Set the SMARTCARD state ready to be able to start again the process */ + hsmartcard->State = HAL_SMARTCARD_STATE_READY; + } + + /* SMARTCARD noise error interrupt occured --------------------------------------*/ + if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_NE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_ERR) != RESET)) + { + __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_NEF); + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_NE; + /* Set the SMARTCARD state ready to be able to start again the process */ + hsmartcard->State = HAL_SMARTCARD_STATE_READY; + } + + /* SMARTCARD Over-Run interrupt occured -----------------------------------------*/ + if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_ORE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_ERR) != RESET)) + { + __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_OREF); + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_ORE; + /* Set the SMARTCARD state ready to be able to start again the process */ + hsmartcard->State = HAL_SMARTCARD_STATE_READY; + } + + /* SMARTCARD receiver timeout interrupt occured -----------------------------------------*/ + if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_RTO) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_RTO) != RESET)) + { + __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_RTOF); + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_RTO; + /* Set the SMARTCARD state ready to be able to start again the process */ + hsmartcard->State = HAL_SMARTCARD_STATE_READY; + } + + /* Call SMARTCARD Error Call back function if need be --------------------------*/ + if(hsmartcard->ErrorCode != HAL_SMARTCARD_ERROR_NONE) + { + HAL_SMARTCARD_ErrorCallback(hsmartcard); + } + + /* SMARTCARD in mode Receiver ---------------------------------------------------*/ + if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_RXNE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_RXNE) != RESET)) + { + SMARTCARD_Receive_IT(hsmartcard); + /* Clear RXNE interrupt flag */ + __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST); + } + + /* SMARTCARD in mode Receiver, end of block interruption ------------------------*/ + if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_EOB) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_EOB) != RESET)) + { + hsmartcard->State = HAL_SMARTCARD_STATE_READY; + __HAL_UNLOCK(hsmartcard); + HAL_SMARTCARD_RxCpltCallback(hsmartcard); + /* Clear EOBF interrupt after HAL_SMARTCARD_RxCpltCallback() call for the End of Block information + * to be available during HAL_SMARTCARD_RxCpltCallback() processing */ + __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_EOBF); + } + + /* SMARTCARD in mode Transmitter ------------------------------------------------*/ + if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_TXE) != RESET) &&(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_TXE) != RESET)) + { + SMARTCARD_Transmit_IT(hsmartcard); + } + + /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/ + if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_TC) != RESET) &&(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_TC) != RESET)) + { + SMARTCARD_EndTransmit_IT(hsmartcard); + } +} + +/** + * @brief Tx Transfer completed callbacks + * @param hsmartcard: SMARTCARD handle + * @retval None + */ + __weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks + * @param hsmartcard: SMARTCARD handle + * @retval None + */ +__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief SMARTCARD error callbacks + * @param hsmartcard: SMARTCARD handle + * @retval None + */ + __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMARTCARD_ErrorCallback can be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief SMARTCARD State and Errors functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Errors functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to return the State of SmartCard + communication process and also return Peripheral Errors occurred during communication process + (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state of the SMARTCARD peripheral + (+) HAL_SMARTCARD_GetError() check in run-time errors that could be occurred during + communication. + + (+) SMARTCARD_SetConfig() API configures the SMARTCARD peripheral + (+) SMARTCARD_AdvFeatureConfig() API optionally configures the SMARTCARD advanced features + (+) SMARTCARD_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization +@endverbatim + * @{ + */ + +/** + * @brief return the SMARTCARD state + * @param hsmartcard: SMARTCARD handle + * @retval HAL state + */ +HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard) +{ + return hsmartcard->State; +} + +/** +* @brief Return the SMARTCARD error code +* @param hsmartcard : pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD. +* @retval SMARTCARD Error Code +*/ +uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard) +{ + return hsmartcard->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions + * @{ + */ + +/** + * @brief This function handles SMARTCARD Communication Timeout. + * @param hsmartcard: SMARTCARD handle + * @param Flag: specifies the SMARTCARD flag to check. + * @param Status: The new Flag status (SET or RESET). + * @param Timeout: Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + + /* Wait until flag is set */ + if(Status == RESET) + { + while(__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) == RESET) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TXE); + __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_RXNE); + __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_PE); + __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR); + + hsmartcard->State= HAL_SMARTCARD_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + return HAL_TIMEOUT; + } + } + } + } + else + { + while(__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) != RESET) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TXE); + __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_RXNE); + __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_PE); + __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR); + + hsmartcard->State= HAL_SMARTCARD_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + return HAL_TIMEOUT; + } + } + } + } + return HAL_OK; +} + +/** + * @brief DMA SMARTCARD transmit process complete callback. + * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + SMARTCARD_HandleTypeDef* hsmartcard = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + hsmartcard->TxXferCount = 0; + + /* Disable the DMA transfer for transmit request by resetting the DMAT bit + in the SMARTCARD associated USART CR3 register */ + hsmartcard->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAT); + + /* Enable the SMARTCARD Transmit Complete Interrupt */ + __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_TC); +} + +/** + * @brief DMA SMARTCARD receive process complete callback. + * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SMARTCARD_HandleTypeDef* hsmartcard = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + hsmartcard->RxXferCount = 0; + + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the SMARTCARD associated USART CR3 register */ + hsmartcard->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAR); + + /* Check if a transmit Process is ongoing or not */ + if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) + { + hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX; + } + else + { + hsmartcard->State = HAL_SMARTCARD_STATE_READY; + } + + HAL_SMARTCARD_RxCpltCallback(hsmartcard); +} + +/** + * @brief DMA SMARTCARD communication error callback. + * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma) +{ + SMARTCARD_HandleTypeDef* hsmartcard = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + hsmartcard->RxXferCount = 0; + hsmartcard->TxXferCount = 0; + hsmartcard->State= HAL_SMARTCARD_STATE_READY; + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_DMA; + HAL_SMARTCARD_ErrorCallback(hsmartcard); +} + +/** + * @brief Send an amount of data in non blocking mode + * @param hsmartcard: SMARTCARD handle. + * Function called under interruption only, once + * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT() + * @retval HAL status + */ +static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard) +{ + if ((hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)) + { + + if(hsmartcard->TxXferCount == 0) + { + /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */ + __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TXE); + + /* Enable the SMARTCARD Transmit Complete Interrupt */ + __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_TC); + + return HAL_OK; + } + else + { + hsmartcard->Instance->TDR = (*hsmartcard->pTxBuffPtr++ & (uint8_t)0xFF); + hsmartcard->TxXferCount--; + + return HAL_OK; + } + } + else + { + return HAL_BUSY; + } +} + + +/** + * @brief Wraps up transmission in non blocking mode. + * @param hsmartcard: pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval HAL status + */ +static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Disable the SMARTCARD Transmit Complete Interrupt */ + __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TC); + + /* Check if a receive process is ongoing or not */ + if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) + { + hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX; + } + else + { + /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR); + + hsmartcard->State = HAL_SMARTCARD_STATE_READY; + } + + HAL_SMARTCARD_TxCpltCallback(hsmartcard); + + return HAL_OK; +} + + +/** + * @brief Receive an amount of data in non blocking mode + * @param hsmartcard: SMARTCARD handle. + * Function called under interruption only, once + * interruptions have been enabled by HAL_SMARTCARD_Receive_IT() + * @retval HAL status + */ +static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard) +{ + if ((hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)) + { + + *hsmartcard->pRxBuffPtr++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF); + + if(--hsmartcard->RxXferCount == 0) + { + __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_RXNE); + + /* Check if a transmit Process is ongoing or not */ + if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) + { + hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX; + } + else + { + /* Disable the SMARTCARD Parity Error Interrupt */ + __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_PE); + + /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR); + + hsmartcard->State = HAL_SMARTCARD_STATE_READY; + } + + HAL_SMARTCARD_RxCpltCallback(hsmartcard); + + return HAL_OK; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Configure the SMARTCARD associated USART peripheral + * @param hsmartcard: SMARTCARD handle + * @retval None + */ +static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard) +{ + uint32_t tmpreg = 0x00000000; + SMARTCARD_ClockSourceTypeDef clocksource = SMARTCARD_CLOCKSOURCE_UNDEFINED; + HAL_StatusTypeDef ret = HAL_OK; + + /* Check the parameters */ + assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance)); + assert_param(IS_SMARTCARD_BAUDRATE(hsmartcard->Init.BaudRate)); + assert_param(IS_SMARTCARD_WORD_LENGTH(hsmartcard->Init.WordLength)); + assert_param(IS_SMARTCARD_STOPBITS(hsmartcard->Init.StopBits)); + assert_param(IS_SMARTCARD_PARITY(hsmartcard->Init.Parity)); + assert_param(IS_SMARTCARD_MODE(hsmartcard->Init.Mode)); + assert_param(IS_SMARTCARD_POLARITY(hsmartcard->Init.CLKPolarity)); + assert_param(IS_SMARTCARD_PHASE(hsmartcard->Init.CLKPhase)); + assert_param(IS_SMARTCARD_LASTBIT(hsmartcard->Init.CLKLastBit)); + assert_param(IS_SMARTCARD_ONEBIT_SAMPLING(hsmartcard->Init.OneBitSampling)); + assert_param(IS_SMARTCARD_NACK(hsmartcard->Init.NACKEnable)); + assert_param(IS_SMARTCARD_TIMEOUT(hsmartcard->Init.TimeOutEnable)); + assert_param(IS_SMARTCARD_AUTORETRY_COUNT(hsmartcard->Init.AutoRetryCount)); + + /*-------------------------- USART CR1 Configuration -----------------------*/ + /* In SmartCard mode, M and PCE are forced to 1 (8 bits + parity). + * Oversampling is forced to 16 (OVER8 = 0). + * Configure the Parity and Mode: + * set PS bit according to hsmartcard->Init.Parity value + * set TE and RE bits according to hsmartcard->Init.Mode value */ + tmpreg = (uint32_t) hsmartcard->Init.Parity | hsmartcard->Init.Mode; + /* in case of TX-only mode, if NACK is enabled, the USART must be able to monitor + the bidirectional line to detect a NACK signal in case of parity error. + Therefore, the receiver block must be enabled as well (RE bit must be set). */ + if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) + && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLED)) + { + tmpreg |= USART_CR1_RE; + } + tmpreg |= (uint32_t) hsmartcard->Init.WordLength; + MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg); + + /*-------------------------- USART CR2 Configuration -----------------------*/ + /* Stop bits are forced to 1.5 (STOP = 11) */ + tmpreg = hsmartcard->Init.StopBits; + /* Synchronous mode is activated by default */ + tmpreg |= (uint32_t) USART_CR2_CLKEN | hsmartcard->Init.CLKPolarity; + tmpreg |= (uint32_t) hsmartcard->Init.CLKPhase | hsmartcard->Init.CLKLastBit; + tmpreg |= (uint32_t) hsmartcard->Init.TimeOutEnable; + MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_FIELDS, tmpreg); + + /*-------------------------- USART CR3 Configuration -----------------------*/ + /* Configure + * - one-bit sampling method versus three samples' majority rule + * according to hsmartcard->Init.OneBitSampling + * - NACK transmission in case of parity error according + * to hsmartcard->Init.NACKEnable + * - autoretry counter according to hsmartcard->Init.AutoRetryCount */ + tmpreg = (uint32_t) hsmartcard->Init.OneBitSampling | hsmartcard->Init.NACKEnable; + tmpreg |= ((uint32_t)hsmartcard->Init.AutoRetryCount << SMARTCARD_CR3_SCARCNT_LSB_POS); + MODIFY_REG(hsmartcard->Instance-> CR3,USART_CR3_FIELDS, tmpreg); + + /*-------------------------- USART GTPR Configuration ----------------------*/ + tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << SMARTCARD_GTPR_GT_LSB_POS)); + MODIFY_REG(hsmartcard->Instance->GTPR, (USART_GTPR_GT|USART_GTPR_PSC), tmpreg); + + /*-------------------------- USART RTOR Configuration ----------------------*/ + tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS); + if (hsmartcard->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLED) + { + assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue)); + tmpreg |= (uint32_t) hsmartcard->Init.TimeOutValue; + } + MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO|USART_RTOR_BLEN), tmpreg); + + /*-------------------------- USART BRR Configuration -----------------------*/ + __HAL_SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource); + switch (clocksource) + { + case SMARTCARD_CLOCKSOURCE_PCLK1: + hsmartcard->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK1Freq() / hsmartcard->Init.BaudRate); + break; + case SMARTCARD_CLOCKSOURCE_HSI: + hsmartcard->Instance->BRR = (uint16_t)(HSI_VALUE / hsmartcard->Init.BaudRate); + break; + case SMARTCARD_CLOCKSOURCE_SYSCLK: + hsmartcard->Instance->BRR = (uint16_t)(HAL_RCC_GetSysClockFreq() / hsmartcard->Init.BaudRate); + break; + case SMARTCARD_CLOCKSOURCE_LSE: + hsmartcard->Instance->BRR = (uint16_t)(LSE_VALUE / hsmartcard->Init.BaudRate); + break; + case SMARTCARD_CLOCKSOURCE_UNDEFINED: + default: + ret = HAL_ERROR; + break; + } + + return ret; +} + +/** + * @brief Check the SMARTCARD Idle State + * @param hsmartcard: SMARTCARD handle + * @retval HAL status + */ +static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard) +{ + + /* Initialize the SMARTCARD ErrorCode */ + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + + /* Check if the Transmitter is enabled */ + if((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + { + /* Wait until TEACK flag is set */ + if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, TEACK_REACK_TIMEOUT) != HAL_OK) + { + return HAL_TIMEOUT; + } + } + /* Check if the Receiver is enabled */ + if((hsmartcard->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + { + /* Wait until REACK flag is set */ + if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, TEACK_REACK_TIMEOUT) != HAL_OK) + { + return HAL_TIMEOUT; + } + } + + /* Initialize the SMARTCARD state*/ + hsmartcard->State= HAL_SMARTCARD_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + return HAL_OK; +} + +/** + * @brief Configure the SMARTCARD associated USART peripheral advanced feautures + * @param hsmartcard: SMARTCARD handle + * @retval None + */ +static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Check whether the set of advanced features to configure is properly set */ + assert_param(IS_SMARTCARD_ADVFEATURE_INIT(hsmartcard->AdvancedInit.AdvFeatureInit)); + + /* if required, configure TX pin active level inversion */ + if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXINVERT_INIT)) + { + assert_param(IS_SMARTCARD_ADVFEATURE_TXINV(hsmartcard->AdvancedInit.TxPinLevelInvert)); + MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_TXINV, hsmartcard->AdvancedInit.TxPinLevelInvert); + } + + /* if required, configure RX pin active level inversion */ + if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXINVERT_INIT)) + { + assert_param(IS_SMARTCARD_ADVFEATURE_RXINV(hsmartcard->AdvancedInit.RxPinLevelInvert)); + MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_RXINV, hsmartcard->AdvancedInit.RxPinLevelInvert); + } + + /* if required, configure data inversion */ + if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DATAINVERT_INIT)) + { + assert_param(IS_SMARTCARD_ADVFEATURE_DATAINV(hsmartcard->AdvancedInit.DataInvert)); + MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_DATAINV, hsmartcard->AdvancedInit.DataInvert); + } + + /* if required, configure RX/TX pins swap */ + if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_SWAP_INIT)) + { + assert_param(IS_SMARTCARD_ADVFEATURE_SWAP(hsmartcard->AdvancedInit.Swap)); + MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_SWAP, hsmartcard->AdvancedInit.Swap); + } + + /* if required, configure RX overrun detection disabling */ + if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT)) + { + assert_param(IS_SMARTCARD_OVERRUN(hsmartcard->AdvancedInit.OverrunDisable)); + MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_OVRDIS, hsmartcard->AdvancedInit.OverrunDisable); + } + + /* if required, configure DMA disabling on reception error */ + if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT)) + { + assert_param(IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(hsmartcard->AdvancedInit.DMADisableonRxError)); + MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_DDRE, hsmartcard->AdvancedInit.DMADisableonRxError); + } + + /* if required, configure MSB first on communication line */ + if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_MSBFIRST_INIT)) + { + assert_param(IS_SMARTCARD_ADVFEATURE_MSBFIRST(hsmartcard->AdvancedInit.MSBFirst)); + MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_MSBFIRST, hsmartcard->AdvancedInit.MSBFirst); + } +} + +/** + * @} + */ + +#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */ + +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_smartcard_ex.c b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_smartcard_ex.c new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_smartcard_ex.c @@ -0,0 +1,195 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_smartcard_ex.c + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief SMARTCARD HAL module driver. + * + * This file provides extended firmware functions to manage the following + * functionalities of the SmartCard. + * + Initialization and de-initialization function + * + Peripheral Control function + * + * + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The Extended SMARTCARD HAL driver can be used as follows: + + + (#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(), + then if required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, + auto-retry counter,...) in the hsmartcard AdvancedInit structure. + + + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup SMARTCARDEx SMARTCARD Extended HAL module driver + * @brief SMARTCARD Extended HAL module driver + * @{ + */ +#ifdef HAL_SMARTCARD_MODULE_ENABLED + +#if !defined(STM32F030x6) && !defined(STM32F030x8) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup SMARTCARDEx_Exported_Functions SMARTCARDEx Exported Functions + * @{ + */ + +/** @defgroup SMARTCARDEx_Exported_Functions_Group1 Extended Peripheral Control functions + * @brief Extended control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the SMARTCARD. + (+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly + (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly + (+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature + (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature + +@endverbatim + * @{ + */ + +/** + * @brief Update on the fly the SMARTCARD block length in RTOR register + * @param hsmartcard: SMARTCARD handle + * @param BlockLength: SMARTCARD block length (8-bit long at most) + * @retval None + */ +void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength) +{ + MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_BLEN, ((uint32_t)BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS)); +} + +/** + * @brief Update on the fly the receiver timeout value in RTOR register + * @param hsmartcard: SMARTCARD handle + * @param TimeOutValue: receiver timeout value in number of baud blocks. The timeout + * value must be less or equal to 0x0FFFFFFFF. + * @retval None + */ +void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue) +{ + assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue)); + MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_RTO, TimeOutValue); +} + +/** + * @brief Enable the SMARTCARD receiver timeout feature + * @param hsmartcard: SMARTCARD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard) +{ + + /* Process Locked */ + __HAL_LOCK(hsmartcard); + + hsmartcard->State = HAL_SMARTCARD_STATE_BUSY; + + /* Set the USART RTOEN bit */ + hsmartcard->Instance->CR2 |= USART_CR2_RTOEN; + + hsmartcard->State = HAL_SMARTCARD_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + return HAL_OK; +} + +/** + * @brief Disable the SMARTCARD receiver timeout feature + * @param hsmartcard: SMARTCARD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard) +{ + + /* Process Locked */ + __HAL_LOCK(hsmartcard); + + hsmartcard->State = HAL_SMARTCARD_STATE_BUSY; + + /* Clear the USART RTOEN bit */ + hsmartcard->Instance->CR2 &= ~(USART_CR2_RTOEN); + + hsmartcard->State = HAL_SMARTCARD_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */ + +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_smbus.c b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_smbus.c new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_smbus.c @@ -0,0 +1,1940 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_smbus.c + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief SMBUS HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the System Management Bus (SMBus) peripheral, + * based on I2C principales of operation : + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and Errors functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The SMBUS HAL driver can be used as follows: + + (#) Declare a SMBUS_HandleTypeDef handle structure, for example: + SMBUS_HandleTypeDef hsmbus; + + (#)Initialize the SMBUS low level resources by implement the HAL_SMBUS_MspInit ()API: + (##) Enable the SMBUSx interface clock + (##) SMBUS pins configuration + (+++) Enable the clock for the SMBUS GPIOs + (+++) Configure SMBUS pins as alternate function open-drain + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the SMBUSx interrupt priority + (+++) Enable the NVIC SMBUS IRQ Channel + + (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Adressing Mode, + Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode, + Peripheral mode and Packet Error Check mode in the hsmbus Init structure. + + (#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API: + (++) These API s configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + by calling the customed HAL_SMBUS_MspInit(&hsmbus) API. + + (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady() + + (#) For SMBUS IO operations, only one mode of operations is available within this driver : + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Transmit in master/host SMBUS mode an amount of data in non blocking mode using HAL_SMBUS_Master_Transmit_IT() + (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback + (+) Receive in master/host SMBUS mode an amount of data in non blocking mode using HAL_SMBUS_Master_Receive_IT() + (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback + (+) Abort a master/host SMBUS process commnunication with Interrupt using HAL_SMBUS_Master_Abort_IT() + (++) The associated previous transfer callback is called at the end of abort process + (++) mean HAL_SMBUS_MasterTxCpltCallback in case of previous state was master transmit + (++) mean HAL_SMBUS_MasterRxCpltCallback in case of previous state was master receive + (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode + using HAL_SMBUS_Slave_Listen_IT() HAL_SMBUS_DisableListen_IT() + (++) When address slave/device SMBUS match, HAL_SMBUS_SlaveAddrCallback is executed and user can + add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read). + (++) At Listen mode end HAL_SMBUS_SlaveListenCpltCallback is executed and user can + add his own code by customization of function pointer HAL_SMBUS_SlaveListenCpltCallback + (+) Transmit in slave/device SMBUS mode an amount of data in non blocking mode using HAL_SMBUS_Slave_Transmit_IT() + (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback + (+) Receive in slave/device SMBUS mode an amount of data in non blocking mode using HAL_SMBUS_Slave_Receive_IT() + (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback + (+) Enable/Disable the SMBUS alert mode using HAL_SMBUS_EnableAlert_IT() HAL_SMBUS_DisableAlert_IT() + (++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and user can + add his own code by customization of function pointer HAL_SMBUS_ErrorCallback + to check the Alert Error Code using function HAL_SMBUS_GetError() + (+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError() + (+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_SMBUS_ErrorCallback + to check the Error Code using function HAL_SMBUS_GetError() + + *** SMBUS HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in SMBUS HAL driver. + + (+) __HAL_SMBUS_ENABLE: Enable the SMBUS peripheral + (+) __HAL_SMBUS_DISABLE: Disable the SMBUS peripheral + (+) __HAL_SMBUS_GET_FLAG : Checks whether the specified SMBUS flag is set or not + (+) __HAL_SMBUS_CLEAR_FLAG : Clears the specified SMBUS pending flag + (+) __HAL_SMBUS_ENABLE_IT: Enables the specified SMBUS interrupt + (+) __HAL_SMBUS_DISABLE_IT: Disables the specified SMBUS interrupt + + [..] + (@) You can refer to the SMBUS HAL driver header file for more useful macros + + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup SMBUS SMBUS HAL module driver + * @brief SMBUS HAL module driver + * @{ + */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup SMBUS_Private_Define SMBUS Private Define + * @{ + */ +#define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /*Instance->ISR) +#define __SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK))) +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup SMBUS_Private_Functions SMBUS Private Functions + * @{ + */ +static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout); + +static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest); +static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest); +static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus); +static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus); + +static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup SMBUS_Exported_Functions SMBUS Exported Functions + * @{ + */ + +/** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + de-initialiaze the SMBUSx peripheral: + + (+) User must Implement HAL_SMBUS_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, IT and NVIC ). + + (+) Call the function HAL_SMBUS_Init() to configure the selected device with + the selected configuration: + (++) Clock Timing + (++) Bus Timeout + (++) Analog Filer mode + (++) Own Address 1 + (++) Addressing mode (Master, Slave) + (++) Dual Addressing mode + (++) Own Address 2 + (++) Own Address 2 Mask + (++) General call mode + (++) Nostretch mode + (++) Packet Error Check mode + (++) Peripheral mode + + + (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration + of the selected SMBUSx periperal. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the SMBUS according to the specified parameters + * in the SMBUS_InitTypeDef and create the associated handle. + * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) +{ + /* Check the SMBUS handle allocation */ + if(hsmbus == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); + assert_param(IS_SMBUS_ANALOG_FILTER(hsmbus->Init.AnalogFilter)); + assert_param(IS_SMBUS_OWN_ADDRESS1(hsmbus->Init.OwnAddress1)); + assert_param(IS_SMBUS_ADDRESSING_MODE(hsmbus->Init.AddressingMode)); + assert_param(IS_SMBUS_DUAL_ADDRESS(hsmbus->Init.DualAddressMode)); + assert_param(IS_SMBUS_OWN_ADDRESS2(hsmbus->Init.OwnAddress2)); + assert_param(IS_SMBUS_OWN_ADDRESS2_MASK(hsmbus->Init.OwnAddress2Masks)); + assert_param(IS_SMBUS_GENERAL_CALL(hsmbus->Init.GeneralCallMode)); + assert_param(IS_SMBUS_NO_STRETCH(hsmbus->Init.NoStretchMode)); + assert_param(IS_SMBUS_PEC(hsmbus->Init.PacketErrorCheckMode)); + assert_param(IS_SMBUS_PERIPHERAL_MODE(hsmbus->Init.PeripheralMode)); + + if(hsmbus->State == HAL_SMBUS_STATE_RESET) + { + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_SMBUS_MspInit(hsmbus); + } + + hsmbus->State = HAL_SMBUS_STATE_BUSY; + + /* Disable the selected SMBUS peripheral */ + __HAL_SMBUS_DISABLE(hsmbus); + + /*---------------------------- SMBUSx TIMINGR Configuration ------------------------*/ + /* Configure SMBUSx: Frequency range */ + hsmbus->Instance->TIMINGR = hsmbus->Init.Timing & TIMING_CLEAR_MASK; + + /*---------------------------- SMBUSx TIMEOUTR Configuration ------------------------*/ + /* Configure SMBUSx: Bus Timeout */ + hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TIMOUTEN; + hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TEXTEN; + hsmbus->Instance->TIMEOUTR = hsmbus->Init.SMBusTimeout; + + /*---------------------------- SMBUSx OAR1 Configuration -----------------------*/ + /* Configure SMBUSx: Own Address1 and ack own address1 mode */ + hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN; + + if(hsmbus->Init.OwnAddress1 != 0) + { + if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT) + { + hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | hsmbus->Init.OwnAddress1); + } + else /* SMBUS_ADDRESSINGMODE_10BIT */ + { + hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hsmbus->Init.OwnAddress1); + } + } + + /*---------------------------- SMBUSx CR2 Configuration ------------------------*/ + /* Configure SMBUSx: Addressing Master mode */ + if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_10BIT) + { + hsmbus->Instance->CR2 = (I2C_CR2_ADD10); + } + /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process) */ + /* AUTOEND and NACK bit will be manage during Transfer process */ + hsmbus->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); + + /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/ + /* Configure SMBUSx: Dual mode and Own Address2 */ + hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | (hsmbus->Init.OwnAddress2Masks << 8)); + + /*---------------------------- SMBUSx CR1 Configuration ------------------------*/ + /* Configure SMBUSx: Generalcall and NoStretch mode */ + hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | hsmbus->Init.AnalogFilter); + + /* Enable Slave Byte Control only in case of Packet Error Check is enabled and SMBUS Peripheral is set in Slave mode */ + if( (hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLED) + && ( (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP) ) ) + { + hsmbus->Instance->CR1 |= I2C_CR1_SBC; + } + + /* Enable the selected SMBUS peripheral */ + __HAL_SMBUS_ENABLE(hsmbus); + + hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; + hsmbus->PreviousState = HAL_SMBUS_STATE_READY; + hsmbus->State = HAL_SMBUS_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the SMBUS peripheral. + * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus) +{ + /* Check the SMBUS handle allocation */ + if(hsmbus == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); + + hsmbus->State = HAL_SMBUS_STATE_BUSY; + + /* Disable the SMBUS Peripheral Clock */ + __HAL_SMBUS_DISABLE(hsmbus); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_SMBUS_MspDeInit(hsmbus); + + hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; + hsmbus->PreviousState = HAL_SMBUS_STATE_RESET; + hsmbus->State = HAL_SMBUS_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hsmbus); + + return HAL_OK; +} + +/** + * @brief SMBUS MSP Init. + * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval None + */ + __weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SMBUS_MspInit could be implemented in the user file + */ +} + +/** + * @brief SMBUS MSP DeInit + * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval None + */ + __weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SMBUS_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup SMBUS_Exported_Functions_Group2 Input and Output operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the SMBUS data + transfers. + + (#) Blocking mode function to check if device is ready for usage is : + (++) HAL_SMBUS_IsDeviceReady() + + (#) There is only one mode of transfer: + (++) No-Blocking mode : The communication is performed using Interrupts. + These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated SMBUS IRQ when using Interrupt mode. + + (#) No-Blocking mode functions with Interrupt are : + (++) HAL_SMBUS_Master_Transmit_IT() + (++) HAL_SMBUS_Master_Receive_IT() + (++) HAL_SMBUS_Slave_Transmit_IT() + (++) HAL_SMBUS_Slave_Receive_IT() + (++) HAL_SMBUS_Slave_Listen_IT() or alias HAL_SMBUS_EnableListen_IT() + (++) HAL_SMBUS_DisableListen_IT() + (++) HAL_SMBUS_EnableAlert_IT() + (++) HAL_SMBUS_DisableAlert_IT() + + (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode: + (++) HAL_SMBUS_MasterTxCpltCallback() + (++) HAL_SMBUS_MasterRxCpltCallback() + (++) HAL_SMBUS_SlaveTxCpltCallback() + (++) HAL_SMBUS_SlaveRxCpltCallback() + (++) HAL_SMBUS_SlaveAddrCallback() or alias HAL_SMBUS_AddrCallback() + (++) HAL_SMBUS_SlaveListenCpltCallback() or alias HAL_SMBUS_ListenCpltCallback() + (++) HAL_SMBUS_ErrorCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Transmit in master/host SMBUS mode an amount of data in no-blocking mode with Interrupt + * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param DevAddress: Target device address + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @param XferOptions: Options of Transfer, value of @ref SMBUS_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if(hsmbus->State == HAL_SMBUS_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX; + hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; + /* Prepare transfer parameters */ + hsmbus->pBuffPtr = pData; + hsmbus->XferCount = Size; + hsmbus->XferOptions = XferOptions; + + /* In case of Quick command, remove autoend mode */ + /* Manage the stop generation by software */ + if(hsmbus->pBuffPtr == NULL) + { + hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE; + } + + if(Size > MAX_NBYTE_SIZE) + { + hsmbus->XferSize = MAX_NBYTE_SIZE; + } + else + { + hsmbus->XferSize = Size; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ + if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) ) + { + SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE); + } + else + { + /* If transfer direction not change, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) + { + SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + } + /* Else transfer direction change, so generate Restart with new transfer direction */ + else + { + SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE); + } + + /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */ + /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ + if(__HAL_SMBUS_GET_PEC_MODE(hsmbus) != RESET) + { + hsmbus->XferSize--; + hsmbus->XferCount--; + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Note : The SMBUS interrupts must be enabled after unlocking current process + to avoid the risk of SMBUS interrupt handle execution before current + process unlock */ + SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master/host SMBUS mode an amount of data in no-blocking mode with Interrupt + * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param DevAddress: Target device address + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @param XferOptions: Options of Transfer, value of @ref SMBUS_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if(hsmbus->State == HAL_SMBUS_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX; + hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; + + /* Prepare transfer parameters */ + hsmbus->pBuffPtr = pData; + hsmbus->XferCount = Size; + hsmbus->XferOptions = XferOptions; + + /* In case of Quick command, remove autoend mode */ + /* Manage the stop generation by software */ + if(hsmbus->pBuffPtr == NULL) + { + hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE; + } + + if(Size > MAX_NBYTE_SIZE) + { + hsmbus->XferSize = MAX_NBYTE_SIZE; + } + else + { + hsmbus->XferSize = Size; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ + if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) ) + { + SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ); + } + else + { + /* If transfer direction not change, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) + { + SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + } + /* Else transfer direction change, so generate Restart with new transfer direction */ + else + { + SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ); + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Note : The SMBUS interrupts must be enabled after unlocking current process + to avoid the risk of SMBUS interrupt handle execution before current + process unlock */ + SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Abort a master/host SMBUS process commnunication with Interrupt + * @note : This abort can be called only if state is ready + * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param DevAddress: Target device address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress) +{ + if(hsmbus->State == HAL_SMBUS_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsmbus); + + /* Keep the same state as previous */ + /* to perform as well the call of the corresponding end of transfer callback */ + if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) + { + hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX; + } + else if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) + { + hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX; + } + else + { + /* Wrong usage of abort function */ + /* This function should be used only in case of abort monitored by master device */ + return HAL_ERROR; + } + hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; + + /* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */ + /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ + SMBUS_TransferConfig(hsmbus, DevAddress, 1, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP); + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Note : The SMBUS interrupts must be enabled after unlocking current process + to avoid the risk of SMBUS interrupt handle execution before current + process unlock */ + if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) + { + SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX); + } + else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) + { + SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave/device SMBUS mode an amount of data in no-blocking mode with Interrupt + * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @param XferOptions: Options of Transfer, value of @ref SMBUS_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if(hsmbus->State == HAL_SMBUS_STATE_LISTEN) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_TX); + + /* Process Locked */ + __HAL_LOCK(hsmbus); + + hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_TX; + hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; + + /* Set SBC bit to manage Acknowledge at each bit */ + hsmbus->Instance->CR1 |= I2C_CR1_SBC; + + /* Enable Address Acknowledge */ + hsmbus->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hsmbus->pBuffPtr = pData; + hsmbus->XferSize = Size; + hsmbus->XferCount = Size; + hsmbus->XferOptions = XferOptions; + + if(Size > MAX_NBYTE_SIZE) + { + hsmbus->XferSize = MAX_NBYTE_SIZE; + } + else + { + hsmbus->XferSize = Size; + } + + /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ + if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) ) + { + SMBUS_TransferConfig(hsmbus,0,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); + } + else + { + /* Set NBYTE to transmit */ + SMBUS_TransferConfig(hsmbus,0,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + + /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ + /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ + if(__HAL_SMBUS_GET_PEC_MODE(hsmbus) != RESET) + { + hsmbus->XferSize--; + hsmbus->XferCount--; + } + } + + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the HOST */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Note : The SMBUS interrupts must be enabled after unlocking current process + to avoid the risk of SMBUS interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX | SMBUS_IT_ADDR); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Receive in slave/device SMBUS mode an amount of data in no-blocking mode with Interrupt + * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @param XferOptions: Options of Transfer, value of @ref SMBUS_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if(hsmbus->State == HAL_SMBUS_STATE_LISTEN) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_RX); + + /* Process Locked */ + __HAL_LOCK(hsmbus); + + hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_RX; + hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; + + /* Set SBC bit to manage Acknowledge at each bit */ + hsmbus->Instance->CR1 |= I2C_CR1_SBC; + + /* Enable Address Acknowledge */ + hsmbus->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hsmbus->pBuffPtr = pData; + hsmbus->XferSize = Size; + hsmbus->XferCount = Size; + hsmbus->XferOptions = XferOptions; + + /* Set NBYTE to receive */ + /* If XferSize equal "1", or XferSize equal "2" with PEC requested (mean 1 data byte + 1 PEC byte */ + /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */ + /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */ + /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */ + if((hsmbus->XferSize == 1) || ((hsmbus->XferSize == 2) && (__HAL_SMBUS_GET_PEC_MODE(hsmbus) != RESET))) + { + SMBUS_TransferConfig(hsmbus,0,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + } + else + { + SMBUS_TransferConfig(hsmbus,0, 1, hsmbus->XferOptions | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP); + } + + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the HOST */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Note : The SMBUS interrupts must be enabled after unlocking current process + to avoid the risk of SMBUS interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_ADDR); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief This function enable the Address listen mode + * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_Slave_Listen_IT(SMBUS_HandleTypeDef *hsmbus) +{ + hsmbus->State = HAL_SMBUS_STATE_LISTEN; + + /* Enable the Address Match interrupt */ + SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ADDR); + + return HAL_OK; +} + +/** + * @brief This function disable the Address listen mode + * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus) +{ + /* Disable Address listen mode only if a transfer is not ongoing */ + if(hsmbus->State == HAL_SMBUS_STATE_LISTEN) + { + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Disable the Address Match interrupt */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief This function enable the SMBUS alert mode. + * @param hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUSx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus) +{ + /* Enable SMBus alert */ + hsmbus->Instance->CR1 |= I2C_CR1_ALERTEN; + + /* Clear ALERT flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT); + + /* Enable Alert Interrupt */ + SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ALERT); + + return HAL_OK; +} +/** + * @brief This function disable the SMBUS alert mode. + * @param hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUSx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus) +{ + /* Enable SMBus alert */ + hsmbus->Instance->CR1 &= ~I2C_CR1_ALERTEN; + + /* Disable Alert Interrupt */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ALERT); + + return HAL_OK; +} + +/** + * @brief Checks if target device is ready for communication. + * @note This function is used with Memory devices + * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param DevAddress: Target device address + * @param Trials: Number of trials + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) +{ + uint32_t tickstart = 0; + + __IO uint32_t SMBUS_Trials = 0; + + if(hsmbus->State == HAL_SMBUS_STATE_READY) + { + if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_BUSY; + hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; + + do + { + /* Generate Start */ + hsmbus->Instance->CR2 = __HAL_SMBUS_GENERATE_START(hsmbus->Init.AddressingMode,DevAddress); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set or a NACK flag is set*/ + tickstart = HAL_GetTick(); + while((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) == RESET) && (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) && (hsmbus->State != HAL_SMBUS_STATE_TIMEOUT)) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + { + /* Device is ready */ + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + return HAL_TIMEOUT; + } + } + } + + /* Check if the NACKF flag has not been set */ + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) + { + /* Wait until STOPF flag is reset */ + if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Clear STOP Flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); + + /* Device is ready */ + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_OK; + } + else + { + /* Wait until STOPF flag is reset */ + if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Clear NACK Flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); + + /* Clear STOP Flag, auto generated with autoend*/ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); + } + + /* Check if the maximum allowed number of trials has been reached */ + if (SMBUS_Trials++ == Trials) + { + /* Generate Stop */ + hsmbus->Instance->CR2 |= I2C_CR2_STOP; + + /* Wait until STOPF flag is reset */ + if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Clear STOP Flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); + } + }while(SMBUS_Trials < Trials); + + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_TIMEOUT; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief This function handles SMBUS event interrupt request. + * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval None + */ +void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) +{ + uint32_t tmpisrvalue = 0; + + /* Use a local variable to store the current ISR flags */ + /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */ + tmpisrvalue = __SMBUS_GET_ISR_REG(hsmbus); + + /* SMBUS in mode Transmitter ---------------------------------------------------*/ + if (((__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET)) + { + /* Slave mode selected */ + if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) + { + SMBUS_Slave_ISR(hsmbus); + } + /* Master mode selected */ + else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX) + { + SMBUS_Master_ISR(hsmbus); + } + } + + /* SMBUS in mode Receiver ----------------------------------------------------*/ + if (((__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET)) + { + /* Slave mode selected */ + if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) + { + SMBUS_Slave_ISR(hsmbus); + } + /* Master mode selected */ + else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX) + { + SMBUS_Master_ISR(hsmbus); + } + } + + /* SMBUS in mode Listener Only --------------------------------------------------*/ + if (((__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) + && ((__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ADDRI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_STOPI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_NACKI) != RESET))) + { + if (hsmbus->State == HAL_SMBUS_STATE_LISTEN) + { + SMBUS_Slave_ISR(hsmbus); + } + } +} + +/** + * @brief This function handles SMBUS error interrupt request. + * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval None + */ +void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus) +{ + /* SMBUS Bus error interrupt occurred ------------------------------------*/ + if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR); + } + + /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/ + if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_OVR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR; + + /* Clear OVR flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR); + } + + /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/ + if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ARLO) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO); + } + + /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/ + if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT; + + /* Clear TIMEOUT flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT); + } + + /* SMBUS Alert error interrupt occurred -----------------------------------------------*/ + if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ALERT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT; + + /* Clear ALERT flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT); + } + + /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/ + if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_PECERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR; + + /* Clear PEC error flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR); + } + + /* Call the Error Callback in case of Error detected */ + if((hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE)&&(hsmbus->ErrorCode != HAL_SMBUS_ERROR_ACKF)) + { + /* Do not Reset the the HAL state in case of ALERT error */ + if((hsmbus->ErrorCode & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT) + { + if(((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) + || ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)) + { + /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */ + /* keep HAL_SMBUS_STATE_LISTEN if set */ + hsmbus->PreviousState = HAL_SMBUS_STATE_READY; + hsmbus->State = HAL_SMBUS_STATE_LISTEN; + } + } + + /* Call the Error callback to prevent upper layer */ + HAL_SMBUS_ErrorCallback(hsmbus); + } +} + +/** + * @brief Master Tx Transfer completed callbacks. + * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval None + */ + __weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SMBUS_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Master Rx Transfer completed callbacks. + * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval None + */ +__weak void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SMBUS_TxCpltCallback could be implemented in the user file + */ +} + +/** @brief Slave Tx Transfer completed callbacks. + * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval None + */ + __weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SMBUS_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave Rx Transfer completed callbacks. + * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval None + */ +__weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SMBUS_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave Address Match callbacks. + * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param TransferDirection: Master request Transfer Direction (Write/Read) + * @param AddrMatchCode: Address Match Code + * @retval None + */ +__weak void HAL_SMBUS_SlaveAddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SMBUS_SlaveAddrCallback could be implemented in the user file + */ +} + +/** + * @brief Listen Complete callbacks. + * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval None + */ +__weak void HAL_SMBUS_SlaveListenCpltCallback(SMBUS_HandleTypeDef *hsmbus) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SMBUS_SlaveListenCpltCallback could be implemented in the user file + */ +} + +/** + * @brief SMBUS error callbacks. + * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval None + */ + __weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SMBUS_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection permit to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the SMBUS state. + * @param hsmbus : SMBUS handle + * @retval HAL state + */ +HAL_SMBUS_StateTypeDef HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus) +{ + return hsmbus->State; +} + +/** +* @brief Return the SMBUS error code +* @param hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. +* @retval SMBUS Error Code +*/ +uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus) +{ + return hsmbus->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions + * @brief Data transfers Private functions + * @{ + */ + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode + * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval HAL status + */ +static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) +{ + uint16_t DevAddress; + + /* Process Locked */ + __HAL_LOCK(hsmbus); + + if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET) + { + /* Clear NACK Flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); + + /* Set corresponding Error Code */ + /* No need to generate STOP, it is automatically done */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Call the Error callback to prevent upper layer */ + HAL_SMBUS_ErrorCallback(hsmbus); + } + else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET) + { + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) + { + /* Disable Interrupt */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX); + + /* Clear STOP Flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + __HAL_SMBUS_RESET_CR2(hsmbus); + + /* Flush remaining data in Fifo register in case of error occurs before TXEmpty */ + /* Disable the selected SMBUS peripheral */ + __HAL_SMBUS_DISABLE(hsmbus); + + hsmbus->PreviousState = HAL_SMBUS_STATE_READY; + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* REenable the selected SMBUS peripheral */ + __HAL_SMBUS_ENABLE(hsmbus); + + HAL_SMBUS_MasterTxCpltCallback(hsmbus); + } + else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) + { + /* Disable Interrupt */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); + + /* Clear STOP Flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + __HAL_SMBUS_RESET_CR2(hsmbus); + + hsmbus->PreviousState = HAL_SMBUS_STATE_READY; + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + HAL_SMBUS_MasterRxCpltCallback(hsmbus); + } + } + else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) + { + /* Read data from RXDR */ + (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR; + hsmbus->XferSize--; + hsmbus->XferCount--; + } + else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET) + { + /* Write data to TXDR */ + hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++); + hsmbus->XferSize--; + hsmbus->XferCount--; + } + else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET) + { + if((hsmbus->XferSize == 0)&&(hsmbus->XferCount!=0)) + { + DevAddress = (hsmbus->Instance->CR2 & I2C_CR2_SADD); + + if(hsmbus->XferCount > MAX_NBYTE_SIZE) + { + SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP); + hsmbus->XferSize = MAX_NBYTE_SIZE; + } + else + { + hsmbus->XferSize = hsmbus->XferCount; + SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ + /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ + if(__HAL_SMBUS_GET_PEC_MODE(hsmbus) != RESET) + { + hsmbus->XferSize--; + hsmbus->XferCount--; + } + } + } + else if((hsmbus->XferSize == 0)&&(hsmbus->XferCount==0)) + { + /* Call TxCpltCallback if no stop mode is set */ + if(__HAL_SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) + { + /* Disable Interrupt */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX); + hsmbus->PreviousState = hsmbus->State; + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + HAL_SMBUS_MasterTxCpltCallback(hsmbus); + } + else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) + { + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); + hsmbus->PreviousState = hsmbus->State; + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + HAL_SMBUS_MasterRxCpltCallback(hsmbus); + } + } + } + } + else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TC) != RESET) + { + if(hsmbus->XferCount == 0) + { + /* Specific use case for Quick command */ + if(hsmbus->pBuffPtr == NULL) + { + /* Generate a Stop command */ + hsmbus->Instance->CR2 |= I2C_CR2_STOP; + } + /* Call TxCpltCallback if no stop mode is set */ + else if(__HAL_SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) + { + /* No Generate Stop, to permit restart mode */ + /* The stop will be done at the end of transfer, when SMBUS_AUTOEND_MODE enable */ + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) + { + /* Disable Interrupt */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX); + hsmbus->PreviousState = hsmbus->State; + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + HAL_SMBUS_MasterTxCpltCallback(hsmbus); + } + else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) + { + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); + hsmbus->PreviousState = hsmbus->State; + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + HAL_SMBUS_MasterRxCpltCallback(hsmbus); + } + } + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_OK; +} +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode + * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval HAL status + */ +static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) +{ + uint8_t TransferDirection = 0; + uint16_t SlaveAddrCode = 0; + + /* Process Locked */ + __HAL_LOCK(hsmbus); + + if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET) + { + /* Check that SMBUS transfer finished */ + /* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */ + /* Mean XferCount == 0*/ + /* So clear Flag NACKF only */ + if(hsmbus->XferCount == 0) + { + /* Clear NACK Flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + } + else + { + /* if no, error usecase, a Non-Acknowledge of last Data is generated by the HOST*/ + /* Clear NACK Flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); + + /* Set HAL State to "Idle" State, mean to LISTEN state */ + /* So reset Slave Busy state */ + hsmbus->PreviousState = hsmbus->State; + hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX); + hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX); + + /* Disable RX/TX Interrupts, keep only ADDR Interrupt */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Call the Error callback to prevent upper layer */ + HAL_SMBUS_ErrorCallback(hsmbus); + } + } + else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) != RESET) + { + TransferDirection = __HAL_SMBUS_GET_DIR(hsmbus); + SlaveAddrCode = __HAL_SMBUS_GET_ADDR_MATCH(hsmbus); + + /* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/ + /* Other ADDRInterrupt will be treat in next Listen usecase */ + __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_ADDRI); + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Call Slave Addr callback */ + HAL_SMBUS_SlaveAddrCallback(hsmbus, TransferDirection, SlaveAddrCode); + } + else if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) || (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET)) + { + if( (hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) + { + /* Read data from RXDR */ + (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR; + hsmbus->XferSize--; + hsmbus->XferCount--; + + if(hsmbus->XferCount == 1) + { + /* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */ + /* or only the last Byte of Transfer */ + /* So reset the RELOAD bit mode */ + hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE; + SMBUS_TransferConfig(hsmbus,0 ,1 , hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + } + else if(hsmbus->XferCount == 0) + { + /* Last Byte is received, disable Interrupt */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); + + /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_RX, keep only HAL_SMBUS_STATE_LISTEN */ + hsmbus->PreviousState = hsmbus->State; + hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX); + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Call the Rx complete callback to inform upper layer of the end of receive process */ + HAL_SMBUS_SlaveRxCpltCallback(hsmbus); + } + else + { + /* Set Reload for next Bytes */ + SMBUS_TransferConfig(hsmbus,0, 1, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); + + /* Ack last Byte Read */ + hsmbus->Instance->CR2 &= ~I2C_CR2_NACK; + } + } + else if( (hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) + { + if((hsmbus->XferSize == 0)&&(hsmbus->XferCount!=0)) + { + if(hsmbus->XferCount > MAX_NBYTE_SIZE) + { + SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP); + hsmbus->XferSize = MAX_NBYTE_SIZE; + } + else + { + hsmbus->XferSize = hsmbus->XferCount; + SMBUS_TransferConfig(hsmbus, 0, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ + /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ + if(__HAL_SMBUS_GET_PEC_MODE(hsmbus) != RESET) + { + hsmbus->XferSize--; + hsmbus->XferCount--; + } + } + } + } + } + else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET) + { + /* Write data to TXDR only if XferCount not reach "0" */ + /* A TXIS flag can be set, during STOP treatment */ + /* Check if all Datas have already been sent */ + /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ + if(hsmbus->XferCount > 0) + { + /* Write data to TXDR */ + hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++); + hsmbus->XferCount--; + hsmbus->XferSize--; + } + + if(hsmbus->XferCount == 0) + { + /* Last Byte is Transmitted */ + /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX); + hsmbus->PreviousState = hsmbus->State; + hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX); + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Call the Tx complete callback to inform upper layer of the end of transmit process */ + HAL_SMBUS_SlaveTxCpltCallback(hsmbus); + } + } + + /* Check if STOPF is set */ + if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET) + { + if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) + { + /* Disable RX and TX Interrupts */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX); + + /* Disable ADDR Interrupt */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR); + + /* Disable Address Acknowledge */ + hsmbus->Instance->CR2 |= I2C_CR2_NACK; + + /* Clear Configuration Register 2 */ + __HAL_SMBUS_RESET_CR2(hsmbus); + + /* Clear STOP Flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); + + /* Clear ADDR flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR); + + hsmbus->XferOptions = 0; + hsmbus->PreviousState = hsmbus->State; + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Call the Listen Complete callback, to prevent upper layer of the end of Listen usecase */ + HAL_SMBUS_SlaveListenCpltCallback(hsmbus); + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_OK; +} +/** + * @brief Manage the enabling of Interrupts + * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param InterruptRequest : Value of @ref SMBUS_Interrupt_configuration_definition. + * @retval HAL status + */ +static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest) +{ + uint32_t tmpisr = 0; + + if((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) + { + /* Enable ERR interrupt */ + tmpisr |= SMBUS_IT_ERRI; + } + + if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR) + { + /* Enable ADDR, STOP interrupt */ + tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_ERRI; + } + + if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX) + { + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI; + } + + if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX) + { + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI; + } + + /* Enable interrupts only at the end */ + /* to avoid the risk of SMBUS interrupt handle execution before */ + /* all interrupts requested done */ + __HAL_SMBUS_ENABLE_IT(hsmbus, tmpisr); + + return HAL_OK; +} +/** + * @brief Manage the disabling of Interrupts + * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param InterruptRequest : Value of @ref SMBUS_Interrupt_configuration_definition. + * @retval HAL status + */ +static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest) +{ + uint32_t tmpisr = 0; + + if( ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) && (hsmbus->State == HAL_SMBUS_STATE_READY) ) + { + /* Disable ERR interrupt */ + tmpisr |= SMBUS_IT_ERRI; + } + + if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX) + { + /* Disable TC, STOP, NACK, TXI interrupt */ + tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI; + + if((__HAL_SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) + && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) + { + /* Disable ERR interrupt */ + tmpisr |= SMBUS_IT_ERRI; + } + + if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN) + { + /* Disable STOPI, NACKI */ + tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI; + } + } + + if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX) + { + /* Disable TC, STOP, NACK, RXI interrupt */ + tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI; + + if((__HAL_SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) + && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) + { + /* Disable ERR interrupt */ + tmpisr |= SMBUS_IT_ERRI; + } + + if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN) + { + /* Disable STOPI, NACKI */ + tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI; + } + } + + if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR) + { + /* Enable ADDR, STOP interrupt */ + tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI; + + if(__HAL_SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) + { + /* Disable ERR interrupt */ + tmpisr |= SMBUS_IT_ERRI; + } + } + + /* Disable interrupts only at the end */ + /* to avoid a breaking situation like at "t" time */ + /* all disable interrupts request are not done */ + __HAL_SMBUS_DISABLE_IT(hsmbus, tmpisr); + + return HAL_OK; +} +/** + * @brief This function handles SMBUS Communication Timeout. + * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param Flag: specifies the SMBUS flag to check. + * @param Status: The new Flag status (SET or RESET). + * @param Timeout: Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + + /* Wait until flag is set */ + if(Status == RESET) + { + while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) == RESET) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + { + hsmbus->PreviousState = hsmbus->State; + hsmbus->State= HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_TIMEOUT; + } + } + } + } + else + { + while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) != RESET) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + { + hsmbus->PreviousState = hsmbus->State; + hsmbus->State= HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_TIMEOUT; + } + } + } + } + return HAL_OK; +} + +/** + * @brief Handles SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set). + * @param hsmbus: SMBUS handle. + * @param DevAddress: specifies the slave address to be programmed. + * @param Size: specifies the number of bytes to be programmed. + * This parameter must be a value between 0 and 255. + * @param Mode: new state of the SMBUS START condition generation. + * This parameter can be one or a combination of the following values: + * @arg SMBUS_NO_MODE: No specific mode enabled. + * @arg SMBUS_RELOAD_MODE: Enable Reload mode. + * @arg SMBUS_AUTOEND_MODE: Enable Automatic end mode. + * @arg SMBUS_SOFTEND_MODE: Enable Software end mode and Reload mode. + * @param Request: new state of the SMBUS START condition generation. + * This parameter can be one of the following values: + * @arg SMBUS_NO_STARTSTOP: Don't Generate stop and start condition. + * @arg SMBUS_GENERATE_STOP: Generate stop condition (Size should be set to 0). + * @arg SMBUS_GENERATE_START_READ: Generate Restart for read request. + * @arg SMBUS_GENERATE_START_WRITE: Generate Restart for write request. + * @retval None + */ +static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); + assert_param(IS_SMBUS_TRANSFER_MODE(Mode)); + assert_param(IS_SMBUS_TRANSFER_REQUEST(Request)); + + /* Get the CR2 register value */ + tmpreg = hsmbus->Instance->CR2; + + /* clear tmpreg specific bits */ + tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)); + + /* update tmpreg */ + tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request); + + /* update CR2 register */ + hsmbus->Instance->CR2 = tmpreg; +} +/** + * @} + */ + +#endif /* HAL_SMBUS_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_spi.c b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_spi.c new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_spi.c @@ -0,0 +1,2496 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_spi.c + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief SPI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the SPI peripheral: + * + Initialization/de-initialization functions + * + I/O operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + @verbatim +=============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The SPI HAL driver can be used as follows: + + (#) Declare a SPI_HandleTypeDef handle structure, for example: + SPI_HandleTypeDef hspi; + + (#)Initialize the SPI low level resources by implement the HAL_SPI_MspInit ()API: + (##) Enable the SPIx interface clock + (##) SPI pins configuration + (+++) Enable the clock for the SPI GPIOs + (+++) Configure these SPI pins as alternate function push-pull + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the SPIx interrupt priority + (+++) Enable the NVIC SPI IRQ handle + (##) DMA Configuration if you need to use DMA process + (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel + (+++) Enable the DMAx interface clock using + (+++) Configure the DMA handle parameters + (+++) Configure the DMA Tx or Rx channel + (+++) Associate the initilalized hdma_tx handle to the hspi DMA Tx or Rx handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx channel + + (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS + management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. + + (#) Initialize the SPI registers by calling the HAL_SPI_Init() API: + (++) These APIs configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + by calling the customed HAL_SPI_MspInit(&hspi) API. + + [..] + Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes, + the following table resume the max SPI frequency reached with data size 8bits/16bits: + +-----------------------------------------------------------------------------------------+ + | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | + | Process | Tranfert mode |--------------------|--------------------|--------------------| + | | | Master | Slave | Master | Slave | Master | Slave | + |=========================================================================================| + | T | Polling | Fcpu/32 | Fcpu/32 | NA | NA | NA | NA | + | X |----------------|----------|---------|----------|---------|----------|---------| + | / | Interrupt | Fcpu/32 | Fcpu/32 | NA | NA | NA | NA | + | R |----------------|----------|---------|----------|---------|----------|---------| + | X | DMA | Fcpu/32 | Fcpu/16 | NA | NA | NA | NA | + |=========|================|==========|=========|==========|=========|==========|=========| + | | Polling | Fcpu/32 | Fcpu/16 | Fcpu/16 | Fcpu/16 | Fcpu/16 | Fcpu/16 | + | |----------------|----------|---------|----------|---------|----------|---------| + | R | Interrupt | Fcpu/16 | Fcpu/16 | Fcpu/16 | Fcpu/16 | Fcpu/16 | Fcpu/16 | + | X |----------------|----------|---------|----------|---------|----------|---------| + | | DMA | Fcpu/4 | Fcpu/8 | Fcpu/4 | Fcpu/4 | Fcpu/8 | Fcpu/16 | + |=========|================|==========|=========|==========|=========|==========|=========| + | | Polling | Fcpu/16 | Fcpu/16 | NA | NA | Fcpu/16 | Fcpu/16 | + | |----------------|----------|---------|----------|---------|----------|---------| + | T | Interrupt | Fcpu/32 | Fcpu/16 | NA | NA | Fcpu/16 | Fcpu/16 | + | X |----------------|----------|---------|----------|---------|----------|---------| + | | DMA | Fcpu/2 | Fcpu/16 | NA | NA | Fcpu/8 | Fcpu/16 | + +-----------------------------------------------------------------------------------------+ + @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits), + SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA). + @note + (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA() + (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() + (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup SPI SPI HAL module driver + * @brief SPI HAL module driver + * @{ + */ +#ifdef HAL_SPI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup SPI_Private_Constants SPI Private Constants + * @{ + */ +#define SPI_DEFAULT_TIMEOUT 50 +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup SPI_Private_Functions SPI Private Functions + * @{ + */ + +static void HAL_SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void HAL_SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void HAL_SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma); +static void HAL_SPI_DMAError(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout); +static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout); +static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); +static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); +static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi); +static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi); +static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi); +static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout); +static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup SPI_Exported_Functions SPI Exported Functions + * @{ + */ + +/** @defgroup SPI_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + de-initialiaze the SPIx peripheral: + + (+) User must Implement HAL_SPI_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + + (+) Call the function HAL_SPI_Init() to configure the selected device with + the selected configuration: + (++) Mode + (++) Direction + (++) Data Size + (++) Clock Polarity and Phase + (++) NSS Management + (++) BaudRate Prescaler + (++) FirstBit + (++) TIMode + (++) CRC Calculation + (++) CRC Polynomial if CRC enabled + (++) CRC Length, used only with Data8 and Data16 + (++) FIFO reception threshold + + (+) Call the function HAL_SPI_DeInit() to restore the default configuration + of the selected SPIx periperal. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the SPI according to the specified parameters + * in the SPI_InitTypeDef and create the associated handle. + * @param hspi: SPI handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) +{ + uint32_t frxth; + + /* Check the SPI handle allocation */ + if(hspi == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); + assert_param(IS_SPI_MODE(hspi->Init.Mode)); + assert_param(IS_SPI_DIRECTION(hspi->Init.Direction)); + assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); + assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); + assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); + assert_param(IS_SPI_NSS(hspi->Init.NSS)); + assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode)); + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); + assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); + assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); + assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength)); + + hspi->State = HAL_SPI_STATE_BUSY; + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_SPI_MspInit(hspi); + + /* Disable the selected SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Align by default the rs fifo threshold on the data size */ + if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + frxth = SPI_RXFIFO_THRESHOLD_HF; + } + else + { + frxth = SPI_RXFIFO_THRESHOLD_QF; + } + + /* CRC calculation is valid only for 16Bit and 8 Bit */ + if(( hspi->Init.DataSize != SPI_DATASIZE_16BIT ) && ( hspi->Init.DataSize != SPI_DATASIZE_8BIT )) + { + /* CRC must be disabled */ + hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED; + } + + /* Align the CRC Length on the data size */ + if( hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE) + { + /* CRC Lengtht aligned on the data size : value set by default */ + if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT; + } + else + { + hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT; + } + } + + /*---------------------------- SPIx CR1 & CR2 Configuration ------------------------*/ + /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management, + Communication speed, First bit, CRC calculation state, CRC Length */ + hspi->Instance->CR1 = (hspi->Init.Mode | hspi->Init.Direction | + hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) | + hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation); + + if( hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) + { + hspi->Instance->CR1|= SPI_CR1_CRCL; + } + + /* Configure : NSS management */ + /* Configure : Rx Fifo Threshold */ + hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode | hspi->Init.NSSPMode | + hspi->Init.DataSize ) | frxth; + + /*---------------------------- SPIx CRCPOLY Configuration --------------------*/ + /* Configure : CRC Polynomial */ + hspi->Instance->CRCPR = hspi->Init.CRCPolynomial; + + /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ + hspi->Instance->I2SCFGR &= (uint16_t)(~SPI_I2SCFGR_I2SMOD); + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->State= HAL_SPI_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the SPI peripheral + * @param hspi: SPI handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) +{ + /* Check the SPI handle allocation */ + if(hspi == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); + + hspi->State = HAL_SPI_STATE_BUSY; + + /* Disable the SPI Peripheral Clock */ + __HAL_SPI_DISABLE(hspi); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + HAL_SPI_MspDeInit(hspi); + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->State = HAL_SPI_STATE_RESET; + + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief SPI MSP Init + * @param hspi: SPI handle + * @retval None + */ + __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_MspInit could be implenetd in the user file + */ +} + +/** + * @brief SPI MSP DeInit + * @param hspi: SPI handle + * @retval None + */ + __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_MspDeInit could be implenetd in the user file + */ +} + +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions_Group2 I/O operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of functions allowing to manage the SPI + data transfers. + + [..] The SPI supports master and slave mode : + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) Non Blocking mode: The communication is performed using Interrupts + or DMA, These APIs return the HAL status. + The end of the data processing will be indicated through the + dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks + will be executed respectivelly at the end of the transmit or Receive process + The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected + + (#) Blocking mode APIs are : + (++) HAL_SPI_Transmit()in 1Line (simplex) and 2Lines (full duplex) mode + (++) HAL_SPI_Receive() in 1Line (simplex) and 2Lines (full duplex) mode + (++) HAL_SPI_TransmitReceive() in full duplex mode + + (#) Non Blocking mode APIs with Interrupt are : + (++) HAL_SPI_Transmit_IT()in 1Line (simplex) and 2Lines (full duplex) mode + (++) HAL_SPI_Receive_IT() in 1Line (simplex) and 2Lines (full duplex) mode + (++) HAL_SPI_TransmitReceive_IT()in full duplex mode + (++) HAL_SPI_IRQHandler() + + (#) Non Blocking mode functions with DMA are : + (++) HAL_SPI_Transmit_DMA()in 1Line (simplex) and 2Lines (full duplex) mode + (++) HAL_SPI_Receive_DMA() in 1Line (simplex) and 2Lines (full duplex) mode + (++) HAL_SPI_TransmitReceie_DMA() in full duplex mode + + (#) A set of Transfer Complete Callbacks are provided in Non Blocking mode: + (++) HAL_SPI_TxCpltCallback() + (++) HAL_SPI_RxCpltCallback() + (++) HAL_SPI_ErrorCallback() + (++) HAL_SPI_TxRxCpltCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Transmit an amount of data in blocking mode + * @param hspi: SPI handle + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + if(hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + if((pData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + hspi->pRxBuffPtr = NULL; + hspi->RxXferSize = 0; + hspi->RxXferCount = 0; + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + __HAL_SPI_RESET_CRC(hspi); + } + + /* Configure communication direction : 1Line */ + if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + __HAL_SPI_1LINE_TX(hspi); + } + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Transmit data in 16 Bit mode */ + if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + while (hspi->TxXferCount > 0) + { + /* Wait until TXE flag is set to send data */ + if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + } + } + /* Transmit data in 8 Bit mode */ + else + { + while (hspi->TxXferCount > 0) + { + if(hspi->TxXferCount != 0x1) + { + /* Wait until TXE flag is set to send data */ + if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount -= 2; + } + else + { + /* Wait until TXE flag is set to send data */ + if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + *((__IO uint8_t*)&hspi->Instance->DR) = (*hspi->pTxBuffPtr++); + hspi->TxXferCount--; + } + } + } + + /* Enable CRC Transmission */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + hspi->Instance->CR1|= SPI_CR1_CRCNEXT; + } + + /* Check the end of the transaction */ + if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Clear OVERUN flag in 2 Lines communication mode because received is not read */ + if(hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + return HAL_ERROR; + } + else + { + return HAL_OK; + } +} + +/** + * @brief Receive an amount of data in blocking mode + * @param hspi: SPI handle + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + __IO uint16_t tmpreg; + + if(hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + if((pData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) + { + /* the receive process is not supported in 2Lines direction master mode */ + /* in this case we call the transmitReceive process */ + return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout); + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + hspi->pTxBuffPtr = NULL; + hspi->TxXferSize = 0; + hspi->TxXferCount = 0; + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + __HAL_SPI_RESET_CRC(hspi); + } + + /* Set the Rx Fido thresold */ + if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + /* set fiforxthresold according the reception data lenght: 16bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + else + { + /* set fiforxthresold according the reception data lenght: 8bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + + /* Configure communication direction 1Line and enabled SPI if needed */ + if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + __HAL_SPI_1LINE_RX(hspi); + } + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Receive data in 8 Bit mode */ + if(hspi->Init.DataSize <= SPI_DATASIZE_8BIT) + { + while(hspi->RxXferCount > 1) + { + /* Wait until the RXNE flag */ + if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + (*hspi->pRxBuffPtr++)= *(__IO uint8_t *)&hspi->Instance->DR; + hspi->RxXferCount--; + } + } + else /* Receive data in 16 Bit mode */ + { + while(hspi->RxXferCount > 1 ) + { + /* Wait until RXNE flag is reset to read data */ + if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + } + } + + /* Enable CRC Transmission */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; + } + + /* Wait until RXNE flag is set */ + if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Receive last data in 16 Bit mode */ + if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint16_t); + } + /* Receive last data in 8 Bit mode */ + else + { + (*hspi->pRxBuffPtr++) = *(__IO uint8_t *)&hspi->Instance->DR; + } + hspi->RxXferCount--; + + /* Read CRC from DR to close CRC calculation process */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + /* Wait until TXE flag */ + if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) + { + /* Erreur on the CRC reception */ + hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + } + if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + tmpreg = hspi->Instance->DR; + } + else + { + tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; + if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) + { + if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) + { + /* Erreur on the CRC reception */ + hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + } + tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; + } + } + } + + /* Check the end of the transaction */ + if(SPI_EndRxTransaction(hspi,Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + hspi->State = HAL_SPI_STATE_READY; + + /* Check if CRC error occurred */ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + return HAL_ERROR; + } + else + { + return HAL_OK; + } +} + +/** + * @brief Transmit and Receive an amount of data in blocking mode + * @param hspi: SPI handle + * @param pTxData: pointer to transmission data buffer + * @param pRxData: pointer to reception data buffer to be + * @param Size: amount of data to be sent + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) +{ + __IO uint16_t tmpreg = 0; + uint32_t tickstart = 0; + + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + if(hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + tickstart = HAL_GetTick(); + + /* Process Locked */ + __HAL_LOCK(hspi); + + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = pRxData; + hspi->RxXferCount = Size; + hspi->RxXferSize = Size; + hspi->pTxBuffPtr = pTxData; + hspi->TxXferCount = Size; + hspi->TxXferSize = Size; + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + __HAL_SPI_RESET_CRC(hspi); + } + + /* Set the Rx Fido threshold */ + if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1)) + { + /* set fiforxthreshold according the reception data lenght: 16bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + else + { + /* set fiforxthreshold according the reception data lenght: 8bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Transmit and Receive data in 16 Bit mode */ + if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + while ((hspi->TxXferCount > 0 ) || (hspi->RxXferCount > 0)) + { + /* Wait until TXE flag */ + if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)) + { + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + + /* Enable CRC Transmission */ + if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + } + + /* Wait until RXNE flag */ + if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)) + { + *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + } + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + { + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; + } + } + } + } + /* Transmit and Receive data in 8 Bit mode */ + else + { + while((hspi->TxXferCount > 0) || (hspi->RxXferCount > 0)) + { + /* check if TXE flag is set to send data */ + if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)) + { + if(hspi->TxXferCount > 2) + { + hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount -= 2; + } + else + { + *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++); + hspi->TxXferCount--; + } + + /* Enable CRC Transmission */ + if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + } + + /* Wait until RXNE flag is reset */ + if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)) + { + if(hspi->RxXferCount > 1) + { + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount -= 2; + if(hspi->RxXferCount <= 1) + { + /* set fiforxthresold before to switch on 8 bit data size */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + } + else + { + (*hspi->pRxBuffPtr++) = *(__IO uint8_t *)&hspi->Instance->DR; + hspi->RxXferCount--; + } + } + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + { + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; + } + } + } + } + + /* Read CRC from DR to close CRC calculation process */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + /* Wait until TXE flag */ + if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) + { + /* Erreur on the CRC reception */ + hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + } + + if(hspi->Init.DataSize == SPI_DATASIZE_16BIT) + { + tmpreg = hspi->Instance->DR; + } + else + { + tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; + if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) + { + if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) + { + /* Erreur on the CRC reception */ + hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + } + tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; + } + } + } + + /* Check the end of the transaction */ + if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + hspi->State = HAL_SPI_STATE_READY; + + /* Check if CRC error occurred */ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + /* Clear CRC Flag */ + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_ERROR; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + return HAL_ERROR; + } + else + { + return HAL_OK; + } +} + +/** + * @brief Transmit an amount of data in no-blocking mode with Interrupt + * @param hspi: SPI handle + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + if(hspi->State == HAL_SPI_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + hspi->pRxBuffPtr = NULL; + hspi->RxXferSize = 0; + hspi->RxXferCount = 0; + + /* Set the function for IT treatement */ + if(hspi->Init.DataSize > SPI_DATASIZE_8BIT ) + { + hspi->RxISR = NULL; + hspi->TxISR = SPI_TxISR_16BIT; + } + else + { + hspi->RxISR = NULL; + hspi->TxISR = SPI_TxISR_8BIT; + } + + /* Configure communication direction : 1Line */ + if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + __HAL_SPI_1LINE_TX(hspi); + } + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + __HAL_SPI_RESET_CRC(hspi); + } + + /* Enable TXE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi,(SPI_IT_TXE)); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Note : The SPI must be enabled after unlocking current process + to avoid the risk of SPI interrupt handle execution before current + process unlock */ + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in no-blocking mode with Interrupt + * @param hspi: SPI handle + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + if(hspi->State == HAL_SPI_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Configure communication */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + hspi->pTxBuffPtr = NULL; + hspi->TxXferSize = 0; + hspi->TxXferCount = 0; + + if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + /* the receive process is not supported in 2Lines direction master mode */ + /* in this we call the transmitReceive process */ + return HAL_SPI_TransmitReceive_IT(hspi,pData,pData,Size); + } + + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + hspi->CRCSize = 1; + if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) + { + hspi->CRCSize = 2; + } + } + else + { + hspi->CRCSize = 0; + } + + /* check the data size to adapt Rx threshold and the set the function for IT treatement */ + if(hspi->Init.DataSize > SPI_DATASIZE_8BIT ) + { + /* set fiforxthresold according the reception data lenght: 16 bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + hspi->RxISR = SPI_RxISR_16BIT; + hspi->TxISR = NULL; + } + else + { + /* set fiforxthresold according the reception data lenght: 8 bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + hspi->RxISR = SPI_RxISR_8BIT; + hspi->TxISR = NULL; + } + + /* Configure communication direction : 1Line */ + if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + __HAL_SPI_1LINE_RX(hspi); + } + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + __HAL_SPI_RESET_CRC(hspi); + } + + /* Enable TXE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Note : The SPI must be enabled after unlocking current process + to avoid the risk of SPI interrupt handle execution before current + process unlock */ + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt + * @param hspi: SPI handle + * @param pTxData: pointer to transmission data buffer + * @param pRxData: pointer to reception data buffer to be + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +{ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + if((hspi->State == HAL_SPI_STATE_READY) || \ + ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))) + { + if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hspi); + + hspi->CRCSize = 0; + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + hspi->CRCSize = 1; + if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) + { + hspi->CRCSize = 2; + } + } + + if(hspi->State != HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + hspi->pRxBuffPtr = pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /* Set the function for IT treatement */ + if(hspi->Init.DataSize > SPI_DATASIZE_8BIT ) + { + hspi->RxISR = SPI_2linesRxISR_16BIT; + hspi->TxISR = SPI_2linesTxISR_16BIT; + } + else + { + hspi->RxISR = SPI_2linesRxISR_8BIT; + hspi->TxISR = SPI_2linesTxISR_8BIT; + } + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + __HAL_SPI_RESET_CRC(hspi); + } + + /* check if packing mode is enabled and if there is more than 2 data to receive */ + if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2)) + { + /* set fiforxthresold according the reception data lenght: 16 bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + else + { + /* set fiforxthresold according the reception data lenght: 8 bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + + /* Enable TXE, RXNE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit an amount of data in no-blocking mode with DMA + * @param hspi: SPI handle + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + if(hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + hspi->pRxBuffPtr = NULL; + hspi->RxXferSize = 0; + hspi->RxXferCount = 0; + + /* Configure communication direction : 1Line */ + if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + __HAL_SPI_1LINE_TX(hspi); + } + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + __HAL_SPI_RESET_CRC(hspi); + } + + /* Set the SPI TxDMA transfer complete callback */ + hspi->hdmatx->XferCpltCallback = HAL_SPI_DMATransmitCplt; + + /* Set the DMA error callback */ + hspi->hdmatx->XferErrorCallback = HAL_SPI_DMAError; + + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); + /* packing mode is enabled only if the DMA setting is HALWORD */ + if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)) + { + /* Check the even/odd of the data size + crc if enabled */ + if((hspi->TxXferCount & 0x1) == 0) + { + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); + hspi->TxXferCount = (hspi->TxXferCount >> 1); + } + else + { + SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); + hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1; + } + } + + /* Enable the Tx DMA channel */ + HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Enable Tx DMA Request */ + hspi->Instance->CR2 |= SPI_CR2_TXDMAEN; + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** +* @brief Receive an amount of data in no-blocking mode with DMA +* @param hspi: SPI handle +* @param pData: pointer to data buffer +* @param Size: amount of data to be sent +* @retval HAL status +*/ +HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + if(hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + hspi->pTxBuffPtr = NULL; + hspi->TxXferSize = 0; + hspi->TxXferCount = 0; + + if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + /* the receive process is not supported in 2Lines direction master mode */ + /* in this case we call the transmitReceive process */ + return HAL_SPI_TransmitReceive_DMA(hspi,pData,pData,Size); + } + + /* Configure communication direction : 1Line */ + if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + __HAL_SPI_1LINE_RX(hspi); + } + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + __HAL_SPI_RESET_CRC(hspi); + } + + /* packing mode management is enabled by the DMA settings */ + if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)) + { + /* Process Locked */ + __HAL_UNLOCK(hspi); + /* Restriction the DMA data received is not allowed in this mode */ + return HAL_ERROR; + } + + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); + if( hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + /* set fiforxthresold according the reception data lenght: 16bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + else + { + /* set fiforxthresold according the reception data lenght: 8bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + + /* Set the SPI Rx DMA transfer complete callback */ + hspi->hdmarx->XferCpltCallback = HAL_SPI_DMAReceiveCplt; + + /* Set the DMA error callback */ + hspi->hdmarx->XferErrorCallback = HAL_SPI_DMAError; + + /* Enable Rx DMA Request */ + hspi->Instance->CR2 |= SPI_CR2_RXDMAEN; + + /* Enable the Rx DMA channel */ + HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + return HAL_OK; +} + +/** + * @brief Transmit and Receive an amount of data in no-blocking mode with DMA + * @param hspi: SPI handle + * @param pTxData: pointer to transmission data buffer + * @param pRxData: pointer to reception data buffer to be + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +{ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + if((hspi->State == HAL_SPI_STATE_READY) || + ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))) + { + if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hspi); + + /* check if the transmit Receive function is not called by a receive master */ + if(hspi->State != HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + hspi->pRxBuffPtr = (uint8_t *)pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /* Reset CRC Calculation + increase the rxsize */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + __HAL_SPI_RESET_CRC(hspi); + } + + /* Reset the threshold bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); + + /* the packing mode management is enabled by the DMA settings according the spi data size */ + if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + /* set fiforxthreshold according the reception data lenght: 16bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + else + { + /* set fiforxthresold according the reception data lenght: 8bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + + if(hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + { + if((hspi->TxXferSize & 0x1) == 0x0 ) + { + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); + hspi->TxXferCount = hspi->TxXferCount >> 1; + } + else + { + SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); + hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1; + } + } + + if(hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + { + /* set fiforxthresold according the reception data lenght: 16bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + + /* Size must include the CRC lenght */ + if((hspi->RxXferCount & 0x1) == 0x0 ) + { + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); + hspi->RxXferCount = hspi->RxXferCount >> 1; + } + else + { + SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); + hspi->RxXferCount = (hspi->RxXferCount >> 1) + 1; + } + } + } + + /* Set the SPI Rx DMA transfer complete callback because the last generated transfer request is + the reception request (RXNE) */ + if(hspi->State == HAL_SPI_STATE_BUSY_RX) + { + hspi->hdmarx->XferCpltCallback = HAL_SPI_DMAReceiveCplt; + } + else + { + hspi->hdmarx->XferCpltCallback = HAL_SPI_DMATransmitReceiveCplt; + } + /* Set the DMA error callback */ + hspi->hdmarx->XferErrorCallback = HAL_SPI_DMAError; + + /* Enable Rx DMA Request */ + hspi->Instance->CR2 |= SPI_CR2_RXDMAEN; + + /* Enable the Rx DMA channel */ + HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t) hspi->pRxBuffPtr, hspi->RxXferCount); + + /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing + is performed in DMA reception complete callback */ + hspi->hdmatx->XferCpltCallback = NULL; + + /* Set the DMA error callback */ + hspi->hdmatx->XferErrorCallback = HAL_SPI_DMAError; + + /* Enable the Tx DMA channel */ + HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Enable Tx DMA Request */ + hspi->Instance->CR2 |= SPI_CR2_TXDMAEN; + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief This function handles SPI interrupt request. + * @param hspi: SPI handle + * @retval HAL status + */ +void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) +{ + /* SPI in mode Receiver ----------------------------------------------------*/ + if((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) == RESET) && + (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE) != RESET) && (__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) != RESET)) + { + hspi->RxISR(hspi); + return; + } + + /* SPI in mode Tramitter ---------------------------------------------------*/ + if((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET) && (__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET)) + { + hspi->TxISR(hspi); + return; + } + + /* SPI in Erreur Treatment ---------------------------------------------------*/ + if((hspi->Instance->SR & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET) + { + /* SPI Overrun error interrupt occured -------------------------------------*/ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET) + { + if(hspi->State != HAL_SPI_STATE_BUSY_TX) + { + hspi->ErrorCode |= HAL_SPI_ERROR_OVR; + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + else + { + return; + } + } + + /* SPI Mode Fault error interrupt occured -------------------------------------*/ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET) + { + hspi->ErrorCode |= HAL_SPI_ERROR_MODF; + __HAL_SPI_CLEAR_MODFFLAG(hspi); + } + + /* SPI Frame error interrupt occured ----------------------------------------*/ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET) + { + hspi->ErrorCode |= HAL_SPI_ERROR_FRE; + __HAL_SPI_CLEAR_FREFLAG(hspi); + } + + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR); + hspi->State = HAL_SPI_STATE_READY; + HAL_SPI_ErrorCallback(hspi); + return; + } +} + +/** + * @brief DMA SPI transmit process complete callback + * @param hdma : DMA handle + * @retval None + */ +static void HAL_SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Disable Tx DMA Request */ + hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN); + + /* Check the end of the transaction */ + SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT); + + /* Clear OVERUN flag in 2 Lines communication mode because received data is not read */ + if(hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + hspi->TxXferCount = 0; + hspi->State = HAL_SPI_STATE_READY; + + /* Check if CRC error occurred or Error code */ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + HAL_SPI_ErrorCallback(hspi); + } + else + { + if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) + { + HAL_SPI_TxCpltCallback(hspi); + } + else + { + HAL_SPI_ErrorCallback(hspi); + } + } +} + +/** + * @brief DMA SPI receive process complete callback + * @param hdma : DMA handle + * @retval None + */ +static void HAL_SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + __IO uint16_t tmpreg; + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* CRC handling */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + /* Wait until TXE flag */ + if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK) + { + /* Erreur on the CRC reception */ + hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + } + if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + tmpreg = hspi->Instance->DR; + } + else + { + tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; + if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) + { + if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK) + { + /* Erreur on the CRC reception */ + hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + } + tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; + } + } + } + + /* Disable Rx DMA Request */ + hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN); + /* Disable Tx DMA Request (done by default to handle the case master rx direction 2 lines) */ + hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN); + + /* Check the end of the transaction */ + SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT); + + hspi->RxXferCount = 0; + hspi->State = HAL_SPI_STATE_READY; + + /* Check if CRC error occurred */ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + HAL_SPI_RxCpltCallback(hspi); + } + else + { + if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) + { + HAL_SPI_RxCpltCallback(hspi); + } + else + { + HAL_SPI_ErrorCallback(hspi); + } + } +} + +/** + * @brief DMA SPI transmit receive process complete callback + * @param hdma : DMA handle + * @retval None + */ + +static void HAL_SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) +{ + __IO int16_t tmpreg; + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* CRC handling */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT)) + { + if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK) + { + /* Erreur on the CRC reception */ + hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + } + tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; + } + else + { + if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK) + { + /* Erreur on the CRC reception */ + hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + } + tmpreg = hspi->Instance->DR; + } + } + + /* Check the end of the transaction */ + SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT); + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + /* Disable Rx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + hspi->TxXferCount = 0; + hspi->RxXferCount = 0; + hspi->State = HAL_SPI_STATE_READY; + + /* Check if CRC error occurred */ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + hspi->ErrorCode = HAL_SPI_ERROR_CRC; + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + HAL_SPI_ErrorCallback(hspi); + } + else + { + if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) + { + HAL_SPI_TxRxCpltCallback(hspi); + } + else + { + HAL_SPI_ErrorCallback(hspi); + } + } +} + +/** + * @brief DMA SPI communication error callback + * @param hdma : DMA handle + * @retval None + */ +static void HAL_SPI_DMAError(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + hspi->TxXferCount = 0; + hspi->RxXferCount = 0; + hspi->ErrorCode|= HAL_SPI_ERROR_DMA; + hspi->State = HAL_SPI_STATE_READY; + HAL_SPI_ErrorCallback(hspi); +} + +/** + * @brief Tx Transfer completed callbacks + * @param hspi: SPI handle + * @retval None + */ +__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_TxCpltCallback could be implenetd in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks + * @param hspi: SPI handle + * @retval None + */ +__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_RxCpltCallback could be implenetd in the user file + */ +} + +/** + * @brief Tx and Rx Transfer completed callbacks + * @param hspi: SPI handle + * @retval None + */ +__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_TxRxCpltCallback could be implenetd in the user file + */ +} + +/** + * @brief SPI error callbacks + * @param hspi: SPI handle + * @retval None + */ + __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_ErrorCallback could be implenetd in the user file + */ +} + +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions_Group3 Peripheral Control functions + * @brief SPI control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the SPI. + (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral. + (+) HAL_SPI_Ctl() API can be used to update the spi configuration (only one parameter) + without calling the HAL_SPI_Init() API +@endverbatim + * @{ + */ + +/** + * @brief Return the SPI state + * @param hspi : SPI handle + * @retval HAL state + */ +HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) +{ + return hspi->State; +} +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup SPI_Private_Functions SPI Private Functions + * @brief Data transfers Private functions + * @{ + */ + +/** + * @brief Rx Handler for Transmit and Receive in Interrupt mode + * @param hspi: SPI handle + */ +static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +{ + /* Receive data in packing mode */ + if(hspi->RxXferCount > 1) + { + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount -= 2; + if(hspi->RxXferCount == 1) + { + /* set fiforxthresold according the reception data lenght: 8bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + } + /* Receive data in 8 Bit mode */ + else + { + *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR); + hspi->RxXferCount--; + } + + /* check end of the reception */ + if(hspi->RxXferCount == 0) + { + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + hspi->RxISR = SPI_2linesRxISR_8BITCRC; + return; + } + + /* Disable RXNE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); + + if(hspi->TxXferCount == 0) + { + SPI_CloseRxTx_ISR(hspi); + } + } +} + +/** + * @brief Rx Handler for Transmit and Receive in Interrupt mode + * @param hspi: SPI handle + */ +static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) +{ + __IO uint8_t tmpreg; + + tmpreg = *((__IO uint8_t *)&hspi->Instance->DR); + hspi->CRCSize--; + + /* check end of the reception */ + if(hspi->CRCSize == 0) + { + /* Disable RXNE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); + + if(hspi->TxXferCount == 0) + { + SPI_CloseRxTx_ISR(hspi); + } + } +} + +/** + * @brief Tx Handler for Transmit and Receive in Interrupt mode + * @param hspi: SPI handle + */ +static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +{ + /* Transmit data in packing Bit mode */ + if(hspi->TxXferCount >= 2) + { + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount -= 2; + } + /* Transmit data in 8 Bit mode */ + else + { + *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++); + hspi->TxXferCount--; + } + + /* check the end of the transmission */ + if(hspi->TxXferCount == 0) + { + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; + } + /* Disable TXE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + + if(hspi->RxXferCount == 0) + { + SPI_CloseRxTx_ISR(hspi); + } + } +} + +/** + * @brief Rx 16Bit Handler for Transmit and Receive in Interrupt mode + * @param hspi: SPI handle + */ +static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +{ + /* Receive data in 16 Bit mode */ + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + + if(hspi->RxXferCount == 0) + { + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + hspi->RxISR = SPI_2linesRxISR_16BITCRC; + return; + } + + /* Disable RXNE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); + + if(hspi->TxXferCount == 0) + { + SPI_CloseRxTx_ISR(hspi); + } + } +} + +/** + * @brief Manage the CRC 16bit receive for Transmit and Receive in Interrupt mode + * @param hspi: SPI handle + */ +static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) +{ + __IO uint16_t tmpreg; + /* Receive data in 16 Bit mode */ + tmpreg = hspi->Instance->DR; + + /* Disable RXNE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); + + SPI_CloseRxTx_ISR(hspi); +} + +/** + * @brief Tx Handler for Transmit and Receive in Interrupt mode + * @param hspi: SPI handle + */ +static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +{ + /* Transmit data in 16 Bit mode */ + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + + /* Enable CRC Transmission */ + if(hspi->TxXferCount == 0) + { + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; + } + /* Disable TXE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + + if(hspi->RxXferCount == 0) + { + SPI_CloseRxTx_ISR(hspi); + } + } +} + +/** + * @brief Manage the CRC receive in Interrupt context + * @param hspi: SPI handle + */ +static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) +{ + __IO uint8_t tmpreg; + tmpreg = *((__IO uint8_t*)&hspi->Instance->DR); + hspi->CRCSize--; + + if(hspi->CRCSize == 0) + { + SPI_CloseRx_ISR(hspi); + } +} + +/** + * @brief Manage the recieve in Interrupt context + * @param hspi: SPI handle + */ +static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +{ + *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR); + hspi->RxXferCount--; + + /* Enable CRC Transmission */ + if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)) + { + hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; + } + + if(hspi->RxXferCount == 0) + { + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + hspi->RxISR = SPI_RxISR_8BITCRC; + return; + } + SPI_CloseRx_ISR(hspi); + } +} + +/** + * @brief Manage the CRC 16bit recieve in Interrupt context + * @param hspi: SPI handle + */ +static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) +{ + __IO uint16_t tmpreg; + + tmpreg = hspi->Instance->DR; + + /* Disable RXNE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + SPI_CloseRx_ISR(hspi); +} + +/** + * @brief Manage the 16Bit recieve in Interrupt context + * @param hspi: SPI handle + */ +static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +{ + *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + + /* Enable CRC Transmission */ + if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)) + { + hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; + } + + if(hspi->RxXferCount == 0) + { + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + hspi->RxISR = SPI_RxISR_16BITCRC; + return; + } + SPI_CloseRx_ISR(hspi); + } +} + +/** + * @brief Handle the data 8Bit transmit in Interrupt mode + * @param hspi: SPI handle + */ +static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +{ + *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++); + hspi->TxXferCount--; + + if(hspi->TxXferCount == 0) + { + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + /* Enable CRC Transmission */ + hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; + } + SPI_CloseTx_ISR(hspi); + } +} + +/** + * @brief Handle the data 16Bit transmit in Interrupt mode + * @param hspi: SPI handle + */ +static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +{ + /* Transmit data in 16 Bit mode */ + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + + if(hspi->TxXferCount == 0) + { + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + /* Enable CRC Transmission */ + hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; + } + SPI_CloseTx_ISR(hspi); + } +} + +/** + * @brief This function handles SPI Communication Timeout. + * @param hspi: SPI handle + * @param Flag : SPI flag to check + * @param State : flag state to check + * @param Timeout : Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + + while((hspi->Instance->SR & Flag) != State) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + { + /* Disable the SPI and reset the CRC: the CRC value should be cleared + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ + + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + } + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + __HAL_SPI_RESET_CRC(hspi); + } + + hspi->State= HAL_SPI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + + return HAL_OK; +} + +/** + * @brief This function handles SPI Communication Timeout. + * @param hspi: SPI handle + * @param Fifo: Fifo to check + * @param State: Fifo state to check + * @param Timeout : Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout) +{ + __IO uint8_t tmpreg; + uint32_t tickstart = HAL_GetTick(); + + while((hspi->Instance->SR & Fifo) != State) + { + if((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY)) + { + tmpreg = *((__IO uint8_t*)&hspi->Instance->DR); + } + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + { + /* Disable the SPI and reset the CRC: the CRC value should be cleared + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ + + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + } + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + __HAL_SPI_RESET_CRC(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + + return HAL_OK; +} + +/** + * @brief This function handles the check of the RX transaction complete. + * @param hspi: SPI handle + * @param Timeout : Timeout duration + */ +static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout) +{ + if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + } + if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK) + { + hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; + return HAL_TIMEOUT; + } + if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK) + { + hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; + return HAL_TIMEOUT; + } + + return HAL_OK; +} + +/** + * @brief This function handles the check of the RXTX or TX transaction complete. + * @param hspi: SPI handle + * @param Timeout : Timeout duration + */ +static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout) +{ + /* Procedure to check the transaction complete */ + if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout) != HAL_OK) + { + hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; + return HAL_TIMEOUT; + } + if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK) + { + hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; + return HAL_TIMEOUT; + } + if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK) + { + hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; + return HAL_TIMEOUT; + } + return HAL_OK; +} + +/** + * @brief This function handles the close of the RXTX transaction. + * @param hspi: SPI handle + */ +static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) +{ + /* Disable ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); + + /* Check the end of the transaction */ + SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT); + + /* Check if CRC error occurred */ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + hspi->State = HAL_SPI_STATE_READY; + hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + HAL_SPI_ErrorCallback(hspi); + } + else + { + if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) + { + if(hspi->State == HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_READY; + HAL_SPI_RxCpltCallback(hspi); + } + else + { + hspi->State = HAL_SPI_STATE_READY; + HAL_SPI_TxRxCpltCallback(hspi); + } + } + else + { + hspi->State = HAL_SPI_STATE_READY; + HAL_SPI_ErrorCallback(hspi); + } + } +} + +/** + * @brief This function handles the close of the RX transaction. + * @param hspi: SPI handle + */ +static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi) +{ + /* Disable RXNE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + /* Check the end of the transaction */ + SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT); + + hspi->State = HAL_SPI_STATE_READY; + + /* Check if CRC error occurred */ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + HAL_SPI_ErrorCallback(hspi); + } + else + { + if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) + { + HAL_SPI_RxCpltCallback(hspi); + } + else + { + HAL_SPI_ErrorCallback(hspi); + } + } +} + +/** + * @brief This function handles the close of the TX transaction. + * @param hspi: SPI handle + */ +static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi) +{ + /* Disable TXE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); + + /* Check the end of the transaction */ + SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT); + + /* Clear OVERUN flag in 2 Lines communication mode because received is not read */ + if(hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + HAL_SPI_ErrorCallback(hspi); + } + else + { + HAL_SPI_TxCpltCallback(hspi); + } +} + +/** + * @} + */ + +#endif /* HAL_SPI_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c @@ -0,0 +1,5305 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_tim.c + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer (TIM) peripheral: + * + Time Base Initialization + * + Time Base Start + * + Time Base Start Interruption + * + Time Base Start DMA + * + Time Output Compare/PWM Initialization + * + Time Output Compare/PWM Channel Configuration + * + Time Output Compare/PWM Start + * + Time Output Compare/PWM Start Interruption + * + Time Output Compare/PWM Start DMA + * + Time Input Capture Initialization + * + Time Input Capture Channel Configuration + * + Time Input Capture Start + * + Time Input Capture Start Interruption + * + Time Input Capture Start DMA + * + Time One Pulse Initialization + * + Time One Pulse Channel Configuration + * + Time One Pulse Start + * + Time Encoder Interface Initialization + * + Time Encoder Interface Start + * + Time Encoder Interface Start Interruption + * + Time Encoder Interface Start DMA + * + Commutation Event configuration with Interruption and DMA + * + Time OCRef clear configuration + * + Time External Clock configuration + @verbatim + ============================================================================== + ##### TIMER Generic features ##### + ============================================================================== + [..] The Timer features include: + (#) 16-bit up, down, up/down auto-reload counter. + (#) 16-bit programmable prescaler allowing dividing (also on the fly) the + counter clock frequency either by any factor between 1 and 65536. + (#) Up to 4 independent channels for: + (++) Input Capture + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending from feature used : + (++) Time Base : HAL_TIM_Base_MspInit() + (++) Input Capture : HAL_TIM_IC_MspInit() + (++) Output Compare : HAL_TIM_OC_MspInit() + (++) PWM generation : HAL_TIM_PWM_MspInit() + (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() + (++) Encoder mode output : HAL_TIM_Encoder_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + Initialization function of this driver: + (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base + (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an + Output Compare signal. + (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a + PWM signal. + (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an + external signal. + (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer + in One Pulse Mode. + (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. + + (#) Activate the TIM peripheral using one of the start functions depending from the feature used: + (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() + (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() + (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() + (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() + (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() + (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). + + (#) The DMA Burst is managed with the two following functions: + HAL_TIM_DMABurst_WriteStart() + HAL_TIM_DMABurst_ReadStart() + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup TIM TIM HAL module driver + * @brief TIM HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/** @defgroup TIM_Private_Functions TIM_Private_Functions + * @{ + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); +static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource); +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); +static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + TIM_SlaveConfigTypeDef * sSlaveConfig); + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup TIM_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @defgroup TIM_Exported_Functions_Group1 Time Base functions + * @brief Time Base functions + * +@verbatim + ============================================================================== + ##### Time Base functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM base. + (+) De-initialize the TIM base. + (+) Start the Time Base. + (+) Stop the Time Base. + (+) Start the Time Base and enable interrupt. + (+) Stop the Time Base and disable interrupt. + (+) Start the Time Base and enable DMA transfer. + (+) Stop the Time Base and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Time base Unit according to the specified + * parameters in the TIM_HandleTypeDef and create the associated handle. + * @param htim : TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if(htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + + if(htim->State == HAL_TIM_STATE_RESET) + { + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspInit(htim); + } + + /* Set the TIM state */ + htim->State= HAL_TIM_STATE_BUSY; + + /* Set the Time Base configuration */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the TIM state*/ + htim->State= HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Base peripheral + * @param htim : TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspDeInit(htim); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Base MSP. + * @param htim : TIM handle + * @retval None + */ +__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_Base_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Base MSP. + * @param htim : TIM handle + * @retval None + */ +__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_Base_MspDeInit could be implemented in the user file + */ +} + + +/** + * @brief Starts the TIM Base generation. + * @param htim : TIM handle + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Set the TIM state */ + htim->State= HAL_TIM_STATE_BUSY; + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Change the TIM state*/ + htim->State= HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation. + * @param htim : TIM handle + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Set the TIM state */ + htim->State= HAL_TIM_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the TIM state*/ + htim->State= HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in interrupt mode. + * @param htim : TIM handle + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Enable the TIM Update interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in interrupt mode. + * @param htim : TIM handle + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + /* Disable the TIM Update interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in DMA mode. + * @param htim : TIM handle + * @param pData : The source Buffer address. + * @param Length : The length of data to be transferred from memory to peripheral. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + if((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if((htim->State == HAL_TIM_STATE_READY)) + { + if((pData == 0 ) && (Length > 0)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length); + + /* Enable the TIM Update DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in DMA mode. + * @param htim : TIM handle + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions + * @brief Time Output Compare functions + * +@verbatim + ============================================================================== + ##### Time Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Output Compare. + (+) De-initialize the TIM Output Compare. + (+) Start the Time Output Compare. + (+) Stop the Time Output Compare. + (+) Start the Time Output Compare and enable interrupt. + (+) Stop the Time Output Compare and disable interrupt. + (+) Start the Time Output Compare and enable DMA transfer. + (+) Stop the Time Output Compare and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Output Compare according to the specified + * parameters in the TIM_HandleTypeDef and create the associated handle. + * @param htim : TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) +{ + /* Check the TIM handle allocation */ + if(htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + + if(htim->State == HAL_TIM_STATE_RESET) + { + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspInit(htim); + } + + /* Set the TIM state */ + htim->State= HAL_TIM_STATE_BUSY; + + /* Init the base time for the Output Compare */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the TIM state*/ + htim->State= HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim : TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspDeInit(htim); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Output Compare MSP. + * @param htim : TIM handle + * @retval None + */ +__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_OC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Output Compare MSP. + * @param htim : TIM handle + * @retval None + */ +__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_OC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Output Compare signal generation. + * @param htim : TIM Output Compare handle + * @param Channel : TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation. + * @param htim : TIM handle + * @param Channel : TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode. + * @param htim : TIM OC handle + * @param Channel : TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + } + break; + + default: + break; + } + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode. + * @param htim : TIM Output Compare handle + * @param Channel : TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + } + break; + + default: + break; + } + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode. + * @param htim : TIM Output Compare handle + * @param Channel : TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData : The source Buffer address. + * @param Length : The length of data to be transferred from memory to TIM peripheral + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + if((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if((htim->State == HAL_TIM_STATE_READY)) + { + if(((uint32_t)pData == 0 ) && (Length > 0)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); + + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); + + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); + + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + } + break; + + default: + break; + } + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode. + * @param htim : TIM Output Compare handle + * @param Channel : TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + } + break; + + default: + break; + } + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions + * @brief Time PWM functions + * +@verbatim + ============================================================================== + ##### Time PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM OPWM. + (+) De-initialize the TIM PWM. + (+) Start the Time PWM. + (+) Stop the Time PWM. + (+) Start the Time PWM and enable interrupt. + (+) Stop the Time PWM and disable interrupt. + (+) Start the Time PWM and enable DMA transfer. + (+) Stop the Time PWM and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM PWM Time Base according to the specified + * parameters in the TIM_HandleTypeDef and create the associated handle. + * @param htim : TIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if(htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + + if(htim->State == HAL_TIM_STATE_RESET) + { + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspInit(htim); + } + + /* Set the TIM state */ + htim->State= HAL_TIM_STATE_BUSY; + + /* Init the base time for the PWM */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the TIM state*/ + htim->State= HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim : TIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspDeInit(htim); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM PWM MSP. + * @param htim : TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM PWM MSP. + * @param htim : TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the PWM signal generation. + * @param htim : TIM handle + * @param Channel : TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation. + * @param htim : TIM handle + * @param Channel : TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode. + * @param htim : TIM handle + * @param Channel : TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + } + break; + + default: + break; + } + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode. + * @param htim : TIM handle + * @param Channel : TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + } + break; + + default: + break; + } + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode. + * @param htim : TIM handle + * @param Channel : TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData : The source Buffer address. + * @param Length : The length of data to be transferred from memory to TIM peripheral + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + if((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if((htim->State == HAL_TIM_STATE_READY)) + { + if(((uint32_t)pData == 0 ) && (Length > 0)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); + + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); + + /* Enable the TIM Output Capture/Compare 3 request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); + + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + } + break; + + default: + break; + } + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode. + * @param htim : TIM handle + * @param Channel : TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + } + break; + + default: + break; + } + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions + * @brief Time Input Capture functions + * +@verbatim + ============================================================================== + ##### Time Input Capture functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Input Capture. + (+) De-initialize the TIM Input Capture. + (+) Start the Time Input Capture. + (+) Stop the Time Input Capture. + (+) Start the Time Input Capture and enable interrupt. + (+) Stop the Time Input Capture and disable interrupt. + (+) Start the Time Input Capture and enable DMA transfer. + (+) Stop the Time Input Capture and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Input Capture Time base according to the specified + * parameters in the TIM_HandleTypeDef and create the associated handle. + * @param htim : TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if(htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + + if(htim->State == HAL_TIM_STATE_RESET) + { + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspInit(htim); + } + + /* Set the TIM state */ + htim->State= HAL_TIM_STATE_BUSY; + + /* Init the base time for the input capture */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the TIM state*/ + htim->State= HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim : TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspDeInit(htim); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Input Capture MSP. + * @param htim : TIM handle + * @retval None + */ +__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_IC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Input Capture MSP. + * @param htim : TIM handle + * @retval None + */ +__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_IC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Input Capture measurement. + * @param htim : TIM Input Capture handle + * @param Channel : TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement. + * @param htim : TIM handle + * @param Channel : TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Input Capture measurement in interrupt mode. + * @param htim : TIM Input Capture handle + * @param Channel : TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + } + break; + + default: + break; + } + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement in interrupt mode. + * @param htim : TIM handle + * @param Channel : TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + } + break; + + default: + break; + } + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Input Capture measurement in DMA mode. + * @param htim : TIM Input Capture handle + * @param Channel : TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData : The destination Buffer address. + * @param Length : The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + if((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if((htim->State == HAL_TIM_STATE_READY)) + { + if((pData == 0 ) && (Length > 0)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length); + + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length); + + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length); + + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + } + break; + + default: + break; + } + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement in DMA mode. + * @param htim : TIM Input Capture handle + * @param Channel : TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + } + break; + + default: + break; + } + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions + * @brief Time One Pulse functions + * +@verbatim + ============================================================================== + ##### Time One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM One Pulse. + (+) De-initialize the TIM One Pulse. + (+) Start the Time One Pulse. + (+) Stop the Time One Pulse. + (+) Start the Time One Pulse and enable interrupt. + (+) Stop the Time One Pulse and disable interrupt. + (+) Start the Time One Pulse and enable DMA transfer. + (+) Stop the Time One Pulse and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM One Pulse Time Base according to the specified + * parameters in the TIM_HandleTypeDef and create the associated handle. + * @param htim : TIM OnePulse handle + * @param OnePulseMode : Select the One pulse mode. + * This parameter can be one of the following values: + * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. + * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) +{ + /* Check the TIM handle allocation */ + if(htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_OPM_MODE(OnePulseMode)); + + if(htim->State == HAL_TIM_STATE_RESET) + { + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OnePulse_MspInit(htim); + } + + /* Set the TIM state */ + htim->State= HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the One Pulse Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Reset the OPM Bit */ + htim->Instance->CR1 &= ~TIM_CR1_OPM; + + /* Configure the OPM Mode */ + htim->Instance->CR1 |= OnePulseMode; + + /* Initialize the TIM state*/ + htim->State= HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM One Pulse + * @param htim : TIM One Pulse handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_OnePulse_MspDeInit(htim); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM One Pulse MSP. + * @param htim : TIM handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM One Pulse MSP. + * @param htim : TIM handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM One Pulse signal generation. + * @param htim : TIM One Pulse handle + * @param OutputChannel : TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation. + * @param htim : TIM One Pulse handle + * @param OutputChannel : TIM Channels to be disable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode. + * @param htim : TIM One Pulse handle + * @param OutputChannel : TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode. + * @param htim : TIM One Pulse handle + * @param OutputChannel : TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions + * @brief Time Encoder functions + * +@verbatim + ============================================================================== + ##### Time Encoder functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Encoder. + (+) De-initialize the TIM Encoder. + (+) Start the Time Encoder. + (+) Stop the Time Encoder. + (+) Start the Time Encoder and enable interrupt. + (+) Stop the Time Encoder and disable interrupt. + (+) Start the Time Encoder and enable DMA transfer. + (+) Stop the Time Encoder and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Encoder Interface and create the associated handle. + * @param htim : TIM Encoder Interface handle + * @param sConfig : TIM Encoder Interface configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig) +{ + uint32_t tmpsmcr = 0; + uint32_t tmpccmr1 = 0; + uint32_t tmpccer = 0; + + /* Check the TIM handle allocation */ + if(htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); + assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); + + if(htim->State == HAL_TIM_STATE_RESET) + { + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_Encoder_MspInit(htim); + } + + /* Set the TIM state */ + htim->State= HAL_TIM_STATE_BUSY; + + /* Reset the SMS bits */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = htim->Instance->CCMR1; + + /* Get the TIMx CCER register value */ + tmpccer = htim->Instance->CCER; + + /* Set the encoder Mode */ + tmpsmcr |= sConfig->EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); + tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8)); + + /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ + tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); + tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); + tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8); + tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12); + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); + tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); + tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4); + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Write to TIMx CCMR1 */ + htim->Instance->CCMR1 = tmpccmr1; + + /* Write to TIMx CCER */ + htim->Instance->CCER = tmpccer; + + /* Initialize the TIM state*/ + htim->State= HAL_TIM_STATE_READY; + + return HAL_OK; +} + + +/** + * @brief DeInitializes the TIM Encoder interface + * @param htim : TIM Encoder handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Encoder_MspDeInit(htim); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Encoder Interface MSP. + * @param htim : TIM handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Encoder Interface MSP. + * @param htim : TIM handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Encoder Interface. + * @param htim : TIM Encoder Interface handle + * @param Channel : TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Enable the encoder interface channels */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + break; + } + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + } + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface. + * @param htim : TIM Encoder Interface handle + * @param Channel : TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + break; + } + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in interrupt mode. + * @param htim : TIM Encoder Interface handle + * @param Channel : TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Enable the encoder interface channels */ + /* Enable the capture compare Interrupts 1 and/or 2 */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + } + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in interrupt mode. + * @param htim : TIM Encoder Interface handle + * @param Channel : TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if(Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + } + else if(Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 and 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in DMA mode. + * @param htim : TIM Encoder Interface handle + * @param Channel : TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param pData1 : The destination Buffer address for IC1. + * @param pData2 : The destination Buffer address for IC2. + * @param Length : The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + if((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if((htim->State == HAL_TIM_STATE_READY)) + { + if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length); + + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + } + break; + + case TIM_CHANNEL_2: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError; + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length); + + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + } + break; + + case TIM_CHANNEL_ALL: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length); + + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + } + break; + + default: + break; + } + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in DMA mode. + * @param htim : TIM Encoder Interface handle + * @param Channel : TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if(Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + } + else if(Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 and 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ +/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief IRQ handler management + * +@verbatim + ============================================================================== + ##### IRQ handler management ##### + ============================================================================== + [..] + This section provides Timer IRQ handler function. + +@endverbatim + * @{ + */ +/** + * @brief This function handles TIM interrupts requests. + * @param htim : TIM handle + * @retval None + */ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) +{ + /* Capture compare 1 event */ + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) + { + if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC1) !=RESET) + { + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + /* Input capture event */ + if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00) + { + HAL_TIM_IC_CaptureCallback(htim); + } + /* Output compare event */ + else + { + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + } + /* Capture compare 2 event */ + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) + { + if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC2) !=RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + /* Input capture event */ + if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00) + { + HAL_TIM_IC_CaptureCallback(htim); + } + /* Output compare event */ + else + { + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 3 event */ + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) + { + if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC3) !=RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + /* Input capture event */ + if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00) + { + HAL_TIM_IC_CaptureCallback(htim); + } + /* Output compare event */ + else + { + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 4 event */ + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) + { + if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC4) !=RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + /* Input capture event */ + if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00) + { + HAL_TIM_IC_CaptureCallback(htim); + } + /* Output compare event */ + else + { + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* TIM Update event */ + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) + { + if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_UPDATE) !=RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); + HAL_TIM_PeriodElapsedCallback(htim); + } + } + /* TIM Break input event */ + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) + { + if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_BREAK) !=RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); + HAL_TIMEx_BreakCallback(htim); + } + } + /* TIM Trigger detection event */ + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) + { + if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_TRIGGER) !=RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); + HAL_TIM_TriggerCallback(htim); + } + } + /* TIM commutation event */ + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) + { + if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_COM) !=RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); + HAL_TIMEx_CommutationCallback(htim); + } + } +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. + (+) Configure External Clock source. + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master and the Slave synchronization. + (+) Configure the DMA Burst Mode. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the TIM Output Compare Channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim : TIM Output Compare handle + * @param sConfig : TIM Output Compare configuration structure + * @param Channel : TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState)); + + /* Check input state */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + switch (Channel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + /* Configure the TIM Channel 1 in Output Compare */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + } + break; + + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + /* Configure the TIM Channel 2 in Output Compare */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + } + break; + + case TIM_CHANNEL_3: + { + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + /* Configure the TIM Channel 3 in Output Compare */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + } + break; + + case TIM_CHANNEL_4: + { + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + /* Configure the TIM Channel 4 in Output Compare */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + } + break; + + default: + break; + } + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Input Capture Channels according to the specified + * parameters in the TIM_IC_InitTypeDef. + * @param htim : TIM IC handle + * @param sConfig : TIM Input Capture configuration structure + * @param Channel : TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); + assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if (Channel == TIM_CHANNEL_1) + { + /* TI1 Configuration */ + TIM_TI1_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->ICPrescaler; + } + else if (Channel == TIM_CHANNEL_2) + { + /* TI2 Configuration */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Set the IC2PSC value */ + htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8); + } + else if (Channel == TIM_CHANNEL_3) + { + /* TI3 Configuration */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + TIM_TI3_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC3PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; + + /* Set the IC3PSC value */ + htim->Instance->CCMR2 |= sConfig->ICPrescaler; + } + else + { + /* TI4 Configuration */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + TIM_TI4_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC4PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; + + /* Set the IC4PSC value */ + htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8); + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM PWM channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim : TIM handle + * @param sConfig : TIM PWM configuration structure + * @param Channel : TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel) +{ + __HAL_LOCK(htim); + + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity)); + assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); + assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState)); + + htim->State = HAL_TIM_STATE_BUSY; + + switch (Channel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + /* Configure the Channel 1 in PWM mode */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel1 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode; + } + break; + + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + /* Configure the Channel 2 in PWM mode */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel2 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode << 8; + } + break; + + case TIM_CHANNEL_3: + { + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + /* Configure the Channel 3 in PWM mode */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel3 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode; + } + break; + + case TIM_CHANNEL_4: + { + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + /* Configure the Channel 4 in PWM mode */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel4 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode << 8; + } + break; + + default: + break; + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM One Pulse Channels according to the specified + * parameters in the TIM_OnePulse_InitTypeDef. + * @param htim : TIM One Pulse handle + * @param sConfig : TIM One Pulse configuration structure + * @param OutputChannel : TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param InputChannel : TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel) +{ + TIM_OC_InitTypeDef temp1; + + /* Check the parameters */ + assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); + assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); + + if(OutputChannel != InputChannel) + { + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Extract the Ouput compare configuration from sConfig structure */ + temp1.OCMode = sConfig->OCMode; + temp1.Pulse = sConfig->Pulse; + temp1.OCPolarity = sConfig->OCPolarity; + temp1.OCNPolarity = sConfig->OCNPolarity; + temp1.OCIdleState = sConfig->OCIdleState; + temp1.OCNIdleState = sConfig->OCNIdleState; + + switch (OutputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_OC1_SetConfig(htim->Instance, &temp1); + } + break; + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_OC2_SetConfig(htim->Instance, &temp1); + } + break; + default: + break; + } + switch (InputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1FP1; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + } + break; + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI2FP2; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + } + break; + + default: + break; + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + else + { + return HAL_ERROR; + } +} + +/** + * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral + * @param htim : TIM handle + * @param BurstBaseAddress : TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABase_CR1 + * @arg TIM_DMABase_CR2 + * @arg TIM_DMABase_SMCR + * @arg TIM_DMABase_DIER + * @arg TIM_DMABase_SR + * @arg TIM_DMABase_EGR + * @arg TIM_DMABase_CCMR1 + * @arg TIM_DMABase_CCMR2 + * @arg TIM_DMABase_CCER + * @arg TIM_DMABase_CNT + * @arg TIM_DMABase_PSC + * @arg TIM_DMABase_ARR + * @arg TIM_DMABase_RCR + * @arg TIM_DMABase_CCR1 + * @arg TIM_DMABase_CCR2 + * @arg TIM_DMABase_CCR3 + * @arg TIM_DMABase_CCR4 + * @arg TIM_DMABase_BDTR + * @arg TIM_DMABase_DCR + * @param BurstRequestSrc : TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer : The Buffer address. + * @param BurstLength : DMA Burst length. This parameter can be one value + * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, + uint32_t* BurstBuffer, uint32_t BurstLength) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + + if((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if((htim->State == HAL_TIM_STATE_READY)) + { + if((BurstBuffer == 0 ) && (BurstLength > 0)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + switch(BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + } + break; + case TIM_DMA_CC1: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + } + break; + case TIM_DMA_CC2: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + } + break; + case TIM_DMA_CC3: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + } + break; + case TIM_DMA_CC4: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + } + break; + case TIM_DMA_COM: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + } + break; + case TIM_DMA_TRIGGER: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + } + break; + default: + break; + } + /* configure the DMA Burst Mode */ + htim->Instance->DCR = BurstBaseAddress | BurstLength; + + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM DMA Burst mode + * @param htim : TIM handle + * @param BurstRequestSrc : TIM DMA Request sources to disable + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA channel) */ + switch(BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]); + } + break; + case TIM_DMA_CC1: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]); + } + break; + case TIM_DMA_CC2: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]); + } + break; + case TIM_DMA_CC3: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]); + } + break; + case TIM_DMA_CC4: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]); + } + break; + case TIM_DMA_COM: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]); + } + break; + case TIM_DMA_TRIGGER: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]); + } + break; + default: + break; + } + + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @param htim : TIM handle + * @param BurstBaseAddress : TIM Base address from where the DMA will starts the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABase_CR1 + * @arg TIM_DMABase_CR2 + * @arg TIM_DMABase_SMCR + * @arg TIM_DMABase_DIER + * @arg TIM_DMABase_SR + * @arg TIM_DMABase_EGR + * @arg TIM_DMABase_CCMR1 + * @arg TIM_DMABase_CCMR2 + * @arg TIM_DMABase_CCER + * @arg TIM_DMABase_CNT + * @arg TIM_DMABase_PSC + * @arg TIM_DMABase_ARR + * @arg TIM_DMABase_RCR + * @arg TIM_DMABase_CCR1 + * @arg TIM_DMABase_CCR2 + * @arg TIM_DMABase_CCR3 + * @arg TIM_DMABase_CCR4 + * @arg TIM_DMABase_BDTR + * @arg TIM_DMABase_DCR + * @param BurstRequestSrc : TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer : The Buffer address. + * @param BurstLength : DMA Burst length. This parameter can be one value + * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, + uint32_t *BurstBuffer, uint32_t BurstLength) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + + if((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if((htim->State == HAL_TIM_STATE_READY)) + { + if((BurstBuffer == 0 ) && (BurstLength > 0)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + switch(BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + } + break; + case TIM_DMA_CC1: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + } + break; + case TIM_DMA_CC2: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + } + break; + case TIM_DMA_CC3: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + } + break; + case TIM_DMA_CC4: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + } + break; + case TIM_DMA_COM: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + } + break; + case TIM_DMA_TRIGGER: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + } + break; + default: + break; + } + + /* configure the DMA Burst Mode */ + htim->Instance->DCR = BurstBaseAddress | BurstLength; + + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop the DMA burst reading + * @param htim : TIM handle + * @param BurstRequestSrc : TIM DMA Request sources to disable. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA channel) */ + switch(BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]); + } + break; + case TIM_DMA_CC1: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]); + } + break; + case TIM_DMA_CC2: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]); + } + break; + case TIM_DMA_CC3: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]); + } + break; + case TIM_DMA_CC4: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]); + } + break; + case TIM_DMA_COM: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]); + } + break; + case TIM_DMA_TRIGGER: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]); + } + break; + default: + break; + } + + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Generate a software event + * @param htim : TIM handle + * @param EventSource : specifies the event source. + * This parameter can be one of the following values: + * @arg TIM_EventSource_Update: Timer update Event source + * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source + * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source + * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source + * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source + * @arg TIM_EventSource_COM: Timer COM event source + * @arg TIM_EventSource_Trigger: Timer Trigger Event source + * @arg TIM_EventSource_Break: Timer Break event source + * @note TIM6 and TIM7 can only generate an update event. + * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1, TIM15, TIM16 and TIM17. + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_EVENT_SOURCE(EventSource)); + + /* Process Locked */ + __HAL_LOCK(htim); + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the event sources */ + htim->Instance->EGR = EventSource; + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configures the OCRef clear feature + * @param htim : TIM handle + * @param sClearInputConfig : pointer to a TIM_ClearInputConfigTypeDef structure that + * contains the OCREF clear feature and parameters for the TIM peripheral. + * @param Channel : specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_Channel_1: TIM Channel 1 + * @arg TIM_Channel_2: TIM Channel 2 + * @arg TIM_Channel_3: TIM Channel 3 + * @arg TIM_Channel_4: TIM Channel 4 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel) +{ + uint32_t tmpsmcr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); + assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); + assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); + assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + switch (sClearInputConfig->ClearInputSource) + { + case TIM_CLEARINPUTSOURCE_NONE: + { + /* Clear the OCREF clear selection bit */ + tmpsmcr &= ~TIM_SMCR_OCCS; + + /* Clear the ETR Bits */ + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + + /* Set TIMx_SMCR */ + htim->Instance->SMCR = tmpsmcr; + } + break; + + case TIM_CLEARINPUTSOURCE_ETR: + { + TIM_ETR_SetConfig(htim->Instance, + sClearInputConfig->ClearInputPrescaler, + sClearInputConfig->ClearInputPolarity, + sClearInputConfig->ClearInputFilter); + + /* Set the OCREF clear selection bit */ + htim->Instance->SMCR |= TIM_SMCR_OCCS; + } + break; + default: + break; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + if(sClearInputConfig->ClearInputState != RESET) + { + /* Enable the Ocref clear feature for Channel 1 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE; + } + else + { + /* Disable the Ocref clear feature for Channel 1 */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE; + } + } + break; + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + if(sClearInputConfig->ClearInputState != RESET) + { + /* Enable the Ocref clear feature for Channel 2 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE; + } + else + { + /* Disable the Ocref clear feature for Channel 2 */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE; + } + } + break; + case TIM_CHANNEL_3: + { + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + if(sClearInputConfig->ClearInputState != RESET) + { + /* Enable the Ocref clear feature for Channel 3 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE; + } + else + { + /* Disable the Ocref clear feature for Channel 3 */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE; + } + } + break; + case TIM_CHANNEL_4: + { + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + if(sClearInputConfig->ClearInputState != RESET) + { + /* Enable the Ocref clear feature for Channel 4 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE; + } + else + { + /* Disable the Ocref clear feature for Channel 4 */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE; + } + } + break; + default: + break; + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the clock source to be used + * @param htim : TIM handle + * @param sClockSourceConfig : pointer to a TIM_ClockConfigTypeDef structure that + * contains the clock source information for the TIM peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig) +{ + uint32_t tmpsmcr = 0; + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ + tmpsmcr = htim->Instance->SMCR; + tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + htim->Instance->SMCR = tmpsmcr; + + switch (sClockSourceConfig->ClockSource) + { + case TIM_CLOCKSOURCE_INTERNAL: + { + assert_param(IS_TIM_INSTANCE(htim->Instance)); + /* Disable slave mode to clock the prescaler directly with the internal clock */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + } + break; + + case TIM_CLOCKSOURCE_ETRMODE1: + { + /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + /* Reset the SMS and TS Bits */ + tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + /* Select the External clock mode1 and the ETRF trigger */ + tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + } + break; + + case TIM_CLOCKSOURCE_ETRMODE2: + { + /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + /* Enable the External clock mode2 */ + htim->Instance->SMCR |= TIM_SMCR_ECE; + } + break; + + case TIM_CLOCKSOURCE_TI1: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); + } + break; + case TIM_CLOCKSOURCE_TI2: + { + /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + TIM_TI2_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); + } + break; + case TIM_CLOCKSOURCE_TI1ED: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); + } + break; + case TIM_CLOCKSOURCE_ITR0: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0); + } + break; + case TIM_CLOCKSOURCE_ITR1: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1); + } + break; + case TIM_CLOCKSOURCE_ITR2: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2); + } + break; + case TIM_CLOCKSOURCE_ITR3: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3); + } + break; + + default: + break; + } + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Selects the signal connected to the TI1 input: direct from CH1_input + * or a XOR combination between CH1_input, CH2_input & CH3_input + * @param htim : TIM handle. + * @param TI1_Selection : Indicate whether or not channel 1 is connected to the + * output of a XOR gate. + * This parameter can be one of the following values: + * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input + * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 + * pins are connected to the TI1 input (XOR combination) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) +{ + uint32_t tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + + /* Reset the TI1 selection */ + tmpcr2 &= ~TIM_CR2_TI1S; + + /* Set the the TI1 selection */ + tmpcr2 |= TI1_Selection; + + /* Write to TIMxCR2 */ + htim->Instance->CR2 = tmpcr2; + + return HAL_OK; +} + +/** + * @brief Configures the TIM in Slave mode + * @param htim : TIM handle. + * @param sSlaveConfig : pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the ) and the Slave + * mode (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + TIM_SlaveTimer_SetConfig(htim, sSlaveConfig); + + /* Disable Trigger Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; + } + +/** + * @brief Configures the TIM in Slave mode in interrupt mode + * @param htim: TIM handle. + * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the ) and the Slave + * mode (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, + TIM_SlaveConfigTypeDef * sSlaveConfig) + { + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + TIM_SlaveTimer_SetConfig(htim, sSlaveConfig); + + /* Enable Trigger Interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Read the captured value from Capture Compare unit + * @param htim : TIM handle. + * @param Channel : TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1 : TIM Channel 1 selected + * @arg TIM_CHANNEL_2 : TIM Channel 2 selected + * @arg TIM_CHANNEL_3 : TIM Channel 3 selected + * @arg TIM_CHANNEL_4 : TIM Channel 4 selected + * @retval Captured value + */ +uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpreg = 0; + + __HAL_LOCK(htim); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Return the capture 1 value */ + tmpreg = htim->Instance->CCR1; + + break; + } + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Return the capture 2 value */ + tmpreg = htim->Instance->CCR2; + + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Return the capture 3 value */ + tmpreg = htim->Instance->CCR3; + + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Return the capture 4 value */ + tmpreg = htim->Instance->CCR4; + + break; + } + + default: + break; + } + + __HAL_UNLOCK(htim); + return tmpreg; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions + * @brief TIM Callbacks functions + * +@verbatim + ============================================================================== + ##### TIM Callbacks functions ##### + ============================================================================== + [..] + This section provides TIM callback functions: + (+) Timer Period elapsed callback + (+) Timer Output Compare callback + (+) Timer Input capture callback + (+) Timer Trigger callback + (+) Timer Error callback + +@endverbatim + * @{ + */ + +/** + * @brief Period elapsed callback in non blocking mode + * @param htim : TIM handle + * @retval None + */ +__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file + */ + +} +/** + * @brief Output Compare callback in non blocking mode + * @param htim : TIM OC handle + * @retval None + */ +__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file + */ +} +/** + * @brief Input Capture callback in non blocking mode + * @param htim : TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the __HAL_TIM_IC_CaptureCallback could be implemented in the user file + */ +} + +/** + * @brief PWM Pulse finished callback in non blocking mode + * @param htim : TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Trigger detection callback in non blocking mode + * @param htim : TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_TriggerCallback could be implemented in the user file + */ +} + +/** + * @brief Timer error callback in non blocking mode + * @param htim : TIM handle + * @retval None + */ +__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State functions ##### + ============================================================================== + [..] + This subsection permit to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Base state + * @param htim : TIM Base handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM OC state + * @param htim : TIM Ouput Compare handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM PWM state + * @param htim : TIM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Input Capture state + * @param htim : TIM IC handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM One Pulse Mode state + * @param htim : TIM OPM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Encoder Mode state + * @param htim : TIM Encoder handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup TIM_Private_Functions TIM_Private_Functions + * @{ + */ + +/** + * @brief TIM DMA error callback + * @param hdma : pointer to DMA handle. + * @retval None + */ +void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + htim->State= HAL_TIM_STATE_READY; + + HAL_TIM_ErrorCallback(htim); +} + +/** + * @brief TIM DMA Delay Pulse complete callback. + * @param hdma : pointer to DMA handle. + * @retval None + */ +void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + htim->State= HAL_TIM_STATE_READY; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + + HAL_TIM_PWM_PulseFinishedCallback(htim); + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} +/** + * @brief TIM DMA Capture complete callback. + * @param hdma : pointer to DMA handle. + * @retval None + */ +void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + htim->State= HAL_TIM_STATE_READY; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + + HAL_TIM_IC_CaptureCallback(htim); + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Period Elapse complete callback. + * @param hdma : pointer to DMA handle. + * @retval None + */ +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + htim->State= HAL_TIM_STATE_READY; + + HAL_TIM_PeriodElapsedCallback(htim); +} + +/** + * @brief TIM DMA Trigger callback. + * @param hdma : pointer to DMA handle. + * @retval None + */ +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + htim->State= HAL_TIM_STATE_READY; + + HAL_TIM_TriggerCallback(htim); +} + +/** + * @brief Time Base configuration + * @param TIMx : TIM periheral + * @param Structure : TIM Base configuration structure + * @retval None + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) +{ + uint32_t tmpcr1 = 0; + tmpcr1 = TIMx->CR1; + + /* Set TIM Time Base Unit parameters ---------------------------------------*/ + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + { + /* Select the Counter Mode */ + tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); + tmpcr1 |= Structure->CounterMode; + } + + if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + { + /* Set the clock division */ + tmpcr1 &= ~TIM_CR1_CKD; + tmpcr1 |= (uint32_t)Structure->ClockDivision; + } + + TIMx->CR1 = tmpcr1; + + /* Set the Autoreload value */ + TIMx->ARR = (uint32_t)Structure->Period ; + + /* Set the Prescaler value */ + TIMx->PSC = (uint32_t)Structure->Prescaler; + + if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) + { + /* Set the Repetition Counter value */ + TIMx->RCR = Structure->RepetitionCounter; + } + + /* Generate an update event to reload the Prescaler + and the repetition counter(only for TIM1 and TIM8) value immediatly */ + TIMx->EGR = TIM_EGR_UG; +} + +/** + * @brief Time Ouput Compare 1 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config : The ouput configuration structure + * @retval None + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx = 0; + uint32_t tmpccer = 0; + uint32_t tmpcr2 = 0; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~TIM_CCMR1_OC1M; + tmpccmrx &= ~TIM_CCMR1_CC1S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC1P; + /* Set the Output Compare Polarity */ + tmpccer |= OC_Config->OCPolarity; + + if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) + { + /* Check parameters */ + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC1NP; + /* Set the Output N Polarity */ + tmpccer |= OC_Config->OCNPolarity; + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC1NE; + } + + if(IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS1; + tmpcr2 &= ~TIM_CR2_OIS1N; + /* Set the Output Idle state */ + tmpcr2 |= OC_Config->OCIdleState; + /* Set the Output N Idle state */ + tmpcr2 |= OC_Config->OCNIdleState; + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Time Ouput Compare 2 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config : The ouput configuration structure + * @retval None + */ +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx = 0; + uint32_t tmpccer = 0; + uint32_t tmpcr2 = 0; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR1_OC2M; + tmpccmrx &= ~TIM_CCMR1_CC2S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC2P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 4); + + if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC2NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 4); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC2NE; + + } + + if(IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS2; + tmpcr2 &= ~TIM_CR2_OIS2N; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 2); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 2); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Time Ouput Compare 3 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config : The ouput configuration structure + * @retval None + */ +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx = 0; + uint32_t tmpccer = 0; + uint32_t tmpcr2 = 0; + + /* Disable the Channel 3: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC3M; + tmpccmrx &= ~TIM_CCMR2_CC3S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC3P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 8); + + if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC3NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 8); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC3NE; + } + + if(IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS3; + tmpcr2 &= ~TIM_CR2_OIS3N; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 4); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 4); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Time Ouput Compare 4 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config : The ouput configuration structure + * @retval None + */ +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx = 0; + uint32_t tmpccer = 0; + uint32_t tmpcr2 = 0; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC4M; + tmpccmrx &= ~TIM_CCMR2_CC4S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC4P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 12); + + if(IS_TIM_BREAK_INSTANCE(TIMx)) + { + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS4; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 6); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + TIM_SlaveConfigTypeDef * sSlaveConfig) +{ + uint32_t tmpsmcr = 0; + uint32_t tmpccmr1 = 0; + uint32_t tmpccer = 0; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Reset the Trigger Selection Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source */ + tmpsmcr |= sSlaveConfig->InputTrigger; + + /* Reset the slave mode Bits */ + tmpsmcr &= ~TIM_SMCR_SMS; + /* Set the slave mode */ + tmpsmcr |= sSlaveConfig->SlaveMode; + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Configure the trigger prescaler, filter, and polarity */ + switch (sSlaveConfig->InputTrigger) + { + case TIM_TS_ETRF: + { + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + /* Configure the ETR Trigger source */ + TIM_ETR_SetConfig(htim->Instance, + sSlaveConfig->TriggerPrescaler, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + } + break; + + case TIM_TS_TI1F_ED: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = htim->Instance->CCER; + htim->Instance->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = htim->Instance->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4); + + /* Write to TIMx CCMR1 and CCER registers */ + htim->Instance->CCMR1 = tmpccmr1; + htim->Instance->CCER = tmpccer; + + } + break; + + case TIM_TS_TI1FP1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI1 Filter and Polarity */ + TIM_TI1_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + } + break; + + case TIM_TS_TI2FP2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI2 Filter and Polarity */ + TIM_TI2_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + } + break; + + case TIM_TS_ITR0: + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + } + break; + + case TIM_TS_ITR1: + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + } + break; + + case TIM_TS_ITR2: + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + } + break; + + case TIM_TS_ITR3: + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + } + break; + + default: + break; + } +} + +/** + * @brief Configure the TI1 as Input. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @arg TIM_ICPolarity_BothEdge + * @param TIM_ICSelection : specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI : TIM Input 1 is selected to be connected to IC1. + * @arg TIM_ICSelection_IndirectTI : TIM Input 1 is selected to be connected to IC2. + * @arg TIM_ICSelection_TRC : TIM Input 1 is selected to be connected to TRC. + * @param TIM_ICFilter : Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 + * (on channel2 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. + */ +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1 = 0; + uint32_t tmpccer = 0; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Select the Input */ + if(IS_TIM_CC2_INSTANCE(TIMx) != RESET) + { + tmpccmr1 &= ~TIM_CCMR1_CC1S; + tmpccmr1 |= TIM_ICSelection; + } + else + { + tmpccmr1 |= TIM_CCMR1_CC1S_0; + } + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI1. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @arg TIM_ICPolarity_BothEdge + * @param TIM_ICFilter : Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1 = 0; + uint32_t tmpccer = 0; + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= (TIM_ICFilter << 4); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= TIM_ICPolarity; + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @arg TIM_ICPolarity_BothEdge + * @param TIM_ICSelection : specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI : TIM Input 2 is selected to be connected to IC2. + * @arg TIM_ICSelection_IndirectTI : TIM Input 2 is selected to be connected to IC1. + * @arg TIM_ICSelection_TRC : TIM Input 2 is selected to be connected to TRC. + * @param TIM_ICFilter : Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 + * (on channel1 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. + */ +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1 = 0; + uint32_t tmpccer = 0; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr1 &= ~TIM_CCMR1_CC2S; + tmpccmr1 |= (TIM_ICSelection << 8); + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI2. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @arg TIM_ICPolarity_BothEdge + * @param TIM_ICFilter : Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1 = 0; + uint32_t tmpccer = 0; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= (TIM_ICFilter << 12); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= (TIM_ICPolarity << 4); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @arg TIM_ICPolarity_BothEdge + * @param TIM_ICSelection : specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI : TIM Input 3 is selected to be connected to IC3. + * @arg TIM_ICSelection_IndirectTI : TIM Input 3 is selected to be connected to IC4. + * @arg TIM_ICSelection_TRC : TIM Input 3 is selected to be connected to TRC. + * @param TIM_ICFilter : Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. + */ +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2 = 0; + uint32_t tmpccer = 0; + + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC3S; + tmpccmr2 |= TIM_ICSelection; + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC3F; + tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F); + + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); + tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI4 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @arg TIM_ICPolarity_BothEdge + * @param TIM_ICSelection : specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI : TIM Input 4 is selected to be connected to IC4. + * @arg TIM_ICSelection_IndirectTI : TIM Input 4 is selected to be connected to IC3. + * @arg TIM_ICSelection_TRC : TIM Input 4 is selected to be connected to TRC. + * @param TIM_ICFilter : Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. + * @retval None + */ +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2 = 0; + uint32_t tmpccer = 0; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC4S; + tmpccmr2 |= (TIM_ICSelection << 8); + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC4F; + tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F); + + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); + tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer ; +} + +/** + * @brief Selects the Input Trigger source + * @param TIMx to select the TIM peripheral + * @param InputTriggerSource : The Input Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0 : Internal Trigger 0 + * @arg TIM_TS_ITR1 : Internal Trigger 1 + * @arg TIM_TS_ITR2 : Internal Trigger 2 + * @arg TIM_TS_ITR3 : Internal Trigger 3 + * @arg TIM_TS_TI1F_ED : TI1 Edge Detector + * @arg TIM_TS_TI1FP1 : Filtered Timer Input 1 + * @arg TIM_TS_TI2FP2 : Filtered Timer Input 2 + * @arg TIM_TS_ETRF : External Trigger input + * @retval None + */ +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource) +{ + uint32_t tmpsmcr = 0; + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the TS Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source and the slave mode*/ + tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1; + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} +/** + * @brief Configures the TIMx External Trigger (ETR). + * @param TIMx to select the TIM peripheral + * @param TIM_ExtTRGPrescaler : The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPSC_DIV1 : ETRP Prescaler OFF. + * @arg TIM_ExtTRGPSC_DIV2 : ETRP frequency divided by 2. + * @arg TIM_ExtTRGPSC_DIV4 : ETRP frequency divided by 4. + * @arg TIM_ExtTRGPSC_DIV8 : ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity : The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPolarity_Inverted : active low or falling edge active. + * @arg TIM_ExtTRGPolarity_NonInverted : active high or rising edge active. + * @param ExtTRGFilter : External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +{ + uint32_t tmpsmcr = 0; + + tmpsmcr = TIMx->SMCR; + + /* Reset the ETR Bits */ + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8))); + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel x. + * @param TIMx to select the TIM peripheral + * @param Channel : specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_Channel_1 : TIM Channel 1 + * @arg TIM_Channel_2 : TIM Channel 2 + * @arg TIM_Channel_3 : TIM Channel 3 + * @arg TIM_Channel_4 : TIM Channel 4 + * @param ChannelState : specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable. + * @retval None + */ +void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState) +{ + uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_TIM_CHANNELS(Channel)); + + tmp = TIM_CCER_CC1E << Channel; + + /* Reset the CCxE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint32_t)(ChannelState << Channel); +} + + +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c @@ -0,0 +1,1835 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_tim_ex.c + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer Extended peripheral: + * + Time Hall Sensor Interface Initialization + * + Time Hall Sensor Interface Start + * + Time Complementary signal bread and dead time configuration + * + Time Master and Slave synchronization configuration + * + Timer remapping capabilities configuration + @verbatim + ============================================================================== + ##### TIMER Extended features ##### + ============================================================================== + [..] + The Timer Extended features include: + (#) Complementary outputs with programmable dead-time for : + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + (#) Synchronization circuit to control the timer with external signals and to + interconnect several timers together. + (#) Break input to put the timer output signals in reset state or in a known state. + (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for + positioning purposes + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending from feature used : + (++) Complementary Output Compare : HAL_TIM_OC_MspInit() + (++) Complementary PWM generation : HAL_TIM_PWM_MspInit() + (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit() + (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + initialization function of this driver: + (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the + Timer Hall Sensor Interface and the commutation event with the corresponding + Interrupt and DMA request if needed (Note that One Timer is used to interface + with the Hall sensor Interface and another Timer should be used to use + the commutation event). + + (#) Activate the TIM peripheral using one of the start functions: + (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT() + (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT() + (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() + (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(). + + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** +*/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup TIMEx TIMEx Extended HAL module driver + * @brief TIM Extended HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/** @defgroup TIMEx_Private_Functions TIMEx Private Functions + * @{ + */ +static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions + * @{ + */ + +/** @defgroup TIMEx_Exported_Functions_Group1 Timer Hall Sensor functions + * @brief Timer Hall Sensor functions + * +@verbatim + ============================================================================== + ##### Timer Hall Sensor functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure TIM HAL Sensor. + (+) De-initialize TIM HAL Sensor. + (+) Start the Hall Sensor Interface. + (+) Stop the Hall Sensor Interface. + (+) Start the Hall Sensor Interface and enable interrupts. + (+) Stop the Hall Sensor Interface and disable interrupts. + (+) Start the Hall Sensor Interface and enable DMA transfers. + (+) Stop the Hall Sensor Interface and disable DMA transfers. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Hall Sensor Interface and create the associated handle. + * @param htim : TIM Encoder Interface handle + * @param sConfig : TIM Hall Sensor configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig) +{ + TIM_OC_InitTypeDef OC_Config; + + /* Check the TIM handle allocation */ + if(htim == NULL) + { + return HAL_ERROR; + } + + assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + + /* Set the TIM state */ + htim->State= HAL_TIM_STATE_BUSY; + + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIMEx_HallSensor_MspInit(htim); + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */ + TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->IC1Prescaler; + + /* Enable the Hall sensor interface (XOR function of the three inputs) */ + htim->Instance->CR2 |= TIM_CR2_TI1S; + + /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1F_ED; + + /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; + + /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/ + OC_Config.OCFastMode = TIM_OCFAST_DISABLE; + OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET; + OC_Config.OCMode = TIM_OCMODE_PWM2; + OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET; + OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH; + OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH; + OC_Config.Pulse = sConfig->Commutation_Delay; + + TIM_OC2_SetConfig(htim->Instance, &OC_Config); + + /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 + register to 101 */ + htim->Instance->CR2 &= ~TIM_CR2_MMS; + htim->Instance->CR2 |= TIM_TRGO_OC2REF; + + /* Initialize the TIM state*/ + htim->State= HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Hall Sensor interface + * @param htim : TIM Hall Sensor handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIMEx_HallSensor_MspDeInit(htim); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Hall Sensor MSP. + * @param htim : TIM handle + * @retval None + */ +__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Hall Sensor MSP. + * @param htim : TIM handle + * @retval None + */ +__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Hall Sensor Interface. + * @param htim : TIM Hall Sensor handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + + /* Enable the Input Capture channels 1 + (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall sensor Interface. + * @param htim : TIM Hall Sensor handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1, 2 and 3 + (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Hall Sensor Interface in interrupt mode. + * @param htim : TIM Hall Sensor handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + + /* Enable the capture compare Interrupts 1 event */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the Input Capture channels 1 + (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall Sensor Interface in interrupt mode. + * @param htim : TIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 + (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts event */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Hall Sensor Interface in DMA mode. + * @param htim : TIM Hall Sensor handle + * @param pData : The destination Buffer address. + * @param Length : The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) +{ + /* Check the parameters */ + assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + + if((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if((htim->State == HAL_TIM_STATE_READY)) + { + if(((uint32_t)pData == 0 ) && (Length > 0)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + /* Enable the Input Capture channels 1 + (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Set the DMA Input Capture 1 Callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt; + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; + + /* Enable the DMA channel for Capture 1*/ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); + + /* Enable the capture compare 1 Interrupt */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall Sensor Interface in DMA mode. + * @param htim : TIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 + (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + + /* Disable the capture compare Interrupts 1 event */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group2 Timer Complementary Output Compare functions + * @brief Timer Complementary Output Compare functions + * +@verbatim + ============================================================================== + ##### Timer Complementary Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary Output Compare/PWM. + (+) Stop the Complementary Output Compare/PWM. + (+) Start the Complementary Output Compare/PWM and enable interrupts. + (+) Stop the Complementary Output Compare/PWM and disable interrupts. + (+) Start the Complementary Output Compare/PWM and enable DMA transfers. + (+) Stop the Complementary Output Compare/PWM and disable DMA transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the TIM Output Compare signal generation on the complementary + * output. + * @param htim : TIM Output Compare handle + * @param Channel : TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Ouput */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation on the complementary + * output. + * @param htim : TIM handle + * @param Channel : TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode + * on the complementary output. + * @param htim : TIM OC handle + * @param Channel : TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + } + break; + + default: + break; + } + + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Ouput */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode + * on the complementary output. + * @param htim : TIM Output Compare handle + * @param Channel : TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + } + break; + + default: + break; + } + + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode + * on the complementary output. + * @param htim : TIM Output Compare handle + * @param Channel : TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData : The source Buffer address. + * @param Length : The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + if((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if((htim->State == HAL_TIM_STATE_READY)) + { + if(((uint32_t)pData == 0 ) && (Length > 0)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); + + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); + + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + } + break; + + case TIM_CHANNEL_3: +{ + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); + + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); + + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + } + break; + + default: + break; + } + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Ouput */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode + * on the complementary output. + * @param htim : TIM Output Compare handle + * @param Channel : TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + } + break; + + default: + break; + } + + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group3 Timer Complementary PWM functions + * @brief Timer Complementary PWM functions + * +@verbatim + ============================================================================== + ##### Timer Complementary PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary PWM. + (+) Stop the Complementary PWM. + (+) Start the Complementary PWM and enable interrupts. + (+) Stop the Complementary PWM and disable interrupts. + (+) Start the Complementary PWM and enable DMA transfers. + (+) Stop the Complementary PWM and disable DMA transfers. + (+) Start the Complementary Input Capture measurement. + (+) Stop the Complementary Input Capture. + (+) Start the Complementary Input Capture and enable interrupts. + (+) Stop the Complementary Input Capture and disable interrupts. + (+) Start the Complementary Input Capture and enable DMA transfers. + (+) Stop the Complementary Input Capture and disable DMA transfers. + (+) Start the Complementary One Pulse generation. + (+) Stop the Complementary One Pulse. + (+) Start the Complementary One Pulse and enable interrupts. + (+) Stop the Complementary One Pulse and disable interrupts. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the PWM signal generation on the complementary output. + * @param htim : TIM handle + * @param Channel : TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Ouput */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation on the complementary output. + * @param htim : TIM handle + * @param Channel : TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode on the + * complementary output. + * @param htim : TIM handle + * @param Channel : TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + } + break; + + default: + break; + } + + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Ouput */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode on the + * complementary output. + * @param htim : TIM handle + * @param Channel : TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + } + break; + + default: + break; + } + + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode on the + * complementary output + * @param htim : TIM handle + * @param Channel : TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData : The source Buffer address. + * @param Length : The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + if((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if((htim->State == HAL_TIM_STATE_READY)) + { + if(((uint32_t)pData == 0 ) && (Length > 0)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); + + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); + + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); + + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + } + break; + + default: + break; + } + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Ouput */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode on the complementary + * output + * @param htim : TIM handle + * @param Channel : TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + } + break; + + default: + break; + } + + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group4 Timer Complementary One Pulse functions + * @brief Timer Complementary One Pulse functions + * +@verbatim + ============================================================================== + ##### Timer Complementary One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary One Pulse generation. + (+) Stop the Complementary One Pulse. + (+) Start the Complementary One Pulse and enable interrupts. + (+) Stop the Complementary One Pulse and disable interrupts. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the TIM One Pulse signal generation on the complemetary + * output. + * @param htim : TIM One Pulse handle + * @param OutputChannel : TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) + { + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Enable the complementary One Pulse output */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + + /* Enable the Main Ouput */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation on the complementary + * output. + * @param htim : TIM One Pulse handle + * @param OutputChannel : TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Disable the complementary One Pulse output */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode on the + * complementary channel. + * @param htim : TIM One Pulse handle + * @param OutputChannel : TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + /* Enable the complementary One Pulse output */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + + /* Enable the Main Ouput */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Return function status */ + return HAL_OK; + } + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode on the + * complementary channel. + * @param htim : TIM One Pulse handle + * @param OutputChannel : TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the complementary One Pulse output */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + + /* Disable the Main Ouput */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + + + +/** + * @} + */ +/** @defgroup TIMEx_Exported_Functions_Group5 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure the commutation event in case of use of the Hall sensor interface. + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master synchronization. + (+) Configure timer remapping capabilities. + +@endverbatim + * @{ + */ +/** + * @brief Configure the TIM commutation event sequence. + * @note: this function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @param htim : TIM handle + * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource : the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure the TIM commutation event sequence with interrupt. + * @note: this function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @param htim : TIM handle + * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource : the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Enable the Commutation Interrupt Request */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure the TIM commutation event sequence with DMA. + * @note: this function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set + * @param htim : TIM handle + * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource : the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Enable the Commutation DMA Request */ + /* Set the DMA Commutation Callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt; + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError; + + /* Enable the Commutation DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM in master mode. + * @param htim : TIM handle. + * @param sMasterConfig : pointer to a TIM_MasterConfigTypeDef structure that + * contains the selected trigger output (TRGO) and the Master/Slave + * mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); + assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Reset the MMS Bits */ + htim->Instance->CR2 &= ~TIM_CR2_MMS; + /* Select the TRGO source */ + htim->Instance->CR2 |= sMasterConfig->MasterOutputTrigger; + + /* Reset the MSM Bit */ + htim->Instance->SMCR &= ~TIM_SMCR_MSM; + /* Set or Reset the MSM Bit */ + htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode; + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State + * and the AOE(automatic output enable). + * @param htim : TIM handle + * @param sBreakDeadTimeConfig : pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that + * contains the BDTR Register configuration information for the TIM peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); + assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode)); + assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel)); + assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); + assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); + assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); + assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + htim->Instance->BDTR = (uint32_t)sBreakDeadTimeConfig->OffStateRunMode | + sBreakDeadTimeConfig->OffStateIDLEMode | + sBreakDeadTimeConfig->LockLevel | + sBreakDeadTimeConfig->DeadTime | + sBreakDeadTimeConfig->BreakState | + sBreakDeadTimeConfig->BreakPolarity | + sBreakDeadTimeConfig->AutomaticOutput; + + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM14 Remapping input capabilities. + * @param htim : TIM handle. + * @param Remap : specifies the TIM remapping source. + * This parameter can be one of the following values: + * @arg TIM_TIM14_GPIO: TIM14 TI1 is connected to GPIO + * @arg TIM_TIM14_RTC: TIM14 TI1 is connected to RTC_clock + * @arg TIM_TIM14_HSE: TIM14 TI1 is connected to HSE/32 + * @arg TIM_TIM14_MCO: TIM14 TI1 is connected to MCO + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) +{ + __HAL_LOCK(htim); + + /* Check parameters */ + assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance)); + assert_param(IS_TIM_REMAP(Remap)); + + /* Set the Timer remapping configuration */ + htim->Instance->OR = Remap; + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group6 Extension Callbacks functions + * @brief Extension Callbacks functions + * +@verbatim + ============================================================================== + ##### Extension Callbacks functions ##### + ============================================================================== + [..] + This section provides Extension TIM callback functions: + (+) Timer Commutation callback + (+) Timer Break callback + +@endverbatim + * @{ + */ + +/** + * @brief Hall commutation changed callback in non blocking mode + * @param htim : TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIMEx_CommutationCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Break detection callback in non blocking mode + * @param htim : TIM handle + * @retval None + */ +__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIMEx_BreakCallback could be implemented in the user file + */ +} + +/** + * @brief TIM DMA Commutation callback. + * @param hdma : pointer to DMA handle. + * @retval None + */ +void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + htim->State= HAL_TIM_STATE_READY; + + HAL_TIMEx_CommutationCallback(htim); +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group7 Extension Peripheral State functions + * @brief Extension Peripheral State functions + * +@verbatim + ============================================================================== + ##### Extension Peripheral State functions ##### + ============================================================================== + [..] + This subsection permit to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Hall Sensor interface state + * @param htim : TIM Hall Sensor handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup TIMEx_Private_Functions + * @{ + */ + +/** + * @brief Enables or disables the TIM Capture Compare Channel xN. + * @param TIMx to select the TIM peripheral + * @param Channel : specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_Channel_1: TIM Channel 1 + * @arg TIM_Channel_2: TIM Channel 2 + * @arg TIM_Channel_3: TIM Channel 3 + * @param ChannelNState : specifies the TIM Channel CCxNE bit new state. + * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. + * @retval None + */ +static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState) +{ + uint32_t tmp = 0; + + tmp = TIM_CCER_CC1NE << Channel; + + /* Reset the CCxNE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxNE Bit */ + TIMx->CCER |= (uint32_t)(ChannelNState << Channel); +} + +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tsc.c b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tsc.c new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tsc.c @@ -0,0 +1,791 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_tsc.c + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the Touch Sensing Controller (TSC) peripheral: + * + Initialization and DeInitialization + * + Channel IOs, Shield IOs and Sampling IOs configuration + * + Start and Stop an acquisition + * + Read acquisition result + * + Interrupts and flags management + * + @verbatim +================================================================================ + ##### TSC specific features ##### +================================================================================ + [..] + (#) Proven and robust surface charge transfer acquisition principle + + (#) Supports up to 3 capacitive sensing channels per group + + (#) Capacitive sensing channels can be acquired in parallel offering a very good + response time + + (#) Spread spectrum feature to improve system robustness in noisy environments + + (#) Full hardware management of the charge transfer acquisition sequence + + (#) Programmable charge transfer frequency + + (#) Programmable sampling capacitor I/O pin + + (#) Programmable channel I/O pin + + (#) Programmable max count value to avoid long acquisition when a channel is faulty + + (#) Dedicated end of acquisition and max count error flags with interrupt capability + + (#) One sampling capacitor for up to 3 capacitive sensing channels to reduce the system + components + + (#) Compatible with proximity, touchkey, linear and rotary touch sensor implementation + + + ##### How to use this driver ##### +================================================================================ + [..] + (#) Enable the TSC interface clock using __TSC_CLK_ENABLE() macro. + + (#) GPIO pins configuration + (++) Enable the clock for the TSC GPIOs using __GPIOx_CLK_ENABLE() macro. + (++) Configure the TSC pins used as sampling IOs in alternate function output Open-Drain mode, + and TSC pins used as channel/shield IOs in alternate function output Push-Pull mode + using HAL_GPIO_Init() function. + (++) Configure the alternate function on all the TSC pins using HAL_xxxx() function. + + (#) Interrupts configuration + (++) Configure the NVIC (if the interrupt model is used) using HAL_xxx() function. + + (#) TSC configuration + (++) Configure all TSC parameters and used TSC IOs using HAL_TSC_Init() function. + + *** Acquisition sequence *** + =================================== + [..] + (+) Discharge all IOs using HAL_TSC_IODischarge() function. + (+) Wait a certain time allowing a good discharge of all capacitors. This delay depends + of the sampling capacitor and electrodes design. + (+) Select the channel IOs to be acquired using HAL_TSC_IOConfig() function. + (+) Launch the acquisition using either HAL_TSC_Start() or HAL_TSC_Start_IT() function. + If the synchronized mode is selected, the acquisition will start as soon as the signal + is received on the synchro pin. + (+) Wait the end of acquisition using either HAL_TSC_PollForAcquisition() or + HAL_TSC_GetState() function or using WFI instruction for example. + (+) Check the group acquisition status using HAL_TSC_GroupGetStatus() function. + (+) Read the acquisition value using HAL_TSC_GroupGetValue() function. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup TSC TSC HAL module driver + * @brief TSC HAL module driver + * @{ + */ + +#ifdef HAL_TSC_MODULE_ENABLED + +#if defined(STM32F051x8) || defined(STM32F071xB) || defined(STM32F091xC) || \ + defined(STM32F042x6) || defined(STM32F072xB) || \ + defined(STM32F048xx) || defined(STM32F058xx) || defined(STM32F078xx) || defined(STM32F098xx) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static uint32_t TSC_extract_groups(uint32_t iomask); +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup TSC_Exported_Functions TSC Exported Functions + * @{ + */ + +/** @defgroup TSC_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the TSC. + (+) De-initialize the TSC. +@endverbatim + * @{ + */ + +/** + * @brief Initializes the TSC peripheral according to the specified parameters + * in the TSC_InitTypeDef structure. + * @param htsc: TSC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc) +{ + /* Check TSC handle allocation */ + if (htsc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); + assert_param(IS_TSC_CTPH(htsc->Init.CTPulseHighLength)); + assert_param(IS_TSC_CTPL(htsc->Init.CTPulseLowLength)); + assert_param(IS_TSC_SS(htsc->Init.SpreadSpectrum)); + assert_param(IS_TSC_SSD(htsc->Init.SpreadSpectrumDeviation)); + assert_param(IS_TSC_SS_PRESC(htsc->Init.SpreadSpectrumPrescaler)); + assert_param(IS_TSC_PG_PRESC(htsc->Init.PulseGeneratorPrescaler)); + assert_param(IS_TSC_MCV(htsc->Init.MaxCountValue)); + assert_param(IS_TSC_IODEF(htsc->Init.IODefaultMode)); + assert_param(IS_TSC_SYNC_POL(htsc->Init.SynchroPinPolarity)); + assert_param(IS_TSC_ACQ_MODE(htsc->Init.AcquisitionMode)); + assert_param(IS_TSC_MCE_IT(htsc->Init.MaxCountInterrupt)); + + /* Initialize the TSC state */ + htsc->State = HAL_TSC_STATE_BUSY; + + /* Init the low level hardware : GPIO, CLOCK, CORTEX */ + HAL_TSC_MspInit(htsc); + + /*--------------------------------------------------------------------------*/ + /* Set TSC parameters */ + + /* Enable TSC */ + htsc->Instance->CR = TSC_CR_TSCE; + + /* Set all functions */ + htsc->Instance->CR |= (htsc->Init.CTPulseHighLength | + htsc->Init.CTPulseLowLength | + (uint32_t)(htsc->Init.SpreadSpectrumDeviation << 17) | + htsc->Init.SpreadSpectrumPrescaler | + htsc->Init.PulseGeneratorPrescaler | + htsc->Init.MaxCountValue | + htsc->Init.IODefaultMode | + htsc->Init.SynchroPinPolarity | + htsc->Init.AcquisitionMode); + + /* Spread spectrum */ + if (htsc->Init.SpreadSpectrum == ENABLE) + { + htsc->Instance->CR |= TSC_CR_SSE; + } + + /* Disable Schmitt trigger hysteresis on all used TSC IOs */ + htsc->Instance->IOHCR = (uint32_t)(~(htsc->Init.ChannelIOs | htsc->Init.ShieldIOs | htsc->Init.SamplingIOs)); + + /* Set channel and shield IOs */ + htsc->Instance->IOCCR = (htsc->Init.ChannelIOs | htsc->Init.ShieldIOs); + + /* Set sampling IOs */ + htsc->Instance->IOSCR = htsc->Init.SamplingIOs; + + /* Set the groups to be acquired */ + htsc->Instance->IOGCSR = TSC_extract_groups(htsc->Init.ChannelIOs); + + /* Clear interrupts */ + htsc->Instance->IER &= (uint32_t)(~(TSC_IT_EOA | TSC_IT_MCE)); + + /* Clear flags */ + htsc->Instance->ICR = (TSC_FLAG_EOA | TSC_FLAG_MCE); + + /*--------------------------------------------------------------------------*/ + + /* Initialize the TSC state */ + htsc->State = HAL_TSC_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Deinitializes the TSC peripheral registers to their default reset values. + * @param htsc: TSC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef* htsc) +{ + /* Check TSC handle allocation */ + if (htsc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); + + /* Change TSC state */ + htsc->State = HAL_TSC_STATE_BUSY; + + /* DeInit the low level hardware */ + HAL_TSC_MspDeInit(htsc); + + /* Change TSC state */ + htsc->State = HAL_TSC_STATE_RESET; + + /* Process unlocked */ + __HAL_UNLOCK(htsc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the TSC MSP. + * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * the configuration information for the specified TSC. + * @retval None + */ +__weak void HAL_TSC_MspInit(TSC_HandleTypeDef* htsc) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TSC_MspInit could be implemented in the user file. + */ +} + +/** + * @brief DeInitializes the TSC MSP. + * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * the configuration information for the specified TSC. + * @retval None + */ +__weak void HAL_TSC_MspDeInit(TSC_HandleTypeDef* htsc) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TSC_MspDeInit could be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup TSC_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Start acquisition in polling mode. + (+) Start acquisition in interrupt mode. + (+) Stop conversion in polling mode. + (+) Stop conversion in interrupt mode. + (+) Get group acquisition status. + (+) Get group acquisition value. +@endverbatim + * @{ + */ + +/** + * @brief Starts the acquisition. + * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * the configuration information for the specified TSC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef* htsc) +{ + /* Check the parameters */ + assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); + + /* Process locked */ + __HAL_LOCK(htsc); + + /* Change TSC state */ + htsc->State = HAL_TSC_STATE_BUSY; + + /* Clear interrupts */ + __HAL_TSC_DISABLE_IT(htsc, (TSC_IT_EOA | TSC_IT_MCE)); + + /* Clear flags */ + __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE)); + + /* Stop discharging the IOs */ + __HAL_TSC_SET_IODEF_INFLOAT(htsc); + + /* Launch the acquisition */ + __HAL_TSC_START_ACQ(htsc); + + /* Process unlocked */ + __HAL_UNLOCK(htsc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Enables the interrupt and starts the acquisition + * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * the configuration information for the specified TSC. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc) +{ + /* Check the parameters */ + assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); + assert_param(IS_TSC_MCE_IT(htsc->Init.MaxCountInterrupt)); + + /* Process locked */ + __HAL_LOCK(htsc); + + /* Change TSC state */ + htsc->State = HAL_TSC_STATE_BUSY; + + /* Enable end of acquisition interrupt */ + __HAL_TSC_ENABLE_IT(htsc, TSC_IT_EOA); + + /* Enable max count error interrupt (optional) */ + if (htsc->Init.MaxCountInterrupt == ENABLE) + { + __HAL_TSC_ENABLE_IT(htsc, TSC_IT_MCE); + } + else + { + __HAL_TSC_DISABLE_IT(htsc, TSC_IT_MCE); + } + + /* Clear flags */ + __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE)); + + /* Stop discharging the IOs */ + __HAL_TSC_SET_IODEF_INFLOAT(htsc); + + /* Launch the acquisition */ + __HAL_TSC_START_ACQ(htsc); + + /* Process unlocked */ + __HAL_UNLOCK(htsc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the acquisition previously launched in polling mode + * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * the configuration information for the specified TSC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef* htsc) +{ + /* Check the parameters */ + assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); + + /* Process locked */ + __HAL_LOCK(htsc); + + /* Stop the acquisition */ + __HAL_TSC_STOP_ACQ(htsc); + + /* Clear flags */ + __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE)); + + /* Change TSC state */ + htsc->State = HAL_TSC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(htsc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the acquisition previously launched in interrupt mode + * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * the configuration information for the specified TSC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef* htsc) +{ + /* Check the parameters */ + assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); + + /* Process locked */ + __HAL_LOCK(htsc); + + /* Stop the acquisition */ + __HAL_TSC_STOP_ACQ(htsc); + + /* Disable interrupts */ + __HAL_TSC_DISABLE_IT(htsc, (TSC_IT_EOA | TSC_IT_MCE)); + + /* Clear flags */ + __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE)); + + /* Change TSC state */ + htsc->State = HAL_TSC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(htsc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Gets the acquisition status for a group + * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * the configuration information for the specified TSC. + * @param gx_index: Index of the group + * @retval Group status + */ +TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef* htsc, uint32_t gx_index) +{ + /* Check the parameters */ + assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); + assert_param(IS_GROUP_INDEX(gx_index)); + + /* Return the group status */ + return(__HAL_TSC_GET_GROUP_STATUS(htsc, gx_index)); +} + +/** + * @brief Gets the acquisition measure for a group + * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * the configuration information for the specified TSC. + * @param gx_index: Index of the group + * @retval Acquisition measure + */ +uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index) +{ + /* Check the parameters */ + assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); + assert_param(IS_GROUP_INDEX(gx_index)); + + /* Return the group acquisition counter */ + return htsc->Instance->IOGXCR[gx_index]; +} + +/** + * @} + */ + +/** @defgroup TSC_Exported_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure TSC IOs + (+) Discharge TSC IOs +@endverbatim + * @{ + */ + +/** + * @brief Configures TSC IOs + * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * the configuration information for the specified TSC. + * @param config: pointer to the configuration structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfigTypeDef* config) +{ + /* Check the parameters */ + assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); + + /* Process locked */ + __HAL_LOCK(htsc); + + /* Stop acquisition */ + __HAL_TSC_STOP_ACQ(htsc); + + /* Disable Schmitt trigger hysteresis on all used TSC IOs */ + htsc->Instance->IOHCR = (uint32_t)(~(config->ChannelIOs | config->ShieldIOs | config->SamplingIOs)); + + /* Set channel and shield IOs */ + htsc->Instance->IOCCR = (config->ChannelIOs | config->ShieldIOs); + + /* Set sampling IOs */ + htsc->Instance->IOSCR = config->SamplingIOs; + + /* Set groups to be acquired */ + htsc->Instance->IOGCSR = TSC_extract_groups(config->ChannelIOs); + + /* Process unlocked */ + __HAL_UNLOCK(htsc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Discharge TSC IOs + * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * the configuration information for the specified TSC. + * @param choice: enable or disable + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice) +{ + /* Check the parameters */ + assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); + + /* Process locked */ + __HAL_LOCK(htsc); + + if (choice == ENABLE) + { + __HAL_TSC_SET_IODEF_OUTPPLOW(htsc); + } + else + { + __HAL_TSC_SET_IODEF_INFLOAT(htsc); + } + + /* Process unlocked */ + __HAL_UNLOCK(htsc); + + /* Return the group acquisition counter */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TSC_Exported_Functions_Group4 State functions + * @brief State functions + * +@verbatim + =============================================================================== + ##### State functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Get TSC state. + (+) Poll for acquisition completed. + (+) Handles TSC interrupt request. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TSC state + * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * the configuration information for the specified TSC. + * @retval HAL state + */ +HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef* htsc) +{ + /* Check the parameters */ + assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); + + if (htsc->State == HAL_TSC_STATE_BUSY) + { + /* Check end of acquisition flag */ + if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_EOA) != RESET) + { + /* Check max count error flag */ + if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_MCE) != RESET) + { + /* Change TSC state */ + htsc->State = HAL_TSC_STATE_ERROR; + } + else + { + /* Change TSC state */ + htsc->State = HAL_TSC_STATE_READY; + } + } + } + + /* Return TSC state */ + return htsc->State; +} + +/** + * @brief Start acquisition and wait until completion + * @note There is no need of a timeout parameter as the max count error is already + * managed by the TSC peripheral. + * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * the configuration information for the specified TSC. + * @retval HAL state + */ +HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef* htsc) +{ + /* Check the parameters */ + assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); + + /* Process locked */ + __HAL_LOCK(htsc); + + /* Check end of acquisition */ + while (HAL_TSC_GetState(htsc) == HAL_TSC_STATE_BUSY) + { + /* The timeout (max count error) is managed by the TSC peripheral itself. */ + } + + /* Process unlocked */ + __HAL_UNLOCK(htsc); + + return HAL_OK; +} + +/** + * @brief Handles TSC interrupt request + * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * the configuration information for the specified TSC. + * @retval None + */ +void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc) +{ + /* Check the parameters */ + assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); + + /* Check if the end of acquisition occured */ + if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_EOA) != RESET) + { + /* Clear EOA flag */ + __HAL_TSC_CLEAR_FLAG(htsc, TSC_FLAG_EOA); + } + + /* Check if max count error occured */ + if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_MCE) != RESET) + { + /* Clear MCE flag */ + __HAL_TSC_CLEAR_FLAG(htsc, TSC_FLAG_MCE); + /* Change TSC state */ + htsc->State = HAL_TSC_STATE_ERROR; + /* Conversion completed callback */ + HAL_TSC_ErrorCallback(htsc); + } + else + { + /* Change TSC state */ + htsc->State = HAL_TSC_STATE_READY; + /* Conversion completed callback */ + HAL_TSC_ConvCpltCallback(htsc); + } +} + +/** + * @} + */ + +/** @defgroup TSC_Exported_Functions_Group5 Callback functions + * @brief Callback functions + * @{ + */ + +/** + * @brief Acquisition completed callback in non blocking mode + * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * the configuration information for the specified TSC. + * @retval None + */ +__weak void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef* htsc) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TSC_ConvCpltCallback could be implemented in the user file. + */ +} + +/** + * @brief Error callback in non blocking mode + * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * the configuration information for the specified TSC. + * @retval None + */ +__weak void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TSC_ErrorCallback could be implemented in the user file. + */ +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup TSC_Private_Functions TSC Private Functions + * @{ + */ + +/** + * @brief Utility function used to set the acquired groups mask + * @param iomask: Channels IOs mask + * @retval Acquired groups mask + */ +static uint32_t TSC_extract_groups(uint32_t iomask) +{ + uint32_t groups = 0; + uint32_t idx; + + for (idx = 0; idx < TSC_NB_OF_GROUPS; idx++) + { + if ((iomask & ((uint32_t)0x0F << (idx * 4))) != RESET) + { + groups |= ((uint32_t)1 << idx); + } + } + + return groups; +} + +/** + * @} + */ + +#endif /* defined(STM32F051x8) || defined(STM32F071xB) || defined(STM32F091xC) || */ + /* defined(STM32F042x6) || defined(STM32F072xB) || */ + /* defined(STM32F048xx) || defined(STM32F058xx) || defined(STM32F078xx) || defined(STM32F098xx) */ + +#endif /* HAL_TSC_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c @@ -0,0 +1,1811 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_uart.c + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief UART HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Errors functions + @verbatim + =============================================================================== + ##### How to use this driver ##### +================================================================================ + [..] + The UART HAL driver can be used as follows: + + (#) Declare a UART_HandleTypeDef handle structure. + + (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit ()API: + (##) Enable the USARTx interface clock. + (##) UART pins configuration: + (+++) Enable the clock for the UART GPIOs. + (+++) Configure these UART pins as alternate function pull-up. + (##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT() + and HAL_UART_Receive_IT() APIs): + (+++) Configure the USARTx interrupt priority. + (+++) Enable the NVIC USART IRQ handle. + (##) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA() + and HAL_UART_Receive_DMA() APIs): + (+++) Declare a DMA handle structure for the Tx/Rx channel. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx channel. + (+++) Associate the initilalized DMA handle to the UART DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. + + (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware + flow control and Mode(Receiver/Transmitter) in the huart Init structure. + + (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...) + in the huart AdvancedInit structure. + + (#) For the UART asynchronous mode, initialize the UART registers by calling + the HAL_UART_Init() API. + + (#) For the UART Half duplex mode, initialize the UART registers by calling + the HAL_HalfDuplex_Init() API. + + (#) For the UART Multiprocessor mode, initialize the UART registers + by calling the HAL_MultiProcessor_Init() API. + + (#) For the UART RS485 Driver Enabled mode, initialize the UART registers + by calling the HAL_RS485Ex_Init() API. + + [..] + (@) The specific UART interrupts (Transmission complete interrupt, + RXNE interrupt and Error Interrupts) will be managed using the macros + __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit and receive process. + + [..] + (@) These APIs(HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_MultiProcessor_Init(), + also configure also the low level Hardware GPIO, CLOCK, CORTEX...etc) by + calling the customed HAL_UART_MspInit() API. + + Three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Send an amount of data in blocking mode using HAL_UART_Transmit() + (+) Receive an amount of data in blocking mode using HAL_UART_Receive() + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT() + (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback + (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_TxCpltCallback + (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT() + (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback + (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_RxCpltCallback + (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_UART_ErrorCallback + + *** DMA mode IO operation *** + ============================== + [..] + (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA() + (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback + (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_TxCpltCallback + (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA() + (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback + (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_RxCpltCallback + (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_UART_ErrorCallback + (+) Pause the DMA Transfer using HAL_UART_DMAPause() + (+) Resume the DMA Transfer using HAL_UART_DMAResume() + (+) Stop the DMA Transfer using HAL_UART_DMAStop() + + *** UART HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in UART HAL driver. + + (+) __HAL_UART_ENABLE: Enable the UART peripheral + (+) __HAL_UART_DISABLE: Disable the UART peripheral + (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not + (+) __HAL_UART_CLEAR_FLAG : Clear the specified UART pending flag + (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt + (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt + + [..] + (@) You can refer to the UART HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup UART UART HAL module driver + * @brief HAL UART module driver + * @{ + */ +#ifdef HAL_UART_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup UART_Private_Constants UART Private Constants + * @{ + */ +#define HAL_UART_TXDMA_TIMEOUTVALUE 22000 +#define UART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ + USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup UART_Private_Functions UART Private Functions + * @{ + */ +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); +static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); +static void UART_DMAError(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup UART_Exported_Functions UART Exported Functions + * @{ + */ + +/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USARTx or the UARTy + in asynchronous mode. + (+) For the asynchronous mode only these parameters can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + Depending on the frame length defined by the M bit (8-bits or 9-bits), + the possible UART frame formats are as listed in the following table: + |-----------|-----------|---------------------------------------| + | M1M0 bits | PCE bit | UART frame | + |-----------------------|---------------------------------------| + | 00 | 0 | | SB | 8-bit data | STB | | + |-----------|-----------|---------------------------------------| + | 00 | 1 | | SB | 7-bit data | PB | STB | | + |-----------|-----------|---------------------------------------| + | 01 | 0 | | SB | 9-bit data | STB | | + |-----------|-----------|---------------------------------------| + | 01 | 1 | | SB | 8-bit data | PB | STB | | + +---------------------------------------------------------------+ + | 10 | 0 | | SB | 7-bit data | STB | | + |-----------|-----------|---------------------------------------| + | 10 | 1 | | SB | 6-bit data | PB | STB | | + +---------------------------------------------------------------+ + (++) Hardware flow control + (++) Receiver/transmitter modes + (++) Over Sampling Method + (++) One-Bit Sampling Method + (+) For the asynchronous mode, the following advanced features can be configured as well: + (++) TX and/or RX pin level inversion + (++) data logical level inversion + (++) RX and TX pins swap + (++) RX overrun detection disabling + (++) DMA disabling on RX error + (++) MSB first on communication line + (++) auto Baud rate detection + [..] + The HAL_UART_Init(), HAL_HalfDuplex_Init() and HAL_MultiProcessor_Init() + API follow respectively the UART asynchronous, UART Half duplex and multiprocessor + configuration procedures (details for the procedures are available in reference manual). + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the UART mode according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle . + * @param huart: uart handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if(huart == NULL) + { + return HAL_ERROR; + } + + if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) + { + /* Check the parameters */ + assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance)); + } + else + { + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + } + + if(huart->State == HAL_UART_STATE_RESET) + { + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); + } + + huart->State = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* In asynchronous mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ + huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN); + huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN); + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->State to Ready */ + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Initializes the half-duplex mode according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle . + * @param huart: uart handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if(huart == NULL) + { + return HAL_ERROR; + } + + /* Check UART instance */ + assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance)); + + if(huart->State == HAL_UART_STATE_RESET) + { + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); + } + + huart->State = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* In half-duplex mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register.*/ + huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN); + huart->Instance->CR3 &= ~(USART_CR3_IREN | USART_CR3_SCEN); + + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ + huart->Instance->CR3 |= USART_CR3_HDSEL; + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->State to Ready */ + return (UART_CheckIdleState(huart)); +} + + +/** + * @brief Initializes the multiprocessor mode according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle. + * @param huart: UART handle + * @param Address: UART node address (4-, 6-, 7- or 8-bit long) + * @param WakeUpMethod: specifies the UART wakeup method. + * This parameter can be one of the following values: + * @arg UART_WAKEUPMETHOD_IDLELINE: WakeUp by an idle line detection + * @arg UART_WAKEUPMETHOD_ADDRESSMARK: WakeUp by an address mark + * @note If the user resorts to idle line detection wake up, the Address parameter + * is useless and ignored by the initialization function. + * @note If the user resorts to address mark wake up, the address length detection + * is configured by default to 4 bits only. For the UART to be able to + * manage 6-, 7- or 8-bit long addresses detection, the API + * HAL_MultiProcessorEx_AddressLength_Set() must be called after + * HAL_MultiProcessor_Init(). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod) +{ + /* Check the UART handle allocation */ + if(huart == NULL) + { + return HAL_ERROR; + } + + /* Check the wake up method parameter */ + assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod)); + + if(huart->State == HAL_UART_STATE_RESET) + { + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); + } + + huart->State = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* In multiprocessor mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register. */ + huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN); + huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN); + + if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK) + { + /* If address mark wake up method is chosen, set the USART address node */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS)); + } + + /* Set the wake up method by setting the WAKE bit in the CR1 register */ + MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod); + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->State to Ready */ + return (UART_CheckIdleState(huart)); +} + +/** + * @brief DeInitializes the UART peripheral + * @param huart: uart handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if(huart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + + huart->State = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + huart->Instance->CR1 = 0x0; + huart->Instance->CR2 = 0x0; + huart->Instance->CR3 = 0x0; + + /* DeInit the low level hardware */ + HAL_UART_MspDeInit(huart); + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->State = HAL_UART_STATE_RESET; + + /* Process Unlock */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief UART MSP Init + * @param huart: uart handle + * @retval None + */ + __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_MspInit can be implemented in the user file + */ +} + +/** + * @brief UART MSP DeInit + * @param huart: uart handle + * @retval None + */ + __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group2 IO operation functions + * @brief UART Transmit and Receive functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to manage the UART asynchronous + and Half duplex data transfers. + + (#) There are two mode of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode: The communication is performed using Interrupts + or DMA, These APIs return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks + will be executed respectivelly at the end of the transmit or Receive process + The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected + + (#) Blocking mode APIs are : + (++) HAL_UART_Transmit() + (++) HAL_UART_Receive() + + (#) Non Blocking mode APIs with Interrupt are : + (++) HAL_UART_Transmit_IT() + (++) HAL_UART_Receive_IT() + (++) HAL_UART_IRQHandler() + (++) UART_Transmit_IT() + (++) UART_Receive_IT() + + (#) Non Blocking mode APIs with DMA are : + (++) HAL_UART_Transmit_DMA() + (++) HAL_UART_Receive_DMA() + (++) HAL_UART_DMAPause() + (++) HAL_UART_DMAResume() + (++) HAL_UART_DMAStop() + + (#) A set of Transfer Complete Callbacks are provided in non blocking mode: + (++) HAL_UART_TxHalfCpltCallback() + (++) HAL_UART_TxCpltCallback() + (++) HAL_UART_RxHalfCpltCallback() + (++) HAL_UART_RxCpltCallback() + (++) HAL_UART_ErrorCallback() + + [..] + (@) In the Half duplex communication, it is forbidden to run the transmit + and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. + +@endverbatim + * @{ + */ + +/** + * @brief Send an amount of data in blocking mode + * @param huart: uart handle + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @param Timeout : Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint16_t* tmp; + + if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX)) + { + if((pData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->ErrorCode = HAL_UART_ERROR_NONE; + /* Check if a non-blocking receive process is ongoing or not */ + if(huart->State == HAL_UART_STATE_BUSY_RX) + { + huart->State = HAL_UART_STATE_BUSY_TX_RX; + } + else + { + huart->State = HAL_UART_STATE_BUSY_TX; + } + + huart->TxXferSize = Size; + huart->TxXferCount = Size; + while(huart->TxXferCount > 0) + { + huart->TxXferCount--; + if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + tmp = (uint16_t*) pData; + huart->Instance->TDR = (*tmp & (uint16_t)0x01FF); + pData += 2; + } + else + { + huart->Instance->TDR = (*pData++ & (uint8_t)0xFF); + } + } + if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + /* Check if a non-blocking receive Process is ongoing or not */ + if(huart->State == HAL_UART_STATE_BUSY_TX_RX) + { + huart->State = HAL_UART_STATE_BUSY_RX; + } + else + { + huart->State = HAL_UART_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in blocking mode + * @param huart: uart handle + * @param pData: pointer to data buffer + * @param Size: amount of data to be received + * @param Timeout : Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint16_t* tmp; + uint16_t uhMask; + + if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX)) + { + if((pData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->ErrorCode = HAL_UART_ERROR_NONE; + /* Check if a non-blocking transmit process is ongoing or not */ + if(huart->State == HAL_UART_STATE_BUSY_TX) + { + huart->State = HAL_UART_STATE_BUSY_TX_RX; + } + else + { + huart->State = HAL_UART_STATE_BUSY_RX; + } + + huart->RxXferSize = Size; + huart->RxXferCount = Size; + + /* Computation of UART mask to apply to RDR register */ + __HAL_UART_MASK_COMPUTATION(huart); + uhMask = huart->Mask; + + /* as long as data have to be received */ + while(huart->RxXferCount > 0) + { + huart->RxXferCount--; + if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + tmp = (uint16_t*) pData ; + *tmp = (uint16_t)(huart->Instance->RDR & uhMask); + pData +=2; + } + else + { + *pData++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); + } + } + + /* Check if a non-blocking transmit Process is ongoing or not */ + if(huart->State == HAL_UART_STATE_BUSY_TX_RX) + { + huart->State = HAL_UART_STATE_BUSY_TX; + } + else + { + huart->State = HAL_UART_STATE_READY; + } + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Send an amount of data in interrupt mode + * @param huart: uart handle + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX)) + { + if((pData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->pTxBuffPtr = pData; + huart->TxXferSize = Size; + huart->TxXferCount = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + /* Check if a receive process is ongoing or not */ + if(huart->State == HAL_UART_STATE_BUSY_RX) + { + huart->State = HAL_UART_STATE_BUSY_TX_RX; + } + else + { + huart->State = HAL_UART_STATE_BUSY_TX; + } + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_UART_ENABLE_IT(huart, UART_IT_ERR); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + /* Enable the UART Transmit Data Register Empty Interrupt */ + __HAL_UART_ENABLE_IT(huart, UART_IT_TXE); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in interrupt mode + * @param huart: uart handle + * @param pData: pointer to data buffer + * @param Size: amount of data to be received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX)) + { + if((pData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + huart->RxXferCount = Size; + + /* Computation of UART mask to apply to RDR register */ + __HAL_UART_MASK_COMPUTATION(huart); + + huart->ErrorCode = HAL_UART_ERROR_NONE; + /* Check if a transmit process is ongoing or not */ + if(huart->State == HAL_UART_STATE_BUSY_TX) + { + huart->State = HAL_UART_STATE_BUSY_TX_RX; + } + else + { + huart->State = HAL_UART_STATE_BUSY_RX; + } + + /* Enable the UART Parity Error Interrupt */ + __HAL_UART_ENABLE_IT(huart, UART_IT_PE); + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_UART_ENABLE_IT(huart, UART_IT_ERR); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + /* Enable the UART Data Register not empty Interrupt */ + __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Send an amount of data in DMA mode + * @param huart: uart handle + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + uint32_t *tmp; + + if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX)) + { + if((pData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->pTxBuffPtr = pData; + huart->TxXferSize = Size; + huart->TxXferCount = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + /* Check if a receive process is ongoing or not */ + if(huart->State == HAL_UART_STATE_BUSY_RX) + { + huart->State = HAL_UART_STATE_BUSY_TX_RX; + } + else + { + huart->State = HAL_UART_STATE_BUSY_TX; + } + + /* Set the UART DMA transfer complete callback */ + huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; + + /* Set the DMA error callback */ + huart->hdmatx->XferErrorCallback = UART_DMAError; + + /* Enable the UART transmit DMA channel */ + tmp = (uint32_t*)&pData; + HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t*)tmp, (uint32_t)&huart->Instance->TDR, Size); + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the UART CR3 register */ + huart->Instance->CR3 |= USART_CR3_DMAT; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in DMA mode + * @param huart: uart handle + * @param pData: pointer to data buffer + * @param Size: amount of data to be received + * @note When the UART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + uint32_t *tmp; + + if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX)) + { + if((pData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + /* Check if a transmit process is ongoing or not */ + if(huart->State == HAL_UART_STATE_BUSY_TX) + { + huart->State = HAL_UART_STATE_BUSY_TX_RX; + } + else + { + huart->State = HAL_UART_STATE_BUSY_RX; + } + + /* Set the UART DMA transfer complete callback */ + huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; + + /* Set the DMA error callback */ + huart->hdmarx->XferErrorCallback = UART_DMAError; + + /* Enable the DMA channel */ + tmp = (uint32_t*)&pData; + HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, *(uint32_t*)tmp, Size); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the UART CR3 register */ + huart->Instance->CR3 |= USART_CR3_DMAR; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Pauses the DMA Transfer. + * @param huart: UART handle + * @retval None + */ +HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + if(huart->State == HAL_UART_STATE_BUSY_TX) + { + /* Disable the UART DMA Tx request */ + huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT); + } + else if(huart->State == HAL_UART_STATE_BUSY_RX) + { + /* Disable the UART DMA Rx request */ + huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR); + } + else if(huart->State == HAL_UART_STATE_BUSY_TX_RX) + { + /* Disable the UART DMA Tx request */ + huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT); + /* Disable the UART DMA Rx request */ + huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Resumes the DMA Transfer. + * @param huart: UART handle + * @retval None + */ +HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + if(huart->State == HAL_UART_STATE_BUSY_TX) + { + /* Enable the UART DMA Tx request */ + huart->Instance->CR3 |= USART_CR3_DMAT; + } + else if(huart->State == HAL_UART_STATE_BUSY_RX) + { + /* Enable the UART DMA Rx request */ + huart->Instance->CR3 |= USART_CR3_DMAR; + } + else if(huart->State == HAL_UART_STATE_BUSY_TX_RX) + { + /* Enable the UART DMA Rx request before the DMA Tx request */ + huart->Instance->CR3 |= USART_CR3_DMAR; + /* Enable the UART DMA Tx request */ + huart->Instance->CR3 |= USART_CR3_DMAT; + } + + /* If the UART peripheral is still not enabled, enable it */ + if ((huart->Instance->CR1 & USART_CR1_UE) == 0) + { + /* Enable UART peripheral */ + __HAL_UART_ENABLE(huart); + } + + /* TEACK and/or REACK to check before moving huart->State to Ready */ + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Stops the DMA Transfer. + * @param huart: UART handle + * @retval None + */ +HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + /* Disable the UART Tx/Rx DMA requests */ + huart->Instance->CR3 &= ~USART_CR3_DMAT; + huart->Instance->CR3 &= ~USART_CR3_DMAR; + + /* Abort the UART DMA tx channel */ + if(huart->hdmatx != NULL) + { + HAL_DMA_Abort(huart->hdmatx); + } + /* Abort the UART DMA rx channel */ + if(huart->hdmarx != NULL) + { + HAL_DMA_Abort(huart->hdmarx); + } + + /* Disable UART peripheral */ + __HAL_UART_DISABLE(huart); + + huart->State = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Tx Transfer completed callbacks + * @param huart: uart handle + * @retval None + */ + __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_TxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Tx Half Transfer completed callbacks. + * @param huart: UART handle + * @retval None + */ + __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_TxHalfCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks + * @param huart: uart handle + * @retval None + */ +__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_RxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Rx Half Transfer completed callbacks. + * @param huart: UART handle + * @retval None + */ +__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_RxHalfCpltCallback can be implemented in the user file + */ +} + +/** + * @brief UART error callbacks + * @param huart: uart handle + * @retval None + */ + __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_ErrorCallback can be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions + * @brief UART control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the UART. + (+) HAL_UART_GetState() API is helpful to check in run-time the state of the UART peripheral. + (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode + (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode + (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode + (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode + (+) HAL_UART_EnableStopMode() API enables the UART to wake up the MCU from stop mode + (+) HAL_UART_DisableStopMode() API disables the above functionality + (+) UART_SetConfig() API configures the UART peripheral + (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features + (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization + (+) UART_Wakeup_AddressConfig() API configures the wake-up from stop mode parameters + (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter + (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver +@endverbatim + * @{ + */ + +/** + * @brief Enable UART in mute mode (doesn't mean UART enters mute mode; + * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called) + * @param huart: UART handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + huart->State = HAL_UART_STATE_BUSY; + + /* Enable USART mute mode by setting the MME bit in the CR1 register */ + huart->Instance->CR1 |= USART_CR1_MME; + + huart->State = HAL_UART_STATE_READY; + + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Disable UART mute mode (doesn't mean it actually wakes up the software, + * as it may not have been in mute mode at this very moment). + * @param huart: uart handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + huart->State = HAL_UART_STATE_BUSY; + + /* Disable USART mute mode by clearing the MME bit in the CR1 register */ + huart->Instance->CR1 &= ~(USART_CR1_MME); + + huart->State = HAL_UART_STATE_READY; + + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Enter UART mute mode (means UART actually enters mute mode). + * To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called. + * @param huart: uart handle + * @retval HAL status + */ +void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) +{ + __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST); +} + +/** + * @brief Enables the UART transmitter and disables the UART receiver. + * @param huart: UART handle + * @retval HAL status + * @retval None + */ +HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + huart->State = HAL_UART_STATE_BUSY; + + /* Clear TE and RE bits */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); + /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ + SET_BIT(huart->Instance->CR1, USART_CR1_TE); + + huart->State = HAL_UART_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Enables the UART receiver and disables the UART transmitter. + * @param huart: UART handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + huart->State = HAL_UART_STATE_BUSY; + + /* Clear TE and RE bits */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); + /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ + SET_BIT(huart->Instance->CR1, USART_CR1_RE); + + huart->State = HAL_UART_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Errors functions + * @{ + */ + +/** + * @brief return the UART state + * @param huart: uart handle + * @retval HAL state + */ +HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) +{ + return huart->State; +} + +/** +* @brief Return the UART error code +* @param huart : pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART. +* @retval UART Error Code +*/ +uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) +{ + return huart->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup UART_Private_Functions UART Private Functions + * @{ + */ + +/** + * @brief Send an amount of data in interrupt mode + * Function called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT() + * @param huart: UART handle + * @retval HAL status + */ +HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) +{ + uint16_t* tmp; + + if ((huart->State == HAL_UART_STATE_BUSY_TX) || (huart->State == HAL_UART_STATE_BUSY_TX_RX)) + { + + if(huart->TxXferCount == 0) + { + /* Disable the UART Transmit Data Register Empty Interrupt */ + __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); + + /* Enable the UART Transmit Complete Interrupt */ + __HAL_UART_ENABLE_IT(huart, UART_IT_TC); + + return HAL_OK; + } + else + { + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + tmp = (uint16_t*) huart->pTxBuffPtr; + huart->Instance->TDR = (*tmp & (uint16_t)0x01FF); + huart->pTxBuffPtr += 2; + } + else + { + huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFF); + } + + huart->TxXferCount--; + + return HAL_OK; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in interrupt mode + * Function called under interruption only, once + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart: UART handle + * @retval HAL status + */ +HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) +{ + uint16_t* tmp; + uint16_t uhMask = huart->Mask; + + if((huart->State == HAL_UART_STATE_BUSY_RX) || (huart->State == HAL_UART_STATE_BUSY_TX_RX)) + { + + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + tmp = (uint16_t*) huart->pRxBuffPtr ; + *tmp = (uint16_t)(huart->Instance->RDR & uhMask); + huart->pRxBuffPtr +=2; + } + else + { + *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); + } + + if(--huart->RxXferCount == 0) + { + __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); + + /* Check if a transmit Process is ongoing or not */ + if(huart->State == HAL_UART_STATE_BUSY_TX_RX) + { + huart->State = HAL_UART_STATE_BUSY_TX; + } + else + { + /* Disable the UART Parity Error Interrupt */ + __HAL_UART_DISABLE_IT(huart, UART_IT_PE); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); + + huart->State = HAL_UART_STATE_READY; + } + + HAL_UART_RxCpltCallback(huart); + + return HAL_OK; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Check the UART Idle State + * @param huart: uart handle + * @retval HAL status + */ +HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) +{ + /* Initialize the UART ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Check if the Transmitter is enabled */ + if((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + { + /* Wait until TEACK flag is set */ + if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + { + /* Timeout Occured */ + return HAL_TIMEOUT; + } + } + /* Check if the Receiver is enabled */ + if((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + { + /* Wait until REACK flag is set */ + if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + { + /* Timeout Occured */ + return HAL_TIMEOUT; + } + } + + /* Initialize the UART State */ + huart->State= HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief This function handles UART Communication Timeout. + * @param huart: UART handle + * @param Flag: specifies the UART flag to check. + * @param Status: The new Flag status (SET or RESET). + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + + /* Wait until flag is set */ + if(Status == RESET) + { + while(__HAL_UART_GET_FLAG(huart, Flag) == RESET) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); + __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); + __HAL_UART_DISABLE_IT(huart, UART_IT_PE); + __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); + + huart->State = HAL_UART_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_TIMEOUT; + } + } + } + } + else + { + while(__HAL_UART_GET_FLAG(huart, Flag) != RESET) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); + __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); + __HAL_UART_DISABLE_IT(huart, UART_IT_PE); + __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); + + huart->State = HAL_UART_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_TIMEOUT; + } + } + } + } + return HAL_OK; +} + +/** + * @brief DMA UART transmit process complete callback + * @param hdma: DMA handle + * @retval None + */ +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + huart->TxXferCount = 0; + + /* Disable the DMA transfer for transmit request by setting the DMAT bit + in the UART CR3 register */ + huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT); + + /* Wait for UART TC Flag */ + if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, HAL_UART_TXDMA_TIMEOUTVALUE) != HAL_OK) + { + /* Timeout Occured */ + huart->State = HAL_UART_STATE_TIMEOUT; + HAL_UART_ErrorCallback(huart); + } + else + { + /* No Timeout */ + /* Check if a receive process is ongoing or not */ + if(huart->State == HAL_UART_STATE_BUSY_TX_RX) + { + huart->State = HAL_UART_STATE_BUSY_RX; + } + else + { + huart->State = HAL_UART_STATE_READY; + } + HAL_UART_TxCpltCallback(huart); + } +} + +/** + * @brief DMA UART transmit process half complete callback + * @param hdma : DMA handle + * @retval None + */ +static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + HAL_UART_TxHalfCpltCallback(huart); +} + +/** + * @brief DMA UART receive process complete callback + * @param hdma: DMA handle + * @retval None + */ +static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + huart->RxXferCount = 0; + + /* Disable the DMA transfer for the receiver request by setting the DMAR bit + in the UART CR3 register */ + huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR); + + /* Check if a transmit Process is ongoing or not */ + if(huart->State == HAL_UART_STATE_BUSY_TX_RX) + { + huart->State = HAL_UART_STATE_BUSY_TX; + } + else + { + huart->State = HAL_UART_STATE_READY; + } + HAL_UART_RxCpltCallback(huart); +} + +/** + * @brief DMA UART receive process half complete callback + * @param hdma : DMA handle + * @retval None + */ +static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + HAL_UART_RxHalfCpltCallback(huart); +} + +/** + * @brief DMA UART communication error callback + * @param hdma: DMA handle + * @retval None + */ +static void UART_DMAError(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + huart->RxXferCount = 0; + huart->TxXferCount = 0; + huart->State= HAL_UART_STATE_READY; + huart->ErrorCode |= HAL_UART_ERROR_DMA; + HAL_UART_ErrorCallback(huart); +} + +/** + * @brief Configure the UART peripheral + * @param huart: uart handle + * @retval None + */ +HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) +{ + uint32_t tmpreg = 0x00000000; + UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED; + uint16_t brrtemp = 0x0000; + uint16_t usartdiv = 0x0000; + HAL_StatusTypeDef ret = HAL_OK; + + /* Check the parameters */ + assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); + assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); + assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); + assert_param(IS_UART_PARITY(huart->Init.Parity)); + assert_param(IS_UART_MODE(huart->Init.Mode)); + assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); + assert_param(IS_UART_ONEBIT_SAMPLING(huart->Init.OneBitSampling)); + + + /*-------------------------- USART CR1 Configuration -----------------------*/ + /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure + * the UART Word Length, Parity, Mode and oversampling: + * set the M bits according to huart->Init.WordLength value + * set PCE and PS bits according to huart->Init.Parity value + * set TE and RE bits according to huart->Init.Mode value + * set OVER8 bit according to huart->Init.OverSampling value */ + tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; + MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg); + + /*-------------------------- USART CR2 Configuration -----------------------*/ + /* Configure the UART Stop Bits: Set STOP[13:12] bits according + * to huart->Init.StopBits value */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); + + /*-------------------------- USART CR3 Configuration -----------------------*/ + /* Configure + * - UART HardWare Flow Control: set CTSE and RTSE bits according + * to huart->Init.HwFlowCtl value + * - one-bit sampling method versus three samples' majority rule according + * to huart->Init.OneBitSampling */ + tmpreg = (uint32_t)huart->Init.HwFlowCtl | huart->Init.OneBitSampling ; + MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT), tmpreg); + + /*-------------------------- USART BRR Configuration -----------------------*/ + __HAL_UART_GETCLOCKSOURCE(huart, clocksource); + + /* Check the Over Sampling to set Baud Rate Register */ + if (huart->Init.OverSampling == UART_OVERSAMPLING_8) + { + switch (clocksource) + { + case UART_CLOCKSOURCE_PCLK1: + usartdiv = (uint16_t)(__DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); + break; + case UART_CLOCKSOURCE_HSI: + usartdiv = (uint16_t)(__DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate)); + break; + case UART_CLOCKSOURCE_SYSCLK: + usartdiv = (uint16_t)(__DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); + break; + case UART_CLOCKSOURCE_LSE: + usartdiv = (uint16_t)(__DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate)); + break; + case UART_CLOCKSOURCE_UNDEFINED: + default: + ret = HAL_ERROR; + break; + } + + brrtemp = usartdiv & 0xFFF0; + brrtemp |= (uint16_t) ((usartdiv & (uint16_t)0x000F) >> 1U); + huart->Instance->BRR = brrtemp; + } + else + { + switch (clocksource) + { + case UART_CLOCKSOURCE_PCLK1: + huart->Instance->BRR = (uint16_t)(__DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); + break; + case UART_CLOCKSOURCE_HSI: + huart->Instance->BRR = (uint16_t)(__DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate)); + break; + case UART_CLOCKSOURCE_SYSCLK: + huart->Instance->BRR = (uint16_t)(__DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); + break; + case UART_CLOCKSOURCE_LSE: + huart->Instance->BRR = (uint16_t)(__DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate)); + break; + case UART_CLOCKSOURCE_UNDEFINED: + default: + ret = HAL_ERROR; + break; + } + } + + return ret; + +} + +/** + * @brief Configure the UART peripheral advanced feautures + * @param huart: uart handle + * @retval None + */ +void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) +{ + /* Check whether the set of advanced features to configure is properly set */ + assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); + + /* if required, configure TX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) + { + assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); + } + + /* if required, configure RX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) + { + assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); + } + + /* if required, configure data inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) + { + assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); + } + + /* if required, configure RX/TX pins swap */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) + { + assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); + } + + /* if required, configure RX overrun detection disabling */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) + { + assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); + } + + /* if required, configure DMA disabling on reception error */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) + { + assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); + } + + /* if required, configure auto Baud rate detection scheme */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) + { + assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); + /* set auto Baudrate detection parameters if detection is enabled */ + if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) + { + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); + } + } + + /* if required, configure MSB first on communication line */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) + { + assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); + } +} + +/** + * @} + */ + +#endif /* HAL_UART_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.c b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.c new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.c @@ -0,0 +1,673 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_uart_ex.c + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief Extended UART HAL module driver. + * + * This file provides firmware functions to manage the following extended + * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + * + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The Extended UART HAL driver can be used as follows: + + (#) Declare a UART_HandleTypeDef handle structure. + + (#) For the UART RS485 Driver Enabled mode, initialize the UART registers + by calling the HAL_RS485Ex_Init() API. + + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup UARTEx UARTEx Extended HAL module driver + * @brief UART Extended HAL module driver + * @{ + */ + +#ifdef HAL_UART_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/** @defgroup UARTEx_Private_Functions UARTEx Private Functions + * @{ + */ +#if !defined(STM32F030x6) && !defined(STM32F030x8) +static void UART_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); +#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */ +static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart); + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions + * @{ + */ + +/** @defgroup UARTEx_Exported_Functions_Group2 Extended IO operation function + * @brief UART Interrupt handling function + * +@verbatim + =============================================================================== + ##### IO operation function ##### + =============================================================================== + This subsection provides functions allowing to manage the UART interrupts + and to handle Wake up interrupt call-back. + + (#) Non-Blocking mode API with Interrupt is : + (+) HAL_UART_IRQHandler() + + (#) Callback provided in No_Blocking mode: + (+) HAL_UART_WakeupCallback() + + +@endverbatim + * @{ + */ + +/** + * @brief This function handles UART interrupt request. + * @param huart: uart handle + * @retval None + */ +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) +{ + /* UART parity error interrupt occurred -------------------------------------*/ + if((__HAL_UART_GET_IT(huart, UART_IT_PE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_PE) != RESET)) + { + __HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF); + + huart->ErrorCode |= HAL_UART_ERROR_PE; + /* Set the UART state ready to be able to start again the process */ + huart->State = HAL_UART_STATE_READY; + } + + /* UART frame error interrupt occured --------------------------------------*/ + if((__HAL_UART_GET_IT(huart, UART_IT_FE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET)) + { + __HAL_UART_CLEAR_IT(huart, UART_CLEAR_FEF); + + huart->ErrorCode |= HAL_UART_ERROR_FE; + /* Set the UART state ready to be able to start again the process */ + huart->State = HAL_UART_STATE_READY; + } + + /* UART noise error interrupt occured --------------------------------------*/ + if((__HAL_UART_GET_IT(huart, UART_IT_NE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET)) + { + __HAL_UART_CLEAR_IT(huart, UART_CLEAR_NEF); + + huart->ErrorCode |= HAL_UART_ERROR_NE; + /* Set the UART state ready to be able to start again the process */ + huart->State = HAL_UART_STATE_READY; + } + + /* UART Over-Run interrupt occured -----------------------------------------*/ + if((__HAL_UART_GET_IT(huart, UART_IT_ORE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET)) + { + __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF); + + huart->ErrorCode |= HAL_UART_ERROR_ORE; + /* Set the UART state ready to be able to start again the process */ + huart->State = HAL_UART_STATE_READY; + } + + /* Call UART Error Call back function if need be --------------------------*/ + if(huart->ErrorCode != HAL_UART_ERROR_NONE) + { + HAL_UART_ErrorCallback(huart); + } + +#if !defined(STM32F030x6) && !defined(STM32F030x8) + /* UART wakeup from Stop mode interrupt occurred -------------------------------------*/ + if((__HAL_UART_GET_IT(huart, UART_IT_WUF) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_WUF) != RESET)) + { + __HAL_UART_CLEAR_IT(huart, UART_CLEAR_WUF); + /* Set the UART state ready to be able to start again the process */ + huart->State = HAL_UART_STATE_READY; + HAL_UART_WakeupCallback(huart); + } +#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */ + + /* UART in mode Receiver ---------------------------------------------------*/ + if((__HAL_UART_GET_IT(huart, UART_IT_RXNE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE) != RESET)) + { + UART_Receive_IT(huart); + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } + + + /* UART in mode Transmitter ------------------------------------------------*/ + if((__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET) &&(__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE) != RESET)) + { + UART_Transmit_IT(huart); + } + + /* UART in mode Transmitter ------------------------------------------------*/ + if((__HAL_UART_GET_IT(huart, UART_IT_TC) != RESET) &&(__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET)) + { + UART_EndTransmit_IT(huart); + } +} + +#if !defined(STM32F030x6) && !defined(STM32F030x8) +/** + * @brief UART wakeup from Stop mode callback + * @param huart: uart handle + * @retval None + */ + __weak void HAL_UART_WakeupCallback(UART_HandleTypeDef *huart) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_WakeupCallback can be implemented in the user file + */ +} +#endif /*!defined(STM32F030x6) && !defined(STM32F030x8)*/ + +/** + * @} + */ + +/** @defgroup UARTEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions + * @brief Extended Initialization and Configuration Functions + * +@verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USARTx or the UARTy + in asynchronous mode. + (+) For the asynchronous mode only these parameters can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + Depending on the frame length defined by the M bit (8-bits or 9-bits), + the possible UART frame formats are as listed in the following table: + |-----------|-----------|---------------------------------------| + | M1M0 bits | PCE bit | UART frame | + |-----------------------|---------------------------------------| + | 00 | 0 | | SB | 8-bit data | STB | | + |-----------|-----------|---------------------------------------| + | 00 | 1 | | SB | 7-bit data | PB | STB | | + |-----------|-----------|---------------------------------------| + | 01 | 0 | | SB | 9-bit data | STB | | + |-----------|-----------|---------------------------------------| + | 01 | 1 | | SB | 8-bit data | PB | STB | | + +---------------------------------------------------------------+ + | 10 | 0 | | SB | 7-bit data | STB | | + |-----------|-----------|---------------------------------------| + | 10 | 1 | | SB | 6-bit data | PB | STB | | + +---------------------------------------------------------------+ + (++) Hardware flow control + (++) Receiver/transmitter modes + (++) Over Sampling Method + (++) One-Bit Sampling Method + (+) For the asynchronous mode, the following advanced features can be configured as well: + (++) TX and/or RX pin level inversion + (++) data logical level inversion + (++) RX and TX pins swap + (++) RX overrun detection disabling + (++) DMA disabling on RX error + (++) MSB first on communication line + (++) auto Baud rate detection + [..] + The HAL_LIN_Init() and HAL_RS485Ex_Init() APIs follows respectively the LIN and + the UART RS485 mode configuration procedures (details for the procedures are + available in reference manual). + +@endverbatim + * @{ + */ + + +/** + * @brief Initializes the RS485 Driver enable feature according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle . + * @param huart: uart handle + * @param UART_DEPolarity: select the driver enable polarity + * This parameter can be one of the following values: + * @arg UART_DE_POLARITY_HIGH: DE signal is active high + * @arg UART_DE_POLARITY_LOW: DE signal is active low + * @param UART_DEAssertionTime: Driver Enable assertion time + * 5-bit value defining the time between the activation of the DE (Driver Enable) + * signal and the beginning of the start bit. It is expressed in sample time + * units (1/8 or 1/16 bit time, depending on the oversampling rate) + * @param UART_DEDeassertionTime: Driver Enable deassertion time + * 5-bit value defining the time between the end of the last stop bit, in a + * transmitted message, and the de-activation of the DE (Driver Enable) signal. + * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the + * oversampling rate). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t UART_DEPolarity, uint32_t UART_DEAssertionTime, uint32_t UART_DEDeassertionTime) +{ + uint32_t temp = 0x0; + + /* Check the UART handle allocation */ + if(huart == NULL) + { + return HAL_ERROR; + } + /* Check the Driver Enable UART instance */ + assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance)); + + /* Check the Driver Enable polarity */ + assert_param(IS_UART_DE_POLARITY(UART_DEPolarity)); + + /* Check the Driver Enable assertion time */ + assert_param(IS_UART_ASSERTIONTIME(UART_DEAssertionTime)); + + /* Check the Driver Enable deassertion time */ + assert_param(IS_UART_DEASSERTIONTIME(UART_DEDeassertionTime)); + + if(huart->State == HAL_UART_STATE_RESET) + { + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); + } + + huart->State = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */ + huart->Instance->CR3 |= USART_CR3_DEM; + + /* Set the Driver Enable polarity */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, UART_DEPolarity); + + /* Set the Driver Enable assertion and deassertion times */ + temp = (UART_DEAssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS); + temp |= (UART_DEDeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS); + MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT|USART_CR1_DEAT), temp); + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->State to Ready */ + return (UART_CheckIdleState(huart)); +} + + +#if !defined(STM32F030x6) && !defined(STM32F030x8) +/** + * @brief Initializes the LIN mode according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle . + * @param huart: uart handle + * @param BreakDetectLength: specifies the LIN break detection length. + * This parameter can be one of the following values: + * @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection + * @arg UART_LINBREAKDETECTLENGTH_11B: 11-bit break detection + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength) +{ + /* Check the UART handle allocation */ + if(huart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); + assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength)); + + /* LIN mode limited to 16-bit oversampling only */ + if(huart->Init.OverSampling == UART_OVERSAMPLING_8) + { + return HAL_ERROR; + } + + /* Init the low level hardware : GPIO, CLOCK, CORTEX */ + HAL_UART_MspInit(huart); + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* In LIN mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register.*/ + huart->Instance->CR2 &= ~(USART_CR2_CLKEN); + huart->Instance->CR3 &= ~(USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN); + + /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ + huart->Instance->CR2 |= USART_CR2_LINEN; + + /* Set the USART LIN Break detection length. */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength); + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->State to Ready */ + return (UART_CheckIdleState(huart)); +} +#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */ +/** + * @} + */ + +/** @defgroup UARTEx_Exported_Functions_Group3 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control function ##### + =============================================================================== + [..] + This subsection provides extended functions allowing to control the UART. + (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address + detection length to more than 4 bits for multiprocessor address mark wake up. + (+) HAL_UART_EnableStopMode() API allows the UART to wake up the MCU from Stop mode as + long as UART clock is HSI or LSE + (+) HAL_UART_DisableStopMode() API disables the above feature + (+) HAL_MultiProcessorEx_AddressLength_Set() API configures the address length when the + wake-up event is the address match feature + (+) UART_Wakeup_AddressConfig() API sets the reference address used when address + match feature is carried out + +@endverbatim + * @{ + */ + +#if !defined(STM32F030x6) && !defined(STM32F030x8) +/** + * @brief Set Wakeup from Stop mode interrupt flag selection + * @param huart: uart handle, + * @param WakeUpSelection: address match, Start Bit detection or RXNE bit status. + * This parameter can be one of the following values: + * @arg UART_WAKEUP_ON_ADDRESS + * @arg UART_WAKEUP_ON_STARTBIT + * @arg UART_WAKEUP_ON_READDATA_NONEMPTY + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) +{ + /* Check parameters */ + assert_param(IS_UART_WAKEUP_INSTANCE(huart->Instance)); + assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->State = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the wake-up selection scheme */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent); + + if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS) + { + UART_Wakeup_AddressConfig(huart, WakeUpSelection); + } + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* Wait until REACK flag is set */ + if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + { + return HAL_TIMEOUT; + } + else + { + /* Initialize the UART State */ + huart->State= HAL_UART_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(huart); + return HAL_OK; + } +} + +/** + * @brief Enable UART Stop Mode + * The UART is able to wake up the MCU from Stop mode as long as UART clock is HSI or LSE + * @param huart: uart handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) +{ + /* Check parameter */ + assert_param(IS_UART_WAKEUP_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->State = HAL_UART_STATE_BUSY; + + /* Set the USART UESM bit */ + huart->Instance->CR1 |= USART_CR1_UESM; + + huart->State = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Disable UART Stop Mode + * @param huart: uart handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) +{ + /* Check parameter */ + assert_param(IS_UART_WAKEUP_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->State = HAL_UART_STATE_BUSY; + + /* Clear USART UESM bit */ + huart->Instance->CR1 &= ~(USART_CR1_UESM); + + huart->State = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */ + +/** + * @brief By default in multiprocessor mode, when the wake up method is set + * to address mark, the UART handles only 4-bit long addresses detection. + * This API allows to enable longer addresses detection (6-, 7- or 8-bit + * long): + * - 6-bit address detection in 7-bit data mode + * - 7-bit address detection in 8-bit data mode + * - 8-bit address detection in 9-bit data mode + * @param huart: UART handle + * @param AddressLength: this parameter can be one of the following values: + * @arg UART_ADDRESS_DETECT_4B: 4-bit long address + * @arg UART_ADDRESS_DETECT_7B: 6-, 7- or 8-bit long address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength) +{ + /* Check the UART handle allocation */ + if(huart == NULL) + { + return HAL_ERROR; + } + + /* Check the address length parameter */ + assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength)); + + huart->State = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the address length */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength); + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->State to Ready */ + return (UART_CheckIdleState(huart)); +} + + +#if !defined(STM32F030x6) && !defined(STM32F030x8) +/** + * @brief Initializes the UART wake-up from stop mode parameters when triggered by address detection. + * @param huart: uart handle + * @param WakeUpSelection: UART wake up from stop mode parameters + * @retval HAL status + */ +static void UART_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) +{ + /* Check parmeters */ + assert_param(IS_UART_WAKEUP_INSTANCE(huart->Instance)); + assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength)); + + /* Set the USART address length */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength); + + /* Set the USART address node */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS)); +} +#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */ + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup UARTEx_Private_Functions + * @{ + */ + +/** + * @brief Wraps up transmission in non blocking mode. + * @param huart: pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) +{ + /* Disable the UART Transmit Complete Interrupt */ + __HAL_UART_DISABLE_IT(huart, UART_IT_TC); + + /* Check if a receive process is ongoing or not */ + if(huart->State == HAL_UART_STATE_BUSY_TX_RX) + { + huart->State = HAL_UART_STATE_BUSY_RX; + } + else + { + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); + + huart->State = HAL_UART_STATE_READY; + } + + HAL_UART_TxCpltCallback(huart); + + return HAL_OK; +} + +/** + * @} + */ + +#endif /* HAL_UART_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_usart.c b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_usart.c new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_usart.c @@ -0,0 +1,1831 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_usart.c + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief USART HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Errors functions + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The USART HAL driver can be used as follows: + + (#) Declare a USART_HandleTypeDef handle structure. + (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit ()API: + (##) Enable the USARTx interface clock. + (##) USART pins configuration: + (+++) Enable the clock for the USART GPIOs. + (+++) Configure these USART pins as alternate function pull-up. + (##) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(), + HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs): + (+++) Configure the USARTx interrupt priority. + (+++) Enable the NVIC USART IRQ handle. + (##) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA() + HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs): + (+++) Declare a DMA handle structure for the Tx/Rx channel. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx channel. + (+++) Associate the initilalized DMA handle to the USART DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. + + (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware + flow control and Mode(Receiver/Transmitter) in the husart Init structure. + + (#) Initialize the USART registers by calling the HAL_USART_Init() API: + (++) These APIs configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + by calling the customed HAL_USART_MspInit(&husart) API. + + -@@- The specific USART interrupts (Transmission complete interrupt, + RXNE interrupt and Error Interrupts) will be managed using the macros + __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process. + + (#) Three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Send an amount of data in blocking mode using HAL_USART_Transmit() + (+) Receive an amount of data in blocking mode using HAL_USART_Receive() + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Send an amount of data in non blocking mode using HAL_USART_Transmit_IT() + (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback + (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_USART_TxCpltCallback + (+) Receive an amount of data in non blocking mode using HAL_USART_Receive_IT() + (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback + (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_USART_RxCpltCallback + (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_USART_ErrorCallback + + *** DMA mode IO operation *** + ============================== + [..] + (+) Send an amount of data in non blocking mode (DMA) using HAL_USART_Transmit_DMA() + (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback + (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_USART_TxCpltCallback + (+) Receive an amount of data in non blocking mode (DMA) using HAL_USART_Receive_DMA() + (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback + (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_USART_RxCpltCallback + (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_USART_ErrorCallback + (+) Pause the DMA Transfer using HAL_USART_DMAPause() + (+) Resume the DMA Transfer using HAL_USART_DMAResume() + (+) Stop the DMA Transfer using HAL_USART_DMAStop() + + *** USART HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in USART HAL driver. + + (+) __HAL_USART_ENABLE: Enable the USART peripheral + (+) __HAL_USART_DISABLE: Disable the USART peripheral + (+) __HAL_USART_GET_FLAG : Check whether the specified USART flag is set or not + (+) __HAL_USART_CLEAR_FLAG : Clear the specified USART pending flag + (+) __HAL_USART_ENABLE_IT: Enable the specified USART interrupt + (+) __HAL_USART_DISABLE_IT: Disable the specified USART interrupt + + [..] + (@) You can refer to the USART HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup USART USART HAL module driver + * @brief HAL USART Synchronous module driver + * @{ + */ +#ifdef HAL_USART_MODULE_ENABLED +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup USART_Private_Constants USART Private Constants + * @{ + */ +#define DUMMY_DATA ((uint16_t) 0xFFFF) +#define TEACK_REACK_TIMEOUT ((uint32_t) 1000) +#define USART_TXDMA_TIMEOUTVALUE 22000 +#define USART_TIMEOUT_VALUE 22000 +#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ + USART_CR1_TE | USART_CR1_RE)) +#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | \ + USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP)) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup USART_Private_Functions USART Private Functions + * @{ + */ +static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); +static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); +static void USART_DMAError(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout); +static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart); +static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart); +static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart); +static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart); +static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart); +static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + + +/** @defgroup USART_Exported_Functions USART Exported Functions + * @{ + */ + +/** @defgroup USART_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and Configuration functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USART + in asynchronous and in synchronous modes. + (+) For the asynchronous mode only these parameters can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + Depending on the frame length defined by the M bit (8-bits or 9-bits) + or by the M1 and M0 bits (7-bit, 8-bit or 9-bit), + the possible USART frame formats are as listed in the following table: + +---------------------------------------------------------------+ + | M bit | PCE bit | USART frame | + |-----------|-----------|---------------------------------------| + | 0 | 0 | | SB | 8-bit data | STB | | + |-----------|-----------|---------------------------------------| + | 0 | 1 | | SB | 7-bit data | PB | STB | | + |-----------|-----------|---------------------------------------| + | 1 | 0 | | SB | 9-bit data | STB | | + |-----------|-----------|---------------------------------------| + | 1 | 1 | | SB | 8-bit data | PB | STB | | + +---------------------------------------------------------------+ + | M1M0 bits | PCE bit | USART frame | + |-----------------------|---------------------------------------| + | 10 | 0 | | SB | 7-bit data | STB | | + |-----------|-----------|---------------------------------------| + | 10 | 1 | | SB | 6-bit data | PB | STB | | + +---------------------------------------------------------------+ + (++) USART polarity + (++) USART phase + (++) USART LastBit + (++) Receiver/transmitter modes + + [..] + The HAL_USART_Init() function follows the USART synchronous configuration + procedure (details for the procedure are available in reference manual). + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the USART mode according to the specified + * parameters in the USART_InitTypeDef and create the associated handle . + * @param husart: usart handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) +{ + /* Check the USART handle allocation */ + if(husart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_USART_INSTANCE(husart->Instance)); + + if(husart->State == HAL_USART_STATE_RESET) + { + /* Init the low level hardware : GPIO, CLOCK */ + HAL_USART_MspInit(husart); + } + + husart->State = HAL_USART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_USART_DISABLE(husart); + + /* Set the Usart Communication parameters */ + if (USART_SetConfig(husart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* In Synchronous mode, the following bits must be kept cleared: + - LINEN bit in the USART_CR2 register + - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/ + husart->Instance->CR2 &= ~USART_CR2_LINEN; + husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN); + + /* Enable the Peripharal */ + __HAL_USART_ENABLE(husart); + + /* TEACK and/or REACK to check before moving husart->State to Ready */ + return (USART_CheckIdleState(husart)); +} + +/** + * @brief DeInitializes the USART peripheral + * @param husart: usart handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) +{ + /* Check the USART handle allocation */ + if(husart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_USART_INSTANCE(husart->Instance)); + + husart->State = HAL_USART_STATE_BUSY; + + husart->Instance->CR1 = 0x0; + husart->Instance->CR2 = 0x0; + husart->Instance->CR3 = 0x0; + + /* DeInit the low level hardware */ + HAL_USART_MspDeInit(husart); + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_RESET; + + /* Process Unlock */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief USART MSP Init + * @param husart: usart handle + * @retval None + */ + __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USART_MspInit can be implemented in the user file + */ +} + +/** + * @brief USART MSP DeInit + * @param husart: usart handle + * @retval None + */ + __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USART_MspDeInit can be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup USART_Exported_Functions_Group2 IO operation functions + * @brief USART Transmit and Receive functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to manage the USART synchronous + data transfers. + + [..] + The USART supports master mode only: it cannot receive or send data related to an input + clock (SCLK is always an output). + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) Non Blocking mode: The communication is performed using Interrupts + or DMA, These APIs return the HAL status. + The end of the data processing will be indicated through the + dedicated USART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks + will be executed respectivelly at the end of the transmit or Receive process + The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected + + (#) Blocking mode APIs are : + (++) HAL_USART_Transmit()in simplex mode + (++) HAL_USART_Receive() in full duplex receive only + (++) HAL_USART_TransmitReceive() in full duplex mode + + (#) Non Blocking mode APIs with Interrupt are : + (++) HAL_USART_Transmit_IT()in simplex mode + (++) HAL_USART_Receive_IT() in full duplex receive only + (++) HAL_USART_TransmitReceive_IT()in full duplex mode + (++) HAL_USART_IRQHandler() + + (#) Non Blocking mode functions with DMA are : + (++) HAL_USART_Transmit_DMA()in simplex mode + (++) HAL_USART_Receive_DMA() in full duplex receive only + (++) HAL_USART_TransmitReceive_DMA() in full duplex mode + (++) HAL_USART_DMAPause() + (++) HAL_USART_DMAResume() + (++) HAL_USART_DMAStop() + + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (++) HAL_USART_TxCpltCallback() + (++) HAL_USART_RxCpltCallback() + (++) HAL_USART_TxHalfCpltCallback() + (++) HAL_USART_RxHalfCpltCallback() + (++) HAL_USART_ErrorCallback() + (++) HAL_USART_TxRxCpltCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Simplex Send an amount of data in blocking mode + * @param husart: USART handle + * @param pTxData: pointer to data buffer + * @param Size: amount of data to be sent + * @param Timeout : Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout) +{ + uint16_t* tmp=0; + + if(husart->State == HAL_USART_STATE_READY) + { + if((pTxData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_TX; + + husart->TxXferSize = Size; + husart->TxXferCount = Size; + + /* Check the remaining data to be sent */ + while(husart->TxXferCount > 0) + { + husart->TxXferCount--; + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + tmp = (uint16_t*) pTxData; + husart->Instance->TDR = (*tmp & (uint16_t)0x01FF); + pTxData += 2; + } + else + { + husart->Instance->TDR = (*pTxData++ & (uint8_t)0xFF); + } + } + + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in blocking mode + * To receive synchronous data, dummy data are simultaneously transmitted + * @param husart: USART handle + * @param pRxData: pointer to data buffer + * @param Size: amount of data to be received + * @param Timeout : Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) +{ + uint16_t* tmp=0; + uint16_t uhMask; + + if(husart->State == HAL_USART_STATE_READY) + { + if((pRxData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(husart); + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_RX; + + husart->RxXferSize = Size; + husart->RxXferCount = Size; + + /* Computation of USART mask to apply to RDR register */ + __HAL_USART_MASK_COMPUTATION(husart); + uhMask = husart->Mask; + + /* as long as data have to be received */ + while(husart->RxXferCount > 0) + { + husart->RxXferCount--; + + /* Wait until TC flag is set to send dummy byte in order to generate the + * clock for the slave to send data. + * Whatever the frame length (7, 8 or 9-bit long), the same dummy value + * can be written for all the cases. */ + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x0FF); + + /* Wait for RXNE Flag */ + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + tmp = (uint16_t*) pRxData ; + *tmp = (uint16_t)(husart->Instance->RDR & uhMask); + pRxData +=2; + } + else + { + *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); + } + } + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Full-Duplex Send and Receive an amount of data in blocking mode + * @param husart: USART handle + * @param pTxData: pointer to TX data buffer + * @param pRxData: pointer to RX data buffer + * @param Size: amount of data to be sent (same amount to be received) + * @param Timeout : Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) +{ + uint16_t* tmp=0; + uint16_t uhMask; + + if(husart->State == HAL_USART_STATE_READY) + { + if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(husart); + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_RX; + + husart->RxXferSize = Size; + husart->TxXferSize = Size; + husart->TxXferCount = Size; + husart->RxXferCount = Size; + + /* Computation of USART mask to apply to RDR register */ + __HAL_USART_MASK_COMPUTATION(husart); + uhMask = husart->Mask; + + /* Check the remain data to be sent */ + while(husart->TxXferCount > 0) + { + husart->TxXferCount--; + husart->RxXferCount--; + + /* Wait until TC flag is set to send data */ + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + tmp = (uint16_t*) pTxData; + husart->Instance->TDR = (*tmp & uhMask); + pTxData += 2; + } + else + { + husart->Instance->TDR = (*pTxData++ & (uint8_t)uhMask); + } + + /* Wait for RXNE Flag */ + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + tmp = (uint16_t*) pRxData ; + *tmp = (uint16_t)(husart->Instance->RDR & uhMask); + pRxData +=2; + } + else + { + *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); + } + } + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Send an amount of data in interrupt mode + * @param husart: USART handle + * @param pTxData: pointer to data buffer + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size) +{ + if(husart->State == HAL_USART_STATE_READY) + { + if((pTxData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->pTxBuffPtr = pTxData; + husart->TxXferSize = Size; + husart->TxXferCount = Size; + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_TX; + + /* The USART Error Interrupts: (Frame error, noise error, overrun error) + are not managed by the USART Transmit Process to avoid the overrun interrupt + when the usart mode is configured for transmit and receive "USART_MODE_TX_RX" + to benefit for the frame error and noise interrupts the usart mode should be + configured only for transmit "USART_MODE_TX" */ + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Enable the USART Transmit Data Register Empty Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TXE); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in blocking mode + * To receive synchronous data, dummy data are simultaneously transmitted + * @param husart: usart handle + * @param pRxData: pointer to data buffer + * @param Size: amount of data to be received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size) +{ + if(husart->State == HAL_USART_STATE_READY) + { + if((pRxData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(husart); + + husart->pRxBuffPtr = pRxData; + husart->RxXferSize = Size; + husart->RxXferCount = Size; + + __HAL_USART_MASK_COMPUTATION(husart); + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_RX; + + /* Enable the USART Parity Error Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_PE); + + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_USART_ENABLE_IT(husart, USART_IT_ERR); + + /* Enable the USART Data Register not empty Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE); + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + + /* Send dummy byte in order to generate the clock for the Slave to send the next data */ + if(husart->Init.WordLength == USART_WORDLENGTH_9B) + { + husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x01FF); + } + else + { + husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x00FF); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Full-Duplex Send and Receive an amount of data in interrupt mode + * @param husart: USART handle + * @param pTxData: pointer to TX data buffer + * @param pRxData: pointer to RX data buffer + * @param Size: amount of data to be sent (same amount to be received) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +{ + if(husart->State == HAL_USART_STATE_READY) + { + if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(husart); + + husart->pRxBuffPtr = pRxData; + husart->RxXferSize = Size; + husart->RxXferCount = Size; + husart->pTxBuffPtr = pTxData; + husart->TxXferSize = Size; + husart->TxXferCount = Size; + + /* Computation of USART mask to apply to RDR register */ + __HAL_USART_MASK_COMPUTATION(husart); + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_TX_RX; + + /* Enable the USART Data Register not empty Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE); + + /* Enable the USART Parity Error Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_PE); + + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_USART_ENABLE_IT(husart, USART_IT_ERR); + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Enable the USART Transmit Data Register Empty Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TXE); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Send an amount of data in DMA mode + * @param husart: USART handle + * @param pTxData: pointer to data buffer + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size) +{ + uint32_t *tmp=0; + + if(husart->State == HAL_USART_STATE_READY) + { + if((pTxData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(husart); + + husart->pTxBuffPtr = pTxData; + husart->TxXferSize = Size; + husart->TxXferCount = Size; + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_TX; + + /* Set the USART DMA transfer complete callback */ + husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt; + + /* Set the USART DMA Half transfer complete callback */ + husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt; + + /* Set the DMA error callback */ + husart->hdmatx->XferErrorCallback = USART_DMAError; + + /* Enable the USART transmit DMA channel */ + tmp = (uint32_t*)&pTxData; + HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size); + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the USART CR3 register */ + husart->Instance->CR3 |= USART_CR3_DMAT; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Full-Duplex Receive an amount of data in non-blocking mode + * @param husart: USART handle + * @param pRxData: pointer to data buffer + * @param Size: amount of data to be received + * @note When the USART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position) + * @retval HAL status + * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave. + */ +HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size) +{ + uint32_t *tmp=0; + + if(husart->State == HAL_USART_STATE_READY) + { + if((pRxData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->pRxBuffPtr = pRxData; + husart->RxXferSize = Size; + husart->pTxBuffPtr = pRxData; + husart->TxXferSize = Size; + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_RX; + + /* Set the USART DMA Rx transfer complete callback */ + husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt; + + /* Set the USART DMA Half transfer complete callback */ + husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt; + + /* Set the USART DMA Rx transfer error callback */ + husart->hdmarx->XferErrorCallback = USART_DMAError; + + /* Enable the USART receive DMA channel */ + tmp = (uint32_t*)&pRxData; + HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size); + + /* Enable the USART transmit DMA channel: the transmit channel is used in order + to generate in the non-blocking mode the clock to the slave device, + this mode isn't a simplex receive mode but a full-duplex receive mode */ + tmp = (uint32_t*)&pRxData; + HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the USART CR3 register */ + husart->Instance->CR3 |= USART_CR3_DMAR; + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the USART CR3 register */ + husart->Instance->CR3 |= USART_CR3_DMAT; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Full-Duplex Transmit Receive an amount of data in non blocking mode + * @param husart: usart handle + * @param pTxData: pointer to TX data buffer + * @param pRxData: pointer to RX data buffer + * @param Size: amount of data to be received/sent + * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +{ + uint32_t *tmp=0; + + if(husart->State == HAL_USART_STATE_READY) + { + if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(husart); + + husart->pRxBuffPtr = pRxData; + husart->RxXferSize = Size; + husart->pTxBuffPtr = pTxData; + husart->TxXferSize = Size; + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_TX_RX; + + /* Set the USART DMA Rx transfer complete callback */ + husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt; + + /* Set the USART DMA Half transfer complete callback */ + husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt; + + /* Set the USART DMA Tx transfer complete callback */ + husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt; + + /* Set the USART DMA Half transfer complete callback */ + husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt; + + /* Set the USART DMA Tx transfer error callback */ + husart->hdmatx->XferErrorCallback = USART_DMAError; + + /* Set the USART DMA Rx transfer error callback */ + husart->hdmarx->XferErrorCallback = USART_DMAError; + + /* Enable the USART receive DMA channel */ + tmp = (uint32_t*)&pRxData; + HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size); + + /* Enable the USART transmit DMA channel */ + tmp = (uint32_t*)&pTxData; + HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the USART CR3 register */ + husart->Instance->CR3 |= USART_CR3_DMAR; + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the USART CR3 register */ + husart->Instance->CR3 |= USART_CR3_DMAT; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Pauses the DMA Transfer. + * @param husart: USART handle + * @retval None + */ +HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart) +{ + /* Process Locked */ + __HAL_LOCK(husart); + + if(husart->State == HAL_USART_STATE_BUSY_TX) + { + /* Disable the USART DMA Tx request */ + husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT); + } + else if(husart->State == HAL_USART_STATE_BUSY_RX) + { + /* Disable the USART DMA Rx request */ + husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR); + } + else if(husart->State == HAL_USART_STATE_BUSY_TX_RX) + { + /* Disable the USART DMA Tx request */ + husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT); + /* Disable the USART DMA Rx request */ + husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Resumes the DMA Transfer. + * @param husart: USART handle + * @retval None + */ +HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart) +{ + /* Process Locked */ + __HAL_LOCK(husart); + + if(husart->State == HAL_USART_STATE_BUSY_TX) + { + /* Enable the USART DMA Tx request */ + husart->Instance->CR3 |= USART_CR3_DMAT; + } + else if(husart->State == HAL_USART_STATE_BUSY_RX) + { + /* Enable the USART DMA Rx request */ + husart->Instance->CR3 |= USART_CR3_DMAR; + } + else if(husart->State == HAL_USART_STATE_BUSY_TX_RX) + { + /* Enable the USART DMA Rx request before the DMA Tx request */ + husart->Instance->CR3 |= USART_CR3_DMAR; + /* Enable the USART DMA Tx request */ + husart->Instance->CR3 |= USART_CR3_DMAT; + } + + /* If the USART peripheral is still not enabled, enable it */ + if ((husart->Instance->CR1 & USART_CR1_UE) == 0) + { + /* Enable USART peripheral */ + __HAL_USART_ENABLE(husart); + } + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Stops the DMA Transfer. + * @param husart: USART handle + * @retval None + */ +HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart) +{ + /* Process Locked */ + __HAL_LOCK(husart); + + /* Disable the USART Tx/Rx DMA requests */ + husart->Instance->CR3 &= ~USART_CR3_DMAT; + husart->Instance->CR3 &= ~USART_CR3_DMAR; + + /* Abort the USART DMA tx Channel */ + if(husart->hdmatx != NULL) + { + HAL_DMA_Abort(husart->hdmatx); + } + /* Abort the USART DMA rx Channel */ + if(husart->hdmarx != NULL) + { + HAL_DMA_Abort(husart->hdmarx); + } + + /* Disable USART peripheral */ + __HAL_USART_DISABLE(husart); + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief This function handles USART interrupt request. + * @param husart: USART handle + * @retval None + */ +void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) +{ + + /* USART parity error interrupt occured ------------------------------------*/ + if((__HAL_USART_GET_IT(husart, USART_IT_PE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_PE) != RESET)) + { + __HAL_USART_CLEAR_IT(husart, USART_IT_PE); + husart->ErrorCode |= HAL_USART_ERROR_PE; + /* Set the USART state ready to be able to start again the process */ + husart->State = HAL_USART_STATE_READY; + } + + /* USART frame error interrupt occured -------------------------------------*/ + if((__HAL_USART_GET_IT(husart, USART_IT_FE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR) != RESET)) + { + __HAL_USART_CLEAR_IT(husart, USART_IT_FE); + husart->ErrorCode |= HAL_USART_ERROR_FE; + /* Set the USART state ready to be able to start again the process */ + husart->State = HAL_USART_STATE_READY; + } + + /* USART noise error interrupt occured -------------------------------------*/ + if((__HAL_USART_GET_IT(husart, USART_IT_NE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR) != RESET)) + { + __HAL_USART_CLEAR_IT(husart, USART_IT_NE); + husart->ErrorCode |= HAL_USART_ERROR_NE; + /* Set the USART state ready to be able to start again the process */ + husart->State = HAL_USART_STATE_READY; + } + + /* USART Over-Run interrupt occured ----------------------------------------*/ + if((__HAL_USART_GET_IT(husart, USART_IT_ORE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR) != RESET)) + { + __HAL_USART_CLEAR_IT(husart, USART_IT_ORE); + husart->ErrorCode |= HAL_USART_ERROR_ORE; + /* Set the USART state ready to be able to start again the process */ + husart->State = HAL_USART_STATE_READY; + } + + /* Call USART Error Call back function if need be --------------------------*/ + if(husart->ErrorCode != HAL_USART_ERROR_NONE) + { + HAL_USART_ErrorCallback(husart); + } + + /* USART in mode Receiver --------------------------------------------------*/ + if((__HAL_USART_GET_IT(husart, USART_IT_RXNE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_RXNE) != RESET)) + { + if(husart->State == HAL_USART_STATE_BUSY_RX) + { + USART_Receive_IT(husart); + } + else + { + USART_TransmitReceive_IT(husart); + } + } + + /* USART in mode Transmitter -----------------------------------------------*/ + if((__HAL_USART_GET_IT(husart, USART_IT_TXE) != RESET) &&(__HAL_USART_GET_IT_SOURCE(husart, USART_IT_TXE) != RESET)) + { + if(husart->State == HAL_USART_STATE_BUSY_TX) + { + USART_Transmit_IT(husart); + } + else + { + USART_TransmitReceive_IT(husart); + } + } + + /* USART in mode Transmitter (transmission end) -----------------------------*/ + if((__HAL_USART_GET_IT(husart, USART_IT_TC) != RESET) &&(__HAL_USART_GET_IT_SOURCE(husart, USART_IT_TC) != RESET)) + { + USART_EndTransmit_IT(husart); + } + +} + + +/** + * @brief Tx Transfer completed callbacks + * @param husart: usart handle + * @retval None + */ +__weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USART_TxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Tx Half Transfer completed callbacks. + * @param husart: USART handle + * @retval None + */ + __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart) +{ + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_USART_TxHalfCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks. + * @param husart: USART handle + * @retval None + */ +__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart) +{ + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_USART_RxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Rx Half Transfer completed callbacks + * @param husart: usart handle + * @retval None + */ +__weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USART_RxHalfCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Tx/Rx Transfers completed callback for the non-blocking process + * @param husart: usart handle + * @retval None + */ +__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USART_TxRxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief USART error callbacks + * @param husart: usart handle + * @retval None + */ +__weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USART_ErrorCallback can be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup USART_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief USART control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the USART. + (+) HAL_USART_GetState() API can be helpful to check in run-time the state of the USART peripheral. + (+) USART_SetConfig() API is used to set the USART communication parameters. + (+) USART_CheckIdleState() APi ensures that TEACK and/or REACK bits are set after initialization + +@endverbatim + * @{ + */ + +/** + * @brief return the USART state + * @param husart: USART handle + * @retval HAL state + */ +HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart) +{ + return husart->State; +} + +/** + * @brief Return the USART error code + * @param husart : pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART. + * @retval USART Error Code + */ +uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart) +{ + return husart->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup USART_Private_Functions USART Private Functions + * @brief USART Private functions + * @{ + */ + +/** + * @brief Configure the USART peripheral + * @param husart: USART handle + * @retval None + */ +static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) +{ + uint32_t tmpreg = 0x0; + USART_ClockSourceTypeDef clocksource = USART_CLOCKSOURCE_UNDEFINED; + HAL_StatusTypeDef ret = HAL_OK; + + /* Check the parameters */ + assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity)); + assert_param(IS_USART_PHASE(husart->Init.CLKPhase)); + assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit)); + assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate)); + assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength)); + assert_param(IS_USART_STOPBITS(husart->Init.StopBits)); + assert_param(IS_USART_PARITY(husart->Init.Parity)); + assert_param(IS_USART_MODE(husart->Init.Mode)); + + + /*-------------------------- USART CR1 Configuration -----------------------*/ + /* Clear M, PCE, PS, TE and RE bits and configure + * the USART Word Length, Parity and Mode: + * set the M bits according to husart->Init.WordLength value + * set PCE and PS bits according to husart->Init.Parity value + * set TE and RE bits according to husart->Init.Mode value */ + tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode; + MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg); + + /*---------------------------- USART CR2 Configuration ---------------------*/ + /* Clear and configure the USART Clock, CPOL, CPHA, LBCL and STOP bits: + * set CPOL bit according to husart->Init.CLKPolarity value + * set CPHA bit according to husart->Init.CLKPhase value + * set LBCL bit according to husart->Init.CLKLastBit value + * set STOP[13:12] bits according to husart->Init.StopBits value */ + tmpreg = (uint32_t)(USART_CLOCK_ENABLED); + tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase); + tmpreg |= ((uint32_t)husart->Init.CLKLastBit | (uint32_t)husart->Init.StopBits); + MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg); + + /*-------------------------- USART CR3 Configuration -----------------------*/ + /* no CR3 register configuration */ + + /*-------------------------- USART BRR Configuration -----------------------*/ + __HAL_USART_GETCLOCKSOURCE(husart, clocksource); + switch (clocksource) + { + case USART_CLOCKSOURCE_PCLK1: + husart->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK1Freq() / husart->Init.BaudRate); + break; + case USART_CLOCKSOURCE_HSI: + husart->Instance->BRR = (uint16_t)(HSI_VALUE / husart->Init.BaudRate); + break; + case USART_CLOCKSOURCE_SYSCLK: + husart->Instance->BRR = (uint16_t)(HAL_RCC_GetSysClockFreq() / husart->Init.BaudRate); + break; + case USART_CLOCKSOURCE_LSE: + husart->Instance->BRR = (uint16_t)(LSE_VALUE / husart->Init.BaudRate); + break; + case USART_CLOCKSOURCE_UNDEFINED: + default: + ret = HAL_ERROR; + break; + } + + return ret; +} + +/** + * @brief Check the USART Idle State + * @param husart: USART handle + * @retval HAL status + */ +static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart) +{ + /* Initialize the USART ErrorCode */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + + /* Check if the Transmitter is enabled */ + if((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + { + /* Wait until TEACK flag is set */ + if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, TEACK_REACK_TIMEOUT) != HAL_OK) + { + husart->State= HAL_USART_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + /* Check if the Receiver is enabled */ + if((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + { + /* Wait until REACK flag is set */ + if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, TEACK_REACK_TIMEOUT) != HAL_OK) + { + husart->State= HAL_USART_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + + /* Initialize the USART state*/ + husart->State= HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief This function handles USART Communication Timeout. + * @param husart: USART handle + * @param Flag: specifies the USART flag to check. + * @param Status: The new Flag status (SET or RESET). + * @param Timeout: Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + + /* Wait until flag is set */ + if(Status == RESET) + { + while(__HAL_USART_GET_FLAG(husart, Flag) == RESET) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); + __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE); + __HAL_USART_DISABLE_IT(husart, USART_IT_PE); + __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); + + husart->State= HAL_USART_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_TIMEOUT; + } + } + } + } + else + { + while(__HAL_USART_GET_FLAG(husart, Flag) != RESET) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); + __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE); + __HAL_USART_DISABLE_IT(husart, USART_IT_PE); + __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); + + husart->State= HAL_USART_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_TIMEOUT; + } + } + } + } + return HAL_OK; +} + + +/** + * @brief DMA USART transmit process complete callback + * @param hdma : DMA handle + * @retval None + */ +static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + husart->TxXferCount = 0; + + if(husart->State == HAL_USART_STATE_BUSY_TX) + { + /* Wait for USART TC Flag */ + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, USART_TXDMA_TIMEOUTVALUE) != HAL_OK) + { + /* Timeout Occured */ + husart->State = HAL_USART_STATE_TIMEOUT; + HAL_USART_ErrorCallback(husart); + } + else + { + /* No Timeout */ + /* Disable the DMA transfer for transmit request by setting the DMAT bit + in the USART CR3 register */ + husart->Instance->CR3 &= ~(USART_CR3_DMAT); + husart->State= HAL_USART_STATE_READY; + } + } + /* the usart state is HAL_USART_STATE_BUSY_TX_RX*/ + else + { + husart->State= HAL_USART_STATE_BUSY_RX; + HAL_USART_TxCpltCallback(husart); +} +} + + +/** + * @brief DMA USART transmit process half complete callback + * @param hdma : DMA handle + * @retval None + */ +static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + HAL_USART_TxHalfCpltCallback(husart); +} + +/** + * @brief DMA USART receive process complete callback + * @param hdma : DMA handle + * @retval None + */ +static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + husart->RxXferCount = 0; + + /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit + in USART CR3 register */ + husart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR); + /* similarly, disable the DMA TX transfer that was started to provide the + clock to the slave device */ + husart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT); + + husart->State= HAL_USART_STATE_READY; + + HAL_USART_RxCpltCallback(husart); +} + +/** + * @brief DMA USART receive process half complete callback + * @param hdma : DMA handle + * @retval None + */ +static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + HAL_USART_RxHalfCpltCallback(husart); +} + +/** + * @brief DMA USART communication error callback + * @param hdma : DMA handle + * @retval None + */ +static void USART_DMAError(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + husart->RxXferCount = 0; + husart->TxXferCount = 0; + husart->ErrorCode |= HAL_USART_ERROR_DMA; + husart->State= HAL_USART_STATE_READY; + + HAL_USART_ErrorCallback(husart); +} + +/** + * @brief Simplex Send an amount of data in non-blocking mode. + * Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Transmit_IT() + * @param husart: USART handle + * @retval HAL status + * @note The USART errors are not managed to avoid the overrun error. + */ +static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart) +{ + uint16_t* tmp=0; + + if (husart->State == HAL_USART_STATE_BUSY_TX) + { + + if(husart->TxXferCount == 0) + { + /* Disable the USART Transmit Complete Interrupt */ + __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); + + /* Enable the USART Transmit Complete Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TC); + + return HAL_OK; + } + else + { + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + tmp = (uint16_t*) husart->pTxBuffPtr; + husart->Instance->TDR = (*tmp & (uint16_t)0x01FF); + husart->pTxBuffPtr += 2; + } + else + { + husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFF); + } + + husart->TxXferCount--; + + return HAL_OK; + } + } + else + { + return HAL_BUSY; + } +} + + +/** + * @brief Wraps up transmission in non blocking mode. + * @param husart: pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @retval HAL status + */ +static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart) +{ + /* Disable the USART Transmit Complete Interrupt */ + __HAL_USART_DISABLE_IT(husart, USART_IT_TC); + + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); + + husart->State = HAL_USART_STATE_READY; + + HAL_USART_TxCpltCallback(husart); + + return HAL_OK; +} + + +/** + * @brief Simplex Receive an amount of data in non-blocking mode. + * Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Receive_IT() + * @param husart: USART handle + * @retval HAL status + */ +static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart) +{ + uint16_t* tmp=0; + uint16_t uhMask = husart->Mask; + + if(husart->State == HAL_USART_STATE_BUSY_RX) + { + + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + tmp = (uint16_t*) husart->pRxBuffPtr ; + *tmp = (uint16_t)(husart->Instance->RDR & uhMask); + husart->pRxBuffPtr += 2; + } + else + { + *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); + } + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x00FF); + + if(--husart->RxXferCount == 0) + { + __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE); + + /* Disable the USART Parity Error Interrupt */ + __HAL_USART_DISABLE_IT(husart, USART_IT_PE); + + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); + + husart->State = HAL_USART_STATE_READY; + + HAL_USART_RxCpltCallback(husart); + + return HAL_OK; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking). + * Function called under interruption only, once + * interruptions have been enabled by HAL_USART_TransmitReceive_IT() + * @param husart: USART handle + * @retval HAL status + */ +static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) +{ + uint16_t* tmp=0; + uint16_t uhMask = husart->Mask; + + if(husart->State == HAL_USART_STATE_BUSY_TX_RX) + { + + if(husart->TxXferCount != 0x00) + { + if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET) + { + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + tmp = (uint16_t*) husart->pTxBuffPtr; + husart->Instance->TDR = (uint16_t)(*tmp & uhMask); + husart->pTxBuffPtr += 2; + } + else + { + husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)uhMask); + } + husart->TxXferCount--; + + /* Check the latest data transmitted */ + if(husart->TxXferCount == 0) + { + __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); + } + } + } + + if(husart->RxXferCount != 0x00) + { + if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET) + { + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + tmp = (uint16_t*) husart->pRxBuffPtr ; + *tmp = (uint16_t)(husart->Instance->RDR & uhMask); + husart->pRxBuffPtr += 2; + } + else + { + *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); + } + husart->RxXferCount--; + } + } + + /* Check the latest data received */ + if(husart->RxXferCount == 0) + { + __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE); + + /* Disable the USART Parity Error Interrupt */ + __HAL_USART_DISABLE_IT(husart, USART_IT_PE); + + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); + + husart->State = HAL_USART_STATE_READY; + + HAL_USART_TxRxCpltCallback(husart); + + return HAL_OK; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @} + */ + +#endif /* HAL_USART_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_wwdg.c b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_wwdg.c new file mode 100644 --- /dev/null +++ b/libraries/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_wwdg.c @@ -0,0 +1,446 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_wwdg.c + * @author MCD Application Team + * @version V1.1.0 + * @date 03-Oct-2014 + * @brief WWDG HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Window Watchdog (WWDG) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State functions + * + @verbatim + ============================================================================== + ##### WWDG specific features ##### + ============================================================================== + [..] + Once enabled the WWDG generates a system reset on expiry of a programmed + time period, unless the program refreshes the Counter (T[6;0] downcounter) + before reaching 0x3F value (i.e. a reset is generated when the counter + value rolls over from 0x40 to 0x3F). + + (+) An MCU reset is also generated if the counter value is refreshed + before the counter has reached the refresh window value. This + implies that the counter must be refreshed in a limited window. + (+) Once enabled the WWDG cannot be disabled except by a system reset. + (+) WWDGRST flag in RCC_CSR register can be used to inform when a WWDG + reset occurs. + (+) The WWDG counter input clock is derived from the APB clock divided + by a programmable prescaler. + (+) WWDG clock (Hz) = PCLK / (4096 * Prescaler) + (+) WWDG timeout (mS) = 1000 * (T[5;0] + 1) / WWDG clock + where T[5;0] are the lowest 6 bits of Counter. + (+) WWDG Counter refresh is allowed between the following limits : + (++) min time (mS) = 1000 * (Counter-Window) / WWDG clock + (++) max time (mS) = 1000 * (Counter-0x40) / WWDG clock + + (+) Min-max timeout value @48 MHz(PCLK): ~85,3us / ~5,46 ms + + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + (+) Enable WWDG APB1 clock using __WWDG_CLK_ENABLE(). + (+) Set the WWDG prescaler, refresh window and counter value + using HAL_WWDG_Init() function. + (+) Start the WWDG using HAL_WWDG_Start() function. + When the WWDG is enabled the counter value should be configured to + a value greater than 0x40 to prevent generating an immediate reset. + (+) Optionally you can enable the Early Wakeup Interrupt (EWI) which is + generated when the counter reaches 0x40, and then start the WWDG using + HAL_WWDG_Start_IT(). At EWI HAL_WWDG_WakeupCallback is executed and user can + add his own code by customization of function pointer HAL_WWDG_WakeupCallback + Once enabled, EWI interrupt cannot be disabled except by a system reset. + (+) Then the application program must refresh the WWDG counter at regular + intervals during normal operation to prevent an MCU reset, using + HAL_WWDG_Refresh() function. This operation must occur only when + the counter is lower than the refresh window value already programmed. + + *** WWDG HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in WWDG HAL driver. + + (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral + (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status + (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags + (+) __HAL_WWDG_ENABLE_IT: Enables the WWDG early wakeup interrupt + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup WWDG WWDG HAL module driver + * @brief WWDG HAL module driver. + * @{ + */ + +#ifdef HAL_WWDG_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup WWDG_Exported_Functions WWDG Exported Functions + * @{ + */ + +/** @defgroup WWDG_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions. + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize the WWDG according to the specified parameters + in the WWDG_InitTypeDef and create the associated handle + (+) DeInitialize the WWDG peripheral + (+) Initialize the WWDG MSP + (+) DeInitialize the WWDG MSP + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the WWDG according to the specified + * parameters in the WWDG_InitTypeDef and creates the associated handle. + * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg) +{ + /* Check the WWDG handle allocation */ + if(hwwdg == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance)); + assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler)); + assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window)); + assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter)); + + if(hwwdg->State == HAL_WWDG_STATE_RESET) + { + /* Init the low level hardware */ + HAL_WWDG_MspInit(hwwdg); + } + + /* Change WWDG peripheral state */ + hwwdg->State = HAL_WWDG_STATE_BUSY; + + /* Set WWDG Prescaler and Window */ + MODIFY_REG(hwwdg->Instance->CFR, (WWDG_CFR_WDGTB | WWDG_CFR_W), (hwwdg->Init.Prescaler | hwwdg->Init.Window)); + + /* Set WWDG Counter */ + MODIFY_REG(hwwdg->Instance->CR, WWDG_CR_T, hwwdg->Init.Counter); + + /* Change WWDG peripheral state */ + hwwdg->State = HAL_WWDG_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief DeInitializes the WWDG peripheral. + * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg) +{ + /* Check the parameters */ + assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance)); + + /* Change WWDG peripheral state */ + hwwdg->State = HAL_WWDG_STATE_BUSY; + + /* DeInit the low level hardware */ + HAL_WWDG_MspDeInit(hwwdg); + + /* Reset WWDG Control register */ + hwwdg->Instance->CR = (uint32_t)0x0000007F; + + /* Reset WWDG Configuration register */ + hwwdg->Instance->CFR = (uint32_t)0x0000007F; + + /* Reset WWDG Status register */ + hwwdg->Instance->SR = 0; + + /* Change WWDG peripheral state */ + hwwdg->State = HAL_WWDG_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hwwdg); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the WWDG MSP. + * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. + * @retval None + */ +__weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_WWDG_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the WWDG MSP. + * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. + * @retval None + */ +__weak void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_WWDG_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the WWDG. + (+) Refresh the WWDG. + (+) Handle WWDG interrupt request. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the WWDG. + * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg) +{ + /* Process Locked */ + __HAL_LOCK(hwwdg); + + /* Change WWDG peripheral state */ + hwwdg->State = HAL_WWDG_STATE_BUSY; + + /* Enable the peripheral */ + __HAL_WWDG_ENABLE(hwwdg); + + /* Change WWDG peripheral state */ + hwwdg->State = HAL_WWDG_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hwwdg); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the WWDG with interrupt enabled. + * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg) +{ + /* Process Locked */ + __HAL_LOCK(hwwdg); + + /* Change WWDG peripheral state */ + hwwdg->State = HAL_WWDG_STATE_BUSY; + + /* Enable the Early Wakeup Interrupt */ + __HAL_WWDG_ENABLE_IT(WWDG_IT_EWI); + + /* Enable the peripheral */ + __HAL_WWDG_ENABLE(hwwdg); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Refreshes the WWDG. + * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. + * @param Counter: value of counter to put in WWDG counter + * @retval HAL status + */ +HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter) +{ + /* Process Locked */ + __HAL_LOCK(hwwdg); + + /* Change WWDG peripheral state */ + hwwdg->State = HAL_WWDG_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_WWDG_COUNTER(Counter)); + + /* Write to WWDG CR the WWDG Counter value to refresh with */ + MODIFY_REG(hwwdg->Instance->CR, (uint32_t)WWDG_CR_T, Counter); + + /* Change WWDG peripheral state */ + hwwdg->State = HAL_WWDG_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hwwdg); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Handles WWDG interrupt request. + * @note The Early Wakeup Interrupt (EWI) can be used if specific safety operations + * or data logging must be performed before the actual reset is generated. + * The EWI interrupt is enabled using __HAL_WWDG_ENABLE_IT() macro. + * When the downcounter reaches the value 0x40, and EWI interrupt is + * generated and the corresponding Interrupt Service Routine (ISR) can + * be used to trigger specific actions (such as communications or data + * logging), before resetting the device. + * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. + * @retval None + */ +void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg) +{ + /* WWDG Early Wakeup Interrupt occurred */ + if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET) + { + /* Early Wakeup callback */ + HAL_WWDG_WakeupCallback(hwwdg); + + /* Change WWDG peripheral state */ + hwwdg->State = HAL_WWDG_STATE_READY; + + /* Clear the WWDG Data Ready flag */ + __HAL_WWDG_CLEAR_IT(hwwdg, WWDG_FLAG_EWIF); + + /* Process Unlocked */ + __HAL_UNLOCK(hwwdg); +} + } + +/** + * @brief Early Wakeup WWDG callback. + * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. + * @retval None + */ +__weak void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_WWDG_WakeupCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup WWDG_Exported_Functions_Group3 Peripheral State functions + * @brief Peripheral State functions. + * +@verbatim + ============================================================================== + ##### Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the WWDG state. + * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. + * @retval HAL state + */ +HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg) +{ + return hwwdg->State; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_WWDG_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_adc.h b/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_adc.h deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_adc.h +++ /dev/null @@ -1,450 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_adc.h - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file contains all the functions prototypes for the ADC firmware - * library - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0XX_ADC_H -#define __STM32F0XX_ADC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup ADC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief ADC Init structure definition - */ - -typedef struct -{ - uint32_t ADC_Resolution; /*!< Selects the resolution of the conversion. - This parameter can be a value of @ref ADC_Resolution */ - - FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in - Continuous or Single mode. - This parameter can be set to ENABLE or DISABLE. */ - - uint32_t ADC_ExternalTrigConvEdge; /*!< Selects the external trigger Edge and enables the - trigger of a regular group. This parameter can be a value - of @ref ADC_external_trigger_edge_conversion */ - - uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog - to digital conversion of regular channels. This parameter - can be a value of @ref ADC_external_trigger_sources_for_channels_conversion */ - - uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right. - This parameter can be a value of @ref ADC_data_align */ - - uint32_t ADC_ScanDirection; /*!< Specifies in which direction the channels will be scanned - in the sequence. - This parameter can be a value of @ref ADC_Scan_Direction */ -}ADC_InitTypeDef; - - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup ADC_Exported_Constants - * @{ - */ -#define IS_ADC_ALL_PERIPH(PERIPH) ((PERIPH) == ADC1) - -/** @defgroup ADC_JitterOff - * @{ - */ -/* These defines are obsolete and maintained for legacy purpose only. They are replaced by the ADC_ClockMode */ -#define ADC_JitterOff_PCLKDiv2 ADC_CFGR2_JITOFFDIV2 -#define ADC_JitterOff_PCLKDiv4 ADC_CFGR2_JITOFFDIV4 - -#define IS_ADC_JITTEROFF(JITTEROFF) (((JITTEROFF) & 0x3FFFFFFF) == (uint32_t)RESET) - -/** - * @} - */ - -/** @defgroup ADC_ClockMode - * @{ - */ -#define ADC_ClockMode_AsynClk ((uint32_t)0x00000000) /*!< ADC Asynchronous clock mode */ -#define ADC_ClockMode_SynClkDiv2 ADC_CFGR2_CKMODE_0 /*!< Synchronous clock mode divided by 2 */ -#define ADC_ClockMode_SynClkDiv4 ADC_CFGR2_CKMODE_1 /*!< Synchronous clock mode divided by 4 */ -#define IS_ADC_CLOCKMODE(CLOCK) (((CLOCK) == ADC_ClockMode_AsynClk) ||\ - ((CLOCK) == ADC_ClockMode_SynClkDiv2) ||\ - ((CLOCK) == ADC_ClockMode_SynClkDiv4)) - -/** - * @} - */ - -/** @defgroup ADC_Resolution - * @{ - */ -#define ADC_Resolution_12b ((uint32_t)0x00000000) -#define ADC_Resolution_10b ADC_CFGR1_RES_0 -#define ADC_Resolution_8b ADC_CFGR1_RES_1 -#define ADC_Resolution_6b ADC_CFGR1_RES - -#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \ - ((RESOLUTION) == ADC_Resolution_10b) || \ - ((RESOLUTION) == ADC_Resolution_8b) || \ - ((RESOLUTION) == ADC_Resolution_6b)) - -/** - * @} - */ - -/** @defgroup ADC_external_trigger_edge_conversion - * @{ - */ -#define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000) -#define ADC_ExternalTrigConvEdge_Rising ADC_CFGR1_EXTEN_0 -#define ADC_ExternalTrigConvEdge_Falling ADC_CFGR1_EXTEN_1 -#define ADC_ExternalTrigConvEdge_RisingFalling ADC_CFGR1_EXTEN - -#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \ - ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \ - ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \ - ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling)) -/** - * @} - */ - -/** @defgroup ADC_external_trigger_sources_for_channels_conversion - * @{ - */ - -/* TIM1 */ -#define ADC_ExternalTrigConv_T1_TRGO ((uint32_t)0x00000000) -#define ADC_ExternalTrigConv_T1_CC4 ADC_CFGR1_EXTSEL_0 - -/* TIM2 */ -#define ADC_ExternalTrigConv_T2_TRGO ADC_CFGR1_EXTSEL_1 - -/* TIM3 */ -#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)(ADC_CFGR1_EXTSEL_0 | ADC_CFGR1_EXTSEL_1)) - -/* TIM15 */ -#define ADC_ExternalTrigConv_T15_TRGO ADC_CFGR1_EXTSEL_2 - -#define IS_ADC_EXTERNAL_TRIG_CONV(CONV) (((CONV) == ADC_ExternalTrigConv_T1_TRGO) || \ - ((CONV) == ADC_ExternalTrigConv_T1_CC4) || \ - ((CONV) == ADC_ExternalTrigConv_T2_TRGO) || \ - ((CONV) == ADC_ExternalTrigConv_T3_TRGO) || \ - ((CONV) == ADC_ExternalTrigConv_T15_TRGO)) -/** - * @} - */ - -/** @defgroup ADC_data_align - * @{ - */ - -#define ADC_DataAlign_Right ((uint32_t)0x00000000) -#define ADC_DataAlign_Left ADC_CFGR1_ALIGN - -#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ - ((ALIGN) == ADC_DataAlign_Left)) -/** - * @} - */ - -/** @defgroup ADC_Scan_Direction - * @{ - */ - -#define ADC_ScanDirection_Upward ((uint32_t)0x00000000) -#define ADC_ScanDirection_Backward ADC_CFGR1_SCANDIR - -#define IS_ADC_SCAN_DIRECTION(DIRECTION) (((DIRECTION) == ADC_ScanDirection_Upward) || \ - ((DIRECTION) == ADC_ScanDirection_Backward)) -/** - * @} - */ - -/** @defgroup ADC_DMA_Mode - * @{ - */ - -#define ADC_DMAMode_OneShot ((uint32_t)0x00000000) -#define ADC_DMAMode_Circular ADC_CFGR1_DMACFG - -#define IS_ADC_DMA_MODE(MODE) (((MODE) == ADC_DMAMode_OneShot) || \ - ((MODE) == ADC_DMAMode_Circular)) -/** - * @} - */ - -/** @defgroup ADC_analog_watchdog_selection - * @{ - */ - -#define ADC_AnalogWatchdog_Channel_0 ((uint32_t)0x00000000) -#define ADC_AnalogWatchdog_Channel_1 ((uint32_t)0x04000000) -#define ADC_AnalogWatchdog_Channel_2 ((uint32_t)0x08000000) -#define ADC_AnalogWatchdog_Channel_3 ((uint32_t)0x0C000000) -#define ADC_AnalogWatchdog_Channel_4 ((uint32_t)0x10000000) -#define ADC_AnalogWatchdog_Channel_5 ((uint32_t)0x14000000) -#define ADC_AnalogWatchdog_Channel_6 ((uint32_t)0x18000000) -#define ADC_AnalogWatchdog_Channel_7 ((uint32_t)0x1C000000) -#define ADC_AnalogWatchdog_Channel_8 ((uint32_t)0x20000000) -#define ADC_AnalogWatchdog_Channel_9 ((uint32_t)0x24000000) -#define ADC_AnalogWatchdog_Channel_10 ((uint32_t)0x28000000) /*!< Not available for STM32F031 devices */ -#define ADC_AnalogWatchdog_Channel_11 ((uint32_t)0x2C000000) /*!< Not available for STM32F031 devices */ -#define ADC_AnalogWatchdog_Channel_12 ((uint32_t)0x30000000) /*!< Not available for STM32F031 devices */ -#define ADC_AnalogWatchdog_Channel_13 ((uint32_t)0x34000000) /*!< Not available for STM32F031 devices */ -#define ADC_AnalogWatchdog_Channel_14 ((uint32_t)0x38000000) /*!< Not available for STM32F031 devices */ -#define ADC_AnalogWatchdog_Channel_15 ((uint32_t)0x3C000000) /*!< Not available for STM32F031 devices */ -#define ADC_AnalogWatchdog_Channel_16 ((uint32_t)0x40000000) -#define ADC_AnalogWatchdog_Channel_17 ((uint32_t)0x44000000) -#define ADC_AnalogWatchdog_Channel_18 ((uint32_t)0x48000000) - - -#define IS_ADC_ANALOG_WATCHDOG_CHANNEL(CHANNEL) (((CHANNEL) == ADC_AnalogWatchdog_Channel_0) || \ - ((CHANNEL) == ADC_AnalogWatchdog_Channel_1) || \ - ((CHANNEL) == ADC_AnalogWatchdog_Channel_2) || \ - ((CHANNEL) == ADC_AnalogWatchdog_Channel_3) || \ - ((CHANNEL) == ADC_AnalogWatchdog_Channel_4) || \ - ((CHANNEL) == ADC_AnalogWatchdog_Channel_5) || \ - ((CHANNEL) == ADC_AnalogWatchdog_Channel_6) || \ - ((CHANNEL) == ADC_AnalogWatchdog_Channel_7) || \ - ((CHANNEL) == ADC_AnalogWatchdog_Channel_8) || \ - ((CHANNEL) == ADC_AnalogWatchdog_Channel_9) || \ - ((CHANNEL) == ADC_AnalogWatchdog_Channel_10) || \ - ((CHANNEL) == ADC_AnalogWatchdog_Channel_11) || \ - ((CHANNEL) == ADC_AnalogWatchdog_Channel_12) || \ - ((CHANNEL) == ADC_AnalogWatchdog_Channel_13) || \ - ((CHANNEL) == ADC_AnalogWatchdog_Channel_14) || \ - ((CHANNEL) == ADC_AnalogWatchdog_Channel_15) || \ - ((CHANNEL) == ADC_AnalogWatchdog_Channel_16) || \ - ((CHANNEL) == ADC_AnalogWatchdog_Channel_17) || \ - ((CHANNEL) == ADC_AnalogWatchdog_Channel_18)) -/** - * @} - */ - -/** @defgroup ADC_sampling_times - * @{ - */ - -#define ADC_SampleTime_1_5Cycles ((uint32_t)0x00000000) -#define ADC_SampleTime_7_5Cycles ((uint32_t)0x00000001) -#define ADC_SampleTime_13_5Cycles ((uint32_t)0x00000002) -#define ADC_SampleTime_28_5Cycles ((uint32_t)0x00000003) -#define ADC_SampleTime_41_5Cycles ((uint32_t)0x00000004) -#define ADC_SampleTime_55_5Cycles ((uint32_t)0x00000005) -#define ADC_SampleTime_71_5Cycles ((uint32_t)0x00000006) -#define ADC_SampleTime_239_5Cycles ((uint32_t)0x00000007) - -#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1_5Cycles) || \ - ((TIME) == ADC_SampleTime_7_5Cycles) || \ - ((TIME) == ADC_SampleTime_13_5Cycles) || \ - ((TIME) == ADC_SampleTime_28_5Cycles) || \ - ((TIME) == ADC_SampleTime_41_5Cycles) || \ - ((TIME) == ADC_SampleTime_55_5Cycles) || \ - ((TIME) == ADC_SampleTime_71_5Cycles) || \ - ((TIME) == ADC_SampleTime_239_5Cycles)) -/** - * @} - */ - -/** @defgroup ADC_thresholds - * @{ - */ - -#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) - -/** - * @} - */ - -/** @defgroup ADC_channels - * @{ - */ - -#define ADC_Channel_0 ADC_CHSELR_CHSEL0 -#define ADC_Channel_1 ADC_CHSELR_CHSEL1 -#define ADC_Channel_2 ADC_CHSELR_CHSEL2 -#define ADC_Channel_3 ADC_CHSELR_CHSEL3 -#define ADC_Channel_4 ADC_CHSELR_CHSEL4 -#define ADC_Channel_5 ADC_CHSELR_CHSEL5 -#define ADC_Channel_6 ADC_CHSELR_CHSEL6 -#define ADC_Channel_7 ADC_CHSELR_CHSEL7 -#define ADC_Channel_8 ADC_CHSELR_CHSEL8 -#define ADC_Channel_9 ADC_CHSELR_CHSEL9 -#define ADC_Channel_10 ADC_CHSELR_CHSEL10 /*!< Not available for STM32F031 devices */ -#define ADC_Channel_11 ADC_CHSELR_CHSEL11 /*!< Not available for STM32F031 devices */ -#define ADC_Channel_12 ADC_CHSELR_CHSEL12 /*!< Not available for STM32F031 devices */ -#define ADC_Channel_13 ADC_CHSELR_CHSEL13 /*!< Not available for STM32F031 devices */ -#define ADC_Channel_14 ADC_CHSELR_CHSEL14 /*!< Not available for STM32F031 devices */ -#define ADC_Channel_15 ADC_CHSELR_CHSEL15 /*!< Not available for STM32F031 devices */ -#define ADC_Channel_16 ADC_CHSELR_CHSEL16 -#define ADC_Channel_17 ADC_CHSELR_CHSEL17 -#define ADC_Channel_18 ADC_CHSELR_CHSEL18 /*!< Not available for STM32F030 devices */ - -#define ADC_Channel_TempSensor ((uint32_t)ADC_Channel_16) -#define ADC_Channel_Vrefint ((uint32_t)ADC_Channel_17) -#define ADC_Channel_Vbat ((uint32_t)ADC_Channel_18) /*!< Not available for STM32F030 devices */ - -#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) != (uint32_t)RESET) && (((CHANNEL) & 0xFFF80000) == (uint32_t)RESET)) - -/** - * @} - */ - -/** @defgroup ADC_interrupts_definition - * @{ - */ - -#define ADC_IT_ADRDY ADC_IER_ADRDYIE -#define ADC_IT_EOSMP ADC_IER_EOSMPIE -#define ADC_IT_EOC ADC_IER_EOCIE -#define ADC_IT_EOSEQ ADC_IER_EOSEQIE -#define ADC_IT_OVR ADC_IER_OVRIE -#define ADC_IT_AWD ADC_IER_AWDIE - -#define IS_ADC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFFFF60) == (uint32_t)RESET)) - -#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_ADRDY) || ((IT) == ADC_IT_EOSMP) || \ - ((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_EOSEQ) || \ - ((IT) == ADC_IT_OVR) || ((IT) == ADC_IT_AWD)) - -#define IS_ADC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFFFF60) == (uint32_t)RESET)) - -/** - * @} - */ - -/** @defgroup ADC_flags_definition - * @{ - */ - -#define ADC_FLAG_ADRDY ADC_ISR_ADRDY -#define ADC_FLAG_EOSMP ADC_ISR_EOSMP -#define ADC_FLAG_EOC ADC_ISR_EOC -#define ADC_FLAG_EOSEQ ADC_ISR_EOSEQ -#define ADC_FLAG_OVR ADC_ISR_OVR -#define ADC_FLAG_AWD ADC_ISR_AWD - -#define ADC_FLAG_ADEN ((uint32_t)0x01000001) -#define ADC_FLAG_ADDIS ((uint32_t)0x01000002) -#define ADC_FLAG_ADSTART ((uint32_t)0x01000004) -#define ADC_FLAG_ADSTP ((uint32_t)0x01000010) -#define ADC_FLAG_ADCAL ((uint32_t)0x81000000) - -#define IS_ADC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFFFF60) == (uint32_t)RESET)) - -#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_ADRDY) || ((FLAG) == ADC_FLAG_EOSMP) || \ - ((FLAG) == ADC_FLAG_EOC) || ((FLAG) == ADC_FLAG_EOSEQ) || \ - ((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_OVR) || \ - ((FLAG) == ADC_FLAG_ADEN) || ((FLAG) == ADC_FLAG_ADDIS) || \ - ((FLAG) == ADC_FLAG_ADSTART) || ((FLAG) == ADC_FLAG_ADSTP) || \ - ((FLAG) == ADC_FLAG_ADCAL)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Function used to set the ADC configuration to the default reset state *****/ -void ADC_DeInit(ADC_TypeDef* ADCx); - -/* Initialization and Configuration functions *********************************/ -void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); -void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); -void ADC_ClockModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ClockMode); -void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); -/* This Function is obsolete and maintained for legacy purpose only. - ADC_ClockModeConfig() function should be used instead */ -void ADC_JitterCmd(ADC_TypeDef* ADCx, uint32_t ADC_JitterOff, FunctionalState NewState); - -/* Power saving functions *****************************************************/ -void ADC_AutoPowerOffCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_WaitModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); - -/* Analog Watchdog configuration functions ************************************/ -void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold); -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog_Channel); -void ADC_AnalogWatchdogSingleChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState); - -/* Temperature Sensor , Vrefint and Vbat management function ******************/ -void ADC_TempSensorCmd(FunctionalState NewState); -void ADC_VrefintCmd(FunctionalState NewState); -void ADC_VbatCmd(FunctionalState NewState); /*!< Not applicable for STM32F030 devices */ - -/* Channels Configuration functions *******************************************/ -void ADC_ChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_Channel, uint32_t ADC_SampleTime); -void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_OverrunModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -uint32_t ADC_GetCalibrationFactor(ADC_TypeDef* ADCx); -void ADC_StopOfConversion(ADC_TypeDef* ADCx); -void ADC_StartOfConversion(ADC_TypeDef* ADCx); -uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); - -/* Regular Channels DMA Configuration functions *******************************/ -void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_DMARequestModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_DMARequestMode); - -/* Interrupts and flags management functions **********************************/ -void ADC_ITConfig(ADC_TypeDef* ADCx, uint32_t ADC_IT, FunctionalState NewState); -FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG); -void ADC_ClearFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG); -ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint32_t ADC_IT); -void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F0XX_ADC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_can.h b/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_can.h deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_can.h +++ /dev/null @@ -1,643 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_can.h - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file contains all the functions prototypes for the CAN firmware - * library, applicable only for STM32F072 devices. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_CAN_H -#define __STM32F0xx_CAN_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup CAN - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN)) - -/** - * @brief CAN init structure definition - */ -typedef struct -{ - uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum. - It ranges from 1 to 1024. */ - - uint8_t CAN_Mode; /*!< Specifies the CAN operating mode. - This parameter can be a value of @ref CAN_operating_mode */ - - uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta - the CAN hardware is allowed to lengthen or - shorten a bit to perform resynchronization. - This parameter can be a value of @ref CAN_synchronisation_jump_width */ - - uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit - Segment 1. This parameter can be a value of - @ref CAN_time_quantum_in_bit_segment_1 */ - - uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2. - This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ - - FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_NART; /*!< Enable or disable the non-automatic retransmission mode. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority. - This parameter can be set either to ENABLE or DISABLE. */ -} CAN_InitTypeDef; - -/** - * @brief CAN filter init structure definition - */ -typedef struct -{ - uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit - configuration, first one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit - configuration, second one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, - according to the mode (MSBs for a 32-bit configuration, - first one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, - according to the mode (LSBs for a 32-bit configuration, - second one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. - This parameter can be a value of @ref CAN_filter_FIFO */ - - uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */ - - uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized. - This parameter can be a value of @ref CAN_filter_mode */ - - uint8_t CAN_FilterScale; /*!< Specifies the filter scale. - This parameter can be a value of @ref CAN_filter_scale */ - - FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter. - This parameter can be set either to ENABLE or DISABLE. */ -} CAN_FilterInitTypeDef; - -/** - * @brief CAN Tx message structure definition - */ -typedef struct -{ - uint32_t StdId; /*!< Specifies the standard identifier. - This parameter can be a value between 0 to 0x7FF. */ - - uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter can be a value between 0 to 0x1FFFFFFF. */ - - uint8_t IDE; /*!< Specifies the type of identifier for the message that - will be transmitted. This parameter can be a value - of @ref CAN_identifier_type */ - - uint8_t RTR; /*!< Specifies the type of frame for the message that will - be transmitted. This parameter can be a value of - @ref CAN_remote_transmission_request */ - - uint8_t DLC; /*!< Specifies the length of the frame that will be - transmitted. This parameter can be a value between - 0 to 8 */ - - uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 - to 0xFF. */ -} CanTxMsg; - -/** - * @brief CAN Rx message structure definition - */ -typedef struct -{ - uint32_t StdId; /*!< Specifies the standard identifier. - This parameter can be a value between 0 to 0x7FF. */ - - uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter can be a value between 0 to 0x1FFFFFFF. */ - - uint8_t IDE; /*!< Specifies the type of identifier for the message that - will be received. This parameter can be a value of - @ref CAN_identifier_type */ - - uint8_t RTR; /*!< Specifies the type of frame for the received message. - This parameter can be a value of - @ref CAN_remote_transmission_request */ - - uint8_t DLC; /*!< Specifies the length of the frame that will be received. - This parameter can be a value between 0 to 8 */ - - uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to - 0xFF. */ - - uint8_t FMI; /*!< Specifies the index of the filter the message stored in - the mailbox passes through. This parameter can be a - value between 0 to 0xFF */ -} CanRxMsg; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup CAN_Exported_Constants - * @{ - */ - -/** @defgroup CAN_InitStatus - * @{ - */ - -#define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */ -#define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */ - - -/* Legacy defines */ -#define CANINITFAILED CAN_InitStatus_Failed -#define CANINITOK CAN_InitStatus_Success -/** - * @} - */ - -/** @defgroup CAN_operating_mode - * @{ - */ - -#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */ -#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */ -#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */ -#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */ - -#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \ - ((MODE) == CAN_Mode_LoopBack)|| \ - ((MODE) == CAN_Mode_Silent) || \ - ((MODE) == CAN_Mode_Silent_LoopBack)) -/** - * @} - */ - - - /** - * @defgroup CAN_operating_mode - * @{ - */ -#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */ -#define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */ -#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */ - - -#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\ - ((MODE) == CAN_OperatingMode_Normal)|| \ - ((MODE) == CAN_OperatingMode_Sleep)) -/** - * @} - */ - -/** - * @defgroup CAN_operating_mode_status - * @{ - */ - -#define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */ -#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */ -/** - * @} - */ - -/** @defgroup CAN_synchronisation_jump_width - * @{ - */ -#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */ -#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */ -#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */ -#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */ - -#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \ - ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq)) -/** - * @} - */ - -/** @defgroup CAN_time_quantum_in_bit_segment_1 - * @{ - */ -#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */ -#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */ -#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */ -#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */ -#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */ -#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */ -#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */ -#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */ -#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */ -#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */ -#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */ -#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */ -#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */ -#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */ -#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */ -#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */ - -#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq) -/** - * @} - */ - -/** @defgroup CAN_time_quantum_in_bit_segment_2 - * @{ - */ -#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */ -#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */ -#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */ -#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */ -#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */ -#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */ -#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */ -#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */ - -#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq) -/** - * @} - */ - -/** @defgroup CAN_clock_prescaler - * @{ - */ -#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) -/** - * @} - */ - -/** @defgroup CAN_filter_number - * @{ - */ -#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) -/** - * @} - */ - -/** @defgroup CAN_filter_mode - * @{ - */ -#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */ -#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */ - -#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \ - ((MODE) == CAN_FilterMode_IdList)) -/** - * @} - */ - -/** @defgroup CAN_filter_scale - * @{ - */ -#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */ -#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */ - -#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \ - ((SCALE) == CAN_FilterScale_32bit)) -/** - * @} - */ - -/** @defgroup CAN_filter_FIFO - * @{ - */ -#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ -#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ -#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \ - ((FIFO) == CAN_FilterFIFO1)) - -/* Legacy defines */ -#define CAN_FilterFIFO0 CAN_Filter_FIFO0 -#define CAN_FilterFIFO1 CAN_Filter_FIFO1 -/** - * @} - */ - -/** @defgroup CAN_Start_bank_filter_for_slave_CAN - * @{ - */ -#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27)) -/** - * @} - */ - -/** @defgroup CAN_Tx - * @{ - */ -#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) -#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) -#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) -#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) -/** - * @} - */ - -/** @defgroup CAN_identifier_type - * @{ - */ -#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */ -#define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */ -#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \ - ((IDTYPE) == CAN_Id_Extended)) - -/* Legacy defines */ -#define CAN_ID_STD CAN_Id_Standard -#define CAN_ID_EXT CAN_Id_Extended -/** - * @} - */ - -/** @defgroup CAN_remote_transmission_request - * @{ - */ -#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */ -#define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */ -#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote)) - -/* Legacy defines */ -#define CAN_RTR_DATA CAN_RTR_Data -#define CAN_RTR_REMOTE CAN_RTR_Remote -/** - * @} - */ - -/** @defgroup CAN_transmit_constants - * @{ - */ -#define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */ -#define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */ -#define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */ -#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide - an empty mailbox */ -/* Legacy defines */ -#define CANTXFAILED CAN_TxStatus_Failed -#define CANTXOK CAN_TxStatus_Ok -#define CANTXPENDING CAN_TxStatus_Pending -#define CAN_NO_MB CAN_TxStatus_NoMailBox -/** - * @} - */ - -/** @defgroup CAN_receive_FIFO_number_constants - * @{ - */ -#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ -#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ - -#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) -/** - * @} - */ - -/** @defgroup CAN_sleep_constants - * @{ - */ -#define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */ -#define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */ - -/* Legacy defines */ -#define CANSLEEPFAILED CAN_Sleep_Failed -#define CANSLEEPOK CAN_Sleep_Ok -/** - * @} - */ - -/** @defgroup CAN_wake_up_constants - * @{ - */ -#define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */ -#define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */ - -/* Legacy defines */ -#define CANWAKEUPFAILED CAN_WakeUp_Failed -#define CANWAKEUPOK CAN_WakeUp_Ok -/** - * @} - */ - -/** - * @defgroup CAN_Error_Code_constants - * @{ - */ -#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */ -#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */ -#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */ -#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */ -#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */ -#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */ -#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */ -#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */ -/** - * @} - */ - -/** @defgroup CAN_flags - * @{ - */ -/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() - and CAN_ClearFlag() functions. */ -/* If the flag is 0x1XXXXXXX, it means that it can only be used with - CAN_GetFlagStatus() function. */ - -/* Transmit Flags */ -#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */ -#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */ -#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */ - -/* Receive Flags */ -#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */ -#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */ -#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */ -#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */ -#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */ -#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */ - -/* Operating Mode Flags */ -#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */ -#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */ -/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. - In this case the SLAK bit can be polled.*/ - -/* Error Flags */ -#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */ -#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */ -#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */ -#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */ - -#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \ - ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \ - ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \ - ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \ - ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \ - ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \ - ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \ - ((FLAG) == CAN_FLAG_SLAK )) - -#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \ - ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \ - ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\ - ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \ - ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK)) -/** - * @} - */ - - -/** @defgroup CAN_interrupts - * @{ - */ -#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/ - -/* Receive Interrupts */ -#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/ -#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/ -#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/ -#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/ -#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/ -#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/ - -/* Operating Mode Interrupts */ -#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/ -#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/ - -/* Error Interrupts */ -#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/ -#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/ -#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/ -#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/ -#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/ - -/* Flags named as Interrupts : kept only for FW compatibility */ -#define CAN_IT_RQCP0 CAN_IT_TME -#define CAN_IT_RQCP1 CAN_IT_TME -#define CAN_IT_RQCP2 CAN_IT_TME - - -#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\ - ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\ - ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\ - ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ - ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ - ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ - ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) - -#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\ - ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\ - ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\ - ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ - ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ - ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the CAN configuration to the default reset state *****/ -void CAN_DeInit(CAN_TypeDef* CANx); - -/* Initialization and Configuration functions *********************************/ -uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct); -void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct); -void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct); -void CAN_SlaveStartBank(uint8_t CAN_BankNumber); -void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState); -void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState); - -/* CAN Frames Transmission functions ******************************************/ -uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage); -uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox); -void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox); - -/* CAN Frames Reception functions *********************************************/ -void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage); -void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber); -uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber); - -/* Operation modes functions **************************************************/ -uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode); -uint8_t CAN_Sleep(CAN_TypeDef* CANx); -uint8_t CAN_WakeUp(CAN_TypeDef* CANx); - -/* CAN Bus Error management functions *****************************************/ -uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx); -uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx); -uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx); - -/* Interrupts and flags management functions **********************************/ -void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState); -FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG); -void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG); -ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT); -void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_CAN_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_cec.h b/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_cec.h deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_cec.h +++ /dev/null @@ -1,300 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_cec.h - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file contains all the functions prototypes for the CEC firmware - * library, applicable only for STM32F051, STM32F042 and STM32F072 devices. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0XX_CEC_H -#define __STM32F0XX_CEC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup CEC - * @{ - */ -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief CEC Init structure definition - */ -typedef struct -{ - uint32_t CEC_SignalFreeTime; /*!< Specifies the CEC Signal Free Time configuration. - This parameter can be a value of @ref CEC_Signal_Free_Time */ - uint32_t CEC_RxTolerance; /*!< Specifies the CEC Reception Tolerance. - This parameter can be a value of @ref CEC_RxTolerance */ - uint32_t CEC_StopReception; /*!< Specifies the CEC Stop Reception. - This parameter can be a value of @ref CEC_Stop_Reception */ - uint32_t CEC_BitRisingError; /*!< Specifies the CEC Bit Rising Error generation. - This parameter can be a value of @ref CEC_Bit_Rising_Error_Generation */ - uint32_t CEC_LongBitPeriodError; /*!< Specifies the CEC Long Bit Error generation. - This parameter can be a value of @ref CEC_Long_Bit_Error_Generation */ - uint32_t CEC_BRDNoGen; /*!< Specifies the CEC Broadcast Error generation. - This parameter can be a value of @ref CEC_BDR_No_Gen */ - uint32_t CEC_SFTOption; /*!< Specifies the CEC Signal Free Time option. - This parameter can be a value of @ref CEC_SFT_Option */ - -}CEC_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup CEC_Exported_Constants - * @{ - */ - -/** @defgroup CEC_Signal_Free_Time - * @{ - */ -#define CEC_SignalFreeTime_Standard ((uint32_t)0x00000000) /*!< CEC Signal Free Time Standard */ -#define CEC_SignalFreeTime_1T ((uint32_t)0x00000001) /*!< CEC 1.5 nominal data bit periods */ -#define CEC_SignalFreeTime_2T ((uint32_t)0x00000002) /*!< CEC 2.5 nominal data bit periods */ -#define CEC_SignalFreeTime_3T ((uint32_t)0x00000003) /*!< CEC 3.5 nominal data bit periods */ -#define CEC_SignalFreeTime_4T ((uint32_t)0x00000004) /*!< CEC 4.5 nominal data bit periods */ -#define CEC_SignalFreeTime_5T ((uint32_t)0x00000005) /*!< CEC 5.5 nominal data bit periods */ -#define CEC_SignalFreeTime_6T ((uint32_t)0x00000006) /*!< CEC 6.5 nominal data bit periods */ -#define CEC_SignalFreeTime_7T ((uint32_t)0x00000007) /*!< CEC 7.5 nominal data bit periods */ - -#define IS_CEC_SIGNAL_FREE_TIME(TIME) (((TIME) == CEC_SignalFreeTime_Standard) || \ - ((TIME) == CEC_SignalFreeTime_1T)|| \ - ((TIME) == CEC_SignalFreeTime_2T)|| \ - ((TIME) == CEC_SignalFreeTime_3T)|| \ - ((TIME) == CEC_SignalFreeTime_4T)|| \ - ((TIME) == CEC_SignalFreeTime_5T)|| \ - ((TIME) == CEC_SignalFreeTime_6T)|| \ - ((TIME) == CEC_SignalFreeTime_7T)) -/** - * @} - */ - -/** @defgroup CEC_RxTolerance - * @{ - */ -#define CEC_RxTolerance_Standard ((uint32_t)0x00000000) /*!< Standard Tolerance Margin */ -#define CEC_RxTolerance_Extended CEC_CFGR_RXTOL /*!< Extended Tolerance Margin */ - -#define IS_CEC_RX_TOLERANCE(TOLERANCE) (((TOLERANCE) == CEC_RxTolerance_Standard) || \ - ((TOLERANCE) == CEC_RxTolerance_Extended)) -/** - * @} - */ - -/** @defgroup CEC_Stop_Reception - * @{ - */ -#define CEC_StopReception_Off ((uint32_t)0x00000000) /*!< No RX Stop on bit Rising Error (BRE) */ -#define CEC_StopReception_On CEC_CFGR_BRESTP /*!< RX Stop on bit Rising Error (BRE) */ - -#define IS_CEC_STOP_RECEPTION(RECEPTION) (((RECEPTION) == CEC_StopReception_On) || \ - ((RECEPTION) == CEC_StopReception_Off)) -/** - * @} - */ - -/** @defgroup CEC_Bit_Rising_Error_Generation - * @{ - */ -#define CEC_BitRisingError_Off ((uint32_t)0x00000000) /*!< Bit Rising Error generation turned Off */ -#define CEC_BitRisingError_On CEC_CFGR_BREGEN /*!< Bit Rising Error generation turned On */ - -#define IS_CEC_BIT_RISING_ERROR(ERROR) (((ERROR) == CEC_BitRisingError_Off) || \ - ((ERROR) == CEC_BitRisingError_On)) -/** - * @} - */ - -/** @defgroup CEC_Long_Bit_Error_Generation - * @{ - */ -#define CEC_LongBitPeriodError_Off ((uint32_t)0x00000000) /*!< Long Bit Period Error generation turned Off */ -#define CEC_LongBitPeriodError_On CEC_CFGR_LREGEN /*!< Long Bit Period Error generation turned On */ - -#define IS_CEC_LONG_BIT_PERIOD_ERROR(ERROR) (((ERROR) == CEC_LongBitPeriodError_Off) || \ - ((ERROR) == CEC_LongBitPeriodError_On)) -/** - * @} - */ - -/** @defgroup CEC_BDR_No_Gen - * @{ - */ - -#define CEC_BRDNoGen_Off ((uint32_t)0x00000000) /*!< Broadcast Bit Rising Error generation turned Off */ -#define CEC_BRDNoGen_On CEC_CFGR_BRDNOGEN /*!< Broadcast Bit Rising Error generation turned On */ - -#define IS_CEC_BDR_NO_GEN_ERROR(ERROR) (((ERROR) == CEC_BRDNoGen_Off) || \ - ((ERROR) == CEC_BRDNoGen_On)) -/** - * @} - */ - -/** @defgroup CEC_SFT_Option - * @{ - */ -#define CEC_SFTOption_Off ((uint32_t)0x00000000) /*!< SFT option turned Off */ -#define CEC_SFTOption_On CEC_CFGR_SFTOPT /*!< SFT option turned On */ - -#define IS_CEC_SFT_OPTION(OPTION) (((OPTION) == CEC_SFTOption_Off) || \ - ((OPTION) == CEC_SFTOption_On)) -/** - * @} - */ - -/** @defgroup CEC_Own_Address - * @{ - */ -#define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10) - -/** - * @} - */ - -/** @defgroup CEC_Interrupt_Configuration_definition - * @{ - */ -#define CEC_IT_TXACKE CEC_IER_TXACKEIE -#define CEC_IT_TXERR CEC_IER_TXERRIE -#define CEC_IT_TXUDR CEC_IER_TXUDRIE -#define CEC_IT_TXEND CEC_IER_TXENDIE -#define CEC_IT_TXBR CEC_IER_TXBRIE -#define CEC_IT_ARBLST CEC_IER_ARBLSTIE -#define CEC_IT_RXACKE CEC_IER_RXACKEIE -#define CEC_IT_LBPE CEC_IER_LBPEIE -#define CEC_IT_SBPE CEC_IER_SBPEIE -#define CEC_IT_BRE CEC_IER_BREIEIE -#define CEC_IT_RXOVR CEC_IER_RXOVRIE -#define CEC_IT_RXEND CEC_IER_RXENDIE -#define CEC_IT_RXBR CEC_IER_RXBRIE - -#define IS_CEC_IT(IT) ((((IT) & (uint32_t)0xFFFFE000) == 0x00) && ((IT) != 0x00)) - -#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TXACKE) || \ - ((IT) == CEC_IT_TXERR)|| \ - ((IT) == CEC_IT_TXUDR)|| \ - ((IT) == CEC_IT_TXEND)|| \ - ((IT) == CEC_IT_TXBR)|| \ - ((IT) == CEC_IT_ARBLST)|| \ - ((IT) == CEC_IT_RXACKE)|| \ - ((IT) == CEC_IT_LBPE)|| \ - ((IT) == CEC_IT_SBPE)|| \ - ((IT) == CEC_IT_BRE)|| \ - ((IT) == CEC_IT_RXOVR)|| \ - ((IT) == CEC_IT_RXEND)|| \ - ((IT) == CEC_IT_RXBR)) -/** - * @} - */ - -/** @defgroup CEC_ISR_register_flags_definition - * @{ - */ -#define CEC_FLAG_TXACKE CEC_ISR_TXACKE -#define CEC_FLAG_TXERR CEC_ISR_TXERR -#define CEC_FLAG_TXUDR CEC_ISR_TXUDR -#define CEC_FLAG_TXEND CEC_ISR_TXEND -#define CEC_FLAG_TXBR CEC_ISR_TXBR -#define CEC_FLAG_ARBLST CEC_ISR_ARBLST -#define CEC_FLAG_RXACKE CEC_ISR_RXACKE -#define CEC_FLAG_LBPE CEC_ISR_LBPE -#define CEC_FLAG_SBPE CEC_ISR_SBPE -#define CEC_FLAG_BRE CEC_ISR_BRE -#define CEC_FLAG_RXOVR CEC_ISR_RXOVR -#define CEC_FLAG_RXEND CEC_ISR_RXEND -#define CEC_FLAG_RXBR CEC_ISR_RXBR - -#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFE000) == 0x00) && ((FLAG) != 0x00)) - -#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_TXACKE) || \ - ((FLAG) == CEC_FLAG_TXERR)|| \ - ((FLAG) == CEC_FLAG_TXUDR)|| \ - ((FLAG) == CEC_FLAG_TXEND)|| \ - ((FLAG) == CEC_FLAG_TXBR)|| \ - ((FLAG) == CEC_FLAG_ARBLST)|| \ - ((FLAG) == CEC_FLAG_RXACKE)|| \ - ((FLAG) == CEC_FLAG_LBPE)|| \ - ((FLAG) == CEC_FLAG_SBPE)|| \ - ((FLAG) == CEC_FLAG_BRE)|| \ - ((FLAG) == CEC_FLAG_RXOVR)|| \ - ((FLAG) == CEC_FLAG_RXEND)|| \ - ((FLAG) == CEC_FLAG_RXBR)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Function used to set the CEC configuration to the default reset state *****/ -void CEC_DeInit(void); - -/* CEC_Initialization and Configuration functions *****************************/ -void CEC_Init(CEC_InitTypeDef* CEC_InitStruct); -void CEC_StructInit(CEC_InitTypeDef* CEC_InitStruct); -void CEC_Cmd(FunctionalState NewState); -void CEC_ListenModeCmd(FunctionalState NewState); -void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress); -void CEC_OwnAddressClear(void); - -/* CEC_Data transfers functions ***********************************************/ -void CEC_SendData(uint8_t Data); -uint8_t CEC_ReceiveData(void); -void CEC_StartOfMessage(void); -void CEC_EndOfMessage(void); - -/* CEC_Interrupts and flags management functions ******************************/ -void CEC_ITConfig(uint16_t CEC_IT, FunctionalState NewState); -FlagStatus CEC_GetFlagStatus(uint16_t CEC_FLAG); -void CEC_ClearFlag(uint32_t CEC_FLAG); -ITStatus CEC_GetITStatus(uint16_t CEC_IT); -void CEC_ClearITPendingBit(uint16_t CEC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0XX_CEC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_comp.h b/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_comp.h deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_comp.h +++ /dev/null @@ -1,245 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_comp.h - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file contains all the functions prototypes for the COMP firmware - * library, applicable only for STM32F051 and STM32F072 devices. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0XX_COMP_H -#define __STM32F0XX_COMP_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup COMP - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief COMP Init structure definition - */ - -typedef struct -{ - - uint32_t COMP_InvertingInput; /*!< Selects the inverting input of the comparator. - This parameter can be a value of @ref COMP_InvertingInput */ - - uint32_t COMP_Output; /*!< Selects the output redirection of the comparator. - This parameter can be a value of @ref COMP_Output */ - - uint32_t COMP_OutputPol; /*!< Selects the output polarity of the comparator. - This parameter can be a value of @ref COMP_OutputPolarity */ - - uint32_t COMP_Hysteresis; /*!< Selects the hysteresis voltage of the comparator. - This parameter can be a value of @ref COMP_Hysteresis */ - - uint32_t COMP_Mode; /*!< Selects the operating mode of the comparator - and allows to adjust the speed/consumption. - This parameter can be a value of @ref COMP_Mode */ - -}COMP_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup COMP_Exported_Constants - * @{ - */ - -/** @defgroup COMP_Selection - * @{ - */ - -#define COMP_Selection_COMP1 ((uint32_t)0x00000000) /*!< COMP1 Selection */ -#define COMP_Selection_COMP2 ((uint32_t)0x00000010) /*!< COMP2 Selection */ - -#define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == COMP_Selection_COMP1) || \ - ((PERIPH) == COMP_Selection_COMP2)) - -/** - * @} - */ - -/** @defgroup COMP_InvertingInput - * @{ - */ - -#define COMP_InvertingInput_1_4VREFINT ((uint32_t)0x00000000) /*!< 1/4 VREFINT connected to comparator inverting input */ -#define COMP_InvertingInput_1_2VREFINT COMP_CSR_COMP1INSEL_0 /*!< 1/2 VREFINT connected to comparator inverting input */ -#define COMP_InvertingInput_3_4VREFINT COMP_CSR_COMP1INSEL_1 /*!< 3/4 VREFINT connected to comparator inverting input */ -#define COMP_InvertingInput_VREFINT ((uint32_t)0x00000030) /*!< VREFINT connected to comparator inverting input */ -#define COMP_InvertingInput_DAC1 COMP_CSR_COMP1INSEL_2 /*!< DAC1_OUT (PA4) connected to comparator inverting input */ -#define COMP_InvertingInput_DAC2 ((uint32_t)0x00000050) /*!< DAC2_OUT (PA5) connected to comparator inverting input, applicable only for STM32F072 devices */ -#define COMP_InvertingInput_IO ((uint32_t)0x00000060) /*!< I/O (PA0 for COMP1 and PA2 for COMP2) connected to comparator inverting input */ - -#define IS_COMP_INVERTING_INPUT(INPUT) (((INPUT) == COMP_InvertingInput_1_4VREFINT) || \ - ((INPUT) == COMP_InvertingInput_1_2VREFINT) || \ - ((INPUT) == COMP_InvertingInput_3_4VREFINT) || \ - ((INPUT) == COMP_InvertingInput_VREFINT) || \ - ((INPUT) == COMP_InvertingInput_DAC1) || \ - ((INPUT) == COMP_InvertingInput_DAC2) || \ - ((INPUT) == COMP_InvertingInput_1_4VREFINT) || \ - ((INPUT) == COMP_InvertingInput_IO)) -/** - * @} - */ - -/** @defgroup COMP_Output - * @{ - */ - -#define COMP_Output_None ((uint32_t)0x00000000) /*!< COMP output isn't connected to other peripherals */ -#define COMP_Output_TIM1BKIN COMP_CSR_COMP1OUTSEL_0 /*!< COMP output connected to TIM1 Break Input (BKIN) */ -#define COMP_Output_TIM1IC1 COMP_CSR_COMP1OUTSEL_1 /*!< COMP output connected to TIM1 Input Capture 1 */ -#define COMP_Output_TIM1OCREFCLR ((uint32_t)0x00000300) /*!< COMP output connected to TIM1 OCREF Clear */ -#define COMP_Output_TIM2IC4 COMP_CSR_COMP1OUTSEL_2 /*!< COMP output connected to TIM2 Input Capture 4 */ -#define COMP_Output_TIM2OCREFCLR ((uint32_t)0x00000500) /*!< COMP output connected to TIM2 OCREF Clear */ -#define COMP_Output_TIM3IC1 ((uint32_t)0x00000600) /*!< COMP output connected to TIM3 Input Capture 1 */ -#define COMP_Output_TIM3OCREFCLR COMP_CSR_COMP1OUTSEL /*!< COMP output connected to TIM3 OCREF Clear */ - - -#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_Output_None) || \ - ((OUTPUT) == COMP_Output_TIM1BKIN) || \ - ((OUTPUT) == COMP_Output_TIM1IC1) || \ - ((OUTPUT) == COMP_Output_TIM1OCREFCLR) || \ - ((OUTPUT) == COMP_Output_TIM2IC4) || \ - ((OUTPUT) == COMP_Output_TIM2OCREFCLR) || \ - ((OUTPUT) == COMP_Output_TIM3IC1) || \ - ((OUTPUT) == COMP_Output_TIM3OCREFCLR)) -/** - * @} - */ - -/** @defgroup COMP_OutputPolarity - * @{ - */ -#define COMP_OutputPol_NonInverted ((uint32_t)0x00000000) /*!< COMP output on GPIO isn't inverted */ -#define COMP_OutputPol_Inverted COMP_CSR_COMP1POL /*!< COMP output on GPIO is inverted */ - -#define IS_COMP_OUTPUT_POL(POL) (((POL) == COMP_OutputPol_NonInverted) || \ - ((POL) == COMP_OutputPol_Inverted)) - -/** - * @} - */ - -/** @defgroup COMP_Hysteresis - * @{ - */ -/* Please refer to the electrical characteristics in the device datasheet for - the hysteresis level */ -#define COMP_Hysteresis_No 0x00000000 /*!< No hysteresis */ -#define COMP_Hysteresis_Low COMP_CSR_COMP1HYST_0 /*!< Hysteresis level low */ -#define COMP_Hysteresis_Medium COMP_CSR_COMP1HYST_1 /*!< Hysteresis level medium */ -#define COMP_Hysteresis_High COMP_CSR_COMP1HYST /*!< Hysteresis level high */ - -#define IS_COMP_HYSTERESIS(HYSTERESIS) (((HYSTERESIS) == COMP_Hysteresis_No) || \ - ((HYSTERESIS) == COMP_Hysteresis_Low) || \ - ((HYSTERESIS) == COMP_Hysteresis_Medium) || \ - ((HYSTERESIS) == COMP_Hysteresis_High)) -/** - * @} - */ - -/** @defgroup COMP_Mode - * @{ - */ -/* Please refer to the electrical characteristics in the device datasheet for - the power consumption values */ -#define COMP_Mode_HighSpeed 0x00000000 /*!< High Speed */ -#define COMP_Mode_MediumSpeed COMP_CSR_COMP1MODE_0 /*!< Medium Speed */ -#define COMP_Mode_LowPower COMP_CSR_COMP1MODE_1 /*!< Low power mode */ -#define COMP_Mode_UltraLowPower COMP_CSR_COMP1MODE /*!< Ultra-low power mode */ - -#define IS_COMP_MODE(MODE) (((MODE) == COMP_Mode_UltraLowPower) || \ - ((MODE) == COMP_Mode_LowPower) || \ - ((MODE) == COMP_Mode_MediumSpeed) || \ - ((MODE) == COMP_Mode_HighSpeed)) -/** - * @} - */ - -/** @defgroup COMP_OutputLevel - * @{ - */ -/* When output polarity is not inverted, comparator output is high when - the non-inverting input is at a higher voltage than the inverting input */ -#define COMP_OutputLevel_High COMP_CSR_COMP1OUT -/* When output polarity is not inverted, comparator output is low when - the non-inverting input is at a lower voltage than the inverting input*/ -#define COMP_OutputLevel_Low ((uint32_t)0x00000000) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Function used to set the COMP configuration to the default reset state ****/ -void COMP_DeInit(void); - -/* Initialization and Configuration functions *********************************/ -void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct); -void COMP_StructInit(COMP_InitTypeDef* COMP_InitStruct); -void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState); -void COMP_SwitchCmd(FunctionalState NewState); -uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection); - -/* Window mode control function ***********************************************/ -void COMP_WindowCmd(FunctionalState NewState); - -/* COMP configuration locking function ****************************************/ -void COMP_LockConfig(uint32_t COMP_Selection); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F0XX_COMP_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_crc.h b/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_crc.h deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_crc.h +++ /dev/null @@ -1,122 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_crc.h - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file contains all the functions prototypes for the CRC firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0XX_CRC_H -#define __STM32F0XX_CRC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/*!< Includes ----------------------------------------------------------------*/ -#include "stm32f0xx.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup CRC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup CRC_ReverseInputData - * @{ - */ -#define CRC_ReverseInputData_No ((uint32_t)0x00000000) /*!< No reverse operation of Input Data */ -#define CRC_ReverseInputData_8bits CRC_CR_REV_IN_0 /*!< Reverse operation of Input Data on 8 bits */ -#define CRC_ReverseInputData_16bits CRC_CR_REV_IN_1 /*!< Reverse operation of Input Data on 16 bits */ -#define CRC_ReverseInputData_32bits CRC_CR_REV_IN /*!< Reverse operation of Input Data on 32 bits */ - -#define IS_CRC_REVERSE_INPUT_DATA(DATA) (((DATA) == CRC_ReverseInputData_No) || \ - ((DATA) == CRC_ReverseInputData_8bits) || \ - ((DATA) == CRC_ReverseInputData_16bits) || \ - ((DATA) == CRC_ReverseInputData_32bits)) - -/** - * @} - */ - -/** @defgroup CRC_PolynomialSize - * @brief Only applicable for STM32F042 and STM32F072 devices - * @{ - */ -#define CRC_PolSize_7 CRC_CR_POLSIZE /*!< 7-bit polynomial for CRC calculation */ -#define CRC_PolSize_8 CRC_CR_POLSIZE_1 /*!< 8-bit polynomial for CRC calculation */ -#define CRC_PolSize_16 CRC_CR_POLSIZE_0 /*!< 16-bit polynomial for CRC calculation */ -#define CRC_PolSize_32 ((uint32_t)0x00000000)/*!< 32-bit polynomial for CRC calculation */ - -#define IS_CRC_POL_SIZE(SIZE) (((SIZE) == CRC_PolSize_7) || \ - ((SIZE) == CRC_PolSize_8) || \ - ((SIZE) == CRC_PolSize_16) || \ - ((SIZE) == CRC_PolSize_32)) - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -/* Configuration of the CRC computation unit **********************************/ -void CRC_DeInit(void); -void CRC_ResetDR(void); -void CRC_PolynomialSizeSelect(uint32_t CRC_PolSize); /*!< Only applicable for STM32F042 and STM32F072 devices */ -void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData); -void CRC_ReverseOutputDataCmd(FunctionalState NewState); -void CRC_SetInitRegister(uint32_t CRC_InitValue); -void CRC_SetPolynomial(uint32_t CRC_Pol); /*!< Only applicable for STM32F042 and STM32F072 devices */ - -/* CRC computation ************************************************************/ -uint32_t CRC_CalcCRC(uint32_t CRC_Data); -uint32_t CRC_CalcCRC16bits(uint16_t CRC_Data); /*!< Only applicable for STM32F042 and STM32F072 devices */ -uint32_t CRC_CalcCRC8bits(uint8_t CRC_Data); /*!< Only applicable for STM32F042 and STM32F072 devices */ -uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); -uint32_t CRC_GetCRC(void); - -/* Independent register (IDR) access (write/read) *****************************/ -void CRC_SetIDRegister(uint8_t CRC_IDValue); -uint8_t CRC_GetIDRegister(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0XX_CRC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_crs.h b/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_crs.h deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_crs.h +++ /dev/null @@ -1,183 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_crs.h - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file contains all the functions prototypes for the CRS firmware - * library, applicable only for STM32F042 and STM32F072 devices. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0XX_CRS_H -#define __STM32F0XX_CRS_H - -#ifdef __cplusplus - extern "C" { -#endif - -/*!< Includes ----------------------------------------------------------------*/ -#include "stm32f0xx.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup CRS - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup CRS_Interrupt_Sources - * @{ - */ -#define CRS_IT_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK */ -#define CRS_IT_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning */ -#define CRS_IT_ERR CRS_ISR_ERRF /*!< error */ -#define CRS_IT_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC */ -#define CRS_IT_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ -#define CRS_IT_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ -#define CRS_IT_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ - -#define IS_CRS_IT(IT) (((IT) == CRS_IT_SYNCOK) || ((IT) == CRS_IT_SYNCWARN) || \ - ((IT) == CRS_IT_ERR) || ((IT) == CRS_IT_ESYNC)) - -#define IS_CRS_GET_IT(IT) (((IT) == CRS_IT_SYNCOK) || ((IT) == CRS_IT_SYNCWARN) || \ - ((IT) == CRS_IT_ERR) || ((IT) == CRS_IT_ESYNC) || \ - ((IT) == CRS_IT_TRIMOVF) || ((IT) == CRS_IT_SYNCERR) || \ - ((IT) == CRS_IT_SYNCMISS)) - -#define IS_CRS_CLEAR_IT(IT) ((IT) != 0x00) - -/** - * @} - */ - -/** @defgroup CRS_Flags - * @{ - */ -#define CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK */ -#define CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning */ -#define CRS_FLAG_ERR CRS_ISR_ERRF /*!< error */ -#define CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC */ -#define CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ -#define CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ -#define CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ - -#define IS_CRS_FLAG(FLAG) (((FLAG) == CRS_FLAG_SYNCOK) || ((FLAG) == CRS_FLAG_SYNCWARN) || \ - ((FLAG) == CRS_FLAG_ERR) || ((FLAG) == CRS_FLAG_ESYNC) || \ - ((FLAG) == CRS_FLAG_TRIMOVF) || ((FLAG) == CRS_FLAG_SYNCERR) || \ - ((FLAG) == CRS_FLAG_SYNCMISS)) - -/** - * @} - */ - -/** @defgroup CRS_Synchro_Source - * @{ - */ -#define CRS_SYNCSource_GPIO ((uint32_t)0x00) /*!< Synchro Signal soucre GPIO */ -#define CRS_SYNCSource_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ -#define CRS_SYNCSource_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF */ - -#define IS_CRS_SYNC_SOURCE(SOURCE) (((SOURCE) == CRS_SYNCSource_GPIO) || \ - ((SOURCE) == CRS_SYNCSource_LSE) ||\ - ((SOURCE) == CRS_SYNCSource_USB)) -/** - * @} - */ - -/** @defgroup CRS_SynchroDivider - * @{ - */ -#define CRS_SYNC_Div1 ((uint32_t)0x00) /*!< Synchro Signal not divided */ -#define CRS_SYNC_Div2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ -#define CRS_SYNC_Div4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ -#define CRS_SYNC_Div8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ -#define CRS_SYNC_Div16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ -#define CRS_SYNC_Div32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ -#define CRS_SYNC_Div64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ -#define CRS_SYNC_Div128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ - -#define IS_CRS_SYNC_DIV(DIV) (((DIV) == CRS_SYNC_Div1) || ((DIV) == CRS_SYNC_Div2) ||\ - ((DIV) == CRS_SYNC_Div4) || ((DIV) == CRS_SYNC_Div8) || \ - ((DIV) == CRS_SYNC_Div16) || ((DIV) == CRS_SYNC_Div32) || \ - ((DIV) == CRS_SYNC_Div64) || ((DIV) == CRS_SYNC_Div128)) -/** - * @} - */ - -/** @defgroup CRS_SynchroPolarity - * @{ - */ -#define CRS_SYNCPolarity_Rising ((uint32_t)0x00) /*!< Synchro Active on rising edge */ -#define CRS_SYNCPolarity_Falling CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ - -#define IS_CRS_SYNC_POLARITY(POLARITY) (((POLARITY) == CRS_SYNCPolarity_Rising) || \ - ((POLARITY) == CRS_SYNCPolarity_Falling)) -/** - * @} - */ - - - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -/* Configuration of the CRS **********************************/ -void CRS_DeInit(void); -void CRS_AdjustHSI48CalibrationValue(uint8_t CRS_HSI48CalibrationValue); -void CRS_FrequencyErrorCounterCmd(FunctionalState NewState); -void CRS_AutomaticCalibrationCmd(FunctionalState NewState); -void CRS_SoftwareSynchronizationGenerate(void); -void CRS_FrequencyErrorCounterReload(uint32_t CRS_ReloadValue); -void CRS_FrequencyErrorLimitConfig(uint8_t CRS_ErrorLimitValue); -void CRS_SynchronizationPrescalerConfig(uint32_t CRS_Prescaler); -void CRS_SynchronizationSourceConfig(uint32_t CRS_Source); -void CRS_SynchronizationPolarityConfig(uint32_t CRS_Polarity); -uint32_t CRS_GetReloadValue(void); -uint32_t CRS_GetHSI48CalibrationValue(void); -uint32_t CRS_GetFrequencyErrorValue(void); -uint32_t CRS_GetFrequencyErrorDirection(void); - -/* Interrupts and flags management functions **********************************/ -void CRS_ITConfig(uint32_t CRS_IT, FunctionalState NewState); -FlagStatus CRS_GetFlagStatus(uint32_t CRS_FLAG); -void CRS_ClearFlag(uint32_t CRS_FLAG); -ITStatus CRS_GetITStatus(uint32_t CRS_IT); -void CRS_ClearITPendingBit(uint32_t CRS_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0XX_CRS_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_dac.h b/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_dac.h deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_dac.h +++ /dev/null @@ -1,312 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_dac.h - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file contains all the functions prototypes for the DAC firmware - * library, applicable only for STM32F051 and STM32F072 devices. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0XX_DAC_H -#define __STM32F0XX_DAC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DAC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief DAC Init structure definition - */ - -typedef struct -{ - uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. - This parameter can be a value of @ref DAC_trigger_selection */ - - uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves - are generated, or whether no wave is generated. - This parameter can be a value of @ref DAC_wave_generation - This parameter is only applicable for STM32F072 devices */ - - uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or - the maximum amplitude triangle generation for the DAC channel. - This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude - This parameter is only applicable for STM32F072 devices */ - - uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. - This parameter can be a value of @ref DAC_output_buffer */ -}DAC_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DAC_Exported_Constants - * @{ - */ - -/** @defgroup DAC_Trigger - * @{ - */ - -#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register - has been loaded, and not by external trigger */ -#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel1 */ -#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel1 */ -#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel1, - applicable only for STM32F072 devices */ -#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel1 */ -#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel1 */ -#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channels */ -#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channels */ - -#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \ - ((TRIGGER) == DAC_Trigger_T6_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T7_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T3_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T15_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T2_TRGO) || \ - ((TRIGGER) == DAC_Trigger_Ext_IT9) || \ - ((TRIGGER) == DAC_Trigger_Software)) - -/** - * @} - */ - -/** @defgroup DAC_wave_generation - * @brief This parameters are only applicable for STM32F072 devices. - * @{ - */ - -#define DAC_WaveGeneration_None ((uint32_t)0x00000000) -#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) -#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) -#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \ - ((WAVE) == DAC_WaveGeneration_Noise) || \ - ((WAVE) == DAC_WaveGeneration_Triangle)) -/** - * @} - */ - -/** @defgroup DAC_lfsrunmask_triangleamplitude - * @brief These parameters are only applicable for STM32F072 devices. - * @{ - */ - -#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ -#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ -#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ -#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */ -#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */ -#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */ -#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */ -#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */ -#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */ -#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */ -#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */ -#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */ -#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */ -#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */ - -#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \ - ((VALUE) == DAC_TriangleAmplitude_1) || \ - ((VALUE) == DAC_TriangleAmplitude_3) || \ - ((VALUE) == DAC_TriangleAmplitude_7) || \ - ((VALUE) == DAC_TriangleAmplitude_15) || \ - ((VALUE) == DAC_TriangleAmplitude_31) || \ - ((VALUE) == DAC_TriangleAmplitude_63) || \ - ((VALUE) == DAC_TriangleAmplitude_127) || \ - ((VALUE) == DAC_TriangleAmplitude_255) || \ - ((VALUE) == DAC_TriangleAmplitude_511) || \ - ((VALUE) == DAC_TriangleAmplitude_1023) || \ - ((VALUE) == DAC_TriangleAmplitude_2047) || \ - ((VALUE) == DAC_TriangleAmplitude_4095)) -/** - * @} - */ - -/** @defgroup DAC_OutputBuffer - * @{ - */ - -#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) -#define DAC_OutputBuffer_Disable DAC_CR_BOFF1 -#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \ - ((STATE) == DAC_OutputBuffer_Disable)) -/** - * @} - */ - -/** @defgroup DAC_Channel_selection - * @{ - */ - -#define DAC_Channel_1 ((uint32_t)0x00000000) -#define DAC_Channel_2 ((uint32_t)0x00000010) /*!< Only applicable for STM32F072 devices */ -#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \ - ((CHANNEL) == DAC_Channel_2)) - -/** - * @} - */ - -/** @defgroup DAC_data_alignment - * @{ - */ - -#define DAC_Align_12b_R ((uint32_t)0x00000000) -#define DAC_Align_12b_L ((uint32_t)0x00000004) -#define DAC_Align_8b_R ((uint32_t)0x00000008) -#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \ - ((ALIGN) == DAC_Align_12b_L) || \ - ((ALIGN) == DAC_Align_8b_R)) -/** - * @} - */ - -/** @defgroup DAC_wave_generation - * @brief These parameters are only applicable for STM32F072 devices. - * @{ - */ - -#define DAC_Wave_Noise ((uint32_t)0x00000040) -#define DAC_Wave_Triangle ((uint32_t)0x00000080) -#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \ - ((WAVE) == DAC_Wave_Triangle)) -/** - * @} - */ - -/** @defgroup DAC_data - * @{ - */ - -#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) - -/** - * @} - */ - -/** @defgroup DAC_interrupts_definition - * @{ - */ - -#define DAC_IT_DMAUDR DAC_SR_DMAUDR1 -#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) - -/** - * @} - */ - - -/** @defgroup DAC_flags_definition - * @{ - */ - -#define DAC_FLAG_DMAUDR DAC_SR_DMAUDR1 - -#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Function used to set the DAC configuration to the default reset state *****/ -void DAC_DeInit(void); - -/* DAC channels configuration: trigger, output buffer, data format functions */ -void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); -void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); -void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); -void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState); -void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); /*!< Only applicable for STM32F072 devices */ -void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); /*!< Only applicable for STM32F072 devices */ -void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); -void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); /*!< Only applicable for STM32F072 devices */ -void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); /*!< Only applicable for STM32F072 devices */ -uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); - -/* DMA management functions ***************************************************/ -void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState); -FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG); -void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG); -ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT); -void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F0XX_DAC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_dbgmcu.h b/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_dbgmcu.h deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_dbgmcu.h +++ /dev/null @@ -1,107 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_dbgmcu.h - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file contains all the functions prototypes for the DBGMCU firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0XX_DBGMCU_H -#define __STM32F0XX_DBGMCU_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DBGMCU - * @{ - */ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - - -/** @defgroup DBGMCU_Exported_Constants - * @{ - */ - -#define DBGMCU_STOP DBGMCU_CR_DBG_STOP -#define DBGMCU_STANDBY DBGMCU_CR_DBG_STANDBY -#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF9) == 0x00) && ((PERIPH) != 0x00)) - -#define DBGMCU_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< Not applicable for STM32F030 devices */ -#define DBGMCU_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP -#define DBGMCU_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP -#define DBGMCU_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< Only applicable for STM32F072 devices */ -#define DBGMCU_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP -#define DBGMCU_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP -#define DBGMCU_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP -#define DBGMCU_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP -#define DBGMCU_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT -#define DBGMCU_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP /*!< Only applicable for STM32F042 and STM32F072 devices */ -#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xFDDFE2CC) == 0x00) && ((PERIPH) != 0x00)) - -#define DBGMCU_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP -#define DBGMCU_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP -#define DBGMCU_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP -#define DBGMCU_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP -#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFF8F7FF) == 0x00) && ((PERIPH) != 0x00)) - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Device and Revision ID management functions ********************************/ -uint32_t DBGMCU_GetREVID(void); -uint32_t DBGMCU_GetDEVID(void); - -/* Peripherals Configuration functions ****************************************/ -void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); -void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState); -void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0XX_DBGMCU_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_dma.h b/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_dma.h deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_dma.h +++ /dev/null @@ -1,804 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_dma.h - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file contains all the functions prototypes for the DMA firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0XX_DMA_H -#define __STM32F0XX_DMA_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DMA - * @{ - */ -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief DMA Init structures definition - */ -typedef struct -{ - uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */ - - uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */ - - uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination. - This parameter can be a value of @ref DMA_data_transfer_direction */ - - uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel. - The data unit is equal to the configuration set in DMA_PeripheralDataSize - or DMA_MemoryDataSize members depending in the transfer direction */ - - uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not. - This parameter can be a value of @ref DMA_peripheral_incremented_mode */ - - uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not. - This parameter can be a value of @ref DMA_memory_incremented_mode */ - - uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width. - This parameter can be a value of @ref DMA_peripheral_data_size */ - - uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width. - This parameter can be a value of @ref DMA_memory_data_size */ - - uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx. - This parameter can be a value of @ref DMA_circular_normal_mode - @note: The circular buffer mode cannot be used if the memory-to-memory - data transfer is configured on the selected Channel */ - - uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx. - This parameter can be a value of @ref DMA_priority_level */ - - uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer. - This parameter can be a value of @ref DMA_memory_to_memory */ -}DMA_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DMA_Exported_Constants - * @{ - */ - -#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \ - ((PERIPH) == DMA1_Channel2) || \ - ((PERIPH) == DMA1_Channel3) || \ - ((PERIPH) == DMA1_Channel4) || \ - ((PERIPH) == DMA1_Channel5) || \ - ((PERIPH) == DMA1_Channel6) || \ - ((PERIPH) == DMA1_Channel7) || \ - ((PERIPH) == DMA2_Channel1) || \ - ((PERIPH) == DMA2_Channel2) || \ - ((PERIPH) == DMA2_Channel3) || \ - ((PERIPH) == DMA2_Channel4) || \ - ((PERIPH) == DMA2_Channel5)) - -/** @defgroup DMA_data_transfer_direction - * @{ - */ - -#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) -#define DMA_DIR_PeripheralDST DMA_CCR_DIR - -#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralSRC) || \ - ((DIR) == DMA_DIR_PeripheralDST)) -/** - * @} - */ - -/** @defgroup DMA_peripheral_incremented_mode - * @{ - */ - -#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) -#define DMA_PeripheralInc_Enable DMA_CCR_PINC - -#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Disable) || \ - ((STATE) == DMA_PeripheralInc_Enable)) -/** - * @} - */ - -/** @defgroup DMA_memory_incremented_mode - * @{ - */ - -#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) -#define DMA_MemoryInc_Enable DMA_CCR_MINC - -#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Disable) || \ - ((STATE) == DMA_MemoryInc_Enable)) -/** - * @} - */ - -/** @defgroup DMA_peripheral_data_size - * @{ - */ - -#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) -#define DMA_PeripheralDataSize_HalfWord DMA_CCR_PSIZE_0 -#define DMA_PeripheralDataSize_Word DMA_CCR_PSIZE_1 - -#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ - ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ - ((SIZE) == DMA_PeripheralDataSize_Word)) -/** - * @} - */ - -/** @defgroup DMA_memory_data_size - * @{ - */ - -#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) -#define DMA_MemoryDataSize_HalfWord DMA_CCR_MSIZE_0 -#define DMA_MemoryDataSize_Word DMA_CCR_MSIZE_1 - -#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ - ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ - ((SIZE) == DMA_MemoryDataSize_Word)) -/** - * @} - */ - -/** @defgroup DMA_circular_normal_mode - * @{ - */ - -#define DMA_Mode_Normal ((uint32_t)0x00000000) -#define DMA_Mode_Circular DMA_CCR_CIRC - -#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal) || ((MODE) == DMA_Mode_Circular)) -/** - * @} - */ - -/** @defgroup DMA_priority_level - * @{ - */ - -#define DMA_Priority_VeryHigh DMA_CCR_PL -#define DMA_Priority_High DMA_CCR_PL_1 -#define DMA_Priority_Medium DMA_CCR_PL_0 -#define DMA_Priority_Low ((uint32_t)0x00000000) - -#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \ - ((PRIORITY) == DMA_Priority_High) || \ - ((PRIORITY) == DMA_Priority_Medium) || \ - ((PRIORITY) == DMA_Priority_Low)) -/** - * @} - */ - -/** @defgroup DMA_memory_to_memory - * @{ - */ - -#define DMA_M2M_Disable ((uint32_t)0x00000000) -#define DMA_M2M_Enable DMA_CCR_MEM2MEM - -#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Disable) || ((STATE) == DMA_M2M_Enable)) - -/** - * @} - */ - -/** @defgroup DMA_Remap_Config - * @{ - */ -#define DMAx_CHANNEL1_RMP 0x00000000 -#define DMAx_CHANNEL2_RMP 0x10000000 -#define DMAx_CHANNEL3_RMP 0x20000000 -#define DMAx_CHANNEL4_RMP 0x30000000 -#define DMAx_CHANNEL5_RMP 0x40000000 -#define DMAx_CHANNEL6_RMP 0x50000000 -#define DMAx_CHANNEL7_RMP 0x60000000 - - -#define IS_DMA_ALL_LIST(LIST) (((LIST) == DMA1) || \ - ((LIST) == DMA2)) - -/****************** DMA1 remap bit field definition********************/ -/* DMA1 - Channel 1 */ -#define DMA1_CH1_DEFAULT (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ -#define DMA1_CH1_ADC (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_ADC) /*!< Remap ADC on DMA1 Channel 1*/ -#define DMA1_CH1_TIM17_CH1 (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 1 */ -#define DMA1_CH1_TIM17_UP (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 1 */ -#define DMA1_CH1_USART1_RX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 1 */ -#define DMA1_CH1_USART2_RX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 1 */ -#define DMA1_CH1_USART3_RX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 1 */ -#define DMA1_CH1_USART4_RX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 1 */ -#define DMA1_CH1_USART5_RX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 1 */ -#define DMA1_CH1_USART6_RX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 1 */ -#define DMA1_CH1_USART7_RX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 1 */ -#define DMA1_CH1_USART8_RX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 1 */ -/* DMA1 - Channel 2 */ -#define DMA1_CH2_DEFAULT (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ -#define DMA1_CH2_ADC (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_ADC) /*!< Remap ADC on DMA1 channel 2 */ -#define DMA1_CH2_I2C1_TX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 2 */ -#define DMA1_CH2_SPI1_RX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_SPI_1RX) /*!< Remap SPI1 Rx on DMA1 channel 2 */ -#define DMA1_CH2_TIM1_CH1 (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 2 */ -#define DMA1_CH2_TIM17_CH1 (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 2 */ -#define DMA1_CH2_TIM17_UP (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 2 */ -#define DMA1_CH2_USART1_TX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 2 */ -#define DMA1_CH2_USART2_TX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 2 */ -#define DMA1_CH2_USART3_TX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 2 */ -#define DMA1_CH2_USART4_TX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 2 */ -#define DMA1_CH2_USART5_TX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 2 */ -#define DMA1_CH2_USART6_TX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 2 */ -#define DMA1_CH2_USART7_TX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 2 */ -#define DMA1_CH2_USART8_TX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 2 */ -/* DMA1 - Channel 3 */ -#define DMA1_CH3_DEFAULT (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMAx */ -#define DMA1_CH3_TIM6_UP (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA1 channel 3 */ -#define DMA1_CH3_DAC_CH1 (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_DAC_CH1) /*!< Remap DAC Channel 1on DMA1 channel 3 */ -#define DMA1_CH3_I2C1_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 3 */ -#define DMA1_CH3_SPI1_TX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_SPI1_TX) /*!< Remap SPI1 Tx on DMA1 channel 3 */ -#define DMA1_CH3_TIM1_CH2 (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 3 */ -#define DMA1_CH3_TIM2_CH2 (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 3 */ -#define DMA1_CH3_TIM16_CH1 (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 3 */ -#define DMA1_CH3_TIM16_UP (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 3 */ -#define DMA1_CH3_USART1_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 3 */ -#define DMA1_CH3_USART2_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 3 */ -#define DMA1_CH3_USART3_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 3 */ -#define DMA1_CH3_USART4_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 3 */ -#define DMA1_CH3_USART5_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 3 */ -#define DMA1_CH3_USART6_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 3 */ -#define DMA1_CH3_USART7_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 3 */ -#define DMA1_CH3_USART8_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 3 */ -/* DMA1 - Channel 4 */ -#define DMA1_CH4_DEFAULT (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ -#define DMA1_CH4_TIM7_UP (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA1 channel 4 */ -#define DMA1_CH4_DAC_CH2 (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_DAC_CH2) /*!< Remap DAC Channel 2 on DMA1 channel 4 */ -#define DMA1_CH4_I2C2_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_I2C2_TX) /*!< Remap I2C2 Tx on DMA1 channel 4 */ -#define DMA1_CH4_SPI2_RX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 4 */ -#define DMA1_CH4_TIM2_CH4 (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 4 */ -#define DMA1_CH4_TIM3_CH1 (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 4 */ -#define DMA1_CH4_TIM3_TRIG (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 4 */ -#define DMA1_CH4_TIM16_CH1 (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 4 */ -#define DMA1_CH4_TIM16_UP (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 4 */ -#define DMA1_CH4_USART1_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 4 */ -#define DMA1_CH4_USART2_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 4 */ -#define DMA1_CH4_USART3_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 4 */ -#define DMA1_CH4_USART4_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 4 */ -#define DMA1_CH4_USART5_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 4 */ -#define DMA1_CH4_USART6_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 4 */ -#define DMA1_CH4_USART7_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 4 */ -#define DMA1_CH4_USART8_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 4 */ -/* DMA1 - Channel 5 */ -#define DMA1_CH5_DEFAULT (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ -#define DMA1_CH5_I2C2_RX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_I2C2_RX) /*!< Remap I2C2 Rx on DMA1 channel 5 */ -#define DMA1_CH5_SPI2_TX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_SPI2_TX) /*!< Remap SPI1 Tx on DMA1 channel 5 */ -#define DMA1_CH5_TIM1_CH3 (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 5 */ -#define DMA1_CH5_USART1_RX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 5 */ -#define DMA1_CH5_USART2_RX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 5 */ -#define DMA1_CH5_USART3_RX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 5 */ -#define DMA1_CH5_USART4_RX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 5 */ -#define DMA1_CH5_USART5_RX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 5 */ -#define DMA1_CH5_USART6_RX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 5 */ -#define DMA1_CH5_USART7_RX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 5 */ -#define DMA1_CH5_USART8_RX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 5 */ -/* DMA1 - Channel 6 */ -#define DMA1_CH6_DEFAULT (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ -#define DMA1_CH6_I2C1_TX (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 6 */ -#define DMA1_CH6_SPI2_RX (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 6 */ -#define DMA1_CH6_TIM1_CH1 (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 6 */ -#define DMA1_CH6_TIM1_CH2 (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 6 */ -#define DMA1_CH6_TIM1_CH3 (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 6 */ -#define DMA1_CH6_TIM3_CH1 (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 6 */ -#define DMA1_CH6_TIM3_TRIG (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 6 */ -#define DMA1_CH6_TIM16_CH1 (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 6 */ -#define DMA1_CH6_TIM16_UP (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 6 */ -#define DMA1_CH6_USART1_RX (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 6 */ -#define DMA1_CH6_USART2_RX (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 6 */ -#define DMA1_CH6_USART3_RX (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 6 */ -#define DMA1_CH6_USART4_RX (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 6 */ -#define DMA1_CH6_USART5_RX (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 6 */ -#define DMA1_CH6_USART6_RX (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 6 */ -#define DMA1_CH6_USART7_RX (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 6 */ -#define DMA1_CH6_USART8_RX (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 6 */ -/* DMA1 - Channel 7 */ -#define DMA1_CH7_DEFAULT (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ -#define DMA1_CH7_I2C1_RX (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 7 */ -#define DMA1_CH7_SPI2_TX (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_SPI2_TX) /*!< Remap SPI2 Tx on DMA1 channel 7 */ -#define DMA1_CH7_TIM2_CH2 (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 7 */ -#define DMA1_CH7_TIM2_CH4 (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 7 */ -#define DMA1_CH7_TIM17_CH1 (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 7 */ -#define DMA1_CH7_TIM17_UP (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 7 */ -#define DMA1_CH7_USART1_TX (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 7 */ -#define DMA1_CH7_USART2_TX (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 7 */ -#define DMA1_CH7_USART3_TX (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 7 */ -#define DMA1_CH7_USART4_TX (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 7 */ -#define DMA1_CH7_USART5_TX (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 7 */ -#define DMA1_CH7_USART6_TX (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 7 */ -#define DMA1_CH7_USART7_TX (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 7 */ -#define DMA1_CH7_USART8_TX (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 7 */ - -#define IS_DMA1_REMAP(REMAP) ((REMAP == DMA1_CH1_DEFAULT) ||\ - (REMAP == DMA1_CH1_ADC) ||\ - (REMAP == DMA1_CH1_TIM17_CH1) ||\ - (REMAP == DMA1_CH1_TIM17_UP) ||\ - (REMAP == DMA1_CH1_USART1_RX) ||\ - (REMAP == DMA1_CH1_USART2_RX) ||\ - (REMAP == DMA1_CH1_USART3_RX) ||\ - (REMAP == DMA1_CH1_USART4_RX) ||\ - (REMAP == DMA1_CH1_USART5_RX) ||\ - (REMAP == DMA1_CH1_USART6_RX) ||\ - (REMAP == DMA1_CH1_USART7_RX) ||\ - (REMAP == DMA1_CH1_USART8_RX) ||\ - (REMAP == DMA1_CH2_DEFAULT) ||\ - (REMAP == DMA1_CH2_ADC) ||\ - (REMAP == DMA1_CH2_I2C1_TX) ||\ - (REMAP == DMA1_CH2_SPI1_RX) ||\ - (REMAP == DMA1_CH2_TIM1_CH1) ||\ - (REMAP == DMA1_CH2_I2C1_TX) ||\ - (REMAP == DMA1_CH2_TIM17_CH1) ||\ - (REMAP == DMA1_CH2_TIM17_UP) ||\ - (REMAP == DMA1_CH2_USART1_TX) ||\ - (REMAP == DMA1_CH2_USART2_TX) ||\ - (REMAP == DMA1_CH2_USART3_TX) ||\ - (REMAP == DMA1_CH2_USART4_TX) ||\ - (REMAP == DMA1_CH2_USART5_TX) ||\ - (REMAP == DMA1_CH2_USART6_TX) ||\ - (REMAP == DMA1_CH2_USART7_TX) ||\ - (REMAP == DMA1_CH2_USART8_TX) ||\ - (REMAP == DMA1_CH3_DEFAULT) ||\ - (REMAP == DMA1_CH3_TIM6_UP) ||\ - (REMAP == DMA1_CH3_DAC_CH1) ||\ - (REMAP == DMA1_CH3_I2C1_RX) ||\ - (REMAP == DMA1_CH3_SPI1_TX) ||\ - (REMAP == DMA1_CH3_TIM1_CH2) ||\ - (REMAP == DMA1_CH3_TIM2_CH2) ||\ - (REMAP == DMA1_CH3_TIM16_CH1) ||\ - (REMAP == DMA1_CH3_TIM16_UP) ||\ - (REMAP == DMA1_CH3_USART1_RX) ||\ - (REMAP == DMA1_CH3_USART2_RX) ||\ - (REMAP == DMA1_CH3_USART3_RX) ||\ - (REMAP == DMA1_CH3_USART4_RX) ||\ - (REMAP == DMA1_CH3_USART5_RX) ||\ - (REMAP == DMA1_CH3_USART6_RX) ||\ - (REMAP == DMA1_CH3_USART7_RX) ||\ - (REMAP == DMA1_CH3_USART8_RX) ||\ - (REMAP == DMA1_CH4_DEFAULT) ||\ - (REMAP == DMA1_CH4_TIM7_UP) ||\ - (REMAP == DMA1_CH4_DAC_CH2) ||\ - (REMAP == DMA1_CH4_I2C2_TX) ||\ - (REMAP == DMA1_CH4_SPI2_RX) ||\ - (REMAP == DMA1_CH4_TIM2_CH4) ||\ - (REMAP == DMA1_CH4_TIM3_CH1) ||\ - (REMAP == DMA1_CH4_TIM3_TRIG) ||\ - (REMAP == DMA1_CH4_TIM16_CH1) ||\ - (REMAP == DMA1_CH4_TIM16_UP) ||\ - (REMAP == DMA1_CH4_USART1_TX) ||\ - (REMAP == DMA1_CH4_USART2_TX) ||\ - (REMAP == DMA1_CH4_USART3_TX) ||\ - (REMAP == DMA1_CH4_USART4_TX) ||\ - (REMAP == DMA1_CH4_USART5_TX) ||\ - (REMAP == DMA1_CH4_USART6_TX) ||\ - (REMAP == DMA1_CH4_USART7_TX) ||\ - (REMAP == DMA1_CH4_USART8_TX) ||\ - (REMAP == DMA1_CH5_DEFAULT) ||\ - (REMAP == DMA1_CH5_I2C2_RX) ||\ - (REMAP == DMA1_CH5_SPI2_TX) ||\ - (REMAP == DMA1_CH5_TIM1_CH3) ||\ - (REMAP == DMA1_CH5_USART1_RX) ||\ - (REMAP == DMA1_CH5_USART2_RX) ||\ - (REMAP == DMA1_CH5_USART3_RX) ||\ - (REMAP == DMA1_CH5_USART4_RX) ||\ - (REMAP == DMA1_CH5_USART5_RX) ||\ - (REMAP == DMA1_CH5_USART6_RX) ||\ - (REMAP == DMA1_CH5_USART7_RX) ||\ - (REMAP == DMA1_CH5_USART8_RX) ||\ - (REMAP == DMA1_CH6_DEFAULT) ||\ - (REMAP == DMA1_CH6_I2C1_TX) ||\ - (REMAP == DMA1_CH6_SPI2_RX) ||\ - (REMAP == DMA1_CH6_TIM1_CH1) ||\ - (REMAP == DMA1_CH6_TIM1_CH2) ||\ - (REMAP == DMA1_CH6_TIM1_CH3) ||\ - (REMAP == DMA1_CH6_TIM3_CH1) ||\ - (REMAP == DMA1_CH6_TIM3_TRIG) ||\ - (REMAP == DMA1_CH6_TIM16_CH1) ||\ - (REMAP == DMA1_CH6_TIM16_UP) ||\ - (REMAP == DMA1_CH6_USART1_RX) ||\ - (REMAP == DMA1_CH6_USART2_RX) ||\ - (REMAP == DMA1_CH6_USART3_RX) ||\ - (REMAP == DMA1_CH6_USART4_RX) ||\ - (REMAP == DMA1_CH6_USART5_RX) ||\ - (REMAP == DMA1_CH6_USART6_RX) ||\ - (REMAP == DMA1_CH6_USART7_RX) ||\ - (REMAP == DMA1_CH6_USART8_RX) ||\ - (REMAP == DMA1_CH7_DEFAULT) ||\ - (REMAP == DMA1_CH7_I2C1_RX) ||\ - (REMAP == DMA1_CH7_SPI2_TX) ||\ - (REMAP == DMA1_CH7_TIM2_CH2) ||\ - (REMAP == DMA1_CH7_TIM2_CH4) ||\ - (REMAP == DMA1_CH7_TIM17_CH1) ||\ - (REMAP == DMA1_CH7_TIM17_UP) ||\ - (REMAP == DMA1_CH7_USART1_TX) ||\ - (REMAP == DMA1_CH7_USART2_TX) ||\ - (REMAP == DMA1_CH7_USART3_TX) ||\ - (REMAP == DMA1_CH7_USART4_TX) ||\ - (REMAP == DMA1_CH7_USART5_TX) ||\ - (REMAP == DMA1_CH7_USART6_TX) ||\ - (REMAP == DMA1_CH7_USART7_TX) ||\ - (REMAP == DMA1_CH7_USART8_TX)) - -/****************** DMA2 remap bit field definition********************/ -/* DMA2 - Channel 1 */ -#define DMA2_CH1_DEFAULT (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */ -#define DMA2_CH1_I2C2_TX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_I2C2_TX) /*!< Remap I2C2 TX on DMA2 channel 1 */ -#define DMA2_CH1_USART1_TX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 1 */ -#define DMA2_CH1_USART2_TX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 1 */ -#define DMA2_CH1_USART3_TX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 1 */ -#define DMA2_CH1_USART4_TX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 1 */ -#define DMA2_CH1_USART5_TX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 1 */ -#define DMA2_CH1_USART6_TX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 1 */ -#define DMA2_CH1_USART7_TX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 1 */ -#define DMA2_CH1_USART8_TX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 1 */ -/* DMA2 - Channel 2 */ -#define DMA2_CH2_DEFAULT (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */ -#define DMA2_CH2_I2C2_RX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_I2C2_RX) /*!< Remap I2C2 Rx on DMA2 channel 2 */ -#define DMA2_CH2_USART1_RX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 2 */ -#define DMA2_CH2_USART2_RX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 2 */ -#define DMA2_CH2_USART3_RX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 2 */ -#define DMA2_CH2_USART4_RX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 2 */ -#define DMA2_CH2_USART5_RX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 2 */ -#define DMA2_CH2_USART6_RX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 2 */ -#define DMA2_CH2_USART7_RX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 2 */ -#define DMA2_CH2_USART8_RX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 2 */ -/* DMA2 - Channel 3 */ -#define DMA2_CH3_DEFAULT (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */ -#define DMA2_CH3_TIM6_UP (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA2 channel 3 */ -#define DMA2_CH3_DAC_CH1 (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_DAC_CH1) /*!< Remap DAC channel 1 on DMA2 channel 3 */ -#define DMA2_CH3_SPI1_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_SPI1_RX) /*!< Remap SPI1 Rx on DMA2 channel 3 */ -#define DMA2_CH3_USART1_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 3 */ -#define DMA2_CH3_USART2_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 3 */ -#define DMA2_CH3_USART3_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 3 */ -#define DMA2_CH3_USART4_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 3 */ -#define DMA2_CH3_USART5_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 3 */ -#define DMA2_CH3_USART6_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 3 */ -#define DMA2_CH3_USART7_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 3 */ -#define DMA2_CH3_USART8_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 3 */ -/* DMA2 - Channel 4 */ -#define DMA2_CH4_DEFAULT (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */ -#define DMA2_CH4_TIM7_UP (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA2 channel 4 */ -#define DMA2_CH4_DAC_CH2 (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_DAC_CH2) /*!< Remap DAC channel 2 on DMA2 channel 4 */ -#define DMA2_CH4_SPI1_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_SPI1_TX) /*!< Remap SPI1 Tx on DMA2 channel 4 */ -#define DMA2_CH4_USART1_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 4 */ -#define DMA2_CH4_USART2_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 4 */ -#define DMA2_CH4_USART3_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 4 */ -#define DMA2_CH4_USART4_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 4 */ -#define DMA2_CH4_USART5_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 4 */ -#define DMA2_CH4_USART6_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 4 */ -#define DMA2_CH4_USART7_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 4 */ -#define DMA2_CH4_USART8_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 4 */ -/* DMA2 - Channel 5 */ -#define DMA2_CH5_DEFAULT (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */ -#define DMA2_CH5_ADC (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_ADC) /*!< Remap ADC on DMA2 channel 5 */ -#define DMA2_CH5_USART1_TX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 5 */ -#define DMA2_CH5_USART2_TX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 5 */ -#define DMA2_CH5_USART3_TX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 5 */ -#define DMA2_CH5_USART4_TX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 5 */ -#define DMA2_CH5_USART5_TX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 5 */ -#define DMA2_CH5_USART6_TX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 5 */ -#define DMA2_CH5_USART7_TX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 5 */ -#define DMA2_CH5_USART8_TX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 5 */ - -#define IS_DMA2_REMAP(REMAP) ((REMAP == DMA2_CH1_DEFAULT) ||\ - (REMAP == DMA2_CH1_I2C2_TX) ||\ - (REMAP == DMA2_CH1_USART1_TX) ||\ - (REMAP == DMA2_CH1_USART2_TX) ||\ - (REMAP == DMA2_CH1_USART3_TX) ||\ - (REMAP == DMA2_CH1_USART4_TX) ||\ - (REMAP == DMA2_CH1_USART5_TX) ||\ - (REMAP == DMA2_CH1_USART6_TX) ||\ - (REMAP == DMA2_CH1_USART7_TX) ||\ - (REMAP == DMA2_CH1_USART8_TX) ||\ - (REMAP == DMA2_CH2_DEFAULT) ||\ - (REMAP == DMA2_CH2_I2C2_RX) ||\ - (REMAP == DMA2_CH2_USART1_RX) ||\ - (REMAP == DMA2_CH2_USART2_RX) ||\ - (REMAP == DMA2_CH2_USART3_RX) ||\ - (REMAP == DMA2_CH2_USART4_RX) ||\ - (REMAP == DMA2_CH2_USART5_RX) ||\ - (REMAP == DMA2_CH2_USART6_RX) ||\ - (REMAP == DMA2_CH2_USART7_RX) ||\ - (REMAP == DMA2_CH2_USART8_RX) ||\ - (REMAP == DMA2_CH3_DEFAULT) ||\ - (REMAP == DMA2_CH3_TIM6_UP) ||\ - (REMAP == DMA2_CH3_DAC_CH1) ||\ - (REMAP == DMA2_CH3_SPI1_RX) ||\ - (REMAP == DMA2_CH3_USART1_RX) ||\ - (REMAP == DMA2_CH3_USART2_RX) ||\ - (REMAP == DMA2_CH3_USART3_RX) ||\ - (REMAP == DMA2_CH3_USART4_RX) ||\ - (REMAP == DMA2_CH3_USART5_RX) ||\ - (REMAP == DMA2_CH3_USART6_RX) ||\ - (REMAP == DMA2_CH3_USART7_RX) ||\ - (REMAP == DMA2_CH3_USART8_RX) ||\ - (REMAP == DMA2_CH4_DEFAULT) ||\ - (REMAP == DMA2_CH4_TIM7_UP) ||\ - (REMAP == DMA2_CH4_DAC_CH2) ||\ - (REMAP == DMA2_CH4_SPI1_TX) ||\ - (REMAP == DMA2_CH4_USART1_TX) ||\ - (REMAP == DMA2_CH4_USART2_TX) ||\ - (REMAP == DMA2_CH4_USART3_TX) ||\ - (REMAP == DMA2_CH4_USART4_TX) ||\ - (REMAP == DMA2_CH4_USART5_TX) ||\ - (REMAP == DMA2_CH4_USART6_TX) ||\ - (REMAP == DMA2_CH4_USART7_TX) ||\ - (REMAP == DMA2_CH4_USART8_TX) ||\ - (REMAP == DMA2_CH5_DEFAULT) ||\ - (REMAP == DMA2_CH5_ADC) ||\ - (REMAP == DMA2_CH5_USART1_TX) ||\ - (REMAP == DMA2_CH5_USART2_TX) ||\ - (REMAP == DMA2_CH5_USART3_TX) ||\ - (REMAP == DMA2_CH5_USART4_TX) ||\ - (REMAP == DMA2_CH5_USART5_TX) ||\ - (REMAP == DMA2_CH5_USART6_TX) ||\ - (REMAP == DMA2_CH5_USART7_TX) ||\ - (REMAP == DMA2_CH5_USART8_TX )) - -/** - * @} - */ - -/** @defgroup DMA_interrupts_definition - * @{ - */ - -#define DMA_IT_TC DMA_CCR_TCIE -#define DMA_IT_HT DMA_CCR_HTIE -#define DMA_IT_TE DMA_CCR_TEIE - -#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00)) - -#define DMA1_IT_GL1 DMA_ISR_GIF1 -#define DMA1_IT_TC1 DMA_ISR_TCIF1 -#define DMA1_IT_HT1 DMA_ISR_HTIF1 -#define DMA1_IT_TE1 DMA_ISR_TEIF1 -#define DMA1_IT_GL2 DMA_ISR_GIF2 -#define DMA1_IT_TC2 DMA_ISR_TCIF2 -#define DMA1_IT_HT2 DMA_ISR_HTIF2 -#define DMA1_IT_TE2 DMA_ISR_TEIF2 -#define DMA1_IT_GL3 DMA_ISR_GIF3 -#define DMA1_IT_TC3 DMA_ISR_TCIF3 -#define DMA1_IT_HT3 DMA_ISR_HTIF3 -#define DMA1_IT_TE3 DMA_ISR_TEIF3 -#define DMA1_IT_GL4 DMA_ISR_GIF4 -#define DMA1_IT_TC4 DMA_ISR_TCIF4 -#define DMA1_IT_HT4 DMA_ISR_HTIF4 -#define DMA1_IT_TE4 DMA_ISR_TEIF4 -#define DMA1_IT_GL5 DMA_ISR_GIF5 -#define DMA1_IT_TC5 DMA_ISR_TCIF5 -#define DMA1_IT_HT5 DMA_ISR_HTIF5 -#define DMA1_IT_TE5 DMA_ISR_TEIF5 -#define DMA1_IT_GL6 DMA_ISR_GIF6 /*!< Only applicable for STM32F072 and STM32F091 devices */ -#define DMA1_IT_TC6 DMA_ISR_TCIF6 /*!< Only applicable for STM32F072 and STM32F091 devices */ -#define DMA1_IT_HT6 DMA_ISR_HTIF6 /*!< Only applicable for STM32F072 and STM32F091 devices */ -#define DMA1_IT_TE6 DMA_ISR_TEIF6 /*!< Only applicable for STM32F072 and STM32F091 devices */ -#define DMA1_IT_GL7 DMA_ISR_GIF7 /*!< Only applicable for STM32F072 and STM32F091 devices */ -#define DMA1_IT_TC7 DMA_ISR_TCIF7 /*!< Only applicable for STM32F072 and STM32F091 devices */ -#define DMA1_IT_HT7 DMA_ISR_HTIF7 /*!< Only applicable for STM32F072 and STM32F091 devices */ -#define DMA1_IT_TE7 DMA_ISR_TEIF7 /*!< Only applicable for STM32F072 and STM32F091 devices */ - -#define DMA2_IT_GL1 ((uint32_t)0x10000001) /*!< Only applicable for STM32F091 devices */ -#define DMA2_IT_TC1 ((uint32_t)0x10000002) /*!< Only applicable for STM32F091 devices */ -#define DMA2_IT_HT1 ((uint32_t)0x10000004) /*!< Only applicable for STM32F091 devices */ -#define DMA2_IT_TE1 ((uint32_t)0x10000008) /*!< Only applicable for STM32F091 devices */ -#define DMA2_IT_GL2 ((uint32_t)0x10000010) /*!< Only applicable for STM32F091 devices */ -#define DMA2_IT_TC2 ((uint32_t)0x10000020) /*!< Only applicable for STM32F091 devices */ -#define DMA2_IT_HT2 ((uint32_t)0x10000040) /*!< Only applicable for STM32F091 devices */ -#define DMA2_IT_TE2 ((uint32_t)0x10000080) /*!< Only applicable for STM32F091 devices */ -#define DMA2_IT_GL3 ((uint32_t)0x10000100) /*!< Only applicable for STM32F091 devices */ -#define DMA2_IT_TC3 ((uint32_t)0x10000200) /*!< Only applicable for STM32F091 devices */ -#define DMA2_IT_HT3 ((uint32_t)0x10000400) /*!< Only applicable for STM32F091 devices */ -#define DMA2_IT_TE3 ((uint32_t)0x10000800) /*!< Only applicable for STM32F091 devices */ -#define DMA2_IT_GL4 ((uint32_t)0x10001000) /*!< Only applicable for STM32F091 devices */ -#define DMA2_IT_TC4 ((uint32_t)0x10002000) /*!< Only applicable for STM32F091 devices */ -#define DMA2_IT_HT4 ((uint32_t)0x10004000) /*!< Only applicable for STM32F091 devices */ -#define DMA2_IT_TE4 ((uint32_t)0x10008000) /*!< Only applicable for STM32F091 devices */ -#define DMA2_IT_GL5 ((uint32_t)0x10010000) /*!< Only applicable for STM32F091 devices */ -#define DMA2_IT_TC5 ((uint32_t)0x10020000) /*!< Only applicable for STM32F091 devices */ -#define DMA2_IT_HT5 ((uint32_t)0x10040000) /*!< Only applicable for STM32F091 devices */ -#define DMA2_IT_TE5 ((uint32_t)0x10080000) /*!< Only applicable for STM32F091 devices */ - -#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00)) - -#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \ - ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \ - ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \ - ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \ - ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \ - ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \ - ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \ - ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \ - ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \ - ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \ - ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \ - ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \ - ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \ - ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \ - ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \ - ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \ - ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \ - ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \ - ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \ - ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \ - ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \ - ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \ - ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \ - ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5)) - -/** - * @} - */ - -/** @defgroup DMA_flags_definition - * @{ - */ -#define DMA1_FLAG_GL1 DMA_ISR_GIF1 -#define DMA1_FLAG_TC1 DMA_ISR_TCIF1 -#define DMA1_FLAG_HT1 DMA_ISR_HTIF1 -#define DMA1_FLAG_TE1 DMA_ISR_TEIF1 -#define DMA1_FLAG_GL2 DMA_ISR_GIF2 -#define DMA1_FLAG_TC2 DMA_ISR_TCIF2 -#define DMA1_FLAG_HT2 DMA_ISR_HTIF2 -#define DMA1_FLAG_TE2 DMA_ISR_TEIF2 -#define DMA1_FLAG_GL3 DMA_ISR_GIF3 -#define DMA1_FLAG_TC3 DMA_ISR_TCIF3 -#define DMA1_FLAG_HT3 DMA_ISR_HTIF3 -#define DMA1_FLAG_TE3 DMA_ISR_TEIF3 -#define DMA1_FLAG_GL4 DMA_ISR_GIF4 -#define DMA1_FLAG_TC4 DMA_ISR_TCIF4 -#define DMA1_FLAG_HT4 DMA_ISR_HTIF4 -#define DMA1_FLAG_TE4 DMA_ISR_TEIF4 -#define DMA1_FLAG_GL5 DMA_ISR_GIF5 -#define DMA1_FLAG_TC5 DMA_ISR_TCIF5 -#define DMA1_FLAG_HT5 DMA_ISR_HTIF5 -#define DMA1_FLAG_TE5 DMA_ISR_TEIF5 -#define DMA1_FLAG_GL6 DMA_ISR_GIF6 /*!< Only applicable for STM32F072 and STM32F091 devices */ -#define DMA1_FLAG_TC6 DMA_ISR_TCIF6 /*!< Only applicable for STM32F072 and STM32F091 devices */ -#define DMA1_FLAG_HT6 DMA_ISR_HTIF6 /*!< Only applicable for STM32F072 and STM32F091 devices */ -#define DMA1_FLAG_TE6 DMA_ISR_TEIF6 /*!< Only applicable for STM32F072 and STM32F091 devices */ -#define DMA1_FLAG_GL7 DMA_ISR_GIF7 /*!< Only applicable for STM32F072 and STM32F091 devices */ -#define DMA1_FLAG_TC7 DMA_ISR_TCIF7 /*!< Only applicable for STM32F072 and STM32F091 devices */ -#define DMA1_FLAG_HT7 DMA_ISR_HTIF7 /*!< Only applicable for STM32F072 and STM32F091 devices */ -#define DMA1_FLAG_TE7 DMA_ISR_TEIF7 /*!< Only applicable for STM32F072 and STM32F091 devices */ - -#define DMA2_FLAG_GL1 ((uint32_t)0x10000001) -#define DMA2_FLAG_TC1 ((uint32_t)0x10000002) -#define DMA2_FLAG_HT1 ((uint32_t)0x10000004) -#define DMA2_FLAG_TE1 ((uint32_t)0x10000008) -#define DMA2_FLAG_GL2 ((uint32_t)0x10000010) -#define DMA2_FLAG_TC2 ((uint32_t)0x10000020) -#define DMA2_FLAG_HT2 ((uint32_t)0x10000040) -#define DMA2_FLAG_TE2 ((uint32_t)0x10000080) -#define DMA2_FLAG_GL3 ((uint32_t)0x10000100) -#define DMA2_FLAG_TC3 ((uint32_t)0x10000200) -#define DMA2_FLAG_HT3 ((uint32_t)0x10000400) -#define DMA2_FLAG_TE3 ((uint32_t)0x10000800) -#define DMA2_FLAG_GL4 ((uint32_t)0x10001000) -#define DMA2_FLAG_TC4 ((uint32_t)0x10002000) -#define DMA2_FLAG_HT4 ((uint32_t)0x10004000) -#define DMA2_FLAG_TE4 ((uint32_t)0x10008000) -#define DMA2_FLAG_GL5 ((uint32_t)0x10010000) -#define DMA2_FLAG_TC5 ((uint32_t)0x10020000) -#define DMA2_FLAG_HT5 ((uint32_t)0x10040000) -#define DMA2_FLAG_TE5 ((uint32_t)0x10080000) - -#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00)) - -#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \ - ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \ - ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \ - ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \ - ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \ - ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \ - ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \ - ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \ - ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \ - ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \ - ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \ - ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \ - ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \ - ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \ - ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \ - ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \ - ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \ - ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \ - ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \ - ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \ - ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \ - ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \ - ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \ - ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5)) -/** - * @} - */ - -/** @defgroup DMA_Buffer_Size - * @{ - */ - -#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Function used to set the DMA configuration to the default reset state ******/ -void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx); - -/* Initialization and Configuration functions *********************************/ -void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct); -void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); -void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState); -void DMA_RemapConfig(DMA_TypeDef* DMAy, uint32_t DMAx_CHy_RemapRequest); - -/* Data Counter functions******************************************************/ -void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber); -uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx); - -/* Interrupts and flags management functions **********************************/ -void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); -FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); -void DMA_ClearFlag(uint32_t DMAy_FLAG); -ITStatus DMA_GetITStatus(uint32_t DMAy_IT); -void DMA_ClearITPendingBit(uint32_t DMAy_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F0XX_DMA_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_exti.h b/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_exti.h deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_exti.h +++ /dev/null @@ -1,216 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_exti.h - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file contains all the functions prototypes for the EXTI - * firmware library - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0XX_EXTI_H -#define __STM32F0XX_EXTI_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup EXTI - * @{ - */ -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief EXTI mode enumeration - */ - -typedef enum -{ - EXTI_Mode_Interrupt = 0x00, - EXTI_Mode_Event = 0x04 -}EXTIMode_TypeDef; - -#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) - -/** - * @brief EXTI Trigger enumeration - */ - -typedef enum -{ - EXTI_Trigger_Rising = 0x08, - EXTI_Trigger_Falling = 0x0C, - EXTI_Trigger_Rising_Falling = 0x10 -}EXTITrigger_TypeDef; - -#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ - ((TRIGGER) == EXTI_Trigger_Falling) || \ - ((TRIGGER) == EXTI_Trigger_Rising_Falling)) -/** - * @brief EXTI Init Structure definition - */ - -typedef struct -{ - uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. - This parameter can be any combination of @ref EXTI_Lines */ - - EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines. - This parameter can be a value of @ref EXTIMode_TypeDef */ - - EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. - This parameter can be a value of @ref EXTIMode_TypeDef */ - - FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. - This parameter can be set either to ENABLE or DISABLE */ -}EXTI_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup EXTI_Exported_Constants - * @{ - */ -/** @defgroup EXTI_Lines - * @{ - */ - -#define EXTI_Line0 ((uint32_t)0x00000001) /*!< External interrupt line 0 */ -#define EXTI_Line1 ((uint32_t)0x00000002) /*!< External interrupt line 1 */ -#define EXTI_Line2 ((uint32_t)0x00000004) /*!< External interrupt line 2 */ -#define EXTI_Line3 ((uint32_t)0x00000008) /*!< External interrupt line 3 */ -#define EXTI_Line4 ((uint32_t)0x00000010) /*!< External interrupt line 4 */ -#define EXTI_Line5 ((uint32_t)0x00000020) /*!< External interrupt line 5 */ -#define EXTI_Line6 ((uint32_t)0x00000040) /*!< External interrupt line 6 */ -#define EXTI_Line7 ((uint32_t)0x00000080) /*!< External interrupt line 7 */ -#define EXTI_Line8 ((uint32_t)0x00000100) /*!< External interrupt line 8 */ -#define EXTI_Line9 ((uint32_t)0x00000200) /*!< External interrupt line 9 */ -#define EXTI_Line10 ((uint32_t)0x00000400) /*!< External interrupt line 10 */ -#define EXTI_Line11 ((uint32_t)0x00000800) /*!< External interrupt line 11 */ -#define EXTI_Line12 ((uint32_t)0x00001000) /*!< External interrupt line 12 */ -#define EXTI_Line13 ((uint32_t)0x00002000) /*!< External interrupt line 13 */ -#define EXTI_Line14 ((uint32_t)0x00004000) /*!< External interrupt line 14 */ -#define EXTI_Line15 ((uint32_t)0x00008000) /*!< External interrupt line 15 */ -#define EXTI_Line16 ((uint32_t)0x00010000) /*!< External interrupt line 16 - Connected to the PVD Output, - not applicable for STM32F030 devices */ -#define EXTI_Line17 ((uint32_t)0x00020000) /*!< Internal interrupt line 17 - Connected to the RTC Alarm - event */ -#define EXTI_Line18 ((uint32_t)0x00040000) /*!< Internal interrupt line 18 - Connected to the USB - event, only applicable for - STM32F072 devices */ -#define EXTI_Line19 ((uint32_t)0x00080000) /*!< Internal interrupt line 19 - Connected to the RTC Tamper - and Time Stamp events */ -#define EXTI_Line20 ((uint32_t)0x00100000) /*!< Internal interrupt line 20 - Connected to the RTC wakeup - event, only applicable for - STM32F072 devices */ -#define EXTI_Line21 ((uint32_t)0x00200000) /*!< Internal interrupt line 21 - Connected to the Comparator 1 - event, only applicable for STM32F051 - ans STM32F072 devices */ -#define EXTI_Line22 ((uint32_t)0x00400000) /*!< Internal interrupt line 22 - Connected to the Comparator 2 - event, only applicable for STM32F051 - and STM32F072 devices */ -#define EXTI_Line23 ((uint32_t)0x00800000) /*!< Internal interrupt line 23 - Connected to the I2C1 wakeup - event, not applicable for STM32F030 devices */ -#define EXTI_Line25 ((uint32_t)0x02000000) /*!< Internal interrupt line 25 - Connected to the USART1 wakeup - event, not applicable for STM32F030 devices */ -#define EXTI_Line26 ((uint32_t)0x04000000) /*!< Internal interrupt line 26 - Connected to the USART2 wakeup - event, applicable only for - STM32F072 devices */ -#define EXTI_Line27 ((uint32_t)0x08000000) /*!< Internal interrupt line 27 - Connected to the CEC wakeup - event, applicable only for STM32F051 - and STM32F072 devices */ -#define EXTI_Line31 ((uint32_t)0x80000000) /*!< Internal interrupt line 31 - Connected to the VDD USB monitor - event, applicable only for - STM32F072 devices */ -#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0x71000000) == 0x00) && ((LINE) != (uint16_t)0x00)) - -#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ - ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ - ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ - ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ - ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ - ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ - ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ - ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ - ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ - ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \ - ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) || \ - ((LINE) == EXTI_Line22) || ((LINE) == EXTI_Line23) || \ - ((LINE) == EXTI_Line25) || ((LINE) == EXTI_Line26) || \ - ((LINE) == EXTI_Line27) || ((LINE) == EXTI_Line31)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -/* Function used to set the EXTI configuration to the default reset state *****/ -void EXTI_DeInit(void); - -/* Initialization and Configuration functions *********************************/ -void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); -void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); - -/* Interrupts and flags management functions **********************************/ -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); -void EXTI_ClearFlag(uint32_t EXTI_Line); -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); -void EXTI_ClearITPendingBit(uint32_t EXTI_Line); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0XX_EXTI_H */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_flash.h b/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_flash.h deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_flash.h +++ /dev/null @@ -1,439 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_flash.h - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file contains all the functions prototypes for the FLASH - * firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0XX_FLASH_H -#define __STM32F0XX_FLASH_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup FLASH - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief FLASH Status - */ -typedef enum -{ - FLASH_BUSY = 1, - FLASH_ERROR_WRP, - FLASH_ERROR_PROGRAM, - FLASH_COMPLETE, - FLASH_TIMEOUT -}FLASH_Status; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup FLASH_Exported_Constants - * @{ - */ - -/** @defgroup FLASH_Latency - * @{ - */ -#define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */ -#define FLASH_Latency_1 FLASH_ACR_LATENCY /*!< FLASH One Latency cycle */ - -#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ - ((LATENCY) == FLASH_Latency_1)) -/** - * @} - */ - -/** @defgroup FLASH_Interrupts - * @{ - */ - -#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of programming interrupt source */ -#define FLASH_IT_ERR FLASH_CR_ERRIE /*!< Error interrupt source */ -#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) -/** - * @} - */ - -/** @defgroup FLASH_Address - * @{ - */ -#ifndef STM32F072 - #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0800FFFF)) -#else - #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0801FFFF)) -#endif /* STM32F072 */ -/** - * @} - */ - -/** @defgroup FLASH_OB_DATA_ADDRESS - * @{ - */ -#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806)) - -/** - * @} - */ - -/** @defgroup FLASH_Option_Bytes_Write_Protection - * @{ - */ - -#if !defined (STM32F072) && !defined (STM32F091) - -#define OB_WRP_Pages0to3 ((uint32_t)0x00000001) /* Write protection of page 0 to 3 */ -#define OB_WRP_Pages4to7 ((uint32_t)0x00000002) /* Write protection of page 4 to 7 */ -#define OB_WRP_Pages8to11 ((uint32_t)0x00000004) /* Write protection of page 8 to 11 */ -#define OB_WRP_Pages12to15 ((uint32_t)0x00000008) /* Write protection of page 12 to 15 */ -#define OB_WRP_Pages16to19 ((uint32_t)0x00000010) /* Write protection of page 16 to 19 */ -#define OB_WRP_Pages20to23 ((uint32_t)0x00000020) /* Write protection of page 20 to 23 */ -#define OB_WRP_Pages24to27 ((uint32_t)0x00000040) /* Write protection of page 24 to 27 */ -#define OB_WRP_Pages28to31 ((uint32_t)0x00000080) /* Write protection of page 28 to 31 */ -#define OB_WRP_Pages32to35 ((uint32_t)0x00000100) /* Write protection of page 32 to 35 */ -#define OB_WRP_Pages36to39 ((uint32_t)0x00000200) /* Write protection of page 36 to 39 */ -#define OB_WRP_Pages40to43 ((uint32_t)0x00000400) /* Write protection of page 40 to 43 */ -#define OB_WRP_Pages44to47 ((uint32_t)0x00000800) /* Write protection of page 44 to 47 */ -#define OB_WRP_Pages48to51 ((uint32_t)0x00001000) /* Write protection of page 48 to 51 */ -#define OB_WRP_Pages52to55 ((uint32_t)0x00002000) /* Write protection of page 52 to 55 */ -#define OB_WRP_Pages56to59 ((uint32_t)0x00004000) /* Write protection of page 56 to 59 */ -#define OB_WRP_Pages60to63 ((uint32_t)0x00008000) /* Write protection of page 60 to 63 */ - -#define OB_WRP_AllPages ((uint32_t)0x0000FFFF) /*!< Write protection of all Sectors */ - -#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000)) - -#else - -#define OB_WRP_Pages0to1 ((uint32_t)0x00000001) /* Write protection of page 0 to 1 */ -#define OB_WRP_Pages2to3 ((uint32_t)0x00000002) /* Write protection of page 2 to 3 */ -#define OB_WRP_Pages4to5 ((uint32_t)0x00000004) /* Write protection of page 4 to 5 */ -#define OB_WRP_Pages6to7 ((uint32_t)0x00000008) /* Write protection of page 6 to 7 */ -#define OB_WRP_Pages8to9 ((uint32_t)0x00000010) /* Write protection of page 8 to 9 */ -#define OB_WRP_Pages10to11 ((uint32_t)0x00000020) /* Write protection of page 10 to 11 */ -#define OB_WRP_Pages12to13 ((uint32_t)0x00000040) /* Write protection of page 12 to 13 */ -#define OB_WRP_Pages14to15 ((uint32_t)0x00000080) /* Write protection of page 14 to 15 */ -#define OB_WRP_Pages16to17 ((uint32_t)0x00000100) /* Write protection of page 16 to 17 */ -#define OB_WRP_Pages18to19 ((uint32_t)0x00000200) /* Write protection of page 18 to 19 */ -#define OB_WRP_Pages20to21 ((uint32_t)0x00000400) /* Write protection of page 20 to 21 */ -#define OB_WRP_Pages22to23 ((uint32_t)0x00000800) /* Write protection of page 22 to 23 */ -#define OB_WRP_Pages24to25 ((uint32_t)0x00001000) /* Write protection of page 24 to 25 */ -#define OB_WRP_Pages26to27 ((uint32_t)0x00002000) /* Write protection of page 26 to 27 */ -#define OB_WRP_Pages28to29 ((uint32_t)0x00004000) /* Write protection of page 28 to 29 */ -#define OB_WRP_Pages30to31 ((uint32_t)0x00008000) /* Write protection of page 30 to 31 */ -#define OB_WRP_Pages32to33 ((uint32_t)0x00010000) /* Write protection of page 32 to 33 */ -#define OB_WRP_Pages34to35 ((uint32_t)0x00020000) /* Write protection of page 34 to 35 */ -#define OB_WRP_Pages36to37 ((uint32_t)0x00040000) /* Write protection of page 36 to 37 */ -#define OB_WRP_Pages38to39 ((uint32_t)0x00080000) /* Write protection of page 38 to 39 */ -#define OB_WRP_Pages40to41 ((uint32_t)0x00100000) /* Write protection of page 40 to 41 */ -#define OB_WRP_Pages42to43 ((uint32_t)0x00200000) /* Write protection of page 42 to 43 */ -#define OB_WRP_Pages44to45 ((uint32_t)0x00400000) /* Write protection of page 44 to 45 */ -#define OB_WRP_Pages46to47 ((uint32_t)0x00800000) /* Write protection of page 46 to 47 */ -#define OB_WRP_Pages48to49 ((uint32_t)0x01000000) /* Write protection of page 48 to 49 */ -#define OB_WRP_Pages50to51 ((uint32_t)0x02000000) /* Write protection of page 50 to 51 */ -#define OB_WRP_Pages52to53 ((uint32_t)0x04000000) /* Write protection of page 52 to 53 */ -#define OB_WRP_Pages54to55 ((uint32_t)0x08000000) /* Write protection of page 54 to 55 */ -#define OB_WRP_Pages56to57 ((uint32_t)0x10000000) /* Write protection of page 56 to 57 */ -#define OB_WRP_Pages58to59 ((uint32_t)0x20000000) /* Write protection of page 58 to 59 */ -#define OB_WRP_Pages60to61 ((uint32_t)0x40000000) /* Write protection of page 60 to 61 */ - -#ifdef STM32F091 - -#define OB_WRP_Pages62to127 ((uint32_t)0x80000000) /* Write protection of page 62 to 127 */ - -#else - -#define OB_WRP_Pages62to63 ((uint32_t)0x80000000) /* Write protection of page 62 to 63 */ - -#endif /* STM32F091 */ - -#define OB_WRP_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */ - -#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000)) - -#endif /* STM32F072 */ - -/** - * @} - */ - -/** @defgroup FLASH_Option_Bytes_Read_Protection - * @{ - */ - -/** - * @brief FLASH_Read Protection Level - */ -#define OB_RDP_Level_0 ((uint8_t)0xAA) -#define OB_RDP_Level_1 ((uint8_t)0xBB) -/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /* Warning: When enabling read protection level 2 - it's no more possible to go back to level 1 or 0 */ - -#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\ - ((LEVEL) == OB_RDP_Level_1))/*||\ - ((LEVEL) == OB_RDP_Level_2))*/ -/** - * @} - */ - -/** @defgroup FLASH_Option_Bytes_IWatchdog - * @{ - */ - -#define OB_IWDG_SW ((uint8_t)0x01) /*!< Software IWDG selected */ -#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */ -#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) - -/** - * @} - */ - -/** @defgroup FLASH_Option_Bytes_nRST_STOP - * @{ - */ - -#define OB_STOP_NoRST ((uint8_t)0x02) /*!< No reset generated when entering in STOP */ -#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */ -#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) - -/** - * @} - */ - -/** @defgroup FLASH_Option_Bytes_nRST_STDBY - * @{ - */ - -#define OB_STDBY_NoRST ((uint8_t)0x04) /*!< No reset generated when entering in STANDBY */ -#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */ -#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) - -/** - * @} - */ - -/** @defgroup FLASH_Option_Bytes_BOOT1 - * @{ - */ - -#define OB_BOOT1_RESET ((uint8_t)0x00) /*!< BOOT1 Reset */ -#define OB_BOOT1_SET ((uint8_t)0x10) /*!< BOOT1 Set */ -#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET)) - -/** - * @} - */ - -/** @defgroup FLASH_Option_Bytes_BOOT0 - * @{ - */ - -#define OB_BOOT0_RESET ((uint8_t)0x00) /*!< BOOT0 Reset */ -#define OB_BOOT0_SET ((uint8_t)0x08) /*!< BOOT0 Set */ -#define IS_OB_BOOT0(BOOT0) (((BOOT0) == OB_BOOT0_RESET) || ((BOOT0) == OB_BOOT0_SET)) - -/** - * @} - */ - -/** @defgroup FLASH_Option_Bytes_BOOT0SW - * @{ - */ - -#define OB_BOOT0_SW ((uint8_t)0x00) /*!< BOOT0 pin disabled */ -#define OB_BOOT0_HW ((uint8_t)0x80) /*!< BOOT0 pin bonded with GPIO */ -#define IS_OB_BOOT0SW(BOOT0) (((BOOT0) == OB_BOOT0_SW) || ((BOOT0) == OB_BOOT0_HW)) - -/** - * @} - */ - -/** @defgroup FLASH_Option_Bytes_VDDA_Analog_Monitoring - * @{ - */ - -#define OB_VDDA_ANALOG_ON ((uint8_t)0x20) /*!< Analog monitoring on VDDA Power source ON */ -#define OB_VDDA_ANALOG_OFF ((uint8_t)0x00) /*!< Analog monitoring on VDDA Power source OFF */ - -#define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF)) - -/** - * @} - */ - -/** @defgroup FLASH_Option_Bytes_SRAM_Parity_Enable - * @{ - */ - -#define OB_SRAM_PARITY_SET ((uint8_t)0x00) /*!< SRAM parity enable Set */ -#define OB_SRAM_PARITY_RESET ((uint8_t)0x40) /*!< SRAM parity enable reset */ - -#define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET)) - -/** - * @} - */ - -/** @defgroup FLASH_Flags - * @{ - */ - -#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ -#define FLASH_FLAG_PGERR FLASH_SR_PGERR /*!< FLASH Programming error flag */ -#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */ -#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Programming flag */ - -#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCB) == 0x00000000) && ((FLAG) != 0x00000000)) - -#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_PGERR) || \ - ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_EOP)) -/** - * @} - */ - -/** @defgroup FLASH_Timeout_definition - * @{ - */ -#define FLASH_ER_PRG_TIMEOUT ((uint32_t)0x000B0000) - -/** - * @} - */ - -/** @defgroup FLASH_Legacy - * @{ - */ -#define FLASH_WRProt_Pages0to3 OB_WRP_Pages0to3 -#define FLASH_WRProt_Pages4to7 OB_WRP_Pages4to7 -#define FLASH_WRProt_Pages8to11 OB_WRP_Pages8to11 -#define FLASH_WRProt_Pages12to15 OB_WRP_Pages12to15 -#define FLASH_WRProt_Pages16to19 OB_WRP_Pages16to19 -#define FLASH_WRProt_Pages20to23 OB_WRP_Pages20to23 -#define FLASH_WRProt_Pages24to27 OB_WRP_Pages24to27 -#define FLASH_WRProt_Pages28to31 OB_WRP_Pages28to31 -#define FLASH_WRProt_Pages32to35 OB_WRP_Pages32to35 -#define FLASH_WRProt_Pages36to39 OB_WRP_Pages36to39 -#define FLASH_WRProt_Pages40to43 OB_WRP_Pages40to21 -#define FLASH_WRProt_Pages44to47 OB_WRP_Pages44to23 -#define FLASH_WRProt_Pages48to51 OB_WRP_Pages48to51 -#define FLASH_WRProt_Pages52to55 OB_WRP_Pages52to55 -#define FLASH_WRProt_Pages56to59 OB_WRP_Pages56to59 -#define FLASH_WRProt_Pages60to63 OB_WRP_Pages60to63 - - -#define FLASH_WRProt_AllPages OB_WRP_AllPages -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/** - * @brief FLASH memory functions that can be executed from FLASH. - */ -/* FLASH Interface configuration functions ************************************/ -void FLASH_SetLatency(uint32_t FLASH_Latency); -void FLASH_PrefetchBufferCmd(FunctionalState NewState); -FlagStatus FLASH_GetPrefetchBufferStatus(void); - -/* FLASH Memory Programming functions *****************************************/ -void FLASH_Unlock(void); -void FLASH_Lock(void); -FLASH_Status FLASH_ErasePage(uint32_t Page_Address); -FLASH_Status FLASH_EraseAllPages(void); -FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); -FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); - -/* FLASH Option Bytes Programming functions *****************************************/ -void FLASH_OB_Unlock(void); -void FLASH_OB_Lock(void); -void FLASH_OB_Launch(void); -FLASH_Status FLASH_OB_Erase(void); -FLASH_Status FLASH_OB_EnableWRP(uint32_t OB_WRP); -FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP); -FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY); -FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1); -FLASH_Status FLASH_OB_BOOT0Config(uint8_t OB_BOOT0); -FLASH_Status FLASH_OB_BOOT0SWConfig(uint8_t OB_BOOT0SW); -FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG); -FLASH_Status FLASH_OB_SRAMParityConfig(uint8_t OB_SRAM_Parity); -FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER); -FLASH_Status FLASH_OB_ProgramData(uint32_t Address, uint8_t Data); -uint8_t FLASH_OB_GetUser(void); -uint32_t FLASH_OB_GetWRP(void); -FlagStatus FLASH_OB_GetRDP(void); - -/* FLASH Interrupts and flags management functions **********************************/ -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); -void FLASH_ClearFlag(uint32_t FLASH_FLAG); -FLASH_Status FLASH_GetStatus(void); -FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); - -/** @defgroup FLASH_Legacy - * @{ - */ -#define FLASH_EraseOptionBytes FLASH_OB_Erase -#define FLASH_EnableWriteProtection FLASH_OB_EnableWRP -#define FLASH_UserOptionByteConfig FLASH_OB_UserConfig -#define FLASH_ProgramOptionByteData FLASH_OB_ProgramData -#define FLASH_GetUserOptionByte FLASH_OB_GetUser -#define FLASH_GetWriteProtectionOptionByte FLASH_OB_GetWRP - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0XX_FLASH_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_gpio.h b/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_gpio.h deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_gpio.h +++ /dev/null @@ -1,360 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_gpio.h - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file contains all the functions prototypes for the GPIO - * firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0XX_GPIO_H -#define __STM32F0XX_GPIO_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup GPIO - * @{ - */ -/* Exported types ------------------------------------------------------------*/ - -#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ - ((PERIPH) == GPIOB) || \ - ((PERIPH) == GPIOC) || \ - ((PERIPH) == GPIOD) || \ - ((PERIPH) == GPIOE) || \ - ((PERIPH) == GPIOF)) - -#define IS_GPIO_LIST_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ - ((PERIPH) == GPIOB)) - -/** @defgroup Configuration_Mode_enumeration - * @{ - */ -typedef enum -{ - GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */ - GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */ - GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */ - GPIO_Mode_AN = 0x03 /*!< GPIO Analog In/Out Mode */ -}GPIOMode_TypeDef; - -#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN)|| ((MODE) == GPIO_Mode_OUT) || \ - ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN)) -/** - * @} - */ - -/** @defgroup Output_type_enumeration - * @{ - */ -typedef enum -{ - GPIO_OType_PP = 0x00, - GPIO_OType_OD = 0x01 -}GPIOOType_TypeDef; - -#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD)) - -/** - * @} - */ - -/** @defgroup Output_Maximum_frequency_enumeration - * @{ - */ -typedef enum -{ - GPIO_Speed_Level_1 = 0x00, /*!< I/O output speed: Low 2 MHz */ - GPIO_Speed_Level_2 = 0x01, /*!< I/O output speed: Medium 10 MHz */ - GPIO_Speed_Level_3 = 0x03 /*!< I/O output speed: High 50 MHz */ -}GPIOSpeed_TypeDef; - -#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_Level_1) || ((SPEED) == GPIO_Speed_Level_2) || \ - ((SPEED) == GPIO_Speed_Level_3)) -/** - * @} - */ - -/** @defgroup Configuration_Pull-Up_Pull-Down_enumeration - * @{ - */ -typedef enum -{ - GPIO_PuPd_NOPULL = 0x00, - GPIO_PuPd_UP = 0x01, - GPIO_PuPd_DOWN = 0x02 -}GPIOPuPd_TypeDef; - -#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \ - ((PUPD) == GPIO_PuPd_DOWN)) -/** - * @} - */ - -/** @defgroup Bit_SET_and_Bit_RESET_enumeration - * @{ - */ -typedef enum -{ - Bit_RESET = 0, - Bit_SET -}BitAction; - -#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) -/** - * @} - */ - -/** - * @brief GPIO Init structure definition - */ -typedef struct -{ - uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured. - This parameter can be any value of @ref GPIO_pins_define */ - - GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. - This parameter can be a value of @ref GPIOMode_TypeDef */ - - GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins. - This parameter can be a value of @ref GPIOSpeed_TypeDef */ - - GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins. - This parameter can be a value of @ref GPIOOType_TypeDef */ - - GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins. - This parameter can be a value of @ref GPIOPuPd_TypeDef */ -}GPIO_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup GPIO_Exported_Constants - * @{ - */ - -/** @defgroup GPIO_pins_define - * @{ - */ -#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */ -#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */ -#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */ -#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */ -#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */ -#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */ -#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */ -#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */ -#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */ -#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */ -#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */ -#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */ -#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */ -#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */ -#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */ -#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */ -#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */ - -#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00) - -#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ - ((PIN) == GPIO_Pin_1) || \ - ((PIN) == GPIO_Pin_2) || \ - ((PIN) == GPIO_Pin_3) || \ - ((PIN) == GPIO_Pin_4) || \ - ((PIN) == GPIO_Pin_5) || \ - ((PIN) == GPIO_Pin_6) || \ - ((PIN) == GPIO_Pin_7) || \ - ((PIN) == GPIO_Pin_8) || \ - ((PIN) == GPIO_Pin_9) || \ - ((PIN) == GPIO_Pin_10) || \ - ((PIN) == GPIO_Pin_11) || \ - ((PIN) == GPIO_Pin_12) || \ - ((PIN) == GPIO_Pin_13) || \ - ((PIN) == GPIO_Pin_14) || \ - ((PIN) == GPIO_Pin_15)) - -/** - * @} - */ - -/** @defgroup GPIO_Pin_sources - * @{ - */ -#define GPIO_PinSource0 ((uint8_t)0x00) -#define GPIO_PinSource1 ((uint8_t)0x01) -#define GPIO_PinSource2 ((uint8_t)0x02) -#define GPIO_PinSource3 ((uint8_t)0x03) -#define GPIO_PinSource4 ((uint8_t)0x04) -#define GPIO_PinSource5 ((uint8_t)0x05) -#define GPIO_PinSource6 ((uint8_t)0x06) -#define GPIO_PinSource7 ((uint8_t)0x07) -#define GPIO_PinSource8 ((uint8_t)0x08) -#define GPIO_PinSource9 ((uint8_t)0x09) -#define GPIO_PinSource10 ((uint8_t)0x0A) -#define GPIO_PinSource11 ((uint8_t)0x0B) -#define GPIO_PinSource12 ((uint8_t)0x0C) -#define GPIO_PinSource13 ((uint8_t)0x0D) -#define GPIO_PinSource14 ((uint8_t)0x0E) -#define GPIO_PinSource15 ((uint8_t)0x0F) - -#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ - ((PINSOURCE) == GPIO_PinSource1) || \ - ((PINSOURCE) == GPIO_PinSource2) || \ - ((PINSOURCE) == GPIO_PinSource3) || \ - ((PINSOURCE) == GPIO_PinSource4) || \ - ((PINSOURCE) == GPIO_PinSource5) || \ - ((PINSOURCE) == GPIO_PinSource6) || \ - ((PINSOURCE) == GPIO_PinSource7) || \ - ((PINSOURCE) == GPIO_PinSource8) || \ - ((PINSOURCE) == GPIO_PinSource9) || \ - ((PINSOURCE) == GPIO_PinSource10) || \ - ((PINSOURCE) == GPIO_PinSource11) || \ - ((PINSOURCE) == GPIO_PinSource12) || \ - ((PINSOURCE) == GPIO_PinSource13) || \ - ((PINSOURCE) == GPIO_PinSource14) || \ - ((PINSOURCE) == GPIO_PinSource15)) -/** - * @} - */ - -/** @defgroup GPIO_Alternate_function_selection_define - * @{ - */ - -/** - * @brief AF 0 selection - */ -#define GPIO_AF_0 ((uint8_t)0x00) /* WKUP, EVENTOUT, TIM15, SPI1, TIM17, - MCO, SWDAT, SWCLK, TIM14, BOOT, - USART1, CEC, IR_OUT, SPI2, TS, TIM3, - USART4, CAN, TIM3, USART2, USART3, - CRS, TIM16, TIM1 */ -/** - * @brief AF 1 selection - */ -#define GPIO_AF_1 ((uint8_t)0x01) /* USART2, CEC, TIM3, USART1, IR, - EVENTOUT, I2C1, I2C2, TIM15, SPI2, - USART3, TS, SPI1 */ -/** - * @brief AF 2 selection - */ -#define GPIO_AF_2 ((uint8_t)0x02) /* TIM2, TIM1, EVENTOUT, TIM16, TIM17, - USB */ -/** - * @brief AF 3 selection - */ -#define GPIO_AF_3 ((uint8_t)0x03) /* TS, I2C1, TIM15, EVENTOUT */ - -/** - * @brief AF 4 selection - */ -#define GPIO_AF_4 ((uint8_t)0x04) /* TIM14, USART4, USART3, CRS, CAN, - I2C1 */ - -/** - * @brief AF 5 selection - */ -#define GPIO_AF_5 ((uint8_t)0x05) /* TIM16, TIM17, TIM15, SPI2, I2C2, - MCO, I2C1, USB */ - -/** - * @brief AF 6 selection - */ -#define GPIO_AF_6 ((uint8_t)0x06) /* EVENTOUT */ -/** - * @brief AF 7 selection - */ -#define GPIO_AF_7 ((uint8_t)0x07) /* COMP1 OUT and COMP2 OUT */ - -#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_0) || ((AF) == GPIO_AF_1) || \ - ((AF) == GPIO_AF_2) || ((AF) == GPIO_AF_3) || \ - ((AF) == GPIO_AF_4) || ((AF) == GPIO_AF_5) || \ - ((AF) == GPIO_AF_6) || ((AF) == GPIO_AF_7)) - -/** - * @} - */ - -/** @defgroup GPIO_Speed_Legacy - * @{ - */ - -#define GPIO_Speed_2MHz GPIO_Speed_Level_1 /*!< I/O output speed: Low 2 MHz */ -#define GPIO_Speed_10MHz GPIO_Speed_Level_2 /*!< I/O output speed: Medium 10 MHz */ -#define GPIO_Speed_50MHz GPIO_Speed_Level_3 /*!< I/O output speed: High 50 MHz */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -/* Function used to set the GPIO configuration to the default reset state *****/ -void GPIO_DeInit(GPIO_TypeDef* GPIOx); - -/* Initialization and Configuration functions *********************************/ -void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); -void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); -void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); - -/* GPIO Read and Write functions **********************************************/ -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); -void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); -void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); - -/* GPIO Alternate functions configuration functions ***************************/ -void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF); - -void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0XX_GPIO_H */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_i2c.h b/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_i2c.h deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_i2c.h +++ /dev/null @@ -1,478 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_i2c.h - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file contains all the functions prototypes for the I2C firmware - * library - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0XX_I2C_H -#define __STM32F0XX_I2C_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup I2C - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief I2C Init structure definition - */ - -typedef struct -{ - uint32_t I2C_Timing; /*!< Specifies the I2C_TIMINGR_register value. - This parameter must be set by referring to I2C_Timing_Config_Tool*/ - - uint32_t I2C_AnalogFilter; /*!< Enables or disables analog noise filter. - This parameter can be a value of @ref I2C_Analog_Filter*/ - - uint32_t I2C_DigitalFilter; /*!< Configures the digital noise filter. - This parameter can be a number between 0x00 and 0x0F*/ - - uint32_t I2C_Mode; /*!< Specifies the I2C mode. - This parameter can be a value of @ref I2C_mode*/ - - uint32_t I2C_OwnAddress1; /*!< Specifies the device own address 1. - This parameter can be a 7-bit or 10-bit address*/ - - uint32_t I2C_Ack; /*!< Enables or disables the acknowledgement. - This parameter can be a value of @ref I2C_acknowledgement*/ - - uint32_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged. - This parameter can be a value of @ref I2C_acknowledged_address*/ -}I2C_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - - -/** @defgroup I2C_Exported_Constants - * @{ - */ - -#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \ - ((PERIPH) == I2C2)) - -#define IS_I2C_1_PERIPH(PERIPH) ((PERIPH) == I2C1) - -/** @defgroup I2C_Analog_Filter - * @{ - */ - -#define I2C_AnalogFilter_Enable ((uint32_t)0x00000000) -#define I2C_AnalogFilter_Disable I2C_CR1_ANFOFF - -#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_AnalogFilter_Enable) || \ - ((FILTER) == I2C_AnalogFilter_Disable)) -/** - * @} - */ - -/** @defgroup I2C_Digital_Filter - * @{ - */ - -#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F) -/** - * @} - */ - -/** @defgroup I2C_mode - * @{ - */ - -#define I2C_Mode_I2C ((uint32_t)0x00000000) -#define I2C_Mode_SMBusDevice I2C_CR1_SMBDEN -#define I2C_Mode_SMBusHost I2C_CR1_SMBHEN - -#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \ - ((MODE) == I2C_Mode_SMBusDevice) || \ - ((MODE) == I2C_Mode_SMBusHost)) -/** - * @} - */ - -/** @defgroup I2C_acknowledgement - * @{ - */ - -#define I2C_Ack_Enable ((uint32_t)0x00000000) -#define I2C_Ack_Disable I2C_CR2_NACK - -#define IS_I2C_ACK(ACK) (((ACK) == I2C_Ack_Enable) || \ - ((ACK) == I2C_Ack_Disable)) -/** - * @} - */ - -/** @defgroup I2C_acknowledged_address - * @{ - */ - -#define I2C_AcknowledgedAddress_7bit ((uint32_t)0x00000000) -#define I2C_AcknowledgedAddress_10bit I2C_OAR1_OA1MODE - -#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \ - ((ADDRESS) == I2C_AcknowledgedAddress_10bit)) -/** - * @} - */ - -/** @defgroup I2C_own_address1 - * @{ - */ - -#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF) -/** - * @} - */ - -/** @defgroup I2C_transfer_direction - * @{ - */ - -#define I2C_Direction_Transmitter ((uint16_t)0x0000) -#define I2C_Direction_Receiver ((uint16_t)0x0400) - -#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \ - ((DIRECTION) == I2C_Direction_Receiver)) -/** - * @} - */ - -/** @defgroup I2C_DMA_transfer_requests - * @{ - */ - -#define I2C_DMAReq_Tx I2C_CR1_TXDMAEN -#define I2C_DMAReq_Rx I2C_CR1_RXDMAEN - -#define IS_I2C_DMA_REQ(REQ) ((((REQ) & (uint32_t)0xFFFF3FFF) == 0x00) && ((REQ) != 0x00)) -/** - * @} - */ - -/** @defgroup I2C_slave_address - * @{ - */ - -#define IS_I2C_SLAVE_ADDRESS(ADDRESS) ((ADDRESS) <= (uint16_t)0x03FF) -/** - * @} - */ - - -/** @defgroup I2C_own_address2 - * @{ - */ - -#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF) - -/** - * @} - */ - -/** @defgroup I2C_own_address2_mask - * @{ - */ - -#define I2C_OA2_NoMask ((uint8_t)0x00) -#define I2C_OA2_Mask01 ((uint8_t)0x01) -#define I2C_OA2_Mask02 ((uint8_t)0x02) -#define I2C_OA2_Mask03 ((uint8_t)0x03) -#define I2C_OA2_Mask04 ((uint8_t)0x04) -#define I2C_OA2_Mask05 ((uint8_t)0x05) -#define I2C_OA2_Mask06 ((uint8_t)0x06) -#define I2C_OA2_Mask07 ((uint8_t)0x07) - -#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NoMask) || \ - ((MASK) == I2C_OA2_Mask01) || \ - ((MASK) == I2C_OA2_Mask02) || \ - ((MASK) == I2C_OA2_Mask03) || \ - ((MASK) == I2C_OA2_Mask04) || \ - ((MASK) == I2C_OA2_Mask05) || \ - ((MASK) == I2C_OA2_Mask06) || \ - ((MASK) == I2C_OA2_Mask07)) - -/** - * @} - */ - -/** @defgroup I2C_timeout - * @{ - */ - -#define IS_I2C_TIMEOUT(TIMEOUT) ((TIMEOUT) <= (uint16_t)0x0FFF) - -/** - * @} - */ - -/** @defgroup I2C_registers - * @{ - */ - -#define I2C_Register_CR1 ((uint8_t)0x00) -#define I2C_Register_CR2 ((uint8_t)0x04) -#define I2C_Register_OAR1 ((uint8_t)0x08) -#define I2C_Register_OAR2 ((uint8_t)0x0C) -#define I2C_Register_TIMINGR ((uint8_t)0x10) -#define I2C_Register_TIMEOUTR ((uint8_t)0x14) -#define I2C_Register_ISR ((uint8_t)0x18) -#define I2C_Register_ICR ((uint8_t)0x1C) -#define I2C_Register_PECR ((uint8_t)0x20) -#define I2C_Register_RXDR ((uint8_t)0x24) -#define I2C_Register_TXDR ((uint8_t)0x28) - -#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \ - ((REGISTER) == I2C_Register_CR2) || \ - ((REGISTER) == I2C_Register_OAR1) || \ - ((REGISTER) == I2C_Register_OAR2) || \ - ((REGISTER) == I2C_Register_TIMINGR) || \ - ((REGISTER) == I2C_Register_TIMEOUTR) || \ - ((REGISTER) == I2C_Register_ISR) || \ - ((REGISTER) == I2C_Register_ICR) || \ - ((REGISTER) == I2C_Register_PECR) || \ - ((REGISTER) == I2C_Register_RXDR) || \ - ((REGISTER) == I2C_Register_TXDR)) -/** - * @} - */ - -/** @defgroup I2C_interrupts_definition - * @{ - */ - -#define I2C_IT_ERRI I2C_CR1_ERRIE -#define I2C_IT_TCI I2C_CR1_TCIE -#define I2C_IT_STOPI I2C_CR1_STOPIE -#define I2C_IT_NACKI I2C_CR1_NACKIE -#define I2C_IT_ADDRI I2C_CR1_ADDRIE -#define I2C_IT_RXI I2C_CR1_RXIE -#define I2C_IT_TXI I2C_CR1_TXIE - -#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint32_t)0xFFFFFF01) == 0x00) && ((IT) != 0x00)) - -/** - * @} - */ - -/** @defgroup I2C_flags_definition - * @{ - */ - -#define I2C_FLAG_TXE I2C_ISR_TXE -#define I2C_FLAG_TXIS I2C_ISR_TXIS -#define I2C_FLAG_RXNE I2C_ISR_RXNE -#define I2C_FLAG_ADDR I2C_ISR_ADDR -#define I2C_FLAG_NACKF I2C_ISR_NACKF -#define I2C_FLAG_STOPF I2C_ISR_STOPF -#define I2C_FLAG_TC I2C_ISR_TC -#define I2C_FLAG_TCR I2C_ISR_TCR -#define I2C_FLAG_BERR I2C_ISR_BERR -#define I2C_FLAG_ARLO I2C_ISR_ARLO -#define I2C_FLAG_OVR I2C_ISR_OVR -#define I2C_FLAG_PECERR I2C_ISR_PECERR -#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT -#define I2C_FLAG_ALERT I2C_ISR_ALERT -#define I2C_FLAG_BUSY I2C_ISR_BUSY - -#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFF4000) == 0x00) && ((FLAG) != 0x00)) - -#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_TXIS) || \ - ((FLAG) == I2C_FLAG_RXNE) || ((FLAG) == I2C_FLAG_ADDR) || \ - ((FLAG) == I2C_FLAG_NACKF) || ((FLAG) == I2C_FLAG_STOPF) || \ - ((FLAG) == I2C_FLAG_TC) || ((FLAG) == I2C_FLAG_TCR) || \ - ((FLAG) == I2C_FLAG_BERR) || ((FLAG) == I2C_FLAG_ARLO) || \ - ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_PECERR) || \ - ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_ALERT) || \ - ((FLAG) == I2C_FLAG_BUSY)) - -/** - * @} - */ - - -/** @defgroup I2C_interrupts_definition - * @{ - */ - -#define I2C_IT_TXIS I2C_ISR_TXIS -#define I2C_IT_RXNE I2C_ISR_RXNE -#define I2C_IT_ADDR I2C_ISR_ADDR -#define I2C_IT_NACKF I2C_ISR_NACKF -#define I2C_IT_STOPF I2C_ISR_STOPF -#define I2C_IT_TC I2C_ISR_TC -#define I2C_IT_TCR I2C_ISR_TCR -#define I2C_IT_BERR I2C_ISR_BERR -#define I2C_IT_ARLO I2C_ISR_ARLO -#define I2C_IT_OVR I2C_ISR_OVR -#define I2C_IT_PECERR I2C_ISR_PECERR -#define I2C_IT_TIMEOUT I2C_ISR_TIMEOUT -#define I2C_IT_ALERT I2C_ISR_ALERT - -#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFFFFC001) == 0x00) && ((IT) != 0x00)) - -#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_TXIS) || ((IT) == I2C_IT_RXNE) || \ - ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_NACKF) || \ - ((IT) == I2C_IT_STOPF) || ((IT) == I2C_IT_TC) || \ - ((IT) == I2C_IT_TCR) || ((IT) == I2C_IT_BERR) || \ - ((IT) == I2C_IT_ARLO) || ((IT) == I2C_IT_OVR) || \ - ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_TIMEOUT) || \ - ((IT) == I2C_IT_ALERT)) - - -/** - * @} - */ - -/** @defgroup I2C_ReloadEndMode_definition - * @{ - */ - -#define I2C_Reload_Mode I2C_CR2_RELOAD -#define I2C_AutoEnd_Mode I2C_CR2_AUTOEND -#define I2C_SoftEnd_Mode ((uint32_t)0x00000000) - - -#define IS_RELOAD_END_MODE(MODE) (((MODE) == I2C_Reload_Mode) || \ - ((MODE) == I2C_AutoEnd_Mode) || \ - ((MODE) == I2C_SoftEnd_Mode)) - - -/** - * @} - */ - -/** @defgroup I2C_StartStopMode_definition - * @{ - */ - -#define I2C_No_StartStop ((uint32_t)0x00000000) -#define I2C_Generate_Stop I2C_CR2_STOP -#define I2C_Generate_Start_Read (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) -#define I2C_Generate_Start_Write I2C_CR2_START - - -#define IS_START_STOP_MODE(MODE) (((MODE) == I2C_Generate_Stop) || \ - ((MODE) == I2C_Generate_Start_Read) || \ - ((MODE) == I2C_Generate_Start_Write) || \ - ((MODE) == I2C_No_StartStop)) - - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - - -/* Initialization and Configuration functions *********************************/ -void I2C_DeInit(I2C_TypeDef* I2Cx); -void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); -void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); -void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx); -void I2C_ITConfig(I2C_TypeDef* I2Cx, uint32_t I2C_IT, FunctionalState NewState); -void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_StopModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); /*!< not applicable for STM32F030 devices */ -void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Mask); -void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_SlaveByteControlCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_SlaveAddressConfig(I2C_TypeDef* I2Cx, uint16_t Address); -void I2C_10BitAddressingModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); - -/* Communications handling functions ******************************************/ -void I2C_AutoEndCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_ReloadCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_NumberOfBytesConfig(I2C_TypeDef* I2Cx, uint8_t Number_Bytes); -void I2C_MasterRequestConfig(I2C_TypeDef* I2Cx, uint16_t I2C_Direction); -void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_10BitAddressHeaderCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); -uint8_t I2C_GetAddressMatched(I2C_TypeDef* I2Cx); -uint16_t I2C_GetTransferDirection(I2C_TypeDef* I2Cx); -void I2C_TransferHandling(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode); - -/* SMBUS management functions ************************************************/ -void I2C_SMBusAlertCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_ClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_ExtendedClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_IdleClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_TimeoutAConfig(I2C_TypeDef* I2Cx, uint16_t Timeout); -void I2C_TimeoutBConfig(I2C_TypeDef* I2Cx, uint16_t Timeout); -void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_PECRequestCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); - -/* I2C registers management functions *****************************************/ -uint32_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); - -/* Data transfers management functions ****************************************/ -void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); -uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); - -/* DMA transfers management functions *****************************************/ -void I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); -void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); -ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); -void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); - - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F0XX_I2C_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_iwdg.h b/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_iwdg.h deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_iwdg.h +++ /dev/null @@ -1,140 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_iwdg.h - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file contains all the functions prototypes for the IWDG - * firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0XX_IWDG_H -#define __STM32F0XX_IWDG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup IWDG - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup IWDG_Exported_Constants - * @{ - */ - -/** @defgroup IWDG_WriteAccess - * @{ - */ - -#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) -#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) -#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ - ((ACCESS) == IWDG_WriteAccess_Disable)) -/** - * @} - */ - -/** @defgroup IWDG_prescaler - * @{ - */ - -#define IWDG_Prescaler_4 ((uint8_t)0x00) -#define IWDG_Prescaler_8 ((uint8_t)0x01) -#define IWDG_Prescaler_16 ((uint8_t)0x02) -#define IWDG_Prescaler_32 ((uint8_t)0x03) -#define IWDG_Prescaler_64 ((uint8_t)0x04) -#define IWDG_Prescaler_128 ((uint8_t)0x05) -#define IWDG_Prescaler_256 ((uint8_t)0x06) -#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ - ((PRESCALER) == IWDG_Prescaler_8) || \ - ((PRESCALER) == IWDG_Prescaler_16) || \ - ((PRESCALER) == IWDG_Prescaler_32) || \ - ((PRESCALER) == IWDG_Prescaler_64) || \ - ((PRESCALER) == IWDG_Prescaler_128)|| \ - ((PRESCALER) == IWDG_Prescaler_256)) -/** - * @} - */ - -/** @defgroup IWDG_Flag - * @{ - */ - -#define IWDG_FLAG_PVU IWDG_SR_PVU -#define IWDG_FLAG_RVU IWDG_SR_RVU -#define IWDG_FLAG_WVU IWDG_SR_WVU -#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU) || \ - ((FLAG) == IWDG_FLAG_WVU)) - -#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) - -#define IS_IWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0xFFF) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Prescaler and Counter configuration functions ******************************/ -void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); -void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); -void IWDG_SetReload(uint16_t Reload); -void IWDG_ReloadCounter(void); -void IWDG_SetWindowValue(uint16_t WindowValue); - -/* IWDG activation function ***************************************************/ -void IWDG_Enable(void); - -/* Flag management function ***************************************************/ -FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0XX_IWDG_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_misc.h b/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_misc.h deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_misc.h +++ /dev/null @@ -1,143 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_misc.h - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file contains all the functions prototypes for the miscellaneous - * firmware library functions (add-on to CMSIS functions). - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0XX_MISC_H -#define __STM32F0XX_MISC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup MISC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief NVIC Init Structure definition - */ - -typedef struct -{ - uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. - This parameter can be a value of @ref IRQn_Type - (For the complete STM32 Devices IRQ Channels list, - please refer to stm32f0xx.h file) */ - - uint8_t NVIC_IRQChannelPriority; /*!< Specifies the priority level for the IRQ channel specified - in NVIC_IRQChannel. This parameter can be a value - between 0 and 3. */ - - FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel - will be enabled or disabled. - This parameter can be set either to ENABLE or DISABLE */ -} NVIC_InitTypeDef; - -/** - * -@verbatim - -@endverbatim -*/ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup MISC_Exported_Constants - * @{ - */ - -/** @defgroup MISC_System_Low_Power - * @{ - */ - -#define NVIC_LP_SEVONPEND ((uint8_t)0x10) -#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) -#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) -#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ - ((LP) == NVIC_LP_SLEEPDEEP) || \ - ((LP) == NVIC_LP_SLEEPONEXIT)) -/** - * @} - */ - -/** @defgroup MISC_Preemption_Priority_Group - * @{ - */ -#define IS_NVIC_PRIORITY(PRIORITY) ((PRIORITY) < 0x04) - -/** - * @} - */ - -/** @defgroup MISC_SysTick_clock_source - * @{ - */ - -#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) -#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) -#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ - ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); -void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); -void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0XX_MISC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_pwr.h b/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_pwr.h deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_pwr.h +++ /dev/null @@ -1,197 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_pwr.h - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file contains all the functions prototypes for the PWR firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0XX_PWR_H -#define __STM32F0XX_PWR_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup PWR - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup PWR_Exported_Constants - * @{ - */ - -/** @defgroup PWR_PVD_detection_level - * @brief This parameters are only applicable for STM32F051 and STM32F072 devices - * @{ - */ - -#define PWR_PVDLevel_0 PWR_CR_PLS_LEV0 -#define PWR_PVDLevel_1 PWR_CR_PLS_LEV1 -#define PWR_PVDLevel_2 PWR_CR_PLS_LEV2 -#define PWR_PVDLevel_3 PWR_CR_PLS_LEV3 -#define PWR_PVDLevel_4 PWR_CR_PLS_LEV4 -#define PWR_PVDLevel_5 PWR_CR_PLS_LEV5 -#define PWR_PVDLevel_6 PWR_CR_PLS_LEV6 -#define PWR_PVDLevel_7 PWR_CR_PLS_LEV7 - -#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \ - ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \ - ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \ - ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7)) -/** - * @} - */ - -/** @defgroup PWR_WakeUp_Pins - * @{ - */ - -#define PWR_WakeUpPin_1 PWR_CSR_EWUP1 -#define PWR_WakeUpPin_2 PWR_CSR_EWUP2 -#define PWR_WakeUpPin_3 PWR_CSR_EWUP3 /*!< only applicable for STM32F072 devices */ -#define PWR_WakeUpPin_4 PWR_CSR_EWUP4 /*!< only applicable for STM32F072 devices */ -#define PWR_WakeUpPin_5 PWR_CSR_EWUP5 /*!< only applicable for STM32F072 devices */ -#define PWR_WakeUpPin_6 PWR_CSR_EWUP6 /*!< only applicable for STM32F072 devices */ -#define PWR_WakeUpPin_7 PWR_CSR_EWUP7 /*!< only applicable for STM32F072 devices */ -#define PWR_WakeUpPin_8 PWR_CSR_EWUP8 /*!< only applicable for STM32F072 devices */ -#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUpPin_1) || ((PIN) == PWR_WakeUpPin_2) || \ - ((PIN) == PWR_WakeUpPin_3) || ((PIN) == PWR_WakeUpPin_4) || \ - ((PIN) == PWR_WakeUpPin_5) || ((PIN) == PWR_WakeUpPin_6) || \ - ((PIN) == PWR_WakeUpPin_7) || ((PIN) == PWR_WakeUpPin_8)) -/** - * @} - */ - - -/** @defgroup PWR_Regulator_state_is_Sleep_STOP_mode - * @{ - */ - -#define PWR_Regulator_ON ((uint32_t)0x00000000) -#define PWR_Regulator_LowPower PWR_CR_LPSDSR -#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \ - ((REGULATOR) == PWR_Regulator_LowPower)) -/** - * @} - */ - -/** @defgroup PWR_SLEEP_mode_entry - * @{ - */ - -#define PWR_SLEEPEntry_WFI ((uint8_t)0x01) -#define PWR_SLEEPEntry_WFE ((uint8_t)0x02) -#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE)) - -/** - * @} - */ - -/** @defgroup PWR_STOP_mode_entry - * @{ - */ - -#define PWR_STOPEntry_WFI ((uint8_t)0x01) -#define PWR_STOPEntry_WFE ((uint8_t)0x02) -#define PWR_STOPEntry_SLEEPONEXIT ((uint8_t)0x03) -#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE) ||\ - ((ENTRY) == PWR_STOPEntry_SLEEPONEXIT)) - -/** - * @} - */ - -/** @defgroup PWR_Flag - * @{ - */ - -#define PWR_FLAG_WU PWR_CSR_WUF -#define PWR_FLAG_SB PWR_CSR_SBF -#define PWR_FLAG_PVDO PWR_CSR_PVDO /*!< Not applicable for STM32F030 devices */ -#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF - -#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ - ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY)) - -#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Function used to set the PWR configuration to the default reset state ******/ -void PWR_DeInit(void); - -/* Backup Domain Access function **********************************************/ -void PWR_BackupAccessCmd(FunctionalState NewState); - -/* PVD configuration functions ************************************************/ -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); /*!< only applicable for STM32F051 and STM32F072 devices */ -void PWR_PVDCmd(FunctionalState NewState); /*!< only applicable for STM32F051 and STM32F072 devices */ - -/* WakeUp pins configuration functions ****************************************/ -void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState); - -/* Low Power modes configuration functions ************************************/ -void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry); -void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); -void PWR_EnterSTANDBYMode(void); - -/* Flags management functions *************************************************/ -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); -void PWR_ClearFlag(uint32_t PWR_FLAG); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0XX_PWR_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_rcc.h b/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_rcc.h deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_rcc.h +++ /dev/null @@ -1,624 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_rcc.h - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file contains all the functions prototypes for the RCC - * firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0XX_RCC_H -#define __STM32F0XX_RCC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup RCC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -typedef struct -{ - uint32_t SYSCLK_Frequency; - uint32_t HCLK_Frequency; - uint32_t PCLK_Frequency; - uint32_t ADCCLK_Frequency; - uint32_t CECCLK_Frequency; - uint32_t I2C1CLK_Frequency; - uint32_t USART1CLK_Frequency; - uint32_t USART2CLK_Frequency; /*!< Only applicable for STM32F072 and STM32F091 devices */ - uint32_t USART3CLK_Frequency; /*!< Only applicable for STM32F091 devices */ - uint32_t USBCLK_Frequency; /*!< Only applicable for STM32F072 devices */ -}RCC_ClocksTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup RCC_Exported_Constants - * @{ - */ - -/** @defgroup RCC_HSE_configuration - * @{ - */ - -#define RCC_HSE_OFF ((uint8_t)0x00) -#define RCC_HSE_ON ((uint8_t)0x01) -#define RCC_HSE_Bypass ((uint8_t)0x05) -#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ - ((HSE) == RCC_HSE_Bypass)) - -/** - * @} - */ - -/** @defgroup RCC_PLL_Clock_Source - * @{ - */ - -#define RCC_PLLSource_HSI_Div2 RCC_CFGR_PLLSRC_HSI_Div2 -#define RCC_PLLSource_PREDIV1 RCC_CFGR_PLLSRC_HSE_PREDIV /* Old HSEPREDIV1 bit definition, maintained for legacy purpose */ -#define RCC_PLLSource_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< Only applicable for STM32F072 devices */ -#define RCC_PLLSource_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV /*!< Only applicable for STM32F072 devices */ -#define RCC_PLLSource_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /*!< Only applicable for STM32F072 devices */ - -#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ - ((SOURCE) == RCC_PLLSource_HSI48) || \ - ((SOURCE) == RCC_PLLSource_HSI) || \ - ((SOURCE) == RCC_PLLSource_HSE) || \ - ((SOURCE) == RCC_PLLSource_PREDIV1)) -/** - * @} - */ - -/** @defgroup RCC_PLL_Multiplication_Factor - * @{ - */ - -#define RCC_PLLMul_2 RCC_CFGR_PLLMULL2 -#define RCC_PLLMul_3 RCC_CFGR_PLLMULL3 -#define RCC_PLLMul_4 RCC_CFGR_PLLMULL4 -#define RCC_PLLMul_5 RCC_CFGR_PLLMULL5 -#define RCC_PLLMul_6 RCC_CFGR_PLLMULL6 -#define RCC_PLLMul_7 RCC_CFGR_PLLMULL7 -#define RCC_PLLMul_8 RCC_CFGR_PLLMULL8 -#define RCC_PLLMul_9 RCC_CFGR_PLLMULL9 -#define RCC_PLLMul_10 RCC_CFGR_PLLMULL10 -#define RCC_PLLMul_11 RCC_CFGR_PLLMULL11 -#define RCC_PLLMul_12 RCC_CFGR_PLLMULL12 -#define RCC_PLLMul_13 RCC_CFGR_PLLMULL13 -#define RCC_PLLMul_14 RCC_CFGR_PLLMULL14 -#define RCC_PLLMul_15 RCC_CFGR_PLLMULL15 -#define RCC_PLLMul_16 RCC_CFGR_PLLMULL16 -#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \ - ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ - ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ - ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ - ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ - ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ - ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ - ((MUL) == RCC_PLLMul_16)) -/** - * @} - */ - -/** @defgroup RCC_PREDIV1_division_factor - * @{ - */ -#define RCC_PREDIV1_Div1 RCC_CFGR2_PREDIV1_DIV1 -#define RCC_PREDIV1_Div2 RCC_CFGR2_PREDIV1_DIV2 -#define RCC_PREDIV1_Div3 RCC_CFGR2_PREDIV1_DIV3 -#define RCC_PREDIV1_Div4 RCC_CFGR2_PREDIV1_DIV4 -#define RCC_PREDIV1_Div5 RCC_CFGR2_PREDIV1_DIV5 -#define RCC_PREDIV1_Div6 RCC_CFGR2_PREDIV1_DIV6 -#define RCC_PREDIV1_Div7 RCC_CFGR2_PREDIV1_DIV7 -#define RCC_PREDIV1_Div8 RCC_CFGR2_PREDIV1_DIV8 -#define RCC_PREDIV1_Div9 RCC_CFGR2_PREDIV1_DIV9 -#define RCC_PREDIV1_Div10 RCC_CFGR2_PREDIV1_DIV10 -#define RCC_PREDIV1_Div11 RCC_CFGR2_PREDIV1_DIV11 -#define RCC_PREDIV1_Div12 RCC_CFGR2_PREDIV1_DIV12 -#define RCC_PREDIV1_Div13 RCC_CFGR2_PREDIV1_DIV13 -#define RCC_PREDIV1_Div14 RCC_CFGR2_PREDIV1_DIV14 -#define RCC_PREDIV1_Div15 RCC_CFGR2_PREDIV1_DIV15 -#define RCC_PREDIV1_Div16 RCC_CFGR2_PREDIV1_DIV16 - -#define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \ - ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \ - ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \ - ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \ - ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \ - ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \ - ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \ - ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16)) -/** - * @} - */ - -/** @defgroup RCC_System_Clock_Source - * @{ - */ - -#define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI -#define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE -#define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL -#define RCC_SYSCLKSource_HSI48 RCC_CFGR_SW_HSI48 /*!< Only applicable for STM32F072 devices */ - -#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ - ((SOURCE) == RCC_SYSCLKSource_HSE) || \ - ((SOURCE) == RCC_SYSCLKSource_HSI48) || \ - ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) -/** - * @} - */ - -/** @defgroup RCC_AHB_Clock_Source - * @{ - */ - -#define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1 -#define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2 -#define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4 -#define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8 -#define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16 -#define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64 -#define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128 -#define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256 -#define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512 -#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ - ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ - ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ - ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ - ((HCLK) == RCC_SYSCLK_Div512)) -/** - * @} - */ - -/** @defgroup RCC_APB_Clock_Source - * @{ - */ - -#define RCC_HCLK_Div1 RCC_CFGR_PPRE_DIV1 -#define RCC_HCLK_Div2 RCC_CFGR_PPRE_DIV2 -#define RCC_HCLK_Div4 RCC_CFGR_PPRE_DIV4 -#define RCC_HCLK_Div8 RCC_CFGR_PPRE_DIV8 -#define RCC_HCLK_Div16 RCC_CFGR_PPRE_DIV16 -#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ - ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ - ((PCLK) == RCC_HCLK_Div16)) -/** - * @} - */ - -/** @defgroup RCC_ADC_clock_source - * @{ - */ -/* These defines are obsolete and kept for legacy purpose only. -Proper ADC clock selection is done within ADC driver by mean of the ADC_ClockModeConfig() function */ -#define RCC_ADCCLK_HSI14 ((uint32_t)0x00000000) -#define RCC_ADCCLK_PCLK_Div2 ((uint32_t)0x01000000) -#define RCC_ADCCLK_PCLK_Div4 ((uint32_t)0x01004000) - -#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_ADCCLK_HSI14) || ((ADCCLK) == RCC_ADCCLK_PCLK_Div2) || \ - ((ADCCLK) == RCC_ADCCLK_PCLK_Div4)) - -/** - * @} - */ - -/** @defgroup RCC_CEC_clock_source - * @{ - */ - -#define RCC_CECCLK_HSI_Div244 ((uint32_t)0x00000000) -#define RCC_CECCLK_LSE RCC_CFGR3_CECSW - -#define IS_RCC_CECCLK(CECCLK) (((CECCLK) == RCC_CECCLK_HSI_Div244) || ((CECCLK) == RCC_CECCLK_LSE)) - -/** - * @} - */ - -/** @defgroup RCC_I2C_clock_source - * @{ - */ - -#define RCC_I2C1CLK_HSI ((uint32_t)0x00000000) -#define RCC_I2C1CLK_SYSCLK RCC_CFGR3_I2C1SW - -#define IS_RCC_I2CCLK(I2CCLK) (((I2CCLK) == RCC_I2C1CLK_HSI) || ((I2CCLK) == RCC_I2C1CLK_SYSCLK)) - -/** - * @} - */ - -/** @defgroup RCC_USB_clock_source - * @brief Applicable only for STM32F072 devices - * @{ - */ - -#define RCC_USBCLK_HSI48 ((uint32_t)0x00000000) -#define RCC_USBCLK_PLLCLK RCC_CFGR3_USBSW - -#define IS_RCC_USBCLK(USBCLK) (((USBCLK) == RCC_USBCLK_HSI48) || ((USBCLK) == RCC_USBCLK_PLLCLK)) - -/** - * @} - */ - -/** @defgroup RCC_USART_clock_source - * @{ - */ - -#define RCC_USART1CLK_PCLK ((uint32_t)0x10000000) -#define RCC_USART1CLK_SYSCLK ((uint32_t)0x10000001) -#define RCC_USART1CLK_LSE ((uint32_t)0x10000002) -#define RCC_USART1CLK_HSI ((uint32_t)0x10000003) - -#define RCC_USART2CLK_PCLK ((uint32_t)0x20000000) /*!< Only applicable for STM32F072 and STM32F091 devices */ -#define RCC_USART2CLK_SYSCLK ((uint32_t)0x20010000) /*!< Only applicable for STM32F072 and STM32F091 devices */ -#define RCC_USART2CLK_LSE ((uint32_t)0x20020000) /*!< Only applicable for STM32F072 and STM32F091 devices */ -#define RCC_USART2CLK_HSI ((uint32_t)0x20030000) /*!< Only applicable for STM32F072 and STM32F091 devices */ - -#define RCC_USART3CLK_PCLK ((uint32_t)0x30000000) /*!< Only applicable for STM32F091 devices */ -#define RCC_USART3CLK_SYSCLK ((uint32_t)0x30040000) /*!< Only applicable for STM32F091 devices */ -#define RCC_USART3CLK_LSE ((uint32_t)0x30080000) /*!< Only applicable for STM32F091 devices */ -#define RCC_USART3CLK_HSI ((uint32_t)0x300C0000) /*!< Only applicable for STM32F091 devices */ - - -#define IS_RCC_USARTCLK(USARTCLK) (((USARTCLK) == RCC_USART1CLK_PCLK) || \ - ((USARTCLK) == RCC_USART1CLK_SYSCLK) || \ - ((USARTCLK) == RCC_USART1CLK_LSE) || \ - ((USARTCLK) == RCC_USART1CLK_HSI) || \ - ((USARTCLK) == RCC_USART2CLK_PCLK) || \ - ((USARTCLK) == RCC_USART2CLK_SYSCLK) || \ - ((USARTCLK) == RCC_USART2CLK_LSE) || \ - ((USARTCLK) == RCC_USART2CLK_HSI)|| \ - ((USARTCLK) == RCC_USART3CLK_PCLK) || \ - ((USARTCLK) == RCC_USART3CLK_SYSCLK) || \ - ((USARTCLK) == RCC_USART3CLK_LSE) || \ - ((USARTCLK) == RCC_USART3CLK_HSI)) - -/** - * @} - */ - -/** @defgroup RCC_Interrupt_Source - * @{ - */ - -#define RCC_IT_LSIRDY ((uint8_t)0x01) -#define RCC_IT_LSERDY ((uint8_t)0x02) -#define RCC_IT_HSIRDY ((uint8_t)0x04) -#define RCC_IT_HSERDY ((uint8_t)0x08) -#define RCC_IT_PLLRDY ((uint8_t)0x10) -#define RCC_IT_HSI14RDY ((uint8_t)0x20) -#define RCC_IT_HSI48RDY ((uint8_t)0x40) /*!< Only applicable for STM32F072 devices */ -#define RCC_IT_CSS ((uint8_t)0x80) - -#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00)) - -#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ - ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ - ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_HSI14RDY) || \ - ((IT) == RCC_IT_CSS) || ((IT) == RCC_IT_HSI48RDY)) - -#define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00) - -/** - * @} - */ - -/** @defgroup RCC_LSE_Configuration - * @{ - */ - -#define RCC_LSE_OFF ((uint32_t)0x00000000) -#define RCC_LSE_ON RCC_BDCR_LSEON -#define RCC_LSE_Bypass ((uint32_t)(RCC_BDCR_LSEON | RCC_BDCR_LSEBYP)) -#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ - ((LSE) == RCC_LSE_Bypass)) -/** - * @} - */ - -/** @defgroup RCC_RTC_Clock_Source - * @{ - */ - -#define RCC_RTCCLKSource_LSE RCC_BDCR_RTCSEL_LSE -#define RCC_RTCCLKSource_LSI RCC_BDCR_RTCSEL_LSI -#define RCC_RTCCLKSource_HSE_Div32 RCC_BDCR_RTCSEL_HSE - -#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ - ((SOURCE) == RCC_RTCCLKSource_LSI) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div32)) -/** - * @} - */ - -/** @defgroup RCC_LSE_Drive_Configuration - * @{ - */ - -#define RCC_LSEDrive_Low ((uint32_t)0x00000000) -#define RCC_LSEDrive_MediumLow RCC_BDCR_LSEDRV_0 -#define RCC_LSEDrive_MediumHigh RCC_BDCR_LSEDRV_1 -#define RCC_LSEDrive_High RCC_BDCR_LSEDRV -#define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDrive_Low) || ((DRIVE) == RCC_LSEDrive_MediumLow) || \ - ((DRIVE) == RCC_LSEDrive_MediumHigh) || ((DRIVE) == RCC_LSEDrive_High)) -/** - * @} - */ - -/** @defgroup RCC_AHB_Peripherals - * @{ - */ - -#define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN -#define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN -#define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN -#define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN -#define RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN /*!< Only applicable for STM32F072 and STM32F091 devices */ -#define RCC_AHBPeriph_GPIOF RCC_AHBENR_GPIOFEN -#define RCC_AHBPeriph_TS RCC_AHBENR_TSEN -#define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN -#define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN -#define RCC_AHBPeriph_SRAM RCC_AHBENR_SRAMEN -#define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN -#define RCC_AHBPeriph_DMA2 RCC_AHBENR_DMA2EN - -#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFE81FFA8) == 0x00) && ((PERIPH) != 0x00)) -#define IS_RCC_AHB_RST_PERIPH(PERIPH) ((((PERIPH) & 0xFE81FFA8) == 0x00) && ((PERIPH) != 0x00)) - -/** - * @} - */ - -/** @defgroup RCC_APB2_Peripherals - * @{ - */ - -#define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN -#define RCC_APB2Periph_USART6 RCC_APB2ENR_USART6EN -#define RCC_APB2Periph_USART7 RCC_APB2ENR_USART7EN -#define RCC_APB2Periph_USART8 RCC_APB2ENR_USART8EN -#define RCC_APB2Periph_ADC1 RCC_APB2ENR_ADC1EN -#define RCC_APB2Periph_TIM1 RCC_APB2ENR_TIM1EN -#define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN -#define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN -#define RCC_APB2Periph_TIM15 RCC_APB2ENR_TIM15EN -#define RCC_APB2Periph_TIM16 RCC_APB2ENR_TIM16EN -#define RCC_APB2Periph_TIM17 RCC_APB2ENR_TIM17EN -#define RCC_APB2Periph_DBGMCU RCC_APB2ENR_DBGMCUEN - -#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFB8A51E) == 0x00) && ((PERIPH) != 0x00)) - -/** - * @} - */ - -/** @defgroup RCC_APB1_Peripherals - * @{ - */ - -#define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN /*!< Only applicable for STM32F051, STM32F072 and STM32F091 devices */ -#define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN -#define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN -#define RCC_APB1Periph_TIM7 RCC_APB1ENR_TIM7EN /*!< Only applicable for STM32F072 devices */ -#define RCC_APB1Periph_TIM14 RCC_APB1ENR_TIM14EN -#define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN -#define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN -#define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN -#define RCC_APB1Periph_USART3 RCC_APB1ENR_USART3EN /*!< Only applicable for STM32F072 and STM32F091 devices */ -#define RCC_APB1Periph_USART4 RCC_APB1ENR_USART4EN /*!< Only applicable for STM32F072 and STM32F091 devices */ -#define RCC_APB1Periph_USART5 RCC_APB1ENR_USART5EN /*!< Only applicable for STM32F091 devices */ -#define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN -#define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN -#define RCC_APB1Periph_USB RCC_APB1ENR_USBEN /*!< Only applicable for STM32F072 and STM32F042 devices */ -#define RCC_APB1Periph_CAN RCC_APB1ENR_CANEN /*!< Only applicable for STM32F072, STM32F042 and STM32F091 devices */ -#define RCC_APB1Periph_CRS RCC_APB1ENR_CRSEN /*!< Only applicable for STM32F072, STM32F042 and STM32F091 devices */ -#define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN -#define RCC_APB1Periph_DAC RCC_APB1ENR_DACEN /*!< Only applicable for STM32F051, STM32F072 and STM32F091 devices */ -#define RCC_APB1Periph_CEC RCC_APB1ENR_CECEN /*!< Only applicable for STM32F051, STM32F042, STM32F072 and STM32F091 devices */ - -#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x8581B6CC) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/** @defgroup RCC_MCO_Clock_Source - * @{ - */ - -#define RCC_MCOSource_NoClock ((uint8_t)0x00) -#define RCC_MCOSource_HSI14 ((uint8_t)0x01) -#define RCC_MCOSource_LSI ((uint8_t)0x02) -#define RCC_MCOSource_LSE ((uint8_t)0x03) -#define RCC_MCOSource_SYSCLK ((uint8_t)0x04) -#define RCC_MCOSource_HSI ((uint8_t)0x05) -#define RCC_MCOSource_HSE ((uint8_t)0x06) -#define RCC_MCOSource_PLLCLK_Div2 ((uint8_t)0x07) -#define RCC_MCOSource_HSI48 ((uint8_t)0x08) /*!< Only applicable for STM32F072 devices */ -#define RCC_MCOSource_PLLCLK ((uint8_t)0x87) - -#define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) || ((SOURCE) == RCC_MCOSource_HSI14) || \ - ((SOURCE) == RCC_MCOSource_SYSCLK) || ((SOURCE) == RCC_MCOSource_HSI) || \ - ((SOURCE) == RCC_MCOSource_HSE) || ((SOURCE) == RCC_MCOSource_PLLCLK_Div2)|| \ - ((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_HSI48) || \ - ((SOURCE) == RCC_MCOSource_PLLCLK) || ((SOURCE) == RCC_MCOSource_LSE)) -/** - * @} - */ - -/** @defgroup RCC_MCOPrescaler - * @{ - */ -#if !defined (STM32F051) -#define RCC_MCOPrescaler_1 RCC_CFGR_MCO_PRE_1 -#define RCC_MCOPrescaler_2 RCC_CFGR_MCO_PRE_2 -#define RCC_MCOPrescaler_4 RCC_CFGR_MCO_PRE_4 -#define RCC_MCOPrescaler_8 RCC_CFGR_MCO_PRE_8 -#define RCC_MCOPrescaler_16 RCC_CFGR_MCO_PRE_16 -#define RCC_MCOPrescaler_32 RCC_CFGR_MCO_PRE_32 -#define RCC_MCOPrescaler_64 RCC_CFGR_MCO_PRE_64 -#define RCC_MCOPrescaler_128 RCC_CFGR_MCO_PRE_128 - -#define IS_RCC_MCO_PRESCALER(PRESCALER) (((PRESCALER) == RCC_MCOPrescaler_1) || \ - ((PRESCALER) == RCC_MCOPrescaler_2) || \ - ((PRESCALER) == RCC_MCOPrescaler_4) || \ - ((PRESCALER) == RCC_MCOPrescaler_8) || \ - ((PRESCALER) == RCC_MCOPrescaler_16) || \ - ((PRESCALER) == RCC_MCOPrescaler_32) || \ - ((PRESCALER) == RCC_MCOPrescaler_64) || \ - ((PRESCALER) == RCC_MCOPrescaler_128)) -#endif /* STM32F051 */ -/** - * @} - */ - -/** @defgroup RCC_Flag - * @{ - */ -#define RCC_FLAG_HSIRDY ((uint8_t)0x01) -#define RCC_FLAG_HSERDY ((uint8_t)0x11) -#define RCC_FLAG_PLLRDY ((uint8_t)0x19) -#define RCC_FLAG_LSERDY ((uint8_t)0x21) -#define RCC_FLAG_LSIRDY ((uint8_t)0x41) -#define RCC_FLAG_V18PWRRSTF ((uint8_t)0x57) -#define RCC_FLAG_OBLRST ((uint8_t)0x59) -#define RCC_FLAG_PINRST ((uint8_t)0x5A) -#define RCC_FLAG_PORRST ((uint8_t)0x5B) -#define RCC_FLAG_SFTRST ((uint8_t)0x5C) -#define RCC_FLAG_IWDGRST ((uint8_t)0x5D) -#define RCC_FLAG_WWDGRST ((uint8_t)0x5E) -#define RCC_FLAG_LPWRRST ((uint8_t)0x5F) -#define RCC_FLAG_HSI14RDY ((uint8_t)0x61) -#define RCC_FLAG_HSI48RDY ((uint8_t)0x71) /*!< Only applicable for STM32F072 devices */ - -#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ - ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ - ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_OBLRST) || \ - ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ - ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST) || \ - ((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST) || \ - ((FLAG) == RCC_FLAG_HSI14RDY)|| ((FLAG) == RCC_FLAG_HSI48RDY)|| \ - ((FLAG) == RCC_FLAG_V18PWRRSTF)) - -#define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) -#define IS_RCC_HSI14_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Function used to set the RCC clock configuration to the default reset state */ -void RCC_DeInit(void); - -/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/ -void RCC_HSEConfig(uint8_t RCC_HSE); -ErrorStatus RCC_WaitForHSEStartUp(void); -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); -void RCC_HSICmd(FunctionalState NewState); -void RCC_AdjustHSI14CalibrationValue(uint8_t HSI14CalibrationValue); -void RCC_HSI14Cmd(FunctionalState NewState); -void RCC_HSI14ADCRequestCmd(FunctionalState NewState); -void RCC_LSEConfig(uint32_t RCC_LSE); -void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive); -void RCC_LSICmd(FunctionalState NewState); -void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); -void RCC_PLLCmd(FunctionalState NewState); -void RCC_HSI48Cmd(FunctionalState NewState); /*!< Only applicable for STM32F072 devices */ -uint32_t RCC_GetHSI48CalibrationValue(void); /*!< Only applicable for STM32F072 devices */ -void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div); -void RCC_ClockSecuritySystemCmd(FunctionalState NewState); -#ifdef STM32F051 -void RCC_MCOConfig(uint8_t RCC_MCOSource); -#else -void RCC_MCOConfig(uint8_t RCC_MCOSource,uint32_t RCC_MCOPrescaler); -#endif /* STM32F051 */ - -/* System, AHB and APB busses clocks configuration functions ******************/ -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); -uint8_t RCC_GetSYSCLKSource(void); -void RCC_HCLKConfig(uint32_t RCC_SYSCLK); -void RCC_PCLKConfig(uint32_t RCC_HCLK); -void RCC_ADCCLKConfig(uint32_t RCC_ADCCLK); /* This function is obsolete. - For proper ADC clock selection, refer to - ADC_ClockModeConfig() in the ADC driver */ -void RCC_CECCLKConfig(uint32_t RCC_CECCLK); -void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK); -void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK); -void RCC_USBCLKConfig(uint32_t RCC_USBCLK); /*!< Only applicable for STM32F042 and STM32F072 devices */ -void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); - -/* Peripheral clocks configuration functions **********************************/ -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); -void RCC_RTCCLKCmd(FunctionalState NewState); -void RCC_BackupResetCmd(FunctionalState NewState); - -void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); - -void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); -void RCC_ClearFlag(void); -ITStatus RCC_GetITStatus(uint8_t RCC_IT); -void RCC_ClearITPendingBit(uint8_t RCC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0XX_RCC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_rtc.h b/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_rtc.h deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_rtc.h +++ /dev/null @@ -1,807 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_rtc.h - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file contains all the functions prototypes for the RTC firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0XX_RTC_H -#define __STM32F0XX_RTC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup RTC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief RTC Init structures definition - */ -typedef struct -{ - uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format. - This parameter can be a value of @ref RTC_Hour_Formats */ - - uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. - This parameter must be set to a value lower than 0x7F */ - - uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value. - This parameter must be set to a value lower than 0x1FFF */ -}RTC_InitTypeDef; - -/** - * @brief RTC Time structure definition - */ -typedef struct -{ - uint8_t RTC_Hours; /*!< Specifies the RTC Time Hour. - This parameter must be set to a value in the 0-12 range - if the RTC_HourFormat_12 is selected or 0-23 range if - the RTC_HourFormat_24 is selected. */ - - uint8_t RTC_Minutes; /*!< Specifies the RTC Time Minutes. - This parameter must be set to a value in the 0-59 range. */ - - uint8_t RTC_Seconds; /*!< Specifies the RTC Time Seconds. - This parameter must be set to a value in the 0-59 range. */ - - uint8_t RTC_H12; /*!< Specifies the RTC AM/PM Time. - This parameter can be a value of @ref RTC_AM_PM_Definitions */ -}RTC_TimeTypeDef; - -/** - * @brief RTC Date structure definition - */ -typedef struct -{ - uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay. - This parameter can be a value of @ref RTC_WeekDay_Definitions */ - - uint8_t RTC_Month; /*!< Specifies the RTC Date Month. - This parameter can be a value of @ref RTC_Month_Date_Definitions */ - - uint8_t RTC_Date; /*!< Specifies the RTC Date. - This parameter must be set to a value in the 1-31 range. */ - - uint8_t RTC_Year; /*!< Specifies the RTC Date Year. - This parameter must be set to a value in the 0-99 range. */ -}RTC_DateTypeDef; - -/** - * @brief RTC Alarm structure definition - */ -typedef struct -{ - RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */ - - uint32_t RTC_AlarmMask; /*!< Specifies the RTC Alarm Masks. - This parameter can be a value of @ref RTC_AlarmMask_Definitions */ - - uint32_t RTC_AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay. - This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ - - uint8_t RTC_AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay. - This parameter must be set to a value in the 1-31 range - if the Alarm Date is selected. - This parameter can be a value of @ref RTC_WeekDay_Definitions - if the Alarm WeekDay is selected. */ -}RTC_AlarmTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup RTC_Exported_Constants - * @{ - */ - - -/** @defgroup RTC_Hour_Formats - * @{ - */ -#define RTC_HourFormat_24 ((uint32_t)0x00000000) -#define RTC_HourFormat_12 ((uint32_t)0x00000040) -#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \ - ((FORMAT) == RTC_HourFormat_24)) -/** - * @} - */ - -/** @defgroup RTC_Asynchronous_Predivider - * @{ - */ -#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F) - -/** - * @} - */ - - -/** @defgroup RTC_Synchronous_Predivider - * @{ - */ -#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFF) - -/** - * @} - */ - -/** @defgroup RTC_Time_Definitions - * @{ - */ -#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12)) -#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23) -#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59) -#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59) - -/** - * @} - */ - -/** @defgroup RTC_AM_PM_Definitions - * @{ - */ -#define RTC_H12_AM ((uint8_t)0x00) -#define RTC_H12_PM ((uint8_t)0x40) -#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM)) - -/** - * @} - */ - -/** @defgroup RTC_Year_Date_Definitions - * @{ - */ -#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99) - -/** - * @} - */ - -/** @defgroup RTC_Month_Date_Definitions - * @{ - */ -#define RTC_Month_January ((uint8_t)0x01) -#define RTC_Month_February ((uint8_t)0x02) -#define RTC_Month_March ((uint8_t)0x03) -#define RTC_Month_April ((uint8_t)0x04) -#define RTC_Month_May ((uint8_t)0x05) -#define RTC_Month_June ((uint8_t)0x06) -#define RTC_Month_July ((uint8_t)0x07) -#define RTC_Month_August ((uint8_t)0x08) -#define RTC_Month_September ((uint8_t)0x09) -#define RTC_Month_October ((uint8_t)0x10) -#define RTC_Month_November ((uint8_t)0x11) -#define RTC_Month_December ((uint8_t)0x12) -#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12)) -#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31)) - -/** - * @} - */ - -/** @defgroup RTC_WeekDay_Definitions - * @{ - */ - -#define RTC_Weekday_Monday ((uint8_t)0x01) -#define RTC_Weekday_Tuesday ((uint8_t)0x02) -#define RTC_Weekday_Wednesday ((uint8_t)0x03) -#define RTC_Weekday_Thursday ((uint8_t)0x04) -#define RTC_Weekday_Friday ((uint8_t)0x05) -#define RTC_Weekday_Saturday ((uint8_t)0x6) -#define RTC_Weekday_Sunday ((uint8_t)0x07) -#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \ - ((WEEKDAY) == RTC_Weekday_Tuesday) || \ - ((WEEKDAY) == RTC_Weekday_Wednesday) || \ - ((WEEKDAY) == RTC_Weekday_Thursday) || \ - ((WEEKDAY) == RTC_Weekday_Friday) || \ - ((WEEKDAY) == RTC_Weekday_Saturday) || \ - ((WEEKDAY) == RTC_Weekday_Sunday)) -/** - * @} - */ - - -/** @defgroup RTC_Alarm_Definitions - * @{ - */ -#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31)) -#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \ - ((WEEKDAY) == RTC_Weekday_Tuesday) || \ - ((WEEKDAY) == RTC_Weekday_Wednesday) || \ - ((WEEKDAY) == RTC_Weekday_Thursday) || \ - ((WEEKDAY) == RTC_Weekday_Friday) || \ - ((WEEKDAY) == RTC_Weekday_Saturday) || \ - ((WEEKDAY) == RTC_Weekday_Sunday)) - -/** - * @} - */ - - -/** @defgroup RTC_AlarmDateWeekDay_Definitions - * @{ - */ -#define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000) -#define RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000) - -#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \ - ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay)) - -/** - * @} - */ - - -/** @defgroup RTC_AlarmMask_Definitions - * @{ - */ -#define RTC_AlarmMask_None ((uint32_t)0x00000000) -#define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000) -#define RTC_AlarmMask_Hours ((uint32_t)0x00800000) -#define RTC_AlarmMask_Minutes ((uint32_t)0x00008000) -#define RTC_AlarmMask_Seconds ((uint32_t)0x00000080) -#define RTC_AlarmMask_All ((uint32_t)0x80808080) -#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET) - -/** - * @} - */ - -/** @defgroup RTC_Alarms_Definitions - * @{ - */ -#define RTC_Alarm_A ((uint32_t)0x00000100) -#define IS_RTC_ALARM(ALARM) ((ALARM) == RTC_Alarm_A) -#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A)) != (uint32_t)RESET) - -/** - * @} - */ - -/** @defgroup RTC_Alarm_Sub_Seconds_Masks Definitions. - * @{ - */ -#define RTC_AlarmSubSecondMask_All ((uint8_t)0x00) /*!< All Alarm SS fields are masked. - There is no comparison on sub seconds - for Alarm */ -#define RTC_AlarmSubSecondMask_SS14_1 ((uint8_t)0x01) /*!< SS[14:1] are don't care in Alarm - comparison. Only SS[0] is compared. */ -#define RTC_AlarmSubSecondMask_SS14_2 ((uint8_t)0x02) /*!< SS[14:2] are don't care in Alarm - comparison. Only SS[1:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_3 ((uint8_t)0x03) /*!< SS[14:3] are don't care in Alarm - comparison. Only SS[2:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_4 ((uint8_t)0x04) /*!< SS[14:4] are don't care in Alarm - comparison. Only SS[3:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_5 ((uint8_t)0x05) /*!< SS[14:5] are don't care in Alarm - comparison. Only SS[4:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_6 ((uint8_t)0x06) /*!< SS[14:6] are don't care in Alarm - comparison. Only SS[5:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_7 ((uint8_t)0x07) /*!< SS[14:7] are don't care in Alarm - comparison. Only SS[6:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_8 ((uint8_t)0x08) /*!< SS[14:8] are don't care in Alarm - comparison. Only SS[7:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_9 ((uint8_t)0x09) /*!< SS[14:9] are don't care in Alarm - comparison. Only SS[8:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_10 ((uint8_t)0x0A) /*!< SS[14:10] are don't care in Alarm - comparison. Only SS[9:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_11 ((uint8_t)0x0B) /*!< SS[14:11] are don't care in Alarm - comparison. Only SS[10:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_12 ((uint8_t)0x0C) /*!< SS[14:12] are don't care in Alarm - comparison.Only SS[11:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_13 ((uint8_t)0x0D) /*!< SS[14:13] are don't care in Alarm - comparison. Only SS[12:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14 ((uint8_t)0x0E) /*!< SS[14] is don't care in Alarm - comparison.Only SS[13:0] are compared */ -#define RTC_AlarmSubSecondMask_None ((uint8_t)0x0F) /*!< SS[14:0] are compared and must match - to activate alarm. */ -#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_AlarmSubSecondMask_All) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14) || \ - ((MASK) == RTC_AlarmSubSecondMask_None)) -/** - * @} - */ - -/** @defgroup RTC_Alarm_Sub_Seconds_Value - * @{ - */ - -#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF) - -/** - * @} - */ - -/** @defgroup RTC_Wakeup_Timer_Definitions - * @brief These parameters are only available for STM32F072 devices - * @{ - */ -#define RTC_WakeUpClock_RTCCLK_Div16 ((uint32_t)0x00000000) -#define RTC_WakeUpClock_RTCCLK_Div8 ((uint32_t)0x00000001) -#define RTC_WakeUpClock_RTCCLK_Div4 ((uint32_t)0x00000002) -#define RTC_WakeUpClock_RTCCLK_Div2 ((uint32_t)0x00000003) -#define RTC_WakeUpClock_CK_SPRE_16bits ((uint32_t)0x00000004) -#define RTC_WakeUpClock_CK_SPRE_17bits ((uint32_t)0x00000006) -#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \ - ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \ - ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \ - ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \ - ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \ - ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits)) -#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF) -/** - * @} - */ - -/** @defgroup RTC_Time_Stamp_Edges_definitions - * @{ - */ -#define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000) -#define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008) -#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \ - ((EDGE) == RTC_TimeStampEdge_Falling)) -/** - * @} - */ - -/** @defgroup RTC_Output_selection_Definitions - * @{ - */ -#define RTC_Output_Disable ((uint32_t)0x00000000) -#define RTC_Output_AlarmA ((uint32_t)0x00200000) -#define RTC_Output_WakeUp ((uint32_t)0x00600000) /*!< available only for STM32F072 devices */ - -#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \ - ((OUTPUT) == RTC_Output_AlarmA) || \ - ((OUTPUT) == RTC_Output_WakeUp)) - -/** - * @} - */ - -/** @defgroup RTC_Output_Polarity_Definitions - * @{ - */ -#define RTC_OutputPolarity_High ((uint32_t)0x00000000) -#define RTC_OutputPolarity_Low ((uint32_t)0x00100000) -#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \ - ((POL) == RTC_OutputPolarity_Low)) -/** - * @} - */ - - -/** @defgroup RTC_Calib_Output_selection_Definitions - * @{ - */ -#define RTC_CalibOutput_512Hz ((uint32_t)0x00000000) -#define RTC_CalibOutput_1Hz ((uint32_t)0x00080000) -#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CalibOutput_512Hz) || \ - ((OUTPUT) == RTC_CalibOutput_1Hz)) -/** - * @} - */ - -/** @defgroup RTC_Smooth_calib_period_Definitions - * @{ - */ -#define RTC_SmoothCalibPeriod_32sec ((uint32_t)0x00000000) /*!< if RTCCLK = 32768 Hz, Smooth calibation - period is 32s, else 2exp20 RTCCLK seconds */ -#define RTC_SmoothCalibPeriod_16sec ((uint32_t)0x00002000) /*!< if RTCCLK = 32768 Hz, Smooth calibation - period is 16s, else 2exp19 RTCCLK seconds */ -#define RTC_SmoothCalibPeriod_8sec ((uint32_t)0x00004000) /*!< if RTCCLK = 32768 Hz, Smooth calibation - period is 8s, else 2exp18 RTCCLK seconds */ -#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \ - ((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \ - ((PERIOD) == RTC_SmoothCalibPeriod_8sec)) - -/** - * @} - */ - -/** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions - * @{ - */ -#define RTC_SmoothCalibPlusPulses_Set ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added - during a X -second window = Y - CALM[8:0]. - with Y = 512, 256, 128 when X = 32, 16, 8 */ -#define RTC_SmoothCalibPlusPulses_Reset ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited - during a 32-second window = CALM[8:0]. */ -#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \ - ((PLUS) == RTC_SmoothCalibPlusPulses_Reset)) - -/** - * @} - */ - -/** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions - * @{ - */ -#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF) - -/** - * @} - */ - -/** @defgroup RTC_DayLightSaving_Definitions - * @{ - */ -#define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000) -#define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000) -#define IS_RTC_DAYLIGHT_SAVING(SAVING) (((SAVING) == RTC_DayLightSaving_SUB1H) || \ - ((SAVING) == RTC_DayLightSaving_ADD1H)) - -#define RTC_StoreOperation_Reset ((uint32_t)0x00000000) -#define RTC_StoreOperation_Set ((uint32_t)0x00040000) -#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \ - ((OPERATION) == RTC_StoreOperation_Set)) -/** - * @} - */ - -/** @defgroup RTC_Tamper_Trigger_Definitions - * @{ - */ -#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000) -#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001) -#define RTC_TamperTrigger_LowLevel ((uint32_t)0x00000000) -#define RTC_TamperTrigger_HighLevel ((uint32_t)0x00000001) -#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \ - ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \ - ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \ - ((TRIGGER) == RTC_TamperTrigger_HighLevel)) - -/** - * @} - */ - -/** @defgroup RTC_Tamper_Filter_Definitions - * @{ - */ -#define RTC_TamperFilter_Disable ((uint32_t)0x00000000) /*!< Tamper filter is disabled */ - -#define RTC_TamperFilter_2Sample ((uint32_t)0x00000800) /*!< Tamper is activated after 2 - consecutive samples at the active level */ -#define RTC_TamperFilter_4Sample ((uint32_t)0x00001000) /*!< Tamper is activated after 4 - consecutive samples at the active level */ -#define RTC_TamperFilter_8Sample ((uint32_t)0x00001800) /*!< Tamper is activated after 8 - consecutive samples at the active leve. */ -#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \ - ((FILTER) == RTC_TamperFilter_2Sample) || \ - ((FILTER) == RTC_TamperFilter_4Sample) || \ - ((FILTER) == RTC_TamperFilter_8Sample)) -/** - * @} - */ - -/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions - * @{ - */ -#define RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 32768 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x00000100) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 16384 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 8192 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 4096 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 2048 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 1024 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 512 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 256 */ -#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256)) - -/** - * @} - */ - - /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions - * @{ - */ -#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before - sampling during 1 RTCCLK cycle */ -#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before - sampling during 2 RTCCLK cycles */ -#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before - sampling during 4 RTCCLK cycles */ -#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before - sampling during 8 RTCCLK cycles */ - -#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \ - ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \ - ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \ - ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK)) -/** - * @} - */ - -/** @defgroup RTC_Tamper_Pins_Definitions - * @{ - */ -#define RTC_Tamper_1 RTC_TAFCR_TAMP1E /*!< Tamper detection enable for - input tamper 1 */ -#define RTC_Tamper_2 RTC_TAFCR_TAMP2E /*!< Tamper detection enable for - input tamper 2 */ -#define RTC_Tamper_3 RTC_TAFCR_TAMP3E /*!< Tamper detection enable for - input tamper 3, available only - for STM32F072 devices */ -#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET)) - -/** - * @} - */ - -/** @defgroup RTC_Output_Type_ALARM_OUT - * @{ - */ -#define RTC_OutputType_OpenDrain ((uint32_t)0x00000000) -#define RTC_OutputType_PushPull ((uint32_t)0x00040000) -#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \ - ((TYPE) == RTC_OutputType_PushPull)) - -/** - * @} - */ - -/** @defgroup RTC_Add_1_Second_Parameter_Definitions - * @{ - */ -#define RTC_ShiftAdd1S_Reset ((uint32_t)0x00000000) -#define RTC_ShiftAdd1S_Set ((uint32_t)0x80000000) -#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) || \ - ((SEL) == RTC_ShiftAdd1S_Set)) -/** - * @} - */ - -/** @defgroup RTC_Substract_Fraction_Of_Second_Value - * @{ - */ -#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF) - -/** - * @} - */ - -/** @defgroup RTC_Backup_Registers_Definitions - * @{ - */ - -#define RTC_BKP_DR0 ((uint32_t)0x00000000) -#define RTC_BKP_DR1 ((uint32_t)0x00000001) -#define RTC_BKP_DR2 ((uint32_t)0x00000002) -#define RTC_BKP_DR3 ((uint32_t)0x00000003) -#define RTC_BKP_DR4 ((uint32_t)0x00000004) -#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \ - ((BKP) == RTC_BKP_DR1) || \ - ((BKP) == RTC_BKP_DR2) || \ - ((BKP) == RTC_BKP_DR3) || \ - ((BKP) == RTC_BKP_DR4)) -/** - * @} - */ - -/** @defgroup RTC_Input_parameter_format_definitions - * @{ - */ -#define RTC_Format_BIN ((uint32_t)0x000000000) -#define RTC_Format_BCD ((uint32_t)0x000000001) -#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD)) - -/** - * @} - */ - -/** @defgroup RTC_Flags_Definitions - * @{ - */ -#define RTC_FLAG_RECALPF RTC_ISR_RECALPF -#define RTC_FLAG_TAMP3F RTC_ISR_TAMP3F /*!< Only available for STM32F072 devices */ -#define RTC_FLAG_TAMP2F RTC_ISR_TAMP2F -#define RTC_FLAG_TAMP1F RTC_ISR_TAMP1F -#define RTC_FLAG_TSOVF RTC_ISR_TSOVF -#define RTC_FLAG_TSF RTC_ISR_TSF -#define RTC_FLAG_WUTF RTC_ISR_WUTF /*!< Only available for STM32F072 devices */ -#define RTC_FLAG_ALRAF RTC_ISR_ALRAF -#define RTC_FLAG_INITF RTC_ISR_INITF -#define RTC_FLAG_RSF RTC_ISR_RSF -#define RTC_FLAG_INITS RTC_ISR_INITS -#define RTC_FLAG_SHPF RTC_ISR_SHPF -#define RTC_FLAG_WUTWF RTC_ISR_WUTWF /*!< Only available for STM32F072 devices */ -#define RTC_FLAG_ALRAWF RTC_ISR_ALRAWF - -#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \ - ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRAWF) || \ - ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \ - ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \ - ((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_TAMP2F) || \ - ((FLAG) == RTC_FLAG_TAMP3F) || ((FLAG) == RTC_FLAG_RECALPF) || \ - ((FLAG) == RTC_FLAG_SHPF)) -#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF02DF) == (uint32_t)RESET)) - -/** - * @} - */ - -/** @defgroup RTC_Interrupts_Definitions - * @{ - */ -#define RTC_IT_TS ((uint32_t)0x00008000) -#define RTC_IT_WUT ((uint32_t)0x00004000) /* Available only for STM32F072 devices */ -#define RTC_IT_ALRA ((uint32_t)0x00001000) -#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */ -#define RTC_IT_TAMP1 ((uint32_t)0x00020000) -#define RTC_IT_TAMP2 ((uint32_t)0x00040000) -#define RTC_IT_TAMP3 ((uint32_t)0x00080000) /* Available only for STM32F072 devices */ - -#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF2FFB) == (uint32_t)RESET)) -#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_ALRA) || \ - ((IT) == RTC_IT_TAMP1) || ((IT) == RTC_IT_WUT) || \ - ((IT) == RTC_IT_TAMP2) || ((IT) == RTC_IT_TAMP3)) - -#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFF12FFF) == (uint32_t)RESET)) - -/** - * @} - */ - -/** - * @} - */ - - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -/* Function used to set the RTC configuration to the default reset state *****/ -ErrorStatus RTC_DeInit(void); - - -/* Initialization and Configuration functions *********************************/ -ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct); -void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct); -void RTC_WriteProtectionCmd(FunctionalState NewState); -ErrorStatus RTC_EnterInitMode(void); -void RTC_ExitInitMode(void); -ErrorStatus RTC_WaitForSynchro(void); -ErrorStatus RTC_RefClockCmd(FunctionalState NewState); -void RTC_BypassShadowCmd(FunctionalState NewState); - -/* Time and Date configuration functions **************************************/ -ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct); -void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct); -void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct); -uint32_t RTC_GetSubSecond(void); -ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct); -void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct); -void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct); - -/* Alarms (Alarm A) configuration functions **********************************/ -void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); -void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct); -void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); -ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState); -void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint8_t RTC_AlarmSubSecondMask); -uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm); - -/* WakeUp Timer configuration functions ***************************************/ -void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock); /*!< available only for STM32F072 devices */ -void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter); /*!< available only for STM32F072 devices */ -uint32_t RTC_GetWakeUpCounter(void); /*!< available only for STM32F072 devices */ -ErrorStatus RTC_WakeUpCmd(FunctionalState NewState); /*!< available only for STM32F072 devices */ - -/* Daylight Saving configuration functions ************************************/ -void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation); -uint32_t RTC_GetStoreOperation(void); - -/* Output pin Configuration function ******************************************/ -void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity); - -/* Digital Calibration configuration functions ********************************/ -void RTC_CalibOutputCmd(FunctionalState NewState); -void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput); -ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod, - uint32_t RTC_SmoothCalibPlusPulses, - uint32_t RTC_SmouthCalibMinusPulsesValue); - -/* TimeStamp configuration functions ******************************************/ -void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState); -void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, RTC_DateTypeDef* RTC_StampDateStruct); -uint32_t RTC_GetTimeStampSubSecond(void); - -/* Tampers configuration functions ********************************************/ -void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger); -void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState); -void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter); -void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq); -void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration); -void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState); -void RTC_TamperPullUpCmd(FunctionalState NewState); - -/* Backup Data Registers configuration functions ******************************/ -void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data); -uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR); - -/* Output Type Config configuration functions *********************************/ -void RTC_OutputTypeConfig(uint32_t RTC_OutputType); - -/* RTC_Shift_control_synchonisation_functions *********************************/ -ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS); - -/* Interrupts and flags management functions **********************************/ -void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState); -FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG); -void RTC_ClearFlag(uint32_t RTC_FLAG); -ITStatus RTC_GetITStatus(uint32_t RTC_IT); -void RTC_ClearITPendingBit(uint32_t RTC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F0XX_RTC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_spi.h b/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_spi.h deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_spi.h +++ /dev/null @@ -1,588 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_spi.h - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file contains all the functions prototypes for the SPI - * firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0XX_SPI_H -#define __STM32F0XX_SPI_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup SPI - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief SPI Init structure definition - */ - -typedef struct -{ - uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. - This parameter can be a value of @ref SPI_data_direction */ - - uint16_t SPI_Mode; /*!< Specifies the SPI mode (Master/Slave). - This parameter can be a value of @ref SPI_mode */ - - uint16_t SPI_DataSize; /*!< Specifies the SPI data size. - This parameter can be a value of @ref SPI_data_size */ - - uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. - This parameter can be a value of @ref SPI_Clock_Polarity */ - - uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. - This parameter can be a value of @ref SPI_Clock_Phase */ - - uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by - hardware (NSS pin) or by software using the SSI bit. - This parameter can be a value of @ref SPI_Slave_Select_management */ - - uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be - used to configure the transmit and receive SCK clock. - This parameter can be a value of @ref SPI_BaudRate_Prescaler - @note The communication clock is derived from the master - clock. The slave clock does not need to be set. */ - - uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. - This parameter can be a value of @ref SPI_MSB_LSB_transmission */ - - uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ -}SPI_InitTypeDef; - - -/** - * @brief I2S Init structure definition - * @note These parameters are not available for STM32F030 devices. - */ - -typedef struct -{ - uint16_t I2S_Mode; /*!< Specifies the I2S operating mode. - This parameter can be a value of @ref SPI_I2S_Mode */ - - uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication. - This parameter can be a value of @ref SPI_I2S_Standard */ - - uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication. - This parameter can be a value of @ref SPI_I2S_Data_Format */ - - uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. - This parameter can be a value of @ref SPI_I2S_MCLK_Output */ - - uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication. - This parameter can be a value of @ref SPI_I2S_Audio_Frequency */ - - uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock. - This parameter can be a value of @ref SPI_I2S_Clock_Polarity */ -}I2S_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup SPI_Exported_Constants - * @{ - */ - -#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ - ((PERIPH) == SPI2)) - -#define IS_SPI_1_PERIPH(PERIPH) (((PERIPH) == SPI1)) - -/** @defgroup SPI_data_direction - * @{ - */ - -#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) -#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) -#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) -#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) -#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ - ((MODE) == SPI_Direction_2Lines_RxOnly) || \ - ((MODE) == SPI_Direction_1Line_Rx) || \ - ((MODE) == SPI_Direction_1Line_Tx)) -/** - * @} - */ - -/** @defgroup SPI_mode - * @{ - */ - -#define SPI_Mode_Master ((uint16_t)0x0104) -#define SPI_Mode_Slave ((uint16_t)0x0000) -#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ - ((MODE) == SPI_Mode_Slave)) -/** - * @} - */ - -/** @defgroup SPI_data_size - * @{ - */ - -#define SPI_DataSize_4b ((uint16_t)0x0300) -#define SPI_DataSize_5b ((uint16_t)0x0400) -#define SPI_DataSize_6b ((uint16_t)0x0500) -#define SPI_DataSize_7b ((uint16_t)0x0600) -#define SPI_DataSize_8b ((uint16_t)0x0700) -#define SPI_DataSize_9b ((uint16_t)0x0800) -#define SPI_DataSize_10b ((uint16_t)0x0900) -#define SPI_DataSize_11b ((uint16_t)0x0A00) -#define SPI_DataSize_12b ((uint16_t)0x0B00) -#define SPI_DataSize_13b ((uint16_t)0x0C00) -#define SPI_DataSize_14b ((uint16_t)0x0D00) -#define SPI_DataSize_15b ((uint16_t)0x0E00) -#define SPI_DataSize_16b ((uint16_t)0x0F00) -#define IS_SPI_DATA_SIZE(SIZE) (((SIZE) == SPI_DataSize_4b) || \ - ((SIZE) == SPI_DataSize_5b) || \ - ((SIZE) == SPI_DataSize_6b) || \ - ((SIZE) == SPI_DataSize_7b) || \ - ((SIZE) == SPI_DataSize_8b) || \ - ((SIZE) == SPI_DataSize_9b) || \ - ((SIZE) == SPI_DataSize_10b) || \ - ((SIZE) == SPI_DataSize_11b) || \ - ((SIZE) == SPI_DataSize_12b) || \ - ((SIZE) == SPI_DataSize_13b) || \ - ((SIZE) == SPI_DataSize_14b) || \ - ((SIZE) == SPI_DataSize_15b) || \ - ((SIZE) == SPI_DataSize_16b)) -/** - * @} - */ - -/** @defgroup SPI_CRC_length - * @{ - */ - -#define SPI_CRCLength_8b ((uint16_t)0x0000) -#define SPI_CRCLength_16b SPI_CR1_CRCL -#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRCLength_8b) || \ - ((LENGTH) == SPI_CRCLength_16b)) -/** - * @} - */ - -/** @defgroup SPI_Clock_Polarity - * @{ - */ - -#define SPI_CPOL_Low ((uint16_t)0x0000) -#define SPI_CPOL_High SPI_CR1_CPOL -#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ - ((CPOL) == SPI_CPOL_High)) -/** - * @} - */ - -/** @defgroup SPI_Clock_Phase - * @{ - */ - -#define SPI_CPHA_1Edge ((uint16_t)0x0000) -#define SPI_CPHA_2Edge SPI_CR1_CPHA -#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ - ((CPHA) == SPI_CPHA_2Edge)) -/** - * @} - */ - -/** @defgroup SPI_Slave_Select_management - * @{ - */ - -#define SPI_NSS_Soft SPI_CR1_SSM -#define SPI_NSS_Hard ((uint16_t)0x0000) -#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ - ((NSS) == SPI_NSS_Hard)) -/** - * @} - */ - -/** @defgroup SPI_BaudRate_Prescaler - * @{ - */ - -#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) -#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) -#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) -#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) -#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) -#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) -#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) -#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) -#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_256)) -/** - * @} - */ - -/** @defgroup SPI_MSB_LSB_transmission - * @{ - */ - -#define SPI_FirstBit_MSB ((uint16_t)0x0000) -#define SPI_FirstBit_LSB SPI_CR1_LSBFIRST -#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ - ((BIT) == SPI_FirstBit_LSB)) -/** - * @} - */ - -/** @defgroup SPI_I2S_Mode - * @{ - */ - -#define I2S_Mode_SlaveTx ((uint16_t)0x0000) -#define I2S_Mode_SlaveRx ((uint16_t)0x0100) -#define I2S_Mode_MasterTx ((uint16_t)0x0200) -#define I2S_Mode_MasterRx ((uint16_t)0x0300) -#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ - ((MODE) == I2S_Mode_SlaveRx) || \ - ((MODE) == I2S_Mode_MasterTx)|| \ - ((MODE) == I2S_Mode_MasterRx)) -/** - * @} - */ - -/** @defgroup SPI_I2S_Standard - * @{ - */ - -#define I2S_Standard_Phillips ((uint16_t)0x0000) -#define I2S_Standard_MSB ((uint16_t)0x0010) -#define I2S_Standard_LSB ((uint16_t)0x0020) -#define I2S_Standard_PCMShort ((uint16_t)0x0030) -#define I2S_Standard_PCMLong ((uint16_t)0x00B0) -#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \ - ((STANDARD) == I2S_Standard_MSB) || \ - ((STANDARD) == I2S_Standard_LSB) || \ - ((STANDARD) == I2S_Standard_PCMShort) || \ - ((STANDARD) == I2S_Standard_PCMLong)) -/** - * @} - */ - -/** @defgroup SPI_I2S_Data_Format - * @{ - */ - -#define I2S_DataFormat_16b ((uint16_t)0x0000) -#define I2S_DataFormat_16bextended ((uint16_t)0x0001) -#define I2S_DataFormat_24b ((uint16_t)0x0003) -#define I2S_DataFormat_32b ((uint16_t)0x0005) -#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \ - ((FORMAT) == I2S_DataFormat_16bextended) || \ - ((FORMAT) == I2S_DataFormat_24b) || \ - ((FORMAT) == I2S_DataFormat_32b)) -/** - * @} - */ - -/** @defgroup SPI_I2S_MCLK_Output - * @{ - */ - -#define I2S_MCLKOutput_Enable SPI_I2SPR_MCKOE -#define I2S_MCLKOutput_Disable ((uint16_t)0x0000) -#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \ - ((OUTPUT) == I2S_MCLKOutput_Disable)) -/** - * @} - */ - -/** @defgroup SPI_I2S_Audio_Frequency - * @{ - */ - -#define I2S_AudioFreq_192k ((uint32_t)192000) -#define I2S_AudioFreq_96k ((uint32_t)96000) -#define I2S_AudioFreq_48k ((uint32_t)48000) -#define I2S_AudioFreq_44k ((uint32_t)44100) -#define I2S_AudioFreq_32k ((uint32_t)32000) -#define I2S_AudioFreq_22k ((uint32_t)22050) -#define I2S_AudioFreq_16k ((uint32_t)16000) -#define I2S_AudioFreq_11k ((uint32_t)11025) -#define I2S_AudioFreq_8k ((uint32_t)8000) -#define I2S_AudioFreq_Default ((uint32_t)2) - -#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \ - ((FREQ) <= I2S_AudioFreq_192k)) || \ - ((FREQ) == I2S_AudioFreq_Default)) -/** - * @} - */ - -/** @defgroup SPI_I2S_Clock_Polarity - * @{ - */ - -#define I2S_CPOL_Low ((uint16_t)0x0000) -#define I2S_CPOL_High SPI_I2SCFGR_CKPOL -#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \ - ((CPOL) == I2S_CPOL_High)) -/** - * @} - */ - -/** @defgroup SPI_FIFO_reception_threshold - * @{ - */ - -#define SPI_RxFIFOThreshold_HF ((uint16_t)0x0000) -#define SPI_RxFIFOThreshold_QF SPI_CR2_FRXTH -#define IS_SPI_RX_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_RxFIFOThreshold_HF) || \ - ((THRESHOLD) == SPI_RxFIFOThreshold_QF)) -/** - * @} - */ - -/** @defgroup SPI_I2S_DMA_transfer_requests - * @{ - */ - -#define SPI_I2S_DMAReq_Tx SPI_CR2_TXDMAEN -#define SPI_I2S_DMAReq_Rx SPI_CR2_RXDMAEN -#define IS_SPI_I2S_DMA_REQ(REQ) ((((REQ) & (uint16_t)0xFFFC) == 0x00) && ((REQ) != 0x00)) -/** - * @} - */ - -/** @defgroup SPI_last_DMA_transfers - * @{ - */ - -#define SPI_LastDMATransfer_TxEvenRxEven ((uint16_t)0x0000) -#define SPI_LastDMATransfer_TxOddRxEven ((uint16_t)0x4000) -#define SPI_LastDMATransfer_TxEvenRxOdd ((uint16_t)0x2000) -#define SPI_LastDMATransfer_TxOddRxOdd ((uint16_t)0x6000) -#define IS_SPI_LAST_DMA_TRANSFER(TRANSFER) (((TRANSFER) == SPI_LastDMATransfer_TxEvenRxEven) || \ - ((TRANSFER) == SPI_LastDMATransfer_TxOddRxEven) || \ - ((TRANSFER) == SPI_LastDMATransfer_TxEvenRxOdd) || \ - ((TRANSFER) == SPI_LastDMATransfer_TxOddRxOdd)) -/** - * @} - */ -/** @defgroup SPI_NSS_internal_software_management - * @{ - */ - -#define SPI_NSSInternalSoft_Set SPI_CR1_SSI -#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) -#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ - ((INTERNAL) == SPI_NSSInternalSoft_Reset)) -/** - * @} - */ - -/** @defgroup SPI_CRC_Transmit_Receive - * @{ - */ - -#define SPI_CRC_Tx ((uint8_t)0x00) -#define SPI_CRC_Rx ((uint8_t)0x01) -#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) -/** - * @} - */ - -/** @defgroup SPI_direction_transmit_receive - * @{ - */ - -#define SPI_Direction_Rx ((uint16_t)0xBFFF) -#define SPI_Direction_Tx ((uint16_t)0x4000) -#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ - ((DIRECTION) == SPI_Direction_Tx)) -/** - * @} - */ - -/** @defgroup SPI_I2S_interrupts_definition - * @{ - */ - -#define SPI_I2S_IT_TXE ((uint8_t)0x71) -#define SPI_I2S_IT_RXNE ((uint8_t)0x60) -#define SPI_I2S_IT_ERR ((uint8_t)0x50) - -#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ - ((IT) == SPI_I2S_IT_RXNE) || \ - ((IT) == SPI_I2S_IT_ERR)) - -#define I2S_IT_UDR ((uint8_t)0x53) -#define SPI_IT_MODF ((uint8_t)0x55) -#define SPI_I2S_IT_OVR ((uint8_t)0x56) -#define SPI_I2S_IT_FRE ((uint8_t)0x58) - -#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \ - ((IT) == SPI_I2S_IT_OVR) || ((IT) == SPI_IT_MODF) || \ - ((IT) == SPI_I2S_IT_FRE)|| ((IT) == I2S_IT_UDR)) -/** - * @} - */ - - -/** @defgroup SPI_transmission_fifo_status_level - * @{ - */ - -#define SPI_TransmissionFIFOStatus_Empty ((uint16_t)0x0000) -#define SPI_TransmissionFIFOStatus_1QuarterFull ((uint16_t)0x0800) -#define SPI_TransmissionFIFOStatus_HalfFull ((uint16_t)0x1000) -#define SPI_TransmissionFIFOStatus_Full ((uint16_t)0x1800) - -/** - * @} - */ - -/** @defgroup SPI_reception_fifo_status_level - * @{ - */ -#define SPI_ReceptionFIFOStatus_Empty ((uint16_t)0x0000) -#define SPI_ReceptionFIFOStatus_1QuarterFull ((uint16_t)0x0200) -#define SPI_ReceptionFIFOStatus_HalfFull ((uint16_t)0x0400) -#define SPI_ReceptionFIFOStatus_Full ((uint16_t)0x0600) - -/** - * @} - */ - - -/** @defgroup SPI_I2S_flags_definition - * @{ - */ - -#define SPI_I2S_FLAG_RXNE SPI_SR_RXNE -#define SPI_I2S_FLAG_TXE SPI_SR_TXE -#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE -#define I2S_FLAG_UDR SPI_SR_UDR -#define SPI_FLAG_CRCERR SPI_SR_CRCERR -#define SPI_FLAG_MODF SPI_SR_MODF -#define SPI_I2S_FLAG_OVR SPI_SR_OVR -#define SPI_I2S_FLAG_BSY SPI_SR_BSY -#define SPI_I2S_FLAG_FRE SPI_SR_FRE - - - -#define IS_SPI_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) -#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ - ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ - ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \ - ((FLAG) == SPI_I2S_FLAG_FRE)|| ((FLAG) == I2S_FLAG_CHSIDE)|| \ - ((FLAG) == I2S_FLAG_UDR)) -/** - * @} - */ - -/** @defgroup SPI_CRC_polynomial - * @{ - */ - -#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Initialization and Configuration functions *********************************/ -void SPI_I2S_DeInit(SPI_TypeDef* SPIx); -void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); -void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); /*!< Not applicable for STM32F030 devices */ -void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); -void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); /*!< Not applicable for STM32F030 devices */ -void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); /*!< Not applicable for STM32F030 devices */ -void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); -void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold); -void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); -void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); - -/* Data transfers functions ***************************************************/ -void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data); -void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data); -uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx); -uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx); - -/* Hardware CRC Calculation functions *****************************************/ -void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength); -void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_TransmitCRC(SPI_TypeDef* SPIx); -uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); - -/* DMA transfers management functions *****************************************/ -void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); -void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer); - -/* Interrupts and flags management functions **********************************/ -void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); -uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx); -uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx); -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); -void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F0XX_SPI_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_syscfg.h b/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_syscfg.h deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_syscfg.h +++ /dev/null @@ -1,459 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_syscfg.h - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file contains all the functions prototypes for the SYSCFG firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/*!< Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0XX_SYSCFG_H -#define __STM32F0XX_SYSCFG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/*!< Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup SYSCFG - * @{ - */ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup SYSCFG_Exported_Constants - * @{ - */ - -/** @defgroup SYSCFG_EXTI_Port_Sources - * @{ - */ -#define EXTI_PortSourceGPIOA ((uint8_t)0x00) -#define EXTI_PortSourceGPIOB ((uint8_t)0x01) -#define EXTI_PortSourceGPIOC ((uint8_t)0x02) -#define EXTI_PortSourceGPIOD ((uint8_t)0x03) /*!< not available for STM32F031 devices */ -#define EXTI_PortSourceGPIOE ((uint8_t)0x04) /*!< only available for STM32F072 devices */ -#define EXTI_PortSourceGPIOF ((uint8_t)0x05) - -#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOF)) -/** - * @} - */ - -/** @defgroup SYSCFG_EXTI_Pin_sources - * @{ - */ -#define EXTI_PinSource0 ((uint8_t)0x00) -#define EXTI_PinSource1 ((uint8_t)0x01) -#define EXTI_PinSource2 ((uint8_t)0x02) -#define EXTI_PinSource3 ((uint8_t)0x03) -#define EXTI_PinSource4 ((uint8_t)0x04) -#define EXTI_PinSource5 ((uint8_t)0x05) -#define EXTI_PinSource6 ((uint8_t)0x06) -#define EXTI_PinSource7 ((uint8_t)0x07) -#define EXTI_PinSource8 ((uint8_t)0x08) -#define EXTI_PinSource9 ((uint8_t)0x09) -#define EXTI_PinSource10 ((uint8_t)0x0A) -#define EXTI_PinSource11 ((uint8_t)0x0B) -#define EXTI_PinSource12 ((uint8_t)0x0C) -#define EXTI_PinSource13 ((uint8_t)0x0D) -#define EXTI_PinSource14 ((uint8_t)0x0E) -#define EXTI_PinSource15 ((uint8_t)0x0F) - -#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \ - ((PINSOURCE) == EXTI_PinSource1) || \ - ((PINSOURCE) == EXTI_PinSource2) || \ - ((PINSOURCE) == EXTI_PinSource3) || \ - ((PINSOURCE) == EXTI_PinSource4) || \ - ((PINSOURCE) == EXTI_PinSource5) || \ - ((PINSOURCE) == EXTI_PinSource6) || \ - ((PINSOURCE) == EXTI_PinSource7) || \ - ((PINSOURCE) == EXTI_PinSource8) || \ - ((PINSOURCE) == EXTI_PinSource9) || \ - ((PINSOURCE) == EXTI_PinSource10) || \ - ((PINSOURCE) == EXTI_PinSource11) || \ - ((PINSOURCE) == EXTI_PinSource12) || \ - ((PINSOURCE) == EXTI_PinSource13) || \ - ((PINSOURCE) == EXTI_PinSource14) || \ - ((PINSOURCE) == EXTI_PinSource15)) -/** - * @} - */ - -/** @defgroup SYSCFG_Memory_Remap_Config - * @{ - */ -#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00) -#define SYSCFG_MemoryRemap_SystemMemory ((uint8_t)0x01) -#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03) - - -#define IS_SYSCFG_MEMORY_REMAP(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \ - ((REMAP) == SYSCFG_MemoryRemap_SystemMemory) || \ - ((REMAP) == SYSCFG_MemoryRemap_SRAM)) - -/** - * @} - */ - -/** @defgroup SYSCFG_DMA_Remap_Config - * @{ - */ -#define SYSCFG_DMARemap_TIM3 SYSCFG_CFGR1_TIM3_DMA_RMP /* Remap TIM3 DMA requests from channel4 to channel6, - available only for STM32F072 devices */ -#define SYSCFG_DMARemap_TIM2 SYSCFG_CFGR1_TIM2_DMA_RMP /* Remap TIM2 DMA requests from channel3/4 to channel7, - available only for STM32F072 devices */ -#define SYSCFG_DMARemap_TIM1 SYSCFG_CFGR1_TIM1_DMA_RMP /* Remap TIM1 DMA requests from channel2/3/4 to channel6, - available only for STM32F072 devices */ -#define SYSCFG_DMARemap_I2C1 SYSCFG_CFGR1_I2C1_DMA_RMP /* Remap I2C1 DMA requests from channel3/2 to channel7/6, - available only for STM32F072 devices */ -#define SYSCFG_DMARemap_USART3 SYSCFG_CFGR1_USART3_DMA_RMP /* Remap USART3 DMA requests from channel6/7 to channel3/2, - available only for STM32F072 devices */ -#define SYSCFG_DMARemap_USART2 SYSCFG_CFGR1_USART2_DMA_RMP /* Remap USART2 DMA requests from channel4/5 to channel6/7, - available only for STM32F072 devices */ -#define SYSCFG_DMARemap_SPI2 SYSCFG_CFGR1_SPI2_DMA_RMP /* Remap SPI2 DMA requests from channel4/5 to channel6/7, - available only for STM32F072 devices */ -#define SYSCFG_DMARemap_TIM17_2 SYSCFG_CFGR1_TIM17_DMA_RMP2 /* Remap TIM17 DMA requests from channel1/2 to channel7, - available only for STM32F072 devices */ -#define SYSCFG_DMARemap_TIM16_2 SYSCFG_CFGR1_TIM16_DMA_RMP2 /* Remap TIM16 DMA requests from channel3/4 to channel6, - available only for STM32F072 devices */ -#define SYSCFG_DMARemap_TIM17 SYSCFG_CFGR1_TIM17_DMA_RMP /* Remap TIM17 DMA requests from channel1 to channel2 */ -#define SYSCFG_DMARemap_TIM16 SYSCFG_CFGR1_TIM16_DMA_RMP /* Remap TIM16 DMA requests from channel3 to channel4 */ -#define SYSCFG_DMARemap_USART1Rx SYSCFG_CFGR1_USART1RX_DMA_RMP /* Remap USART1 Rx DMA requests from channel3 to channel5 */ -#define SYSCFG_DMARemap_USART1Tx SYSCFG_CFGR1_USART1TX_DMA_RMP /* Remap USART1 Tx DMA requests from channel2 to channel4 */ -#define SYSCFG_DMARemap_ADC1 SYSCFG_CFGR1_ADC_DMA_RMP /* Remap ADC1 DMA requests from channel1 to channel2 */ - -#define IS_SYSCFG_DMA_REMAP(REMAP) (((REMAP) == SYSCFG_DMARemap_TIM17) || \ - ((REMAP) == SYSCFG_DMARemap_TIM16) || \ - ((REMAP) == SYSCFG_DMARemap_USART1Rx) || \ - ((REMAP) == SYSCFG_DMARemap_USART1Tx) || \ - ((REMAP) == SYSCFG_CFGR1_TIM3_DMA_RMP) || \ - ((REMAP) == SYSCFG_CFGR1_TIM2_DMA_RMP) || \ - ((REMAP) == SYSCFG_CFGR1_TIM1_DMA_RMP) || \ - ((REMAP) == SYSCFG_CFGR1_I2C1_DMA_RMP) || \ - ((REMAP) == SYSCFG_CFGR1_USART3_DMA_RMP) || \ - ((REMAP) == SYSCFG_CFGR1_USART2_DMA_RMP) || \ - ((REMAP) == SYSCFG_CFGR1_SPI2_DMA_RMP) || \ - ((REMAP) == SYSCFG_CFGR1_TIM17_DMA_RMP2) || \ - ((REMAP) == SYSCFG_CFGR1_TIM16_DMA_RMP2) || \ - ((REMAP) == SYSCFG_DMARemap_ADC1)) - -/** - * @} - */ - -/** @defgroup SYSCFG_I2C_FastModePlus_Config - * @{ - */ -#define SYSCFG_I2CFastModePlus_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /* Enable Fast Mode Plus on PB6 */ -#define SYSCFG_I2CFastModePlus_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /* Enable Fast Mode Plus on PB7 */ -#define SYSCFG_I2CFastModePlus_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /* Enable Fast Mode Plus on PB8 */ -#define SYSCFG_I2CFastModePlus_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /* Enable Fast Mode Plus on PB9 */ -#define SYSCFG_I2CFastModePlus_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1 /* Enable Fast Mode Plus on PB10, PB11, PF6 and PF7(only for STM32F0031 and STM32F030 devices) */ -#define SYSCFG_I2CFastModePlus_I2C2 SYSCFG_CFGR1_I2C_FMP_I2C2 /* Enable Fast Mode Plus on I2C2 pins, available only for STM32F072 devices */ -#define SYSCFG_I2CFastModePlus_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /* Enable Fast Mode Plus on PA9 (only for STM32F031 and STM32F030 devices) */ -#define SYSCFG_I2CFastModePlus_PA10 SYSCFG_CFGR1_I2C_FMP_PA10/* Enable Fast Mode Plus on PA10(only for STM32F031 and STM32F030 devices) */ - -#define IS_SYSCFG_I2C_FMP(PIN) (((PIN) == SYSCFG_I2CFastModePlus_PB6) || \ - ((PIN) == SYSCFG_I2CFastModePlus_PB7) || \ - ((PIN) == SYSCFG_I2CFastModePlus_PB8) || \ - ((PIN) == SYSCFG_I2CFastModePlus_PB9) || \ - ((PIN) == SYSCFG_I2CFastModePlus_I2C1) || \ - ((PIN) == SYSCFG_I2CFastModePlus_I2C2) || \ - ((PIN) == SYSCFG_I2CFastModePlus_PA9) || \ - ((PIN) == SYSCFG_I2CFastModePlus_PA10)) - - -/** - * @} - */ - -/** @defgroup SYSCFG_Lock_Config - * @{ - */ -#define SYSCFG_Break_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Connects the PVD event to the Break Input of TIM1, not available for STM32F030 devices */ -#define SYSCFG_Break_SRAMParity SYSCFG_CFGR2_SRAM_PARITY_LOCK /*!< Connects the SRAM_PARITY error signal to the Break Input of TIM1 */ -#define SYSCFG_Break_Lockup SYSCFG_CFGR2_LOCKUP_LOCK /*!< Connects Lockup output of CortexM0 to the break input of TIM1 */ - -#define IS_SYSCFG_LOCK_CONFIG(CONFIG) (((CONFIG) == SYSCFG_Break_PVD) || \ - ((CONFIG) == SYSCFG_Break_SRAMParity) || \ - ((CONFIG) == SYSCFG_Break_Lockup)) - -/** - * @} - */ - -/** @defgroup SYSCFG_flags_definition - * @{ - */ - -#define SYSCFG_FLAG_PE SYSCFG_CFGR2_SRAM_PE - -#define IS_SYSCFG_FLAG(FLAG) (((FLAG) == SYSCFG_FLAG_PE)) - -/** - * @} - */ - -/** @defgroup SYSCFG_ISR_WRAPPER - * @{ - */ -#define SYSCFG_ITLINE0 ((uint32_t) 0x00000000) -#define SYSCFG_ITLINE1 ((uint32_t) 0x00000001) -#define SYSCFG_ITLINE2 ((uint32_t) 0x00000002) -#define SYSCFG_ITLINE3 ((uint32_t) 0x00000003) -#define SYSCFG_ITLINE4 ((uint32_t) 0x00000004) -#define SYSCFG_ITLINE5 ((uint32_t) 0x00000005) -#define SYSCFG_ITLINE6 ((uint32_t) 0x00000006) -#define SYSCFG_ITLINE7 ((uint32_t) 0x00000007) -#define SYSCFG_ITLINE8 ((uint32_t) 0x00000008) -#define SYSCFG_ITLINE9 ((uint32_t) 0x00000009) -#define SYSCFG_ITLINE10 ((uint32_t) 0x0000000A) -#define SYSCFG_ITLINE11 ((uint32_t) 0x0000000B) -#define SYSCFG_ITLINE12 ((uint32_t) 0x0000000C) -#define SYSCFG_ITLINE13 ((uint32_t) 0x0000000D) -#define SYSCFG_ITLINE14 ((uint32_t) 0x0000000E) -#define SYSCFG_ITLINE15 ((uint32_t) 0x0000000F) -#define SYSCFG_ITLINE16 ((uint32_t) 0x00000010) -#define SYSCFG_ITLINE17 ((uint32_t) 0x00000011) -#define SYSCFG_ITLINE18 ((uint32_t) 0x00000012) -#define SYSCFG_ITLINE19 ((uint32_t) 0x00000013) -#define SYSCFG_ITLINE20 ((uint32_t) 0x00000014) -#define SYSCFG_ITLINE21 ((uint32_t) 0x00000015) -#define SYSCFG_ITLINE22 ((uint32_t) 0x00000016) -#define SYSCFG_ITLINE23 ((uint32_t) 0x00000017) -#define SYSCFG_ITLINE24 ((uint32_t) 0x00000018) -#define SYSCFG_ITLINE25 ((uint32_t) 0x00000019) -#define SYSCFG_ITLINE26 ((uint32_t) 0x0000001A) -#define SYSCFG_ITLINE27 ((uint32_t) 0x0000001B) -#define SYSCFG_ITLINE28 ((uint32_t) 0x0000001C) -#define SYSCFG_ITLINE29 ((uint32_t) 0x0000001D) -#define SYSCFG_ITLINE30 ((uint32_t) 0x0000001E) -#define SYSCFG_ITLINE31 ((uint32_t) 0x0000001F) - -#define ITLINE_EWDG ((uint32_t) ((SYSCFG_ITLINE0 << 0x18) | SYSCFG_ITLINE0_SR_EWDG)) /* EWDG Interrupt */ -#define ITLINE_PVDOUT ((uint32_t) ((SYSCFG_ITLINE1 << 0x18) | SYSCFG_ITLINE1_SR_PVDOUT)) /* Power voltage detection Interrupt */ -#define ITLINE_VDDIO2 ((uint32_t) ((SYSCFG_ITLINE1 << 0x18) | SYSCFG_ITLINE1_SR_VDDIO2)) /* VDDIO2 Interrupt */ -#define ITLINE_RTC_WAKEUP ((uint32_t) ((SYSCFG_ITLINE2 << 0x18) | SYSCFG_ITLINE2_SR_RTC_WAKEUP)) /* RTC WAKEUP -> exti[20] Interrupt */ -#define ITLINE_RTC_TSTAMP ((uint32_t) ((SYSCFG_ITLINE2 << 0x18) | SYSCFG_ITLINE2_SR_RTC_TSTAMP)) /* RTC Time Stamp -> exti[19] interrupt */ -#define ITLINE_RTC_ALRA ((uint32_t) ((SYSCFG_ITLINE2 << 0x18) | SYSCFG_ITLINE2_SR_RTC_ALRA)) /* RTC Alarm -> exti[17] interrupt */ -#define ITLINE_FLASH_ITF ((uint32_t) ((SYSCFG_ITLINE3 << 0x18) | SYSCFG_ITLINE3_SR_FLASH_ITF)) /* Flash ITF Interrupt */ -#define ITLINE_CRS ((uint32_t) ((SYSCFG_ITLINE4 << 0x18) | SYSCFG_ITLINE4_SR_CRS)) /* CRS Interrupt */ -#define ITLINE_CLK_CTRL ((uint32_t) ((SYSCFG_ITLINE4 << 0x18) | SYSCFG_ITLINE4_SR_CLK_CTRL)) /* CLK Control Interrupt */ -#define ITLINE_EXTI0 ((uint32_t) ((SYSCFG_ITLINE5 << 0x18) | SYSCFG_ITLINE5_SR_EXTI0)) /* External Interrupt 0 */ -#define ITLINE_EXTI1 ((uint32_t) ((SYSCFG_ITLINE5 << 0x18) | SYSCFG_ITLINE5_SR_EXTI1)) /* External Interrupt 1 */ -#define ITLINE_EXTI2 ((uint32_t) ((SYSCFG_ITLINE6 << 0x18) | SYSCFG_ITLINE6_SR_EXTI2)) /* External Interrupt 2 */ -#define ITLINE_EXTI3 ((uint32_t) ((SYSCFG_ITLINE6 << 0x18) | SYSCFG_ITLINE6_SR_EXTI3)) /* External Interrupt 3 */ -#define ITLINE_EXTI4 ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI4)) /* EXTI4 Interrupt */ -#define ITLINE_EXTI5 ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI5)) /* EXTI5 Interrupt */ -#define ITLINE_EXTI6 ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI6)) /* EXTI6 Interrupt */ -#define ITLINE_EXTI7 ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI7)) /* EXTI7 Interrupt */ -#define ITLINE_EXTI8 ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI8)) /* EXTI8 Interrupt */ -#define ITLINE_EXTI9 ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI9)) /* EXTI9 Interrupt */ -#define ITLINE_EXTI10 ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI10)) /* EXTI10 Interrupt */ -#define ITLINE_EXTI11 ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI11)) /* EXTI11 Interrupt */ -#define ITLINE_EXTI12 ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI12)) /* EXTI12 Interrupt */ -#define ITLINE_EXTI13 ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI13)) /* EXTI13 Interrupt */ -#define ITLINE_EXTI14 ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI14)) /* EXTI14 Interrupt */ -#define ITLINE_EXTI15 ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI15)) /* EXTI15 Interrupt */ -#define ITLINE_TSC_EOA ((uint32_t) ((SYSCFG_ITLINE8 << 0x18) | SYSCFG_ITLINE8_SR_TSC_EOA)) /* Touch control EOA Interrupt */ -#define ITLINE_TSC_MCE ((uint32_t) ((SYSCFG_ITLINE8 << 0x18) | SYSCFG_ITLINE8_SR_TSC_MCE)) /* Touch control MCE Interrupt */ -#define ITLINE_DMA1_CH1 ((uint32_t) ((SYSCFG_ITLINE9 << 0x18) | SYSCFG_ITLINE9_SR_DMA1_CH1)) /* DMA1 Channel 1 Interrupt */ -#define ITLINE_DMA1_CH2 ((uint32_t) ((SYSCFG_ITLINE10 << 0x18) | SYSCFG_ITLINE10_SR_DMA1_CH2)) /* DMA1 Channel 2 Interrupt */ -#define ITLINE_DMA1_CH3 ((uint32_t) ((SYSCFG_ITLINE10 << 0x18) | SYSCFG_ITLINE10_SR_DMA1_CH3)) /* DMA1 Channel 3 Interrupt */ -#define ITLINE_DMA2_CH1 ((uint32_t) ((SYSCFG_ITLINE10 << 0x18) | SYSCFG_ITLINE10_SR_DMA2_CH1)) /* DMA2 Channel 1 Interrupt */ -#define ITLINE_DMA2_CH2 ((uint32_t) ((SYSCFG_ITLINE10 << 0x18) | SYSCFG_ITLINE10_SR_DMA2_CH2)) /* DMA2 Channel 2 Interrupt */ -#define ITLINE_DMA1_CH4 ((uint32_t) ((SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA1_CH4)) /* DMA1 Channel 4 Interrupt */ -#define ITLINE_DMA1_CH5 ((uint32_t) ((SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA1_CH5)) /* DMA1 Channel 5 Interrupt */ -#define ITLINE_DMA1_CH6 ((uint32_t) ((SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA1_CH6)) /* DMA1 Channel 6 Interrupt */ -#define ITLINE_DMA1_CH7 ((uint32_t) ((SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA1_CH7)) /* DMA1 Channel 7 Interrupt */ -#define ITLINE_DMA2_CH3 ((uint32_t) ((SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA2_CH3)) /* DMA2 Channel 3 Interrupt */ -#define ITLINE_DMA2_CH4 ((uint32_t) ((SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA2_CH4)) /* DMA2 Channel 4 Interrupt */ -#define ITLINE_DMA2_CH5 ((uint32_t) ((SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA2_CH5)) /* DMA2 Channel 5 Interrupt */ -#define ITLINE_ADC ((uint32_t) ((SYSCFG_ITLINE12 << 0x18) | SYSCFG_ITLINE12_SR_ADC)) /* ADC Interrupt */ -#define ITLINE_COMP1 ((uint32_t) ((SYSCFG_ITLINE12 << 0x18) | SYSCFG_ITLINE12_SR_COMP1)) /* COMP1 Interrupt -> exti[21] */ -#define ITLINE_COMP2 ((uint32_t) ((SYSCFG_ITLINE12 << 0x18) | SYSCFG_ITLINE12_SR_COMP2)) /* COMP2 Interrupt -> exti[21] */ -#define ITLINE_TIM1_BRK ((uint32_t) ((SYSCFG_ITLINE13 << 0x18) | SYSCFG_ITLINE13_SR_TIM1_BRK)) /* TIM1 BRK Interrupt */ -#define ITLINE_TIM1_UPD ((uint32_t) ((SYSCFG_ITLINE13 << 0x18) | SYSCFG_ITLINE13_SR_TIM1_UPD)) /* TIM1 UPD Interrupt */ -#define ITLINE_TIM1_TRG ((uint32_t) ((SYSCFG_ITLINE13 << 0x18) | SYSCFG_ITLINE13_SR_TIM1_TRG)) /* TIM1 TRG Interrupt */ -#define ITLINE_TIM1_CCU ((uint32_t) ((SYSCFG_ITLINE13 << 0x18) | SYSCFG_ITLINE13_SR_TIM1_CCU)) /* TIM1 CCU Interrupt */ -#define ITLINE_TIM1_CC ((uint32_t) ((SYSCFG_ITLINE14 << 0x18) | SYSCFG_ITLINE14_SR_TIM1_CC)) /* TIM1 CC Interrupt */ -#define ITLINE_TIM2 ((uint32_t) ((SYSCFG_ITLINE15 << 0x18) | SYSCFG_ITLINE15_SR_TIM2_GLB)) /* TIM2 Interrupt */ -#define ITLINE_TIM3 ((uint32_t) ((SYSCFG_ITLINE16 << 0x18) | SYSCFG_ITLINE16_SR_TIM3_GLB)) /* TIM3 Interrupt */ -#define ITLINE_DAC ((uint32_t) ((SYSCFG_ITLINE17 << 0x18) | SYSCFG_ITLINE17_SR_DAC)) /* DAC Interrupt */ -#define ITLINE_TIM6 ((uint32_t) ((SYSCFG_ITLINE17 << 0x18) | SYSCFG_ITLINE17_SR_TIM6_GLB)) /* TIM6 Interrupt */ -#define ITLINE_TIM7 ((uint32_t) ((SYSCFG_ITLINE18 << 0x18) | SYSCFG_ITLINE18_SR_TIM7_GLB)) /* TIM7 Interrupt */ -#define ITLINE_TIM14 ((uint32_t) ((SYSCFG_ITLINE19 << 0x18) | SYSCFG_ITLINE19_SR_TIM14_GLB)) /* TIM14 Interrupt */ -#define ITLINE_TIM15 ((uint32_t) ((SYSCFG_ITLINE20 << 0x18) | SYSCFG_ITLINE20_SR_TIM15_GLB)) /* TIM15 Interrupt */ -#define ITLINE_TIM16 ((uint32_t) ((SYSCFG_ITLINE21 << 0x18) | SYSCFG_ITLINE21_SR_TIM16_GLB)) /* TIM16 Interrupt */ -#define ITLINE_TIM17 ((uint32_t) ((SYSCFG_ITLINE22 << 0x18) | SYSCFG_ITLINE22_SR_TIM17_GLB)) /* TIM17 Interrupt */ -#define ITLINE_I2C1 ((uint32_t) ((SYSCFG_ITLINE23 << 0x18) | SYSCFG_ITLINE23_SR_I2C1_GLB)) /* I2C1 Interrupt -> exti[23] */ -#define ITLINE_I2C2 ((uint32_t) ((SYSCFG_ITLINE24 << 0x18) | SYSCFG_ITLINE24_SR_I2C2_GLB)) /* I2C2 Interrupt */ -#define ITLINE_SPI1 ((uint32_t) ((SYSCFG_ITLINE25 << 0x18) | SYSCFG_ITLINE25_SR_SPI1)) /* I2C1 Interrupt -> exti[23] */ -#define ITLINE_SPI2 ((uint32_t) ((SYSCFG_ITLINE26 << 0x18) | SYSCFG_ITLINE26_SR_SPI2)) /* SPI1 Interrupt */ -#define ITLINE_USART1 ((uint32_t) ((SYSCFG_ITLINE27 << 0x18) | SYSCFG_ITLINE27_SR_USART1_GLB)) /*!< USART1 GLB Interrupt -> exti[25] */ -#define ITLINE_USART2 ((uint32_t) ((SYSCFG_ITLINE28 << 0x18) | SYSCFG_ITLINE28_SR_USART2_GLB)) /*!< USART2 GLB Interrupt -> exti[26] */ -#define ITLINE_USART3 ((uint32_t) ((SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART3_GLB)) /* USART3 Interrupt */ -#define ITLINE_USART4 ((uint32_t) ((SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART4_GLB)) /* USART4 Interrupt */ -#define ITLINE_USART5 ((uint32_t) ((SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART5_GLB)) /* USART5 Interrupt */ -#define ITLINE_USART6 ((uint32_t) ((SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART6_GLB)) /* USART6 Interrupt */ -#define ITLINE_USART7 ((uint32_t) ((SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART7_GLB)) /* USART7 Interrupt */ -#define ITLINE_USART8 ((uint32_t) ((SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART8_GLB)) /* USART8 Interrupt */ -#define ITLINE_CAN ((uint32_t) ((SYSCFG_ITLINE30 << 0x18) | SYSCFG_ITLINE30_SR_CAN)) /* CAN Interrupt */ -#define ITLINE_CEC ((uint32_t) ((SYSCFG_ITLINE30 << 0x18) | SYSCFG_ITLINE30_SR_CEC)) /* CEC Interrupt -> exti[27] */ - -#define IS_SYSCFG_ITLINE(LINE) (((LINE) == ITLINE_EWDG) || \ - ((LINE) == ITLINE_PVDOUT) || \ - ((LINE) == ITLINE_VDDIO2) || \ - ((LINE) == ITLINE_RTC_WAKEUP) || \ - ((LINE) == ITLINE_RTC_TSTAMP) || \ - ((LINE) == ITLINE_RTC_ALRA) || \ - ((LINE) == ITLINE_FLASH_ITF) || \ - ((LINE) == ITLINE_CRS) || \ - ((LINE) == ITLINE_CLK_CTRL) || \ - ((LINE) == ITLINE_EXTI0) || \ - ((LINE) == ITLINE_EXTI1) || \ - ((LINE) == ITLINE_EXTI2) || \ - ((LINE) == ITLINE_EXTI3) || \ - ((LINE) == ITLINE_EXTI4) || \ - ((LINE) == ITLINE_EXTI5) || \ - ((LINE) == ITLINE_EXTI6) || \ - ((LINE) == ITLINE_EXTI7) || \ - ((LINE) == ITLINE_EXTI8) || \ - ((LINE) == ITLINE_EXTI9) || \ - ((LINE) == ITLINE_EXTI10) || \ - ((LINE) == ITLINE_EXTI11) || \ - ((LINE) == ITLINE_EXTI12) || \ - ((LINE) == ITLINE_EXTI13) || \ - ((LINE) == ITLINE_EXTI14) || \ - ((LINE) == ITLINE_EXTI15) || \ - ((LINE) == ITLINE_TSC_EOA) || \ - ((LINE) == ITLINE_TSC_MCE) || \ - ((LINE) == ITLINE_DMA1_CH1) || \ - ((LINE) == ITLINE_DMA1_CH2) || \ - ((LINE) == ITLINE_DMA1_CH3) || \ - ((LINE) == ITLINE_DMA1_CH4) || \ - ((LINE) == ITLINE_DMA1_CH5) || \ - ((LINE) == ITLINE_DMA1_CH6) || \ - ((LINE) == ITLINE_DMA1_CH7) || \ - ((LINE) == ITLINE_DMA2_CH1) || \ - ((LINE) == ITLINE_DMA2_CH2) || \ - ((LINE) == ITLINE_DMA2_CH3) || \ - ((LINE) == ITLINE_DMA2_CH4) || \ - ((LINE) == ITLINE_DMA2_CH5) || \ - ((LINE) == ITLINE_ADC) || \ - ((LINE) == ITLINE_COMP1) || \ - ((LINE) == ITLINE_COMP2) || \ - ((LINE) == ITLINE_TIM1_BRK) || \ - ((LINE) == ITLINE_TIM1_UPD) || \ - ((LINE) == ITLINE_TIM1_TRG) || \ - ((LINE) == ITLINE_TIM1_CCU) || \ - ((LINE) == ITLINE_TIM1_CC) || \ - ((LINE) == ITLINE_TIM2) || \ - ((LINE) == ITLINE_TIM3) || \ - ((LINE) == ITLINE_DAC) || \ - ((LINE) == ITLINE_TIM6) || \ - ((LINE) == ITLINE_TIM7) || \ - ((LINE) == ITLINE_TIM14) || \ - ((LINE) == ITLINE_TIM15) || \ - ((LINE) == ITLINE_TIM16) || \ - ((LINE) == ITLINE_TIM17) || \ - ((LINE) == ITLINE_I2C1) || \ - ((LINE) == ITLINE_I2C2) || \ - ((LINE) == ITLINE_SPI1) || \ - ((LINE) == ITLINE_SPI2) || \ - ((LINE) == ITLINE_USART1) || \ - ((LINE) == ITLINE_USART2) || \ - ((LINE) == ITLINE_USART3) || \ - ((LINE) == ITLINE_USART4) || \ - ((LINE) == ITLINE_USART5) || \ - ((LINE) == ITLINE_USART6) || \ - ((LINE) == ITLINE_USART7) || \ - ((LINE) == ITLINE_USART8) || \ - ((LINE) == ITLINE_CAN) || \ - ((LINE) == ITLINE_CEC)) - -/** - * @} - */ -/** @defgroup IRDA_ENV_SEL - * @{ - */ -#define SYSCFG_IRDA_ENV_SEL_TIM16 (SYSCFG_CFGR1_IRDA_ENV_SEL_0&SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* Timer16 is selected as IRDA Modulation envelope source */ -#define SYSCFG_IRDA_ENV_SEL_USART1 (SYSCFG_CFGR1_IRDA_ENV_SEL_0) /* USART1 is selected as IRDA Modulation envelope source.*/ -#define SYSCFG_IRDA_ENV_SEL_USART4 (SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* USART4 is selected as IRDA Modulation envelope source.*/ - -#define IS_SYSCFG_IRDA_ENV(ENV) (((ENV) == SYSCFG_IRDA_ENV_SEL_TIM16) || \ - ((ENV) == SYSCFG_IRDA_ENV_SEL_USART1) || \ - ((ENV) == SYSCFG_IRDA_ENV_SEL_USART4)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Function used to set the SYSCFG configuration to the default reset state **/ -void SYSCFG_DeInit(void); - -/* SYSCFG configuration functions *********************************************/ -void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap); -void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState); -void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState); -void SYSCFG_IRDAEnvSelection(uint32_t SYSCFG_IRDAEnv); -void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex); -uint32_t SYSCFG_GetPendingIT(uint32_t ITSourceLine); -void SYSCFG_BreakConfig(uint32_t SYSCFG_Break); -FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag); -void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F0XX_SYSCFG_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_tim.h b/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_tim.h deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_tim.h +++ /dev/null @@ -1,1186 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_tim.h - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file contains all the functions prototypes for the TIM - * firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0XX_TIM_H -#define __STM32F0XX_TIM_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup TIM - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief TIM Time Base Init structure definition - * @note This sturcture is used with all TIMx. - */ - -typedef struct -{ - uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. - This parameter can be a number between 0x0000 and 0xFFFF */ - - uint16_t TIM_CounterMode; /*!< Specifies the counter mode. - This parameter can be a value of @ref TIM_Counter_Mode */ - - uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active - Auto-Reload Register at the next update event. - This parameter must be a number between 0x0000 and 0xFFFF. */ - - uint16_t TIM_ClockDivision; /*!< Specifies the clock division. - This parameter can be a value of @ref TIM_Clock_Division_CKD */ - - uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter - reaches zero, an update event is generated and counting restarts - from the RCR value (N). - This means in PWM mode that (N+1) corresponds to: - - the number of PWM periods in edge-aligned mode - - the number of half PWM period in center-aligned mode - This parameter must be a number between 0x00 and 0xFF. - @note This parameter is valid only for TIM1. */ -} TIM_TimeBaseInitTypeDef; - -/** - * @brief TIM Output Compare Init structure definition - */ - -typedef struct -{ - uint16_t TIM_OCMode; /*!< Specifies the TIM mode. - This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - - uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state. - This parameter can be a value of @ref TIM_Output_Compare_state */ - - uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state. - This parameter can be a value of @ref TIM_Output_Compare_N_state - @note This parameter is valid only for TIM1. */ - - uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between 0x0000 and 0xFFFF ( or 0xFFFFFFFF - for TIM2) */ - - uint16_t TIM_OCPolarity; /*!< Specifies the output polarity. - This parameter can be a value of @ref TIM_Output_Compare_Polarity */ - - uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity. - This parameter can be a value of @ref TIM_Output_Compare_N_Polarity - @note This parameter is valid only for TIM1. */ - - uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for TIM1. */ - - uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State - @note This parameter is valid only for TIM1. */ -} TIM_OCInitTypeDef; - -/** - * @brief TIM Input Capture Init structure definition - */ - -typedef struct -{ - - uint16_t TIM_Channel; /*!< Specifies the TIM channel. - This parameter can be a value of @ref TIM_Channel */ - - uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint16_t TIM_ICSelection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint16_t TIM_ICFilter; /*!< Specifies the input capture filter. - This parameter can be a number between 0x0 and 0xF */ -} TIM_ICInitTypeDef; - -/** - * @brief TIM_BDTR structure definition - * @note This sturcture is used only with TIM1. - */ - -typedef struct -{ - - uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode. - This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ - - uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state. - This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ - - uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters. - This parameter can be a value of @ref TIM_Lock_level */ - - uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the - switching-on of the outputs. - This parameter can be a number between 0x00 and 0xFF */ - - uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. - This parameter can be a value of @ref TIM_Break_Input_enable_disable */ - - uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. - This parameter can be a value of @ref TIM_Break_Polarity */ - - uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. - This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ -} TIM_BDTRInitTypeDef; - -/** - * @brief TIM Input Capture Init structure definition - */ - -/* Exported constants --------------------------------------------------------*/ - - -/** @defgroup TIM_Exported_constants - * @{ - */ - -#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM6) || \ - ((PERIPH) == TIM7) || \ - ((PERIPH) == TIM14)|| \ - ((PERIPH) == TIM15)|| \ - ((PERIPH) == TIM16)|| \ - ((PERIPH) == TIM17)) - -/* LIST1: TIM 1 */ -#define IS_TIM_LIST1_PERIPH(PERIPH) ((PERIPH) == TIM1) - -/* LIST2: TIM 1, 15, 16 and 17 */ -#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM15)|| \ - ((PERIPH) == TIM16)|| \ - ((PERIPH) == TIM17)) - -/* LIST3: TIM 1, 2 and 3 */ -#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3)) - -/* LIST4: TIM 1, 2, 3, 14, 15, 16 and 17 */ -#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM14) || \ - ((PERIPH) == TIM15)|| \ - ((PERIPH) == TIM16)|| \ - ((PERIPH) == TIM17)) - -/* LIST5: TIM 1, 2, 3, 15, 16 and 17 */ -#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM15)|| \ - ((PERIPH) == TIM16)|| \ - ((PERIPH) == TIM17)) - -/* LIST6: TIM 1, 2, 3 and 15 */ -#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM15)) - -/* LIST7: TIM 1, 2, 3, 6, 7 and 14 */ -#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM6) || \ - ((PERIPH) == TIM7) || \ - ((PERIPH) == TIM14)) - -/* LIST8: TIM 1, 2, 3 and 14 */ -#define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM14)) - -/* LIST9: TIM 1, 2, 3, 6, 7 and 15 */ -#define IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM6) || \ - ((PERIPH) == TIM7) || \ - ((PERIPH) == TIM15)) - -/* LIST10: TIM 1, 2, 3, 6, 7, 15, 16 and 17 */ -#define IS_TIM_LIST10_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM6) || \ - ((PERIPH) == TIM7) || \ - ((PERIPH) == TIM15)|| \ - ((PERIPH) == TIM16)|| \ - ((PERIPH) == TIM17)) - -/* LIST1: TIM 11 */ -#define IS_TIM_LIST11_PERIPH(PERIPH) ((PERIPH) == TIM14) - - -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_and_PWM_modes - * @{ - */ - -#define TIM_OCMode_Timing ((uint16_t)0x0000) -#define TIM_OCMode_Active ((uint16_t)0x0010) -#define TIM_OCMode_Inactive ((uint16_t)0x0020) -#define TIM_OCMode_Toggle ((uint16_t)0x0030) -#define TIM_OCMode_PWM1 ((uint16_t)0x0060) -#define TIM_OCMode_PWM2 ((uint16_t)0x0070) -#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ - ((MODE) == TIM_OCMode_Active) || \ - ((MODE) == TIM_OCMode_Inactive) || \ - ((MODE) == TIM_OCMode_Toggle)|| \ - ((MODE) == TIM_OCMode_PWM1) || \ - ((MODE) == TIM_OCMode_PWM2)) -#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ - ((MODE) == TIM_OCMode_Active) || \ - ((MODE) == TIM_OCMode_Inactive) || \ - ((MODE) == TIM_OCMode_Toggle)|| \ - ((MODE) == TIM_OCMode_PWM1) || \ - ((MODE) == TIM_OCMode_PWM2) || \ - ((MODE) == TIM_ForcedAction_Active) || \ - ((MODE) == TIM_ForcedAction_InActive)) -/** - * @} - */ - -/** @defgroup TIM_One_Pulse_Mode - * @{ - */ - -#define TIM_OPMode_Single ((uint16_t)0x0008) -#define TIM_OPMode_Repetitive ((uint16_t)0x0000) -#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ - ((MODE) == TIM_OPMode_Repetitive)) -/** - * @} - */ - -/** @defgroup TIM_Channel - * @{ - */ - -#define TIM_Channel_1 ((uint16_t)0x0000) -#define TIM_Channel_2 ((uint16_t)0x0004) -#define TIM_Channel_3 ((uint16_t)0x0008) -#define TIM_Channel_4 ((uint16_t)0x000C) - -#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ - ((CHANNEL) == TIM_Channel_2) || \ - ((CHANNEL) == TIM_Channel_3) || \ - ((CHANNEL) == TIM_Channel_4)) -#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ - ((CHANNEL) == TIM_Channel_2) || \ - ((CHANNEL) == TIM_Channel_3)) -#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ - ((CHANNEL) == TIM_Channel_2)) - -/** - * @} - */ - -/** @defgroup TIM_Clock_Division_CKD - * @{ - */ - -#define TIM_CKD_DIV1 ((uint16_t)0x0000) -#define TIM_CKD_DIV2 ((uint16_t)0x0100) -#define TIM_CKD_DIV4 ((uint16_t)0x0200) -#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ - ((DIV) == TIM_CKD_DIV2) || \ - ((DIV) == TIM_CKD_DIV4)) -/** - * @} - */ - -/** @defgroup TIM_Counter_Mode - * @{ - */ - -#define TIM_CounterMode_Up ((uint16_t)0x0000) -#define TIM_CounterMode_Down ((uint16_t)0x0010) -#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) -#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) -#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) -#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ - ((MODE) == TIM_CounterMode_Down) || \ - ((MODE) == TIM_CounterMode_CenterAligned1) || \ - ((MODE) == TIM_CounterMode_CenterAligned2) || \ - ((MODE) == TIM_CounterMode_CenterAligned3)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Polarity - * @{ - */ - -#define TIM_OCPolarity_High ((uint16_t)0x0000) -#define TIM_OCPolarity_Low ((uint16_t)0x0002) -#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ - ((POLARITY) == TIM_OCPolarity_Low)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_Polarity - * @{ - */ - -#define TIM_OCNPolarity_High ((uint16_t)0x0000) -#define TIM_OCNPolarity_Low ((uint16_t)0x0008) -#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \ - ((POLARITY) == TIM_OCNPolarity_Low)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_state - * @{ - */ - -#define TIM_OutputState_Disable ((uint16_t)0x0000) -#define TIM_OutputState_Enable ((uint16_t)0x0001) -#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ - ((STATE) == TIM_OutputState_Enable)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_state - * @{ - */ - -#define TIM_OutputNState_Disable ((uint16_t)0x0000) -#define TIM_OutputNState_Enable ((uint16_t)0x0004) -#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ - ((STATE) == TIM_OutputNState_Enable)) -/** - * @} - */ - -/** @defgroup TIM_Capture_Compare_state - * @{ - */ - -#define TIM_CCx_Enable ((uint16_t)0x0001) -#define TIM_CCx_Disable ((uint16_t)0x0000) -#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ - ((CCX) == TIM_CCx_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Capture_Compare_N_state - * @{ - */ - -#define TIM_CCxN_Enable ((uint16_t)0x0004) -#define TIM_CCxN_Disable ((uint16_t)0x0000) -#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \ - ((CCXN) == TIM_CCxN_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Break_Input_enable_disable - * @{ - */ - -#define TIM_Break_Enable ((uint16_t)0x1000) -#define TIM_Break_Disable ((uint16_t)0x0000) -#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ - ((STATE) == TIM_Break_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Break_Polarity - * @{ - */ - -#define TIM_BreakPolarity_Low ((uint16_t)0x0000) -#define TIM_BreakPolarity_High ((uint16_t)0x2000) -#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \ - ((POLARITY) == TIM_BreakPolarity_High)) -/** - * @} - */ - -/** @defgroup TIM_AOE_Bit_Set_Reset - * @{ - */ - -#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) -#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) -#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \ - ((STATE) == TIM_AutomaticOutput_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Lock_level - * @{ - */ - -#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) -#define TIM_LOCKLevel_1 ((uint16_t)0x0100) -#define TIM_LOCKLevel_2 ((uint16_t)0x0200) -#define TIM_LOCKLevel_3 ((uint16_t)0x0300) -#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \ - ((LEVEL) == TIM_LOCKLevel_1) || \ - ((LEVEL) == TIM_LOCKLevel_2) || \ - ((LEVEL) == TIM_LOCKLevel_3)) -/** - * @} - */ - -/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state - * @{ - */ - -#define TIM_OSSIState_Enable ((uint16_t)0x0400) -#define TIM_OSSIState_Disable ((uint16_t)0x0000) -#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ - ((STATE) == TIM_OSSIState_Disable)) -/** - * @} - */ - -/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state - * @{ - */ - -#define TIM_OSSRState_Enable ((uint16_t)0x0800) -#define TIM_OSSRState_Disable ((uint16_t)0x0000) -#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ - ((STATE) == TIM_OSSRState_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Idle_State - * @{ - */ - -#define TIM_OCIdleState_Set ((uint16_t)0x0100) -#define TIM_OCIdleState_Reset ((uint16_t)0x0000) -#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ - ((STATE) == TIM_OCIdleState_Reset)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_Idle_State - * @{ - */ - -#define TIM_OCNIdleState_Set ((uint16_t)0x0200) -#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) -#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ - ((STATE) == TIM_OCNIdleState_Reset)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Polarity - * @{ - */ - -#define TIM_ICPolarity_Rising ((uint16_t)0x0000) -#define TIM_ICPolarity_Falling ((uint16_t)0x0002) -#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) -#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ - ((POLARITY) == TIM_ICPolarity_Falling)|| \ - ((POLARITY) == TIM_ICPolarity_BothEdge)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Selection - * @{ - */ - -#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC1, IC2, IC3 or IC4, respectively */ -#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC2, IC1, IC4 or IC3, respectively. */ -#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ -#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ - ((SELECTION) == TIM_ICSelection_IndirectTI) || \ - ((SELECTION) == TIM_ICSelection_TRC)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Prescaler - * @{ - */ - -#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */ -#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */ -#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */ -#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */ -#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ - ((PRESCALER) == TIM_ICPSC_DIV2) || \ - ((PRESCALER) == TIM_ICPSC_DIV4) || \ - ((PRESCALER) == TIM_ICPSC_DIV8)) -/** - * @} - */ - -/** @defgroup TIM_interrupt_sources - * @{ - */ - -#define TIM_IT_Update ((uint16_t)0x0001) -#define TIM_IT_CC1 ((uint16_t)0x0002) -#define TIM_IT_CC2 ((uint16_t)0x0004) -#define TIM_IT_CC3 ((uint16_t)0x0008) -#define TIM_IT_CC4 ((uint16_t)0x0010) -#define TIM_IT_COM ((uint16_t)0x0020) -#define TIM_IT_Trigger ((uint16_t)0x0040) -#define TIM_IT_Break ((uint16_t)0x0080) -#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) - -#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ - ((IT) == TIM_IT_CC1) || \ - ((IT) == TIM_IT_CC2) || \ - ((IT) == TIM_IT_CC3) || \ - ((IT) == TIM_IT_CC4) || \ - ((IT) == TIM_IT_COM) || \ - ((IT) == TIM_IT_Trigger) || \ - ((IT) == TIM_IT_Break)) -/** - * @} - */ - -/** @defgroup TIM_DMA_Base_address - * @{ - */ - -#define TIM_DMABase_CR1 ((uint16_t)0x0000) -#define TIM_DMABase_CR2 ((uint16_t)0x0001) -#define TIM_DMABase_SMCR ((uint16_t)0x0002) -#define TIM_DMABase_DIER ((uint16_t)0x0003) -#define TIM_DMABase_SR ((uint16_t)0x0004) -#define TIM_DMABase_EGR ((uint16_t)0x0005) -#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) -#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) -#define TIM_DMABase_CCER ((uint16_t)0x0008) -#define TIM_DMABase_CNT ((uint16_t)0x0009) -#define TIM_DMABase_PSC ((uint16_t)0x000A) -#define TIM_DMABase_ARR ((uint16_t)0x000B) -#define TIM_DMABase_RCR ((uint16_t)0x000C) -#define TIM_DMABase_CCR1 ((uint16_t)0x000D) -#define TIM_DMABase_CCR2 ((uint16_t)0x000E) -#define TIM_DMABase_CCR3 ((uint16_t)0x000F) -#define TIM_DMABase_CCR4 ((uint16_t)0x0010) -#define TIM_DMABase_BDTR ((uint16_t)0x0011) -#define TIM_DMABase_DCR ((uint16_t)0x0012) -#define TIM_DMABase_OR ((uint16_t)0x0013) -#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ - ((BASE) == TIM_DMABase_CR2) || \ - ((BASE) == TIM_DMABase_SMCR) || \ - ((BASE) == TIM_DMABase_DIER) || \ - ((BASE) == TIM_DMABase_SR) || \ - ((BASE) == TIM_DMABase_EGR) || \ - ((BASE) == TIM_DMABase_CCMR1) || \ - ((BASE) == TIM_DMABase_CCMR2) || \ - ((BASE) == TIM_DMABase_CCER) || \ - ((BASE) == TIM_DMABase_CNT) || \ - ((BASE) == TIM_DMABase_PSC) || \ - ((BASE) == TIM_DMABase_ARR) || \ - ((BASE) == TIM_DMABase_RCR) || \ - ((BASE) == TIM_DMABase_CCR1) || \ - ((BASE) == TIM_DMABase_CCR2) || \ - ((BASE) == TIM_DMABase_CCR3) || \ - ((BASE) == TIM_DMABase_CCR4) || \ - ((BASE) == TIM_DMABase_BDTR) || \ - ((BASE) == TIM_DMABase_DCR) || \ - ((BASE) == TIM_DMABase_OR)) -/** - * @} - */ - - -/** @defgroup TIM_DMA_Burst_Length - * @{ - */ - -#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) -#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) -#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) -#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) -#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) -#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) -#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) -#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) -#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) -#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) -#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) -#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) -#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) -#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) -#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) -#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) -#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) -#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) -#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \ - ((LENGTH) == TIM_DMABurstLength_2Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_3Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_4Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_5Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_6Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_7Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_8Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_9Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_10Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_11Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_12Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_13Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_14Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_15Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_16Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_17Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_18Transfers)) -/** - * @} - */ - -/** @defgroup TIM_DMA_sources - * @{ - */ - -#define TIM_DMA_Update ((uint16_t)0x0100) -#define TIM_DMA_CC1 ((uint16_t)0x0200) -#define TIM_DMA_CC2 ((uint16_t)0x0400) -#define TIM_DMA_CC3 ((uint16_t)0x0800) -#define TIM_DMA_CC4 ((uint16_t)0x1000) -#define TIM_DMA_COM ((uint16_t)0x2000) -#define TIM_DMA_Trigger ((uint16_t)0x4000) -#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) - -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Prescaler - * @{ - */ - -#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) -#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) -#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) -#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) -#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) -/** - * @} - */ - -/** @defgroup TIM_Internal_Trigger_Selection - * @{ - */ - -#define TIM_TS_ITR0 ((uint16_t)0x0000) -#define TIM_TS_ITR1 ((uint16_t)0x0010) -#define TIM_TS_ITR2 ((uint16_t)0x0020) -#define TIM_TS_ITR3 ((uint16_t)0x0030) -#define TIM_TS_TI1F_ED ((uint16_t)0x0040) -#define TIM_TS_TI1FP1 ((uint16_t)0x0050) -#define TIM_TS_TI2FP2 ((uint16_t)0x0060) -#define TIM_TS_ETRF ((uint16_t)0x0070) -#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3) || \ - ((SELECTION) == TIM_TS_TI1F_ED) || \ - ((SELECTION) == TIM_TS_TI1FP1) || \ - ((SELECTION) == TIM_TS_TI2FP2) || \ - ((SELECTION) == TIM_TS_ETRF)) -#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3)) -/** - * @} - */ - -/** @defgroup TIM_TIx_External_Clock_Source - * @{ - */ - -#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) -#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) -#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) - -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Polarity - * @{ - */ -#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) -#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) -#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ - ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) -/** - * @} - */ - -/** @defgroup TIM_Prescaler_Reload_Mode - * @{ - */ - -#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) -#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) -#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ - ((RELOAD) == TIM_PSCReloadMode_Immediate)) -/** - * @} - */ - -/** @defgroup TIM_Forced_Action - * @{ - */ - -#define TIM_ForcedAction_Active ((uint16_t)0x0050) -#define TIM_ForcedAction_InActive ((uint16_t)0x0040) -#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ - ((ACTION) == TIM_ForcedAction_InActive)) -/** - * @} - */ - -/** @defgroup TIM_Encoder_Mode - * @{ - */ - -#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) -#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) -#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) -#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ - ((MODE) == TIM_EncoderMode_TI2) || \ - ((MODE) == TIM_EncoderMode_TI12)) -/** - * @} - */ - - -/** @defgroup TIM_Event_Source - * @{ - */ - -#define TIM_EventSource_Update ((uint16_t)0x0001) -#define TIM_EventSource_CC1 ((uint16_t)0x0002) -#define TIM_EventSource_CC2 ((uint16_t)0x0004) -#define TIM_EventSource_CC3 ((uint16_t)0x0008) -#define TIM_EventSource_CC4 ((uint16_t)0x0010) -#define TIM_EventSource_COM ((uint16_t)0x0020) -#define TIM_EventSource_Trigger ((uint16_t)0x0040) -#define TIM_EventSource_Break ((uint16_t)0x0080) -#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) - -/** - * @} - */ - -/** @defgroup TIM_Update_Source - * @{ - */ - -#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow - or the setting of UG bit, or an update generation - through the slave mode controller. */ -#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ -#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ - ((SOURCE) == TIM_UpdateSource_Regular)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Preload_State - * @{ - */ - -#define TIM_OCPreload_Enable ((uint16_t)0x0008) -#define TIM_OCPreload_Disable ((uint16_t)0x0000) -#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ - ((STATE) == TIM_OCPreload_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Fast_State - * @{ - */ - -#define TIM_OCFast_Enable ((uint16_t)0x0004) -#define TIM_OCFast_Disable ((uint16_t)0x0000) -#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ - ((STATE) == TIM_OCFast_Disable)) - -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Clear_State - * @{ - */ - -#define TIM_OCClear_Enable ((uint16_t)0x0080) -#define TIM_OCClear_Disable ((uint16_t)0x0000) -#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ - ((STATE) == TIM_OCClear_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Trigger_Output_Source - * @{ - */ - -#define TIM_TRGOSource_Reset ((uint16_t)0x0000) -#define TIM_TRGOSource_Enable ((uint16_t)0x0010) -#define TIM_TRGOSource_Update ((uint16_t)0x0020) -#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) -#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) -#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) -#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) -#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) -#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ - ((SOURCE) == TIM_TRGOSource_Enable) || \ - ((SOURCE) == TIM_TRGOSource_Update) || \ - ((SOURCE) == TIM_TRGOSource_OC1) || \ - ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC4Ref)) -/** - * @} - */ - -/** @defgroup TIM_Slave_Mode - * @{ - */ - -#define TIM_SlaveMode_Reset ((uint16_t)0x0004) -#define TIM_SlaveMode_Gated ((uint16_t)0x0005) -#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) -#define TIM_SlaveMode_External1 ((uint16_t)0x0007) -#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ - ((MODE) == TIM_SlaveMode_Gated) || \ - ((MODE) == TIM_SlaveMode_Trigger) || \ - ((MODE) == TIM_SlaveMode_External1)) -/** - * @} - */ - -/** @defgroup TIM_Master_Slave_Mode - * @{ - */ - -#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) -#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) -#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ - ((STATE) == TIM_MasterSlaveMode_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Flags - * @{ - */ - -#define TIM_FLAG_Update ((uint16_t)0x0001) -#define TIM_FLAG_CC1 ((uint16_t)0x0002) -#define TIM_FLAG_CC2 ((uint16_t)0x0004) -#define TIM_FLAG_CC3 ((uint16_t)0x0008) -#define TIM_FLAG_CC4 ((uint16_t)0x0010) -#define TIM_FLAG_COM ((uint16_t)0x0020) -#define TIM_FLAG_Trigger ((uint16_t)0x0040) -#define TIM_FLAG_Break ((uint16_t)0x0080) -#define TIM_FLAG_CC1OF ((uint16_t)0x0200) -#define TIM_FLAG_CC2OF ((uint16_t)0x0400) -#define TIM_FLAG_CC3OF ((uint16_t)0x0800) -#define TIM_FLAG_CC4OF ((uint16_t)0x1000) -#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \ - ((FLAG) == TIM_FLAG_CC1) || \ - ((FLAG) == TIM_FLAG_CC2) || \ - ((FLAG) == TIM_FLAG_CC3) || \ - ((FLAG) == TIM_FLAG_CC4) || \ - ((FLAG) == TIM_FLAG_COM) || \ - ((FLAG) == TIM_FLAG_Trigger) || \ - ((FLAG) == TIM_FLAG_Break) || \ - ((FLAG) == TIM_FLAG_CC1OF) || \ - ((FLAG) == TIM_FLAG_CC2OF) || \ - ((FLAG) == TIM_FLAG_CC3OF) || \ - ((FLAG) == TIM_FLAG_CC4OF)) - - -#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000)) -/** - * @} - */ - - -/** @defgroup TIM_Input_Capture_Filer_Value - * @{ - */ - -#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Filter - * @{ - */ - -#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) -/** - * @} - */ - -/** @defgroup TIM_OCReferenceClear - * @{ - */ -#define TIM_OCReferenceClear_ETRF ((uint16_t)0x0008) -#define TIM_OCReferenceClear_OCREFCLR ((uint16_t)0x0000) -#define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) || \ - ((SOURCE) == TIM_OCReferenceClear_OCREFCLR)) - -/** - * @} - */ -/** @defgroup TIM_Remap - * @{ - */ -#define TIM14_GPIO ((uint16_t)0x0000) -#define TIM14_RTC_CLK ((uint16_t)0x0001) -#define TIM14_HSEDiv32 ((uint16_t)0x0002) -#define TIM14_MCO ((uint16_t)0x0003) - -#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM14_GPIO)|| \ - ((TIM_REMAP) == TIM14_RTC_CLK) || \ - ((TIM_REMAP) == TIM14_HSEDiv32) || \ - ((TIM_REMAP) == TIM14_MCO)) -/** - * @} - */ - -/** @defgroup TIM_Legacy - * @{ - */ - -#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer -#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers -#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers -#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers -#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers -#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers -#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers -#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers -#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers -#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers -#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers -#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers -#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers -#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers -#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers -#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers -#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers -#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* TimeBase management ********************************************************/ -void TIM_DeInit(TIM_TypeDef* TIMx); -void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); -void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); -void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); -void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter); -void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload); -uint32_t TIM_GetCounter(TIM_TypeDef* TIMx); -uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); -void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); -void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); -void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); -void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); - -/* Advanced-control timers (TIM1) specific features*******************/ -void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); -void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); -void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); - -/* Output Compare management **************************************************/ -void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); -void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1); -void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2); -void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3); -void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4); -void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear); -void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); -void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); -void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); - -/* Input Capture management ***************************************************/ -void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); -void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); -void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); -uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx); -uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx); -uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx); -uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx); -void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); - -/* Interrupts, DMA and flags management ***************************************/ -void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); -void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); -FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); -void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); -ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); -void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); -void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); -void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); -void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); - -/* Clocks management **********************************************************/ -void TIM_InternalClockConfig(TIM_TypeDef* TIMx); -void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); -void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, - uint16_t TIM_ICPolarity, uint16_t ICFilter); -void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); -void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); - - -/* Synchronization management *************************************************/ -void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); -void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); -void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); -void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); -void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); - -/* Specific interface management **********************************************/ -void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, - uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); -void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); - -/* Specific remapping management **********************************************/ -void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap); - - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F0XX_TIM_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_usart.h b/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_usart.h deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_usart.h +++ /dev/null @@ -1,604 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_usart.h - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file contains all the functions prototypes for the USART - * firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0XX_USART_H -#define __STM32F0XX_USART_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup USART - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - - - -/** - * @brief USART Init Structure definition - */ - -typedef struct -{ - uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate. - The baud rate is computed using the following formula: - - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) - - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */ - - uint32_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref USART_Word_Length */ - - uint32_t USART_StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref USART_Stop_Bits */ - - uint32_t USART_Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref USART_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ - - uint32_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref USART_Mode */ - - uint32_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled - or disabled. - This parameter can be a value of @ref USART_Hardware_Flow_Control*/ -} USART_InitTypeDef; - -/** - * @brief USART Clock Init Structure definition - */ - -typedef struct -{ - uint32_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled. - This parameter can be a value of @ref USART_Clock */ - - uint32_t USART_CPOL; /*!< Specifies the steady state of the serial clock. - This parameter can be a value of @ref USART_Clock_Polarity */ - - uint32_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref USART_Clock_Phase */ - - uint32_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted - data bit (MSB) has to be output on the SCLK pin in synchronous mode. - This parameter can be a value of @ref USART_Last_Bit */ -} USART_ClockInitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup USART_Exported_Constants - * @{ - */ - -#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \ - ((PERIPH) == USART2) || \ - ((PERIPH) == USART3) || \ - ((PERIPH) == USART4) || \ - ((PERIPH) == USART5) || \ - ((PERIPH) == USART6) || \ - ((PERIPH) == USART7) || \ - ((PERIPH) == USART8)) - -#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \ - ((PERIPH) == USART2) || \ - ((PERIPH) == USART3)) - -/** @defgroup USART_Word_Length - * @{ - */ - -#define USART_WordLength_8b ((uint32_t)0x00000000) -#define USART_WordLength_9b USART_CR1_M /* should be ((uint32_t)0x00001000) */ -#define USART_WordLength_7b ((uint32_t)0x10001000) /*!< only available for STM32F072 and STM32F030 devices */ -#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \ - ((LENGTH) == USART_WordLength_9b) || \ - ((LENGTH) == USART_WordLength_7b)) -/** - * @} - */ - -/** @defgroup USART_Stop_Bits - * @{ - */ - -#define USART_StopBits_1 ((uint32_t)0x00000000) -#define USART_StopBits_2 USART_CR2_STOP_1 -#define USART_StopBits_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) -#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \ - ((STOPBITS) == USART_StopBits_2) || \ - ((STOPBITS) == USART_StopBits_1_5)) -/** - * @} - */ - -/** @defgroup USART_Parity - * @{ - */ - -#define USART_Parity_No ((uint32_t)0x00000000) -#define USART_Parity_Even USART_CR1_PCE -#define USART_Parity_Odd (USART_CR1_PCE | USART_CR1_PS) -#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \ - ((PARITY) == USART_Parity_Even) || \ - ((PARITY) == USART_Parity_Odd)) -/** - * @} - */ - -/** @defgroup USART_Mode - * @{ - */ - -#define USART_Mode_Rx USART_CR1_RE -#define USART_Mode_Tx USART_CR1_TE -#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFFFFFF3) == 0x00) && \ - ((MODE) != (uint32_t)0x00)) -/** - * @} - */ - -/** @defgroup USART_Hardware_Flow_Control - * @{ - */ - -#define USART_HardwareFlowControl_None ((uint32_t)0x00000000) -#define USART_HardwareFlowControl_RTS USART_CR3_RTSE -#define USART_HardwareFlowControl_CTS USART_CR3_CTSE -#define USART_HardwareFlowControl_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) -#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ - (((CONTROL) == USART_HardwareFlowControl_None) || \ - ((CONTROL) == USART_HardwareFlowControl_RTS) || \ - ((CONTROL) == USART_HardwareFlowControl_CTS) || \ - ((CONTROL) == USART_HardwareFlowControl_RTS_CTS)) -/** - * @} - */ - -/** @defgroup USART_Clock - * @{ - */ - -#define USART_Clock_Disable ((uint32_t)0x00000000) -#define USART_Clock_Enable USART_CR2_CLKEN -#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \ - ((CLOCK) == USART_Clock_Enable)) -/** - * @} - */ - -/** @defgroup USART_Clock_Polarity - * @{ - */ - -#define USART_CPOL_Low ((uint32_t)0x00000000) -#define USART_CPOL_High USART_CR2_CPOL -#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High)) - -/** - * @} - */ - -/** @defgroup USART_Clock_Phase - * @{ - */ - -#define USART_CPHA_1Edge ((uint32_t)0x00000000) -#define USART_CPHA_2Edge USART_CR2_CPHA -#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge)) - -/** - * @} - */ - -/** @defgroup USART_Last_Bit - * @{ - */ - -#define USART_LastBit_Disable ((uint32_t)0x00000000) -#define USART_LastBit_Enable USART_CR2_LBCL -#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \ - ((LASTBIT) == USART_LastBit_Enable)) -/** - * @} - */ - -/** @defgroup USART_DMA_Requests - * @{ - */ - -#define USART_DMAReq_Tx USART_CR3_DMAT -#define USART_DMAReq_Rx USART_CR3_DMAR -#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint32_t)0xFFFFFF3F) == 0x00) && \ - ((DMAREQ) != (uint32_t)0x00)) - -/** - * @} - */ - -/** @defgroup USART_DMA_Recception_Error - * @{ - */ - -#define USART_DMAOnError_Enable ((uint32_t)0x00000000) -#define USART_DMAOnError_Disable USART_CR3_DDRE -#define IS_USART_DMAONERROR(DMAERROR) (((DMAERROR) == USART_DMAOnError_Disable)|| \ - ((DMAERROR) == USART_DMAOnError_Enable)) -/** - * @} - */ - -/** @defgroup USART_MuteMode_WakeUp_methods - * @{ - */ - -#define USART_WakeUp_IdleLine ((uint32_t)0x00000000) -#define USART_WakeUp_AddressMark USART_CR1_WAKE -#define IS_USART_MUTEMODE_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \ - ((WAKEUP) == USART_WakeUp_AddressMark)) -/** - * @} - */ - -/** @defgroup USART_Address_Detection - * @{ - */ - -#define USART_AddressLength_4b ((uint32_t)0x00000000) -#define USART_AddressLength_7b USART_CR2_ADDM7 -#define IS_USART_ADDRESS_DETECTION(ADDRESS) (((ADDRESS) == USART_AddressLength_4b) || \ - ((ADDRESS) == USART_AddressLength_7b)) -/** - * @} - */ - -/** @defgroup USART_StopMode_WakeUp_methods - * @note These parameters are only available for STM32F051 and STM32F072 devices - * @{ - */ - -#define USART_WakeUpSource_AddressMatch ((uint32_t)0x00000000) -#define USART_WakeUpSource_StartBit USART_CR3_WUS_1 -#define USART_WakeUpSource_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) -#define IS_USART_STOPMODE_WAKEUPSOURCE(SOURCE) (((SOURCE) == USART_WakeUpSource_AddressMatch) || \ - ((SOURCE) == USART_WakeUpSource_StartBit) || \ - ((SOURCE) == USART_WakeUpSource_RXNE)) -/** - * @} - */ - -/** @defgroup USART_LIN_Break_Detection_Length - * @{ - */ - -#define USART_LINBreakDetectLength_10b ((uint32_t)0x00000000) -#define USART_LINBreakDetectLength_11b USART_CR2_LBDL -#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \ - (((LENGTH) == USART_LINBreakDetectLength_10b) || \ - ((LENGTH) == USART_LINBreakDetectLength_11b)) -/** - * @} - */ - -/** @defgroup USART_IrDA_Low_Power - * @{ - */ - -#define USART_IrDAMode_LowPower USART_CR3_IRLP -#define USART_IrDAMode_Normal ((uint32_t)0x00000000) -#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \ - ((MODE) == USART_IrDAMode_Normal)) -/** - * @} - */ - -/** @defgroup USART_DE_Polarity - * @{ - */ - -#define USART_DEPolarity_High ((uint32_t)0x00000000) -#define USART_DEPolarity_Low USART_CR3_DEP -#define IS_USART_DE_POLARITY(POLARITY) (((POLARITY) == USART_DEPolarity_Low) || \ - ((POLARITY) == USART_DEPolarity_High)) -/** - * @} - */ - -/** @defgroup USART_Inversion_Pins - * @{ - */ - -#define USART_InvPin_Tx USART_CR2_TXINV -#define USART_InvPin_Rx USART_CR2_RXINV -#define IS_USART_INVERSTION_PIN(PIN) ((((PIN) & (uint32_t)0xFFFCFFFF) == 0x00) && \ - ((PIN) != (uint32_t)0x00)) - -/** - * @} - */ - -/** @defgroup USART_AutoBaudRate_Mode - * @{ - */ - -#define USART_AutoBaudRate_StartBit ((uint32_t)0x00000000) -#define USART_AutoBaudRate_FallingEdge USART_CR2_ABRMODE_0 -#define IS_USART_AUTOBAUDRATE_MODE(MODE) (((MODE) == USART_AutoBaudRate_StartBit) || \ - ((MODE) == USART_AutoBaudRate_FallingEdge)) -/** - * @} - */ - -/** @defgroup USART_OVR_DETECTION - * @{ - */ - -#define USART_OVRDetection_Enable ((uint32_t)0x00000000) -#define USART_OVRDetection_Disable USART_CR3_OVRDIS -#define IS_USART_OVRDETECTION(OVR) (((OVR) == USART_OVRDetection_Enable)|| \ - ((OVR) == USART_OVRDetection_Disable)) -/** - * @} - */ -/** @defgroup USART_Request - * @{ - */ - -#define USART_Request_ABRRQ USART_RQR_ABRRQ -#define USART_Request_SBKRQ USART_RQR_SBKRQ -#define USART_Request_MMRQ USART_RQR_MMRQ -#define USART_Request_RXFRQ USART_RQR_RXFRQ -#define USART_Request_TXFRQ USART_RQR_TXFRQ - -#define IS_USART_REQUEST(REQUEST) (((REQUEST) == USART_Request_TXFRQ) || \ - ((REQUEST) == USART_Request_RXFRQ) || \ - ((REQUEST) == USART_Request_MMRQ) || \ - ((REQUEST) == USART_Request_SBKRQ) || \ - ((REQUEST) == USART_Request_ABRRQ)) -/** - * @} - */ - -/** @defgroup USART_Flags - * @{ - */ -#define USART_FLAG_REACK USART_ISR_REACK -#define USART_FLAG_TEACK USART_ISR_TEACK -#define USART_FLAG_WU USART_ISR_WUF /*!< Not available for STM32F030 devices */ -#define USART_FLAG_RWU USART_ISR_RWU /*!< Not available for STM32F030 devices */ -#define USART_FLAG_SBK USART_ISR_SBKF -#define USART_FLAG_CM USART_ISR_CMF -#define USART_FLAG_BUSY USART_ISR_BUSY -#define USART_FLAG_ABRF USART_ISR_ABRF -#define USART_FLAG_ABRE USART_ISR_ABRE -#define USART_FLAG_EOB USART_ISR_EOBF /*!< Not available for STM32F030 devices */ -#define USART_FLAG_RTO USART_ISR_RTOF -#define USART_FLAG_nCTSS USART_ISR_CTS -#define USART_FLAG_CTS USART_ISR_CTSIF -#define USART_FLAG_LBD USART_ISR_LBD /*!< Not available for STM32F030 devices */ -#define USART_FLAG_TXE USART_ISR_TXE -#define USART_FLAG_TC USART_ISR_TC -#define USART_FLAG_RXNE USART_ISR_RXNE -#define USART_FLAG_IDLE USART_ISR_IDLE -#define USART_FLAG_ORE USART_ISR_ORE -#define USART_FLAG_NE USART_ISR_NE -#define USART_FLAG_FE USART_ISR_FE -#define USART_FLAG_PE USART_ISR_PE -#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \ - ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \ - ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \ - ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \ - ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \ - ((FLAG) == USART_FLAG_nCTSS) || ((FLAG) == USART_FLAG_RTO) || \ - ((FLAG) == USART_FLAG_EOB) || ((FLAG) == USART_FLAG_ABRE) || \ - ((FLAG) == USART_FLAG_ABRF) || ((FLAG) == USART_FLAG_BUSY) || \ - ((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_SBK) || \ - ((FLAG) == USART_FLAG_RWU) || ((FLAG) == USART_FLAG_WU) || \ - ((FLAG) == USART_FLAG_TEACK)|| ((FLAG) == USART_FLAG_REACK)) - -#define IS_USART_CLEAR_FLAG(FLAG) (((FLAG) == USART_FLAG_WU) || ((FLAG) == USART_FLAG_TC) || \ - ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_ORE) || \ - ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \ - ((FLAG) == USART_FLAG_LBD) || ((FLAG) == USART_FLAG_CTS) || \ - ((FLAG) == USART_FLAG_RTO) || ((FLAG) == USART_FLAG_EOB) || \ - ((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_PE)) -/** - * @} - */ - -/** @defgroup USART_Interrupt_definition - * @brief USART Interrupt definition - * USART_IT possible values - * Elements values convention: 0xZZZZYYXX - * XX: Position of the corresponding Interrupt - * YY: Register index - * ZZZZ: Flag position - * @{ - */ - -#define USART_IT_WU ((uint32_t)0x00140316) /*!< Not available for STM32F030 devices */ -#define USART_IT_CM ((uint32_t)0x0011010E) -#define USART_IT_EOB ((uint32_t)0x000C011B) /*!< Not available for STM32F030 devices */ -#define USART_IT_RTO ((uint32_t)0x000B011A) -#define USART_IT_PE ((uint32_t)0x00000108) -#define USART_IT_TXE ((uint32_t)0x00070107) -#define USART_IT_TC ((uint32_t)0x00060106) -#define USART_IT_RXNE ((uint32_t)0x00050105) -#define USART_IT_IDLE ((uint32_t)0x00040104) -#define USART_IT_LBD ((uint32_t)0x00080206) /*!< Not available for STM32F030 devices */ -#define USART_IT_CTS ((uint32_t)0x0009030A) -#define USART_IT_ERR ((uint32_t)0x00000300) -#define USART_IT_ORE ((uint32_t)0x00030300) -#define USART_IT_NE ((uint32_t)0x00020300) -#define USART_IT_FE ((uint32_t)0x00010300) - -#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ - ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ - ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR) || \ - ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \ - ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU)) - -#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ - ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ - ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \ - ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE) || \ - ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \ - ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU)) - -#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_PE) || \ - ((IT) == USART_IT_FE) || ((IT) == USART_IT_NE) || \ - ((IT) == USART_IT_ORE) || ((IT) == USART_IT_IDLE) || \ - ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS) || \ - ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \ - ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU)) -/** - * @} - */ - -/** @defgroup USART_Global_definition - * @{ - */ - -#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x005B8D81)) -#define IS_USART_DE_ASSERTION_DEASSERTION_TIME(TIME) ((TIME) <= 0x1F) -#define IS_USART_AUTO_RETRY_COUNTER(COUNTER) ((COUNTER) <= 0x7) -#define IS_USART_TIMEOUT(TIMEOUT) ((TIMEOUT) <= 0x00FFFFFF) -#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Initialization and Configuration functions *********************************/ -void USART_DeInit(USART_TypeDef* USARTx); -void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); -void USART_StructInit(USART_InitTypeDef* USART_InitStruct); -void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); -void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); -void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_DirectionModeCmd(USART_TypeDef* USARTx, uint32_t USART_DirectionMode, FunctionalState NewState); -void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); /* Not available for STM32F030 devices */ -void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_MSBFirstCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_DataInvCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_InvPinCmd(USART_TypeDef* USARTx, uint32_t USART_InvPin, FunctionalState NewState); -void USART_SWAPPinCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_ReceiverTimeOutCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SetReceiverTimeOut(USART_TypeDef* USARTx, uint32_t USART_ReceiverTimeOut); - -/* STOP Mode functions ********************************************************/ -void USART_STOPModeCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_StopModeWakeUpSourceConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUpSource); /* Not available for STM32F030 devices */ - -/* AutoBaudRate functions *****************************************************/ -void USART_AutoBaudRateCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_AutoBaudRateConfig(USART_TypeDef* USARTx, uint32_t USART_AutoBaudRate); - -/* Data transfers functions ***************************************************/ -void USART_SendData(USART_TypeDef* USARTx, uint16_t Data); -uint16_t USART_ReceiveData(USART_TypeDef* USARTx); - -/* Multi-Processor Communication functions ************************************/ -void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address); -void USART_MuteModeWakeUpConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUp); -void USART_MuteModeCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_AddressDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_AddressLength); - -/* LIN mode functions *********************************************************/ -void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint32_t USART_LINBreakDetectLength); /* Not available for STM32F030 devices */ -void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); /* Not available for STM32F030 devices */ - -/* Half-duplex mode function **************************************************/ -void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); - -/* Smartcard mode functions ***************************************************/ -void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); /* Not available for STM32F030 devices */ -void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); /* Not available for STM32F030 devices */ -void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); /* Not available for STM32F030 devices */ -void USART_SetAutoRetryCount(USART_TypeDef* USARTx, uint8_t USART_AutoCount); /* Not available for STM32F030 devices */ -void USART_SetBlockLength(USART_TypeDef* USARTx, uint8_t USART_BlockLength); /* Not available for STM32F030 devices */ - -/* IrDA mode functions ********************************************************/ -void USART_IrDAConfig(USART_TypeDef* USARTx, uint32_t USART_IrDAMode); /* Not available for STM32F030 devices */ -void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); /* Not available for STM32F030 devices */ - -/* RS485 mode functions *******************************************************/ -void USART_DECmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_DEPolarityConfig(USART_TypeDef* USARTx, uint32_t USART_DEPolarity); -void USART_SetDEAssertionTime(USART_TypeDef* USARTx, uint32_t USART_DEAssertionTime); -void USART_SetDEDeassertionTime(USART_TypeDef* USARTx, uint32_t USART_DEDeassertionTime); - -/* DMA transfers management functions *****************************************/ -void USART_DMACmd(USART_TypeDef* USARTx, uint32_t USART_DMAReq, FunctionalState NewState); -void USART_DMAReceptionErrorConfig(USART_TypeDef* USARTx, uint32_t USART_DMAOnError); - -/* Interrupts and flags management functions **********************************/ -void USART_ITConfig(USART_TypeDef* USARTx, uint32_t USART_IT, FunctionalState NewState); -void USART_RequestCmd(USART_TypeDef* USARTx, uint32_t USART_Request, FunctionalState NewState); -void USART_OverrunDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_OVRDetection); -FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint32_t USART_FLAG); -void USART_ClearFlag(USART_TypeDef* USARTx, uint32_t USART_FLAG); -ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint32_t USART_IT); -void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint32_t USART_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0XX_USART_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_wwdg.h b/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_wwdg.h deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_wwdg.h +++ /dev/null @@ -1,109 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_wwdg.h - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file contains all the functions prototypes for the WWDG - * firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0XX_WWDG_H -#define __STM32F0XX_WWDG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup WWDG - * @{ - */ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup WWDG_Exported_Constants - * @{ - */ - -/** @defgroup WWDG_Prescaler - * @{ - */ - -#define WWDG_Prescaler_1 ((uint32_t)0x00000000) -#define WWDG_Prescaler_2 ((uint32_t)0x00000080) -#define WWDG_Prescaler_4 ((uint32_t)0x00000100) -#define WWDG_Prescaler_8 ((uint32_t)0x00000180) -#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \ - ((PRESCALER) == WWDG_Prescaler_2) || \ - ((PRESCALER) == WWDG_Prescaler_4) || \ - ((PRESCALER) == WWDG_Prescaler_8)) -#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) -#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -/* Function used to set the WWDG configuration to the default reset state ****/ -void WWDG_DeInit(void); - -/* Prescaler, Refresh window and Counter configuration functions **************/ -void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); -void WWDG_SetWindowValue(uint8_t WindowValue); -void WWDG_EnableIT(void); -void WWDG_SetCounter(uint8_t Counter); - -/* WWDG activation functions **************************************************/ -void WWDG_Enable(uint8_t Counter); - -/* Interrupts and flags management functions **********************************/ -FlagStatus WWDG_GetFlagStatus(void); -void WWDG_ClearFlag(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0XX_WWDG_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_adc.c b/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_adc.c deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_adc.c +++ /dev/null @@ -1,1240 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_adc.c - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the Analog to Digital Convertor (ADC) peripheral: - * + Initialization and Configuration - * + Power saving - * + Analog Watchdog configuration - * + Temperature Sensor, Vrefint (Internal Reference Voltage) and - * Vbat (Voltage battery) management - * + ADC Channels Configuration - * + ADC Channels DMA Configuration - * + Interrupts and flags management - * - * @verbatim -================================================================================ - ##### How to use this driver ##### -================================================================================ - [..] - (#) Enable the ADC interface clock using - RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE); - (#) ADC pins configuration - (++) Enable the clock for the ADC GPIOs using the following function: - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOx, ENABLE); - (++) Configure these ADC pins in analog mode using GPIO_Init(); - (#) Configure the ADC conversion resolution, data alignment, external - trigger and edge, scan direction and Enable/Disable the continuous mode - using the ADC_Init() function. - (#) Activate the ADC peripheral using ADC_Cmd() function. - - *** ADC channels group configuration *** - ============================================ - [..] - (+) To configure the ADC channels features, use ADC_Init() and - ADC_ChannelConfig() functions. - (+) To activate the continuous mode, use the ADC_ContinuousModeCmd() - function. - (+) To activate the Discontinuous mode, use the ADC_DiscModeCmd() functions. - (+) To activate the overrun mode, use the ADC_OverrunModeCmd() functions. - (+) To activate the calibration mode, use the ADC_GetCalibrationFactor() functions. - (+) To read the ADC converted values, use the ADC_GetConversionValue() - function. - - *** DMA for ADC channels features configuration *** - ============================================================= - [..] - (+) To enable the DMA mode for ADC channels group, use the ADC_DMACmd() function. - (+) To configure the DMA transfer request, use ADC_DMARequestModeConfig() function. - - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_adc.h" -#include "stm32f0xx_rcc.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup ADC - * @brief ADC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* ADC CFGR mask */ -#define CFGR1_CLEAR_MASK ((uint32_t)0xFFFFD203) - -/* Calibration time out */ -#define CALIBRATION_TIMEOUT ((uint32_t)0x0000F000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup ADC_Private_Functions - * @{ - */ - -/** @defgroup ADC_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize and configure the ADC Prescaler - (+) ADC Conversion Resolution (12bit..6bit) - (+) ADC Continuous Conversion Mode (Continuous or Single conversion) - (+) External trigger Edge and source - (+) Converted data alignment (left or right) - (+) The direction in which the channels will be scanned in the sequence - (+) Enable or disable the ADC peripheral - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes ADC1 peripheral registers to their default reset values. - * @param ADCx: where x can be 1 to select the ADC peripheral. - * @retval None - */ -void ADC_DeInit(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - if(ADCx == ADC1) - { - /* Enable ADC1 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE); - - /* Release ADC1 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE); - } -} - -/** - * @brief Initializes the ADCx peripheral according to the specified parameters - * in the ADC_InitStruct. - * @note This function is used to configure the global features of the ADC ( - * Resolution, Data Alignment, continuous mode activation, External - * trigger source and edge, Sequence Scan Direction). - * @param ADCx: where x can be 1 to select the ADC peripheral. - * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains - * the configuration information for the specified ADC peripheral. - * @retval None - */ -void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution)); - assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); - assert_param(IS_ADC_EXT_TRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigConvEdge)); - assert_param(IS_ADC_EXTERNAL_TRIG_CONV(ADC_InitStruct->ADC_ExternalTrigConv)); - assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); - assert_param(IS_ADC_SCAN_DIRECTION(ADC_InitStruct->ADC_ScanDirection)); - - /* Get the ADCx CFGR value */ - tmpreg = ADCx->CFGR1; - - /* Clear SCANDIR, RES[1:0], ALIGN, EXTSEL[2:0], EXTEN[1:0] and CONT bits */ - tmpreg &= CFGR1_CLEAR_MASK; - - /*---------------------------- ADCx CFGR Configuration ---------------------*/ - - /* Set RES[1:0] bits according to ADC_Resolution value */ - /* Set CONT bit according to ADC_ContinuousConvMode value */ - /* Set EXTEN[1:0] bits according to ADC_ExternalTrigConvEdge value */ - /* Set EXTSEL[2:0] bits according to ADC_ExternalTrigConv value */ - /* Set ALIGN bit according to ADC_DataAlign value */ - /* Set SCANDIR bit according to ADC_ScanDirection value */ - - tmpreg |= (uint32_t)(ADC_InitStruct->ADC_Resolution | ((uint32_t)(ADC_InitStruct->ADC_ContinuousConvMode) << 13) | - ADC_InitStruct->ADC_ExternalTrigConvEdge | ADC_InitStruct->ADC_ExternalTrigConv | - ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ScanDirection); - - /* Write to ADCx CFGR */ - ADCx->CFGR1 = tmpreg; -} - -/** - * @brief Fills each ADC_InitStruct member with its default value. - * @note This function is used to initialize the global features of the ADC ( - * Resolution, Data Alignment, continuous mode activation, External - * trigger source and edge, Sequence Scan Direction). - * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) -{ - /* Reset ADC init structure parameters values */ - /* Initialize the ADC_Resolution member */ - ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b; - - /* Initialize the ADC_ContinuousConvMode member */ - ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; - - /* Initialize the ADC_ExternalTrigConvEdge member */ - ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None; - - /* Initialize the ADC_ExternalTrigConv member */ - ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_TRGO; - - /* Initialize the ADC_DataAlign member */ - ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; - - /* Initialize the ADC_ScanDirection member */ - ADC_InitStruct->ADC_ScanDirection = ADC_ScanDirection_Upward; -} - -/** - * @brief Enables or disables the specified ADC peripheral. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param NewState: new state of the ADCx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the ADEN bit to Enable the ADC peripheral */ - ADCx->CR |= (uint32_t)ADC_CR_ADEN; - } - else - { - /* Set the ADDIS to Disable the ADC peripheral */ - ADCx->CR |= (uint32_t)ADC_CR_ADDIS; - } -} - -/** - * @brief Configure the ADC to either be clocked by the asynchronous clock(which is - * independent, the dedicated 14MHz clock) or the synchronous clock derived from - * the APB clock of the ADC bus interface divided by 2 or 4 - * @note This function can be called only when ADC is disabled. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param ADC_ClockMode: This parameter can be : - * @arg ADC_ClockMode_AsynClk: ADC clocked by the dedicated 14MHz clock - * @arg ADC_ClockMode_SynClkDiv2: ADC clocked by PCLK/2 - * @arg ADC_ClockMode_SynClkDiv4: ADC clocked by PCLK/4 - * @retval None - */ -void ADC_ClockModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ClockMode) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CLOCKMODE(ADC_ClockMode)); - - /* Configure the ADC Clock mode according to ADC_ClockMode */ - ADCx->CFGR2 = (uint32_t)ADC_ClockMode; - -} - -/** - * @brief Enables or disables the jitter when the ADC is clocked by PCLK div2 - * or div4 - * @note This function is obsolete and maintained for legacy purpose only. ADC_ClockModeConfig() - * function should be used instead. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param ADC_JitterOff: This parameter can be : - * @arg ADC_JitterOff_PCLKDiv2: Remove jitter when ADC is clocked by PLCK divided by 2 - * @arg ADC_JitterOff_PCLKDiv4: Remove jitter when ADC is clocked by PLCK divided by 4 - * @param NewState: new state of the ADCx jitter. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_JitterCmd(ADC_TypeDef* ADCx, uint32_t ADC_JitterOff, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_JITTEROFF(ADC_JitterOff)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Disable Jitter */ - ADCx->CFGR2 |= (uint32_t)ADC_JitterOff; - } - else - { - /* Enable Jitter */ - ADCx->CFGR2 &= (uint32_t)(~ADC_JitterOff); - } -} - -/** - * @} - */ - -/** @defgroup ADC_Group2 Power saving functions - * @brief Power saving functions - * -@verbatim - =============================================================================== - ##### Power saving functions ##### - =============================================================================== - [..] This section provides functions allowing to reduce power consumption. - [..] The two function must be combined to get the maximal benefits: - When the ADC frequency is higher than the CPU one, it is recommended to - (#) Enable the Auto Delayed Conversion mode : - ==> using ADC_WaitModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); - (#) Enable the power off in Delay phases : - ==> using ADC_AutoPowerOffCmd(ADC_TypeDef* ADCx, FunctionalState NewState); - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the ADC Power Off. - * @note ADC power-on and power-off can be managed by hardware to cut the - * consumption when the ADC is not converting. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @note The ADC can be powered down: - * - During the Auto delay phase: The ADC is powered on again at the end - * of the delay (until the previous data is read from the ADC data register). - * - During the ADC is waiting for a trigger event: The ADC is powered up - * at the next trigger event (when the conversion is started). - * @param NewState: new state of the ADCx power Off. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_AutoPowerOffCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the ADC Automatic Power-Off */ - ADCx->CFGR1 |= ADC_CFGR1_AUTOFF; - } - else - { - /* Disable the ADC Automatic Power-Off */ - ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_AUTOFF; - } -} - -/** - * @brief Enables or disables the Wait conversion mode. - * @note When the CPU clock is not fast enough to manage the data rate, a - * Hardware delay can be introduced between ADC conversions to reduce - * this data rate. - * @note The Hardware delay is inserted after each conversions and until the - * previous data is read from the ADC data register - * @note This is a way to automatically adapt the speed of the ADC to the speed - * of the system which will read the data. - * @note Any hardware triggers wich occur while a conversion is on going or - * while the automatic Delay is applied are ignored - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param NewState: new state of the ADCx Auto-Delay. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_WaitModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the ADC Automatic Delayed conversion */ - ADCx->CFGR1 |= ADC_CFGR1_WAIT; - } - else - { - /* Disable the ADC Automatic Delayed conversion */ - ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_WAIT; - } -} - -/** - * @} - */ - -/** @defgroup ADC_Group3 Analog Watchdog configuration functions - * @brief Analog Watchdog configuration functions - * -@verbatim - =============================================================================== - ##### Analog Watchdog configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to configure the Analog Watchdog - (AWD) feature in the ADC. - [..] A typical configuration Analog Watchdog is done following these steps : - (#) the ADC guarded channel(s) is (are) selected using the - ADC_AnalogWatchdogSingleChannelConfig() function. - (#) The Analog watchdog lower and higher threshold are configured using the - ADC_AnalogWatchdogThresholdsConfig() function. - (#) The Analog watchdog is enabled and configured to enable the check, on one - or more channels, using the ADC_AnalogWatchdogCmd() function. - (#) Enable the analog watchdog on the selected channel using - ADC_AnalogWatchdogSingleChannelCmd() function - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the analog watchdog - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param NewState: new state of the ADCx Analog Watchdog. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the ADC Analog Watchdog */ - ADCx->CFGR1 |= ADC_CFGR1_AWDEN; - } - else - { - /* Disable the ADC Analog Watchdog */ - ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_AWDEN; - } -} - -/** - * @brief Configures the high and low thresholds of the analog watchdog. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param HighThreshold: the ADC analog watchdog High threshold value. - * This parameter must be a 12bit value. - * @param LowThreshold: the ADC analog watchdog Low threshold value. - * This parameter must be a 12bit value. - * @retval None - */ -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, - uint16_t LowThreshold) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_THRESHOLD(HighThreshold)); - assert_param(IS_ADC_THRESHOLD(LowThreshold)); - - /* Set the ADCx high and low threshold */ - ADCx->TR = LowThreshold | ((uint32_t)HighThreshold << 16); - -} - -/** - * @brief Configures the analog watchdog guarded single channel - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param ADC_AnalogWatchdog_Channel: the ADC channel to configure for the analog watchdog. - * This parameter can be one of the following values: - * @arg ADC_AnalogWatchdog_Channel_0: ADC Channel0 selected - * @arg ADC_AnalogWatchdog_Channel_1: ADC Channel1 selected - * @arg ADC_AnalogWatchdog_Channel_2: ADC Channel2 selected - * @arg ADC_AnalogWatchdog_Channel_3: ADC Channel3 selected - * @arg ADC_AnalogWatchdog_Channel_4: ADC Channel4 selected - * @arg ADC_AnalogWatchdog_Channel_5: ADC Channel5 selected - * @arg ADC_AnalogWatchdog_Channel_6: ADC Channel6 selected - * @arg ADC_AnalogWatchdog_Channel_7: ADC Channel7 selected - * @arg ADC_AnalogWatchdog_Channel_8: ADC Channel8 selected - * @arg ADC_AnalogWatchdog_Channel_9: ADC Channel9 selected - * @arg ADC_AnalogWatchdog_Channel_10: ADC Channel10 selected, not available for STM32F031 devices - * @arg ADC_AnalogWatchdog_Channel_11: ADC Channel11 selected, not available for STM32F031 devices - * @arg ADC_AnalogWatchdog_Channel_12: ADC Channel12 selected, not available for STM32F031 devices - * @arg ADC_AnalogWatchdog_Channel_13: ADC Channel13 selected, not available for STM32F031 devices - * @arg ADC_AnalogWatchdog_Channel_14: ADC Channel14 selected, not available for STM32F031 devices - * @arg ADC_AnalogWatchdog_Channel_15: ADC Channel15 selected, not available for STM32F031 devices - * @arg ADC_AnalogWatchdog_Channel_16: ADC Channel16 selected - * @arg ADC_AnalogWatchdog_Channel_17: ADC Channel17 selected - * @arg ADC_AnalogWatchdog_Channel_18: ADC Channel18 selected, not available for STM32F030 devices - * @note The channel selected on the AWDCH must be also set into the CHSELR - * register - * @retval None - */ -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog_Channel) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_ANALOG_WATCHDOG_CHANNEL(ADC_AnalogWatchdog_Channel)); - - /* Get the old register value */ - tmpreg = ADCx->CFGR1; - - /* Clear the Analog watchdog channel select bits */ - tmpreg &= ~ADC_CFGR1_AWDCH; - - /* Set the Analog watchdog channel */ - tmpreg |= ADC_AnalogWatchdog_Channel; - - /* Store the new register value */ - ADCx->CFGR1 = tmpreg; -} - -/** - * @brief Enables or disables the ADC Analog Watchdog Single Channel. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param NewState: new state of the ADCx ADC Analog Watchdog Single Channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_AnalogWatchdogSingleChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the ADC Analog Watchdog Single Channel */ - ADCx->CFGR1 |= ADC_CFGR1_AWDSGL; - } - else - { - /* Disable the ADC Analog Watchdog Single Channel */ - ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_AWDSGL; - } -} - -/** - * @} - */ - -/** @defgroup ADC_Group4 Temperature Sensor, Vrefint and Vbat management functions - * @brief Temperature Sensor, Vrefint and Vbat management functions - * -@verbatim - =============================================================================== - ##### Temperature Sensor, Vrefint and Vbat management function ##### - =============================================================================== - [..] This section provides a function allowing to enable/disable the internal - connections between the ADC and the Temperature Sensor, the Vrefint and - Vbat source. - - [..] A typical configuration to get the Temperature sensor, Vrefint and Vbat channels - voltages is done following these steps : - (#) Enable the internal connection of Temperature sensor, Vrefint or Vbat sources - with the ADC channels using ADC_TempSensorCmd(), ADC_VrefintCmd() or ADC_VbatCmd() - functions. - (#) select the ADC_Channel_16(Temperature sensor), ADC_Channel_17(Vrefint) - or ADC_Channel_18(Voltage battery) using ADC_ChannelConfig() function - (#) Get the voltage values, using ADC_GetConversionValue() function - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the temperature sensor channel. - * @param NewState: new state of the temperature sensor input channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_TempSensorCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the temperature sensor channel*/ - ADC->CCR |= (uint32_t)ADC_CCR_TSEN; - } - else - { - /* Disable the temperature sensor channel*/ - ADC->CCR &= (uint32_t)(~ADC_CCR_TSEN); - } -} - -/** - * @brief Enables or disables the Vrefint channel. - * @param NewState: new state of the Vref input channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_VrefintCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Vrefint channel*/ - ADC->CCR |= (uint32_t)ADC_CCR_VREFEN; - } - else - { - /* Disable the Vrefint channel*/ - ADC->CCR &= (uint32_t)(~ADC_CCR_VREFEN); - } -} - -/** - * @brief Enables or disables the Vbat channel. - * @note This feature is not applicable for STM32F030 devices. - * @param NewState: new state of the Vbat input channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_VbatCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Vbat channel*/ - ADC->CCR |= (uint32_t)ADC_CCR_VBATEN; - } - else - { - /* Disable the Vbat channel*/ - ADC->CCR &= (uint32_t)(~ADC_CCR_VBATEN); - } -} - -/** - * @} - */ - -/** @defgroup ADC_Group5 Channels Configuration functions - * @brief Channels Configuration functions - * -@verbatim - =============================================================================== - ##### Channels Configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to manage the ADC channels, - it is composed of 3 sub sections : - (#) Configuration and management functions for ADC channels: This subsection - provides functions allowing to configure the ADC channels : - (++) Select the ADC channels - (++) Activate ADC Calibration - (++) Activate the Overrun Mode. - (++) Activate the Discontinuous Mode - (++) Activate the Continuous Mode. - (++) Configure the sampling time for each channel - (++) Select the conversion Trigger and Edge for ADC channels - (++) Select the scan direction. - -@@- Please Note that the following features for ADC channels are configurated - using the ADC_Init() function : - (+@@) Activate the Continuous Mode (can be also activated by ADC_OverrunModeCmd(). - (+@@) Select the conversion Trigger and Edge for ADC channels - (+@@) Select the scan direction. - (#) Control the ADC peripheral : This subsection permits to command the ADC: - (++) Stop or discard an on-going conversion (ADSTP command) - (++) Start the ADC conversion . - (#) Get the conversion data: This subsection provides an important function in - the ADC peripheral since it returns the converted data of the current - ADC channel. When the Conversion value is read, the EOC Flag is - automatically cleared. - -@endverbatim - * @{ - */ - -/** - * @brief Configures for the selected ADC and its sampling time. - * @param ADCx: where x can be 1 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure. - * This parameter can be any combination of the following values: - * @arg ADC_Channel_0: ADC Channel0 selected - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected, not available for STM32F031 devices - * @arg ADC_Channel_11: ADC Channel11 selected, not available for STM32F031 devices - * @arg ADC_Channel_12: ADC Channel12 selected, not available for STM32F031 devices - * @arg ADC_Channel_13: ADC Channel13 selected, not available for STM32F031 devices - * @arg ADC_Channel_14: ADC Channel14 selected, not available for STM32F031 devices - * @arg ADC_Channel_15: ADC Channel15 selected, not available for STM32F031 devices - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @arg ADC_Channel_18: ADC Channel18 selected, not available for STM32F030 devices - * @param ADC_SampleTime: The sample time value to be set for the selected channel. - * This parameter can be one of the following values: - * @arg ADC_SampleTime_1_5Cycles: Sample time equal to 1.5 cycles - * @arg ADC_SampleTime_7_5Cycles: Sample time equal to 7.5 cycles - * @arg ADC_SampleTime_13_5Cycles: Sample time equal to 13.5 cycles - * @arg ADC_SampleTime_28_5Cycles: Sample time equal to 28.5 cycles - * @arg ADC_SampleTime_41_5Cycles: Sample time equal to 41.5 cycles - * @arg ADC_SampleTime_55_5Cycles: Sample time equal to 55.5 cycles - * @arg ADC_SampleTime_71_5Cycles: Sample time equal to 71.5 cycles - * @arg ADC_SampleTime_239_5Cycles: Sample time equal to 239.5 cycles - * @retval None - */ -void ADC_ChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_Channel, uint32_t ADC_SampleTime) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); - - /* Configure the ADC Channel */ - ADCx->CHSELR |= (uint32_t)ADC_Channel; - - /* Clear the Sampling time Selection bits */ - tmpreg &= ~ADC_SMPR1_SMPR; - - /* Set the ADC Sampling Time register */ - tmpreg |= (uint32_t)ADC_SampleTime; - - /* Configure the ADC Sample time register */ - ADCx->SMPR = tmpreg ; -} - -/** - * @brief Enable the Continuous mode for the selected ADCx channels. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param NewState: new state of the Continuous mode. - * This parameter can be: ENABLE or DISABLE. - * @note It is not possible to have both discontinuous mode and continuous mode - * enabled. In this case (If DISCEN and CONT are Set), the ADC behaves - * as if continuous mode was disabled - * @retval None - */ -void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Continuous mode*/ - ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_CONT; - } - else - { - /* Disable the Continuous mode */ - ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_CONT); - } -} - -/** - * @brief Enable the discontinuous mode for the selected ADC channels. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param NewState: new state of the discontinuous mode. - * This parameter can be: ENABLE or DISABLE. - * @note It is not possible to have both discontinuous mode and continuous mode - * enabled. In this case (If DISCEN and CONT are Set), the ADC behaves - * as if continuous mode was disabled - * @retval None - */ -void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Discontinuous mode */ - ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_DISCEN; - } - else - { - /* Disable the Discontinuous mode */ - ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_DISCEN); - } -} - -/** - * @brief Enable the Overrun mode for the selected ADC channels. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param NewState: new state of the Overrun mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_OverrunModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Overrun mode */ - ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_OVRMOD; - } - else - { - /* Disable the Overrun mode */ - ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_OVRMOD); - } -} - -/** - * @brief Active the Calibration operation for the selected ADC. - * @note The Calibration can be initiated only when ADC is still in the - * reset configuration (ADEN must be equal to 0). - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @retval ADC Calibration factor - */ -uint32_t ADC_GetCalibrationFactor(ADC_TypeDef* ADCx) -{ - uint32_t tmpreg = 0, calibrationcounter = 0, calibrationstatus = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Set the ADC calibartion */ - ADCx->CR |= (uint32_t)ADC_CR_ADCAL; - - /* Wait until no ADC calibration is completed */ - do - { - calibrationstatus = ADCx->CR & ADC_CR_ADCAL; - calibrationcounter++; - } while((calibrationcounter != CALIBRATION_TIMEOUT) && (calibrationstatus != 0x00)); - - if((uint32_t)(ADCx->CR & ADC_CR_ADCAL) == RESET) - { - /*Get the calibration factor from the ADC data register */ - tmpreg = ADCx->DR; - } - else - { - /* Error factor */ - tmpreg = 0x00000000; - } - return tmpreg; -} - -/** - * @brief Stop the on going conversions for the selected ADC. - * @note When ADSTP is set, any on going conversion is aborted, and the ADC - * data register is not updated with current conversion. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @retval None - */ -void ADC_StopOfConversion(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - ADCx->CR |= (uint32_t)ADC_CR_ADSTP; -} - -/** - * @brief Start Conversion for the selected ADC channels. - * @note In continuous mode, ADSTART is not cleared by hardware with the - * assertion of EOSEQ because the sequence is automatic relaunched - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @retval None - */ -void ADC_StartOfConversion(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - ADCx->CR |= (uint32_t)ADC_CR_ADSTART; -} - -/** - * @brief Returns the last ADCx conversion result data for ADC channel. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @retval The Data conversion value. - */ -uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Return the selected ADC conversion value */ - return (uint16_t) ADCx->DR; -} - -/** - * @} - */ - -/** @defgroup ADC_Group6 DMA Configuration functions - * @brief Regular Channels DMA Configuration functions - * -@verbatim - =============================================================================== - ##### DMA Configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to configure the DMA for ADC hannels. - Since converted channel values are stored into a unique data register, - it is useful to use DMA for conversion of more than one channel. This - avoids the loss of the data already stored in the ADC Data register. - When the DMA mode is enabled (using the ADC_DMACmd() function), after each - conversion of a channel, a DMA request is generated. - - [..] Depending on the "DMA disable selection" configuration (using the - ADC_DMARequestModeConfig() function), at the end of the last DMA - transfer, two possibilities are allowed: - (+) No new DMA request is issued to the DMA controller (One Shot Mode) - (+) Requests can continue to be generated (Circular Mode). - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified ADC DMA request. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param NewState: new state of the selected ADC DMA transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected ADC DMA request */ - ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_DMAEN; - } - else - { - /* Disable the selected ADC DMA request */ - ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_DMAEN); - } -} - -/** - * @brief Enables or disables the ADC DMA request after last transfer (Single-ADC mode) - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param ADC_DMARequestMode: the ADC channel to configure. - * This parameter can be one of the following values: - * @arg ADC_DMAMode_OneShot: DMA One Shot Mode - * @arg ADC_DMAMode_Circular: DMA Circular Mode - * @retval None - */ -void ADC_DMARequestModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_DMARequestMode) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_DMACFG; - ADCx->CFGR1 |= (uint32_t)ADC_DMARequestMode; -} - -/** - * @} - */ - -/** @defgroup ADC_Group7 Interrupts and flags management functions - * @brief Interrupts and flags management functions. - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - [..] This section provides functions allowing to configure the ADC Interrupts - and get the status and clear flags and Interrupts pending bits. - - [..] The ADC provide 6 Interrupts sources and 11 Flags which can be divided into - 3 groups: - - *** Flags for ADC status *** - ====================================================== - [..] - (+)Flags : - (##) ADC_FLAG_ADRDY : This flag is set after the ADC has been enabled (bit ADEN=1) - and when the ADC reaches a state where it is ready to accept conversion requests - (##) ADC_FLAG_ADEN : This flag is set by software to enable the ADC. - The ADC will be effectively ready to operate once the ADRDY flag has been set. - (##) ADC_FLAG_ADDIS : This flag is cleared once the ADC is effectively - disabled. - (##) ADC_FLAG_ADSTART : This flag is cleared after the execution of - ADC_StopOfConversion() function, at the same time as the ADSTP bit is - cleared by hardware - (##) ADC_FLAG_ADSTP : This flag is cleared by hardware when the conversion - is effectively discarded and the ADC is ready to accept a new start conversion - (##) ADC_FLAG_ADCAL : This flag is set once the calibration is complete. - - (+)Interrupts - (##) ADC_IT_ADRDY : specifies the interrupt source for ADC ready event. - - *** Flags and Interrupts for ADC channel conversion *** - ===================================================== - [..] - (+)Flags : - (##) ADC_FLAG_EOC : This flag is set by hardware at the end of each conversion - of a channel when a new data result is available in the data register - (##) ADC_FLAG_EOSEQ : This bit is set by hardware at the end of the conversion - of a sequence of channels selected by ADC_ChannelConfig() function. - (##) ADC_FLAG_EOSMP : This bit is set by hardware at the end of the sampling phase. - (##) ADC_FLAG_OVR : This flag is set by hardware when an overrun occurs, - meaning that a new conversion has complete while the EOC flag was already set. - - (+)Interrupts : - (##) ADC_IT_EOC : specifies the interrupt source for end of conversion event. - (##) ADC_IT_EOSEQ : specifies the interrupt source for end of sequence event. - (##) ADC_IT_EOSMP : specifies the interrupt source for end of sampling event. - (##) ADC_IT_OVR : specifies the interrupt source for Overrun detection - event. - - *** Flags and Interrupts for the Analog Watchdog *** - ================================================ - [..] - (+)Flags : - (##) ADC_FLAG_AWD: This flag is set by hardware when the converted - voltage crosses the values programmed thrsholds - - (+)Interrupts : - (##) ADC_IT_AWD : specifies the interrupt source for Analog watchdog - event. - - [..] The user should identify which mode will be used in his application to - manage the ADC controller events: Polling mode or Interrupt mode. - - [..] In the Polling Mode it is advised to use the following functions: - (+) ADC_GetFlagStatus() : to check if flags events occur. - (+) ADC_ClearFlag() : to clear the flags events. - - [..] In the Interrupt Mode it is advised to use the following functions: - (+) ADC_ITConfig() : to enable or disable the interrupt source. - (+) ADC_GetITStatus() : to check if Interrupt occurs. - (+) ADC_ClearITPendingBit() : to clear the Interrupt pending Bit - (corresponding Flag). - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified ADC interrupts. - * @param ADCx: where x can be 1 to select the ADC peripheral. - * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg ADC_IT_ADRDY: ADC ready interrupt - * @arg ADC_IT_EOSMP: End of sampling interrupt - * @arg ADC_IT_EOC: End of conversion interrupt - * @arg ADC_IT_EOSEQ: End of sequence of conversion interrupt - * @arg ADC_IT_OVR: overrun interrupt - * @arg ADC_IT_AWD: Analog watchdog interrupt - * @param NewState: new state of the specified ADC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_ITConfig(ADC_TypeDef* ADCx, uint32_t ADC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_ADC_CONFIG_IT(ADC_IT)); - - if (NewState != DISABLE) - { - /* Enable the selected ADC interrupts */ - ADCx->IER |= ADC_IT; - } - else - { - /* Disable the selected ADC interrupts */ - ADCx->IER &= (~(uint32_t)ADC_IT); - } -} - -/** - * @brief Checks whether the specified ADC flag is set or not. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param ADC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg ADC_FLAG_AWD: Analog watchdog flag - * @arg ADC_FLAG_OVR: Overrun flag - * @arg ADC_FLAG_EOSEQ: End of Sequence flag - * @arg ADC_FLAG_EOC: End of conversion flag - * @arg ADC_FLAG_EOSMP: End of sampling flag - * @arg ADC_FLAG_ADRDY: ADC Ready flag - * @arg ADC_FLAG_ADEN: ADC enable flag - * @arg ADC_FLAG_ADDIS: ADC disable flag - * @arg ADC_FLAG_ADSTART: ADC start flag - * @arg ADC_FLAG_ADSTP: ADC stop flag - * @arg ADC_FLAG_ADCAL: ADC Calibration flag - * @retval The new state of ADC_FLAG (SET or RESET). - */ -FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_GET_FLAG(ADC_FLAG)); - - if((uint32_t)(ADC_FLAG & 0x01000000)) - { - tmpreg = ADCx->CR & 0xFEFFFFFF; - } - else - { - tmpreg = ADCx->ISR; - } - - /* Check the status of the specified ADC flag */ - if ((tmpreg & ADC_FLAG) != (uint32_t)RESET) - { - /* ADC_FLAG is set */ - bitstatus = SET; - } - else - { - /* ADC_FLAG is reset */ - bitstatus = RESET; - } - /* Return the ADC_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the ADCx's pending flags. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param ADC_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg ADC_FLAG_AWD: Analog watchdog flag - * @arg ADC_FLAG_EOC: End of conversion flag - * @arg ADC_FLAG_ADRDY: ADC Ready flag - * @arg ADC_FLAG_EOSMP: End of sampling flag - * @arg ADC_FLAG_EOSEQ: End of Sequence flag - * @arg ADC_FLAG_OVR: Overrun flag - * @retval None - */ -void ADC_ClearFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG)); - - /* Clear the selected ADC flags */ - ADCx->ISR = (uint32_t)ADC_FLAG; -} - -/** - * @brief Checks whether the specified ADC interrupt has occurred or not. - * @param ADCx: where x can be 1 to select the ADC1 peripheral - * @param ADC_IT: specifies the ADC interrupt source to check. - * This parameter can be one of the following values: - * @arg ADC_IT_ADRDY: ADC ready interrupt - * @arg ADC_IT_EOSMP: End of sampling interrupt - * @arg ADC_IT_EOC: End of conversion interrupt - * @arg ADC_IT_EOSEQ: End of sequence of conversion interrupt - * @arg ADC_IT_OVR: overrun interrupt - * @arg ADC_IT_AWD: Analog watchdog interrupt - * @retval The new state of ADC_IT (SET or RESET). - */ -ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint32_t ADC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_GET_IT(ADC_IT)); - - /* Get the ADC_IT enable bit status */ - enablestatus = (uint32_t)(ADCx->IER & ADC_IT); - - /* Check the status of the specified ADC interrupt */ - if (((uint32_t)(ADCx->ISR & ADC_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) - { - /* ADC_IT is set */ - bitstatus = SET; - } - else - { - /* ADC_IT is reset */ - bitstatus = RESET; - } - /* Return the ADC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the ADCx's interrupt pending bits. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param ADC_IT: specifies the ADC interrupt pending bit to clear. - * This parameter can be one of the following values: - * @arg ADC_IT_ADRDY: ADC ready interrupt - * @arg ADC_IT_EOSMP: End of sampling interrupt - * @arg ADC_IT_EOC: End of conversion interrupt - * @arg ADC_IT_EOSEQ: End of sequence of conversion interrupt - * @arg ADC_IT_OVR: overrun interrupt - * @arg ADC_IT_AWD: Analog watchdog interrupt - * @retval None - */ -void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CLEAR_IT(ADC_IT)); - - /* Clear the selected ADC interrupt pending bits */ - ADCx->ISR = (uint32_t)ADC_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_can.c b/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_can.c deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_can.c +++ /dev/null @@ -1,1631 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_can.c - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the Controller area network (CAN) peripheral and - * applicable only for STM32F072 devices : - * + Initialization and Configuration - * + CAN Frames Transmission - * + CAN Frames Reception - * + Operation modes switch - * + Error management - * + Interrupts and flags - * - @verbatim - - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - (#) Enable the CAN controller interface clock using - RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN, ENABLE); - (#) CAN pins configuration: - (++) Enable the clock for the CAN GPIOs using the following function: - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOx, ENABLE); - (++) Connect the involved CAN pins to AF0 using the following function - GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_CANx); - (++) Configure these CAN pins in alternate function mode by calling - the function GPIO_Init(); - (#) Initialise and configure the CAN using CAN_Init() and - CAN_FilterInit() functions. - (#) Transmit the desired CAN frame using CAN_Transmit() function. - (#) Check the transmission of a CAN frame using CAN_TransmitStatus() function. - (#) Cancel the transmission of a CAN frame using CAN_CancelTransmit() function. - (#) Receive a CAN frame using CAN_Recieve() function. - (#) Release the receive FIFOs using CAN_FIFORelease() function. - (#) Return the number of pending received frames using CAN_MessagePending() function. - (#) To control CAN events you can use one of the following two methods: - (++) Check on CAN flags using the CAN_GetFlagStatus() function. - (++) Use CAN interrupts through the function CAN_ITConfig() at initialization - phase and CAN_GetITStatus() function into interrupt routines to check - if the event has occurred or not. - After checking on a flag you should clear it using CAN_ClearFlag() - function. And after checking on an interrupt event you should clear it - using CAN_ClearITPendingBit() function. - - @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_can.h" -#include "stm32f0xx_rcc.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup CAN - * @brief CAN driver modules - * @{ - */ -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* CAN Master Control Register bits */ -#define MCR_DBF ((uint32_t)0x00010000) /* software master reset */ - -/* CAN Mailbox Transmit Request */ -#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */ - -/* CAN Filter Master Register bits */ -#define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */ - -/* Time out for INAK bit */ -#define INAK_TIMEOUT ((uint32_t)0x00FFFFFF) -/* Time out for SLAK bit */ -#define SLAK_TIMEOUT ((uint32_t)0x00FFFFFF) - -/* Flags in TSR register */ -#define CAN_FLAGS_TSR ((uint32_t)0x08000000) -/* Flags in RF1R register */ -#define CAN_FLAGS_RF1R ((uint32_t)0x04000000) -/* Flags in RF0R register */ -#define CAN_FLAGS_RF0R ((uint32_t)0x02000000) -/* Flags in MSR register */ -#define CAN_FLAGS_MSR ((uint32_t)0x01000000) -/* Flags in ESR register */ -#define CAN_FLAGS_ESR ((uint32_t)0x00F00000) - -/* Mailboxes definition */ -#define CAN_TXMAILBOX_0 ((uint8_t)0x00) -#define CAN_TXMAILBOX_1 ((uint8_t)0x01) -#define CAN_TXMAILBOX_2 ((uint8_t)0x02) - -#define CAN_MODE_MASK ((uint32_t) 0x00000003) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit); - -/** @defgroup CAN_Private_Functions - * @{ - */ - -/** @defgroup CAN_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize the CAN peripherals : Prescaler, operating mode, the maximum - number of time quanta to perform resynchronization, the number of time - quanta in Bit Segment 1 and 2 and many other modes. - (+) Configure the CAN reception filter. - (+) Select the start bank filter for slave CAN. - (+) Enable or disable the Debug Freeze mode for CAN. - (+) Enable or disable the CAN Time Trigger Operation communication mode. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the CAN peripheral registers to their default reset values. - * @param CANx: where x can be 1 to select the CAN peripheral. - * @retval None. - */ -void CAN_DeInit(CAN_TypeDef* CANx) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Enable CAN reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN, ENABLE); - /* Release CAN from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN, DISABLE); -} - -/** - * @brief Initializes the CAN peripheral according to the specified - * parameters in the CAN_InitStruct. - * @param CANx: where x can be 1 to select the CAN peripheral. - * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that contains - * the configuration information for the CAN peripheral. - * @retval Constant indicates initialization succeed which will be - * CAN_InitStatus_Failed or CAN_InitStatus_Success. - */ -uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) -{ - uint8_t InitStatus = CAN_InitStatus_Failed; - uint32_t wait_ack = 0x00000000; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP)); - assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode)); - assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW)); - assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1)); - assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2)); - assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler)); - - /* Exit from sleep mode */ - CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP); - - /* Request initialisation */ - CANx->MCR |= CAN_MCR_INRQ ; - - /* Wait the acknowledge */ - while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT)) - { - wait_ack++; - } - - /* Check acknowledge */ - if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) - { - InitStatus = CAN_InitStatus_Failed; - } - else - { - /* Set the time triggered communication mode */ - if (CAN_InitStruct->CAN_TTCM == ENABLE) - { - CANx->MCR |= CAN_MCR_TTCM; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM; - } - - /* Set the automatic bus-off management */ - if (CAN_InitStruct->CAN_ABOM == ENABLE) - { - CANx->MCR |= CAN_MCR_ABOM; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM; - } - - /* Set the automatic wake-up mode */ - if (CAN_InitStruct->CAN_AWUM == ENABLE) - { - CANx->MCR |= CAN_MCR_AWUM; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM; - } - - /* Set the no automatic retransmission */ - if (CAN_InitStruct->CAN_NART == ENABLE) - { - CANx->MCR |= CAN_MCR_NART; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_NART; - } - - /* Set the receive FIFO locked mode */ - if (CAN_InitStruct->CAN_RFLM == ENABLE) - { - CANx->MCR |= CAN_MCR_RFLM; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM; - } - - /* Set the transmit FIFO priority */ - if (CAN_InitStruct->CAN_TXFP == ENABLE) - { - CANx->MCR |= CAN_MCR_TXFP; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP; - } - - /* Set the bit timing register */ - CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \ - ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \ - ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \ - ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \ - ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1); - - /* Request leave initialisation */ - CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ; - - /* Wait the acknowledge */ - wait_ack = 0; - - while (((CANx->MSR & CAN_MSR_INAK) == (uint16_t)CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT)) - { - wait_ack++; - } - - /* ...and check acknowledged */ - if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) - { - InitStatus = CAN_InitStatus_Failed; - } - else - { - InitStatus = CAN_InitStatus_Success ; - } - } - - /* At this step, return the status of initialization */ - return InitStatus; -} - -/** - * @brief Configures the CAN reception filter according to the specified - * parameters in the CAN_FilterInitStruct. - * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef structure that - * contains the configuration information. - * @retval None - */ -void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct) -{ - uint32_t filter_number_bit_pos = 0; - /* Check the parameters */ - assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber)); - assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode)); - assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale)); - assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment)); - assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation)); - - filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber; - - /* Initialisation mode for the filter */ - CAN->FMR |= FMR_FINIT; - - /* Filter Deactivation */ - CAN->FA1R &= ~(uint32_t)filter_number_bit_pos; - - /* Filter Scale */ - if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit) - { - /* 16-bit scale for the filter */ - CAN->FS1R &= ~(uint32_t)filter_number_bit_pos; - - /* First 16-bit identifier and First 16-bit mask */ - /* Or First 16-bit identifier and Second 16-bit identifier */ - CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); - - /* Second 16-bit identifier and Second 16-bit mask */ - /* Or Third 16-bit identifier and Fourth 16-bit identifier */ - CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh); - } - - if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit) - { - /* 32-bit scale for the filter */ - CAN->FS1R |= filter_number_bit_pos; - /* 32-bit identifier or First 32-bit identifier */ - CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); - /* 32-bit mask or Second 32-bit identifier */ - CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow); - } - - /* Filter Mode */ - if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask) - { - /*Id/Mask mode for the filter*/ - CAN->FM1R &= ~(uint32_t)filter_number_bit_pos; - } - else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ - { - /*Identifier list mode for the filter*/ - CAN->FM1R |= (uint32_t)filter_number_bit_pos; - } - - /* Filter FIFO assignment */ - if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0) - { - /* FIFO 0 assignation for the filter */ - CAN->FFA1R &= ~(uint32_t)filter_number_bit_pos; - } - - if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1) - { - /* FIFO 1 assignation for the filter */ - CAN->FFA1R |= (uint32_t)filter_number_bit_pos; - } - - /* Filter activation */ - if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) - { - CAN->FA1R |= filter_number_bit_pos; - } - - /* Leave the initialisation mode for the filter */ - CAN->FMR &= ~FMR_FINIT; -} - -/** - * @brief Fills each CAN_InitStruct member with its default value. - * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which ill be initialized. - * @retval None - */ -void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) -{ - /* Reset CAN init structure parameters values */ - - /* Initialize the time triggered communication mode */ - CAN_InitStruct->CAN_TTCM = DISABLE; - - /* Initialize the automatic bus-off management */ - CAN_InitStruct->CAN_ABOM = DISABLE; - - /* Initialize the automatic wake-up mode */ - CAN_InitStruct->CAN_AWUM = DISABLE; - - /* Initialize the no automatic retransmission */ - CAN_InitStruct->CAN_NART = DISABLE; - - /* Initialize the receive FIFO locked mode */ - CAN_InitStruct->CAN_RFLM = DISABLE; - - /* Initialize the transmit FIFO priority */ - CAN_InitStruct->CAN_TXFP = DISABLE; - - /* Initialize the CAN_Mode member */ - CAN_InitStruct->CAN_Mode = CAN_Mode_Normal; - - /* Initialize the CAN_SJW member */ - CAN_InitStruct->CAN_SJW = CAN_SJW_1tq; - - /* Initialize the CAN_BS1 member */ - CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq; - - /* Initialize the CAN_BS2 member */ - CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq; - - /* Initialize the CAN_Prescaler member */ - CAN_InitStruct->CAN_Prescaler = 1; -} - -/** - * @brief Select the start bank filter for slave CAN. - * @param CAN_BankNumber: Select the start slave bank filter from 1..27. - * @retval None - */ -void CAN_SlaveStartBank(uint8_t CAN_BankNumber) -{ - /* Check the parameters */ - assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber)); - - /* Enter Initialisation mode for the filter */ - CAN->FMR |= FMR_FINIT; - - /* Select the start slave bank */ - CAN->FMR &= (uint32_t)0xFFFFC0F1 ; - CAN->FMR |= (uint32_t)(CAN_BankNumber)<<8; - - /* Leave Initialisation mode for the filter */ - CAN->FMR &= ~FMR_FINIT; -} - -/** - * @brief Enables or disables the DBG Freeze for CAN. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param NewState: new state of the CAN peripheral. - * This parameter can be: ENABLE (CAN reception/transmission is frozen - * during debug. Reception FIFOs can still be accessed/controlled normally) - * or DISABLE (CAN is working during debug). - * @retval None - */ -void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable Debug Freeze */ - CANx->MCR |= MCR_DBF; - } - else - { - /* Disable Debug Freeze */ - CANx->MCR &= ~MCR_DBF; - } -} - -/** - * @brief Enables or disables the CAN Time TriggerOperation communication mode. - * @note DLC must be programmed as 8 in order Time Stamp (2 bytes) to be - * sent over the CAN bus. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param NewState: Mode new state. This parameter can be: ENABLE or DISABLE. - * When enabled, Time stamp (TIME[15:0]) value is sent in the last two - * data bytes of the 8-byte message: TIME[7:0] in data byte 6 and TIME[15:8] - * in data byte 7. - * @retval None - */ -void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the TTCM mode */ - CANx->MCR |= CAN_MCR_TTCM; - - /* Set TGT bits */ - CANx->sTxMailBox[0].TDTR |= ((uint32_t)CAN_TDT0R_TGT); - CANx->sTxMailBox[1].TDTR |= ((uint32_t)CAN_TDT1R_TGT); - CANx->sTxMailBox[2].TDTR |= ((uint32_t)CAN_TDT2R_TGT); - } - else - { - /* Disable the TTCM mode */ - CANx->MCR &= (uint32_t)(~(uint32_t)CAN_MCR_TTCM); - - /* Reset TGT bits */ - CANx->sTxMailBox[0].TDTR &= ((uint32_t)~CAN_TDT0R_TGT); - CANx->sTxMailBox[1].TDTR &= ((uint32_t)~CAN_TDT1R_TGT); - CANx->sTxMailBox[2].TDTR &= ((uint32_t)~CAN_TDT2R_TGT); - } -} -/** - * @} - */ - - -/** @defgroup CAN_Group2 CAN Frames Transmission functions - * @brief CAN Frames Transmission functions - * -@verbatim - =============================================================================== - ##### CAN Frames Transmission functions ##### - =============================================================================== - [..] This section provides functions allowing to - (+) Initiate and transmit a CAN frame message (if there is an empty mailbox). - (+) Check the transmission status of a CAN Frame. - (+) Cancel a transmit request. - -@endverbatim - * @{ - */ - -/** - * @brief Initiates and transmits a CAN frame message. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param TxMessage: pointer to a structure which contains CAN Id, CAN DLC and CAN data. - * @retval The number of the mailbox that is used for transmission or - * CAN_TxStatus_NoMailBox if there is no empty mailbox. - */ -uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage) -{ - uint8_t transmit_mailbox = 0; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_IDTYPE(TxMessage->IDE)); - assert_param(IS_CAN_RTR(TxMessage->RTR)); - assert_param(IS_CAN_DLC(TxMessage->DLC)); - - /* Select one empty transmit mailbox */ - if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) - { - transmit_mailbox = 0; - } - else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) - { - transmit_mailbox = 1; - } - else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) - { - transmit_mailbox = 2; - } - else - { - transmit_mailbox = CAN_TxStatus_NoMailBox; - } - - if (transmit_mailbox != CAN_TxStatus_NoMailBox) - { - /* Set up the Id */ - CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ; - if (TxMessage->IDE == CAN_Id_Standard) - { - assert_param(IS_CAN_STDID(TxMessage->StdId)); - CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | \ - TxMessage->RTR); - } - else - { - assert_param(IS_CAN_EXTID(TxMessage->ExtId)); - CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId << 3) | \ - TxMessage->IDE | \ - TxMessage->RTR); - } - - /* Set up the DLC */ - TxMessage->DLC &= (uint8_t)0x0000000F; - CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0; - CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC; - - /* Set up the data field */ - CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) | - ((uint32_t)TxMessage->Data[2] << 16) | - ((uint32_t)TxMessage->Data[1] << 8) | - ((uint32_t)TxMessage->Data[0])); - CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) | - ((uint32_t)TxMessage->Data[6] << 16) | - ((uint32_t)TxMessage->Data[5] << 8) | - ((uint32_t)TxMessage->Data[4])); - /* Request transmission */ - CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ; - } - return transmit_mailbox; -} - -/** - * @brief Checks the transmission status of a CAN Frame. - * @param CANx: where x can be 1 to select the CAN peripheral. - * @param TransmitMailbox: the number of the mailbox that is used for transmission. - * @retval CAN_TxStatus_Ok if the CAN driver transmits the message, - * CAN_TxStatus_Failed in an other case. - */ -uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox) -{ - uint32_t state = 0; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox)); - - switch (TransmitMailbox) - { - case (CAN_TXMAILBOX_0): - state = CANx->TSR & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0); - break; - case (CAN_TXMAILBOX_1): - state = CANx->TSR & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1); - break; - case (CAN_TXMAILBOX_2): - state = CANx->TSR & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2); - break; - default: - state = CAN_TxStatus_Failed; - break; - } - switch (state) - { - /* transmit pending */ - case (0x0): state = CAN_TxStatus_Pending; - break; - /* transmit failed */ - case (CAN_TSR_RQCP0 | CAN_TSR_TME0): state = CAN_TxStatus_Failed; - break; - case (CAN_TSR_RQCP1 | CAN_TSR_TME1): state = CAN_TxStatus_Failed; - break; - case (CAN_TSR_RQCP2 | CAN_TSR_TME2): state = CAN_TxStatus_Failed; - break; - /* transmit succeeded */ - case (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0):state = CAN_TxStatus_Ok; - break; - case (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1):state = CAN_TxStatus_Ok; - break; - case (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2):state = CAN_TxStatus_Ok; - break; - default: state = CAN_TxStatus_Failed; - break; - } - return (uint8_t) state; -} - -/** - * @brief Cancels a transmit request. - * @param CANx: where x can be 1 to select the CAN peripheral. - * @param Mailbox: Mailbox number. - * @retval None - */ -void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox)); - /* abort transmission */ - switch (Mailbox) - { - case (CAN_TXMAILBOX_0): CANx->TSR |= CAN_TSR_ABRQ0; - break; - case (CAN_TXMAILBOX_1): CANx->TSR |= CAN_TSR_ABRQ1; - break; - case (CAN_TXMAILBOX_2): CANx->TSR |= CAN_TSR_ABRQ2; - break; - default: - break; - } -} -/** - * @} - */ - - -/** @defgroup CAN_Group3 CAN Frames Reception functions - * @brief CAN Frames Reception functions - * -@verbatim - =============================================================================== - ##### CAN Frames Reception functions ##### - =============================================================================== - [..] This section provides functions allowing to - (+) Receive a correct CAN frame. - (+) Release a specified receive FIFO (2 FIFOs are available). - (+) Return the number of the pending received CAN frames. - -@endverbatim - * @{ - */ - -/** - * @brief Receives a correct CAN frame. - * @param CANx: where x can be 1 to select the CAN peripheral. - * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @param RxMessage: pointer to a structure receive frame which contains CAN Id, - * CAN DLC, CAN data and FMI number. - * @retval None - */ -void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_FIFO(FIFONumber)); - /* Get the Id */ - RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR; - if (RxMessage->IDE == CAN_Id_Standard) - { - RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21); - } - else - { - RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3); - } - - RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR; - /* Get the DLC */ - RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR; - /* Get the FMI */ - RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8); - /* Get the data field */ - RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR; - RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8); - RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16); - RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24); - RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR; - RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8); - RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16); - RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24); - /* Release the FIFO */ - /* Release FIFO0 */ - if (FIFONumber == CAN_FIFO0) - { - CANx->RF0R |= CAN_RF0R_RFOM0; - } - /* Release FIFO1 */ - else /* FIFONumber == CAN_FIFO1 */ - { - CANx->RF1R |= CAN_RF1R_RFOM1; - } -} - -/** - * @brief Releases the specified receive FIFO. - * @param CANx: where x can be 1 to select the CAN peripheral. - * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1. - * @retval None - */ -void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_FIFO(FIFONumber)); - /* Release FIFO0 */ - if (FIFONumber == CAN_FIFO0) - { - CANx->RF0R |= CAN_RF0R_RFOM0; - } - /* Release FIFO1 */ - else /* FIFONumber == CAN_FIFO1 */ - { - CANx->RF1R |= CAN_RF1R_RFOM1; - } -} - -/** - * @brief Returns the number of pending received messages. - * @param CANx: where x can be 1 to select the CAN peripheral. - * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @retval NbMessage : which is the number of pending message. - */ -uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber) -{ - uint8_t message_pending=0; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_FIFO(FIFONumber)); - if (FIFONumber == CAN_FIFO0) - { - message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03); - } - else if (FIFONumber == CAN_FIFO1) - { - message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03); - } - else - { - message_pending = 0; - } - return message_pending; -} -/** - * @} - */ - - -/** @defgroup CAN_Group4 CAN Operation modes functions - * @brief CAN Operation modes functions - * -@verbatim - =============================================================================== - ##### CAN Operation modes functions ##### - =============================================================================== - [..] This section provides functions allowing to select the CAN Operation modes: - (+) sleep mode. - (+) normal mode. - (+) initialization mode. - -@endverbatim - * @{ - */ - - -/** - * @brief Selects the CAN Operation mode. - * @param CAN_OperatingMode: CAN Operating Mode. - * This parameter can be one of @ref CAN_OperatingMode_TypeDef enumeration. - * @retval status of the requested mode which can be: - * - CAN_ModeStatus_Failed: CAN failed entering the specific mode - * - CAN_ModeStatus_Success: CAN Succeed entering the specific mode - */ -uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode) -{ - uint8_t status = CAN_ModeStatus_Failed; - - /* Timeout for INAK or also for SLAK bits*/ - uint32_t timeout = INAK_TIMEOUT; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode)); - - if (CAN_OperatingMode == CAN_OperatingMode_Initialization) - { - /* Request initialisation */ - CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_SLEEP)) | CAN_MCR_INRQ); - - /* Wait the acknowledge */ - while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0)) - { - timeout--; - } - if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) - { - status = CAN_ModeStatus_Failed; - } - else - { - status = CAN_ModeStatus_Success; - } - } - else if (CAN_OperatingMode == CAN_OperatingMode_Normal) - { - /* Request leave initialisation and sleep mode and enter Normal mode */ - CANx->MCR &= (uint32_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ)); - - /* Wait the acknowledge */ - while (((CANx->MSR & CAN_MODE_MASK) != 0) && (timeout!=0)) - { - timeout--; - } - if ((CANx->MSR & CAN_MODE_MASK) != 0) - { - status = CAN_ModeStatus_Failed; - } - else - { - status = CAN_ModeStatus_Success; - } - } - else if (CAN_OperatingMode == CAN_OperatingMode_Sleep) - { - /* Request Sleep mode */ - CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); - - /* Wait the acknowledge */ - while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0)) - { - timeout--; - } - if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) - { - status = CAN_ModeStatus_Failed; - } - else - { - status = CAN_ModeStatus_Success; - } - } - else - { - status = CAN_ModeStatus_Failed; - } - - return (uint8_t) status; -} - -/** - * @brief Enters the Sleep (low power) mode. - * @param CANx: where x can be 1 to select the CAN peripheral. - * @retval CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed otherwise. - */ -uint8_t CAN_Sleep(CAN_TypeDef* CANx) -{ - uint8_t sleepstatus = CAN_Sleep_Failed; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Request Sleep mode */ - CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); - - /* Sleep mode status */ - if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK) - { - /* Sleep mode not entered */ - sleepstatus = CAN_Sleep_Ok; - } - /* return sleep mode status */ - return (uint8_t)sleepstatus; -} - -/** - * @brief Wakes up the CAN peripheral from sleep mode . - * @param CANx: where x can be 1 to select the CAN peripheral. - * @retval CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed otherwise. - */ -uint8_t CAN_WakeUp(CAN_TypeDef* CANx) -{ - uint32_t wait_slak = SLAK_TIMEOUT; - uint8_t wakeupstatus = CAN_WakeUp_Failed; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Wake up request */ - CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP; - - /* Sleep mode status */ - while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00)) - { - wait_slak--; - } - if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK) - { - /* wake up done : Sleep mode exited */ - wakeupstatus = CAN_WakeUp_Ok; - } - /* return wakeup status */ - return (uint8_t)wakeupstatus; -} -/** - * @} - */ - - -/** @defgroup CAN_Group5 CAN Bus Error management functions - * @brief CAN Bus Error management functions - * -@verbatim - =============================================================================== - ##### CAN Bus Error management functions ##### - =============================================================================== - [..] This section provides functions allowing to - (+) Return the CANx's last error code (LEC). - (+) Return the CANx Receive Error Counter (REC). - (+) Return the LSB of the 9-bit CANx Transmit Error Counter(TEC). - [..] - (@) If TEC is greater than 255, The CAN is in bus-off state. - (@) If REC or TEC are greater than 96, an Error warning flag occurs. - (@) If REC or TEC are greater than 127, an Error Passive Flag occurs. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the CANx's last error code (LEC). - * @param CANx: where x can be 1 to select the CAN peripheral. - * @retval Error code: - * - CAN_ERRORCODE_NoErr: No Error - * - CAN_ERRORCODE_StuffErr: Stuff Error - * - CAN_ERRORCODE_FormErr: Form Error - * - CAN_ERRORCODE_ACKErr : Acknowledgment Error - * - CAN_ERRORCODE_BitRecessiveErr: Bit Recessive Error - * - CAN_ERRORCODE_BitDominantErr: Bit Dominant Error - * - CAN_ERRORCODE_CRCErr: CRC Error - * - CAN_ERRORCODE_SoftwareSetErr: Software Set Error - */ -uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx) -{ - uint8_t errorcode=0; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Get the error code*/ - errorcode = (((uint8_t)CANx->ESR) & (uint8_t)CAN_ESR_LEC); - - /* Return the error code*/ - return errorcode; -} - -/** - * @brief Returns the CANx Receive Error Counter (REC). - * @note In case of an error during reception, this counter is incremented - * by 1 or by 8 depending on the error condition as defined by the CAN - * standard. After every successful reception, the counter is - * decremented by 1 or reset to 120 if its value was higher than 128. - * When the counter value exceeds 127, the CAN controller enters the - * error passive state. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @retval CAN Receive Error Counter. - */ -uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx) -{ - uint8_t counter=0; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Get the Receive Error Counter*/ - counter = (uint8_t)((CANx->ESR & CAN_ESR_REC)>> 24); - - /* Return the Receive Error Counter*/ - return counter; -} - - -/** - * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC). - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @retval LSB of the 9-bit CAN Transmit Error Counter. - */ -uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx) -{ - uint8_t counter=0; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ - counter = (uint8_t)((CANx->ESR & CAN_ESR_TEC)>> 16); - - /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ - return counter; -} -/** - * @} - */ - -/** @defgroup CAN_Group6 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - [..] This section provides functions allowing to configure the CAN Interrupts - and to get the status and clear flags and Interrupts pending bits. - [..] The CAN provides 14 Interrupts sources and 15 Flags: - - *** Flags *** - ============= - [..] The 15 flags can be divided on 4 groups: - (+) Transmit Flags: - (++) CAN_FLAG_RQCP0. - (++) CAN_FLAG_RQCP1. - (++) CAN_FLAG_RQCP2: Request completed MailBoxes 0, 1 and 2 Flags - Set when when the last request (transmit or abort) has - been performed. - (+) Receive Flags: - (++) CAN_FLAG_FMP0. - (++) CAN_FLAG_FMP1: FIFO 0 and 1 Message Pending Flags; - Set to signal that messages are pending in the receive FIFO. - These Flags are cleared only by hardware. - (++) CAN_FLAG_FF0. - (++) CAN_FLAG_FF1: FIFO 0 and 1 Full Flags; - Set when three messages are stored in the selected FIFO. - (++) CAN_FLAG_FOV0. - (++) CAN_FLAG_FOV1: FIFO 0 and 1 Overrun Flags; - Set when a new message has been received and passed the filter - while the FIFO was full. - (+) Operating Mode Flags: - (++) CAN_FLAG_WKU: Wake up Flag; - Set to signal that a SOF bit has been detected while the CAN - hardware was in Sleep mode. - (++) CAN_FLAG_SLAK: Sleep acknowledge Flag; - Set to signal that the CAN has entered Sleep Mode. - (+) Error Flags: - (++) CAN_FLAG_EWG: Error Warning Flag; - Set when the warning limit has been reached (Receive Error Counter - or Transmit Error Counter greater than 96). - This Flag is cleared only by hardware. - (++) CAN_FLAG_EPV: Error Passive Flag; - Set when the Error Passive limit has been reached (Receive Error - Counter or Transmit Error Counter greater than 127). - This Flag is cleared only by hardware. - (++) CAN_FLAG_BOF: Bus-Off Flag; - Set when CAN enters the bus-off state. The bus-off state is - entered on TEC overflow, greater than 255. - This Flag is cleared only by hardware. - (++) CAN_FLAG_LEC: Last error code Flag; - Set If a message has been transferred (reception or transmission) - with error, and the error code is hold. - - *** Interrupts *** - ================== - [..] The 14 interrupts can be divided on 4 groups: - (+) Transmit interrupt: - (++) CAN_IT_TME: Transmit mailbox empty Interrupt; - If enabled, this interrupt source is pending when no transmit - request are pending for Tx mailboxes. - (+) Receive Interrupts: - (++) CAN_IT_FMP0. - (++) CAN_IT_FMP1: FIFO 0 and FIFO1 message pending Interrupts; - If enabled, these interrupt sources are pending when messages - are pending in the receive FIFO. - The corresponding interrupt pending bits are cleared only by hardware. - (++) CAN_IT_FF0. - (++) CAN_IT_FF1: FIFO 0 and FIFO1 full Interrupts; - If enabled, these interrupt sources are pending when three messages - are stored in the selected FIFO. - (++) CAN_IT_FOV0. - (++) CAN_IT_FOV1: FIFO 0 and FIFO1 overrun Interrupts; - If enabled, these interrupt sources are pending when a new message - has been received and passed the filter while the FIFO was full. - (+) Operating Mode Interrupts: - (++) CAN_IT_WKU: Wake-up Interrupt; - If enabled, this interrupt source is pending when a SOF bit has - been detected while the CAN hardware was in Sleep mode. - (++) CAN_IT_SLK: Sleep acknowledge Interrupt: - If enabled, this interrupt source is pending when the CAN has - entered Sleep Mode. - (+) Error Interrupts: - (++) CAN_IT_EWG: Error warning Interrupt; - If enabled, this interrupt source is pending when the warning limit - has been reached (Receive Error Counter or Transmit Error Counter=96). - (++) CAN_IT_EPV: Error passive Interrupt; - If enabled, this interrupt source is pending when the Error Passive - limit has been reached (Receive Error Counter or Transmit Error Counter>127). - (++) CAN_IT_BOF: Bus-off Interrupt; - If enabled, this interrupt source is pending when CAN enters - the bus-off state. The bus-off state is entered on TEC overflow, - greater than 255. - This Flag is cleared only by hardware. - (++) CAN_IT_LEC: Last error code Interrupt; - If enabled, this interrupt source is pending when a message has - been transferred (reception or transmission) with error and the - error code is hold. - (++) CAN_IT_ERR: Error Interrupt; - If enabled, this interrupt source is pending when an error condition - is pending. - [..] Managing the CAN controller events: - The user should identify which mode will be used in his application to manage - the CAN controller events: Polling mode or Interrupt mode. - (+) In the Polling Mode it is advised to use the following functions: - (++) CAN_GetFlagStatus() : to check if flags events occur. - (++) CAN_ClearFlag() : to clear the flags events. - (+) In the Interrupt Mode it is advised to use the following functions: - (++) CAN_ITConfig() : to enable or disable the interrupt source. - (++) CAN_GetITStatus() : to check if Interrupt occurs. - (++) CAN_ClearITPendingBit() : to clear the Interrupt pending Bit - (corresponding Flag). - This function has no impact on CAN_IT_FMP0 and CAN_IT_FMP1 Interrupts - pending bits since there are cleared only by hardware. - -@endverbatim - * @{ - */ -/** - * @brief Enables or disables the specified CANx interrupts. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled. - * This parameter can be: - * @arg CAN_IT_TME: Transmit mailbox empty Interrupt - * @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt - * @arg CAN_IT_FF0: FIFO 0 full Interrupt - * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt - * @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt - * @arg CAN_IT_FF1: FIFO 1 full Interrupt - * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt - * @arg CAN_IT_WKU: Wake-up Interrupt - * @arg CAN_IT_SLK: Sleep acknowledge Interrupt - * @arg CAN_IT_EWG: Error warning Interrupt - * @arg CAN_IT_EPV: Error passive Interrupt - * @arg CAN_IT_BOF: Bus-off Interrupt - * @arg CAN_IT_LEC: Last error code Interrupt - * @arg CAN_IT_ERR: Error Interrupt - * @param NewState: new state of the CAN interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_IT(CAN_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected CANx interrupt */ - CANx->IER |= CAN_IT; - } - else - { - /* Disable the selected CANx interrupt */ - CANx->IER &= ~CAN_IT; - } -} -/** - * @brief Checks whether the specified CAN flag is set or not. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag - * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag - * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag - * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag - * @arg CAN_FLAG_FF0: FIFO 0 Full Flag - * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag - * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag - * @arg CAN_FLAG_FF1: FIFO 1 Full Flag - * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag - * @arg CAN_FLAG_WKU: Wake up Flag - * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag - * @arg CAN_FLAG_EWG: Error Warning Flag - * @arg CAN_FLAG_EPV: Error Passive Flag - * @arg CAN_FLAG_BOF: Bus-Off Flag - * @arg CAN_FLAG_LEC: Last error code Flag - * @retval The new state of CAN_FLAG (SET or RESET). - */ -FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_GET_FLAG(CAN_FLAG)); - - - if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET) - { - /* Check the status of the specified CAN flag */ - if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET) - { - /* Check the status of the specified CAN flag */ - if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET) - { - /* Check the status of the specified CAN flag */ - if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET) - { - /* Check the status of the specified CAN flag */ - if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */ - { - /* Check the status of the specified CAN flag */ - if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - /* Return the CAN_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the CAN's pending flags. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_FLAG: specifies the flag to clear. - * This parameter can be one of the following values: - * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag - * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag - * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag - * @arg CAN_FLAG_FF0: FIFO 0 Full Flag - * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag - * @arg CAN_FLAG_FF1: FIFO 1 Full Flag - * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag - * @arg CAN_FLAG_WKU: Wake up Flag - * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag - * @arg CAN_FLAG_LEC: Last error code Flag - * @retval None - */ -void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG) -{ - uint32_t flagtmp=0; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG)); - - if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */ - { - /* Clear the selected CAN flags */ - CANx->ESR = (uint32_t)RESET; - } - else /* MSR or TSR or RF0R or RF1R */ - { - flagtmp = CAN_FLAG & 0x000FFFFF; - - if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET) - { - /* Receive Flags */ - CANx->RF0R = (uint32_t)(flagtmp); - } - else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET) - { - /* Receive Flags */ - CANx->RF1R = (uint32_t)(flagtmp); - } - else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET) - { - /* Transmit Flags */ - CANx->TSR = (uint32_t)(flagtmp); - } - else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */ - { - /* Operating mode Flags */ - CANx->MSR = (uint32_t)(flagtmp); - } - } -} - -/** - * @brief Checks whether the specified CANx interrupt has occurred or not. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_IT: specifies the CAN interrupt source to check. - * This parameter can be one of the following values: - * @arg CAN_IT_TME: Transmit mailbox empty Interrupt - * @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt - * @arg CAN_IT_FF0: FIFO 0 full Interrupt - * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt - * @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt - * @arg CAN_IT_FF1: FIFO 1 full Interrupt - * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt - * @arg CAN_IT_WKU: Wake-up Interrupt - * @arg CAN_IT_SLK: Sleep acknowledge Interrupt - * @arg CAN_IT_EWG: Error warning Interrupt - * @arg CAN_IT_EPV: Error passive Interrupt - * @arg CAN_IT_BOF: Bus-off Interrupt - * @arg CAN_IT_LEC: Last error code Interrupt - * @arg CAN_IT_ERR: Error Interrupt - * @retval The current state of CAN_IT (SET or RESET). - */ -ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT) -{ - ITStatus itstatus = RESET; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_IT(CAN_IT)); - - /* check the interrupt enable bit */ - if((CANx->IER & CAN_IT) != RESET) - { - /* in case the Interrupt is enabled, .... */ - switch (CAN_IT) - { - case CAN_IT_TME: - /* Check CAN_TSR_RQCPx bits */ - itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2); - break; - case CAN_IT_FMP0: - /* Check CAN_RF0R_FMP0 bit */ - itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0); - break; - case CAN_IT_FF0: - /* Check CAN_RF0R_FULL0 bit */ - itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0); - break; - case CAN_IT_FOV0: - /* Check CAN_RF0R_FOVR0 bit */ - itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0); - break; - case CAN_IT_FMP1: - /* Check CAN_RF1R_FMP1 bit */ - itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1); - break; - case CAN_IT_FF1: - /* Check CAN_RF1R_FULL1 bit */ - itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1); - break; - case CAN_IT_FOV1: - /* Check CAN_RF1R_FOVR1 bit */ - itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1); - break; - case CAN_IT_WKU: - /* Check CAN_MSR_WKUI bit */ - itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI); - break; - case CAN_IT_SLK: - /* Check CAN_MSR_SLAKI bit */ - itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI); - break; - case CAN_IT_EWG: - /* Check CAN_ESR_EWGF bit */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF); - break; - case CAN_IT_EPV: - /* Check CAN_ESR_EPVF bit */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF); - break; - case CAN_IT_BOF: - /* Check CAN_ESR_BOFF bit */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF); - break; - case CAN_IT_LEC: - /* Check CAN_ESR_LEC bit */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC); - break; - case CAN_IT_ERR: - /* Check CAN_MSR_ERRI bit */ - itstatus = CheckITStatus(CANx->MSR, CAN_MSR_ERRI); - break; - default: - /* in case of error, return RESET */ - itstatus = RESET; - break; - } - } - else - { - /* in case the Interrupt is not enabled, return RESET */ - itstatus = RESET; - } - - /* Return the CAN_IT status */ - return itstatus; -} - -/** - * @brief Clears the CANx's interrupt pending bits. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_IT: specifies the interrupt pending bit to clear. - * This parameter can be one of the following values: - * @arg CAN_IT_TME: Transmit mailbox empty Interrupt - * @arg CAN_IT_FF0: FIFO 0 full Interrupt - * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt - * @arg CAN_IT_FF1: FIFO 1 full Interrupt - * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt - * @arg CAN_IT_WKU: Wake-up Interrupt - * @arg CAN_IT_SLK: Sleep acknowledge Interrupt - * @arg CAN_IT_EWG: Error warning Interrupt - * @arg CAN_IT_EPV: Error passive Interrupt - * @arg CAN_IT_BOF: Bus-off Interrupt - * @arg CAN_IT_LEC: Last error code Interrupt - * @arg CAN_IT_ERR: Error Interrupt - * @retval None - */ -void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_CLEAR_IT(CAN_IT)); - - switch (CAN_IT) - { - case CAN_IT_TME: - /* Clear CAN_TSR_RQCPx (rc_w1)*/ - CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2; - break; - case CAN_IT_FF0: - /* Clear CAN_RF0R_FULL0 (rc_w1)*/ - CANx->RF0R = CAN_RF0R_FULL0; - break; - case CAN_IT_FOV0: - /* Clear CAN_RF0R_FOVR0 (rc_w1)*/ - CANx->RF0R = CAN_RF0R_FOVR0; - break; - case CAN_IT_FF1: - /* Clear CAN_RF1R_FULL1 (rc_w1)*/ - CANx->RF1R = CAN_RF1R_FULL1; - break; - case CAN_IT_FOV1: - /* Clear CAN_RF1R_FOVR1 (rc_w1)*/ - CANx->RF1R = CAN_RF1R_FOVR1; - break; - case CAN_IT_WKU: - /* Clear CAN_MSR_WKUI (rc_w1)*/ - CANx->MSR = CAN_MSR_WKUI; - break; - case CAN_IT_SLK: - /* Clear CAN_MSR_SLAKI (rc_w1)*/ - CANx->MSR = CAN_MSR_SLAKI; - break; - case CAN_IT_EWG: - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/ - break; - case CAN_IT_EPV: - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/ - break; - case CAN_IT_BOF: - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/ - break; - case CAN_IT_LEC: - /* Clear LEC bits */ - CANx->ESR = RESET; - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - break; - case CAN_IT_ERR: - /*Clear LEC bits */ - CANx->ESR = RESET; - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - /* @note BOFF, EPVF and EWGF Flags are cleared by hardware depending on the CAN Bus status*/ - break; - default: - break; - } -} - /** - * @} - */ - -/** - * @brief Checks whether the CAN interrupt has occurred or not. - * @param CAN_Reg: specifies the CAN interrupt register to check. - * @param It_Bit: specifies the interrupt source bit to check. - * @retval The new state of the CAN Interrupt (SET or RESET). - */ -static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit) -{ - ITStatus pendingbitstatus = RESET; - - if ((CAN_Reg & It_Bit) != (uint32_t)RESET) - { - /* CAN_IT is set */ - pendingbitstatus = SET; - } - else - { - /* CAN_IT is reset */ - pendingbitstatus = RESET; - } - return pendingbitstatus; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_cec.c b/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_cec.c deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_cec.c +++ /dev/null @@ -1,607 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_cec.c - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the Consumer Electronics Control (CEC) peripheral - * applicable only on STM32F051, STM32F042 and STM32F072 devices: - * + Initialization and Configuration - * + Data transfers functions - * + Interrupts and flags management - * - * @verbatim - ============================================================================== - ##### CEC features ##### - ============================================================================== - [..] This device provides some features: - (#) Supports HDMI-CEC specification 1.4. - (#) Supports two source clocks(HSI/244 or LSE). - (#) Works in stop mode(without APB clock, but with CEC clock 32KHz). - It can genarate an interrupt in the CEC clock domain that the CPU - wakes up from the low power mode. - (#) Configurable Signal Free Time before of transmission start. The - number of nominal data bit periods waited before transmission can be - ruled by Hardware or Software. - (#) Configurable Peripheral Address (multi-addressing configuration). - (#) Supports listen mode.The CEC Messages addressed to different destination - can be received without interfering with CEC bus when Listen mode option is enabled. - (#) Configurable Rx-Tolerance(Standard and Extended tolerance margin). - (#) Error detection with configurable error bit generation. - (#) Arbitration lost error in the case of two CEC devices starting at the same time. - - ##### How to use this driver ##### - ============================================================================== - [..] This driver provides functions to configure and program the CEC device, - follow steps below: - (#) The source clock can be configured using: - (++) RCC_CECCLKConfig(RCC_CECCLK_HSI_Div244) for HSI(Default) - (++) RCC_CECCLKConfig(RCC_CECCLK_LSE) for LSE. - (#) Enable CEC peripheral clock using RCC_APBPeriphClockCmd(RCC_APBPeriph_CEC, ENABLE). - (#) Peripherals alternate function. - (++) Connect the pin to the desired peripherals' Alternate Function (AF) using - GPIO_PinAFConfig() function. - (++) Configure the desired pin in alternate function by: - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF. - (++) Select the type open-drain and output speed via GPIO_OType - and GPIO_Speed members. - (++) Call GPIO_Init() function. - (#) Configure the Signal Free Time, Rx Tolerance, Stop reception generation - and Bit error generation using the CEC_Init() function. - The function CEC_Init() must be called when the CEC peripheral is disabled. - (#) Configure the CEC own address by calling the fuction CEC_OwnAddressConfig(). - (#) Optionally, you can configure the Listen mode using the function CEC_ListenModeCmd(). - (#) Enable the NVIC and the corresponding interrupt using the function - CEC_ITConfig() if you need to use interrupt mode. - CEC_ITConfig() must be called before enabling the CEC peripheral. - (#) Enable the CEC using the CEC_Cmd() function. - (#) Charge the first data byte in the TXDR register using CEC_SendDataByte(). - (#) Enable the transmission of the Byte of a CEC message using CEC_StartOfMessage() - (#) Transmit single data through the CEC peripheral using CEC_SendDataByte() - and Receive the last transmitted byte using CEC_ReceiveDataByte(). - (#) Enable the CEC_EndOfMessage() in order to indicate the last byte of the message. - [..] - (@) If the listen mode is enabled, Stop reception generation and Bit error generation - must be in reset state. - (@) If the CEC message consists of only 1 byte, the function CEC_EndOfMessage() - must be called before CEC_StartOfMessage(). - - @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_cec.h" -#include "stm32f0xx_rcc.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup CEC - * @brief CEC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define BROADCAST_ADDRESS ((uint32_t)0x0000F) -#define CFGR_CLEAR_MASK ((uint32_t)0x7000FE00) /* CFGR register Mask */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup CEC_Private_Functions - * @{ - */ - -/** @defgroup CEC_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to initialize: - (+) CEC own addresses - (+) CEC Signal Free Time - (+) CEC Rx Tolerance - (+) CEC Stop Reception - (+) CEC Bit Rising Error - (+) CEC Long Bit Period Error - [..] This section provides also a function to configure the CEC peripheral in Listen Mode. - Messages addressed to different destination can be received when Listen mode is - enabled without interfering with CEC bus. -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the CEC peripheral registers to their default reset values. - * @param None - * @retval None - */ -void CEC_DeInit(void) -{ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE); -} - -/** - * @brief Initializes the CEC peripheral according to the specified parameters - * in the CEC_InitStruct. - * @note The CEC parameters must be configured before enabling the CEC peripheral. - * @param CEC_InitStruct: pointer to an CEC_InitTypeDef structure that contains - * the configuration information for the specified CEC peripheral. - * @retval None - */ -void CEC_Init(CEC_InitTypeDef* CEC_InitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_CEC_SIGNAL_FREE_TIME(CEC_InitStruct->CEC_SignalFreeTime)); - assert_param(IS_CEC_RX_TOLERANCE(CEC_InitStruct->CEC_RxTolerance)); - assert_param(IS_CEC_STOP_RECEPTION(CEC_InitStruct->CEC_StopReception)); - assert_param(IS_CEC_BIT_RISING_ERROR(CEC_InitStruct->CEC_BitRisingError)); - assert_param(IS_CEC_LONG_BIT_PERIOD_ERROR(CEC_InitStruct->CEC_LongBitPeriodError)); - assert_param(IS_CEC_BDR_NO_GEN_ERROR(CEC_InitStruct->CEC_BRDNoGen)); - assert_param(IS_CEC_SFT_OPTION(CEC_InitStruct->CEC_SFTOption)); - - /* Get the CEC CFGR value */ - tmpreg = CEC->CFGR; - - /* Clear CFGR bits */ - tmpreg &= CFGR_CLEAR_MASK; - - /* Configure the CEC peripheral */ - tmpreg |= (CEC_InitStruct->CEC_SignalFreeTime | CEC_InitStruct->CEC_RxTolerance | - CEC_InitStruct->CEC_StopReception | CEC_InitStruct->CEC_BitRisingError | - CEC_InitStruct->CEC_LongBitPeriodError| CEC_InitStruct->CEC_BRDNoGen | - CEC_InitStruct->CEC_SFTOption); - - /* Write to CEC CFGR register */ - CEC->CFGR = tmpreg; -} - -/** - * @brief Fills each CEC_InitStruct member with its default value. - * @param CEC_InitStruct: pointer to a CEC_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void CEC_StructInit(CEC_InitTypeDef* CEC_InitStruct) -{ - CEC_InitStruct->CEC_SignalFreeTime = CEC_SignalFreeTime_Standard; - CEC_InitStruct->CEC_RxTolerance = CEC_RxTolerance_Standard; - CEC_InitStruct->CEC_StopReception = CEC_StopReception_Off; - CEC_InitStruct->CEC_BitRisingError = CEC_BitRisingError_Off; - CEC_InitStruct->CEC_LongBitPeriodError = CEC_LongBitPeriodError_Off; - CEC_InitStruct->CEC_BRDNoGen = CEC_BRDNoGen_Off; - CEC_InitStruct->CEC_SFTOption = CEC_SFTOption_Off; -} - -/** - * @brief Enables or disables the CEC peripheral. - * @param NewState: new state of the CEC peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CEC_Cmd(FunctionalState NewState) -{ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the CEC peripheral */ - CEC->CR |= CEC_CR_CECEN; - } - else - { - /* Disable the CEC peripheral */ - CEC->CR &= ~CEC_CR_CECEN; - } -} - -/** - * @brief Enables or disables the CEC Listen Mode. - * @param NewState: new state of the Listen Mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CEC_ListenModeCmd(FunctionalState NewState) -{ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Listen Mode */ - CEC->CFGR |= CEC_CFGR_LSTN; - } - else - { - /* Disable the Listen Mode */ - CEC->CFGR &= ~CEC_CFGR_LSTN; - } -} - -/** - * @brief Defines the Own Address of the CEC device. - * @param CEC_OwnAddress: The CEC own address. - * @retval None - */ -void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress) -{ - uint32_t tmp =0x00; - /* Check the parameters */ - assert_param(IS_CEC_ADDRESS(CEC_OwnAddress)); - tmp = 1 <<(CEC_OwnAddress + 16); - /* Set the CEC own address */ - CEC->CFGR |= tmp; -} - -/** - * @brief Clears the Own Address of the CEC device. - * @param CEC_OwnAddress: The CEC own address. - * @retval None - */ -void CEC_OwnAddressClear(void) -{ - /* Set the CEC own address */ - CEC->CFGR = 0x0; -} - -/** - * @} - */ - -/** @defgroup CEC_Group2 Data transfers functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### Data transfers functions ##### - =============================================================================== - [..] This section provides functions allowing the CEC data transfers.The read - access of the CEC_RXDR register can be done using the CEC_ReceiveData()function - and returns the Rx buffered value. Whereas a write access to the CEC_TXDR can be - done using CEC_SendData() function. -@endverbatim - * @{ - */ - -/** - * @brief Transmits single data through the CEC peripheral. - * @param Data: the data to transmit. - * @retval None - */ -void CEC_SendData(uint8_t Data) -{ - /* Transmit Data */ - CEC->TXDR = Data; -} - -/** - * @brief Returns the most recent received data by the CEC peripheral. - * @param None - * @retval The received data. - */ -uint8_t CEC_ReceiveData(void) -{ - /* Receive Data */ - return (uint8_t)(CEC->RXDR); -} - -/** - * @brief Starts a new message. - * @param None - * @retval None - */ -void CEC_StartOfMessage(void) -{ - /* Starts of new message */ - CEC->CR |= CEC_CR_TXSOM; -} - -/** - * @brief Transmits message with an EOM bit. - * @param None - * @retval None - */ -void CEC_EndOfMessage(void) -{ - /* The data byte will be transmitted with an EOM bit */ - CEC->CR |= CEC_CR_TXEOM; -} - -/** - * @} - */ - -/** @defgroup CEC_Group3 Interrupts and flags management functions - * @brief Interrupts and flags management functions -* -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - [..] This section provides functions allowing to configure the CEC Interrupts - sources and check or clear the flags or pending bits status. - [..] The user should identify which mode will be used in his application to manage - the communication: Polling mode or Interrupt mode. - - [..] In polling mode, the CEC can be managed by the following flags: - (+) CEC_FLAG_TXACKE : to indicate a missing acknowledge in transmission mode. - (+) CEC_FLAG_TXERR : to indicate an error occurs during transmission mode. - The initiator detects low impedance in the CEC line. - (+) CEC_FLAG_TXUDR : to indicate if an underrun error occurs in transmission mode. - The transmission is enabled while the software has not yet - loaded any value into the TXDR register. - (+) CEC_FLAG_TXEND : to indicate the end of successful transmission. - (+) CEC_FLAG_TXBR : to indicate the next transmission data has to be written to TXDR. - (+) CEC_FLAG_ARBLST : to indicate arbitration lost in the case of two CEC devices - starting at the same time. - (+) CEC_FLAG_RXACKE : to indicate a missing acknowledge in receive mode. - (+) CEC_FLAG_LBPE : to indicate a long bit period error generated during receive mode. - (+) CEC_FLAG_SBPE : to indicate a short bit period error generated during receive mode. - (+) CEC_FLAG_BRE : to indicate a bit rising error generated during receive mode. - (+) CEC_FLAG_RXOVR : to indicate if an overrun error occur while receiving a CEC message. - A byte is not yet received while a new byte is stored in the RXDR register. - (+) CEC_FLAG_RXEND : to indicate the end Of reception - (+) CEC_FLAG_RXBR : to indicate a new byte has been received from the CEC line and - stored into the RXDR buffer. - [..] - (@)In this Mode, it is advised to use the following functions: - FlagStatus CEC_GetFlagStatus(uint16_t CEC_FLAG); - void CEC_ClearFlag(uint16_t CEC_FLAG); - - [..] In Interrupt mode, the CEC can be managed by the following interrupt sources: - (+) CEC_IT_TXACKE : to indicate a TX Missing acknowledge - (+) CEC_IT_TXACKE : to indicate a missing acknowledge in transmission mode. - (+) CEC_IT_TXERR : to indicate an error occurs during transmission mode. - The initiator detects low impedance in the CEC line. - (+) CEC_IT_TXUDR : to indicate if an underrun error occurs in transmission mode. - The transmission is enabled while the software has not yet - loaded any value into the TXDR register. - (+) CEC_IT_TXEND : to indicate the end of successful transmission. - (+) CEC_IT_TXBR : to indicate the next transmission data has to be written to TXDR register. - (+) CEC_IT_ARBLST : to indicate arbitration lost in the case of two CEC devices - starting at the same time. - (+) CEC_IT_RXACKE : to indicate a missing acknowledge in receive mode. - (+) CEC_IT_LBPE : to indicate a long bit period error generated during receive mode. - (+) CEC_IT_SBPE : to indicate a short bit period error generated during receive mode. - (+) CEC_IT_BRE : to indicate a bit rising error generated during receive mode. - (+) CEC_IT_RXOVR : to indicate if an overrun error occur while receiving a CEC message. - A byte is not yet received while a new byte is stored in the RXDR register. - (+) CEC_IT_RXEND : to indicate the end Of reception - (+) CEC_IT_RXBR : to indicate a new byte has been received from the CEC line and - stored into the RXDR buffer. - [..] - (@)In this Mode it is advised to use the following functions: - void CEC_ITConfig( uint16_t CEC_IT, FunctionalState NewState); - ITStatus CEC_GetITStatus(uint16_t CEC_IT); - void CEC_ClearITPendingBit(uint16_t CEC_IT); - - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the selected CEC interrupts. - * @param CEC_IT: specifies the CEC interrupt source to be enabled. - * This parameter can be any combination of the following values: - * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error - * @arg CEC_IT_TXERR: Tx Error. - * @arg CEC_IT_TXUDR: Tx-Buffer Underrun. - * @arg CEC_IT_TXEND: End of Transmission (successful transmission of the last byte). - * @arg CEC_IT_TXBR: Tx-Byte Request. - * @arg CEC_IT_ARBLST: Arbitration Lost - * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge - * @arg CEC_IT_LBPE: Rx Long period Error - * @arg CEC_IT_SBPE: Rx Short period Error - * @arg CEC_IT_BRE: Rx Bit Rising Error - * @arg CEC_IT_RXOVR: Rx Overrun. - * @arg CEC_IT_RXEND: End Of Reception - * @arg CEC_IT_RXBR: Rx-Byte Received - * @param NewState: new state of the selected CEC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CEC_ITConfig(uint16_t CEC_IT, FunctionalState NewState) -{ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_CEC_IT(CEC_IT)); - - if (NewState != DISABLE) - { - /* Enable the selected CEC interrupt */ - CEC->IER |= CEC_IT; - } - else - { - CEC_IT =~CEC_IT; - /* Disable the selected CEC interrupt */ - CEC->IER &= CEC_IT; - } -} - -/** - * @brief Gets the CEC flag status. - * @param CEC_FLAG: specifies the CEC flag to check. - * This parameter can be one of the following values: - * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error - * @arg CEC_FLAG_TXERR: Tx Error. - * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun. - * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte). - * @arg CEC_FLAG_TXBR: Tx-Byte Request. - * @arg CEC_FLAG_ARBLST: Arbitration Lost - * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge - * @arg CEC_FLAG_LBPE: Rx Long period Error - * @arg CEC_FLAG_SBPE: Rx Short period Error - * @arg CEC_FLAG_BRE: Rx Bit Rissing Error - * @arg CEC_FLAG_RXOVR: Rx Overrun. - * @arg CEC_FLAG_RXEND: End Of Reception. - * @arg CEC_FLAG_RXBR: Rx-Byte Received. - * @retval The new state of CEC_FLAG (SET or RESET) - */ -FlagStatus CEC_GetFlagStatus(uint16_t CEC_FLAG) -{ - FlagStatus bitstatus = RESET; - - assert_param(IS_CEC_GET_FLAG(CEC_FLAG)); - - /* Check the status of the specified CEC flag */ - if ((CEC->ISR & CEC_FLAG) != (uint16_t)RESET) - { - /* CEC flag is set */ - bitstatus = SET; - } - else - { - /* CEC flag is reset */ - bitstatus = RESET; - } - - /* Return the CEC flag status */ - return bitstatus; -} - -/** - * @brief Clears the CEC's pending flags. - * @param CEC_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error - * @arg CEC_FLAG_TXERR: Tx Error - * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun - * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte). - * @arg CEC_FLAG_TXBR: Tx-Byte Request - * @arg CEC_FLAG_ARBLST: Arbitration Lost - * @arg CEC_FLAG_RXACKE: Rx Missing Acknowledge - * @arg CEC_FLAG_LBPE: Rx Long period Error - * @arg CEC_FLAG_SBPE: Rx Short period Error - * @arg CEC_FLAG_BRE: Rx Bit Rising Error - * @arg CEC_FLAG_RXOVR: Rx Overrun - * @arg CEC_FLAG_RXEND: End Of Reception - * @arg CEC_FLAG_RXBR: Rx-Byte Received - * @retval None - */ -void CEC_ClearFlag(uint32_t CEC_FLAG) -{ - assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG)); - - /* Clear the selected CEC flag */ - CEC->ISR = CEC_FLAG; -} - -/** - * @brief Checks whether the specified CEC interrupt has occurred or not. - * @param CEC_IT: specifies the CEC interrupt source to check. - * This parameter can be one of the following values: - * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error - * @arg CEC_IT_TXERR: Tx Error. - * @arg CEC_IT_TXUDR: Tx-Buffer Underrun. - * @arg CEC_IT_TXEND: End of transmission (successful transmission of the last byte). - * @arg CEC_IT_TXBR: Tx-Byte Request. - * @arg CEC_IT_ARBLST: Arbitration Lost. - * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge. - * @arg CEC_IT_LBPE: Rx Long period Error. - * @arg CEC_IT_SBPE: Rx Short period Error. - * @arg CEC_IT_BRE: Rx Bit Rising Error. - * @arg CEC_IT_RXOVR: Rx Overrun. - * @arg CEC_IT_RXEND: End Of Reception. - * @arg CEC_IT_RXBR: Rx-Byte Received - * @retval The new state of CEC_IT (SET or RESET). - */ -ITStatus CEC_GetITStatus(uint16_t CEC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_CEC_GET_IT(CEC_IT)); - - /* Get the CEC IT enable bit status */ - enablestatus = (CEC->IER & CEC_IT); - - /* Check the status of the specified CEC interrupt */ - if (((CEC->ISR & CEC_IT) != (uint32_t)RESET) && enablestatus) - { - /* CEC interrupt is set */ - bitstatus = SET; - } - else - { - /* CEC interrupt is reset */ - bitstatus = RESET; - } - - /* Return the CEC interrupt status */ - return bitstatus; -} - -/** - * @brief Clears the CEC's interrupt pending bits. - * @param CEC_IT: specifies the CEC interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error - * @arg CEC_IT_TXERR: Tx Error - * @arg CEC_IT_TXUDR: Tx-Buffer Underrun - * @arg CEC_IT_TXEND: End of Transmission - * @arg CEC_IT_TXBR: Tx-Byte Request - * @arg CEC_IT_ARBLST: Arbitration Lost - * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge - * @arg CEC_IT_LBPE: Rx Long period Error - * @arg CEC_IT_SBPE: Rx Short period Error - * @arg CEC_IT_BRE: Rx Bit Rising Error - * @arg CEC_IT_RXOVR: Rx Overrun - * @arg CEC_IT_RXEND: End Of Reception - * @arg CEC_IT_RXBR: Rx-Byte Received - * @retval None - */ -void CEC_ClearITPendingBit(uint16_t CEC_IT) -{ - assert_param(IS_CEC_IT(CEC_IT)); - - /* Clear the selected CEC interrupt pending bits */ - CEC->ISR = CEC_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_comp.c b/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_comp.c deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_comp.c +++ /dev/null @@ -1,408 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_comp.c - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the comparators (COMP1 and COMP2) peripheral - * applicable only on STM32F051 and STM32F072 devices: - * + Comparators configuration - * + Window mode control - * - * @verbatim - * - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - - The device integrates two analog comparators COMP1 and COMP2: - (+) The non inverting input is set to PA1 for COMP1 and to PA3 - for COMP2. - - (+) The inverting input can be selected among: DAC1_OUT, DAC2_OUT - 1/4 VREFINT, 1/2 VERFINT, 3/4 VREFINT, VREFINT, - I/O (PA0 for COMP1 and PA2 for COMP2) - - (+) The COMP output is internally is available using COMP_GetOutputLevel() - and can be set on GPIO pins: PA0, PA6, PA11 for COMP1 - and PA2, PA7, PA12 for COMP2 - - (+) The COMP output can be redirected to embedded timers (TIM1, TIM2 - and TIM3) - - (+) The two comparators COMP1 and COMP2 can be combined in window - mode and only COMP1 non inverting (PA1) can be used as non- - inverting input. - - (+) The two comparators COMP1 and COMP2 have interrupt capability - with wake-up from Sleep and Stop modes (through the EXTI controller). - COMP1 and COMP2 outputs are internally connected to EXTI Line 21 - and EXTI Line 22 respectively. - - - ##### How to configure the comparator ##### - =============================================================================== - [..] - This driver provides functions to configure and program the Comparators - of all STM32F0xx devices. - - [..] To use the comparator, perform the following steps: - - (#) Enable the SYSCFG APB clock to get write access to comparator - register using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); - - (#) Configure the comparator input in analog mode using GPIO_Init() - - (#) Configure the comparator output in alternate function mode - using GPIO_Init() and use GPIO_PinAFConfig() function to map the - comparator output to the GPIO pin - - (#) Configure the comparator using COMP_Init() function: - (++) Select the inverting input - (++) Select the output polarity - (++) Select the output redirection - (++) Select the hysteresis level - (++) Select the power mode - - (#) Enable the comparator using COMP_Cmd() function - - (#) If required enable the COMP interrupt by configuring and enabling - EXTI line in Interrupt mode and selecting the desired sensitivity - level using EXTI_Init() function. After that enable the comparator - interrupt vector using NVIC_Init() function. - - @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_comp.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup COMP - * @brief COMP driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* CSR register Mask */ -#define COMP_CSR_CLEAR_MASK ((uint32_t)0x00003FFE) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup COMP_Private_Functions - * @{ - */ - -/** @defgroup COMP_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes COMP peripheral registers to their default reset values. - * @note Deinitialization can't be performed if the COMP configuration is locked. - * To unlock the configuration, perform a system reset. - * @param None - * @retval None - */ -void COMP_DeInit(void) -{ - COMP->CSR = ((uint32_t)0x00000000); /*!< Set COMP_CSR register to reset value */ -} - -/** - * @brief Initializes the COMP peripheral according to the specified parameters - * in COMP_InitStruct - * @note If the selected comparator is locked, initialization can't be performed. - * To unlock the configuration, perform a system reset. - * @note By default, PA1 is selected as COMP1 non inverting input. - * To use PA4 as COMP1 non inverting input call COMP_SwitchCmd() after COMP_Init() - * @param COMP_Selection: the selected comparator. - * This parameter can be one of the following values: - * @arg COMP_Selection_COMP1: COMP1 selected - * @arg COMP_Selection_COMP2: COMP2 selected - * @param COMP_InitStruct: pointer to an COMP_InitTypeDef structure that contains - * the configuration information for the specified COMP peripheral. - * @retval None - */ -void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_COMP_ALL_PERIPH(COMP_Selection)); - assert_param(IS_COMP_INVERTING_INPUT(COMP_InitStruct->COMP_InvertingInput)); - assert_param(IS_COMP_OUTPUT(COMP_InitStruct->COMP_Output)); - assert_param(IS_COMP_OUTPUT_POL(COMP_InitStruct->COMP_OutputPol)); - assert_param(IS_COMP_HYSTERESIS(COMP_InitStruct->COMP_Hysteresis)); - assert_param(IS_COMP_MODE(COMP_InitStruct->COMP_Mode)); - - /*!< Get the COMP_CSR register value */ - tmpreg = COMP->CSR; - - /*!< Clear the COMP1SW1, COMPx_IN_SEL, COMPx_OUT_TIM_SEL, COMPx_POL, COMPx_HYST and COMPx_PWR_MODE bits */ - tmpreg &= (uint32_t) ~(COMP_CSR_CLEAR_MASK<COMP_InvertingInput value */ - /*!< Set COMPxOUTSEL bits according to COMP_InitStruct->COMP_Output value */ - /*!< Set COMPxPOL bit according to COMP_InitStruct->COMP_OutputPol value */ - /*!< Set COMPxHYST bits according to COMP_InitStruct->COMP_Hysteresis value */ - /*!< Set COMPxMODE bits according to COMP_InitStruct->COMP_Mode value */ - tmpreg |= (uint32_t)((COMP_InitStruct->COMP_InvertingInput | COMP_InitStruct->COMP_Output | - COMP_InitStruct->COMP_OutputPol | COMP_InitStruct->COMP_Hysteresis | - COMP_InitStruct->COMP_Mode)<CSR = tmpreg; -} - -/** - * @brief Fills each COMP_InitStruct member with its default value. - * @param COMP_InitStruct: pointer to an COMP_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void COMP_StructInit(COMP_InitTypeDef* COMP_InitStruct) -{ - COMP_InitStruct->COMP_InvertingInput = COMP_InvertingInput_1_4VREFINT; - COMP_InitStruct->COMP_Output = COMP_Output_None; - COMP_InitStruct->COMP_OutputPol = COMP_OutputPol_NonInverted; - COMP_InitStruct->COMP_Hysteresis = COMP_Hysteresis_No; - COMP_InitStruct->COMP_Mode = COMP_Mode_UltraLowPower; -} - -/** - * @brief Enable or disable the COMP peripheral. - * @note If the selected comparator is locked, enable/disable can't be performed. - * To unlock the configuration, perform a system reset. - * @param COMP_Selection: the selected comparator. - * This parameter can be one of the following values: - * @arg COMP_Selection_COMP1: COMP1 selected - * @arg COMP_Selection_COMP2: COMP2 selected - * @param NewState: new state of the COMP peripheral. - * This parameter can be: ENABLE or DISABLE. - * @note When enabled, the comparator compares the non inverting input with - * the inverting input and the comparison result is available on comparator output. - * @note When disabled, the comparator doesn't perform comparison and the - * output level is low. - * @retval None - */ -void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_COMP_ALL_PERIPH(COMP_Selection)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected COMP peripheral */ - COMP->CSR |= (uint32_t) (1<CSR &= (uint32_t)(~((uint32_t)1<CSR |= (uint32_t) (COMP_CSR_COMP1SW1); - } - else - { - /* Open SW1 switch */ - COMP->CSR &= (uint32_t)(~COMP_CSR_COMP1SW1); - } -} - -/** - * @brief Return the output level (high or low) of the selected comparator. - * @note The output level depends on the selected polarity. - * @note If the polarity is not inverted: - * - Comparator output is low when the non-inverting input is at a lower - * voltage than the inverting input - * - Comparator output is high when the non-inverting input is at a higher - * voltage than the inverting input - * @note If the polarity is inverted: - * - Comparator output is high when the non-inverting input is at a lower - * voltage than the inverting input - * - Comparator output is low when the non-inverting input is at a higher - * voltage than the inverting input - * @param COMP_Selection: the selected comparator. - * This parameter can be one of the following values: - * @arg COMP_Selection_COMP1: COMP1 selected - * @arg COMP_Selection_COMP2: COMP2 selected - * @retval Returns the selected comparator output level: low or high. - * - */ -uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection) -{ - uint32_t compout = 0x0; - - /* Check the parameters */ - assert_param(IS_COMP_ALL_PERIPH(COMP_Selection)); - - /* Check if selected comparator output is high */ - if ((COMP->CSR & (COMP_CSR_COMP1OUT<CSR |= (uint32_t) COMP_CSR_WNDWEN; - } - else - { - /* Disable the window mode */ - COMP->CSR &= (uint32_t)(~COMP_CSR_WNDWEN); - } -} - -/** - * @} - */ - -/** @defgroup COMP_Group3 COMP configuration locking function - * @brief COMP1 and COMP2 configuration locking function - * COMP1 and COMP2 configuration can be locked each separately. - * Unlocking is performed by system reset. - * -@verbatim - =============================================================================== - ##### Configuration Lock function ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Lock the selected comparator (COMP1/COMP2) configuration. - * @note Locking the configuration means that all control bits are read-only. - * To unlock the comparator configuration, perform a system reset. - * @param COMP_Selection: selects the comparator to be locked - * This parameter can be a value of the following values: - * @arg COMP_Selection_COMP1: COMP1 configuration is locked. - * @arg COMP_Selection_COMP2: COMP2 configuration is locked. - * @retval None - */ -void COMP_LockConfig(uint32_t COMP_Selection) -{ - /* Check the parameter */ - assert_param(IS_COMP_ALL_PERIPH(COMP_Selection)); - - /* Set the lock bit corresponding to selected comparator */ - COMP->CSR |= (uint32_t) (COMP_CSR_COMP1LOCK<
© COPYRIGHT 2014 STMicroelectronics
- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_crc.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup CRC - * @brief CRC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup CRC_Private_Functions - * @{ - */ - -/** @defgroup CRC_Group1 Configuration of the CRC computation unit functions - * @brief Configuration of the CRC computation unit functions - * -@verbatim - =============================================================================== - ##### CRC configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes CRC peripheral registers to their default reset values. - * @param None - * @retval None - */ -void CRC_DeInit(void) -{ - /* Set DR register to reset value */ - CRC->DR = 0xFFFFFFFF; - - /* Set the POL register to the reset value: 0x04C11DB7 */ - CRC->POL = 0x04C11DB7; - - /* Reset IDR register */ - CRC->IDR = 0x00; - - /* Set INIT register to reset value */ - CRC->INIT = 0xFFFFFFFF; - - /* Reset the CRC calculation unit */ - CRC->CR = CRC_CR_RESET; -} - -/** - * @brief Resets the CRC calculation unit and sets INIT register content in DR register. - * @param None - * @retval None - */ -void CRC_ResetDR(void) -{ - /* Reset CRC generator */ - CRC->CR |= CRC_CR_RESET; -} - -/** - * @brief Selects the polynomial size. This function is only applicable for - * STM32F072 devices. - * @param CRC_PolSize: Specifies the polynomial size. - * This parameter can be: - * @arg CRC_PolSize_7: 7-bit polynomial for CRC calculation - * @arg CRC_PolSize_8: 8-bit polynomial for CRC calculation - * @arg CRC_PolSize_16: 16-bit polynomial for CRC calculation - * @arg CRC_PolSize_32: 32-bit polynomial for CRC calculation - * @retval None - */ -void CRC_PolynomialSizeSelect(uint32_t CRC_PolSize) -{ - uint32_t tmpcr = 0; - - /* Check the parameter */ - assert_param(IS_CRC_POL_SIZE(CRC_PolSize)); - - /* Get CR register value */ - tmpcr = CRC->CR; - - /* Reset POL_SIZE bits */ - tmpcr &= (uint32_t)~((uint32_t)CRC_CR_POLSIZE); - /* Set the polynomial size */ - tmpcr |= (uint32_t)CRC_PolSize; - - /* Write to CR register */ - CRC->CR = (uint32_t)tmpcr; -} - -/** - * @brief Selects the reverse operation to be performed on input data. - * @param CRC_ReverseInputData: Specifies the reverse operation on input data. - * This parameter can be: - * @arg CRC_ReverseInputData_No: No reverse operation is performed - * @arg CRC_ReverseInputData_8bits: reverse operation performed on 8 bits - * @arg CRC_ReverseInputData_16bits: reverse operation performed on 16 bits - * @arg CRC_ReverseInputData_32bits: reverse operation performed on 32 bits - * @retval None - */ -void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData) -{ - uint32_t tmpcr = 0; - - /* Check the parameter */ - assert_param(IS_CRC_REVERSE_INPUT_DATA(CRC_ReverseInputData)); - - /* Get CR register value */ - tmpcr = CRC->CR; - - /* Reset REV_IN bits */ - tmpcr &= (uint32_t)~((uint32_t)CRC_CR_REV_IN); - /* Set the reverse operation */ - tmpcr |= (uint32_t)CRC_ReverseInputData; - - /* Write to CR register */ - CRC->CR = (uint32_t)tmpcr; -} - -/** - * @brief Enables or disable the reverse operation on output data. - * The reverse operation on output data is performed on 32-bit. - * @param NewState: new state of the reverse operation on output data. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CRC_ReverseOutputDataCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable reverse operation on output data */ - CRC->CR |= CRC_CR_REV_OUT; - } - else - { - /* Disable reverse operation on output data */ - CRC->CR &= (uint32_t)~((uint32_t)CRC_CR_REV_OUT); - } -} - -/** - * @brief Initializes the INIT register. - * @note After resetting CRC calculation unit, CRC_InitValue is stored in DR register - * @param CRC_InitValue: Programmable initial CRC value - * @retval None - */ -void CRC_SetInitRegister(uint32_t CRC_InitValue) -{ - CRC->INIT = CRC_InitValue; -} - -/** - * @brief Initializes the polynomail coefficients. This function is only - * applicable for STM32F072 devices. - * @param CRC_Pol: Polynomial to be used for CRC calculation. - * @retval None - */ -void CRC_SetPolynomial(uint32_t CRC_Pol) -{ - CRC->POL = CRC_Pol; -} - -/** - * @} - */ - -/** @defgroup CRC_Group2 CRC computation of one/many 32-bit data functions - * @brief CRC computation of one/many 32-bit data functions - * -@verbatim - =============================================================================== - ##### CRC computation functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Computes the 32-bit CRC of a given data word(32-bit). - * @param CRC_Data: data word(32-bit) to compute its CRC - * @retval 32-bit CRC - */ -uint32_t CRC_CalcCRC(uint32_t CRC_Data) -{ - CRC->DR = CRC_Data; - - return (CRC->DR); -} - -/** - * @brief Computes the 16-bit CRC of a given 16-bit data. This function is only - * applicable for STM32F072 devices. - * @param CRC_Data: data half-word(16-bit) to compute its CRC - * @retval 16-bit CRC - */ -uint32_t CRC_CalcCRC16bits(uint16_t CRC_Data) -{ - *(uint16_t*)(CRC_BASE) = (uint16_t) CRC_Data; - - return (CRC->DR); -} - -/** - * @brief Computes the 8-bit CRC of a given 8-bit data. This function is only - * applicable for STM32F072 devices. - * @param CRC_Data: 8-bit data to compute its CRC - * @retval 8-bit CRC - */ -uint32_t CRC_CalcCRC8bits(uint8_t CRC_Data) -{ - *(uint8_t*)(CRC_BASE) = (uint8_t) CRC_Data; - - return (CRC->DR); -} - -/** - * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). - * @param pBuffer: pointer to the buffer containing the data to be computed - * @param BufferLength: length of the buffer to be computed - * @retval 32-bit CRC - */ -uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) -{ - uint32_t index = 0; - - for(index = 0; index < BufferLength; index++) - { - CRC->DR = pBuffer[index]; - } - return (CRC->DR); -} - -/** - * @brief Returns the current CRC value. - * @param None - * @retval 32-bit CRC - */ -uint32_t CRC_GetCRC(void) -{ - return (CRC->DR); -} - -/** - * @} - */ - -/** @defgroup CRC_Group3 CRC Independent Register (IDR) access functions - * @brief CRC Independent Register (IDR) access (write/read) functions - * -@verbatim - =============================================================================== - ##### CRC Independent Register (IDR) access functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Stores an 8-bit data in the Independent Data(ID) register. - * @param CRC_IDValue: 8-bit value to be stored in the ID register - * @retval None - */ -void CRC_SetIDRegister(uint8_t CRC_IDValue) -{ - CRC->IDR = CRC_IDValue; -} - -/** - * @brief Returns the 8-bit data stored in the Independent Data(ID) register - * @param None - * @retval 8-bit value of the ID register - */ -uint8_t CRC_GetIDRegister(void) -{ - return (CRC->IDR); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_crs.c b/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_crs.c deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_crs.c +++ /dev/null @@ -1,466 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_crs.c - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of CRS peripheral applicable only on STM32F042 and - * STM32F072 devices: - * + Configuration of the CRS peripheral - * + Interrupts and flags management - * - * - * @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - - (+) Enable CRS AHB clock using RCC_APB1eriphClockCmd(RCC_APB1Periph_CRS, ENABLE) - function - - - @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_crs.h" -#include "stm32f0xx_rcc.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup CRS - * @brief CRS driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* CRS Flag Mask */ -#define FLAG_MASK ((uint32_t)0x700) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup CRS_Private_Functions - * @{ - */ - -/** @defgroup CRS_Group1 Configuration of the CRS functions - * @brief Configuration of the CRS functions - * -@verbatim - =============================================================================== - ##### CRS configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes CRS peripheral registers to their default reset values. - * @param None - * @retval None - */ -void CRS_DeInit(void) -{ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CRS, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CRS, DISABLE); -} - -/** - * @brief Adjusts the Internal High Speed 48 oscillator (HSI 48) calibration value. - * @note The calibration is used to compensate for the variations in voltage - * and temperature that influence the frequency of the internal HSI48 RC. - * @note This function can be called only when the AUTOTRIMEN bit is reset. - * @param CRS_HSI48CalibrationValue: - * @retval None - */ -void CRS_AdjustHSI48CalibrationValue(uint8_t CRS_HSI48CalibrationValue) -{ - /* Clear TRIM[5:0] bits */ - CRS->CR &= ~CRS_CR_TRIM; - - /* Set the TRIM[5:0] bits according to CRS_HSI48CalibrationValue value */ - CRS->CR |= (uint32_t)((uint32_t)CRS_HSI48CalibrationValue << 8); - -} - -/** - * @brief Enables or disables the oscillator clock for frequency error counter. - * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. - * @param NewState: new state of the frequency error counter. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CRS_FrequencyErrorCounterCmd(FunctionalState NewState) -{ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - CRS->CR |= CRS_CR_CEN; - } - else - { - CRS->CR &= ~CRS_CR_CEN; - } -} - -/** - * @brief Enables or disables the automatic hardware adjustement of TRIM bits. - * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. - * @param NewState: new state of the automatic trimming. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CRS_AutomaticCalibrationCmd(FunctionalState NewState) -{ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - CRS->CR |= CRS_CR_AUTOTRIMEN; - } -else - { - CRS->CR &= ~CRS_CR_AUTOTRIMEN; - } -} - -/** - * @brief Generate the software synchronization event - * @param None - * @retval None - */ -void CRS_SoftwareSynchronizationGenerate(void) -{ - CRS->CR |= CRS_CR_SWSYNC; -} - -/** - * @brief Adjusts the Internal High Speed 48 oscillator (HSI 48) calibration value. - * @note The calibration is used to compensate for the variations in voltage - * and temperature that influence the frequency of the internal HSI48 RC. - * @note This function can be called only when the CEN bit is reset. - * @param CRS_ReloadValue: specifies the HSI calibration trimming value. - * This parameter must be a number between 0 and . - * @retval None - */ -void CRS_FrequencyErrorCounterReload(uint32_t CRS_ReloadValue) -{ - - /* Clear RELOAD[15:0] bits */ - CRS->CFGR &= ~CRS_CFGR_RELOAD; - - /* Set the RELOAD[15:0] bits according to CRS_ReloadValue value */ - CRS->CFGR |= (uint32_t)CRS_ReloadValue; - -} - -/** - * @brief - * @note This function can be called only when the CEN bit is reset. - * @param CRS_ErrorLimitValue: specifies the HSI calibration trimming value. - * This parameter must be a number between 0 and . - * @retval None - */ -void CRS_FrequencyErrorLimitConfig(uint8_t CRS_ErrorLimitValue) -{ - /* Clear FELIM[7:0] bits */ - CRS->CFGR &= ~CRS_CFGR_FELIM; - - /* Set the FELIM[7:0] bits according to CRS_ErrorLimitValue value */ - CRS->CFGR |= (uint32_t)CRS_ErrorLimitValue; -} - -/** - * @brief - * @note This function can be called only when the CEN bit is reset. - * @param CRS_Prescaler: specifies the HSI calibration trimming value. - * This parameter can be one of the following values: - * @arg CRS_SYNC_Div1: - * @arg CRS_SYNC_Div2: - * @arg CRS_SYNC_Div4: - * @arg CRS_SYNC_Div8: - * @arg CRS_SYNC_Div16: - * @arg CRS_SYNC_Div32: - * @arg CRS_SYNC_Div64: - * @arg CRS_SYNC_Div128: - * @retval None - */ -void CRS_SynchronizationPrescalerConfig(uint32_t CRS_Prescaler) -{ - /* Check the parameters */ - assert_param(IS_CRS_SYNC_DIV(CRS_Prescaler)); - - /* Clear SYNCDIV[2:0] bits */ - CRS->CFGR &= ~CRS_CFGR_SYNCDIV; - - /* Set the CRS_CFGR_SYNCDIV[2:0] bits according to CRS_Prescaler value */ - CRS->CFGR |= CRS_Prescaler; -} - -/** - * @brief - * @note This function can be called only when the CEN bit is reset. - * @param CRS_Source: . - * This parameter can be one of the following values: - * @arg CRS_SYNCSource_GPIO: - * @arg CRS_SYNCSource_LSE: - * @arg CRS_SYNCSource_USB: - * @retval None - */ -void CRS_SynchronizationSourceConfig(uint32_t CRS_Source) -{ - /* Check the parameters */ - assert_param(IS_CRS_SYNC_SOURCE(CRS_Source)); - - /* Clear SYNCSRC[1:0] bits */ - CRS->CFGR &= ~CRS_CFGR_SYNCSRC; - - /* Set the SYNCSRC[1:0] bits according to CRS_Source value */ - CRS->CFGR |= CRS_Source; -} - -/** - * @brief - * @note This function can be called only when the CEN bit is reset. - * @param CRS_Polarity: . - * This parameter can be one of the following values: - * @arg CRS_SYNCPolarity_Rising: - * @arg CRS_SYNCPolarity_Falling: - * @retval None - */ -void CRS_SynchronizationPolarityConfig(uint32_t CRS_Polarity) -{ - /* Check the parameters */ - assert_param(IS_CRS_SYNC_POLARITY(CRS_Polarity)); - - /* Clear SYNCSPOL bit */ - CRS->CFGR &= ~CRS_CFGR_SYNCPOL; - - /* Set the SYNCSPOL bits according to CRS_Polarity value */ - CRS->CFGR |= CRS_Polarity; -} - -/** - * @brief Returns the Relaod value. - * @param None - * @retval The reload value - */ -uint32_t CRS_GetReloadValue(void) -{ - return ((uint32_t)(CRS->CFGR & CRS_CFGR_RELOAD)); -} - -/** - * @brief Returns the HSI48 Calibration value. - * @param None - * @retval The reload value - */ -uint32_t CRS_GetHSI48CalibrationValue(void) -{ - return (((uint32_t)(CRS->CR & CRS_CR_TRIM)) >> 8); -} - -/** - * @brief Returns the frequency error capture. - * @param None - * @retval The frequency error capture value - */ -uint32_t CRS_GetFrequencyErrorValue(void) -{ - return ((uint32_t)(CRS->ISR & CRS_ISR_FECAP)); -} - -/** - * @brief Returns the frequency error direction. - * @param None - * @retval The frequency error direction. The returned value can be one - * of the following values: - * - 0x00: Up counting - * - 0x8000: Down counting - */ -uint32_t CRS_GetFrequencyErrorDirection(void) -{ - return ((uint32_t)(CRS->ISR & CRS_ISR_FEDIR)); -} - -/** @defgroup CRS_Group2 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== -@endverbatim - * @{ - */ -/** - * @brief Enables or disables the specified CRS interrupts. - * @param CRS_IT: specifies the RCC interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg CRS_IT_SYNCOK: - * @arg CRS_IT_SYNCWARN: - * @arg CRS_IT_ERR: - * @arg CRS_IT_ESYNC: - * @param NewState: new state of the specified CRS interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CRS_ITConfig(uint32_t CRS_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CRS_IT(CRS_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - CRS->CR |= CRS_IT; - } - else - { - CRS->CR &= ~CRS_IT; - } -} - -/** - * @brief Checks whether the specified CRS flag is set or not. - * @param CRS_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg CRS_FLAG_SYNCOK: - * @arg CRS_FLAG_SYNCWARN: - * @arg CRS_FLAG_ERR: - * @arg CRS_FLAG_ESYNC: - * @arg CRS_FLAG_TRIMOVF: - * @arg CRS_FLAG_SYNCERR: - * @arg CRS_FLAG_SYNCMISS: - * @retval The new state of CRS_FLAG (SET or RESET). - */ -FlagStatus CRS_GetFlagStatus(uint32_t CRS_FLAG) -{ - /* Check the parameters */ - assert_param(IS_CRS_FLAG(CRS_FLAG)); - - return ((FlagStatus)(CRS->ISR & CRS_FLAG)); -} - -/** - * @brief Clears the CRS specified FLAG. - * @param CRS_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg CRS_FLAG_SYNCOK: - * @arg CRS_FLAG_SYNCWARN: - * @arg CRS_FLAG_ERR: - * @arg CRS_FLAG_ESYNC: - * @arg CRS_FLAG_TRIMOVF: - * @arg CRS_FLAG_SYNCERR: - * @arg CRS_FLAG_SYNCMISS: - * @retval None - */ -void CRS_ClearFlag(uint32_t CRS_FLAG) -{ - /* Check the parameters */ - assert_param(IS_CRS_FLAG(CRS_FLAG)); - - if ((CRS_FLAG & FLAG_MASK)!= 0) - { - CRS->ICR |= CRS_ICR_ERRC; - } - else - { - CRS->ICR |= CRS_FLAG; - } -} - -/** - * @brief Checks whether the specified CRS IT pending bit is set or not. - * @param CRS_IT: specifies the IT pending bit to check. - * This parameter can be one of the following values: - * @arg CRS_IT_SYNCOK: - * @arg CRS_IT_SYNCWARN: - * @arg CRS_IT_ERR: - * @arg CRS_IT_ESYNC: - * @arg CRS_IT_TRIMOVF: - * @arg CRS_IT_SYNCERR: - * @arg CRS_IT_SYNCMISS: - * @retval The new state of CRS_IT (SET or RESET). - */ -ITStatus CRS_GetITStatus(uint32_t CRS_IT) -{ - /* Check the parameters */ - assert_param(IS_CRS_GET_IT(CRS_IT)); - - return ((ITStatus)(CRS->ISR & CRS_IT)); -} - -/** - * @brief Clears the CRS specified IT pending bi. - * @param CRS_FLAG: specifies the IT pending bi to clear. - * This parameter can be one of the following values: - * @arg CRS_IT_SYNCOK: - * @arg CRS_IT_SYNCWARN: - * @arg CRS_IT_ERR: - * @arg CRS_IT_ESYNC: - * @arg CRS_IT_TRIMOVF: - * @arg CRS_IT_SYNCERR: - * @arg CRS_IT_SYNCMISS: - * @retval None - */ -void CRS_ClearITPendingBit(uint32_t CRS_IT) -{ - /* Check the parameters */ - assert_param(IS_CRS_CLEAR_IT(CRS_IT)); - - if ((CRS_IT & FLAG_MASK)!= 0) - { - CRS->ICR |= CRS_ICR_ERRC; - } - else - { - CRS->ICR |= CRS_IT; - } -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_dac.c b/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_dac.c deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_dac.c +++ /dev/null @@ -1,692 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_dac.c - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the Digital-to-Analog Converter (DAC) peripheral - * applicable only on STM32F051 and STM32F072 devices: - * + DAC channel configuration: trigger, output buffer, data format - * + DMA management - * + Interrupts and flags management - * - * @verbatim - * - =============================================================================== - ##### DAC Peripheral features ##### - =============================================================================== - [..] The device integrates two 12-bit Digital Analog Converters refered as - DAC channel1 with DAC_OUT1 (PA4) and DAC_OUT2 (PA5) as outputs. - - [..] Digital to Analog conversion can be non-triggered using DAC_Trigger_None - and DAC_OUTx is available once writing to DHRx register using - DAC_SetChannel1Data() or DAC_SetChannel2Data() - - [..] Digital to Analog conversion can be triggered by: - (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9. - The used pin (GPIOx_Pin9) must be configured in input mode. - - (#) Timers TRGO: TIM2, TIM3,TIM7, TIM6 and TIM15 - (DAC_Trigger_T2_TRGO, DAC_Trigger_T3_TRGO...) - The timer TRGO event should be selected using TIM_SelectOutputTrigger() - - (#) Software using DAC_Trigger_Software - - [..] Each DAC integrates an output buffer that can be used to - reduce the output impedance, and to drive external loads directly - without having to add an external operational amplifier. - To enable the output buffer use - DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable; - - [..] Refer to the device datasheet for more details about output impedance - value with and without output buffer. - - [..] DAC wave generation feature - Both DAC channels can be used to generate - 1- Noise wave using DAC_WaveGeneration_Noise - 2- Triangle wave using DAC_WaveGeneration_Triangle - - [..] The DAC data format can be: - (#) 8-bit right alignment using DAC_Align_8b_R - (#) 12-bit left alignment using DAC_Align_12b_L - (#) 12-bit right alignment using DAC_Align_12b_R - - [..] The analog output voltage on each DAC channel pin is determined - by the following equation: DAC_OUTx = VREF+ * DOR / 4095 - with DOR is the Data Output Register - VEF+ is the input voltage reference (refer to the device datasheet) - e.g. To set DAC_OUT1 to 0.7V, use - DAC_SetChannel1Data(DAC_Align_12b_R, 868); - Assuming that VREF+ = 3.3, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V - - [..] A DMA1 request can be generated when an external trigger (but not - a software trigger) occurs if DMA1 requests are enabled using - DAC_DMACmd() - DMA1 requests are mapped as following: - (+) DAC channel1 is mapped on DMA1 channel3 which must be already - configured - (+) DAC channel2 is mapped on DMA1 channel4 which must be already - configured - - ##### How to use this driver ##### - =============================================================================== - [..] - (+) Enable DAC APB1 clock to get write access to DAC registers - using RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE) - - (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode - using GPIO_Init() function - - (+) Configure the DAC channel using DAC_Init() - - (+) Enable the DAC channel using DAC_Cmd() - - @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_dac.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup DAC - * @brief DAC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* CR register Mask */ -#define CR_CLEAR_MASK ((uint32_t)0x00000FFE) /* check the value of the mask */ - -/* DAC Dual Channels SWTRIG masks */ -#define DUAL_SWTRIG_SET ((uint32_t)0x00000003) /*!< Only applicable for STM32F072 devices */ -#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC) /*!< Only applicable for STM32F072 devices */ - -/* DHR registers offsets */ -#define DHR12R1_OFFSET ((uint32_t)0x00000008) -#define DHR12R2_OFFSET ((uint32_t)0x00000014) /*!< Only applicable for STM32F072 devices */ -#define DHR12RD_OFFSET ((uint32_t)0x00000020) /*!< Only applicable for STM32F072 devices */ - -/* DOR register offset */ -#define DOR_OFFSET ((uint32_t)0x0000002C) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup DAC_Private_Functions - * @{ - */ - -/** @defgroup DAC_Group1 DAC channels configuration - * @brief DAC channels configuration: trigger, output buffer, data format - * -@verbatim - =============================================================================== - ##### DAC channels configuration: trigger, output buffer, data format ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the DAC peripheral registers to their default reset values. - * @param None - * @retval None - */ -void DAC_DeInit(void) -{ - /* Enable DAC reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE); - /* Release DAC from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE); -} - -/** - * @brief Initializes the DAC peripheral according to the specified parameters - * in the DAC_InitStruct. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices - * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that contains - * the configuration information for the specified DAC channel. - * @retval None - */ -void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0; - - /* Check the DAC parameters */ - assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger)); - assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration)); - assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude)); - assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer)); - -/*---------------------------- DAC CR Configuration --------------------------*/ - /* Get the DAC CR value */ - tmpreg1 = DAC->CR; - /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ - tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel); - /* Configure for the selected DAC channel: buffer output, trigger, - wave generation, mask/amplitude for wave generation */ - /* Set TSELx and TENx bits according to DAC_Trigger value */ - /* Set WAVEx bits according to DAC_WaveGeneration value */ - /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ - /* Set BOFFx bit according to DAC_OutputBuffer value */ - tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration | - DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | \ - DAC_InitStruct->DAC_OutputBuffer); - /* Calculate CR register value depending on DAC_Channel */ - tmpreg1 |= tmpreg2 << DAC_Channel; - /* Write to DAC CR */ - DAC->CR = tmpreg1; -} - -/** - * @brief Fills each DAC_InitStruct member with its default value. - * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct) -{ -/*--------------- Reset DAC init structure parameters values -----------------*/ - /* Initialize the DAC_Trigger member */ - DAC_InitStruct->DAC_Trigger = DAC_Trigger_None; - - /* Initialize the DAC_WaveGeneration member */ - DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None; - - /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */ - DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; - - /* Initialize the DAC_OutputBuffer member */ - DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable; -} - -/** - * @brief Enables or disables the specified DAC channel. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices - * @param NewState: new state of the DAC channel. - * This parameter can be: ENABLE or DISABLE. - * @note When the DAC channel is enabled the trigger source can no more be modified. - * @retval None - */ -void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected DAC channel */ - DAC->CR |= (DAC_CR_EN1 << DAC_Channel); - } - else - { - /* Disable the selected DAC channel */ - DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel)); - } -} - -/** - * @brief Enables or disables the selected DAC channel software trigger. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices - * @param NewState: new state of the selected DAC channel software trigger. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable software trigger for the selected DAC channel */ - DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4); - } - else - { - /* Disable software trigger for the selected DAC channel */ - DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4)); - } -} - -/** - * @brief Enables or disables simultaneously the two DAC channels software triggers. - * This function is applicable only for STM32F072 devices. - * @param NewState: new state of the DAC channels software triggers. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_DualSoftwareTriggerCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable software trigger for both DAC channels */ - DAC->SWTRIGR |= DUAL_SWTRIG_SET; - } - else - { - /* Disable software trigger for both DAC channels */ - DAC->SWTRIGR &= DUAL_SWTRIG_RESET; - } -} - -/** - * @brief Enables or disables the selected DAC channel wave generation. - * This function is applicable only for STM32F072 devices. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_Wave: specifies the wave type to enable or disable. - * This parameter can be: - * @arg DAC_Wave_Noise: noise wave generation - * @arg DAC_Wave_Triangle: triangle wave generation - * @param NewState: new state of the selected DAC channel wave generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_WAVE(DAC_Wave)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected wave generation for the selected DAC channel */ - DAC->CR |= DAC_Wave << DAC_Channel; - } - else - { - /* Disable the selected wave generation for the selected DAC channel */ - DAC->CR &= ~(DAC_Wave << DAC_Channel); - } -} - -/** - * @brief Set the specified data holding register value for DAC channel1. - * @param DAC_Align: Specifies the data alignment for DAC channel1. - * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignment selected - * @arg DAC_Align_12b_L: 12bit left data alignment selected - * @arg DAC_Align_12b_R: 12bit right data alignment selected - * @param Data: Data to be loaded in the selected data holding register. - * @retval None - */ -void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data)); - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12R1_OFFSET + DAC_Align; - - /* Set the DAC channel1 selected data holding register */ - *(__IO uint32_t *) tmp = Data; -} - -/** - * @brief Sets the specified data holding register value for DAC channel2. - * This function is applicable only for STM32F072 devices. - * @param DAC_Align: Specifies the data alignment for DAC channel2. - * This parameter can be: - * @arg DAC_Align_8b_R: 8bit right data alignment selected - * @arg DAC_Align_12b_L: 12bit left data alignment selected - * @arg DAC_Align_12b_R: 12bit right data alignment selected - * @param Data: Data to be loaded in the selected data holding register. - * @retval None - */ -void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data)); - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12R2_OFFSET + DAC_Align; - - /* Set the DAC channel2 selected data holding register */ - *(__IO uint32_t *)tmp = Data; -} - -/** - * @brief Sets the specified data holding register value for dual channel DAC. - * This function is applicable only for STM32F072 devices. - * @param DAC_Align: Specifies the data alignment for dual channel DAC. - * This parameter can be: - * @arg DAC_Align_8b_R: 8bit right data alignment selected - * @arg DAC_Align_12b_L: 12bit left data alignment selected - * @arg DAC_Align_12b_R: 12bit right data alignment selected - * @param Data2: Data for DAC Channel2 to be loaded in the selected data holding register. - * @param Data1: Data for DAC Channel1 to be loaded in the selected data holding register. - * @note In dual mode, a unique register access is required to write in both - * DAC channels at the same time. - * @retval None - */ -void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1) -{ - uint32_t data = 0, tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data1)); - assert_param(IS_DAC_DATA(Data2)); - - /* Calculate and set dual DAC data holding register value */ - if (DAC_Align == DAC_Align_8b_R) - { - data = ((uint32_t)Data2 << 8) | Data1; - } - else - { - data = ((uint32_t)Data2 << 16) | Data1; - } - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12RD_OFFSET + DAC_Align; - - /* Set the dual DAC selected data holding register */ - *(__IO uint32_t *)tmp = data; -} - -/** - * @brief Returns the last data output value of the selected DAC channel. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices - * @retval The selected DAC channel data output value. - */ -uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - - tmp = (uint32_t) DAC_BASE ; - tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2); - - /* Returns the DAC channel data output register value */ - return (uint16_t) (*(__IO uint32_t*) tmp); -} - -/** - * @} - */ - -/** @defgroup DAC_Group2 DMA management functions - * @brief DMA management functions - * -@verbatim - =============================================================================== - ##### DMA management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified DAC channel DMA request. - * When enabled DMA1 is generated when an external trigger (EXTI Line9, - * TIM2, TIM3, TIM6 or TIM15 but not a software trigger) occurs - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices - * @param NewState: new state of the selected DAC channel DMA request. - * This parameter can be: ENABLE or DISABLE. - * @note The DAC channel1 is mapped on DMA1 channel3 which must be already configured. - * @note The DAC channel2 is mapped on DMA1 channel4 which must be already configured. - * @retval None - */ -void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected DAC channel DMA request */ - DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel); - } - else - { - /* Disable the selected DAC channel DMA request */ - DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel)); - } -} - -/** - * @} - */ - -/** @defgroup DAC_Group3 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified DAC interrupts. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices - * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. - * This parameter can be the following values: - * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask - * @note The DMA underrun occurs when a second external trigger arrives before the - * acknowledgement for the first external trigger is received (first request). - * @param NewState: new state of the specified DAC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_DAC_IT(DAC_IT)); - - if (NewState != DISABLE) - { - /* Enable the selected DAC interrupts */ - DAC->CR |= (DAC_IT << DAC_Channel); - } - else - { - /* Disable the selected DAC interrupts */ - DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel)); - } -} - -/** - * @brief Checks whether the specified DAC flag is set or not. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices - * @param DAC_FLAG: specifies the flag to check. - * This parameter can be only of the following value: - * @arg DAC_FLAG_DMAUDR: DMA underrun flag - * @note The DMA underrun occurs when a second external trigger arrives before the - * acknowledgement for the first external trigger is received (first request). - * @retval The new state of DAC_FLAG (SET or RESET). - */ -FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_FLAG(DAC_FLAG)); - - /* Check the status of the specified DAC flag */ - if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET) - { - /* DAC_FLAG is set */ - bitstatus = SET; - } - else - { - /* DAC_FLAG is reset */ - bitstatus = RESET; - } - /* Return the DAC_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the DAC channel's pending flags. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices - * @param DAC_FLAG: specifies the flag to clear. - * This parameter can be of the following value: - * @arg DAC_FLAG_DMAUDR: DMA underrun flag - * @retval None - */ -void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_FLAG(DAC_FLAG)); - - /* Clear the selected DAC flags */ - DAC->SR = (DAC_FLAG << DAC_Channel); -} - -/** - * @brief Checks whether the specified DAC interrupt has occurred or not. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices - * @param DAC_IT: specifies the DAC interrupt source to check. - * This parameter can be the following values: - * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask - * @note The DMA underrun occurs when a second external trigger arrives before the - * acknowledgement for the first external trigger is received (first request). - * @retval The new state of DAC_IT (SET or RESET). - */ -ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_IT(DAC_IT)); - - /* Get the DAC_IT enable bit status */ - enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ; - - /* Check the status of the specified DAC interrupt */ - if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus) - { - /* DAC_IT is set */ - bitstatus = SET; - } - else - { - /* DAC_IT is reset */ - bitstatus = RESET; - } - /* Return the DAC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the DAC channel's interrupt pending bits. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices - * @param DAC_IT: specifies the DAC interrupt pending bit to clear. - * This parameter can be the following values: - * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask - * @retval None - */ -void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_IT(DAC_IT)); - - /* Clear the selected DAC interrupt pending bits */ - DAC->SR = (DAC_IT << DAC_Channel); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_dbgmcu.c b/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_dbgmcu.c deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_dbgmcu.c +++ /dev/null @@ -1,218 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_dbgmcu.c - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the Debug MCU (DBGMCU) peripheral: - * + Device and Revision ID management - * + Peripherals Configuration - * @verbatim - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_dbgmcu.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup DBGMCU - * @brief DBGMCU driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup DBGMCU_Private_Functions - * @{ - */ - - -/** @defgroup DBGMCU_Group1 Device and Revision ID management functions - * @brief Device and Revision ID management functions - * -@verbatim - ============================================================================== - ##### Device and Revision ID management functions ##### - ============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Returns the device revision identifier. - * @param None - * @retval Device revision identifier - */ -uint32_t DBGMCU_GetREVID(void) -{ - return(DBGMCU->IDCODE >> 16); -} - -/** - * @brief Returns the device identifier. - * @param None - * @retval Device identifier - */ -uint32_t DBGMCU_GetDEVID(void) -{ - return(DBGMCU->IDCODE & IDCODE_DEVID_MASK); -} - -/** - * @} - */ - -/** @defgroup DBGMCU_Group2 Peripherals Configuration functions - * @brief Peripherals Configuration - * -@verbatim - ============================================================================== - ##### Peripherals Configuration functions ##### - ============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures low power mode behavior when the MCU is in Debug mode. - * @param DBGMCU_Periph: specifies the low power mode. - * This parameter can be any combination of the following values: - * @arg DBGMCU_STOP: Keep debugger connection during STOP mode - * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode - * @param NewState: new state of the specified low power mode in Debug mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - DBGMCU->CR |= DBGMCU_Periph; - } - else - { - DBGMCU->CR &= ~DBGMCU_Periph; - } -} - - -/** - * @brief Configures APB1 peripheral behavior when the MCU is in Debug mode. - * @param DBGMCU_Periph: specifies the APB1 peripheral. - * This parameter can be any combination of the following values: - * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted, - * not applicable for STM32F030 devices - * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted - * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted - * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted, - * applicable only for STM32F072 devices - * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted - * @arg DBGMCU_RTC_STOP: RTC Calendar and Wakeup counter stopped - * when Core is halted. - * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted - * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted - * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped - * when Core is halted - * @arg DBGMCU_CAN1_STOP: Debug CAN1 stopped when Core is halted, - * applicable only for STM32F042 and STM32F072 devices - * @param NewState: new state of the specified APB1 peripheral in Debug mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - DBGMCU->APB1FZ |= DBGMCU_Periph; - } - else - { - DBGMCU->APB1FZ &= ~DBGMCU_Periph; - } -} - -/** - * @brief Configures APB2 peripheral behavior when the MCU is in Debug mode. - * @param DBGMCU_Periph: specifies the APB2 peripheral. - * This parameter can be any combination of the following values: - * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted - * @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted - * @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted - * @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted - * @param NewState: new state of the specified APB2 peripheral in Debug mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - DBGMCU->APB2FZ |= DBGMCU_Periph; - } - else - { - DBGMCU->APB2FZ &= ~DBGMCU_Periph; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_dma.c b/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_dma.c deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_dma.c +++ /dev/null @@ -1,891 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_dma.c - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the Direct Memory Access controller (DMA): - * + Initialization and Configuration - * + Data Counter - * + Interrupts and flags management - * - * @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Enable The DMA controller clock using - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE) function for DMA1. - (#) Enable and configure the peripheral to be connected to the DMA channel - (except for internal SRAM / FLASH memories: no initialization is necessary). - (#) For a given Channel, program the Source and Destination addresses, - the transfer Direction, the Buffer Size, the Peripheral and Memory - Incrementation mode and Data Size, the Circular or Normal mode, - the channel transfer Priority and the Memory-to-Memory transfer - mode (if needed) using the DMA_Init() function. - (#) Enable the NVIC and the corresponding interrupt(s) using the function - DMA_ITConfig() if you need to use DMA interrupts. - (#) Enable the DMA channel using the DMA_Cmd() function. - (#) Activate the needed channel Request using PPP_DMACmd() function for - any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...) - The function allowing this operation is provided in each PPP peripheral - driver (ie. SPI_DMACmd for SPI peripheral). - (#) Optionally, you can configure the number of data to be transferred - when the channel is disabled (ie. after each Transfer Complete event - or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter(). - And you can get the number of remaining data to be transferred using - the function DMA_GetCurrDataCounter() at run time (when the DMA channel is - enabled and running). - (#) To control DMA events you can use one of the following two methods: - (##) Check on DMA channel flags using the function DMA_GetFlagStatus(). - (##) Use DMA interrupts through the function DMA_ITConfig() at initialization - phase and DMA_GetITStatus() function into interrupt routines in - communication phase. - After checking on a flag you should clear it using DMA_ClearFlag() - function. And after checking on an interrupt event you should - clear it using DMA_ClearITPendingBit() function. - @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_dma.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup DMA - * @brief DMA driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define CCR_CLEAR_MASK ((uint32_t)0xFFFF800F) /* DMA Channel config registers Masks */ -#define FLAG_Mask ((uint32_t)0x10000000) /* DMA2 FLAG mask */ - -/* DMA1 Channelx interrupt pending bit masks */ -#define DMA1_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1)) -#define DMA1_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2)) -#define DMA1_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3)) -#define DMA1_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4)) -#define DMA1_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5)) -#define DMA1_CHANNEL6_IT_MASK ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6)) /*!< Only applicable for STM32F072 and STM32F091 devices */ -#define DMA1_CHANNEL7_IT_MASK ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7)) /*!< Only applicable for STM32F072 and STM32F091 devices */ - -/* DMA2 Channelx interrupt pending bit masks: Only applicable for STM32F091 devices */ -#define DMA2_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1)) -#define DMA2_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2)) -#define DMA2_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3)) -#define DMA2_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4)) -#define DMA2_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5)) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup DMA_Private_Functions - * @{ - */ - -/** @defgroup DMA_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] This subsection provides functions allowing to initialize the DMA channel - source and destination addresses, incrementation and data sizes, transfer - direction, buffer size, circular/normal mode selection, memory-to-memory - mode selection and channel priority value. - [..] The DMA_Init() function follows the DMA configuration procedures as described - in reference manual (RM0091). -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the DMAy Channelx registers to their default reset - * values. - * @param DMAy_Channelx: where y can be 1 to select the DMA and - * x can be 1 to 7 for DMA1 to select the DMA Channel. - * @note Channel 6 and 7 are available only for STM32F072 devices. - * @retval None - */ -void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - - /* Disable the selected DMAy Channelx */ - DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN); - - /* Reset DMAy Channelx control register */ - DMAy_Channelx->CCR = 0; - - /* Reset DMAy Channelx remaining bytes register */ - DMAy_Channelx->CNDTR = 0; - - /* Reset DMAy Channelx peripheral address register */ - DMAy_Channelx->CPAR = 0; - - /* Reset DMAy Channelx memory address register */ - DMAy_Channelx->CMAR = 0; - - if (DMAy_Channelx == DMA1_Channel1) - { - /* Reset interrupt pending bits for DMA1 Channel1 */ - DMA1->IFCR |= DMA1_CHANNEL1_IT_MASK; - } - else if (DMAy_Channelx == DMA1_Channel2) - { - /* Reset interrupt pending bits for DMA1 Channel2 */ - DMA1->IFCR |= DMA1_CHANNEL2_IT_MASK; - } - else if (DMAy_Channelx == DMA1_Channel3) - { - /* Reset interrupt pending bits for DMA1 Channel3 */ - DMA1->IFCR |= DMA1_CHANNEL3_IT_MASK; - } - else if (DMAy_Channelx == DMA1_Channel4) - { - /* Reset interrupt pending bits for DMA1 Channel4 */ - DMA1->IFCR |= DMA1_CHANNEL4_IT_MASK; - } - else if (DMAy_Channelx == DMA1_Channel5) - { - /* Reset interrupt pending bits for DMA1 Channel5 */ - DMA1->IFCR |= DMA1_CHANNEL5_IT_MASK; - } - else if (DMAy_Channelx == DMA1_Channel6) - { - /* Reset interrupt pending bits for DMA1 Channel6 */ - DMA1->IFCR |= DMA1_CHANNEL6_IT_MASK; - } - else if (DMAy_Channelx == DMA1_Channel7) - { - /* Reset interrupt pending bits for DMA1 Channel7 */ - DMA1->IFCR |= DMA1_CHANNEL7_IT_MASK; - } - else if (DMAy_Channelx == DMA2_Channel1) - { - /* Reset interrupt pending bits for DMA2 Channel1 */ - DMA2->IFCR |= DMA2_CHANNEL1_IT_MASK; - } - else if (DMAy_Channelx == DMA2_Channel2) - { - /* Reset interrupt pending bits for DMA2 Channel2 */ - DMA2->IFCR |= DMA2_CHANNEL2_IT_MASK; - } - else if (DMAy_Channelx == DMA2_Channel3) - { - /* Reset interrupt pending bits for DMA2 Channel3 */ - DMA2->IFCR |= DMA2_CHANNEL3_IT_MASK; - } - else if (DMAy_Channelx == DMA2_Channel4) - { - /* Reset interrupt pending bits for DMA2 Channel4 */ - DMA2->IFCR |= DMA2_CHANNEL4_IT_MASK; - } - else - { - if (DMAy_Channelx == DMA2_Channel5) - { - /* Reset interrupt pending bits for DMA2 Channel5 */ - DMA2->IFCR |= DMA2_CHANNEL5_IT_MASK; - } - } -} - -/** - * @brief Initializes the DMAy Channelx according to the specified parameters - * in the DMA_InitStruct. - * @param DMAy_Channelx: where y can be 1 to select the DMA and x can be 1 to 7 - * for DMA1 to select the DMA Channel and 1 to 5 for DMA2 to select the DMA Channel. - * @note DMA1 Channel 6 and 7 are available only for STM32F072 and STM32F091 devices. - * @note DMA2 Channel 1 to 5 are available only for STM32F091 devices. - * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval None - */ -void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR)); - assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize)); - assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); - assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); - assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize)); - assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize)); - assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); - assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); - assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M)); - -/*--------------------------- DMAy Channelx CCR Configuration ----------------*/ - /* Get the DMAy_Channelx CCR value */ - tmpreg = DMAy_Channelx->CCR; - - /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ - tmpreg &= CCR_CLEAR_MASK; - - /* Configure DMAy Channelx: data transfer, data size, priority level and mode */ - /* Set DIR bit according to DMA_DIR value */ - /* Set CIRC bit according to DMA_Mode value */ - /* Set PINC bit according to DMA_PeripheralInc value */ - /* Set MINC bit according to DMA_MemoryInc value */ - /* Set PSIZE bits according to DMA_PeripheralDataSize value */ - /* Set MSIZE bits according to DMA_MemoryDataSize value */ - /* Set PL bits according to DMA_Priority value */ - /* Set the MEM2MEM bit according to DMA_M2M value */ - tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | - DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | - DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | - DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; - - /* Write to DMAy Channelx CCR */ - DMAy_Channelx->CCR = tmpreg; - -/*--------------------------- DMAy Channelx CNDTR Configuration --------------*/ - /* Write to DMAy Channelx CNDTR */ - DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize; - -/*--------------------------- DMAy Channelx CPAR Configuration ---------------*/ - /* Write to DMAy Channelx CPAR */ - DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr; - -/*--------------------------- DMAy Channelx CMAR Configuration ---------------*/ - /* Write to DMAy Channelx CMAR */ - DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr; -} - -/** - * @brief Fills each DMA_InitStruct member with its default value. - * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) -{ -/*-------------- Reset DMA init structure parameters values ------------------*/ - /* Initialize the DMA_PeripheralBaseAddr member */ - DMA_InitStruct->DMA_PeripheralBaseAddr = 0; - /* Initialize the DMA_MemoryBaseAddr member */ - DMA_InitStruct->DMA_MemoryBaseAddr = 0; - /* Initialize the DMA_DIR member */ - DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; - /* Initialize the DMA_BufferSize member */ - DMA_InitStruct->DMA_BufferSize = 0; - /* Initialize the DMA_PeripheralInc member */ - DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; - /* Initialize the DMA_MemoryInc member */ - DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; - /* Initialize the DMA_PeripheralDataSize member */ - DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; - /* Initialize the DMA_MemoryDataSize member */ - DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; - /* Initialize the DMA_Mode member */ - DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; - /* Initialize the DMA_Priority member */ - DMA_InitStruct->DMA_Priority = DMA_Priority_Low; - /* Initialize the DMA_M2M member */ - DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; -} - -/** - * @brief Enables or disables the specified DMAy Channelx. - * @param DMAy_Channelx: where y can be 1 to select the DMA and x can be 1 to 7 - * for DMA1 to select the DMA Channel and 1 to 5 for DMA2 to select the DMA Channel. - * @note DMA1 Channel 6 and 7 are available only for STM32F072 and STM32F091 devices. - * @note DMA2 Channel 1 to 5 are available only for STM32F091 devices. - * @param NewState: new state of the DMAy Channelx. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected DMAy Channelx */ - DMAy_Channelx->CCR |= DMA_CCR_EN; - } - else - { - /* Disable the selected DMAy Channelx */ - DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN); - } -} - -/** - * @brief Configure the DMAx channels remapping. - * @param DMAy: where x can be 1 or 2 to select the DMA peripheral. - * @param DMAy_CHx_RemapRequest: where y can be 1 or 2 to select the DMA and x can be 1 to 7 - * for DMA1 to select the DMA1 Channel and can be 1 to 5 for DMA2 to select the DMA2 Channel. - * @note This function is available only for STM32F091 devices. - * @retval None - */ -void DMA_RemapConfig(DMA_TypeDef* DMAy, uint32_t DMAx_CHy_RemapRequest) -{ - assert_param(IS_DMA_ALL_LIST(DMAy)); - - if (DMAy == DMA1) - { - assert_param(IS_DMA1_REMAP(DMAx_CHy_RemapRequest)); - } - else - { - assert_param(IS_DMA2_REMAP(DMAx_CHy_RemapRequest)); - } - - DMAy->RMPCR &= ~((uint32_t)0x0F << (uint32_t)((DMAx_CHy_RemapRequest >> 28) * 4)); - DMAy->RMPCR |= (uint32_t)(DMAx_CHy_RemapRequest & 0x0FFFFFFF); -} - -/** - * @} - */ - -/** @defgroup DMA_Group2 Data Counter functions - * @brief Data Counter functions - * -@verbatim - =============================================================================== - ##### Data Counter functions ##### - =============================================================================== - [..] This subsection provides function allowing to configure and read the buffer - size (number of data to be transferred).The DMA data counter can be written - only when the DMA channel is disabled (ie. after transfer complete event). - [..] The following function can be used to write the Channel data counter value: - (+) void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t - DataNumber). - -@- It is advised to use this function rather than DMA_Init() in situations - where only the Data buffer needs to be reloaded. - [..] The DMA data counter can be read to indicate the number of remaining transfers - for the relative DMA channel. This counter is decremented at the end of each - data transfer and when the transfer is complete: - (+) If Normal mode is selected: the counter is set to 0. - (+) If Circular mode is selected: the counter is reloaded with the initial - value(configured before enabling the DMA channel). - [..] The following function can be used to read the Channel data counter value: - (+) uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx). - -@endverbatim - * @{ - */ - -/** - * @brief Sets the number of data units in the current DMAy Channelx transfer. - * @param DMAy_Channelx: where y can be 1 to select the DMA and x can be 1 to 7 - * for DMA1 to select the DMA Channel and 1 to 5 for DMA2 to select the DMA Channel. - * @note DMA1 Channel 6 and 7 are available only for STM32F072 and STM32F091 devices. - * @note DMA2 Channel 1 to 5 are available only for STM32F091 devices. - * @param DataNumber: The number of data units in the current DMAy Channelx - * transfer. - * @note This function can only be used when the DMAy_Channelx is disabled. - * @retval None. - */ -void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - -/*--------------------------- DMAy Channelx CNDTR Configuration --------------*/ - /* Write to DMAy Channelx CNDTR */ - DMAy_Channelx->CNDTR = DataNumber; -} - -/** - * @brief Returns the number of remaining data units in the current - * DMAy Channelx transfer. - * @param DMAy_Channelx: where y can be 1 to select the DMA and x can be 1 to 7 - * for DMA1 to select the DMA Channel and 1 to 5 for DMA2 to select the DMA Channel. - * @note DMA1 Channel 6 and 7 are available only for STM32F072 and STM32F091 devices. - * @note DMA2 Channel 1 to 5 are available only for STM32F091 devices. - * @retval The number of remaining data units in the current DMAy Channelx - * transfer. - */ -uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - /* Return the number of remaining data units for DMAy Channelx */ - return ((uint16_t)(DMAy_Channelx->CNDTR)); -} - -/** - * @} - */ - -/** @defgroup DMA_Group3 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - [..] This subsection provides functions allowing to configure the DMA Interrupts - sources and check or clear the flags or pending bits status. - The user should identify which mode will be used in his application to manage - the DMA controller events: Polling mode or Interrupt mode. - *** Polling Mode *** - ==================== - [..] Each DMA channel can be managed through 4 event Flags:(y : DMA Controller - number x : DMA channel number ). - (#) DMAy_FLAG_TCx : to indicate that a Transfer Complete event occurred. - (#) DMAy_FLAG_HTx : to indicate that a Half-Transfer Complete event occurred. - (#) DMAy_FLAG_TEx : to indicate that a Transfer Error occurred. - (#) DMAy_FLAG_GLx : to indicate that at least one of the events described - above occurred. - -@- Clearing DMAy_FLAG_GLx results in clearing all other pending flags of the - same channel (DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx). - [..]In this Mode it is advised to use the following functions: - (+) FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG); - (+) void DMA_ClearFlag(uint32_t DMA_FLAG); - - *** Interrupt Mode *** - ====================== - [..] Each DMA channel can be managed through 4 Interrupts: - (+) Interrupt Source - (##) DMA_IT_TC: specifies the interrupt source for the Transfer Complete - event. - (##) DMA_IT_HT : specifies the interrupt source for the Half-transfer Complete - event. - (##) DMA_IT_TE : specifies the interrupt source for the transfer errors event. - (##) DMA_IT_GL : to indicate that at least one of the interrupts described - above occurred. - -@@- Clearing DMA_IT_GL interrupt results in clearing all other interrupts of - the same channel (DMA_IT_TCx, DMA_IT_HT and DMA_IT_TE). - [..]In this Mode it is advised to use the following functions: - (+) void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, - FunctionalState NewState); - (+) ITStatus DMA_GetITStatus(uint32_t DMA_IT); - (+) void DMA_ClearITPendingBit(uint32_t DMA_IT); - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified DMAy Channelx interrupts. - * @param DMAy_Channelx: where y can be 1 to select the DMA and x can be 1 to 7 - * for DMA1 to select the DMA Channel and 1 to 5 for DMA2 to select the DMA Channel. - * @note DMA1 Channel 6 and 7 are available only for STM32F072 and STM32F091 devices. - * @note DMA2 Channel 1 to 5 are available only for STM32F091 devices. - * @param DMA_IT: specifies the DMA interrupts sources to be enabled - * or disabled. - * This parameter can be any combination of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask - * @arg DMA_IT_HT: Half transfer interrupt mask - * @arg DMA_IT_TE: Transfer error interrupt mask - * @param NewState: new state of the specified DMA interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - assert_param(IS_DMA_CONFIG_IT(DMA_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected DMA interrupts */ - DMAy_Channelx->CCR |= DMA_IT; - } - else - { - /* Disable the selected DMA interrupts */ - DMAy_Channelx->CCR &= ~DMA_IT; - } -} - -/** - * @brief Checks whether the specified DMAy Channelx flag is set or not. - * @param DMA_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. - * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. - * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. - * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. - * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. - * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. - * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. - * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. - * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. - * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. - * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. - * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. - * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. - * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. - * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. - * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. - * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. - * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. - * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. - * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. - * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag, applicable only for STM32F072 and STM32FO91 devices. - * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag, applicable only for STM32F072 and STM32FO91 devices. - * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag, applicable only for STM32F072 and STM32FO91 devices. - * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag, applicable only for STM32F072 and STM32FO91 devices. - * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag, applicable only for STM32F072 and STM32FO91 devices. - * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag, applicable only for STM32F072 and STM32FO91 devices. - * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag, applicable only for STM32F072 and STM32FO91 devices. - * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag, applicable only for STM32F072 and STM32FO91 devices. - * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag, applicable only for STM32FO91 devices. - * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag, applicable only for STM32FO91 devices. - * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag, applicable only for STM32FO91 devices. - * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag, applicable only for STM32FO91 devices. - * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag, applicable only for STM32FO91 devices. - * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag, applicable only for STM32FO91 devices. - * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag, applicable only for STM32FO91 devices. - * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag, applicable only for STM32FO91 devices. - * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag, applicable only for STM32FO91 devices. - * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag, applicable only for STM32FO91 devices. - * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag, applicable only for STM32FO91 devices. - * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag, applicable only for STM32FO91 devices. - * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag, applicable only for STM32FO91 devices. - * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag, applicable only for STM32FO91 devices. - * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag, applicable only for STM32FO91 devices. - * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag, applicable only for STM32FO91 devices. - * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag, applicable only for STM32FO91 devices. - * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag, applicable only for STM32FO91 devices. - * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag, applicable only for STM32FO91 devices. - * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag, applicable only for STM32FO91 devices. - * @note The Global flag (DMAy_FLAG_GLx) is set whenever any of the other flags - * relative to the same channel is set (Transfer Complete, Half-transfer - * Complete or Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx or - * DMAy_FLAG_TEx). - * - * @retval The new state of DMA_FLAG (SET or RESET). - */ -FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_DMA_GET_FLAG(DMAy_FLAG)); - - /* Calculate the used DMAy */ - if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET) - { - /* Get DMA2 ISR register value */ - tmpreg = DMA2->ISR ; - } - else - { - /* Get DMA1 ISR register value */ - tmpreg = DMA1->ISR ; - } - - /* Check the status of the specified DMAy flag */ - if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET) - { - /* DMAy_FLAG is set */ - bitstatus = SET; - } - else - { - /* DMAy_FLAG is reset */ - bitstatus = RESET; - } - - /* Return the DMAy_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the DMAy Channelx's pending flags. - * @param DMA_FLAG: specifies the flag to clear. - * This parameter can be any combination (for the same DMA) of the following values: - * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. - * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. - * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. - * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. - * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. - * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. - * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. - * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. - * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. - * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. - * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. - * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. - * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. - * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. - * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. - * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. - * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. - * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. - * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. - * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. - * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag, applicable only for STM32F072 and STM32FO91 devices. - * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag, applicable only for STM32F072 and STM32FO91 devices. - * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag, applicable only for STM32F072 and STM32FO91 devices. - * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag, applicable only for STM32F072 and STM32FO91 devices. - * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag, applicable only for STM32F072 and STM32FO91 devices. - * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag, applicable only for STM32F072 and STM32FO91 devices. - * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag, applicable only for STM32F072 and STM32FO91 devices. - * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag, applicable only for STM32F072 and STM32FO91 devices. - * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag, applicable only for STM32FO91 devices. - * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag, applicable only for STM32FO91 devices. - * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag, applicable only for STM32FO91 devices. - * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag, applicable only for STM32FO91 devices. - * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag, applicable only for STM32FO91 devices. - * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag, applicable only for STM32FO91 devices. - * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag, applicable only for STM32FO91 devices. - * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag, applicable only for STM32FO91 devices. - * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag, applicable only for STM32FO91 devices. - * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag, applicable only for STM32FO91 devices. - * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag, applicable only for STM32FO91 devices. - * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag, applicable only for STM32FO91 devices. - * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag, applicable only for STM32FO91 devices. - * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag, applicable only for STM32FO91 devices. - * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag, applicable only for STM32FO91 devices. - * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag, applicable only for STM32FO91 devices. - * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag, applicable only for STM32FO91 devices. - * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag, applicable only for STM32FO91 devices. - * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag, applicable only for STM32FO91 devices. - * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag, applicable only for STM32FO91 devices. - * - * @note Clearing the Global flag (DMAy_FLAG_GLx) results in clearing all other flags - * relative to the same channel (Transfer Complete, Half-transfer Complete and - * Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx). - * - * @retval None - */ -void DMA_ClearFlag(uint32_t DMAy_FLAG) -{ - /* Check the parameters */ - assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG)); - -/* Calculate the used DMAy */ - if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET) - { - /* Clear the selected DMAy flags */ - DMA2->IFCR = DMAy_FLAG; - } - else - { - /* Clear the selected DMAy flags */ - DMA1->IFCR = DMAy_FLAG; - } -} - -/** - * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not. - * @param DMA_IT: specifies the DMA interrupt source to check. - * This parameter can be one of the following values: - * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. - * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. - * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. - * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. - * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. - * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. - * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. - * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. - * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. - * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. - * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. - * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. - * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. - * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. - * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. - * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. - * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. - * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. - * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. - * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. - * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt, applicable only for STM32F072 and STM32FO91 devices. - * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt, applicable only for STM32F072 and STM32FO91 devices. - * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt, applicable only for STM32F072 and STM32FO91 devices. - * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt, applicable only for STM32F072 and STM32FO91 devices. - * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt, applicable only for STM32F072 and STM32FO91 devices. - * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt, applicable only for STM32F072 and STM32FO91 devices. - * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt, applicable only for STM32F072 and STM32FO91 devices. - * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt, applicable only for STM32F072 and STM32FO91 devices. - * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt, applicable only for STM32FO91 devices. - * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt, applicable only for STM32FO91 devices. - * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt, applicable only for STM32FO91 devices. - * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt, applicable only for STM32FO91 devices. - * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt, applicable only for STM32FO91 devices. - * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt, applicable only for STM32FO91 devices. - * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt, applicable only for STM32FO91 devices. - * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt, applicable only for STM32FO91 devices. - * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt, applicable only for STM32FO91 devices. - * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt, applicable only for STM32FO91 devices. - * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt, applicable only for STM32FO91 devices. - * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt, applicable only for STM32FO91 devices. - * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt, applicable only for STM32FO91 devices. - * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt, applicable only for STM32FO91 devices. - * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt, applicable only for STM32FO91 devices. - * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt, applicable only for STM32FO91 devices. - * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt, applicable only for STM32FO91 devices. - * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt, applicable only for STM32FO91 devices. - * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt, applicable only for STM32FO91 devices. - * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt, applicable only for STM32FO91 devices. - * @note The Global interrupt (DMAy_FLAG_GLx) is set whenever any of the other - * interrupts relative to the same channel is set (Transfer Complete, - * Half-transfer Complete or Transfer Error interrupts: DMAy_IT_TCx, - * DMAy_IT_HTx or DMAy_IT_TEx). - * - * @retval The new state of DMA_IT (SET or RESET). - */ -ITStatus DMA_GetITStatus(uint32_t DMAy_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_DMA_GET_IT(DMAy_IT)); - - /* Calculate the used DMA */ - if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET) - { - /* Get DMA2 ISR register value */ - tmpreg = DMA2->ISR; - } - else - { - /* Get DMA1 ISR register value */ - tmpreg = DMA1->ISR; - } - - /* Check the status of the specified DMAy interrupt */ - if ((tmpreg & DMAy_IT) != (uint32_t)RESET) - { - /* DMAy_IT is set */ - bitstatus = SET; - } - else - { - /* DMAy_IT is reset */ - bitstatus = RESET; - } - /* Return the DMAy_IT status */ - return bitstatus; -} - -/** - * @brief Clears the DMAy Channelx's interrupt pending bits. - * @param DMA_IT: specifies the DMA interrupt pending bit to clear. - * This parameter can be any combination (for the same DMA) of the following values: - * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. - * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. - * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. - * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. - * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. - * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. - * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. - * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. - * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. - * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. - * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. - * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. - * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. - * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. - * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. - * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. - * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. - * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. - * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. - * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. - * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt, applicable only for STM32F072 and STM32FO91 devices. - * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt, applicable only for STM32F072 and STM32FO91 devices. - * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt, applicable only for STM32F072 and STM32FO91 devices. - * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt, applicable only for STM32F072 and STM32FO91 devices. - * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt, applicable only for STM32F072 and STM32FO91 devices. - * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt, applicable only for STM32F072 and STM32FO91 devices. - * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt, applicable only for STM32F072 and STM32FO91 devices. - * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt, applicable only for STM32F072 and STM32FO91 devices. - * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt, applicable only for STM32FO91 devices. - * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt, applicable only for STM32FO91 devices. - * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt, applicable only for STM32FO91 devices. - * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt, applicable only for STM32FO91 devices. - * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt, applicable only for STM32FO91 devices. - * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt, applicable only for STM32FO91 devices. - * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt, applicable only for STM32FO91 devices. - * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt, applicable only for STM32FO91 devices. - * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt, applicable only for STM32FO91 devices. - * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt, applicable only for STM32FO91 devices. - * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt, applicable only for STM32FO91 devices. - * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt, applicable only for STM32FO91 devices. - * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt, applicable only for STM32FO91 devices. - * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt, applicable only for STM32FO91 devices. - * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt, applicable only for STM32FO91 devices. - * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt, applicable only for STM32FO91 devices. - * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt, applicable only for STM32FO91 devices. - * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt, applicable only for STM32FO91 devices. - * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt, applicable only for STM32FO91 devices. - * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt, applicable only for STM32FO91 devices. - * - * @note Clearing the Global interrupt (DMAy_IT_GLx) results in clearing all other - * interrupts relative to the same channel (Transfer Complete, Half-transfer - * Complete and Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx and - * DMAy_IT_TEx). - * - * @retval None - */ -void DMA_ClearITPendingBit(uint32_t DMAy_IT) -{ - /* Check the parameters */ - assert_param(IS_DMA_CLEAR_IT(DMAy_IT)); - - /* Calculate the used DMAy */ - if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET) - { - /* Clear the selected DMAy interrupt pending bits */ - DMA2->IFCR = DMAy_IT; - } - else - { - /* Clear the selected DMAy interrupt pending bits */ - DMA1->IFCR = DMAy_IT; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_exti.c b/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_exti.c deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_exti.c +++ /dev/null @@ -1,314 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_exti.c - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the EXTI peripheral: - * + Initialization and Configuration - * + Interrupts and flags management - * - * @verbatim - ============================================================================== - ##### EXTI features ##### - ============================================================================== - [..] External interrupt/event lines are mapped as following: - (#) All available GPIO pins are connected to the 16 external - interrupt/event lines from EXTI0 to EXTI15. - (#) EXTI line 16 is connected to the PVD output, not applicable for STM32F030 devices. - (#) EXTI line 17 is connected to the RTC Alarm event. - (#) EXTI line 18 is connected to the RTC Alarm event, applicable only for STM32F072 devices. - (#) EXTI line 19 is connected to the RTC Tamper and TimeStamp events. - (#) EXTI line 20 is connected to the RTC wakeup event, applicable only for STM32F072 devices. - (#) EXTI line 21 is connected to the Comparator 1 wakeup event, applicable only for STM32F051 and STM32F072 devices. - (#) EXTI line 22 is connected to the Comparator 2 wakeup event, applicable only for STM32F051 and STM32F072 devices. - (#) EXTI line 23 is connected to the I2C1 wakeup event, not applicable for STM32F030 devices. - (#) EXTI line 25 is connected to the USART1 wakeup event, not applicable for STM32F030 devices. - (#) EXTI line 26 is connected to the USART2 wakeup event, applicable only for STM32F072 devices. - (#) EXTI line 27 is connected to the CEC wakeup event, applicable only for STM32F051 and STM32F072 devices. - (#) EXTI line 31 is connected to the VDD USB monitor event, applicable only for STM32F072 devices. - - ##### How to use this driver ##### - ============================================================================== - [..] In order to use an I/O pin as an external interrupt source, follow - steps below: - (#) Configure the I/O in input mode using GPIO_Init() - (#) Select the input source pin for the EXTI line using - SYSCFG_EXTILineConfig(). - (#) Select the mode(interrupt, event) and configure the trigger selection - (Rising, falling or both) using EXTI_Init(). For the internal interrupt, - the trigger selection is not needed( the active edge is always the rising one). - (#) Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init(). - (#) Optionally, you can generate a software interrupt using the function EXTI_GenerateSWInterrupt(). - [..] - (@) SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx - registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); - @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_exti.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup EXTI - * @brief EXTI driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup EXTI_Private_Functions - * @{ - */ - -/** @defgroup EXTI_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - ============================================================================== - ##### Initialization and Configuration functions ##### - ============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the EXTI peripheral registers to their default reset - * values. - * @param None - * @retval None - */ -void EXTI_DeInit(void) -{ - EXTI->IMR = 0x0F940000; - EXTI->EMR = 0x00000000; - EXTI->RTSR = 0x00000000; - EXTI->FTSR = 0x00000000; - EXTI->PR = 0x006BFFFF; -} - -/** - * @brief Initializes the EXTI peripheral according to the specified - * parameters in the EXTI_InitStruct. - * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure that - * contains the configuration information for the EXTI peripheral. - * @retval None - */ -void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); - assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); - assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); - assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); - - tmp = (uint32_t)EXTI_BASE; - - if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) - { - /* Clear EXTI line configuration */ - EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line; - EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line; - - tmp += EXTI_InitStruct->EXTI_Mode; - - *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; - - /* Clear Rising Falling edge configuration */ - EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line; - EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line; - - /* Select the trigger for the selected interrupts */ - if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) - { - /* Rising Falling edge */ - EXTI->RTSR |= EXTI_InitStruct->EXTI_Line; - EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; - } - else - { - tmp = (uint32_t)EXTI_BASE; - tmp += EXTI_InitStruct->EXTI_Trigger; - - *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; - } - } - else - { - tmp += EXTI_InitStruct->EXTI_Mode; - - /* Disable the selected external lines */ - *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line; - } -} - -/** - * @brief Fills each EXTI_InitStruct member with its reset value. - * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) -{ - EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; - EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; - EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; - EXTI_InitStruct->EXTI_LineCmd = DISABLE; -} - -/** - * @brief Generates a Software interrupt on selected EXTI line. - * @param EXTI_Line: specifies the EXTI line on which the software interrupt - * will be generated. - * This parameter can be any combination of EXTI_Linex where x can be (0..27). - * @retval None - */ -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(EXTI_Line)); - - EXTI->SWIER |= EXTI_Line; -} - -/** - * @} - */ - -/** @defgroup EXTI_Group2 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - ============================================================================== - ##### Interrupts and flags management functions ##### - ============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Checks whether the specified EXTI line flag is set or not. - * @param EXTI_Line: specifies the EXTI line flag to check. - * This parameter can be EXTI_Linex where x can be (0..27). - * @retval The new state of EXTI_Line (SET or RESET). - */ -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_GET_EXTI_LINE(EXTI_Line)); - - if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the EXTI's line pending flags. - * @param EXTI_Line: specifies the EXTI lines flags to clear. - * This parameter can be any combination of EXTI_Linex where x can be (0..27). - * @retval None - */ -void EXTI_ClearFlag(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(EXTI_Line)); - - EXTI->PR = EXTI_Line; -} - -/** - * @brief Checks whether the specified EXTI line is asserted or not. - * @param EXTI_Line: specifies the EXTI line to check. - * This parameter can be EXTI_Linex where x can be (0..27). - * @retval The new state of EXTI_Line (SET or RESET). - */ -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) -{ - ITStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_GET_EXTI_LINE(EXTI_Line)); - - if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the EXTI's line pending bits. - * @param EXTI_Line: specifies the EXTI lines to clear. - * This parameter can be any combination of EXTI_Linex where x can be (0..27). - * @retval None - */ -void EXTI_ClearITPendingBit(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(EXTI_Line)); - - EXTI->PR = EXTI_Line; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_flash.c b/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_flash.c deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_flash.c +++ /dev/null @@ -1,1256 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_flash.c - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the FLASH peripheral: - * - FLASH Interface configuration - * - FLASH Memory Programming - * - Option Bytes Programming - * - Interrupts and flags management - * - * @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] This driver provides functions to configure and program the Flash - memory of all STM32F0xx devices. These functions are split in 4 groups - (#) FLASH Interface configuration functions: this group includes the - management of following features: - (++) Set the latency - (++) Enable/Disable the prefetch buffer - - (#) FLASH Memory Programming functions: this group includes all needed - functions to erase and program the main memory: - (++) Lock and Unlock the Flash interface. - (++) Erase function: Erase Page, erase all pages. - (++) Program functions: Half Word and Word write. - - (#) FLASH Option Bytes Programming functions: this group includes all - needed functions to: - (++) Lock and Unlock the Flash Option bytes. - (++) Launch the Option Bytes loader - (++) Erase the Option Bytes - (++)Set/Reset the write protection - (++) Set the Read protection Level - (++) Program the user option Bytes - (++) Set/Reset the BOOT1 bit - (++) Enable/Disable the VDDA Analog Monitoring - (++) Get the user option bytes - (++) Get the Write protection - (++) Get the read protection status - - (#) FLASH Interrupts and flag management functions: this group includes - all needed functions to: - (++) Enable/Disable the flash interrupt sources - (++) Get flags status - (++) Clear flags - (++) Get Flash operation status - (++) Wait for last flash operation - - @endverbatim - - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_flash.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup FLASH - * @brief FLASH driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup FLASH_Private_Functions - * @{ - */ - -/** @defgroup FLASH_Group1 FLASH Interface configuration functions - * @brief FLASH Interface configuration functions - * -@verbatim - =============================================================================== - ##### FLASH Interface configuration functions ##### - =============================================================================== - - [..] FLASH_Interface configuration_Functions, includes the following functions: - (+) void FLASH_SetLatency(uint32_t FLASH_Latency): - [..] To correctly read data from Flash memory, the number of wait states (LATENCY) - must be correctly programmed according to the frequency of the CPU clock (HCLK) - [..] - +--------------------------------------------- + - | Wait states | HCLK clock frequency (MHz) | - |---------------|------------------------------| - |0WS(1CPU cycle)| 0 < HCLK <= 24 | - |---------------|------------------------------| - |1WS(2CPU cycle)| 24 < HCLK <= 48 | - +----------------------------------------------+ - [..] - (+) void FLASH_PrefetchBufferCmd(FunctionalState NewState); - [..] - All these functions don't need the unlock sequence. - -@endverbatim - * @{ - */ - -/** - * @brief Sets the code latency value. - * @param FLASH_Latency: specifies the FLASH Latency value. - * This parameter can be one of the following values: - * @arg FLASH_Latency_0: FLASH Zero Latency cycle - * @arg FLASH_Latency_1: FLASH One Latency cycle - * @retval None - */ -void FLASH_SetLatency(uint32_t FLASH_Latency) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_FLASH_LATENCY(FLASH_Latency)); - - /* Read the ACR register */ - tmpreg = FLASH->ACR; - - /* Sets the Latency value */ - tmpreg &= (uint32_t) (~((uint32_t)FLASH_ACR_LATENCY)); - tmpreg |= FLASH_Latency; - - /* Write the ACR register */ - FLASH->ACR = tmpreg; -} - -/** - * @brief Enables or disables the Prefetch Buffer. - * @param NewState: new state of the FLASH prefetch buffer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FLASH_PrefetchBufferCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if(NewState != DISABLE) - { - FLASH->ACR |= FLASH_ACR_PRFTBE; - } - else - { - FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_PRFTBE)); - } -} - -/** - * @brief Checks whether the FLASH Prefetch Buffer status is set or not. - * @param None - * @retval FLASH Prefetch Buffer Status (SET or RESET). - */ -FlagStatus FLASH_GetPrefetchBufferStatus(void) -{ - FlagStatus bitstatus = RESET; - - if ((FLASH->ACR & FLASH_ACR_PRFTBS) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */ - return bitstatus; -} - -/** - * @} - */ - -/** @defgroup FLASH_Group2 FLASH Memory Programming functions - * @brief FLASH Memory Programming functions - * -@verbatim - =============================================================================== - ##### FLASH Memory Programming functions ##### - =============================================================================== - - [..] The FLASH Memory Programming functions, includes the following functions: - (+) void FLASH_Unlock(void); - (+) void FLASH_Lock(void); - (+) FLASH_Status FLASH_ErasePage(uint32_t Page_Address); - (+) FLASH_Status FLASH_EraseAllPages(void); - (+) FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); - (+) FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); - - [..] Any operation of erase or program should follow these steps: - - (#) Call the FLASH_Unlock() function to enable the flash control register and - program memory access - (#) Call the desired function to erase page or program data - (#) Call the FLASH_Lock() to disable the flash program memory access - (recommended to protect the FLASH memory against possible unwanted operation) - -@endverbatim - * @{ - */ - -/** - * @brief Unlocks the FLASH control register and program memory access. - * @param None - * @retval None - */ -void FLASH_Unlock(void) -{ - if((FLASH->CR & FLASH_CR_LOCK) != RESET) - { - /* Unlocking the program memory access */ - FLASH->KEYR = FLASH_FKEY1; - FLASH->KEYR = FLASH_FKEY2; - } -} - -/** - * @brief Locks the Program memory access. - * @param None - * @retval None - */ -void FLASH_Lock(void) -{ - /* Set the LOCK Bit to lock the FLASH control register and program memory access */ - FLASH->CR |= FLASH_CR_LOCK; -} - -/** - * @brief Erases a specified page in program memory. - * @note To correctly run this function, the FLASH_Unlock() function must be called before. - * @note Call the FLASH_Lock() to disable the flash memory access (recommended - * to protect the FLASH memory against possible unwanted operation) - * @param Page_Address: The page address in program memory to be erased. - * @note A Page is erased in the Program memory only if the address to load - * is the start address of a page (multiple of 1024 bytes). - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ErasePage(uint32_t Page_Address) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_PROGRAM_ADDRESS(Page_Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* If the previous operation is completed, proceed to erase the page */ - FLASH->CR |= FLASH_CR_PER; - FLASH->AR = Page_Address; - FLASH->CR |= FLASH_CR_STRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - /* Disable the PER Bit */ - FLASH->CR &= ~FLASH_CR_PER; - } - - /* Return the Erase Status */ - return status; -} - -/** - * @brief Erases all FLASH pages. - * @note To correctly run this function, the FLASH_Unlock() function must be called before. - * @note Call the FLASH_Lock() to disable the flash memory access (recommended - * to protect the FLASH memory against possible unwanted operation) - * @param None - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EraseAllPages(void) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase all pages */ - FLASH->CR |= FLASH_CR_MER; - FLASH->CR |= FLASH_CR_STRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - /* Disable the MER Bit */ - FLASH->CR &= ~FLASH_CR_MER; - } - - /* Return the Erase Status */ - return status; -} - -/** - * @brief Programs a word at a specified address. - * @note To correctly run this function, the FLASH_Unlock() function must be called before. - * @note Call the FLASH_Lock() to disable the flash memory access (recommended - * to protect the FLASH memory against possible unwanted operation) - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* If the previous operation is completed, proceed to program the new first - half word */ - FLASH->CR |= FLASH_CR_PG; - - *(__IO uint16_t*)Address = (uint16_t)Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* If the previous operation is completed, proceed to program the new second - half word */ - tmp = Address + 2; - - *(__IO uint16_t*) tmp = Data >> 16; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - /* Disable the PG Bit */ - FLASH->CR &= ~FLASH_CR_PG; - } - else - { - /* Disable the PG Bit */ - FLASH->CR &= ~FLASH_CR_PG; - } - } - - /* Return the Program Status */ - return status; -} - -/** - * @brief Programs a half word at a specified address. - * @note To correctly run this function, the FLASH_Unlock() function must be called before. - * @note Call the FLASH_Lock() to disable the flash memory access (recommended - * to protect the FLASH memory against possible unwanted operation) - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* If the previous operation is completed, proceed to program the new data */ - FLASH->CR |= FLASH_CR_PG; - - *(__IO uint16_t*)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - /* Disable the PG Bit */ - FLASH->CR &= ~FLASH_CR_PG; - } - - /* Return the Program Status */ - return status; -} - -/** - * @} - */ - -/** @defgroup FLASH_Group3 Option Bytes Programming functions - * @brief Option Bytes Programming functions - * -@verbatim - =============================================================================== - ##### Option Bytes Programming functions ##### - =============================================================================== - - [..] The FLASH_Option Bytes Programming_functions, includes the following functions: - (+) void FLASH_OB_Unlock(void); - (+) void FLASH_OB_Lock(void); - (+) void FLASH_OB_Launch(void); - (+) FLASH_Status FLASH_OB_Erase(void); - (+) FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState); - (+) FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP); - (+) FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY); - (+) FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1); - (+) FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG); - (+) FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER); - (+) FLASH_OB_ProgramData(uint32_t Address, uint8_t Data); - (+) uint8_t FLASH_OB_GetUser(void); - (+) uint32_t FLASH_OB_GetWRP(void); - (+) FlagStatus FLASH_OB_GetRDP(void); - - [..] Any operation of erase or program should follow these steps: - - (#) Call the FLASH_OB_Unlock() function to enable the Option Bytes registers access - - (#) Call one or several functions to program the desired option bytes - (++) FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read Protection Level - (++) FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) - => to Enable/Disable the desired sector write protection - (++) FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) - => to configure the user option Bytes: IWDG, STOP and the Standby. - (++) FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1) - => to set or reset BOOT1 - (++) FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG) - => to enable or disable the VDDA Analog Monitoring - (++) You can write all User Options bytes at once using a single function - by calling FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER) - (++) FLASH_OB_ProgramData(uint32_t Address, uint8_t Data) to program the - two half word in the option bytes - - (#) Once all needed option bytes to be programmed are correctly written, call the - FLASH_OB_Launch(void) function to launch the Option Bytes programming process. - - (#) Call the FLASH_OB_Lock() to disable the Option Bytes registers access (recommended - to protect the option Bytes against possible unwanted operations) - -@endverbatim - * @{ - */ - -/** - * @brief Unlocks the option bytes block access. - * @param None - * @retval None - */ -void FLASH_OB_Unlock(void) -{ - if((FLASH->CR & FLASH_CR_OPTWRE) == RESET) - { - /* Unlocking the option bytes block access */ - FLASH->OPTKEYR = FLASH_OPTKEY1; - FLASH->OPTKEYR = FLASH_OPTKEY2; - } -} - -/** - * @brief Locks the option bytes block access. - * @param None - * @retval None - */ -void FLASH_OB_Lock(void) -{ - /* Set the OPTWREN Bit to lock the option bytes block access */ - FLASH->CR &= ~FLASH_CR_OPTWRE; -} - -/** - * @brief Launch the option byte loading. - * @param None - * @retval None - */ -void FLASH_OB_Launch(void) -{ - /* Set the OBL_Launch bit to launch the option byte loading */ - FLASH->CR |= FLASH_CR_OBL_LAUNCH; -} - -/** - * @brief Erases the FLASH option bytes. - * @note To correctly run this function, the FLASH_OB_Unlock() function must be called before. - * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option - * bytes (recommended to protect the FLASH memory against possible unwanted operation) - * @note This functions erases all option bytes except the Read protection (RDP). - * @param None - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_OB_Erase(void) -{ - uint16_t rdptmp = OB_RDP_Level_0; - - FLASH_Status status = FLASH_COMPLETE; - - /* Get the actual read protection Option Byte value */ - if(FLASH_OB_GetRDP() != RESET) - { - rdptmp = 0x00; - } - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* If the previous operation is completed, proceed to erase the option bytes */ - FLASH->CR |= FLASH_CR_OPTER; - FLASH->CR |= FLASH_CR_STRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* If the erase operation is completed, disable the OPTER Bit */ - FLASH->CR &= ~FLASH_CR_OPTER; - - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= FLASH_CR_OPTPG; - - /* Restore the last read protection Option Byte value */ - OB->RDP = (uint16_t)rdptmp; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= ~FLASH_CR_OPTPG; - } - } - else - { - if (status != FLASH_TIMEOUT) - { - /* Disable the OPTPG Bit */ - FLASH->CR &= ~FLASH_CR_OPTPG; - } - } - } - /* Return the erase status */ - return status; -} - -/** - * @brief Write protects the desired pages - * @note To correctly run this function, the FLASH_OB_Unlock() function must be called before. - * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option - * bytes (recommended to protect the FLASH memory against possible unwanted operation) - * @param OB_WRP: specifies the address of the pages to be write protected. - * This parameter can be: - * @arg OB_WRP_Pages0to3..OB_WRP_Pages60to63 - * @arg OB_WRP_AllPages - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_OB_EnableWRP(uint32_t OB_WRP) -{ - uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF; - - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_WRP(OB_WRP)); - - OB_WRP = (uint32_t)(~OB_WRP); - WRP0_Data = (uint16_t)(OB_WRP & OB_WRP0_WRP0); - WRP1_Data = (uint16_t)((OB_WRP >> 8) & OB_WRP0_WRP0); - WRP2_Data = (uint16_t)((OB_WRP >> 16) & OB_WRP0_WRP0) ; - WRP3_Data = (uint16_t)((OB_WRP >> 24) & OB_WRP0_WRP0) ; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - FLASH->CR |= FLASH_CR_OPTPG; - - if(WRP0_Data != 0xFF) - { - OB->WRP0 = WRP0_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - } - if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF)) - { - OB->WRP1 = WRP1_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - } - if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF)) - { - OB->WRP2 = WRP2_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - } - if((status == FLASH_COMPLETE) && (WRP3_Data != 0xFF)) - { - OB->WRP3 = WRP3_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - } - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= ~FLASH_CR_OPTPG; - } - } - /* Return the write protection operation Status */ - return status; -} - -/** - * @brief Enables or disables the read out protection. - * @note To correctly run this function, the FLASH_OB_Unlock() function must be called before. - * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option - * bytes (recommended to protect the FLASH memory against possible unwanted operation) - * @param FLASH_ReadProtection_Level: specifies the read protection level. - * This parameter can be: - * @arg OB_RDP_Level_0: No protection - * @arg OB_RDP_Level_1: Read protection of the memory - * @arg OB_RDP_Level_2: Chip protection - * @note When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_RDP(OB_RDP)); - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - FLASH->CR |= FLASH_CR_OPTER; - FLASH->CR |= FLASH_CR_STRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* If the erase operation is completed, disable the OPTER Bit */ - FLASH->CR &= ~FLASH_CR_OPTER; - - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= FLASH_CR_OPTPG; - - OB->RDP = OB_RDP; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= ~FLASH_CR_OPTPG; - } - } - else - { - if(status != FLASH_TIMEOUT) - { - /* Disable the OPTER Bit */ - FLASH->CR &= ~FLASH_CR_OPTER; - } - } - } - /* Return the protection operation Status */ - return status; -} - -/** - * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. - * @note To correctly run this function, the FLASH_OB_Unlock() function must be called before. - * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option - * bytes (recommended to protect the FLASH memory against possible unwanted operation) - * @param OB_IWDG: Selects the WDG mode - * This parameter can be one of the following values: - * @arg OB_IWDG_SW: Software WDG selected - * @arg OB_IWDG_HW: Hardware WDG selected - * @param OB_STOP: Reset event when entering STOP mode. - * This parameter can be one of the following values: - * @arg OB_STOP_NoRST: No reset generated when entering in STOP - * @arg OB_STOP_RST: Reset generated when entering in STOP - * @param OB_STDBY: Reset event when entering Standby mode. - * This parameter can be one of the following values: - * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY - * @arg OB_STDBY_RST: Reset generated when entering in STANDBY - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); - assert_param(IS_OB_STOP_SOURCE(OB_STOP)); - assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= FLASH_CR_OPTPG; - - OB->USER = (uint16_t)((uint16_t)(OB_IWDG | OB_STOP) | (uint16_t)(OB_STDBY | 0xF8)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status != FLASH_TIMEOUT) - { - /* If the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= ~FLASH_CR_OPTPG; - } - } - /* Return the Option Byte program Status */ - return status; -} - -/** - * @brief Sets or resets the BOOT1 option bit. - * @param OB_BOOT1: Set or Reset the BOOT1 option bit. - * This parameter can be one of the following values: - * @arg OB_BOOT1_RESET: BOOT1 option bit reset - * @arg OB_BOOT1_SET: BOOT1 option bit set - * @retval None - */ -FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_BOOT1(OB_BOOT1)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= FLASH_CR_OPTPG; - - OB->USER = OB_BOOT1 | 0xEF; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status != FLASH_TIMEOUT) - { - /* If the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= ~FLASH_CR_OPTPG; - } - } - /* Return the Option Byte program Status */ - return status; -} - -/** - * @brief Sets or resets the BOOT0 option bit. - * @note This function is applicable only for the STM32F042 devices. - * @param OB_BOOT0: Set or Reset the BOOT0 option bit. - * This parameter can be one of the following values: - * @arg OB_BOOT0_RESET: BOOT0 option bit reset - * @arg OB_BOOT0_SET: BOOT0 option bit set - * @retval None - */ -FLASH_Status FLASH_OB_BOOT0Config(uint8_t OB_BOOT0) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_BOOT0(OB_BOOT0)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= FLASH_CR_OPTPG; - - OB->USER = OB_BOOT0 | 0xF7; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status != FLASH_TIMEOUT) - { - /* If the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= ~FLASH_CR_OPTPG; - } - } - /* Return the Option Byte program Status */ - return status; -} - -/** - * @brief Sets or resets the BOOT0SW option bit. - * @note This function is applicable only for the STM32F042 devices. - * @param OB_BOOT0SW: Set or Reset the BOOT0_SW option bit. - * This parameter can be one of the following values: - * @arg OB_BOOT0_SW: BOOT0_SW option bit reset - * @arg OB_BOOT0_HW: BOOT0_SW option bit set - * @retval None - */ -FLASH_Status FLASH_OB_BOOT0SWConfig(uint8_t OB_BOOT0SW) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_BOOT0SW(OB_BOOT0SW)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= FLASH_CR_OPTPG; - - OB->USER = OB_BOOT0SW | 0x7F; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status != FLASH_TIMEOUT) - { - /* If the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= ~FLASH_CR_OPTPG; - } - } - /* Return the Option Byte program Status */ - return status; -} - -/** - * @brief Sets or resets the analogue monitoring on VDDA Power source. - * @param OB_VDDA_ANALOG: Selects the analog monitoring on VDDA Power source. - * This parameter can be one of the following values: - * @arg OB_VDDA_ANALOG_ON: Analog monitoring on VDDA Power source ON - * @arg OB_VDDA_ANALOG_OFF: Analog monitoring on VDDA Power source OFF - * @retval None - */ -FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_VDDA_ANALOG(OB_VDDA_ANALOG)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= FLASH_CR_OPTPG; - - OB->USER = OB_VDDA_ANALOG | 0xDF; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= ~FLASH_CR_OPTPG; - } - } - /* Return the Option Byte program Status */ - return status; -} - -/** - * @brief Sets or resets the SRAM parity. - * @param OB_SRAM_Parity: Set or Reset the SRAM parity enable bit. - * This parameter can be one of the following values: - * @arg OB_SRAM_PARITY_SET: Set SRAM parity. - * @arg OB_SRAM_PARITY_RESET: Reset SRAM parity. - * @retval None - */ -FLASH_Status FLASH_OB_SRAMParityConfig(uint8_t OB_SRAM_Parity) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_SRAM_PARITY(OB_SRAM_Parity)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= FLASH_CR_OPTPG; - - OB->USER = OB_SRAM_Parity | 0xBF; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= ~FLASH_CR_OPTPG; - } - } - /* Return the Option Byte program Status */ - return status; -} - -/** - * @brief Programs the FLASH User Option Byte: IWDG_SW, RST_STOP, RST_STDBY, - * BOOT1 and VDDA ANALOG monitoring. - * @note To correctly run this function, the FLASH_OB_Unlock() function must be called before. - * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option - * bytes (recommended to protect the FLASH memory against possible unwanted operation) - * @param OB_USER: Selects all user option bytes - * This parameter is a combination of the following values: - * @arg OB_IWDG_SW / OB_IWDG_HW: Software / Hardware WDG selected - * @arg OB_STOP_NoRST / OB_STOP_RST: No reset / Reset generated when entering in STOP - * @arg OB_STDBY_NoRST / OB_STDBY_RST: No reset / Reset generated when entering in STANDBY - * @arg OB_BOOT1_RESET / OB_BOOT1_SET: BOOT1 Reset / Set - * @arg OB_VDDA_ANALOG_ON / OB_VDDA_ANALOG_OFF: Analog monitoring on VDDA Power source ON / OFF - * @arg OB_SRAM_PARITY_SET / OB_SRAM_PARITY_RESET: SRAM Parity SET / RESET - * @arg OB_BOOT0_RESET / OB_BOOT0_SET: BOOT0 Reset / Set - * @arg OB_BOOT0_SW / OB_BOOT0_SW: BOOT0 pin disabled / BOOT0 pin bonded with GPIO - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= FLASH_CR_OPTPG; - - OB->USER = OB_USER; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status != FLASH_TIMEOUT) - { - /* If the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= ~FLASH_CR_OPTPG; - } - } - /* Return the Option Byte program Status */ - return status; - -} - -/** - * @brief Programs a half word at a specified Option Byte Data address. - * @note To correctly run this function, the FLASH_OB_Unlock() function must be called before. - * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option - * bytes (recommended to protect the FLASH memory against possible unwanted operation) - * @param Address: specifies the address to be programmed. - * This parameter can be 0x1FFFF804 or 0x1FFFF806. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_OB_ProgramData(uint32_t Address, uint8_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - /* Check the parameters */ - assert_param(IS_OB_DATA_ADDRESS(Address)); - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* Enables the Option Bytes Programming operation */ - FLASH->CR |= FLASH_CR_OPTPG; - *(__IO uint16_t*)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status != FLASH_TIMEOUT) - { - /* If the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= ~FLASH_CR_OPTPG; - } - } - /* Return the Option Byte Data Program Status */ - return status; -} - -/** - * @brief Returns the FLASH User Option Bytes values. - * @param None - * @retval The FLASH User Option Bytes . - */ -uint8_t FLASH_OB_GetUser(void) -{ - /* Return the User Option Byte */ - return (uint8_t)(FLASH->OBR >> 8); -} - -/** - * @brief Returns the FLASH Write Protection Option Bytes value. - * @param None - * @retval The FLASH Write Protection Option Bytes value - */ -uint32_t FLASH_OB_GetWRP(void) -{ - /* Return the FLASH write protection Register value */ - return (uint32_t)(FLASH->WRPR); -} - -/** - * @brief Checks whether the FLASH Read out Protection Status is set or not. - * @param None - * @retval FLASH ReadOut Protection Status(SET or RESET) - */ -FlagStatus FLASH_OB_GetRDP(void) -{ - FlagStatus readstatus = RESET; - - if ((uint8_t)(FLASH->OBR & (FLASH_OBR_RDPRT1 | FLASH_OBR_RDPRT2)) != RESET) - { - readstatus = SET; - } - else - { - readstatus = RESET; - } - return readstatus; -} - -/** - * @} - */ - -/** @defgroup FLASH_Group4 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified FLASH interrupts. - * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or - * disabled. - * This parameter can be any combination of the following values: - * @arg FLASH_IT_EOP: FLASH end of programming Interrupt - * @arg FLASH_IT_ERR: FLASH Error Interrupt - * @retval None - */ -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FLASH_IT(FLASH_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if(NewState != DISABLE) - { - /* Enable the interrupt sources */ - FLASH->CR |= FLASH_IT; - } - else - { - /* Disable the interrupt sources */ - FLASH->CR &= ~(uint32_t)FLASH_IT; - } -} - -/** - * @brief Checks whether the specified FLASH flag is set or not. - * @param FLASH_FLAG: specifies the FLASH flag to check. - * This parameter can be one of the following values: - * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag - * @arg FLASH_FLAG_PGERR: FLASH Programming error flag flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag - * @arg FLASH_FLAG_EOP: FLASH End of Programming flag - * @retval The new state of FLASH_FLAG (SET or RESET). - */ -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)); - - if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the new state of FLASH_FLAG (SET or RESET) */ - return bitstatus; -} - -/** - * @brief Clears the FLASH's pending flags. - * @param FLASH_FLAG: specifies the FLASH flags to clear. - * This parameter can be any combination of the following values: - * @arg FLASH_FLAG_PGERR: FLASH Programming error flag flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag - * @arg FLASH_FLAG_EOP: FLASH End of Programming flag - * @retval None - */ -void FLASH_ClearFlag(uint32_t FLASH_FLAG) -{ - /* Check the parameters */ - assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)); - - /* Clear the flags */ - FLASH->SR = FLASH_FLAG; -} - -/** - * @brief Returns the FLASH Status. - * @param None - * @retval FLASH Status: The returned value can be: - * FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP or FLASH_COMPLETE. - */ -FLASH_Status FLASH_GetStatus(void) -{ - FLASH_Status FLASHstatus = FLASH_COMPLETE; - - if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) - { - FLASHstatus = FLASH_BUSY; - } - else - { - if((FLASH->SR & (uint32_t)FLASH_FLAG_WRPERR)!= (uint32_t)0x00) - { - FLASHstatus = FLASH_ERROR_WRP; - } - else - { - if((FLASH->SR & (uint32_t)(FLASH_SR_PGERR)) != (uint32_t)0x00) - { - FLASHstatus = FLASH_ERROR_PROGRAM; - } - else - { - FLASHstatus = FLASH_COMPLETE; - } - } - } - /* Return the FLASH Status */ - return FLASHstatus; -} - - -/** - * @brief Waits for a FLASH operation to complete or a TIMEOUT to occur. - * @param Timeout: FLASH programming Timeout - * @retval FLASH Status: The returned value can be: FLASH_BUSY, - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check for the FLASH Status */ - status = FLASH_GetStatus(); - - /* Wait for a FLASH operation to complete or a TIMEOUT to occur */ - while((status == FLASH_BUSY) && (Timeout != 0x00)) - { - status = FLASH_GetStatus(); - Timeout--; - } - - if(Timeout == 0x00 ) - { - status = FLASH_TIMEOUT; - } - /* Return the operation status */ - return status; -} - -/** - * @} - */ - -/** - * @} - */ - - /** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_gpio.c b/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_gpio.c deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_gpio.c +++ /dev/null @@ -1,558 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_gpio.c - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the GPIO peripheral: - * + Initialization and Configuration functions - * + GPIO Read and Write functions - * + GPIO Alternate functions configuration functions - * - * @verbatim - * - * - =========================================================================== - ##### How to use this driver ##### - =========================================================================== - [..] - (#) Enable the GPIO AHB clock using RCC_AHBPeriphClockCmd() - (#) Configure the GPIO pin(s) using GPIO_Init() - Four possible configuration are available for each pin: - (++) Input: Floating, Pull-up, Pull-down. - (++) Output: Push-Pull (Pull-up, Pull-down or no Pull) - Open Drain (Pull-up, Pull-down or no Pull). - In output mode, the speed is configurable: Low, Medium, Fast or High. - (++) Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull) - Open Drain (Pull-up, Pull-down or no Pull). - (++) Analog: required mode when a pin is to be used as ADC channel, - DAC output or comparator input. - (#) Peripherals alternate function: - (++) For ADC, DAC and comparators, configure the desired pin in analog - mode using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN - (++) For other peripherals (TIM, USART...): - (+++) Connect the pin to the desired peripherals' Alternate - Function (AF) using GPIO_PinAFConfig() function. For PortC, - PortD and PortF, no configuration is needed. - (+++) Configure the desired pin in alternate function mode using - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - (+++) Select the type, pull-up/pull-down and output speed via - GPIO_PuPd, GPIO_OType and GPIO_Speed members - (+++) Call GPIO_Init() function - (#) To get the level of a pin configured in input mode use GPIO_ReadInputDataBit() - (#) To set/reset the level of a pin configured in output mode use - GPIO_SetBits()/GPIO_ResetBits() - (#) During and just after reset, the alternate functions are not active and - the GPIO pins are configured in input floating mode (except JTAG pins). - (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as - general-purpose (PC14 and PC15, respectively) when the LSE oscillator - is off. The LSE has priority over the GPIO function. - (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose - PD0 and PD1, respectively, when the HSE oscillator is off. The HSE has - priority over the GPIO function. - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_gpio.h" -#include "stm32f0xx_rcc.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup GPIO - * @brief GPIO driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup GPIO_Private_Functions - * @{ - */ - -/** @defgroup GPIO_Group1 Initialization and Configuration - * @brief Initialization and Configuration - * -@verbatim - =============================================================================== - ##### Initialization and Configuration ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the GPIOx peripheral registers to their default reset - * values. - * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral. - * @note GPIOE is available only for STM32F072. - * @note GPIOD is not available for STM32F031. - * @retval None - */ -void GPIO_DeInit(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - if(GPIOx == GPIOA) - { - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, ENABLE); - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, DISABLE); - } - else if(GPIOx == GPIOB) - { - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, ENABLE); - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, DISABLE); - } - else if(GPIOx == GPIOC) - { - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, ENABLE); - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, DISABLE); - } - else if(GPIOx == GPIOD) - { - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, ENABLE); - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, DISABLE); - } - else if(GPIOx == GPIOE) - { - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, ENABLE); - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, DISABLE); - } - else - { - if(GPIOx == GPIOF) - { - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, ENABLE); - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, DISABLE); - } - } -} - -/** - * @brief Initializes the GPIOx peripheral according to the specified - * parameters in the GPIO_InitStruct. - * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral. - * @note GPIOE is available only for STM32F072. - * @note GPIOD is not available for STM32F031. - * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains - * the configuration information for the specified GPIO peripheral. - * @retval None - */ -void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) -{ - uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); - assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); - assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd)); - - /*-------------------------- Configure the port pins -----------------------*/ - /*-- GPIO Mode Configuration --*/ - for (pinpos = 0x00; pinpos < 0x10; pinpos++) - { - pos = ((uint32_t)0x01) << pinpos; - - /* Get the port pins position */ - currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; - - if (currentpin == pos) - { - if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF)) - { - /* Check Speed mode parameters */ - assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); - - /* Speed mode configuration */ - GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2)); - GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2)); - - /* Check Output mode parameters */ - assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType)); - - /* Output mode configuration */ - GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)); - GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos)); - } - - GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2)); - - GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2)); - - /* Pull-up Pull down resistor configuration */ - GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2)); - GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2)); - } - } -} - -/** - * @brief Fills each GPIO_InitStruct member with its default value. - * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) -{ - /* Reset GPIO init structure parameters values */ - GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStruct->GPIO_Speed = GPIO_Speed_Level_2; - GPIO_InitStruct->GPIO_OType = GPIO_OType_PP; - GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL; -} - -/** - * @brief Locks GPIO Pins configuration registers. - * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, - * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. - * @note The configuration of the locked GPIO pins can no longer be modified - * until the next device reset. - * @param GPIOx: where x can be (A or B) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - __IO uint32_t tmp = 0x00010000; - - /* Check the parameters */ - assert_param(IS_GPIO_LIST_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - tmp |= GPIO_Pin; - /* Set LCKK bit */ - GPIOx->LCKR = tmp; - /* Reset LCKK bit */ - GPIOx->LCKR = GPIO_Pin; - /* Set LCKK bit */ - GPIOx->LCKR = tmp; - /* Read LCKK bit */ - tmp = GPIOx->LCKR; - /* Read LCKK bit */ - tmp = GPIOx->LCKR; -} - -/** - * @} - */ - -/** @defgroup GPIO_Group2 GPIO Read and Write - * @brief GPIO Read and Write - * -@verbatim - =============================================================================== - ##### GPIO Read and Write ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Reads the specified input port pin. - * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral. - * @note GPIOE is available only for STM32F072. - * @note GPIOD is not available for STM32F031. - * @param GPIO_Pin: specifies the port bit to read. - * @note This parameter can be GPIO_Pin_x where x can be: - * For STM32F051 and STM32F030: (0..15) for GPIOA, GPIOB, GPIOC, (2) for GPIOD and (0..1, 4..7) for GIIOF. - * For STM32F072: (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF. - * For STM32F031: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOF. - * @retval The input port pin value. - */ -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - - if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - return bitstatus; -} - -/** - * @brief Reads the specified input port pin. - * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral. - * @note GPIOE is available only for STM32F072. - * @note GPIOD is not available for STM32F031. - * @retval The input port pin value. - */ -uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - return ((uint16_t)GPIOx->IDR); -} - -/** - * @brief Reads the specified output data port bit. - * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral. - * @note GPIOE is available only for STM32F072. - * @note GPIOD is not available for STM32F031. - * @param GPIO_Pin: Specifies the port bit to read. - * @note This parameter can be GPIO_Pin_x where x can be: - * For STM32F051 and STM32F030: (0..15) for GPIOA, GPIOB, GPIOC, (2) for GPIOD and (0..1, 4..7) for GIIOF. - * For STM32F072: (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF. - * For STM32F031: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOF. - * @retval The output port pin value. - */ -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - - if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - return bitstatus; -} - -/** - * @brief Reads the specified GPIO output data port. - * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral. - * @note GPIOE is available only for STM32F072. - * @note GPIOD is not available for STM32F031. - * @retval GPIO output data port value. - */ -uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - return ((uint16_t)GPIOx->ODR); -} - -/** - * @brief Sets the selected data port bits. - * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral. - * @note GPIOE is available only for STM32F072. - * @note GPIOD is not available for STM32F031. - * @param GPIO_Pin: specifies the port bits to be written. - * @note This parameter can be GPIO_Pin_x where x can be: - * For STM32F051 and STM32F030: (0..15) for GPIOA, GPIOB, GPIOC, (2) for GPIOD and (0..1, 4..7) for GIIOF. - * For STM32F072: (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF. - * For STM32F031: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOF. - * @retval None - */ -void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - GPIOx->BSRR = GPIO_Pin; -} - -/** - * @brief Clears the selected data port bits. - * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral. - * @note GPIOE is available only for STM32F072. - * @note GPIOD is not available for STM32F031. - * @param GPIO_Pin: specifies the port bits to be written. - * @note This parameter can be GPIO_Pin_x where x can be: - * For STM32F051 and STM32F030: (0..15) for GPIOA, GPIOB, GPIOC, (2) for GPIOD and (0..1, 4..7) for GIIOF. - * For STM32F072: (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF. - * For STM32F031: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOF. - * @retval None - */ -void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - GPIOx->BRR = GPIO_Pin; -} - -/** - * @brief Sets or clears the selected data port bit. - * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral. - * @note GPIOE is available only for STM32F072. - * @note GPIOD is not available for STM32F031. - * @param GPIO_Pin: specifies the port bit to be written. - * @param BitVal: specifies the value to be written to the selected bit. - * This parameter can be one of the BitAction enumeration values: - * @arg Bit_RESET: to clear the port pin - * @arg Bit_SET: to set the port pin - * @note This parameter can be GPIO_Pin_x where x can be: - * For STM32F051 and STM32F030: (0..15) for GPIOA, GPIOB, GPIOC, (2) for GPIOD and (0..1, 4..7) for GIIOF. - * For STM32F072: (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF. - * For STM32F031: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOF. - * @retval None - */ -void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - assert_param(IS_GPIO_BIT_ACTION(BitVal)); - - if (BitVal != Bit_RESET) - { - GPIOx->BSRR = GPIO_Pin; - } - else - { - GPIOx->BRR = GPIO_Pin ; - } -} - -/** - * @brief Writes data to the specified GPIO data port. - * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral. - * @note GPIOE is available only for STM32F072. - * @note GPIOD is not available for STM32F031. - * @param PortVal: specifies the value to be written to the port output data register. - * @retval None - */ -void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - GPIOx->ODR = PortVal; -} - -/** - * @} - */ - -/** @defgroup GPIO_Group3 GPIO Alternate functions configuration functions - * @brief GPIO Alternate functions configuration functions - * -@verbatim - =============================================================================== - ##### GPIO Alternate functions configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Writes data to the specified GPIO data port. - * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral. - * @note GPIOC, GPIOD, GPIOE and GPIOF are available only for STM32F072 and STM32F091. - * @param GPIO_PinSource: specifies the pin for the Alternate function. - * This parameter can be GPIO_PinSourcex where x can be (0..15) for GPIOA, GPIOB, GPIOD, GPIOE - * and (0..12) for GPIOC and (0, 2..5, 9..10) for GPIOF. - * @param GPIO_AF: selects the pin to used as Alternate function. - * This parameter can be one of the following value: - * @arg GPIO_AF_0: WKUP, EVENTOUT, TIM15, SPI1, TIM17, MCO, SWDAT, SWCLK, - * TIM14, BOOT, USART1, CEC, IR_OUT, SPI2, TIM3, USART4, - * CAN, USART2, CRS, TIM16, TIM1, TS, USART8 - * @arg GPIO_AF_1: USART2, CEC, TIM3, USART1, USART2, EVENTOUT, I2C1, - * I2C2, TIM15, SPI2, USART3, TS, SPI1, USART7, USART8 - * USART5, USART4, USART6, I2C1 - * @arg GPIO_AF_2: TIM2, TIM1, EVENTOUT, TIM16, TIM17, USB, USART6, USART5, - * USART8, USART7, USART6 - * @arg GPIO_AF_3: TS, I2C1, TIM15, EVENTOUT - * @arg GPIO_AF_4: TIM14, USART4, USART3, CRS, CAN, I2C1, USART5 - * @arg GPIO_AF_5: TIM16, TIM17, TIM15, SPI2, I2C2, USART6, MCO - * @arg GPIO_AF_6: EVENTOUT - * @arg GPIO_AF_7: COMP1 OUT, COMP2 OUT - * @note The pin should already been configured in Alternate Function mode(AF) - * using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - * @note Refer to the Alternate function mapping table in the device datasheet - * for the detailed mapping of the system and peripherals'alternate - * function I/O pins. - * @retval None - */ -void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF) -{ - uint32_t temp = 0x00; - uint32_t temp_2 = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); - assert_param(IS_GPIO_AF(GPIO_AF)); - - temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)); - GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)); - temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp; - GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2; -} - - -/** - * @brief Toggles the specified GPIO pins. NOTE: Imported by EMZ - * @param GPIOx: where x can be (A..H) to select the GPIO peripheral. - * @param GPIO_Pin: Specifies the pins to be toggled. - * @retval None - */ -void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - GPIOx->ODR ^= GPIO_Pin; -} - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_i2c.c b/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_i2c.c deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_i2c.c +++ /dev/null @@ -1,1585 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_i2c.c - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the Inter-Integrated circuit (I2C): - * + Initialization and Configuration - * + Communications handling - * + SMBUS management - * + I2C registers management - * + Data transfers management - * + DMA transfers management - * + Interrupts and flags management - * - * @verbatim - ============================================================================ - ##### How to use this driver ##### - ============================================================================ - [..] - (#) Enable peripheral clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2Cx, ENABLE) - function for I2C1 or I2C2. - (#) Enable SDA, SCL and SMBA (when used) GPIO clocks using - RCC_AHBPeriphClockCmd() function. - (#) Peripherals alternate function: - (++) Connect the pin to the desired peripherals' Alternate - Function (AF) using GPIO_PinAFConfig() function. - (++) Configure the desired pin in alternate function by: - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - (++) Select the type, OpenDrain and speed via - GPIO_PuPd, GPIO_OType and GPIO_Speed members - (++) Call GPIO_Init() function. - (#) Program the Mode, Timing , Own address, Ack and Acknowledged Address - using the I2C_Init() function. - (#) Optionally you can enable/configure the following parameters without - re-initialization (i.e there is no need to call again I2C_Init() function): - (++) Enable the acknowledge feature using I2C_AcknowledgeConfig() function. - (++) Enable the dual addressing mode using I2C_DualAddressCmd() function. - (++) Enable the general call using the I2C_GeneralCallCmd() function. - (++) Enable the clock stretching using I2C_StretchClockCmd() function. - (++) Enable the PEC Calculation using I2C_CalculatePEC() function. - (++) For SMBus Mode: - (+++) Enable the SMBusAlert pin using I2C_SMBusAlertCmd() function. - (#) Enable the NVIC and the corresponding interrupt using the function - I2C_ITConfig() if you need to use interrupt mode. - (#) When using the DMA mode - (++) Configure the DMA using DMA_Init() function. - (++) Active the needed channel Request using I2C_DMACmd() function. - (#) Enable the I2C using the I2C_Cmd() function. - (#) Enable the DMA using the DMA_Cmd() function when using DMA mode in the - transfers. - [..] - (@) When using I2C in Fast Mode Plus, SCL and SDA pin 20mA current drive capability - must be enabled by setting the driving capability control bit in SYSCFG. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_i2c.h" -#include "stm32f0xx_rcc.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup I2C - * @brief I2C driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -#define CR1_CLEAR_MASK ((uint32_t)0x00CFE0FF) /*I2C_AnalogFilter)); - assert_param(IS_I2C_DIGITAL_FILTER(I2C_InitStruct->I2C_DigitalFilter)); - assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode)); - assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1)); - assert_param(IS_I2C_ACK(I2C_InitStruct->I2C_Ack)); - assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress)); - - /* Disable I2Cx Peripheral */ - I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE); - - /*---------------------------- I2Cx FILTERS Configuration ------------------*/ - /* Get the I2Cx CR1 value */ - tmpreg = I2Cx->CR1; - /* Clear I2Cx CR1 register */ - tmpreg &= CR1_CLEAR_MASK; - /* Configure I2Cx: analog and digital filter */ - /* Set ANFOFF bit according to I2C_AnalogFilter value */ - /* Set DFN bits according to I2C_DigitalFilter value */ - tmpreg |= (uint32_t)I2C_InitStruct->I2C_AnalogFilter |(I2C_InitStruct->I2C_DigitalFilter << 8); - - /* Write to I2Cx CR1 */ - I2Cx->CR1 = tmpreg; - - /*---------------------------- I2Cx TIMING Configuration -------------------*/ - /* Configure I2Cx: Timing */ - /* Set TIMINGR bits according to I2C_Timing */ - /* Write to I2Cx TIMING */ - I2Cx->TIMINGR = I2C_InitStruct->I2C_Timing & TIMING_CLEAR_MASK; - - /* Enable I2Cx Peripheral */ - I2Cx->CR1 |= I2C_CR1_PE; - - /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ - /* Clear tmpreg local variable */ - tmpreg = 0; - /* Clear OAR1 register */ - I2Cx->OAR1 = (uint32_t)tmpreg; - /* Clear OAR2 register */ - I2Cx->OAR2 = (uint32_t)tmpreg; - /* Configure I2Cx: Own Address1 and acknowledged address */ - /* Set OA1MODE bit according to I2C_AcknowledgedAddress value */ - /* Set OA1 bits according to I2C_OwnAddress1 value */ - tmpreg = (uint32_t)((uint32_t)I2C_InitStruct->I2C_AcknowledgedAddress | \ - (uint32_t)I2C_InitStruct->I2C_OwnAddress1); - /* Write to I2Cx OAR1 */ - I2Cx->OAR1 = tmpreg; - /* Enable Own Address1 acknowledgement */ - I2Cx->OAR1 |= I2C_OAR1_OA1EN; - - /*---------------------------- I2Cx MODE Configuration ---------------------*/ - /* Configure I2Cx: mode */ - /* Set SMBDEN and SMBHEN bits according to I2C_Mode value */ - tmpreg = I2C_InitStruct->I2C_Mode; - /* Write to I2Cx CR1 */ - I2Cx->CR1 |= tmpreg; - - /*---------------------------- I2Cx ACK Configuration ----------------------*/ - /* Get the I2Cx CR2 value */ - tmpreg = I2Cx->CR2; - /* Clear I2Cx CR2 register */ - tmpreg &= CR2_CLEAR_MASK; - /* Configure I2Cx: acknowledgement */ - /* Set NACK bit according to I2C_Ack value */ - tmpreg |= I2C_InitStruct->I2C_Ack; - /* Write to I2Cx CR2 */ - I2Cx->CR2 = tmpreg; -} - -/** - * @brief Fills each I2C_InitStruct member with its default value. - * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized. - * @retval None - */ -void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) -{ - /*---------------- Reset I2C init structure parameters values --------------*/ - /* Initialize the I2C_Timing member */ - I2C_InitStruct->I2C_Timing = 0; - /* Initialize the I2C_AnalogFilter member */ - I2C_InitStruct->I2C_AnalogFilter = I2C_AnalogFilter_Enable; - /* Initialize the I2C_DigitalFilter member */ - I2C_InitStruct->I2C_DigitalFilter = 0; - /* Initialize the I2C_Mode member */ - I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; - /* Initialize the I2C_OwnAddress1 member */ - I2C_InitStruct->I2C_OwnAddress1 = 0; - /* Initialize the I2C_Ack member */ - I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; - /* Initialize the I2C_AcknowledgedAddress member */ - I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; -} - -/** - * @brief Enables or disables the specified I2C peripheral. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2Cx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C peripheral */ - I2Cx->CR1 |= I2C_CR1_PE; - } - else - { - /* Disable the selected I2C peripheral */ - I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE); - } -} - -/** - * @brief Enables or disables the specified I2C software reset. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @retval None - */ -void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - /* Disable peripheral */ - I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE); - - /* Perform a dummy read to delay the disable of peripheral for minimum - 3 APB clock cycles to perform the software reset functionality */ - *(__IO uint32_t *)(uint32_t)I2Cx; - - /* Enable peripheral */ - I2Cx->CR1 |= I2C_CR1_PE; -} - -/** - * @brief Enables or disables the specified I2C interrupts. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg I2C_IT_ERRI: Error interrupt mask - * @arg I2C_IT_TCI: Transfer Complete interrupt mask - * @arg I2C_IT_STOPI: Stop Detection interrupt mask - * @arg I2C_IT_NACKI: Not Acknowledge received interrupt mask - * @arg I2C_IT_ADDRI: Address Match interrupt mask - * @arg I2C_IT_RXI: RX interrupt mask - * @arg I2C_IT_TXI: TX interrupt mask - * @param NewState: new state of the specified I2C interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_ITConfig(I2C_TypeDef* I2Cx, uint32_t I2C_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_I2C_CONFIG_IT(I2C_IT)); - - if (NewState != DISABLE) - { - /* Enable the selected I2C interrupts */ - I2Cx->CR1 |= I2C_IT; - } - else - { - /* Disable the selected I2C interrupts */ - I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_IT); - } -} - -/** - * @brief Enables or disables the I2C Clock stretching. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2Cx Clock stretching. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable clock stretching */ - I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_NOSTRETCH); - } - else - { - /* Disable clock stretching */ - I2Cx->CR1 |= I2C_CR1_NOSTRETCH; - } -} - -/** - * @brief Enables or disables I2C wakeup from stop mode. - * This function is not applicable for STM32F030 devices. - * @param I2Cx: where x can be 1 to select the I2C peripheral. - * @param NewState: new state of the I2Cx stop mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_StopModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_1_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable wakeup from stop mode */ - I2Cx->CR1 |= I2C_CR1_WUPEN; - } - else - { - /* Disable wakeup from stop mode */ - I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_WUPEN); - } -} - -/** - * @brief Enables or disables the I2C own address 2. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C own address 2. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable own address 2 */ - I2Cx->OAR2 |= I2C_OAR2_OA2EN; - } - else - { - /* Disable own address 2 */ - I2Cx->OAR2 &= (uint32_t)~((uint32_t)I2C_OAR2_OA2EN); - } -} - -/** - * @brief Configures the I2C slave own address 2 and mask. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param Address: specifies the slave address to be programmed. - * @param Mask: specifies own address 2 mask to be programmed. - * This parameter can be one of the following values: - * @arg I2C_OA2_NoMask: no mask. - * @arg I2C_OA2_Mask01: OA2[1] is masked and don't care. - * @arg I2C_OA2_Mask02: OA2[2:1] are masked and don't care. - * @arg I2C_OA2_Mask03: OA2[3:1] are masked and don't care. - * @arg I2C_OA2_Mask04: OA2[4:1] are masked and don't care. - * @arg I2C_OA2_Mask05: OA2[5:1] are masked and don't care. - * @arg I2C_OA2_Mask06: OA2[6:1] are masked and don't care. - * @arg I2C_OA2_Mask07: OA2[7:1] are masked and don't care. - * @retval None - */ -void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Mask) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_OWN_ADDRESS2(Address)); - assert_param(IS_I2C_OWN_ADDRESS2_MASK(Mask)); - - /* Get the old register value */ - tmpreg = I2Cx->OAR2; - - /* Reset I2Cx OA2 bit [7:1] and OA2MSK bit [1:0] */ - tmpreg &= (uint32_t)~((uint32_t)(I2C_OAR2_OA2 | I2C_OAR2_OA2MSK)); - - /* Set I2Cx SADD */ - tmpreg |= (uint32_t)(((uint32_t)Address & I2C_OAR2_OA2) | \ - (((uint32_t)Mask << 8) & I2C_OAR2_OA2MSK)) ; - - /* Store the new register value */ - I2Cx->OAR2 = tmpreg; -} - -/** - * @brief Enables or disables the I2C general call mode. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C general call mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable general call mode */ - I2Cx->CR1 |= I2C_CR1_GCEN; - } - else - { - /* Disable general call mode */ - I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_GCEN); - } -} - -/** - * @brief Enables or disables the I2C slave byte control. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C slave byte control. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_SlaveByteControlCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable slave byte control */ - I2Cx->CR1 |= I2C_CR1_SBC; - } - else - { - /* Disable slave byte control */ - I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_SBC); - } -} - -/** - * @brief Configures the slave address to be transmitted after start generation. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param Address: specifies the slave address to be programmed. - * @note This function should be called before generating start condition. - * @retval None - */ -void I2C_SlaveAddressConfig(I2C_TypeDef* I2Cx, uint16_t Address) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_SLAVE_ADDRESS(Address)); - - /* Get the old register value */ - tmpreg = I2Cx->CR2; - - /* Reset I2Cx SADD bit [9:0] */ - tmpreg &= (uint32_t)~((uint32_t)I2C_CR2_SADD); - - /* Set I2Cx SADD */ - tmpreg |= (uint32_t)((uint32_t)Address & I2C_CR2_SADD); - - /* Store the new register value */ - I2Cx->CR2 = tmpreg; -} - -/** - * @brief Enables or disables the I2C 10-bit addressing mode for the master. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C 10-bit addressing mode. - * This parameter can be: ENABLE or DISABLE. - * @note This function should be called before generating start condition. - * @retval None - */ -void I2C_10BitAddressingModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable 10-bit addressing mode */ - I2Cx->CR2 |= I2C_CR2_ADD10; - } - else - { - /* Disable 10-bit addressing mode */ - I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_ADD10); - } -} - -/** - * @} - */ - - -/** @defgroup I2C_Group2 Communications handling functions - * @brief Communications handling functions - * -@verbatim - =============================================================================== - ##### Communications handling functions ##### - =============================================================================== - [..] This section provides a set of functions that handles I2C communication. - - [..] Automatic End mode is enabled using I2C_AutoEndCmd() function. When Reload - mode is enabled via I2C_ReloadCmd() AutoEnd bit has no effect. - - [..] I2C_NumberOfBytesConfig() function set the number of bytes to be transferred, - this configuration should be done before generating start condition in master - mode. - - [..] When switching from master write operation to read operation in 10Bit addressing - mode, master can only sends the 1st 7 bits of the 10 bit address, followed by - Read direction by enabling HEADR bit using I2C_10BitAddressHeader() function. - - [..] In master mode, when transferring more than 255 bytes Reload mode should be used - to handle communication. In the first phase of transfer, Nbytes should be set to - 255. After transferring these bytes TCR flag is set and I2C_TransferHandling() - function should be called to handle remaining communication. - - [..] In master mode, when software end mode is selected when all data is transferred - TC flag is set I2C_TransferHandling() function should be called to generate STOP - or generate ReStart. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the I2C automatic end mode (stop condition is - * automatically sent when nbytes data are transferred). - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C automatic end mode. - * This parameter can be: ENABLE or DISABLE. - * @note This function has effect if Reload mode is disabled. - * @retval None - */ -void I2C_AutoEndCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable Auto end mode */ - I2Cx->CR2 |= I2C_CR2_AUTOEND; - } - else - { - /* Disable Auto end mode */ - I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_AUTOEND); - } -} - -/** - * @brief Enables or disables the I2C nbytes reload mode. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the nbytes reload mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_ReloadCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable Auto Reload mode */ - I2Cx->CR2 |= I2C_CR2_RELOAD; - } - else - { - /* Disable Auto Reload mode */ - I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_RELOAD); - } -} - -/** - * @brief Configures the number of bytes to be transmitted/received. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param Number_Bytes: specifies the number of bytes to be programmed. - * @retval None - */ -void I2C_NumberOfBytesConfig(I2C_TypeDef* I2Cx, uint8_t Number_Bytes) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - /* Get the old register value */ - tmpreg = I2Cx->CR2; - - /* Reset I2Cx Nbytes bit [7:0] */ - tmpreg &= (uint32_t)~((uint32_t)I2C_CR2_NBYTES); - - /* Set I2Cx Nbytes */ - tmpreg |= (uint32_t)(((uint32_t)Number_Bytes << 16 ) & I2C_CR2_NBYTES); - - /* Store the new register value */ - I2Cx->CR2 = tmpreg; -} - -/** - * @brief Configures the type of transfer request for the master. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_Direction: specifies the transfer request direction to be programmed. - * This parameter can be one of the following values: - * @arg I2C_Direction_Transmitter: Master request a write transfer - * @arg I2C_Direction_Receiver: Master request a read transfer - * @retval None - */ -void I2C_MasterRequestConfig(I2C_TypeDef* I2Cx, uint16_t I2C_Direction) -{ -/* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_DIRECTION(I2C_Direction)); - - /* Test on the direction to set/reset the read/write bit */ - if (I2C_Direction == I2C_Direction_Transmitter) - { - /* Request a write Transfer */ - I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_RD_WRN); - } - else - { - /* Request a read Transfer */ - I2Cx->CR2 |= I2C_CR2_RD_WRN; - } -} - -/** - * @brief Generates I2Cx communication START condition. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C START condition generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Generate a START condition */ - I2Cx->CR2 |= I2C_CR2_START; - } - else - { - /* Disable the START condition generation */ - I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_START); - } -} - -/** - * @brief Generates I2Cx communication STOP condition. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C STOP condition generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Generate a STOP condition */ - I2Cx->CR2 |= I2C_CR2_STOP; - } - else - { - /* Disable the STOP condition generation */ - I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_STOP); - } -} - -/** - * @brief Enables or disables the I2C 10-bit header only mode with read direction. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C 10-bit header only mode. - * This parameter can be: ENABLE or DISABLE. - * @note This mode can be used only when switching from master transmitter mode - * to master receiver mode. - * @retval None - */ -void I2C_10BitAddressHeaderCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable 10-bit header only mode */ - I2Cx->CR2 |= I2C_CR2_HEAD10R; - } - else - { - /* Disable 10-bit header only mode */ - I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_HEAD10R); - } -} - -/** - * @brief Generates I2C communication Acknowledge. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the Acknowledge. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable ACK generation */ - I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_NACK); - } - else - { - /* Enable NACK generation */ - I2Cx->CR2 |= I2C_CR2_NACK; - } -} - -/** - * @brief Returns the I2C slave matched address . - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @retval The value of the slave matched address . - */ -uint8_t I2C_GetAddressMatched(I2C_TypeDef* I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - /* Return the slave matched address in the SR1 register */ - return (uint8_t)(((uint32_t)I2Cx->ISR & I2C_ISR_ADDCODE) >> 16) ; -} - -/** - * @brief Returns the I2C slave received request. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @retval The value of the received request. - */ -uint16_t I2C_GetTransferDirection(I2C_TypeDef* I2Cx) -{ - uint32_t tmpreg = 0; - uint16_t direction = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - /* Return the slave matched address in the SR1 register */ - tmpreg = (uint32_t)(I2Cx->ISR & I2C_ISR_DIR); - - /* If write transfer is requested */ - if (tmpreg == 0) - { - /* write transfer is requested */ - direction = I2C_Direction_Transmitter; - } - else - { - /* Read transfer is requested */ - direction = I2C_Direction_Receiver; - } - return direction; -} - -/** - * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param Address: specifies the slave address to be programmed. - * @param Number_Bytes: specifies the number of bytes to be programmed. - * This parameter must be a value between 0 and 255. - * @param ReloadEndMode: new state of the I2C START condition generation. - * This parameter can be one of the following values: - * @arg I2C_Reload_Mode: Enable Reload mode . - * @arg I2C_AutoEnd_Mode: Enable Automatic end mode. - * @arg I2C_SoftEnd_Mode: Enable Software end mode. - * @param StartStopMode: new state of the I2C START condition generation. - * This parameter can be one of the following values: - * @arg I2C_No_StartStop: Don't Generate stop and start condition. - * @arg I2C_Generate_Stop: Generate stop condition (Number_Bytes should be set to 0). - * @arg I2C_Generate_Start_Read: Generate Restart for read request. - * @arg I2C_Generate_Start_Write: Generate Restart for write request. - * @retval None - */ -void I2C_TransferHandling(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_SLAVE_ADDRESS(Address)); - assert_param(IS_RELOAD_END_MODE(ReloadEndMode)); - assert_param(IS_START_STOP_MODE(StartStopMode)); - - /* Get the CR2 register value */ - tmpreg = I2Cx->CR2; - - /* clear tmpreg specific bits */ - tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP)); - - /* update tmpreg */ - tmpreg |= (uint32_t)(((uint32_t)Address & I2C_CR2_SADD) | (((uint32_t)Number_Bytes << 16 ) & I2C_CR2_NBYTES) | \ - (uint32_t)ReloadEndMode | (uint32_t)StartStopMode); - - /* update CR2 register */ - I2Cx->CR2 = tmpreg; -} - -/** - * @} - */ - - -/** @defgroup I2C_Group3 SMBUS management functions - * @brief SMBUS management functions - * -@verbatim - =============================================================================== - ##### SMBUS management functions ##### - =============================================================================== - [..] This section provides a set of functions that handles SMBus communication - and timeouts detection. - - [..] The SMBus Device default address (0b1100 001) is enabled by calling I2C_Init() - function and setting I2C_Mode member of I2C_InitTypeDef() structure to - I2C_Mode_SMBusDevice. - - [..] The SMBus Host address (0b0001 000) is enabled by calling I2C_Init() - function and setting I2C_Mode member of I2C_InitTypeDef() structure to - I2C_Mode_SMBusHost. - - [..] The Alert Response Address (0b0001 100) is enabled using I2C_SMBusAlertCmd() - function. - - [..] To detect cumulative SCL stretch in master and slave mode, TIMEOUTB should be - configured (in accordance to SMBus specification) using I2C_TimeoutBConfig() - function then I2C_ExtendedClockTimeoutCmd() function should be called to enable - the detection. - - [..] SCL low timeout is detected by configuring TIMEOUTB using I2C_TimeoutBConfig() - function followed by the call of I2C_ClockTimeoutCmd(). When adding to this - procedure the call of I2C_IdleClockTimeoutCmd() function, Bus Idle condition - (both SCL and SDA high) is detected also. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables I2C SMBus alert. - * @param I2Cx: where x can be 1 to select the I2C peripheral. - * @param NewState: new state of the I2Cx SMBus alert. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_SMBusAlertCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_1_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable SMBus alert */ - I2Cx->CR1 |= I2C_CR1_ALERTEN; - } - else - { - /* Disable SMBus alert */ - I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_ALERTEN); - } -} - -/** - * @brief Enables or disables I2C Clock Timeout (SCL Timeout detection). - * @param I2Cx: where x can be 1 to select the I2C peripheral. - * @param NewState: new state of the I2Cx clock Timeout. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_ClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_1_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable Clock Timeout */ - I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TIMOUTEN; - } - else - { - /* Disable Clock Timeout */ - I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMOUTEN); - } -} - -/** - * @brief Enables or disables I2C Extended Clock Timeout (SCL cumulative Timeout detection). - * @param I2Cx: where x can be 1 to select the I2C peripheral. - * @param NewState: new state of the I2Cx Extended clock Timeout. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_ExtendedClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_1_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable Clock Timeout */ - I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TEXTEN; - } - else - { - /* Disable Clock Timeout */ - I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TEXTEN); - } -} - -/** - * @brief Enables or disables I2C Idle Clock Timeout (Bus idle SCL and SDA - * high detection). - * @param I2Cx: where x can be 1 to select the I2C peripheral. - * @param NewState: new state of the I2Cx Idle clock Timeout. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_IdleClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_1_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable Clock Timeout */ - I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TIDLE; - } - else - { - /* Disable Clock Timeout */ - I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIDLE); - } -} - -/** - * @brief Configures the I2C Bus Timeout A (SCL Timeout when TIDLE = 0 or Bus - * idle SCL and SDA high when TIDLE = 1). - * @param I2Cx: where x can be 1 to select the I2C peripheral. - * @param Timeout: specifies the TimeoutA to be programmed. - * @retval None - */ -void I2C_TimeoutAConfig(I2C_TypeDef* I2Cx, uint16_t Timeout) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_I2C_1_PERIPH(I2Cx)); - assert_param(IS_I2C_TIMEOUT(Timeout)); - - /* Get the old register value */ - tmpreg = I2Cx->TIMEOUTR; - - /* Reset I2Cx TIMEOUTA bit [11:0] */ - tmpreg &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMEOUTA); - - /* Set I2Cx TIMEOUTA */ - tmpreg |= (uint32_t)((uint32_t)Timeout & I2C_TIMEOUTR_TIMEOUTA) ; - - /* Store the new register value */ - I2Cx->TIMEOUTR = tmpreg; -} - -/** - * @brief Configures the I2C Bus Timeout B (SCL cumulative Timeout). - * @param I2Cx: where x can be 1 to select the I2C peripheral. - * @param Timeout: specifies the TimeoutB to be programmed. - * @retval None - */ -void I2C_TimeoutBConfig(I2C_TypeDef* I2Cx, uint16_t Timeout) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_I2C_1_PERIPH(I2Cx)); - assert_param(IS_I2C_TIMEOUT(Timeout)); - - /* Get the old register value */ - tmpreg = I2Cx->TIMEOUTR; - - /* Reset I2Cx TIMEOUTB bit [11:0] */ - tmpreg &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMEOUTB); - - /* Set I2Cx TIMEOUTB */ - tmpreg |= (uint32_t)(((uint32_t)Timeout << 16) & I2C_TIMEOUTR_TIMEOUTB) ; - - /* Store the new register value */ - I2Cx->TIMEOUTR = tmpreg; -} - -/** - * @brief Enables or disables I2C PEC calculation. - * @param I2Cx: where x can be 1 to select the I2C peripheral. - * @param NewState: new state of the I2Cx PEC calculation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_1_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable PEC calculation */ - I2Cx->CR1 |= I2C_CR1_PECEN; - } - else - { - /* Disable PEC calculation */ - I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PECEN); - } -} - -/** - * @brief Enables or disables I2C PEC transmission/reception request. - * @param I2Cx: where x can be 1 to select the I2C peripheral. - * @param NewState: new state of the I2Cx PEC request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_PECRequestCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_1_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable PEC transmission/reception request */ - I2Cx->CR2 |= I2C_CR2_PECBYTE; - } - else - { - /* Disable PEC transmission/reception request */ - I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_PECBYTE); - } -} - -/** - * @brief Returns the I2C PEC. - * @param I2Cx: where x can be 1 to select the I2C peripheral. - * @retval The value of the PEC . - */ -uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_1_PERIPH(I2Cx)); - - /* Return the slave matched address in the SR1 register */ - return (uint8_t)((uint32_t)I2Cx->PECR & I2C_PECR_PEC); -} - -/** - * @} - */ - - -/** @defgroup I2C_Group4 I2C registers management functions - * @brief I2C registers management functions - * -@verbatim - =============================================================================== - ##### I2C registers management functions ##### - =============================================================================== - [..] This section provides a functions that allow user the management of - I2C registers. - -@endverbatim - * @{ - */ - - /** - * @brief Reads the specified I2C register and returns its value. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_Register: specifies the register to read. - * This parameter can be one of the following values: - * @arg I2C_Register_CR1: CR1 register. - * @arg I2C_Register_CR2: CR2 register. - * @arg I2C_Register_OAR1: OAR1 register. - * @arg I2C_Register_OAR2: OAR2 register. - * @arg I2C_Register_TIMINGR: TIMING register. - * @arg I2C_Register_TIMEOUTR: TIMEOUTR register. - * @arg I2C_Register_ISR: ISR register. - * @arg I2C_Register_ICR: ICR register. - * @arg I2C_Register_PECR: PECR register. - * @arg I2C_Register_RXDR: RXDR register. - * @arg I2C_Register_TXDR: TXDR register. - * @retval The value of the read register. - */ -uint32_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_REGISTER(I2C_Register)); - - tmp = (uint32_t)I2Cx; - tmp += I2C_Register; - - /* Return the selected register value */ - return (*(__IO uint32_t *) tmp); -} - -/** - * @} - */ - -/** @defgroup I2C_Group5 Data transfers management functions - * @brief Data transfers management functions - * -@verbatim - =============================================================================== - ##### Data transfers management functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to manage - the I2C data transfers. - - [..] The read access of the I2C_RXDR register can be done using - the I2C_ReceiveData() function and returns the received value. - Whereas a write access to the I2C_TXDR can be done using I2C_SendData() - function and stores the written data into TXDR. -@endverbatim - * @{ - */ - -/** - * @brief Sends a data byte through the I2Cx peripheral. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param Data: Byte to be transmitted.. - * @retval None - */ -void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - /* Write in the DR register the data to be sent */ - I2Cx->TXDR = (uint8_t)Data; -} - -/** - * @brief Returns the most recent received data by the I2Cx peripheral. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @retval The value of the received data. - */ -uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - /* Return the data in the DR register */ - return (uint8_t)I2Cx->RXDR; -} - -/** - * @} - */ - - -/** @defgroup I2C_Group6 DMA transfers management functions - * @brief DMA transfers management functions - * -@verbatim - =============================================================================== - ##### DMA transfers management functions ##### - =============================================================================== - [..] This section provides two functions that can be used only in DMA mode. - [..] In DMA Mode, the I2C communication can be managed by 2 DMA Channel - requests: - (#) I2C_DMAReq_Tx: specifies the Tx buffer DMA transfer request. - (#) I2C_DMAReq_Rx: specifies the Rx buffer DMA transfer request. - [..] In this Mode it is advised to use the following function: - (+) I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState); -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the I2C DMA interface. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_DMAReq: specifies the I2C DMA transfer request to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg I2C_DMAReq_Tx: Tx DMA transfer request - * @arg I2C_DMAReq_Rx: Rx DMA transfer request - * @param NewState: new state of the selected I2C DMA transfer request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_I2C_DMA_REQ(I2C_DMAReq)); - - if (NewState != DISABLE) - { - /* Enable the selected I2C DMA requests */ - I2Cx->CR1 |= I2C_DMAReq; - } - else - { - /* Disable the selected I2C DMA requests */ - I2Cx->CR1 &= (uint32_t)~I2C_DMAReq; - } -} -/** - * @} - */ - - -/** @defgroup I2C_Group7 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - [..] This section provides functions allowing to configure the I2C Interrupts - sources and check or clear the flags or pending bits status. - The user should identify which mode will be used in his application to manage - the communication: Polling mode, Interrupt mode or DMA mode(refer I2C_Group6). - - *** Polling Mode *** - ==================== - [..] In Polling Mode, the I2C communication can be managed by 15 flags: - (#) I2C_FLAG_TXE: to indicate the status of Transmit data register empty flag. - (#) I2C_FLAG_TXIS: to indicate the status of Transmit interrupt status flag . - (#) I2C_FLAG_RXNE: to indicate the status of Receive data register not empty flag. - (#) I2C_FLAG_ADDR: to indicate the status of Address matched flag (slave mode). - (#) I2C_FLAG_NACKF: to indicate the status of NACK received flag. - (#) I2C_FLAG_STOPF: to indicate the status of STOP detection flag. - (#) I2C_FLAG_TC: to indicate the status of Transfer complete flag(master mode). - (#) I2C_FLAG_TCR: to indicate the status of Transfer complete reload flag. - (#) I2C_FLAG_BERR: to indicate the status of Bus error flag. - (#) I2C_FLAG_ARLO: to indicate the status of Arbitration lost flag. - (#) I2C_FLAG_OVR: to indicate the status of Overrun/Underrun flag. - (#) I2C_FLAG_PECERR: to indicate the status of PEC error in reception flag. - (#) I2C_FLAG_TIMEOUT: to indicate the status of Timeout or Tlow detection flag. - (#) I2C_FLAG_ALERT: to indicate the status of SMBus Alert flag. - (#) I2C_FLAG_BUSY: to indicate the status of Bus busy flag. - - [..] In this Mode it is advised to use the following functions: - (+) FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); - (+) void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); - - [..] - (@)Do not use the BUSY flag to handle each data transmission or reception.It is - better to use the TXIS and RXNE flags instead. - - *** Interrupt Mode *** - ====================== - [..] In Interrupt Mode, the I2C communication can be managed by 7 interrupt sources - and 15 pending bits: - [..] Interrupt Source: - (#) I2C_IT_ERRI: specifies the interrupt source for the Error interrupt. - (#) I2C_IT_TCI: specifies the interrupt source for the Transfer Complete interrupt. - (#) I2C_IT_STOPI: specifies the interrupt source for the Stop Detection interrupt. - (#) I2C_IT_NACKI: specifies the interrupt source for the Not Acknowledge received interrupt. - (#) I2C_IT_ADDRI: specifies the interrupt source for the Address Match interrupt. - (#) I2C_IT_RXI: specifies the interrupt source for the RX interrupt. - (#) I2C_IT_TXI: specifies the interrupt source for the TX interrupt. - - [..] Pending Bits: - (#) I2C_IT_TXIS: to indicate the status of Transmit interrupt status flag. - (#) I2C_IT_RXNE: to indicate the status of Receive data register not empty flag. - (#) I2C_IT_ADDR: to indicate the status of Address matched flag (slave mode). - (#) I2C_IT_NACKF: to indicate the status of NACK received flag. - (#) I2C_IT_STOPF: to indicate the status of STOP detection flag. - (#) I2C_IT_TC: to indicate the status of Transfer complete flag (master mode). - (#) I2C_IT_TCR: to indicate the status of Transfer complete reload flag. - (#) I2C_IT_BERR: to indicate the status of Bus error flag. - (#) I2C_IT_ARLO: to indicate the status of Arbitration lost flag. - (#) I2C_IT_OVR: to indicate the status of Overrun/Underrun flag. - (#) I2C_IT_PECERR: to indicate the status of PEC error in reception flag. - (#) I2C_IT_TIMEOUT: to indicate the status of Timeout or Tlow detection flag. - (#) I2C_IT_ALERT: to indicate the status of SMBus Alert flag. - - [..] In this Mode it is advised to use the following functions: - (+) void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); - (+) ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); - -@endverbatim - * @{ - */ - -/** - * @brief Checks whether the specified I2C flag is set or not. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg I2C_FLAG_TXE: Transmit data register empty - * @arg I2C_FLAG_TXIS: Transmit interrupt status - * @arg I2C_FLAG_RXNE: Receive data register not empty - * @arg I2C_FLAG_ADDR: Address matched (slave mode) - * @arg I2C_FLAG_NACKF: NACK received flag - * @arg I2C_FLAG_STOPF: STOP detection flag - * @arg I2C_FLAG_TC: Transfer complete (master mode) - * @arg I2C_FLAG_TCR: Transfer complete reload - * @arg I2C_FLAG_BERR: Bus error - * @arg I2C_FLAG_ARLO: Arbitration lost - * @arg I2C_FLAG_OVR: Overrun/Underrun - * @arg I2C_FLAG_PECERR: PEC error in reception - * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag - * @arg I2C_FLAG_ALERT: SMBus Alert - * @arg I2C_FLAG_BUSY: Bus busy - * @retval The new state of I2C_FLAG (SET or RESET). - */ -FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) -{ - uint32_t tmpreg = 0; - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_GET_FLAG(I2C_FLAG)); - - /* Get the ISR register value */ - tmpreg = I2Cx->ISR; - - /* Get flag status */ - tmpreg &= I2C_FLAG; - - if(tmpreg != 0) - { - /* I2C_FLAG is set */ - bitstatus = SET; - } - else - { - /* I2C_FLAG is reset */ - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the I2Cx's pending flags. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg I2C_FLAG_ADDR: Address matched (slave mode) - * @arg I2C_FLAG_NACKF: NACK received flag - * @arg I2C_FLAG_STOPF: STOP detection flag - * @arg I2C_FLAG_BERR: Bus error - * @arg I2C_FLAG_ARLO: Arbitration lost - * @arg I2C_FLAG_OVR: Overrun/Underrun - * @arg I2C_FLAG_PECERR: PEC error in reception - * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag - * @arg I2C_FLAG_ALERT: SMBus Alert - * @retval The new state of I2C_FLAG (SET or RESET). - */ -void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG)); - - /* Clear the selected flag */ - I2Cx->ICR = I2C_FLAG; - } - -/** - * @brief Checks whether the specified I2C interrupt has occurred or not. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_IT: specifies the interrupt source to check. - * This parameter can be one of the following values: - * @arg I2C_IT_TXIS: Transmit interrupt status - * @arg I2C_IT_RXNE: Receive data register not empty - * @arg I2C_IT_ADDR: Address matched (slave mode) - * @arg I2C_IT_NACKF: NACK received flag - * @arg I2C_IT_STOPF: STOP detection flag - * @arg I2C_IT_TC: Transfer complete (master mode) - * @arg I2C_IT_TCR: Transfer complete reload - * @arg I2C_IT_BERR: Bus error - * @arg I2C_IT_ARLO: Arbitration lost - * @arg I2C_IT_OVR: Overrun/Underrun - * @arg I2C_IT_PECERR: PEC error in reception - * @arg I2C_IT_TIMEOUT: Timeout or Tlow detection flag - * @arg I2C_IT_ALERT: SMBus Alert - * @retval The new state of I2C_IT (SET or RESET). - */ -ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT) -{ - uint32_t tmpreg = 0; - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_GET_IT(I2C_IT)); - - /* Check if the interrupt source is enabled or not */ - /* If Error interrupt */ - if ((uint32_t)(I2C_IT & ERROR_IT_MASK)) - { - enablestatus = (uint32_t)((I2C_CR1_ERRIE) & (I2Cx->CR1)); - } - /* If TC interrupt */ - else if ((uint32_t)(I2C_IT & TC_IT_MASK)) - { - enablestatus = (uint32_t)((I2C_CR1_TCIE) & (I2Cx->CR1)); - } - else - { - enablestatus = (uint32_t)((I2C_IT) & (I2Cx->CR1)); - } - - /* Get the ISR register value */ - tmpreg = I2Cx->ISR; - - /* Get flag status */ - tmpreg &= I2C_IT; - - /* Check the status of the specified I2C flag */ - if((tmpreg != RESET) && enablestatus) - { - /* I2C_IT is set */ - bitstatus = SET; - } - else - { - /* I2C_IT is reset */ - bitstatus = RESET; - } - - /* Return the I2C_IT status */ - return bitstatus; -} - -/** - * @brief Clears the I2Cx's interrupt pending bits. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg I2C_IT_ADDR: Address matched (slave mode) - * @arg I2C_IT_NACKF: NACK received flag - * @arg I2C_IT_STOPF: STOP detection flag - * @arg I2C_IT_BERR: Bus error - * @arg I2C_IT_ARLO: Arbitration lost - * @arg I2C_IT_OVR: Overrun/Underrun - * @arg I2C_IT_PECERR: PEC error in reception - * @arg I2C_IT_TIMEOUT: Timeout or Tlow detection flag - * @arg I2C_IT_ALERT: SMBus Alert - * @retval The new state of I2C_IT (SET or RESET). - */ -void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_CLEAR_IT(I2C_IT)); - - /* Clear the selected flag */ - I2Cx->ICR = I2C_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_iwdg.c b/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_iwdg.c deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_iwdg.c +++ /dev/null @@ -1,293 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_iwdg.c - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the Independent watchdog (IWDG) peripheral: - * + Prescaler and Counter configuration - * + IWDG activation - * + Flag management - * - * @verbatim - * - ============================================================================== - ##### IWDG features ##### - ============================================================================== - [..] The IWDG can be started by either software or hardware (configurable - through option byte). - - [..] The IWDG is clocked by its own dedicated low-speed clock (LSI) and - thus stays active even if the main clock fails. - Once the IWDG is started, the LSI is forced ON and cannot be disabled - (LSI cannot be disabled too), and the counter starts counting down from - the reset value of 0xFFF. When it reaches the end of count value (0x000) - a system reset is generated. - The IWDG counter should be reloaded at regular intervals to prevent - an MCU reset. - - [..] The IWDG is implemented in the VDD voltage domain that is still functional - in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY). - - [..] IWDGRST flag in RCC_CSR register can be used to inform when a IWDG - reset occurs. - - [..] Min-max timeout value @40KHz (LSI): ~0.1ms / ~28.3s - The IWDG timeout may vary due to LSI frequency dispersion. STM32F0xx - devices provide the capability to measure the LSI frequency (LSI clock - should be seleted as RTC clock which is internally connected to TIM10 CH1 - input capture). The measured value can be used to have an IWDG timeout with - an acceptable accuracy. - For more information, please refer to the STM32F0xx Reference manual. - - ##### How to use this driver ##### - ============================================================================== - [..] This driver allows to use IWDG peripheral with either window option enabled - or disabled. To do so follow one of the two procedures below. - (#) Window option is enabled: - (++) Start the IWDG using IWDG_Enable() function, when the IWDG is used - in software mode (no need to enable the LSI, it will be enabled - by hardware). - (++) Enable write access to IWDG_PR and IWDG_RLR registers using - IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function. - (++) Configure the IWDG prescaler using IWDG_SetPrescaler() function. - (++) Configure the IWDG counter value using IWDG_SetReload() function. - This value will be loaded in the IWDG counter each time the counter - is reloaded, then the IWDG will start counting down from this value. - (++) Wait for the IWDG registers to be updated using IWDG_GetFlagStatus() function. - (++) Configure the IWDG refresh window using IWDG_SetWindowValue() function. - - (#) Window option is disabled: - (++) Enable write access to IWDG_PR and IWDG_RLR registers using - IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function. - (++) Configure the IWDG prescaler using IWDG_SetPrescaler() function. - (++) Configure the IWDG counter value using IWDG_SetReload() function. - This value will be loaded in the IWDG counter each time the counter - is reloaded, then the IWDG will start counting down from this value. - (++) Wait for the IWDG registers to be updated using IWDG_GetFlagStatus() function. - (++) reload the IWDG counter at regular intervals during normal operation - to prevent an MCU reset, using IWDG_ReloadCounter() function. - (++) Start the IWDG using IWDG_Enable() function, when the IWDG is used - in software mode (no need to enable the LSI, it will be enabled - by hardware). - - @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_iwdg.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup IWDG - * @brief IWDG driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* ---------------------- IWDG registers bit mask ----------------------------*/ -/* KR register bit mask */ -#define KR_KEY_RELOAD ((uint16_t)0xAAAA) -#define KR_KEY_ENABLE ((uint16_t)0xCCCC) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup IWDG_Private_Functions - * @{ - */ - -/** @defgroup IWDG_Group1 Prescaler and Counter configuration functions - * @brief Prescaler and Counter configuration functions - * -@verbatim - ============================================================================== - ##### Prescaler and Counter configuration functions ##### - ============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers. - * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers. - * This parameter can be one of the following values: - * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers - * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers - * @retval None - */ -void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) -{ - /* Check the parameters */ - assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess)); - IWDG->KR = IWDG_WriteAccess; -} - -/** - * @brief Sets IWDG Prescaler value. - * @param IWDG_Prescaler: specifies the IWDG Prescaler value. - * This parameter can be one of the following values: - * @arg IWDG_Prescaler_4: IWDG prescaler set to 4 - * @arg IWDG_Prescaler_8: IWDG prescaler set to 8 - * @arg IWDG_Prescaler_16: IWDG prescaler set to 16 - * @arg IWDG_Prescaler_32: IWDG prescaler set to 32 - * @arg IWDG_Prescaler_64: IWDG prescaler set to 64 - * @arg IWDG_Prescaler_128: IWDG prescaler set to 128 - * @arg IWDG_Prescaler_256: IWDG prescaler set to 256 - * @retval None - */ -void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) -{ - /* Check the parameters */ - assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler)); - IWDG->PR = IWDG_Prescaler; -} - -/** - * @brief Sets IWDG Reload value. - * @param Reload: specifies the IWDG Reload value. - * This parameter must be a number between 0 and 0x0FFF. - * @retval None - */ -void IWDG_SetReload(uint16_t Reload) -{ - /* Check the parameters */ - assert_param(IS_IWDG_RELOAD(Reload)); - IWDG->RLR = Reload; -} - -/** - * @brief Reloads IWDG counter with value defined in the reload register - * (write access to IWDG_PR and IWDG_RLR registers disabled). - * @param None - * @retval None - */ -void IWDG_ReloadCounter(void) -{ - IWDG->KR = KR_KEY_RELOAD; -} - - -/** - * @brief Sets the IWDG window value. - * @param WindowValue: specifies the window value to be compared to the downcounter. - * @retval None - */ -void IWDG_SetWindowValue(uint16_t WindowValue) -{ - /* Check the parameters */ - assert_param(IS_IWDG_WINDOW_VALUE(WindowValue)); - IWDG->WINR = WindowValue; -} - -/** - * @} - */ - -/** @defgroup IWDG_Group2 IWDG activation function - * @brief IWDG activation function - * -@verbatim - ============================================================================== - ##### IWDG activation function ##### - ============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). - * @param None - * @retval None - */ -void IWDG_Enable(void) -{ - IWDG->KR = KR_KEY_ENABLE; -} - -/** - * @} - */ - -/** @defgroup IWDG_Group3 Flag management function - * @brief Flag management function - * -@verbatim - =============================================================================== - ##### Flag management function ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Checks whether the specified IWDG flag is set or not. - * @param IWDG_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg IWDG_FLAG_PVU: Prescaler Value Update on going - * @arg IWDG_FLAG_RVU: Reload Value Update on going - * @arg IWDG_FLAG_WVU: Counter Window Value Update on going - * @retval The new state of IWDG_FLAG (SET or RESET). - */ -FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_IWDG_FLAG(IWDG_FLAG)); - if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_misc.c b/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_misc.c deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_misc.c +++ /dev/null @@ -1,167 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_misc.c - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file provides all the miscellaneous firmware functions (add-on - * to CMSIS functions). - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_misc.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup MISC - * @brief MISC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup MISC_Private_Functions - * @{ - */ -/** - * -@verbatim - ******************************************************************************* - ##### Interrupts configuration functions ##### - ******************************************************************************* - [..] This section provide functions allowing to configure the NVIC interrupts - (IRQ). The Cortex-M0 exceptions are managed by CMSIS functions. - (#) Enable and Configure the priority of the selected IRQ Channels. - The priority can be 0..3. - - -@- Lower priority values gives higher priority. - -@- Priority Order: - (#@) Lowest priority. - (#@) Lowest hardware priority (IRQn position). - -@endverbatim -*/ - -/** - * @brief Initializes the NVIC peripheral according to the specified - * parameters in the NVIC_InitStruct. - * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains - * the configuration information for the specified NVIC peripheral. - * @retval None - */ -void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) -{ - uint32_t tmppriority = 0x00; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); - assert_param(IS_NVIC_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPriority)); - - if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) - { - /* Compute the Corresponding IRQ Priority --------------------------------*/ - tmppriority = NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel >> 0x02]; - tmppriority &= (uint32_t)(~(((uint32_t)0xFF) << ((NVIC_InitStruct->NVIC_IRQChannel & 0x03) * 8))); - tmppriority |= (uint32_t)((((uint32_t)NVIC_InitStruct->NVIC_IRQChannelPriority << 6) & 0xFF) << ((NVIC_InitStruct->NVIC_IRQChannel & 0x03) * 8)); - - NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel >> 0x02] = tmppriority; - - /* Enable the Selected IRQ Channels --------------------------------------*/ - NVIC->ISER[0] = (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); - } - else - { - /* Disable the Selected IRQ Channels -------------------------------------*/ - NVIC->ICER[0] = (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); - } -} - -/** - * @brief Selects the condition for the system to enter low power mode. - * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. - * This parameter can be one of the following values: - * @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend. - * @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request. - * @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit. - * @param NewState: new state of LP condition. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_NVIC_LP(LowPowerMode)); - - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - SCB->SCR |= LowPowerMode; - } - else - { - SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); - } -} - -/** - * @brief Configures the SysTick clock source. - * @param SysTick_CLKSource: specifies the SysTick clock source. - * This parameter can be one of the following values: - * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. - * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. - * @retval None - */ -void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) -{ - /* Check the parameters */ - assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); - - if (SysTick_CLKSource == SysTick_CLKSource_HCLK) - { - SysTick->CTRL |= SysTick_CLKSource_HCLK; - } - else - { - SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_pwr.c b/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_pwr.c deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_pwr.c +++ /dev/null @@ -1,566 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_pwr.c - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the Power Controller (PWR) peripheral: - * + Backup Domain Access - * + PVD configuration - * + WakeUp pins configuration - * + Low Power modes configuration - * + Flags management - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_pwr.h" -#include "stm32f0xx_rcc.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup PWR - * @brief PWR driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* ------------------ PWR registers bit mask ------------------------ */ - -/* CR register bit mask */ -#define CR_DS_MASK ((uint32_t)0xFFFFFFFC) -#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup PWR_Private_Functions - * @{ - */ - -/** @defgroup PWR_Group1 Backup Domain Access function - * @brief Backup Domain Access function - * -@verbatim - ============================================================================== - ##### Backup Domain Access function ##### - ============================================================================== - - [..] After reset, the Backup Domain Registers (RCC BDCR Register, RTC registers - and RTC backup registers) are protected against possible stray write accesses. - [..] To enable access to Backup domain use the PWR_BackupAccessCmd(ENABLE) function. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the PWR peripheral registers to their default reset values. - * @param None - * @retval None - */ -void PWR_DeInit(void) -{ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); -} - -/** - * @brief Enables or disables access to the Backup domain registers. - * @note If the HSE divided by 32 is used as the RTC clock, the - * Backup Domain Access should be kept enabled. - * @param NewState: new state of the access to the Backup domain registers. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_BackupAccessCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Backup Domain Access */ - PWR->CR |= PWR_CR_DBP; - } - else - { - /* Disable the Backup Domain Access */ - PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_DBP); - } -} - -/** - * @} - */ - -/** @defgroup PWR_Group2 PVD configuration functions - * @brief PVD configuration functions - * -@verbatim - ============================================================================== - ##### PVD configuration functions ##### - ============================================================================== - [..] - (+) The PVD is used to monitor the VDD power supply by comparing it to a threshold - selected by the PVD Level (PLS[2:0] bits in the PWR_CR). - (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the - PVD threshold. This event is internally connected to the EXTI line16 - and can generate an interrupt if enabled through the EXTI registers. - (+) The PVD is stopped in Standby mode. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). - * @note This function is not applicable for STM32F030 devices. - * @param PWR_PVDLevel: specifies the PVD detection level - * This parameter can be one of the following values: - * @arg PWR_PVDLevel_0 - * @arg PWR_PVDLevel_1 - * @arg PWR_PVDLevel_2 - * @arg PWR_PVDLevel_3 - * @arg PWR_PVDLevel_4 - * @arg PWR_PVDLevel_5 - * @arg PWR_PVDLevel_6 - * @arg PWR_PVDLevel_7 - * @note Refer to the electrical characteristics of your device datasheet for - * more details about the voltage threshold corresponding to each - * detection level. - * @retval None - */ -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); - - tmpreg = PWR->CR; - - /* Clear PLS[7:5] bits */ - tmpreg &= CR_PLS_MASK; - - /* Set PLS[7:5] bits according to PWR_PVDLevel value */ - tmpreg |= PWR_PVDLevel; - - /* Store the new value */ - PWR->CR = tmpreg; -} - -/** - * @brief Enables or disables the Power Voltage Detector(PVD). - * @note This function is not applicable for STM32F030 devices. - * @param NewState: new state of the PVD. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_PVDCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the PVD */ - PWR->CR |= PWR_CR_PVDE; - } - else - { - /* Disable the PVD */ - PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_PVDE); - } -} - -/** - * @} - */ - -/** @defgroup PWR_Group3 WakeUp pins configuration functions - * @brief WakeUp pins configuration functions - * -@verbatim - ============================================================================== - ##### WakeUp pin configuration functions ##### - ============================================================================== - - (+) WakeUp pins are used to wakeup the system from Standby mode. These pins are - forced in input pull down configuration and are active on rising edges. - (+) There are eight WakeUp pins: WakeUp Pin 1 on PA.00 and WakeUp Pin 2 on PC.13. - The following WakeUp pins are only applicable for STM32F072 dvices: - WakeUp Pin 3 on PE.06, WakeUp Pin 4 on PA.02, WakeUp Pin 5 on PC.05, - WakeUp Pin 6 on PB.05, WakeUp Pin 7 on PB.15 and WakeUp Pin 8 on PF.02. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the WakeUp Pin functionality. - * @param PWR_WakeUpPin: specifies the WakeUpPin. - * This parameter can be one of the following values - * @arg PWR_WakeUpPin_1 - * @arg PWR_WakeUpPin_2 - * @arg PWR_WakeUpPin_3, only applicable for STM32F072 devices - * @arg PWR_WakeUpPin_4, only applicable for STM32F072 devices - * @arg PWR_WakeUpPin_5, only applicable for STM32F072 devices - * @arg PWR_WakeUpPin_6, only applicable for STM32F072 devices - * @arg PWR_WakeUpPin_7, only applicable for STM32F072 devices - * @arg PWR_WakeUpPin_8, only applicable for STM32F072 devices - * @param NewState: new state of the WakeUp Pin functionality. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_PWR_WAKEUP_PIN(PWR_WakeUpPin)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the EWUPx pin */ - PWR->CSR |= PWR_WakeUpPin; - } - else - { - /* Disable the EWUPx pin */ - PWR->CSR &= ~PWR_WakeUpPin; - } -} - -/** - * @} - */ - - -/** @defgroup PWR_Group4 Low Power modes configuration functions - * @brief Low Power modes configuration functions - * -@verbatim - ============================================================================== - ##### Low Power modes configuration functions ##### - ============================================================================== - - [..] The devices feature three low-power modes: - (+) Sleep mode: Cortex-M0 core stopped, peripherals kept running. - (+) Stop mode: all clocks are stopped, regulator running, regulator in low power mode - (+) Standby mode: VCORE domain powered off - - *** Sleep mode *** - ================== - [..] - (+) Entry: - (++) The Sleep mode is entered by executing the WFE() or WFI() instructions. - (+) Exit: - (++) Any peripheral interrupt acknowledged by the nested vectored interrupt - controller (NVIC) can wake up the device from Sleep mode. - - *** Stop mode *** - ================= - [..] In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the HSI, - the HSI14 and the HSE RC oscillators are disabled. Internal SRAM and register - contents are preserved. - The voltage regulator can be configured either in normal or low-power mode. - - (+) Entry: - (++) The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,) - function with regulator in LowPower or with Regulator ON. - (+) Exit: - (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode - or any internal IPs (I2C, UASRT or CEC) wakeup event. - - *** Standby mode *** - ==================== - [..] The Standby mode allows to achieve the lowest power consumption. It is based - on the Cortex-M0 deepsleep mode, with the voltage regulator disabled. - The VCORE domain is consequently powered off. The PLL, the HSI, the HSI14 - oscillator and the HSE oscillator are also switched off. SRAM and register - contents are lost except for the Backup domain (RTC registers, RTC backup - registers and Standby circuitry). - - [..] The voltage regulator is OFF. - - (+) Entry: - (++) The Standby mode is entered using the PWR_EnterSTANDBYMode() function. - (+) Exit: - (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup, - tamper event, time-stamp event, external reset in NRST pin, IWDG reset. - - *** Auto-wakeup (AWU) from low-power mode *** - ============================================= - [..] The MCU can be woken up from low-power mode by an RTC Alarm event, a tamper - event, a time-stamp event, or a comparator event, without depending on an - external interrupt (Auto-wakeup mode). - - (+) RTC auto-wakeup (AWU) from the Stop mode - (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to: - (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt - or Event modes) using the EXTI_Init() function. - (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function - (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() - and RTC_AlarmCmd() functions. - (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it - is necessary to: - (+++) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt - or Event modes) using the EXTI_Init() function. - (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() - function. - (+++) Configure the RTC to detect the tamper or time stamp event using the - RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd() - functions. - - (+) RTC auto-wakeup (AWU) from the Standby mode - (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to: - (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function. - (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() - and RTC_AlarmCmd() functions. - (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it - is necessary to: - (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() - function. - (+++) Configure the RTC to detect the tamper or time stamp event using the - RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd() - functions. - - (+) Comparator auto-wakeup (AWU) from the Stop mode - (++) To wake up from the Stop mode with an comparator 1 or comparator 2 wakeup - event, it is necessary to: - (+++) Configure the EXTI Line 21 for comparator 1 or EXTI Line 22 for comparator 2 - to be sensitive to to the selected edges (falling, rising or falling - and rising) (Interrupt or Event modes) using the EXTI_Init() function. - (+++) Configure the comparator to generate the event. - -@endverbatim - * @{ - */ - -/** - * @brief Enters Sleep mode. - * @note In Sleep mode, all I/O pins keep the same state as in Run mode. - * @param PWR_SLEEPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction - * @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction - * @retval None - */ -void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry) -{ - /* Check the parameters */ - assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry)); - - /* Clear SLEEPDEEP bit of Cortex-M0 System Control Register */ - SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); - - /* Select SLEEP mode entry -------------------------------------------------*/ - if(PWR_SLEEPEntry == PWR_SLEEPEntry_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __SEV(); - __WFE(); - __WFE(); - } -} - -/** - * @brief Enters STOP mode. - * @note In Stop mode, all I/O pins keep the same state as in Run mode. - * @note When exiting Stop mode by issuing an interrupt or a wakeup event, - * the HSI RC oscillator is selected as system clock. - * @note When the voltage regulator operates in low power mode, an additional - * startup delay is incurred when waking up from Stop mode. - * By keeping the internal regulator ON during Stop mode, the consumption - * is higher although the startup time is reduced. - * @param PWR_Regulator: specifies the regulator state in STOP mode. - * This parameter can be one of the following values: - * @arg PWR_Regulator_ON: STOP mode with regulator ON - * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode - * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction - * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction - @arg PWR_STOPEntry_SLEEPONEXIT: enter STOP mode with SLEEPONEXIT instruction - * @retval None - */ -void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR(PWR_Regulator)); - assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); - - /* Select the regulator state in STOP mode ---------------------------------*/ - tmpreg = PWR->CR; - /* Clear PDDS and LPDSR bits */ - tmpreg &= CR_DS_MASK; - - /* Set LPDSR bit according to PWR_Regulator value */ - tmpreg |= PWR_Regulator; - - /* Store the new value */ - PWR->CR = tmpreg; - - /* Set SLEEPDEEP bit of Cortex-M0 System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* Select STOP mode entry --------------------------------------------------*/ - if(PWR_STOPEntry == PWR_STOPEntry_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - /* Reset SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); - } - else if (PWR_STOPEntry == PWR_STOPEntry_WFE) - { - /* Request Wait For Event */ - __WFE(); - /* Reset SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); - } - else - { - /* Set SLEEP on exit bit of Cortex-M0 System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk; - } -} - -/** - * @brief Enters STANDBY mode. - * @note In Standby mode, all I/O pins are high impedance except for: - * - Reset pad (still available) - * - RTC_AF1 pin (PC13) if configured for Wakeup pin 2 (WKUP2), tamper, - * time-stamp, RTC Alarm out, or RTC clock calibration out. - * - WKUP pin 1 (PA0) if enabled. - * @note The Wakeup flag (WUF) need to be cleared at application level before to call this function - * @param None - * @retval None - */ -void PWR_EnterSTANDBYMode(void) -{ - /* Select STANDBY mode */ - PWR->CR |= PWR_CR_PDDS; - - /* Set SLEEPDEEP bit of Cortex-M0 System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* Request Wait For Interrupt */ - __WFI(); -} - -/** - * @} - */ - -/** @defgroup PWR_Group5 Flags management functions - * @brief Flags management functions - * -@verbatim - ============================================================================== - ##### Flags management functions ##### - ============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Checks whether the specified PWR flag is set or not. - * @param PWR_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup - * event was received from the WKUP pin or from the RTC alarm - * (Alarm A or Alarm B), RTC Tamper event or RTC TimeStamp event. - * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the - * system was resumed from StandBy mode. - * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD - * is enabled by the PWR_PVDCmd() function. - * @arg PWR_FLAG_VREFINTRDY: Internal Voltage Reference Ready flag. - * This flag indicates the state of the internal voltage - * reference, VREFINT. - * @retval The new state of PWR_FLAG (SET or RESET). - */ -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); - - if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the PWR's pending flags. - * @param PWR_FLAG: specifies the flag to clear. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag - * @arg PWR_FLAG_SB: StandBy flag - * @retval None - */ -void PWR_ClearFlag(uint32_t PWR_FLAG) -{ - /* Check the parameters */ - assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); - - PWR->CR |= PWR_FLAG << 2; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_rcc.c b/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_rcc.c deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_rcc.c +++ /dev/null @@ -1,1781 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_rcc.c - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the Reset and clock control (RCC) peripheral: - * + Internal/external clocks, PLL, CSS and MCO configuration - * + System, AHB and APB busses clocks configuration - * + Peripheral clocks configuration - * + Interrupts and flags management - * - @verbatim - - =============================================================================== - ##### RCC specific features ##### - =============================================================================== - [..] After reset the device is running from HSI (8 MHz) with Flash 0 WS, - all peripherals are off except internal SRAM, Flash and SWD. - (#) There is no prescaler on High speed (AHB) and Low speed (APB) busses; - all peripherals mapped on these busses are running at HSI speed. - (#) The clock for all peripherals is switched off, except the SRAM and FLASH. - (#) All GPIOs are in input floating state, except the SWD pins which - are assigned to be used for debug purpose. - [..] Once the device started from reset, the user application has to: - (#) Configure the clock source to be used to drive the System clock - (if the application needs higher frequency/performance) - (#) Configure the System clock frequency and Flash settings - (#) Configure the AHB and APB busses prescalers - (#) Enable the clock for the peripheral(s) to be used - (#) Configure the clock source(s) for peripherals which clocks are not - derived from the System clock (ADC, CEC, I2C, USART, RTC and IWDG) - - @endverbatim - - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_rcc.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup RCC - * @brief RCC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* ---------------------- RCC registers mask -------------------------------- */ -/* RCC Flag Mask */ -#define FLAG_MASK ((uint8_t)0x1F) - -/* CR register byte 2 (Bits[23:16]) base address */ -#define CR_BYTE2_ADDRESS ((uint32_t)0x40021002) - -/* CFGR register byte 3 (Bits[31:23]) base address */ -#define CFGR_BYTE3_ADDRESS ((uint32_t)0x40021007) - -/* CIR register byte 1 (Bits[15:8]) base address */ -#define CIR_BYTE1_ADDRESS ((uint32_t)0x40021009) - -/* CIR register byte 2 (Bits[23:16]) base address */ -#define CIR_BYTE2_ADDRESS ((uint32_t)0x4002100A) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; - -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup RCC_Private_Functions - * @{ - */ - -/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions - * @brief Internal and external clocks, PLL, CSS and MCO configuration functions - * -@verbatim - =============================================================================== - ##### Internal-external clocks, PLL, CSS and MCO configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to configure the internal/external clocks, - PLL, CSS and MCO. - (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly - or through the PLL as System clock source. - The HSI clock can be used also to clock the USART, I2C and CEC peripherals. - (#) HSI14 (high-speed internal for ADC), 14 MHz factory-trimmed RC used to clock - the ADC peripheral. - (#) LSI (low-speed internal), 40 KHz low consumption RC used as IWDG and/or RTC - clock source. - (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or - through the PLL as System clock source. Can be used also as RTC clock source. - (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. - LSE can be used also to clock the USART and CEC peripherals. - (#) PLL (clocked by HSI or HSE), for System clock. - (#) CSS (Clock security system), once enabled and if a HSE clock failure occurs - (HSE used directly or through PLL as System clock source), the System clock - is automatically switched to HSI and an interrupt is generated if enabled. - The interrupt is linked to the Cortex-M0 NMI (Non-Maskable Interrupt) - exception vector. - (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSI14, LSI, - HSE, LSE or PLL (divided by 2) clock on PA8 pin. - -@endverbatim - * @{ - */ - -/** - * @brief Resets the RCC clock configuration to the default reset state. - * @note The default reset state of the clock configuration is given below: - * @note HSI ON and used as system clock source - * @note HSI14, HSE and PLL OFF - * @note AHB, APB prescaler set to 1. - * @note CSS and MCO OFF - * @note All interrupts disabled - * @note However, this function doesn't modify the configuration of the - * @note Peripheral clocks - * @note LSI, LSE and RTC clocks - * @param None - * @retval None - */ -void RCC_DeInit(void) -{ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - -#if defined (STM32F051) - /* Reset SW[1:0], HPRE[3:0], PPRE[2:0] and MCOSEL[2:0] bits */ - RCC->CFGR &= (uint32_t)0xF8FFB80C; -#else - /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */ - RCC->CFGR &= (uint32_t)0x08FFB80C; -#endif /* STM32F051 */ - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ - RCC->CFGR &= (uint32_t)0xFFC0FFFF; - - /* Reset PREDIV1[3:0] bits */ - RCC->CFGR2 &= (uint32_t)0xFFFFFFF0; - - /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */ - RCC->CFGR3 &= (uint32_t)0xFFF0FEAC; - - /* Reset HSI14 bit */ - RCC->CR2 &= (uint32_t)0xFFFFFFFE; - - /* Disable all interrupts */ - RCC->CIR = 0x00000000; -} - -/** - * @brief Configures the External High Speed oscillator (HSE). - * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application - * software should wait on HSERDY flag to be set indicating that HSE clock - * is stable and can be used to clock the PLL and/or system clock. - * @note HSE state can not be changed if it is used directly or through the - * PLL as system clock. In this case, you have to select another source - * of the system clock then change the HSE state (ex. disable it). - * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. - * @note This function resets the CSSON bit, so if the Clock security system(CSS) - * was previously enabled you have to enable it again after calling this - * function. - * @param RCC_HSE: specifies the new state of the HSE. - * This parameter can be one of the following values: - * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after - * 6 HSE oscillator clock cycles. - * @arg RCC_HSE_ON: turn ON the HSE oscillator - * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock - * @retval None - */ -void RCC_HSEConfig(uint8_t RCC_HSE) -{ - /* Check the parameters */ - assert_param(IS_RCC_HSE(RCC_HSE)); - - /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ - *(__IO uint8_t *) CR_BYTE2_ADDRESS = RCC_HSE_OFF; - - /* Set the new HSE configuration -------------------------------------------*/ - *(__IO uint8_t *) CR_BYTE2_ADDRESS = RCC_HSE; - -} - -/** - * @brief Waits for HSE start-up. - * @note This function waits on HSERDY flag to be set and return SUCCESS if - * this flag is set, otherwise returns ERROR if the timeout is reached - * and this flag is not set. The timeout value is defined by the constant - * HSE_STARTUP_TIMEOUT in stm32f0xx.h file. You can tailor it depending - * on the HSE crystal used in your application. - * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. - * @param None - * @retval An ErrorStatus enumeration value: - * - SUCCESS: HSE oscillator is stable and ready to use - * - ERROR: HSE oscillator not yet ready - */ -ErrorStatus RCC_WaitForHSEStartUp(void) -{ - __IO uint32_t StartUpCounter = 0; - ErrorStatus status = ERROR; - FlagStatus HSEStatus = RESET; - - /* Wait till HSE is ready and if timeout is reached exit */ - do - { - HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); - StartUpCounter++; - } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); - - if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) - { - status = SUCCESS; - } - else - { - status = ERROR; - } - return (status); -} - -/** - * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. - * @note The calibration is used to compensate for the variations in voltage - * and temperature that influence the frequency of the internal HSI RC. - * Refer to the Application Note AN4067 for more details on how to - * calibrate the HSI. - * @param HSICalibrationValue: specifies the HSI calibration trimming value. - * This parameter must be a number between 0 and 0x1F. - * @retval None - */ -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_HSI_CALIBRATION_VALUE(HSICalibrationValue)); - - tmpreg = RCC->CR; - - /* Clear HSITRIM[4:0] bits */ - tmpreg &= ~RCC_CR_HSITRIM; - - /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ - tmpreg |= (uint32_t)HSICalibrationValue << 3; - - /* Store the new value */ - RCC->CR = tmpreg; -} - -/** - * @brief Enables or disables the Internal High Speed oscillator (HSI). - * @note After enabling the HSI, the application software should wait on - * HSIRDY flag to be set indicating that HSI clock is stable and can - * be used to clock the PLL and/or system clock. - * @note HSI can not be stopped if it is used directly or through the PLL - * as system clock. In this case, you have to select another source - * of the system clock then stop the HSI. - * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. - * @param NewState: new state of the HSI. - * This parameter can be: ENABLE or DISABLE. - * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator - * clock cycles. - * @retval None - */ -void RCC_HSICmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->CR |= RCC_CR_HSION; - } - else - { - RCC->CR &= ~RCC_CR_HSION; - } -} - -/** - * @brief Adjusts the Internal High Speed oscillator for ADC (HSI14) - * calibration value. - * @note The calibration is used to compensate for the variations in voltage - * and temperature that influence the frequency of the internal HSI RC. - * Refer to the Application Note AN4067 for more details on how to - * calibrate the HSI14. - * @param HSI14CalibrationValue: specifies the HSI14 calibration trimming value. - * This parameter must be a number between 0 and 0x1F. - * @retval None - */ -void RCC_AdjustHSI14CalibrationValue(uint8_t HSI14CalibrationValue) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_HSI14_CALIBRATION_VALUE(HSI14CalibrationValue)); - - tmpreg = RCC->CR2; - - /* Clear HSI14TRIM[4:0] bits */ - tmpreg &= ~RCC_CR2_HSI14TRIM; - - /* Set the HSITRIM14[4:0] bits according to HSI14CalibrationValue value */ - tmpreg |= (uint32_t)HSI14CalibrationValue << 3; - - /* Store the new value */ - RCC->CR2 = tmpreg; -} - -/** - * @brief Enables or disables the Internal High Speed oscillator for ADC (HSI14). - * @note After enabling the HSI14, the application software should wait on - * HSIRDY flag to be set indicating that HSI clock is stable and can - * be used to clock the ADC. - * @note The HSI14 is stopped by hardware when entering STOP and STANDBY modes. - * @param NewState: new state of the HSI14. - * This parameter can be: ENABLE or DISABLE. - * @note When the HSI14 is stopped, HSI14RDY flag goes low after 6 HSI14 oscillator - * clock cycles. - * @retval None - */ -void RCC_HSI14Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->CR2 |= RCC_CR2_HSI14ON; - } - else - { - RCC->CR2 &= ~RCC_CR2_HSI14ON; - } -} - -/** - * @brief Enables or disables the Internal High Speed oscillator request from ADC. - * @param NewState: new state of the HSI14 ADC request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_HSI14ADCRequestCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->CR2 &= ~RCC_CR2_HSI14DIS; - } - else - { - RCC->CR2 |= RCC_CR2_HSI14DIS; - } -} - -/** - * @brief Configures the External Low Speed oscillator (LSE). - * @note As the LSE is in the Backup domain and write access is denied to this - * domain after reset, you have to enable write access using - * PWR_BackupAccessCmd(ENABLE) function before to configure the LSE - * (to be done once after reset). - * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application - * software should wait on LSERDY flag to be set indicating that LSE clock - * is stable and can be used to clock the RTC. - * @param RCC_LSE: specifies the new state of the LSE. - * This parameter can be one of the following values: - * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after - * 6 LSE oscillator clock cycles. - * @arg RCC_LSE_ON: turn ON the LSE oscillator - * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock - * @retval None - */ -void RCC_LSEConfig(uint32_t RCC_LSE) -{ - /* Check the parameters */ - assert_param(IS_RCC_LSE(RCC_LSE)); - - /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ - /* Reset LSEON bit */ - RCC->BDCR &= ~(RCC_BDCR_LSEON); - - /* Reset LSEBYP bit */ - RCC->BDCR &= ~(RCC_BDCR_LSEBYP); - - /* Configure LSE */ - RCC->BDCR |= RCC_LSE; -} - -/** - * @brief Configures the External Low Speed oscillator (LSE) drive capability. - * @param RCC_LSEDrive: specifies the new state of the LSE drive capability. - * This parameter can be one of the following values: - * @arg RCC_LSEDrive_Low: LSE oscillator low drive capability. - * @arg RCC_LSEDrive_MediumLow: LSE oscillator medium low drive capability. - * @arg RCC_LSEDrive_MediumHigh: LSE oscillator medium high drive capability. - * @arg RCC_LSEDrive_High: LSE oscillator high drive capability. - * @retval None - */ -void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive) -{ - /* Check the parameters */ - assert_param(IS_RCC_LSE_DRIVE(RCC_LSEDrive)); - - /* Clear LSEDRV[1:0] bits */ - RCC->BDCR &= ~(RCC_BDCR_LSEDRV); - - /* Set the LSE Drive */ - RCC->BDCR |= RCC_LSEDrive; -} - -/** - * @brief Enables or disables the Internal Low Speed oscillator (LSI). - * @note After enabling the LSI, the application software should wait on - * LSIRDY flag to be set indicating that LSI clock is stable and can - * be used to clock the IWDG and/or the RTC. - * @note LSI can not be disabled if the IWDG is running. - * @param NewState: new state of the LSI. - * This parameter can be: ENABLE or DISABLE. - * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator - * clock cycles. - * @retval None - */ -void RCC_LSICmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->CSR |= RCC_CSR_LSION; - } - else - { - RCC->CSR &= ~RCC_CSR_LSION; - } -} - -/** - * @brief Configures the PLL clock source and multiplication factor. - * @note This function must be used only when the PLL is disabled. - * - * @param RCC_PLLSource: specifies the PLL entry clock source. - * This parameter can be one of the following values: - * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock selected as PLL clock source - * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry - * @arg RCC_PLLSource_HSI48 HSI48 oscillator clock selected as PLL clock source, applicable only for STM32F072 devices - * @arg RCC_PLLSource_HSI: HSI clock selected as PLL clock entry, applicable only for STM32F072 devices - * @note The minimum input clock frequency for PLL is 2 MHz (when using HSE as - * PLL source). - * - * @param RCC_PLLMul: specifies the PLL multiplication factor, which drive the PLLVCO clock - * This parameter can be RCC_PLLMul_x where x:[2,16] - * - * @retval None - */ -void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul) -{ - /* Check the parameters */ - assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); - assert_param(IS_RCC_PLL_MUL(RCC_PLLMul)); - - /* Clear PLL Source [16] and Multiplier [21:18] bits */ - RCC->CFGR &= ~(RCC_CFGR_PLLMULL | RCC_CFGR_PLLSRC); - - /* Set the PLL Source and Multiplier */ - RCC->CFGR |= (uint32_t)(RCC_PLLSource | RCC_PLLMul); -} - -/** - * @brief Enables or disables the PLL. - * @note After enabling the PLL, the application software should wait on - * PLLRDY flag to be set indicating that PLL clock is stable and can - * be used as system clock source. - * @note The PLL can not be disabled if it is used as system clock source - * @note The PLL is disabled by hardware when entering STOP and STANDBY modes. - * @param NewState: new state of the PLL. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_PLLCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->CR |= RCC_CR_PLLON; - } - else - { - RCC->CR &= ~RCC_CR_PLLON; - } -} - -/** - * @brief Enables or disables the Internal High Speed oscillator for USB (HSI48). - * This function is only applicable for STM32F072 devices. - * @note After enabling the HSI48, the application software should wait on - * HSI48RDY flag to be set indicating that HSI48 clock is stable and can - * be used to clock the USB. - * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. - * @param NewState: new state of the HSI48. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_HSI48Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->CR2 |= RCC_CR2_HSI48ON; - } - else - { - RCC->CR2 &= ~RCC_CR2_HSI48ON; - } -} - -/** - * @brief Configures the PREDIV1 division factor. - * @note This function must be used only when the PLL is disabled. - * @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor. - * This parameter can be RCC_PREDIV1_Divx where x:[1,16] - * @retval None - */ -void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div)); - - tmpreg = RCC->CFGR2; - /* Clear PREDIV1[3:0] bits */ - tmpreg &= ~(RCC_CFGR2_PREDIV1); - /* Set the PREDIV1 division factor */ - tmpreg |= RCC_PREDIV1_Div; - /* Store the new value */ - RCC->CFGR2 = tmpreg; -} - -/** - * @brief Enables or disables the Clock Security System. - * @note If a failure is detected on the HSE oscillator clock, this oscillator - * is automatically disabled and an interrupt is generated to inform the - * software about the failure (Clock Security System Interrupt, CSSI), - * allowing the MCU to perform rescue operations. The CSSI is linked to - * the Cortex-M0 NMI (Non-Maskable Interrupt) exception vector. - * @param NewState: new state of the Clock Security System. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_ClockSecuritySystemCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->CR |= RCC_CR_CSSON; - } - else - { - RCC->CR &= ~RCC_CR_CSSON; - } -} - -#ifdef STM32F051 -/** - * @brief Selects the clock source to output on MCO pin (PA8). - * @note PA8 should be configured in alternate function mode. - * @param RCC_MCOSource: specifies the clock source to output. - * This parameter can be one of the following values: - * @arg RCC_MCOSource_NoClock: No clock selected. - * @arg RCC_MCOSource_HSI14: HSI14 oscillator clock selected. - * @arg RCC_MCOSource_LSI: LSI oscillator clock selected. - * @arg RCC_MCOSource_LSE: LSE oscillator clock selected. - * @arg RCC_MCOSource_SYSCLK: System clock selected. - * @arg RCC_MCOSource_HSI: HSI oscillator clock selected. - * @arg RCC_MCOSource_HSE: HSE oscillator clock selected. - * @arg RCC_MCOSource_PLLCLK_Div2: PLL clock divided by 2 selected. - * @retval None - */ -void RCC_MCOConfig(uint8_t RCC_MCOSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource)); - - /* Select MCO clock source and prescaler */ - *(__IO uint8_t *) CFGR_BYTE3_ADDRESS = RCC_MCOSource; -} -#else - -/** - * @brief Selects the clock source to output on MCO pin (PA8) and the corresponding - * prescsaler. - * @note PA8 should be configured in alternate function mode. - * @param RCC_MCOSource: specifies the clock source to output. - * This parameter can be one of the following values: - * @arg RCC_MCOSource_NoClock: No clock selected. - * @arg RCC_MCOSource_HSI14: HSI14 oscillator clock selected. - * @arg RCC_MCOSource_LSI: LSI oscillator clock selected. - * @arg RCC_MCOSource_LSE: LSE oscillator clock selected. - * @arg RCC_MCOSource_SYSCLK: System clock selected. - * @arg RCC_MCOSource_HSI: HSI oscillator clock selected. - * @arg RCC_MCOSource_HSE: HSE oscillator clock selected. - * @arg RCC_MCOSource_PLLCLK_Div2: PLL clock divided by 2 selected. - * @arg RCC_MCOSource_PLLCLK: PLL clock selected. - * @arg RCC_MCOSource_HSI48: HSI48 clock selected. - * @param RCC_MCOPrescaler: specifies the prescaler on MCO pin. - * This parameter can be one of the following values: - * @arg RCC_MCOPrescaler_1: MCO clock is divided by 1. - * @arg RCC_MCOPrescaler_2: MCO clock is divided by 2. - * @arg RCC_MCOPrescaler_4: MCO clock is divided by 4. - * @arg RCC_MCOPrescaler_8: MCO clock is divided by 8. - * @arg RCC_MCOPrescaler_16: MCO clock is divided by 16. - * @arg RCC_MCOPrescaler_32: MCO clock is divided by 32. - * @arg RCC_MCOPrescaler_64: MCO clock is divided by 64. - * @arg RCC_MCOPrescaler_128: MCO clock is divided by 128. - * @retval None - */ -void RCC_MCOConfig(uint8_t RCC_MCOSource, uint32_t RCC_MCOPrescaler) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource)); - assert_param(IS_RCC_MCO_PRESCALER(RCC_MCOPrescaler)); - - /* Get CFGR value */ - tmpreg = RCC->CFGR; - /* Clear MCOPRE[2:0] bits */ - tmpreg &= ~(RCC_CFGR_MCO_PRE | RCC_CFGR_MCO | RCC_CFGR_PLLNODIV); - /* Set the RCC_MCOSource and RCC_MCOPrescaler */ - tmpreg |= (RCC_MCOPrescaler | ((uint32_t)RCC_MCOSource<<24)); - /* Store the new value */ - RCC->CFGR = tmpreg; -} -#endif /* STM32F072 */ - -/** - * @} - */ - -/** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions - * @brief System, AHB and APB busses clocks configuration functions - * -@verbatim - =============================================================================== - ##### System, AHB and APB busses clocks configuration functions ##### - =============================================================================== - - [..] This section provide functions allowing to configure the System, AHB and - APB busses clocks. - (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, - HSE and PLL. - The AHB clock (HCLK) is derived from System clock through configurable prescaler - and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA and GPIO). - and APB (PCLK) clocks are derived from AHB clock through - configurable prescalers and used to clock the peripherals mapped on these busses. - You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks. - - -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: - (+@) The ADC clock which is derived from HSI14 or APB (APB divided by a - programmable prescaler: 2 or 4). - (+@) The CEC clock which is derived from LSE or HSI divided by 244. - (+@) The I2C clock which is derived from HSI or system clock (SYSCLK). - (+@) The USART clock which is derived from HSI, system clock (SYSCLK), APB or LSE. - (+@) The RTC/LCD clock which is derived from the LSE, LSI or 2 MHz HSE_RTC (HSE - divided by a programmable prescaler). - The System clock (SYSCLK) frequency must be higher or equal to the RTC/LCD - clock frequency. - (+@) IWDG clock which is always the LSI clock. - - (#) The maximum frequency of the SYSCLK, HCLK and PCLK is 48 MHz. - Depending on the maximum frequency, the FLASH wait states (WS) should be - adapted accordingly: - +--------------------------------------------- + - | Wait states | HCLK clock frequency (MHz) | - |---------------|------------------------------| - |0WS(1CPU cycle)| 0 < HCLK <= 24 | - |---------------|------------------------------| - |1WS(2CPU cycle)| 24 < HCLK <= 48 | - +----------------------------------------------+ - - (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and - prefetch is disabled. - - [..] It is recommended to use the following software sequences to tune the number - of wait states needed to access the Flash memory with the CPU frequency (HCLK). - (+) Increasing the CPU frequency - (++) Program the Flash Prefetch buffer, using "FLASH_PrefetchBufferCmd(ENABLE)" - function - (++) Check that Flash Prefetch buffer activation is taken into account by - reading FLASH_ACR using the FLASH_GetPrefetchBufferStatus() function - (++) Program Flash WS to 1, using "FLASH_SetLatency(FLASH_Latency_1)" function - (++) Check that the new number of WS is taken into account by reading FLASH_ACR - (++) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function - (++) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function - (++) Check that the new CPU clock source is taken into account by reading - the clock source status, using "RCC_GetSYSCLKSource()" function - (+) Decreasing the CPU frequency - (++) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function - (++) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function - (++) Check that the new CPU clock source is taken into account by reading - the clock source status, using "RCC_GetSYSCLKSource()" function - (++) Program the new number of WS, using "FLASH_SetLatency()" function - (++) Check that the new number of WS is taken into account by reading FLASH_ACR - (++) Disable the Flash Prefetch buffer using "FLASH_PrefetchBufferCmd(DISABLE)" - function - (++) Check that Flash Prefetch buffer deactivation is taken into account by reading FLASH_ACR - using the FLASH_GetPrefetchBufferStatus() function. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the system clock (SYSCLK). - * @note The HSI is used (enabled by hardware) as system clock source after - * startup from Reset, wake-up from STOP and STANDBY mode, or in case - * of failure of the HSE used directly or indirectly as system clock - * (if the Clock Security System CSS is enabled). - * @note A switch from one clock source to another occurs only if the target - * clock source is ready (clock stable after startup delay or PLL locked). - * If a clock source which is not yet ready is selected, the switch will - * occur when the clock source will be ready. - * You can use RCC_GetSYSCLKSource() function to know which clock is - * currently used as system clock source. - * @param RCC_SYSCLKSource: specifies the clock source used as system clock source - * This parameter can be one of the following values: - * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source - * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source - * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source - * @arg RCC_SYSCLKSource_HSI48: HSI48 selected as system clock source, applicable only for STM32F072 devices - * @retval None - */ -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); - - tmpreg = RCC->CFGR; - - /* Clear SW[1:0] bits */ - tmpreg &= ~RCC_CFGR_SW; - - /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ - tmpreg |= RCC_SYSCLKSource; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Returns the clock source used as system clock. - * @param None - * @retval The clock source used as system clock. The returned value can be one - * of the following values: - * - 0x00: HSI used as system clock - * - 0x04: HSE used as system clock - * - 0x08: PLL used as system clock - * - 0x0C: HSI48 used as system clock, applicable only for STM32F072 devices - */ -uint8_t RCC_GetSYSCLKSource(void) -{ - return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS)); -} - -/** - * @brief Configures the AHB clock (HCLK). - * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from - * the system clock (SYSCLK). - * This parameter can be one of the following values: - * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK - * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 - * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 - * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 - * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 - * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 - * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 - * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 - * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 - * @retval None - */ -void RCC_HCLKConfig(uint32_t RCC_SYSCLK) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_HCLK(RCC_SYSCLK)); - - tmpreg = RCC->CFGR; - - /* Clear HPRE[3:0] bits */ - tmpreg &= ~RCC_CFGR_HPRE; - - /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ - tmpreg |= RCC_SYSCLK; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Configures the APB clock (PCLK). - * @param RCC_HCLK: defines the APB clock divider. This clock is derived from - * the AHB clock (HCLK). - * This parameter can be one of the following values: - * @arg RCC_HCLK_Div1: APB clock = HCLK - * @arg RCC_HCLK_Div2: APB clock = HCLK/2 - * @arg RCC_HCLK_Div4: APB clock = HCLK/4 - * @arg RCC_HCLK_Div8: APB clock = HCLK/8 - * @arg RCC_HCLK_Div16: APB clock = HCLK/16 - * @retval None - */ -void RCC_PCLKConfig(uint32_t RCC_HCLK) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PCLK(RCC_HCLK)); - - tmpreg = RCC->CFGR; - - /* Clear PPRE[2:0] bits */ - tmpreg &= ~RCC_CFGR_PPRE; - - /* Set PPRE[2:0] bits according to RCC_HCLK value */ - tmpreg |= RCC_HCLK; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Configures the ADC clock (ADCCLK). - * @note This function is obsolete. - * For proper ADC clock selection, refer to ADC_ClockModeConfig() in the ADC driver - * @param RCC_ADCCLK: defines the ADC clock source. This clock is derived - * from the HSI14 or APB clock (PCLK). - * This parameter can be one of the following values: - * @arg RCC_ADCCLK_HSI14: ADC clock = HSI14 (14MHz) - * @arg RCC_ADCCLK_PCLK_Div2: ADC clock = PCLK/2 - * @arg RCC_ADCCLK_PCLK_Div4: ADC clock = PCLK/4 - * @retval None - */ -void RCC_ADCCLKConfig(uint32_t RCC_ADCCLK) -{ - /* Check the parameters */ - assert_param(IS_RCC_ADCCLK(RCC_ADCCLK)); - - /* Clear ADCPRE bit */ - RCC->CFGR &= ~RCC_CFGR_ADCPRE; - /* Set ADCPRE bits according to RCC_PCLK value */ - RCC->CFGR |= RCC_ADCCLK & 0xFFFF; - - /* Clear ADCSW bit */ - RCC->CFGR3 &= ~RCC_CFGR3_ADCSW; - /* Set ADCSW bits according to RCC_ADCCLK value */ - RCC->CFGR3 |= RCC_ADCCLK >> 16; -} - -/** - * @brief Configures the CEC clock (CECCLK). - * @param RCC_CECCLK: defines the CEC clock source. This clock is derived - * from the HSI or LSE clock. - * This parameter can be one of the following values: - * @arg RCC_CECCLK_HSI_Div244: CEC clock = HSI/244 (32768Hz) - * @arg RCC_CECCLK_LSE: CEC clock = LSE - * @retval None - */ -void RCC_CECCLKConfig(uint32_t RCC_CECCLK) -{ - /* Check the parameters */ - assert_param(IS_RCC_CECCLK(RCC_CECCLK)); - - /* Clear CECSW bit */ - RCC->CFGR3 &= ~RCC_CFGR3_CECSW; - /* Set CECSW bits according to RCC_CECCLK value */ - RCC->CFGR3 |= RCC_CECCLK; -} - -/** - * @brief Configures the I2C1 clock (I2C1CLK). - * @param RCC_I2CCLK: defines the I2C1 clock source. This clock is derived - * from the HSI or System clock. - * This parameter can be one of the following values: - * @arg RCC_I2C1CLK_HSI: I2C1 clock = HSI - * @arg RCC_I2C1CLK_SYSCLK: I2C1 clock = System Clock - * @retval None - */ -void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK) -{ - /* Check the parameters */ - assert_param(IS_RCC_I2CCLK(RCC_I2CCLK)); - - /* Clear I2CSW bit */ - RCC->CFGR3 &= ~RCC_CFGR3_I2C1SW; - /* Set I2CSW bits according to RCC_I2CCLK value */ - RCC->CFGR3 |= RCC_I2CCLK; -} - -/** - * @brief Configures the USART1 clock (USART1CLK). - * @param RCC_USARTCLK: defines the USART clock source. This clock is derived - * from the HSI or System clock. - * This parameter can be one of the following values: - * @arg RCC_USART1CLK_PCLK: USART1 clock = APB Clock (PCLK) - * @arg RCC_USART1CLK_SYSCLK: USART1 clock = System Clock - * @arg RCC_USART1CLK_LSE: USART1 clock = LSE Clock - * @arg RCC_USART1CLK_HSI: USART1 clock = HSI Clock - * @arg RCC_USART2CLK_PCLK: USART2 clock = APB Clock (PCLK), applicable only for STM32F072 and STM32F091 devices - * @arg RCC_USART2CLK_SYSCLK: USART2 clock = System Clock, applicable only for STM32F072 and STM32F091 devices - * @arg RCC_USART2CLK_LSE: USART2 clock = LSE Clock, applicable only for STM32F072 and STM32F091 devices - * @arg RCC_USART2CLK_HSI: USART2 clock = HSI Clock, applicable only for STM32F072 and STM32F091 devices - * @arg RCC_USART3CLK_PCLK: USART3 clock = APB Clock (PCLK), applicable only for STM32F091 devices - * @arg RCC_USART3CLK_SYSCLK: USART3 clock = System Clock, applicable only for STM32F091 devices - * @arg RCC_USART3CLK_LSE: USART3 clock = LSE Clock, applicable only for STM32F091 devices - * @arg RCC_USART3CLK_HSI: USART3 clock = HSI Clock, applicable only for STM32F091 devices - * @retval None - */ -void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_RCC_USARTCLK(RCC_USARTCLK)); - - /* Get USART index */ - tmp = (RCC_USARTCLK >> 28); - - /* Clear USARTSW[1:0] bit */ - if (tmp == (uint32_t)0x00000001) - { - /* Clear USART1SW[1:0] bit */ - RCC->CFGR3 &= ~RCC_CFGR3_USART1SW; - } - else if (tmp == (uint32_t)0x00000002) - { - /* Clear USART2SW[1:0] bit */ - RCC->CFGR3 &= ~RCC_CFGR3_USART2SW; - } - else - { - /* Clear USART3SW[1:0] bit */ - RCC->CFGR3 &= ~RCC_CFGR3_USART3SW; - } - - /* Set USARTxSW bits according to RCC_USARTCLK value */ - RCC->CFGR3 |= RCC_USARTCLK; -} - -/** - * @brief Configures the USB clock (USBCLK). - * This function is only applicable for STM32F072 devices. - * @param RCC_USBCLK: defines the USB clock source. This clock is derived - * from the HSI48 or system clock. - * This parameter can be one of the following values: - * @arg RCC_USBCLK_HSI48: USB clock = HSI48 - * @arg RCC_USBCLK_PLLCLK: USB clock = PLL clock - * @retval None - */ -void RCC_USBCLKConfig(uint32_t RCC_USBCLK) -{ - /* Check the parameters */ - assert_param(IS_RCC_USBCLK(RCC_USBCLK)); - - /* Clear USBSW bit */ - RCC->CFGR3 &= ~RCC_CFGR3_USBSW; - /* Set USBSW bits according to RCC_USBCLK value */ - RCC->CFGR3 |= RCC_USBCLK; -} - -/** - * @brief Returns the frequencies of the System, AHB and APB busses clocks. - * @note The frequency returned by this function is not the real frequency - * in the chip. It is calculated based on the predefined constant and - * the source selected by RCC_SYSCLKConfig(): - * - * @note If SYSCLK source is HSI, function returns constant HSI_VALUE(*) - * - * @note If SYSCLK source is HSE, function returns constant HSE_VALUE(**) - * - * @note If SYSCLK source is PLL, function returns constant HSE_VALUE(**) - * or HSI_VALUE(*) multiplied by the PLL factors. - * - * @note If SYSCLK source is HSI48, function returns constant HSI48_VALUE(***) - * - * @note (*) HSI_VALUE is a constant defined in stm32f0xx.h file (default value - * 8 MHz) but the real value may vary depending on the variations - * in voltage and temperature, refer to RCC_AdjustHSICalibrationValue(). - * - * @note (**) HSE_VALUE is a constant defined in stm32f0xx.h file (default value - * 8 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * return wrong result. - * - * @note (***) HSI48_VALUE is a constant defined in stm32f0xx.h file (default value - * 48 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * @note The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold - * the clocks frequencies. - * - * @note This function can be used by the user application to compute the - * baudrate for the communication peripherals or configure other parameters. - * @note Each time SYSCLK, HCLK and/or PCLK clock changes, this function - * must be called to update the structure's field. Otherwise, any - * configuration based on this function will be incorrect. - * - * @retval None - */ -void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) -{ - uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0, presc = 0, pllclk = 0; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* HSI used as system clock */ - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - break; - case 0x04: /* HSE used as system clock */ - RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; - break; - case 0x08: /* PLL used as system clock */ - /* Get PLL clock source and multiplication factor ----------------------*/ - pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; - pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; - pllmull = ( pllmull >> 18) + 2; - - if (pllsource == 0x00) - { - /* HSI oscillator clock divided by 2 selected as PLL clock entry */ - pllclk = (HSI_VALUE >> 1) * pllmull; - } - else - { - prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; - /* HSE oscillator clock selected as PREDIV1 clock entry */ - pllclk = (HSE_VALUE / prediv1factor) * pllmull; - } - RCC_Clocks->SYSCLK_Frequency = pllclk; - break; - case 0x0C: /* HSI48 used as system clock */ - RCC_Clocks->SYSCLK_Frequency = HSI48_VALUE; - break; - default: /* HSI used as system clock */ - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - break; - } - /* Compute HCLK, PCLK clocks frequencies -----------------------------------*/ - /* Get HCLK prescaler */ - tmp = RCC->CFGR & RCC_CFGR_HPRE; - tmp = tmp >> 4; - presc = APBAHBPrescTable[tmp]; - /* HCLK clock frequency */ - RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; - - /* Get PCLK prescaler */ - tmp = RCC->CFGR & RCC_CFGR_PPRE; - tmp = tmp >> 8; - presc = APBAHBPrescTable[tmp]; - /* PCLK clock frequency */ - RCC_Clocks->PCLK_Frequency = RCC_Clocks->HCLK_Frequency >> presc; - - /* ADCCLK clock frequency */ - if((RCC->CFGR3 & RCC_CFGR3_ADCSW) != RCC_CFGR3_ADCSW) - { - /* ADC Clock is HSI14 Osc. */ - RCC_Clocks->ADCCLK_Frequency = HSI14_VALUE; - } - else - { - if((RCC->CFGR & RCC_CFGR_ADCPRE) != RCC_CFGR_ADCPRE) - { - /* ADC Clock is derived from PCLK/2 */ - RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK_Frequency >> 1; - } - else - { - /* ADC Clock is derived from PCLK/4 */ - RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK_Frequency >> 2; - } - - } - - /* CECCLK clock frequency */ - if((RCC->CFGR3 & RCC_CFGR3_CECSW) != RCC_CFGR3_CECSW) - { - /* CEC Clock is HSI/244 */ - RCC_Clocks->CECCLK_Frequency = HSI_VALUE / 244; - } - else - { - /* CECC Clock is LSE Osc. */ - RCC_Clocks->CECCLK_Frequency = LSE_VALUE; - } - - /* I2C1CLK clock frequency */ - if((RCC->CFGR3 & RCC_CFGR3_I2C1SW) != RCC_CFGR3_I2C1SW) - { - /* I2C1 Clock is HSI Osc. */ - RCC_Clocks->I2C1CLK_Frequency = HSI_VALUE; - } - else - { - /* I2C1 Clock is System Clock */ - RCC_Clocks->I2C1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency; - } - - /* USART1CLK clock frequency */ - if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == 0x0) - { - /* USART1 Clock is PCLK */ - RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->PCLK_Frequency; - } - else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW_0) - { - /* USART1 Clock is System Clock */ - RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency; - } - else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW_1) - { - /* USART1 Clock is LSE Osc. */ - RCC_Clocks->USART1CLK_Frequency = LSE_VALUE; - } - else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW) - { - /* USART1 Clock is HSI Osc. */ - RCC_Clocks->USART1CLK_Frequency = HSI_VALUE; - } - - /* USART2CLK clock frequency */ - if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == 0x0) - { - /* USART Clock is PCLK */ - RCC_Clocks->USART2CLK_Frequency = RCC_Clocks->PCLK_Frequency; - } - else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW_0) - { - /* USART Clock is System Clock */ - RCC_Clocks->USART2CLK_Frequency = RCC_Clocks->SYSCLK_Frequency; - } - else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW_1) - { - /* USART Clock is LSE Osc. */ - RCC_Clocks->USART2CLK_Frequency = LSE_VALUE; - } - else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW) - { - /* USART Clock is HSI Osc. */ - RCC_Clocks->USART2CLK_Frequency = HSI_VALUE; - } - - /* USART3CLK clock frequency */ - if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == 0x0) - { - /* USART Clock is PCLK */ - RCC_Clocks->USART3CLK_Frequency = RCC_Clocks->PCLK_Frequency; - } - else if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == RCC_CFGR3_USART3SW_0) - { - /* USART Clock is System Clock */ - RCC_Clocks->USART3CLK_Frequency = RCC_Clocks->SYSCLK_Frequency; - } - else if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == RCC_CFGR3_USART3SW_1) - { - /* USART Clock is LSE Osc. */ - RCC_Clocks->USART3CLK_Frequency = LSE_VALUE; - } - else if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == RCC_CFGR3_USART3SW) - { - /* USART Clock is HSI Osc. */ - RCC_Clocks->USART3CLK_Frequency = HSI_VALUE; - } - - /* USBCLK clock frequency */ - if((RCC->CFGR3 & RCC_CFGR3_USBSW) != RCC_CFGR3_USBSW) - { - /* USB Clock is HSI48 */ - RCC_Clocks->USBCLK_Frequency = HSI48_VALUE; - } - else - { - /* USB Clock is PLL clock */ - RCC_Clocks->USBCLK_Frequency = pllclk; - } -} - -/** - * @} - */ - -/** @defgroup RCC_Group3 Peripheral clocks configuration functions - * @brief Peripheral clocks configuration functions - * -@verbatim - =============================================================================== - #####Peripheral clocks configuration functions ##### - =============================================================================== - - [..] This section provide functions allowing to configure the Peripheral clocks. - (#) The RTC clock which is derived from the LSE, LSI or HSE_Div32 (HSE - divided by 32). - (#) After restart from Reset or wakeup from STANDBY, all peripherals are off - except internal SRAM, Flash and SWD. Before to start using a peripheral you - have to enable its interface clock. You can do this using RCC_AHBPeriphClockCmd(), - RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions. - (#) To reset the peripherals configuration (to the default state after device reset) - you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and - RCC_APB1PeriphResetCmd() functions. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the RTC clock (RTCCLK). - * @note As the RTC clock configuration bits are in the Backup domain and write - * access is denied to this domain after reset, you have to enable write - * access using PWR_BackupAccessCmd(ENABLE) function before to configure - * the RTC clock source (to be done once after reset). - * @note Once the RTC clock is configured it can't be changed unless the RTC - * is reset using RCC_BackupResetCmd function, or by a Power On Reset (POR) - * - * @param RCC_RTCCLKSource: specifies the RTC clock source. - * This parameter can be one of the following values: - * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock - * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock - * @arg RCC_RTCCLKSource_HSE_Div32: HSE divided by 32 selected as RTC clock - * - * @note If the LSE or LSI is used as RTC clock source, the RTC continues to - * work in STOP and STANDBY modes, and can be used as wakeup source. - * However, when the HSE clock is used as RTC clock source, the RTC - * cannot be used in STOP and STANDBY modes. - * - * @note The maximum input clock frequency for RTC is 2MHz (when using HSE as - * RTC clock source). - * - * @retval None - */ -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); - - /* Select the RTC clock source */ - RCC->BDCR |= RCC_RTCCLKSource; -} - -/** - * @brief Enables or disables the RTC clock. - * @note This function must be used only after the RTC clock source was selected - * using the RCC_RTCCLKConfig function. - * @param NewState: new state of the RTC clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_RTCCLKCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->BDCR |= RCC_BDCR_RTCEN; - } - else - { - RCC->BDCR &= ~RCC_BDCR_RTCEN; - } -} - -/** - * @brief Forces or releases the Backup domain reset. - * @note This function resets the RTC peripheral (including the backup registers) - * and the RTC clock source selection in RCC_BDCR register. - * @param NewState: new state of the Backup domain reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_BackupResetCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->BDCR |= RCC_BDCR_BDRST; - } - else - { - RCC->BDCR &= ~RCC_BDCR_BDRST; - } -} - -/** - * @brief Enables or disables the AHB peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_AHBPeriph_GPIOA: GPIOA clock - * @arg RCC_AHBPeriph_GPIOB: GPIOB clock - * @arg RCC_AHBPeriph_GPIOC: GPIOC clock - * @arg RCC_AHBPeriph_GPIOD: GPIOD clock - * @arg RCC_AHBPeriph_GPIOE: GPIOE clock, applicable only for STM32F072 devices - * @arg RCC_AHBPeriph_GPIOF: GPIOF clock - * @arg RCC_AHBPeriph_TS: TS clock - * @arg RCC_AHBPeriph_CRC: CRC clock - * @arg RCC_AHBPeriph_FLITF: (has effect only when the Flash memory is in power down mode) - * @arg RCC_AHBPeriph_SRAM: SRAM clock - * @arg RCC_AHBPeriph_DMA1: DMA1 clock - * @arg RCC_AHBPeriph_DMA2: DMA2 clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHBENR |= RCC_AHBPeriph; - } - else - { - RCC->AHBENR &= ~RCC_AHBPeriph; - } -} - -/** - * @brief Enables or disables the High Speed APB (APB2) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock - * @arg RCC_APB2Periph_USART6: USART6 clock - * @arg RCC_APB2Periph_USART7: USART7 clock - * @arg RCC_APB2Periph_USART8: USART8 clock - * @arg RCC_APB2Periph_ADC1: ADC1 clock - * @arg RCC_APB2Periph_TIM1: TIM1 clock - * @arg RCC_APB2Periph_SPI1: SPI1 clock - * @arg RCC_APB2Periph_USART1: USART1 clock - * @arg RCC_APB2Periph_TIM15: TIM15 clock - * @arg RCC_APB2Periph_TIM16: TIM16 clock - * @arg RCC_APB2Periph_TIM17: TIM17 clock - * @arg RCC_APB2Periph_DBGMCU: DBGMCU clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->APB2ENR |= RCC_APB2Periph; - } - else - { - RCC->APB2ENR &= ~RCC_APB2Periph; - } -} - -/** - * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB1Periph_TIM2: TIM2 clock, applicable only for STM32F051 and STM32F072 devices - * @arg RCC_APB1Periph_TIM3: TIM3 clock - * @arg RCC_APB1Periph_TIM6: TIM6 clock - * @arg RCC_APB1Periph_TIM7: TIM7 clock, applicable only for STM32F072 devices - * @arg RCC_APB1Periph_TIM14: TIM14 clock - * @arg RCC_APB1Periph_WWDG: WWDG clock - * @arg RCC_APB1Periph_SPI2: SPI2 clock - * @arg RCC_APB1Periph_USART2: USART2 clock - * @arg RCC_APB1Periph_USART3: USART3 clock, applicable only for STM32F072 and STM32F091 devices - * @arg RCC_APB1Periph_USART4: USART4 clock, applicable only for STM32F072 and STM32F091 devices - * @arg RCC_APB1Periph_USART5: USART5 clock, applicable only for STM32F091 devices - * @arg RCC_APB1Periph_I2C1: I2C1 clock - * @arg RCC_APB1Periph_I2C2: I2C2 clock - * @arg RCC_APB1Periph_USB: USB clock, applicable only for STM32F042 and STM32F072 devices - * @arg RCC_APB1Periph_CAN: CAN clock, applicable only for STM32F042 and STM32F072 devices - * @arg RCC_APB1Periph_CRS: CRS clock , applicable only for STM32F042 and STM32F072 devices - * @arg RCC_APB1Periph_PWR: PWR clock - * @arg RCC_APB1Periph_DAC: DAC clock, applicable only for STM32F051 and STM32F072 devices - * @arg RCC_APB1Periph_CEC: CEC clock, applicable only for STM32F051, STM32F042 and STM32F072 devices - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->APB1ENR |= RCC_APB1Periph; - } - else - { - RCC->APB1ENR &= ~RCC_APB1Periph; - } -} - -/** - * @brief Forces or releases AHB peripheral reset. - * @param RCC_AHBPeriph: specifies the AHB peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_AHBPeriph_GPIOA: GPIOA clock - * @arg RCC_AHBPeriph_GPIOB: GPIOB clock - * @arg RCC_AHBPeriph_GPIOC: GPIOC clock - * @arg RCC_AHBPeriph_GPIOD: GPIOD clock - * @arg RCC_AHBPeriph_GPIOE: GPIOE clock, applicable only for STM32F072 devices - * @arg RCC_AHBPeriph_GPIOF: GPIOF clock - * @arg RCC_AHBPeriph_TS: TS clock - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB_RST_PERIPH(RCC_AHBPeriph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHBRSTR |= RCC_AHBPeriph; - } - else - { - RCC->AHBRSTR &= ~RCC_AHBPeriph; - } -} - -/** - * @brief Forces or releases High Speed APB (APB2) peripheral reset. - * @param RCC_APB2Periph: specifies the APB2 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock - * @arg RCC_APB2Periph_USART6: USART6 clock - * @arg RCC_APB2Periph_USART7: USART7 clock - * @arg RCC_APB2Periph_USART8: USART8 clock - * @arg RCC_APB2Periph_ADC1: ADC1 clock - * @arg RCC_APB2Periph_TIM1: TIM1 clock - * @arg RCC_APB2Periph_SPI1: SPI1 clock - * @arg RCC_APB2Periph_USART1: USART1 clock - * @arg RCC_APB2Periph_TIM15: TIM15 clock - * @arg RCC_APB2Periph_TIM16: TIM16 clock - * @arg RCC_APB2Periph_TIM17: TIM17 clock - * @arg RCC_APB2Periph_DBGMCU: DBGMCU clock - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->APB2RSTR |= RCC_APB2Periph; - } - else - { - RCC->APB2RSTR &= ~RCC_APB2Periph; - } -} - -/** - * @brief Forces or releases Low Speed APB (APB1) peripheral reset. - * @param RCC_APB1Periph: specifies the APB1 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_APB1Periph_TIM2: TIM2 clock, applicable only for STM32F051 and STM32F072 devices - * @arg RCC_APB1Periph_TIM3: TIM3 clock - * @arg RCC_APB1Periph_TIM6: TIM6 clock - * @arg RCC_APB1Periph_TIM7: TIM7 clock, applicable only for STM32F072 devices - * @arg RCC_APB1Periph_TIM14: TIM14 clock - * @arg RCC_APB1Periph_WWDG: WWDG clock - * @arg RCC_APB1Periph_SPI2: SPI2 clock - * @arg RCC_APB1Periph_USART2: USART2 clock - * @arg RCC_APB1Periph_USART3: USART3 clock, applicable only for STM32F072 and STM32F091 devices - * @arg RCC_APB1Periph_USART4: USART4 clock, applicable only for STM32F072 and STM32F091 devices - * @arg RCC_APB1Periph_USART5: USART5 clock, applicable only for STM32F091 devices - * @arg RCC_APB1Periph_I2C1: I2C1 clock - * @arg RCC_APB1Periph_I2C2: I2C2 clock - * @arg RCC_APB1Periph_USB: USB clock, applicable only for STM32F042 and STM32F072 devices - * @arg RCC_APB1Periph_CAN: CAN clock, applicable only for STM32F042 and STM32F072 devices - * @arg RCC_APB1Periph_CRS: CRS clock , applicable only for STM32F042 and STM32F072 devices - * @arg RCC_APB1Periph_PWR: PWR clock - * @arg RCC_APB1Periph_DAC: DAC clock, applicable only for STM32F051 and STM32F072 devices - * @arg RCC_APB1Periph_CEC: CEC clock, applicable only for STM32F051, STM32F042 and STM32F072 devices - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->APB1RSTR |= RCC_APB1Periph; - } - else - { - RCC->APB1RSTR &= ~RCC_APB1Periph; - } -} - -/** - * @} - */ - -/** @defgroup RCC_Group4 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified RCC interrupts. - * @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled - * and if the HSE clock fails, the CSS interrupt occurs and an NMI is - * automatically generated. The NMI will be executed indefinitely, and - * since NMI has higher priority than any other IRQ (and main program) - * the application will be stacked in the NMI ISR unless the CSS interrupt - * pending bit is cleared. - * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt - * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt, applicable only for STM32F072 devices - * @param NewState: new state of the specified RCC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_IT(RCC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Perform Byte access to RCC_CIR[13:8] bits to enable the selected interrupts */ - *(__IO uint8_t *) CIR_BYTE1_ADDRESS |= RCC_IT; - } - else - { - /* Perform Byte access to RCC_CIR[13:8] bits to disable the selected interrupts */ - *(__IO uint8_t *) CIR_BYTE1_ADDRESS &= (uint8_t)~RCC_IT; - } -} - -/** - * @brief Checks whether the specified RCC flag is set or not. - * @param RCC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready - * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready - * @arg RCC_FLAG_PLLRDY: PLL clock ready - * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready - * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready - * @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset - * @arg RCC_FLAG_PINRST: Pin reset - * @arg RCC_FLAG_V18PWRRSTF: V1.8 power domain reset - * @arg RCC_FLAG_PORRST: POR/PDR reset - * @arg RCC_FLAG_SFTRST: Software reset - * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset - * @arg RCC_FLAG_WWDGRST: Window Watchdog reset - * @arg RCC_FLAG_LPWRRST: Low Power reset - * @arg RCC_FLAG_HSI14RDY: HSI14 oscillator clock ready - * @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready, applicable only for STM32F072 devices - * @retval The new state of RCC_FLAG (SET or RESET). - */ -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) -{ - uint32_t tmp = 0; - uint32_t statusreg = 0; - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_RCC_FLAG(RCC_FLAG)); - - /* Get the RCC register index */ - tmp = RCC_FLAG >> 5; - - if (tmp == 0) /* The flag to check is in CR register */ - { - statusreg = RCC->CR; - } - else if (tmp == 1) /* The flag to check is in BDCR register */ - { - statusreg = RCC->BDCR; - } - else if (tmp == 2) /* The flag to check is in CSR register */ - { - statusreg = RCC->CSR; - } - else /* The flag to check is in CR2 register */ - { - statusreg = RCC->CR2; - } - - /* Get the flag position */ - tmp = RCC_FLAG & FLAG_MASK; - - if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the RCC reset flags. - * The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_V18PWRRSTF, - * RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, - * RCC_FLAG_LPWRRST. - * @param None - * @retval None - */ -void RCC_ClearFlag(void) -{ - /* Set RMVF bit to clear the reset flags */ - RCC->CSR |= RCC_CSR_RMVF; -} - -/** - * @brief Checks whether the specified RCC interrupt has occurred or not. - * @param RCC_IT: specifies the RCC interrupt source to check. - * This parameter can be one of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt - * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt, applicable only for STM32F072 devices - * @arg RCC_IT_CSS: Clock Security System interrupt - * @retval The new state of RCC_IT (SET or RESET). - */ -ITStatus RCC_GetITStatus(uint8_t RCC_IT) -{ - ITStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_RCC_GET_IT(RCC_IT)); - - /* Check the status of the specified RCC interrupt */ - if ((RCC->CIR & RCC_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the RCC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the RCC's interrupt pending bits. - * @param RCC_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt, applicable only for STM32F072 devices - * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt - * @arg RCC_IT_CSS: Clock Security System interrupt - * @retval None - */ -void RCC_ClearITPendingBit(uint8_t RCC_IT) -{ - /* Check the parameters */ - assert_param(IS_RCC_CLEAR_IT(RCC_IT)); - - /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt - pending bits */ - *(__IO uint8_t *) CIR_BYTE2_ADDRESS = RCC_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_rtc.c b/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_rtc.c deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_rtc.c +++ /dev/null @@ -1,2518 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_rtc.c - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the Real-Time Clock (RTC) peripheral: - * + Initialization - * + Calendar (Time and Date) configuration - * + Alarms (Alarm A) configuration - * + Daylight Saving configuration - * + Output pin Configuration - * + Digital Calibration configuration - * + TimeStamp configuration - * + Tampers configuration - * + Backup Data Registers configuration - * + Output Type Config configuration - * + Shift control synchronisation - * + Interrupts and flags management - * - @verbatim - =============================================================================== - ##### Backup Domain Operating Condition ##### - =============================================================================== - [..] The real-time clock (RTC) and the RTC backup registers can be powered - from the VBAT voltage when the main VDD supply is powered off. - To retain the content of the RTC backup registers and supply the RTC - when VDD is turned off, VBAT pin can be connected to an optional - standby voltage supplied by a battery or by another source. - - [..] To allow the RTC to operate even when the main digital supply (VDD) - is turned off, the VBAT pin powers the following blocks: - (#) The RTC - (#) The LSE oscillator - (#) PC13 to PC15 I/Os I/Os (when available) - - [..] When the backup domain is supplied by VDD (analog switch connected - to VDD), the following functions are available: - (#) PC14 and PC15 can be used as either GPIO or LSE pins - (#) PC13 can be used as a GPIO or as the RTC_AF1 pin - - [..] When the backup domain is supplied by VBAT (analog switch connected - to VBAT because VDD is not present), the following functions are available: - (#) PC14 and PC15 can be used as LSE pins only - (#) PC13 can be used as the RTC_AF1 pin - - ##### Backup Domain Reset ##### - =============================================================================== - [..] The backup domain reset sets all RTC registers and the RCC_BDCR - register to their reset values. - A backup domain reset is generated when one of the following events - occurs: - (#) Software reset, triggered by setting the BDRST bit in the - RCC Backup domain control register (RCC_BDCR). You can use the - RCC_BackupResetCmd(). - (#) VDD or VBAT power on, if both supplies have previously been - powered off. - - ##### Backup Domain Access ##### - =============================================================================== - [..] After reset, the backup domain (RTC registers and RTC backup data - registers) is protected against possible unwanted write accesses. - [..] To enable access to the Backup Domain and RTC registers, proceed as follows: - (#) Enable the Power Controller (PWR) APB1 interface clock using the - RCC_APB1PeriphClockCmd() function. - (#) Enable access to Backup domain using the PWR_BackupAccessCmd() function. - (#) Select the RTC clock source using the RCC_RTCCLKConfig() function. - (#) Enable RTC Clock using the RCC_RTCCLKCmd() function. - - - ##### How to use this driver ##### - =============================================================================== - [..] - (+) Enable the backup domain access (see description in the section above) - (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and - RTC hour format using the RTC_Init() function. - - ***Time and Date configuration *** - ================================== - [..] - (+) To configure the RTC Calendar (Time and Date) use the RTC_SetTime() - and RTC_SetDate() functions. - (+) To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate() - functions. - (+) To read the RTC subsecond, use the RTC_GetSubSecond() function. - (+) Use the RTC_DayLightSavingConfig() function to add or sub one - hour to the RTC Calendar. - - ***Alarm configuration *** - ========================== - [..] - (+) To configure the RTC Alarm use the RTC_SetAlarm() function. - (+) Enable the selected RTC Alarm using the RTC_AlarmCmd() function - (+) To read the RTC Alarm, use the RTC_GetAlarm() function. - (+) To read the RTC alarm SubSecond, use the RTC_GetAlarmSubSecond() function. - - ***RTC Wakeup configuration*** - ========================== - [..] - (+) Configure the RTC Wakeup Clock source use the RTC_WakeUpClockConfig() - function. - (+) Configure the RTC WakeUp Counter using the RTC_SetWakeUpCounter() - function - (+) Enable the RTC WakeUp using the RTC_WakeUpCmd() function - (+) To read the RTC WakeUp Counter register, use the RTC_GetWakeUpCounter() - function. - - ***Outputs configuration *** - ============================ - [..] The RTC has 2 different outputs: - (+) AFO_ALARM: this output is used to manage the RTC Alarm A. - To output the selected RTC signal on RTC_AF1 pin, use the - RTC_OutputConfig() function. - (+) AFO_CALIB: this output is 512Hz signal or 1Hz . - To output the RTC Clock on RTC_AF1 pin, use the RTC_CalibOutputCmd() - function. - - ***Original Digital Calibration configuration *** - ================================= - [..] Configure the RTC Original Digital Calibration Value and the corresponding - calibration cycle period (32s,16s and 8s) using the RTC_SmoothCalibConfig() - function. - - ***TimeStamp configuration *** - ============================== - [..] - (+) Configure the RTC_AF1 trigger and enables the RTC TimeStamp - using the RTC_TimeStampCmd() function. - (+) To read the RTC TimeStamp Time and Date register, use the - RTC_GetTimeStamp() function. - (+) To read the RTC TimeStamp SubSecond register, use the - RTC_GetTimeStampSubSecond() function. - - ***Tamper configuration *** - =========================== - [..] - (+) Configure the Tamper filter count using RTC_TamperFilterConfig() - function. - (+) Configure the RTC Tamper trigger Edge or Level according to the Tamper - filter (if equal to 0 Edge else Level) value using the RTC_TamperConfig() function - (+) Configure the Tamper sampling frequency using RTC_TamperSamplingFreqConfig() - function. - (+) Configure the Tamper precharge or discharge duration using - RTC_TamperPinsPrechargeDuration() function. - (+) Enable the Tamper Pull-UP using RTC_TamperPullUpDisableCmd() function. - (+) Enable the RTC Tamper using the RTC_TamperCmd() function. - (+) Enable the Time stamp on Tamper detection event using - RTC_TSOnTamperDetecCmd() function. - - ***Backup Data Registers configuration *** - ========================================== - [..] - (+) To write to the RTC Backup Data registers, use the RTC_WriteBackupRegister() - function. - (+) To read the RTC Backup Data registers, use the RTC_ReadBackupRegister() - function. - - ##### RTC and low power modes ##### - =============================================================================== - [..] The MCU can be woken up from a low power mode by an RTC alternate - function. - [..] The RTC alternate functions are the RTC alarm (Alarm A), RTC tamper - event detection and RTC time stamp event detection. - These RTC alternate functions can wake up the system from the Stop - and Standby lowpower modes. - The system can also wake up from low power modes without depending - on an external interrupt (Auto-wakeup mode), by using the RTC alarm events. - [..] The RTC provides a programmable time base for waking up from the - Stop or Standby mode at regular intervals. - Wakeup from STOP and Standby modes is possible only when the RTC - clock source is LSE or LSI. - - ##### Selection of RTC_AF1 alternate functions ##### - =============================================================================== - [..] The RTC_AF1 pin (PC13) can be used for the following purposes: - (+) AFO_ALARM output - (+) AFO_CALIB output - (+) AFI_TAMPER - (+) AFI_TIMESTAMP - - +------------------------------------------------------------------------------------------+ - | Pin |AFO_ALARM |AFO_CALIB |AFI_TAMPER |AFI_TIMESTAMP | WKUP2 |ALARMOUTTYPE | - | configuration | ENABLED | ENABLED | ENABLED | ENABLED |ENABLED | AFO_ALARM | - | and function | | | | | |Configuration | - |-----------------|----------|----------|-----------|--------------|--------|--------------| - | Alarm out | | | | | Don't | | - | output OD | 1 | 0 |Don't care | Don't care | care | 0 | - |-----------------|----------|----------|-----------|--------------|--------|--------------| - | Alarm out | | | | | Don't | | - | output PP | 1 | 0 |Don't care | Don't care | care | 1 | - |-----------------|----------|----------|-----------|--------------|--------|--------------| - | Calibration out | | | | | Don't | | - | output PP | 0 | 1 |Don't care | Don't care | care | Don't care | - |-----------------|----------|----------|-----------|--------------|--------|--------------| - | TAMPER input | | | | | Don't | | - | floating | 0 | 0 | 1 | 0 | care | Don't care | - |-----------------|----------|----------|-----------|--------------|--------|--------------| - | TIMESTAMP and | | | | | Don't | | - | TAMPER input | 0 | 0 | 1 | 1 | care | Don't care | - | floating | | | | | | | - |-----------------|----------|----------|-----------|--------------|--------|--------------| - | TIMESTAMP input | | | | | Don't | | - | floating | 0 | 0 | 0 | 1 | care | Don't care | - |-----------------|----------|----------|-----------|--------------|--------|--------------| - | Wakeup Pin 2 | 0 | 0 | 0 | 0 | 1 | Don't care | - |-----------------|----------|----------|-----------|--------------|--------|--------------| - | Standard GPIO | 0 | 0 | 0 | 0 | 0 | Don't care | - +------------------------------------------------------------------------------------------+ - - @endverbatim - - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_rtc.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup RTC - * @brief RTC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* Masks Definition */ -#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F) -#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F) -#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF) -#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F) -#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_ALRAF | \ - RTC_FLAG_RSF | RTC_FLAG_INITS |RTC_FLAG_INITF | \ - RTC_FLAG_TAMP1F | RTC_FLAG_TAMP2F | RTC_FLAG_RECALPF | \ - RTC_FLAG_SHPF)) - -#define INITMODE_TIMEOUT ((uint32_t) 0x00004000) -#define SYNCHRO_TIMEOUT ((uint32_t) 0x00008000) -#define RECALPF_TIMEOUT ((uint32_t) 0x00001000) -#define SHPF_TIMEOUT ((uint32_t) 0x00001000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -static uint8_t RTC_ByteToBcd2(uint8_t Value); -static uint8_t RTC_Bcd2ToByte(uint8_t Value); - -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup RTC_Private_Functions - * @{ - */ - -/** @defgroup RTC_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - - [..] This section provide functions allowing to initialize and configure the RTC - Prescaler (Synchronous and Asynchronous), RTC Hour format, disable RTC registers - Write protection, enter and exit the RTC initialization mode, RTC registers - synchronization check and reference clock detection enable. - - (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. - It is split into 2 programmable prescalers to minimize power consumption. - (++) A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler. - (++) When both prescalers are used, it is recommended to configure the - asynchronous prescaler to a high value to minimize consumption. - (#) All RTC registers are Write protected. Writing to the RTC registers - is enabled by writing a key into the Write Protection register, RTC_WPR. - (#) To Configure the RTC Calendar, user application should enter - initialization mode. In this mode, the calendar counter is stopped - and its value can be updated. When the initialization sequence is - complete, the calendar restarts counting after 4 RTCCLK cycles. - (#) To read the calendar through the shadow registers after Calendar - initialization, calendar update or after wakeup from low power modes - the software must first clear the RSF flag. The software must then - wait until it is set again before reading the calendar, which means - that the calendar registers have been correctly copied into the - RTC_TR and RTC_DR shadow registers.The RTC_WaitForSynchro() function - implements the above software sequence (RSF clear and RSF check). - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the RTC registers to their default reset values. - * @note This function doesn't reset the RTC Clock source and RTC Backup Data - * registers. - * @param None - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC registers are deinitialized - * - ERROR: RTC registers are not deinitialized - */ -ErrorStatus RTC_DeInit(void) -{ - ErrorStatus status = ERROR; - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Reset TR, DR and CR registers */ - RTC->TR = (uint32_t)0x00000000; - RTC->WUTR = (uint32_t)0x0000FFFF; - RTC->DR = (uint32_t)0x00002101; - RTC->CR &= (uint32_t)0x00000000; - RTC->PRER = (uint32_t)0x007F00FF; - RTC->ALRMAR = (uint32_t)0x00000000; - RTC->SHIFTR = (uint32_t)0x00000000; - RTC->CALR = (uint32_t)0x00000000; - RTC->ALRMASSR = (uint32_t)0x00000000; - - /* Reset ISR register and exit initialization mode */ - RTC->ISR = (uint32_t)0x00000000; - - /* Reset Tamper and alternate functions configuration register */ - RTC->TAFCR = 0x00000000; - - /* Wait till the RTC RSF flag is set */ - if (RTC_WaitForSynchro() == ERROR) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Initializes the RTC registers according to the specified parameters - * in RTC_InitStruct. - * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure that contains - * the configuration information for the RTC peripheral. - * @note The RTC Prescaler register is write protected and can be written in - * initialization mode only. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC registers are initialized - * - ERROR: RTC registers are not initialized - */ -ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct) -{ - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat)); - assert_param(IS_RTC_ASYNCH_PREDIV(RTC_InitStruct->RTC_AsynchPrediv)); - assert_param(IS_RTC_SYNCH_PREDIV(RTC_InitStruct->RTC_SynchPrediv)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Clear RTC CR FMT Bit */ - RTC->CR &= ((uint32_t)~(RTC_CR_FMT)); - /* Set RTC_CR register */ - RTC->CR |= ((uint32_t)(RTC_InitStruct->RTC_HourFormat)); - - /* Configure the RTC PRER */ - RTC->PRER = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv); - RTC->PRER |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16); - - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - status = SUCCESS; - } - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Fills each RTC_InitStruct member with its default value. - * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure which will be - * initialized. - * @retval None - */ -void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct) -{ - /* Initialize the RTC_HourFormat member */ - RTC_InitStruct->RTC_HourFormat = RTC_HourFormat_24; - - /* Initialize the RTC_AsynchPrediv member */ - RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F; - - /* Initialize the RTC_SynchPrediv member */ - RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF; -} - -/** - * @brief Enables or disables the RTC registers write protection. - * @note All the RTC registers are write protected except for RTC_ISR[13:8], - * RTC_TAFCR and RTC_BKPxR. - * @note Writing a wrong key reactivates the write protection. - * @note The protection mechanism is not affected by system reset. - * @param NewState: new state of the write protection. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_WriteProtectionCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - } - else - { - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - } -} - -/** - * @brief Enters the RTC Initialization mode. - * @note The RTC Initialization mode is write protected, use the - * RTC_WriteProtectionCmd(DISABLE) before calling this function. - * @param None - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC is in Init mode - * - ERROR: RTC is not in Init mode - */ -ErrorStatus RTC_EnterInitMode(void) -{ - __IO uint32_t initcounter = 0x00; - ErrorStatus status = ERROR; - uint32_t initstatus = 0x00; - - /* Check if the Initialization mode is set */ - if ((RTC->ISR & RTC_ISR_INITF) == (uint32_t)RESET) - { - /* Set the Initialization mode */ - RTC->ISR = (uint32_t)RTC_INIT_MASK; - - /* Wait till RTC is in INIT state and if Time out is reached exit */ - do - { - initstatus = RTC->ISR & RTC_ISR_INITF; - initcounter++; - } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00)); - - if ((RTC->ISR & RTC_ISR_INITF) != RESET) - { - status = SUCCESS; - } - else - { - status = ERROR; - } - } - else - { - status = SUCCESS; - } - - return (status); -} - -/** - * @brief Exits the RTC Initialization mode. - * @note When the initialization sequence is complete, the calendar restarts - * counting after 4 RTCCLK cycles. - * @note The RTC Initialization mode is write protected, use the - * RTC_WriteProtectionCmd(DISABLE) before calling this function. - * @param None - * @retval None - */ -void RTC_ExitInitMode(void) -{ - /* Exit Initialization mode */ - RTC->ISR &= (uint32_t)~RTC_ISR_INIT; -} - -/** - * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are - * synchronized with RTC APB clock. - * @note The RTC Resynchronization mode is write protected, use the - * RTC_WriteProtectionCmd(DISABLE) before calling this function. - * @note To read the calendar through the shadow registers after Calendar - * initialization, calendar update or after wakeup from low power modes - * the software must first clear the RSF flag. - * The software must then wait until it is set again before reading - * the calendar, which means that the calendar registers have been - * correctly copied into the RTC_TR and RTC_DR shadow registers. - * @param None - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC registers are synchronised - * - ERROR: RTC registers are not synchronised - */ -ErrorStatus RTC_WaitForSynchro(void) -{ - __IO uint32_t synchrocounter = 0; - ErrorStatus status = ERROR; - uint32_t synchrostatus = 0x00; - - if ((RTC->CR & RTC_CR_BYPSHAD) != RESET) - { - /* Bypass shadow mode */ - status = SUCCESS; - } - else - { - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Clear RSF flag */ - RTC->ISR &= (uint32_t)RTC_RSF_MASK; - - /* Wait the registers to be synchronised */ - do - { - synchrostatus = RTC->ISR & RTC_ISR_RSF; - synchrocounter++; - } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00)); - - if ((RTC->ISR & RTC_ISR_RSF) != RESET) - { - status = SUCCESS; - } - else - { - status = ERROR; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - } - - return (status); -} - -/** - * @brief Enables or disables the RTC reference clock detection. - * @param NewState: new state of the RTC reference clock. - * This parameter can be: ENABLE or DISABLE. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC reference clock detection is enabled - * - ERROR: RTC reference clock detection is disabled - */ -ErrorStatus RTC_RefClockCmd(FunctionalState NewState) -{ - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - if (NewState != DISABLE) - { - /* Enable the RTC reference clock detection */ - RTC->CR |= RTC_CR_REFCKON; - } - else - { - /* Disable the RTC reference clock detection */ - RTC->CR &= ~RTC_CR_REFCKON; - } - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - status = SUCCESS; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Enables or Disables the Bypass Shadow feature. - * @note When the Bypass Shadow is enabled the calendar value are taken - * directly from the Calendar counter. - * @param NewState: new state of the Bypass Shadow feature. - * This parameter can be: ENABLE or DISABLE. - * @retval None -*/ -void RTC_BypassShadowCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - if (NewState != DISABLE) - { - /* Set the BYPSHAD bit */ - RTC->CR |= (uint8_t)RTC_CR_BYPSHAD; - } - else - { - /* Reset the BYPSHAD bit */ - RTC->CR &= (uint8_t)~RTC_CR_BYPSHAD; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @} - */ - -/** @defgroup RTC_Group2 Time and Date configuration functions - * @brief Time and Date configuration functions - * -@verbatim - =============================================================================== - ##### Time and Date configuration functions ##### - =============================================================================== - [..] This section provide functions allowing to program and read the RTC - Calendar (Time and Date). - -@endverbatim - * @{ - */ - -/** - * @brief Set the RTC current time. - * @param RTC_Format: specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that contains - * the time configuration information for the RTC. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Time register is configured - * - ERROR: RTC Time register is not configured - */ -ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct) -{ - uint32_t tmpreg = 0; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - if (RTC_Format == RTC_Format_BIN) - { - if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - assert_param(IS_RTC_HOUR12(RTC_TimeStruct->RTC_Hours)); - assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); - } - else - { - RTC_TimeStruct->RTC_H12 = 0x00; - assert_param(IS_RTC_HOUR24(RTC_TimeStruct->RTC_Hours)); - } - assert_param(IS_RTC_MINUTES(RTC_TimeStruct->RTC_Minutes)); - assert_param(IS_RTC_SECONDS(RTC_TimeStruct->RTC_Seconds)); - } - else - { - if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - tmpreg = RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours); - assert_param(IS_RTC_HOUR12(tmpreg)); - assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); - } - else - { - RTC_TimeStruct->RTC_H12 = 0x00; - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours))); - } - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds))); - } - - /* Check the input parameters format */ - if (RTC_Format != RTC_Format_BIN) - { - tmpreg = (((uint32_t)(RTC_TimeStruct->RTC_Hours) << 16) | \ - ((uint32_t)(RTC_TimeStruct->RTC_Minutes) << 8) | \ - ((uint32_t)RTC_TimeStruct->RTC_Seconds) | \ - ((uint32_t)(RTC_TimeStruct->RTC_H12) << 16)); - } - else - { - tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Minutes) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Seconds)) | \ - (((uint32_t)RTC_TimeStruct->RTC_H12) << 16)); - } - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Set the RTC_TR register */ - RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); - - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if ((RTC->CR & RTC_CR_BYPSHAD) == RESET) - { - if (RTC_WaitForSynchro() == ERROR) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - else - { - status = SUCCESS; - } - - } - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Fills each RTC_TimeStruct member with its default value - * (Time = 00h:00min:00sec). - * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure which will be - * initialized. - * @retval None - */ -void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct) -{ - /* Time = 00h:00min:00sec */ - RTC_TimeStruct->RTC_H12 = RTC_H12_AM; - RTC_TimeStruct->RTC_Hours = 0; - RTC_TimeStruct->RTC_Minutes = 0; - RTC_TimeStruct->RTC_Seconds = 0; -} - -/** - * @brief Get the RTC current Time. - * @param RTC_Format: specifies the format of the returned parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that will - * contain the returned current time configuration. - * @retval None - */ -void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - /* Get the RTC_TR register */ - tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK); - - /* Fill the structure fields with the read parameters */ - RTC_TimeStruct->RTC_Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16); - RTC_TimeStruct->RTC_Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8); - RTC_TimeStruct->RTC_Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU)); - RTC_TimeStruct->RTC_H12 = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16); - - /* Check the input parameters format */ - if (RTC_Format == RTC_Format_BIN) - { - /* Convert the structure parameters to Binary format */ - RTC_TimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours); - RTC_TimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes); - RTC_TimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds); - } -} - -/** - * @brief Gets the RTC current Calendar Subseconds value. - * @note This function freeze the Time and Date registers after reading the - * SSR register. - * @param None - * @retval RTC current Calendar Subseconds value. - */ -uint32_t RTC_GetSubSecond(void) -{ - uint32_t tmpreg = 0; - - /* Get subseconds values from the correspondent registers*/ - tmpreg = (uint32_t)(RTC->SSR); - - /* Read DR register to unfroze calendar registers */ - (void) (RTC->DR); - - return (tmpreg); -} - -/** - * @brief Set the RTC current date. - * @param RTC_Format: specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains - * the date configuration information for the RTC. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Date register is configured - * - ERROR: RTC Date register is not configured - */ -ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct) -{ - uint32_t tmpreg = 0; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - if ((RTC_Format == RTC_Format_BIN) && ((RTC_DateStruct->RTC_Month & 0x10) == 0x10)) - { - RTC_DateStruct->RTC_Month = (RTC_DateStruct->RTC_Month & (uint32_t)~(0x10)) + 0x0A; - } - if (RTC_Format == RTC_Format_BIN) - { - assert_param(IS_RTC_YEAR(RTC_DateStruct->RTC_Year)); - assert_param(IS_RTC_MONTH(RTC_DateStruct->RTC_Month)); - assert_param(IS_RTC_DATE(RTC_DateStruct->RTC_Date)); - } - else - { - assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year))); - tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month); - assert_param(IS_RTC_MONTH(tmpreg)); - tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date); - assert_param(IS_RTC_DATE(tmpreg)); - } - assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->RTC_WeekDay)); - - /* Check the input parameters format */ - if (RTC_Format != RTC_Format_BIN) - { - tmpreg = ((((uint32_t)RTC_DateStruct->RTC_Year) << 16) | \ - (((uint32_t)RTC_DateStruct->RTC_Month) << 8) | \ - ((uint32_t)RTC_DateStruct->RTC_Date) | \ - (((uint32_t)RTC_DateStruct->RTC_WeekDay) << 13)); - } - else - { - tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Year) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Month) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Date)) | \ - ((uint32_t)RTC_DateStruct->RTC_WeekDay << 13)); - } - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Set the RTC_DR register */ - RTC->DR = (uint32_t)(tmpreg & RTC_DR_RESERVED_MASK); - - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if ((RTC->CR & RTC_CR_BYPSHAD) == RESET) - { - if (RTC_WaitForSynchro() == ERROR) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - else - { - status = SUCCESS; - } - } - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Fills each RTC_DateStruct member with its default value - * (Monday, January 01 xx00). - * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure which will be - * initialized. - * @retval None - */ -void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct) -{ - /* Monday, January 01 xx00 */ - RTC_DateStruct->RTC_WeekDay = RTC_Weekday_Monday; - RTC_DateStruct->RTC_Date = 1; - RTC_DateStruct->RTC_Month = RTC_Month_January; - RTC_DateStruct->RTC_Year = 0; -} - -/** - * @brief Get the RTC current date. - * @param RTC_Format: specifies the format of the returned parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that will - * contain the returned current date configuration. - * @retval None - */ -void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - /* Get the RTC_TR register */ - tmpreg = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK); - - /* Fill the structure fields with the read parameters */ - RTC_DateStruct->RTC_Year = (uint8_t)((tmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16); - RTC_DateStruct->RTC_Month = (uint8_t)((tmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8); - RTC_DateStruct->RTC_Date = (uint8_t)(tmpreg & (RTC_DR_DT | RTC_DR_DU)); - RTC_DateStruct->RTC_WeekDay = (uint8_t)((tmpreg & (RTC_DR_WDU)) >> 13); - - /* Check the input parameters format */ - if (RTC_Format == RTC_Format_BIN) - { - /* Convert the structure parameters to Binary format */ - RTC_DateStruct->RTC_Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year); - RTC_DateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month); - RTC_DateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date); - RTC_DateStruct->RTC_WeekDay = (uint8_t)(RTC_DateStruct->RTC_WeekDay); - } -} - -/** - * @} - */ - -/** @defgroup RTC_Group3 Alarms configuration functions - * @brief Alarms (Alarm A) configuration functions - * -@verbatim - =============================================================================== - ##### Alarms (Alarm A and Alarm B) configuration functions ##### - =============================================================================== - [..] This section provide functions allowing to program and read the RTC - Alarms. - -@endverbatim - * @{ - */ - -/** - * @brief Set the specified RTC Alarm. - * @note The Alarm register can only be written when the corresponding Alarm - * is disabled (Use the RTC_AlarmCmd(DISABLE)). - * @param RTC_Format: specifies the format of the returned parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_Alarm: specifies the alarm to be configured. - * This parameter can be one of the following values: - * @arg RTC_Alarm_A: to select Alarm A - * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that - * contains the alarm configuration parameters. - * @retval None - */ -void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - assert_param(IS_RTC_ALARM(RTC_Alarm)); - assert_param(IS_RTC_ALARM_MASK(RTC_AlarmStruct->RTC_AlarmMask)); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel)); - - if (RTC_Format == RTC_Format_BIN) - { - if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - assert_param(IS_RTC_HOUR12(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)); - assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12)); - } - else - { - RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00; - assert_param(IS_RTC_HOUR24(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)); - } - assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes)); - assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)); - - if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date) - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_AlarmStruct->RTC_AlarmDateWeekDay)); - } - else - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_AlarmStruct->RTC_AlarmDateWeekDay)); - } - } - else - { - if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours); - assert_param(IS_RTC_HOUR12(tmpreg)); - assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12)); - } - else - { - RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00; - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours))); - } - - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds))); - - if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date) - { - tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); - } - else - { - tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); - } - } - - /* Check the input parameters format */ - if (RTC_Format != RTC_Format_BIN) - { - tmpreg = (((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \ - ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds) | \ - ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \ - ((uint32_t)(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); - } - else - { - tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)) | \ - ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); - } - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Alarm register */ - RTC->ALRMAR = (uint32_t)tmpreg; - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Fills each RTC_AlarmStruct member with its default value - * (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask = - * all fields are masked). - * @param RTC_AlarmStruct: pointer to a @ref RTC_AlarmTypeDef structure which - * will be initialized. - * @retval None - */ -void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct) -{ - /* Alarm Time Settings : Time = 00h:00mn:00sec */ - RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = RTC_H12_AM; - RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = 0; - RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = 0; - RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = 0; - - /* Alarm Date Settings : Date = 1st day of the month */ - RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = RTC_AlarmDateWeekDaySel_Date; - RTC_AlarmStruct->RTC_AlarmDateWeekDay = 1; - - /* Alarm Masks Settings : Mask = all fields are not masked */ - RTC_AlarmStruct->RTC_AlarmMask = RTC_AlarmMask_None; -} - -/** - * @brief Get the RTC Alarm value and masks. - * @param RTC_Format: specifies the format of the output parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_Alarm: specifies the alarm to be read. - * This parameter can be one of the following values: - * @arg RTC_Alarm_A: to select Alarm A - * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that will - * contains the output alarm configuration values. - * @retval None - */ -void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - assert_param(IS_RTC_ALARM(RTC_Alarm)); - - /* Get the RTC_ALRMAR register */ - tmpreg = (uint32_t)(RTC->ALRMAR); - - /* Fill the structure with the read parameters */ - RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | \ - RTC_ALRMAR_HU)) >> 16); - RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | \ - RTC_ALRMAR_MNU)) >> 8); - RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | \ - RTC_ALRMAR_SU)); - RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16); - RTC_AlarmStruct->RTC_AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24); - RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); - RTC_AlarmStruct->RTC_AlarmMask = (uint32_t)(tmpreg & RTC_AlarmMask_All); - - if (RTC_Format == RTC_Format_BIN) - { - RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ - RTC_AlarmTime.RTC_Hours); - RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ - RTC_AlarmTime.RTC_Minutes); - RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ - RTC_AlarmTime.RTC_Seconds); - RTC_AlarmStruct->RTC_AlarmDateWeekDay = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); - } -} - -/** - * @brief Enables or disables the specified RTC Alarm. - * @param RTC_Alarm: specifies the alarm to be configured. - * This parameter can be any combination of the following values: - * @arg RTC_Alarm_A: to select Alarm A - * @param NewState: new state of the specified alarm. - * This parameter can be: ENABLE or DISABLE. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Alarm is enabled/disabled - * - ERROR: RTC Alarm is not enabled/disabled - */ -ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState) -{ - __IO uint32_t alarmcounter = 0x00; - uint32_t alarmstatus = 0x00; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_CMD_ALARM(RTC_Alarm)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Alarm state */ - if (NewState != DISABLE) - { - RTC->CR |= (uint32_t)RTC_Alarm; - - status = SUCCESS; - } - else - { - /* Disable the Alarm in RTC_CR register */ - RTC->CR &= (uint32_t)~RTC_Alarm; - - /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ - do - { - alarmstatus = RTC->ISR & (RTC_Alarm >> 8); - alarmcounter++; - } while((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00)); - - if ((RTC->ISR & (RTC_Alarm >> 8)) == RESET) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Configure the RTC AlarmA/B Subseconds value and mask. - * @note This function is performed only when the Alarm is disabled. - * @param RTC_Alarm: specifies the alarm to be configured. - * This parameter can be one of the following values: - * @arg RTC_Alarm_A: to select Alarm A - * @param RTC_AlarmSubSecondValue: specifies the Subseconds value. - * This parameter can be a value from 0 to 0x00007FFF. - * @param RTC_AlarmSubSecondMask: specifies the Subseconds Mask. - * This parameter can be any combination of the following values: - * @arg RTC_AlarmSubSecondMask_All: All Alarm SS fields are masked. - * There is no comparison on sub seconds for Alarm. - * @arg RTC_AlarmSubSecondMask_SS14_1: SS[14:1] are don't care in Alarm comparison. - * Only SS[0] is compared - * @arg RTC_AlarmSubSecondMask_SS14_2: SS[14:2] are don't care in Alarm comparison. - * Only SS[1:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_3: SS[14:3] are don't care in Alarm comparison. - * Only SS[2:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_4: SS[14:4] are don't care in Alarm comparison. - * Only SS[3:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_5: SS[14:5] are don't care in Alarm comparison. - * Only SS[4:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_6: SS[14:6] are don't care in Alarm comparison. - * Only SS[5:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_7: SS[14:7] are don't care in Alarm comparison. - * Only SS[6:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_8: SS[14:8] are don't care in Alarm comparison. - * Only SS[7:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_9: SS[14:9] are don't care in Alarm comparison. - * Only SS[8:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_10: SS[14:10] are don't care in Alarm comparison. - * Only SS[9:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_11: SS[14:11] are don't care in Alarm comparison. - * Only SS[10:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_12: SS[14:12] are don't care in Alarm comparison. - * Only SS[11:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_13: SS[14:13] are don't care in Alarm comparison. - * Only SS[12:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14: SS[14] is don't care in Alarm comparison. - * Only SS[13:0] are compared - * @arg RTC_AlarmSubSecondMask_None: SS[14:0] are compared and must match to activate alarm - * @retval None - */ -void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint8_t RTC_AlarmSubSecondMask) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_ALARM(RTC_Alarm)); - assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(RTC_AlarmSubSecondValue)); - assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(RTC_AlarmSubSecondMask)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Alarm A or Alarm B SubSecond registers */ - tmpreg = (uint32_t) (((uint32_t)(RTC_AlarmSubSecondValue)) | ((uint32_t)(RTC_AlarmSubSecondMask) << 24)); - - /* Configure the AlarmA SubSecond register */ - RTC->ALRMASSR = tmpreg; - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - -} - -/** - * @brief Gets the RTC Alarm Subseconds value. - * @param RTC_Alarm: specifies the alarm to be read. - * This parameter can be one of the following values: - * @arg RTC_Alarm_A: to select Alarm A - * @param None - * @retval RTC Alarm Subseconds value. - */ -uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm) -{ - uint32_t tmpreg = 0; - - /* Get the RTC_ALRMAR register */ - tmpreg = (uint32_t)((RTC->ALRMASSR) & RTC_ALRMASSR_SS); - - return (tmpreg); -} - -/** - * @} - */ - -/** @defgroup RTC_Group4 WakeUp Timer configuration functions - * @brief WakeUp Timer configuration functions - * -@verbatim - =============================================================================== - ##### WakeUp Timer configuration functions ##### - =============================================================================== - - [..] This section provide functions allowing to program and read the RTC WakeUp. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the RTC Wakeup clock source. - * This function is available for STM32F072 devices. - * @note The WakeUp Clock source can only be changed when the RTC WakeUp - * is disabled (Use the RTC_WakeUpCmd(DISABLE)). - * @param RTC_WakeUpClock: Wakeup Clock source. - * This parameter can be one of the following values: - * @arg RTC_WakeUpClock_RTCCLK_Div16 - * @arg RTC_WakeUpClock_RTCCLK_Div8 - * @arg RTC_WakeUpClock_RTCCLK_Div4 - * @arg RTC_WakeUpClock_RTCCLK_Div2 - * @arg RTC_WakeUpClock_CK_SPRE_16bits - * @arg RTC_WakeUpClock_CK_SPRE_17bits - * @retval None - */ -void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock) -{ - /* Check the parameters */ - assert_param(IS_RTC_WAKEUP_CLOCK(RTC_WakeUpClock)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Clear the Wakeup Timer clock source bits in CR register */ - RTC->CR &= (uint32_t)~RTC_CR_WUCKSEL; - - /* Configure the clock source */ - RTC->CR |= (uint32_t)RTC_WakeUpClock; - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Configures the RTC Wakeup counter. - * This function is available for STM32F072 devices. - * @note The RTC WakeUp counter can only be written when the RTC WakeUp - * is disabled (Use the RTC_WakeUpCmd(DISABLE)). - * @param RTC_WakeUpCounter: specifies the WakeUp counter. - * This parameter can be a value from 0x0000 to 0xFFFF. - * @retval None - */ -void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter) -{ - /* Check the parameters */ - assert_param(IS_RTC_WAKEUP_COUNTER(RTC_WakeUpCounter)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Wakeup Timer counter */ - RTC->WUTR = (uint32_t)RTC_WakeUpCounter; - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Returns the RTC WakeUp timer counter value. - * This function is available for STM32F072 devices. - * @param None - * @retval The RTC WakeUp Counter value. - */ -uint32_t RTC_GetWakeUpCounter(void) -{ - /* Get the counter value */ - return ((uint32_t)(RTC->WUTR & RTC_WUTR_WUT)); -} - -/** - * @brief Enables or Disables the RTC WakeUp timer. - * This function is available for STM32F072 devices. - * @param NewState: new state of the WakeUp timer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -ErrorStatus RTC_WakeUpCmd(FunctionalState NewState) -{ - __IO uint32_t wutcounter = 0x00; - uint32_t wutwfstatus = 0x00; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - if (NewState != DISABLE) - { - /* Enable the Wakeup Timer */ - RTC->CR |= (uint32_t)RTC_CR_WUTE; - status = SUCCESS; - } - else - { - /* Disable the Wakeup Timer */ - RTC->CR &= (uint32_t)~RTC_CR_WUTE; - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - do - { - wutwfstatus = RTC->ISR & RTC_ISR_WUTWF; - wutcounter++; - } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00)); - - if ((RTC->ISR & RTC_ISR_WUTWF) == RESET) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @} - */ - -/** @defgroup RTC_Group5 Daylight Saving configuration functions - * @brief Daylight Saving configuration functions - * -@verbatim - =============================================================================== - ##### WakeUp Timer configuration functions ##### - =============================================================================== - [..] This section provide functions allowing to program and read the RTC WakeUp. - - This section provide functions allowing to configure the RTC DayLight Saving. - -@endverbatim - * @{ - */ - -/** - * @brief Adds or substract one hour from the current time. - * @param RTC_DayLightSaveOperation: the value of hour adjustment. - * This parameter can be one of the following values: - * @arg RTC_DayLightSaving_SUB1H: Substract one hour (winter time) - * @arg RTC_DayLightSaving_ADD1H: Add one hour (summer time) - * @param RTC_StoreOperation: Specifies the value to be written in the BCK bit - * in CR register to store the operation. - * This parameter can be one of the following values: - * @arg RTC_StoreOperation_Reset: BCK Bit Reset - * @arg RTC_StoreOperation_Set: BCK Bit Set - * @retval None - */ -void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation) -{ - /* Check the parameters */ - assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving)); - assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Clear the bits to be configured */ - RTC->CR &= (uint32_t)~(RTC_CR_BCK); - - /* Configure the RTC_CR register */ - RTC->CR |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation); - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Returns the RTC Day Light Saving stored operation. - * @param None - * @retval RTC Day Light Saving stored operation. - * - RTC_StoreOperation_Reset - * - RTC_StoreOperation_Set - */ -uint32_t RTC_GetStoreOperation(void) -{ - return (RTC->CR & RTC_CR_BCK); -} - -/** - * @} - */ - -/** @defgroup RTC_Group6 Output pin Configuration function - * @brief Output pin Configuration function - * -@verbatim - =============================================================================== - ##### Output pin Configuration function ##### - =============================================================================== - [..] This section provide functions allowing to configure the RTC Output source. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the RTC output source (AFO_ALARM). - * @param RTC_Output: Specifies which signal will be routed to the RTC output. - * This parameter can be one of the following values: - * @arg RTC_Output_Disable: No output selected - * @arg RTC_Output_AlarmA: signal of AlarmA mapped to output - * @arg RTC_Output_WakeUp: signal of WakeUp mapped to output, available only for STM32F072 devices - * @param RTC_OutputPolarity: Specifies the polarity of the output signal. - * This parameter can be one of the following: - * @arg RTC_OutputPolarity_High: The output pin is high when the - * ALRAF is high (depending on OSEL) - * @arg RTC_OutputPolarity_Low: The output pin is low when the - * ALRAF is high (depending on OSEL) - * @retval None - */ -void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity) -{ - /* Check the parameters */ - assert_param(IS_RTC_OUTPUT(RTC_Output)); - assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Clear the bits to be configured */ - RTC->CR &= (uint32_t)~(RTC_CR_OSEL | RTC_CR_POL); - - /* Configure the output selection and polarity */ - RTC->CR |= (uint32_t)(RTC_Output | RTC_OutputPolarity); - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @} - */ - -/** @defgroup RTC_Group7 Digital Calibration configuration functions - * @brief Digital Calibration configuration functions - * -@verbatim - =============================================================================== - ##### Digital Calibration configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the RTC clock to be output through the relative pin. - * @param NewState: new state of the digital calibration Output. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_CalibOutputCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - if (NewState != DISABLE) - { - /* Enable the RTC clock output */ - RTC->CR |= (uint32_t)RTC_CR_COE; - } - else - { - /* Disable the RTC clock output */ - RTC->CR &= (uint32_t)~RTC_CR_COE; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - * @param RTC_CalibOutput: Select the Calibration output Selection . - * This parameter can be one of the following values: - * @arg RTC_CalibOutput_512Hz: A signal has a regular waveform at 512Hz. - * @arg RTC_CalibOutput_1Hz: A signal has a regular waveform at 1Hz. - * @retval None -*/ -void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput) -{ - /* Check the parameters */ - assert_param(IS_RTC_CALIB_OUTPUT(RTC_CalibOutput)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /*clear flags before config*/ - RTC->CR &= (uint32_t)~(RTC_CR_CALSEL); - - /* Configure the RTC_CR register */ - RTC->CR |= (uint32_t)RTC_CalibOutput; - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Configures the Smooth Calibration Settings. - * @param RTC_SmoothCalibPeriod: Select the Smooth Calibration Period. - * This parameter can be can be one of the following values: - * @arg RTC_SmoothCalibPeriod_32sec: The smooth calibration periode is 32s. - * @arg RTC_SmoothCalibPeriod_16sec: The smooth calibration periode is 16s. - * @arg RTC_SmoothCalibPeriod_8sec: The smooth calibartion periode is 8s. - * @param RTC_SmoothCalibPlusPulses: Select to Set or reset the CALP bit. - * This parameter can be one of the following values: - * @arg RTC_SmoothCalibPlusPulses_Set: Add one RTCCLK puls every 2**11 pulses. - * @arg RTC_SmoothCalibPlusPulses_Reset: No RTCCLK pulses are added. - * @param RTC_SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits. - * This parameter can be one any value from 0 to 0x000001FF. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Calib registers are configured - * - ERROR: RTC Calib registers are not configured -*/ -ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod, - uint32_t RTC_SmoothCalibPlusPulses, - uint32_t RTC_SmouthCalibMinusPulsesValue) -{ - ErrorStatus status = ERROR; - uint32_t recalpfcount = 0; - - /* Check the parameters */ - assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(RTC_SmoothCalibPeriod)); - assert_param(IS_RTC_SMOOTH_CALIB_PLUS(RTC_SmoothCalibPlusPulses)); - assert_param(IS_RTC_SMOOTH_CALIB_MINUS(RTC_SmouthCalibMinusPulsesValue)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* check if a calibration is pending*/ - if ((RTC->ISR & RTC_ISR_RECALPF) != RESET) - { - /* wait until the Calibration is completed*/ - while (((RTC->ISR & RTC_ISR_RECALPF) != RESET) && (recalpfcount != RECALPF_TIMEOUT)) - { - recalpfcount++; - } - } - - /* check if the calibration pending is completed or if there is no calibration operation at all*/ - if ((RTC->ISR & RTC_ISR_RECALPF) == RESET) - { - /* Configure the Smooth calibration settings */ - RTC->CALR = (uint32_t)((uint32_t)RTC_SmoothCalibPeriod | (uint32_t)RTC_SmoothCalibPlusPulses | (uint32_t)RTC_SmouthCalibMinusPulsesValue); - - status = SUCCESS; - } - else - { - status = ERROR; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return (ErrorStatus)(status); -} - -/** - * @} - */ - - -/** @defgroup RTC_Group8 TimeStamp configuration functions - * @brief TimeStamp configuration functions - * -@verbatim - =============================================================================== - ##### TimeStamp configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or Disables the RTC TimeStamp functionality with the - * specified time stamp pin stimulating edge. - * @param RTC_TimeStampEdge: Specifies the pin edge on which the TimeStamp is - * activated. - * This parameter can be one of the following: - * @arg RTC_TimeStampEdge_Rising: the Time stamp event occurs on the rising - * edge of the related pin. - * @arg RTC_TimeStampEdge_Falling: the Time stamp event occurs on the - * falling edge of the related pin. - * @param NewState: new state of the TimeStamp. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_TIMESTAMP_EDGE(RTC_TimeStampEdge)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Get the RTC_CR register and clear the bits to be configured */ - tmpreg = (uint32_t)(RTC->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); - - /* Get the new configuration */ - if (NewState != DISABLE) - { - tmpreg |= (uint32_t)(RTC_TimeStampEdge | RTC_CR_TSE); - } - else - { - tmpreg |= (uint32_t)(RTC_TimeStampEdge); - } - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Time Stamp TSEDGE and Enable bits */ - RTC->CR = (uint32_t)tmpreg; - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Get the RTC TimeStamp value and masks. - * @param RTC_Format: specifies the format of the output parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_StampTimeStruct: pointer to a RTC_TimeTypeDef structure that will - * contains the TimeStamp time values. - * @param RTC_StampDateStruct: pointer to a RTC_DateTypeDef structure that will - * contains the TimeStamp date values. - * @retval None - */ -void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, - RTC_DateTypeDef* RTC_StampDateStruct) -{ - uint32_t tmptime = 0, tmpdate = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - /* Get the TimeStamp time and date registers values */ - tmptime = (uint32_t)(RTC->TSTR & RTC_TR_RESERVED_MASK); - tmpdate = (uint32_t)(RTC->TSDR & RTC_DR_RESERVED_MASK); - - /* Fill the Time structure fields with the read parameters */ - RTC_StampTimeStruct->RTC_Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16); - RTC_StampTimeStruct->RTC_Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8); - RTC_StampTimeStruct->RTC_Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU)); - RTC_StampTimeStruct->RTC_H12 = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16); - - /* Fill the Date structure fields with the read parameters */ - RTC_StampDateStruct->RTC_Year = 0; - RTC_StampDateStruct->RTC_Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8); - RTC_StampDateStruct->RTC_Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU)); - RTC_StampDateStruct->RTC_WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13); - - /* Check the input parameters format */ - if (RTC_Format == RTC_Format_BIN) - { - /* Convert the Time structure parameters to Binary format */ - RTC_StampTimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Hours); - RTC_StampTimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Minutes); - RTC_StampTimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Seconds); - - /* Convert the Date structure parameters to Binary format */ - RTC_StampDateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Month); - RTC_StampDateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Date); - RTC_StampDateStruct->RTC_WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_WeekDay); - } -} - -/** - * @brief Get the RTC timestamp Subseconds value. - * @param None - * @retval RTC current timestamp Subseconds value. - */ -uint32_t RTC_GetTimeStampSubSecond(void) -{ - /* Get timestamp subseconds values from the correspondent registers */ - return (uint32_t)(RTC->TSSSR); -} - -/** - * @} - */ - -/** @defgroup RTC_Group9 Tampers configuration functions - * @brief Tampers configuration functions - * -@verbatim - =============================================================================== - ##### Tampers configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the select Tamper pin edge. - * @param RTC_Tamper: Selected tamper pin. - * This parameter can be any combination of the following values: - * @arg RTC_Tamper_1: Select Tamper 1. - * @arg RTC_Tamper_2: Select Tamper 2. - * @param RTC_TamperTrigger: Specifies the trigger on the tamper pin that - * stimulates tamper event. - * This parameter can be one of the following values: - * @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event. - * @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event. - * @arg RTC_TamperTrigger_LowLevel: Low Level of the tamper pin causes tamper event. - * @arg RTC_TamperTrigger_HighLevel: High Level of the tamper pin causes tamper event. - * @retval None - */ -void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER(RTC_Tamper)); - assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger)); - - if (RTC_TamperTrigger == RTC_TamperTrigger_RisingEdge) - { - /* Configure the RTC_TAFCR register */ - RTC->TAFCR &= (uint32_t)((uint32_t)~(RTC_Tamper << 1)); - } - else - { - /* Configure the RTC_TAFCR register */ - RTC->TAFCR |= (uint32_t)(RTC_Tamper << 1); - } -} - -/** - * @brief Enables or Disables the Tamper detection. - * @param RTC_Tamper: Selected tamper pin. - * This parameter can be any combination of the following values: - * @arg RTC_Tamper_1: Select Tamper 1. - * @arg RTC_Tamper_2: Select Tamper 2. - * @param NewState: new state of the tamper pin. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER(RTC_Tamper)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected Tamper pin */ - RTC->TAFCR |= (uint32_t)RTC_Tamper; - } - else - { - /* Disable the selected Tamper pin */ - RTC->TAFCR &= (uint32_t)~RTC_Tamper; - } -} - -/** - * @brief Configures the Tampers Filter. - * @param RTC_TamperFilter: Specifies the tampers filter. - * This parameter can be one of the following values: - * @arg RTC_TamperFilter_Disable: Tamper filter is disabled. - * @arg RTC_TamperFilter_2Sample: Tamper is activated after 2 consecutive - * samples at the active level - * @arg RTC_TamperFilter_4Sample: Tamper is activated after 4 consecutive - * samples at the active level - * @arg RTC_TamperFilter_8Sample: Tamper is activated after 8 consecutive - * samples at the active level - * @retval None - */ -void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER_FILTER(RTC_TamperFilter)); - - /* Clear TAMPFLT[1:0] bits in the RTC_TAFCR register */ - RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFLT); - - /* Configure the RTC_TAFCR register */ - RTC->TAFCR |= (uint32_t)RTC_TamperFilter; -} - -/** - * @brief Configures the Tampers Sampling Frequency. - * @param RTC_TamperSamplingFreq: Specifies the tampers Sampling Frequency. - * This parameter can be one of the following values: - * @arg RTC_TamperSamplingFreq_RTCCLK_Div32768: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 32768 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div16384: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 16384 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div8192: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 8192 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div4096: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 4096 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div2048: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 2048 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div1024: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 1024 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div512: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 512 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div256: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 256 - * @retval None - */ -void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(RTC_TamperSamplingFreq)); - - /* Clear TAMPFREQ[2:0] bits in the RTC_TAFCR register */ - RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFREQ); - - /* Configure the RTC_TAFCR register */ - RTC->TAFCR |= (uint32_t)RTC_TamperSamplingFreq; -} - -/** - * @brief Configures the Tampers Pins input Precharge Duration. - * @param RTC_TamperPrechargeDuration: Specifies the Tampers Pins input - * Precharge Duration. - * This parameter can be one of the following values: - * @arg RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are pre-charged before sampling during 1 RTCCLK cycle - * @arg RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are pre-charged before sampling during 2 RTCCLK cycle - * @arg RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are pre-charged before sampling during 4 RTCCLK cycle - * @arg RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are pre-charged before sampling during 8 RTCCLK cycle - * @retval None - */ -void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(RTC_TamperPrechargeDuration)); - - /* Clear TAMPPRCH[1:0] bits in the RTC_TAFCR register */ - RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPPRCH); - - /* Configure the RTC_TAFCR register */ - RTC->TAFCR |= (uint32_t)RTC_TamperPrechargeDuration; -} - -/** - * @brief Enables or Disables the TimeStamp on Tamper Detection Event. - * @note The timestamp is valid even the TSE bit in tamper control register - * is reset. - * @param NewState: new state of the timestamp on tamper event. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Save timestamp on tamper detection event */ - RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPTS; - } - else - { - /* Tamper detection does not cause a timestamp to be saved */ - RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPTS; - } -} - -/** - * @brief Enables or Disables the Precharge of Tamper pin. - * @param NewState: new state of tamper pull up. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_TamperPullUpCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable precharge of the selected Tamper pin */ - RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPPUDIS; - } - else - { - /* Disable precharge of the selected Tamper pin */ - RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPPUDIS; - } -} - -/** - * @} - */ - -/** @defgroup RTC_Group10 Backup Data Registers configuration functions - * @brief Backup Data Registers configuration functions - * -@verbatim - =============================================================================== - ##### Backup Data Registers configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Writes a data in a specified RTC Backup data register. - * @param RTC_BKP_DR: RTC Backup data Register number. - * This parameter can be: RTC_BKP_DRx where x can be from 0 to 4 to - * specify the register. - * @param Data: Data to be written in the specified RTC Backup data register. - * @retval None - */ -void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_RTC_BKP(RTC_BKP_DR)); - - tmp = RTC_BASE + 0x50; - tmp += (RTC_BKP_DR * 4); - - /* Write the specified register */ - *(__IO uint32_t *)tmp = (uint32_t)Data; -} - -/** - * @brief Reads data from the specified RTC Backup data Register. - * @param RTC_BKP_DR: RTC Backup data Register number. - * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to - * specify the register. - * @retval None - */ -uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_RTC_BKP(RTC_BKP_DR)); - - tmp = RTC_BASE + 0x50; - tmp += (RTC_BKP_DR * 4); - - /* Read the specified register */ - return (*(__IO uint32_t *)tmp); -} - -/** - * @} - */ - -/** @defgroup RTC_Group11 Output Type Config configuration functions - * @brief Output Type Config configuration functions - * -@verbatim - =============================================================================== - ##### Output Type Config configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the RTC Output Pin mode. - * @param RTC_OutputType: specifies the RTC Output (PC13) pin mode. - * This parameter can be one of the following values: - * @arg RTC_OutputType_OpenDrain: RTC Output (PC13) is configured in - * Open Drain mode. - * @arg RTC_OutputType_PushPull: RTC Output (PC13) is configured in - * Push Pull mode. - * @retval None - */ -void RTC_OutputTypeConfig(uint32_t RTC_OutputType) -{ - /* Check the parameters */ - assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType)); - - RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_ALARMOUTTYPE); - RTC->TAFCR |= (uint32_t)(RTC_OutputType); -} - -/** - * @} - */ - -/** @defgroup RTC_Group12 Shift control synchronisation functions - * @brief Shift control synchronisation functions - * -@verbatim - =============================================================================== - ##### Shift control synchronisation functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the Synchronization Shift Control Settings. - * @note When REFCKON is set, firmware must not write to Shift control register - * @param RTC_ShiftAdd1S: Select to add or not 1 second to the time Calendar. - * This parameter can be one of the following values : - * @arg RTC_ShiftAdd1S_Set: Add one second to the clock calendar. - * @arg RTC_ShiftAdd1S_Reset: No effect. - * @param RTC_ShiftSubFS: Select the number of Second Fractions to Substitute. - * This parameter can be one any value from 0 to 0x7FFF. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Shift registers are configured - * - ERROR: RTC Shift registers are not configured -*/ -ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS) -{ - ErrorStatus status = ERROR; - uint32_t shpfcount = 0; - - /* Check the parameters */ - assert_param(IS_RTC_SHIFT_ADD1S(RTC_ShiftAdd1S)); - assert_param(IS_RTC_SHIFT_SUBFS(RTC_ShiftSubFS)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Check if a Shift is pending*/ - if ((RTC->ISR & RTC_ISR_SHPF) != RESET) - { - /* Wait until the shift is completed*/ - while (((RTC->ISR & RTC_ISR_SHPF) != RESET) && (shpfcount != SHPF_TIMEOUT)) - { - shpfcount++; - } - } - - /* Check if the Shift pending is completed or if there is no Shift operation at all*/ - if ((RTC->ISR & RTC_ISR_SHPF) == RESET) - { - /* check if the reference clock detection is disabled */ - if((RTC->CR & RTC_CR_REFCKON) == RESET) - { - /* Configure the Shift settings */ - RTC->SHIFTR = (uint32_t)(uint32_t)(RTC_ShiftSubFS) | (uint32_t)(RTC_ShiftAdd1S); - - if(RTC_WaitForSynchro() == ERROR) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - else - { - status = ERROR; - } - } - else - { - status = ERROR; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return (ErrorStatus)(status); -} - -/** - * @} - */ - -/** @defgroup RTC_Group13 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - [..] All RTC interrupts are connected to the EXTI controller. - - (+) To enable the RTC Alarm interrupt, the following sequence is required: - (++) Configure and enable the EXTI Line 17 in interrupt mode and select the rising - edge sensitivity using the EXTI_Init() function. - (++) Configure and enable the RTC_Alarm IRQ channel in the NVIC using the NVIC_Init() - function. - (++) Configure the RTC to generate RTC alarms (Alarm A) using - the RTC_SetAlarm() and RTC_AlarmCmd() functions. - - (+) To enable the RTC Tamper interrupt, the following sequence is required: - (++) Configure and enable the EXTI Line 19 in interrupt mode and select the rising - edge sensitivity using the EXTI_Init() function. - (++) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init() - function. - (++) Configure the RTC to detect the RTC tamper event using the - RTC_TamperTriggerConfig() and RTC_TamperCmd() functions. - - (+) To enable the RTC TimeStamp interrupt, the following sequence is required: - (++) Configure and enable the EXTI Line 19 in interrupt mode and select the rising - edge sensitivity using the EXTI_Init() function. - (++) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init() - function. - (++) Configure the RTC to detect the RTC time-stamp event using the - RTC_TimeStampCmd() functions. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified RTC interrupts. - * @param RTC_IT: specifies the RTC interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_TS: Time Stamp interrupt mask - * @arg RTC_IT_WUT: WakeUp Timer interrupt mask, available only for STM32F072 devices - * @arg RTC_IT_ALRA: Alarm A interrupt mask - * @arg RTC_IT_TAMP: Tamper event interrupt mask - * @param NewState: new state of the specified RTC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RTC_CONFIG_IT(RTC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - if (NewState != DISABLE) - { - /* Configure the Interrupts in the RTC_CR register */ - RTC->CR |= (uint32_t)(RTC_IT & ~RTC_TAFCR_TAMPIE); - /* Configure the Tamper Interrupt in the RTC_TAFCR */ - RTC->TAFCR |= (uint32_t)(RTC_IT & RTC_TAFCR_TAMPIE); - } - else - { - /* Configure the Interrupts in the RTC_CR register */ - RTC->CR &= (uint32_t)~(RTC_IT & (uint32_t)~RTC_TAFCR_TAMPIE); - /* Configure the Tamper Interrupt in the RTC_TAFCR */ - RTC->TAFCR &= (uint32_t)~(RTC_IT & RTC_TAFCR_TAMPIE); - } - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Checks whether the specified RTC flag is set or not. - * @param RTC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg RTC_FLAG_RECALPF: RECALPF event flag - * @arg RTC_FLAG_TAMP2F: Tamper 2 event flag - * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag - * @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag - * @arg RTC_FLAG_TSF: Time Stamp event flag - * @arg RTC_FLAG_WUTF: WakeUp Timer flag, available only for STM32F072 devices - * @arg RTC_FLAG_ALRAF: Alarm A flag - * @arg RTC_FLAG_INITF: Initialization mode flag - * @arg RTC_FLAG_RSF: Registers Synchronized flag - * @arg RTC_FLAG_INITS: Registers Configured flag - * @retval The new state of RTC_FLAG (SET or RESET). - */ -FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); - - /* Get all the flags */ - tmpreg = (uint32_t)(RTC->ISR & RTC_FLAGS_MASK); - - /* Return the status of the flag */ - if ((tmpreg & RTC_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the RTC's pending flags. - * @param RTC_FLAG: specifies the RTC flag to clear. - * This parameter can be any combination of the following values: - * @arg RTC_FLAG_TAMP2F: Tamper 2 event flag - * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag - * @arg RTC_FLAG_TSOVF: Time Stamp Overflow flag - * @arg RTC_FLAG_TSF: Time Stamp event flag - * @arg RTC_FLAG_WUTF: WakeUp Timer flag, available only for STM32F072 devices - * @arg RTC_FLAG_ALRAF: Alarm A flag - * @arg RTC_FLAG_RSF: Registers Synchronized flag - * @retval None - */ -void RTC_ClearFlag(uint32_t RTC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); - - /* Clear the Flags in the RTC_ISR register */ - RTC->ISR = (uint32_t)((uint32_t)(~((RTC_FLAG | RTC_ISR_INIT)& 0x0001FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); -} - -/** - * @brief Checks whether the specified RTC interrupt has occurred or not. - * @param RTC_IT: specifies the RTC interrupt source to check. - * This parameter can be one of the following values: - * @arg RTC_IT_TS: Time Stamp interrupt - * @arg RTC_IT_WUT: WakeUp Timer interrupt, available only for STM32F072 devices - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_TAMP1: Tamper1 event interrupt - * @arg RTC_IT_TAMP2: Tamper2 event interrupt - * @retval The new state of RTC_IT (SET or RESET). - */ -ITStatus RTC_GetITStatus(uint32_t RTC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpreg = 0, enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_RTC_GET_IT(RTC_IT)); - - /* Get the TAMPER Interrupt enable bit and pending bit */ - tmpreg = (uint32_t)(RTC->TAFCR & (RTC_TAFCR_TAMPIE)); - - /* Get the Interrupt enable Status */ - enablestatus = (uint32_t)((RTC->CR & RTC_IT) | (tmpreg & ((RTC_IT >> (RTC_IT >> 18)) >> 15))); - - /* Get the Interrupt pending bit */ - tmpreg = (uint32_t)((RTC->ISR & (uint32_t)(RTC_IT >> 4))); - - /* Get the status of the Interrupt */ - if ((enablestatus != (uint32_t)RESET) && ((tmpreg & 0x0000FFFF) != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the RTC's interrupt pending bits. - * @param RTC_IT: specifies the RTC interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg RTC_IT_TS: Time Stamp interrupt - * @arg RTC_IT_WUT: WakeUp Timer interrupt, available only for STM32F072 devices - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_TAMP1: Tamper1 event interrupt - * @arg RTC_IT_TAMP2: Tamper2 event interrupt - * @retval None - */ -void RTC_ClearITPendingBit(uint32_t RTC_IT) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_CLEAR_IT(RTC_IT)); - - /* Get the RTC_ISR Interrupt pending bits mask */ - tmpreg = (uint32_t)(RTC_IT >> 4); - - /* Clear the interrupt pending bits in the RTC_ISR register */ - RTC->ISR = (uint32_t)((uint32_t)(~((tmpreg | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); -} - -/** - * @} - */ - -/** - * @brief Converts a 2 digit decimal to BCD format. - * @param Value: Byte to be converted. - * @retval Converted byte - */ -static uint8_t RTC_ByteToBcd2(uint8_t Value) -{ - uint8_t bcdhigh = 0; - - while (Value >= 10) - { - bcdhigh++; - Value -= 10; - } - - return ((uint8_t)(bcdhigh << 4) | Value); -} - -/** - * @brief Convert from 2 digit BCD to Binary. - * @param Value: BCD value to be converted. - * @retval Converted word - */ -static uint8_t RTC_Bcd2ToByte(uint8_t Value) -{ - uint8_t tmp = 0; - tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; - return (tmp + (Value & (uint8_t)0x0F)); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_spi.c b/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_spi.c deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_spi.c +++ /dev/null @@ -1,1334 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_spi.c - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the Serial peripheral interface (SPI): - * + Initialization and Configuration - * + Data transfers functions - * + Hardware CRC Calculation - * + DMA transfers management - * + Interrupts and flags management - * - * @verbatim - - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - (#) Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE) - function for SPI1 or using RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE) - function for SPI2. - - (#) Enable SCK, MOSI, MISO and NSS GPIO clocks using - RCC_AHBPeriphClockCmd() function. - - (#) Peripherals alternate function: - (++) Connect the pin to the desired peripherals' Alternate - Function (AF) using GPIO_PinAFConfig() function. - (++) Configure the desired pin in alternate function by: - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF. - (++) Select the type, pull-up/pull-down and output speed via - GPIO_PuPd, GPIO_OType and GPIO_Speed members. - (++) Call GPIO_Init() function. - - (#) Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave - Management, Peripheral Mode and CRC Polynomial values using the SPI_Init() - function.In I2S mode, program the Mode, Standard, Data Format, MCLK - Output, Audio frequency and Polarity using I2S_Init() function. - - (#) Configure the FIFO threshold using SPI_RxFIFOThresholdConfig() to select - at which threshold the RXNE event is generated. - - (#) Enable the NVIC and the corresponding interrupt using the function - SPI_ITConfig() if you need to use interrupt mode. - - (#) When using the DMA mode - (++) Configure the DMA using DMA_Init() function. - (++) Active the needed channel Request using SPI_I2S_DMACmd() function. - - (#) Enable the SPI using the SPI_Cmd() function or enable the I2S using - I2S_Cmd(). - - (#) Enable the DMA using the DMA_Cmd() function when using DMA mode. - - (#) Optionally, you can enable/configure the following parameters without - re-initialization (i.e there is no need to call again SPI_Init() function): - (++) When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx) - is programmed as Data direction parameter using the SPI_Init() - function it can be possible to switch between SPI_Direction_Tx - or SPI_Direction_Rx using the SPI_BiDirectionalLineConfig() function. - (++) When SPI_NSS_Soft is selected as Slave Select Management parameter - using the SPI_Init() function it can be possible to manage the - NSS internal signal using the SPI_NSSInternalSoftwareConfig() function. - (++) Reconfigure the data size using the SPI_DataSizeConfig() function. - (++) Enable or disable the SS output using the SPI_SSOutputCmd() function. - - (#) To use the CRC Hardware calculation feature refer to the Peripheral - CRC hardware Calculation subsection. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_spi.h" -#include "stm32f0xx_rcc.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup SPI - * @brief SPI driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* SPI registers Masks */ -#define CR1_CLEAR_MASK ((uint16_t)0x3040) -#define CR1_CLEAR_MASK2 ((uint16_t)0xFFFB) -#define CR2_LDMA_MASK ((uint16_t)0x9FFF) - -#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup SPI_Private_Functions - * @{ - */ - -/** @defgroup SPI_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] This section provides a set of functions allowing to initialize the SPI Direction, - SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS Management, SPI Baud - Rate Prescaler, SPI First Bit and SPI CRC Polynomial. - - [..] The SPI_Init() function follows the SPI configuration procedures for Master mode - and Slave mode (details for these procedures are available in reference manual). - - [..] When the Software NSS management (SPI_InitStruct->SPI_NSS = SPI_NSS_Soft) is selected, - use the following function to manage the NSS bit: - void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); - - [..] In Master mode, when the Hardware NSS management (SPI_InitStruct->SPI_NSS = SPI_NSS_Hard) - is selected, use the follwoing function to enable the NSS output feature. - void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); - - [..] The NSS pulse mode can be managed by the SPI TI mode when enabling it using the following function: - void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); - And it can be managed by software in the SPI Motorola mode using this function: - void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); - - [..] This section provides also functions to initialize the I2S Mode, Standard, - Data Format, MCLK Output, Audio frequency and Polarity. - - [..] The I2S_Init() function follows the I2S configuration procedures for Master mode - and Slave mode. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the SPIx peripheral registers to their default - * reset values. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @note SPI2 is not available for STM32F031 devices. - * I2S mode is not supported for STM32F030 devices. - * @retval None - */ -void SPI_I2S_DeInit(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - if (SPIx == SPI1) - { - /* Enable SPI1 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); - /* Release SPI1 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); - } - else - { - if (SPIx == SPI2) - { - /* Enable SPI2 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); - /* Release SPI2 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); - } - } -} - -/** - * @brief Fills each SPI_InitStruct member with its default value. - * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized. - * @retval None - */ -void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) -{ -/*--------------- Reset SPI init structure parameters values -----------------*/ - /* Initialize the SPI_Direction member */ - SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; - /* Initialize the SPI_Mode member */ - SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; - /* Initialize the SPI_DataSize member */ - SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; - /* Initialize the SPI_CPOL member */ - SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; - /* Initialize the SPI_CPHA member */ - SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; - /* Initialize the SPI_NSS member */ - SPI_InitStruct->SPI_NSS = SPI_NSS_Hard; - /* Initialize the SPI_BaudRatePrescaler member */ - SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; - /* Initialize the SPI_FirstBit member */ - SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; - /* Initialize the SPI_CRCPolynomial member */ - SPI_InitStruct->SPI_CRCPolynomial = 7; -} - -/** - * @brief Initializes the SPIx peripheral according to the specified - * parameters in the SPI_InitStruct. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @note SPI2 is not available for STM32F031 devices. - * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that - * contains the configuration information for the specified SPI peripheral. - * @retval None - */ -void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) -{ - uint16_t tmpreg = 0; - - /* check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Check the SPI parameters */ - assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction)); - assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); - assert_param(IS_SPI_DATA_SIZE(SPI_InitStruct->SPI_DataSize)); - assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); - assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); - assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS)); - assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler)); - assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); - assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial)); - - /*---------------------------- SPIx CR1 Configuration ------------------------*/ - /* Get the SPIx CR1 value */ - tmpreg = SPIx->CR1; - /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, CPOL and CPHA bits */ - tmpreg &= CR1_CLEAR_MASK; - /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler - master/slave mode, CPOL and CPHA */ - /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */ - /* Set SSM, SSI bit according to SPI_NSS values */ - /* Set LSBFirst bit according to SPI_FirstBit value */ - /* Set BR bits according to SPI_BaudRatePrescaler value */ - /* Set CPOL bit according to SPI_CPOL value */ - /* Set CPHA bit according to SPI_CPHA value */ - tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_FirstBit | - SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA | - SPI_InitStruct->SPI_NSS | SPI_InitStruct->SPI_BaudRatePrescaler); - /* Write to SPIx CR1 */ - SPIx->CR1 = tmpreg; - /*-------------------------Data Size Configuration -----------------------*/ - /* Get the SPIx CR2 value */ - tmpreg = SPIx->CR2; - /* Clear DS[3:0] bits */ - tmpreg &=(uint16_t)~SPI_CR2_DS; - /* Configure SPIx: Data Size */ - tmpreg |= (uint16_t)(SPI_InitStruct->SPI_DataSize); - /* Write to SPIx CR2 */ - SPIx->CR2 = tmpreg; - - /*---------------------------- SPIx CRCPOLY Configuration --------------------*/ - /* Write to SPIx CRCPOLY */ - SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial; - - /*---------------------------- SPIx CR1 Configuration ------------------------*/ - /* Get the SPIx CR1 value */ - tmpreg = SPIx->CR1; - /* Clear MSTR bit */ - tmpreg &= CR1_CLEAR_MASK2; - /* Configure SPIx: master/slave mode */ - /* Set MSTR bit according to SPI_Mode */ - tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Mode); - /* Write to SPIx CR1 */ - SPIx->CR1 = tmpreg; - - /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ - SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD); -} - -/** - * @brief Fills each I2S_InitStruct member with its default value. - * @note This mode is not supported for STM32F030 devices. - * @param I2S_InitStruct: pointer to a I2S_InitTypeDef structure which will be initialized. - * @retval None - */ -void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct) -{ -/*--------------- Reset I2S init structure parameters values -----------------*/ - /* Initialize the I2S_Mode member */ - I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx; - - /* Initialize the I2S_Standard member */ - I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips; - - /* Initialize the I2S_DataFormat member */ - I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b; - - /* Initialize the I2S_MCLKOutput member */ - I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable; - - /* Initialize the I2S_AudioFreq member */ - I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default; - - /* Initialize the I2S_CPOL member */ - I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low; -} - -/** - * @brief Initializes the SPIx peripheral according to the specified - * parameters in the I2S_InitStruct. - * @note This mode is not supported for STM32F030 devices. - * @param SPIx: where x can be 1 to select the SPI peripheral (configured in I2S mode). - * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that - * contains the configuration information for the specified SPI peripheral - * configured in I2S mode. - * @note This function calculates the optimal prescaler needed to obtain the most - * accurate audio frequency (depending on the I2S clock source, the PLL values - * and the product configuration). But in case the prescaler value is greater - * than 511, the default value (0x02) will be configured instead. - * @retval None - */ -void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct) -{ - uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; - uint32_t tmp = 0; - RCC_ClocksTypeDef RCC_Clocks; - uint32_t sourceclock = 0; - - /* Check the I2S parameters */ - assert_param(IS_SPI_1_PERIPH(SPIx)); - assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); - assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard)); - assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat)); - assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput)); - assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq)); - assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); - -/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ - /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ - SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; - SPIx->I2SPR = 0x0002; - - /* Get the I2SCFGR register value */ - tmpreg = SPIx->I2SCFGR; - - /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ - if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) - { - i2sodd = (uint16_t)0; - i2sdiv = (uint16_t)2; - } - /* If the requested audio frequency is not the default, compute the prescaler */ - else - { - /* Check the frame length (For the Prescaler computing) */ - if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) - { - /* Packet length is 16 bits */ - packetlength = 1; - } - else - { - /* Packet length is 32 bits */ - packetlength = 2; - } - - /* I2S Clock source is System clock: Get System Clock frequency */ - RCC_GetClocksFreq(&RCC_Clocks); - - /* Get the source clock value: based on System Clock value */ - sourceclock = RCC_Clocks.SYSCLK_Frequency; - - /* Compute the Real divider depending on the MCLK output state with a floating point */ - if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) - { - /* MCLK output is enabled */ - tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); - } - else - { - /* MCLK output is disabled */ - tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5); - } - - /* Remove the floating point */ - tmp = tmp / 10; - - /* Check the parity of the divider */ - i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); - - /* Compute the i2sdiv prescaler */ - i2sdiv = (uint16_t)((tmp - i2sodd) / 2); - - /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ - i2sodd = (uint16_t) (i2sodd << 8); - } - - /* Test if the divider is 1 or 0 or greater than 0xFF */ - if ((i2sdiv < 2) || (i2sdiv > 0xFF)) - { - /* Set the default values */ - i2sdiv = 2; - i2sodd = 0; - } - - /* Write to SPIx I2SPR register the computed value */ - SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); - - /* Configure the I2S with the SPI_InitStruct values */ - tmpreg |= (uint16_t)(SPI_I2SCFGR_I2SMOD | (uint16_t)(I2S_InitStruct->I2S_Mode | \ - (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \ - (uint16_t)I2S_InitStruct->I2S_CPOL)))); - - /* Write to SPIx I2SCFGR */ - SPIx->I2SCFGR = tmpreg; -} - -/** - * @brief Enables or disables the specified SPI peripheral. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @note SPI2 is not available for STM32F031 devices. - * @param NewState: new state of the SPIx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected SPI peripheral */ - SPIx->CR1 |= SPI_CR1_SPE; - } - else - { - /* Disable the selected SPI peripheral */ - SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE); - } -} - -/** - * @brief Enables or disables the TI Mode. - * - * @note This function can be called only after the SPI_Init() function has - * been called. - * @note When TI mode is selected, the control bits SSM, SSI, CPOL and CPHA - * are not taken into consideration and are configured by hardware - * respectively to the TI mode requirements. - * - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @note SPI2 is not available for STM32F031 devices. - * @param NewState: new state of the selected SPI TI communication mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the TI mode for the selected SPI peripheral */ - SPIx->CR2 |= SPI_CR2_FRF; - } - else - { - /* Disable the TI mode for the selected SPI peripheral */ - SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_FRF); - } -} - -/** - * @brief Enables or disables the specified SPI peripheral (in I2S mode). - * @note This mode is not supported for STM32F030 devices. - * @param SPIx: where x can be 1 to select the SPI peripheral. - * @param NewState: new state of the SPIx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_1_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI peripheral in I2S mode */ - SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE; - } - else - { - /* Disable the selected SPI peripheral in I2S mode */ - SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE); - } -} - -/** - * @brief Configures the data size for the selected SPI. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @note SPI2 is not available for STM32F031 devices. - * @param SPI_DataSize: specifies the SPI data size. - * For the SPIx peripheral this parameter can be one of the following values: - * @arg SPI_DataSize_4b: Set data size to 4 bits - * @arg SPI_DataSize_5b: Set data size to 5 bits - * @arg SPI_DataSize_6b: Set data size to 6 bits - * @arg SPI_DataSize_7b: Set data size to 7 bits - * @arg SPI_DataSize_8b: Set data size to 8 bits - * @arg SPI_DataSize_9b: Set data size to 9 bits - * @arg SPI_DataSize_10b: Set data size to 10 bits - * @arg SPI_DataSize_11b: Set data size to 11 bits - * @arg SPI_DataSize_12b: Set data size to 12 bits - * @arg SPI_DataSize_13b: Set data size to 13 bits - * @arg SPI_DataSize_14b: Set data size to 14 bits - * @arg SPI_DataSize_15b: Set data size to 15 bits - * @arg SPI_DataSize_16b: Set data size to 16 bits - * @retval None - */ -void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize) -{ - uint16_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_DATA_SIZE(SPI_DataSize)); - /* Read the CR2 register */ - tmpreg = SPIx->CR2; - /* Clear DS[3:0] bits */ - tmpreg &= (uint16_t)~SPI_CR2_DS; - /* Set new DS[3:0] bits value */ - tmpreg |= SPI_DataSize; - SPIx->CR2 = tmpreg; -} - -/** - * @brief Configures the FIFO reception threshold for the selected SPI. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @note SPI2 is not available for STM32F031 devices. - * @param SPI_RxFIFOThreshold: specifies the FIFO reception threshold. - * This parameter can be one of the following values: - * @arg SPI_RxFIFOThreshold_HF: RXNE event is generated if the FIFO - * level is greater or equal to 1/2. - * @arg SPI_RxFIFOThreshold_QF: RXNE event is generated if the FIFO - * level is greater or equal to 1/4. - * @retval None - */ -void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_RX_FIFO_THRESHOLD(SPI_RxFIFOThreshold)); - - /* Clear FRXTH bit */ - SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_FRXTH); - - /* Set new FRXTH bit value */ - SPIx->CR2 |= SPI_RxFIFOThreshold; -} - -/** - * @brief Selects the data transfer direction in bidirectional mode for the specified SPI. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @note SPI2 is not available for STM32F031 devices. - * @param SPI_Direction: specifies the data transfer direction in bidirectional mode. - * This parameter can be one of the following values: - * @arg SPI_Direction_Tx: Selects Tx transmission direction - * @arg SPI_Direction_Rx: Selects Rx receive direction - * @retval None - */ -void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_DIRECTION(SPI_Direction)); - if (SPI_Direction == SPI_Direction_Tx) - { - /* Set the Tx only mode */ - SPIx->CR1 |= SPI_Direction_Tx; - } - else - { - /* Set the Rx only mode */ - SPIx->CR1 &= SPI_Direction_Rx; - } -} - -/** - * @brief Configures internally by software the NSS pin for the selected SPI. - * @note This function can be called only after the SPI_Init() function has - * been called. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @note SPI2 is not available for STM32F031 devices. - * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state. - * This parameter can be one of the following values: - * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally - * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally - * @retval None - */ -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft)); - - if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) - { - /* Set NSS pin internally by software */ - SPIx->CR1 |= SPI_NSSInternalSoft_Set; - } - else - { - /* Reset NSS pin internally by software */ - SPIx->CR1 &= SPI_NSSInternalSoft_Reset; - } -} - -/** - * @brief Enables or disables the SS output for the selected SPI. - * @note This function can be called only after the SPI_Init() function has - * been called and the NSS hardware management mode is selected. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @note SPI2 is not available for STM32F031 devices. - * @param NewState: new state of the SPIx SS output. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI SS output */ - SPIx->CR2 |= SPI_CR2_SSOE; - } - else - { - /* Disable the selected SPI SS output */ - SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE); - } -} - -/** - * @brief Enables or disables the NSS pulse management mode. - * @note This function can be called only after the SPI_Init() function has - * been called. - * @note When TI mode is selected, the control bits NSSP is not taken into - * consideration and are configured by hardware respectively to the - * TI mode requirements. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @note SPI2 is not available for STM32F031 devices. - * @param NewState: new state of the NSS pulse management mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the NSS pulse management mode */ - SPIx->CR2 |= SPI_CR2_NSSP; - } - else - { - /* Disable the NSS pulse management mode */ - SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_NSSP); - } -} - -/** - * @} - */ - -/** @defgroup SPI_Group2 Data transfers functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### Data transfers functions ##### - =============================================================================== - [..] This section provides a set of functions allowing to manage the SPI or I2S - data transfers. - - [..] In reception, data are received and then stored into an internal Rx buffer while - In transmission, data are first stored into an internal Tx buffer before being - transmitted. - - [..] The read access of the SPI_DR register can be done using - SPI_ReceiveData8() (when data size is equal or inferior than 8bits) and. - SPI_I2S_ReceiveData16() (when data size is superior than 8bits)function - and returns the Rx buffered value. Whereas a write access to the SPI_DR - can be done using SPI_SendData8() (when data size is equal or inferior than 8bits) - and SPI_I2S_SendData16() (when data size is superior than 8bits) function - and stores the written data into Tx buffer. - -@endverbatim - * @{ - */ - -/** - * @brief Transmits a Data through the SPIx/I2Sx peripheral. - * @param SPIx: where x can be 1 or 2 in SPI mode to select the SPI peripheral. - * @note SPI2 is not available for STM32F031 devices. - * @param Data: Data to be transmitted. - * @retval None - */ -void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data) -{ - uint32_t spixbase = 0x00; - - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - spixbase = (uint32_t)SPIx; - spixbase += 0x0C; - - *(__IO uint8_t *) spixbase = Data; -} - -/** - * @brief Transmits a Data through the SPIx/I2Sx peripheral. - * @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select - * the SPI peripheral. - * @note SPI2 is not available for STM32F031 devices. - * @param Data: Data to be transmitted. - * @retval None - */ -void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - SPIx->DR = (uint16_t)Data; -} - -/** - * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. - * @param SPIx: where x can be 1 or 2 in SPI mode to select the SPI peripheral. - * @note SPI2 is not available for STM32F031 devices. - * @retval The value of the received data. - */ -uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx) -{ - uint32_t spixbase = 0x00; - - spixbase = (uint32_t)SPIx; - spixbase += 0x0C; - - return *(__IO uint8_t *) spixbase; -} - -/** - * @brief Returns the most recent received data by the SPIx peripheral. - * @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select - * @note SPI2 is not available for STM32F031 devices. - * the SPI peripheral. - * @retval The value of the received data. - */ -uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx) -{ - return SPIx->DR; -} -/** - * @} - */ - -/** @defgroup SPI_Group3 Hardware CRC Calculation functions - * @brief Hardware CRC Calculation functions - * -@verbatim - =============================================================================== - ##### Hardware CRC Calculation functions ##### - =============================================================================== - [..] This section provides a set of functions allowing to manage the SPI CRC hardware - calculation.SPI communication using CRC is possible through the following procedure: - - (#) Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler, - Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init() - function. - (#) Enable the CRC calculation using the SPI_CalculateCRC() function. - (#) Enable the SPI using the SPI_Cmd() function - (#) Before writing the last data to the TX buffer, set the CRCNext bit using the - SPI_TransmitCRC() function to indicate that after transmission of the last - data, the CRC should be transmitted. - (#) After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT - bit is reset. The CRC is also received and compared against the SPI_RXCRCR - value. - If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt - can be generated when the SPI_I2S_IT_ERR interrupt is enabled. - - -@- - (+@) It is advised to don't read the calculate CRC values during the communication. - (+@) When the SPI is in slave mode, be careful to enable CRC calculation only - when the clock is stable, that is, when the clock is in the steady state. - If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive - to the SCK slave input clock as soon as CRCEN is set, and this, whatever - the value of the SPE bit. - (+@) With high bitrate frequencies, be careful when transmitting the CRC. - As the number of used CPU cycles has to be as low as possible in the CRC - transfer phase, it is forbidden to call software functions in the CRC - transmission sequence to avoid errors in the last data and CRC reception. - In fact, CRCNEXT bit has to be written before the end of the transmission/reception - of the last data. - (+@) For high bit rate frequencies, it is advised to use the DMA mode to avoid the - degradation of the SPI speed performance due to CPU accesses impacting the - SPI bandwidth. - (+@) When the STM32F0xx are configured as slaves and the NSS hardware mode is - used, the NSS pin needs to be kept low between the data phase and the CRC - phase. - (+@) When the SPI is configured in slave mode with the CRC feature enabled, CRC - calculation takes place even if a high level is applied on the NSS pin. - This may happen for example in case of a multislave environment where the - communication master addresses slaves alternately. - (+@) Between a slave deselection (high level on NSS) and a new slave selection - (low level on NSS), the CRC value should be cleared on both master and slave - sides in order to resynchronize the master and slave for their respective - CRC calculation. - - -@- To clear the CRC, follow the procedure below: - (#@) Disable SPI using the SPI_Cmd() function - (#@) Disable the CRC calculation using the SPI_CalculateCRC() function. - (#@) Enable the CRC calculation using the SPI_CalculateCRC() function. - (#@) Enable SPI using the SPI_Cmd() function. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the CRC calculation length for the selected SPI. - * @note This function can be called only after the SPI_Init() function has - * been called. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @note SPI2 is not available for STM32F031 devices. - * @param SPI_CRCLength: specifies the SPI CRC calculation length. - * This parameter can be one of the following values: - * @arg SPI_CRCLength_8b: Set CRC Calculation to 8 bits - * @arg SPI_CRCLength_16b: Set CRC Calculation to 16 bits - * @retval None - */ -void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_CRC_LENGTH(SPI_CRCLength)); - - /* Clear CRCL bit */ - SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCL); - - /* Set new CRCL bit value */ - SPIx->CR1 |= SPI_CRCLength; -} - -/** - * @brief Enables or disables the CRC value calculation of the transferred bytes. - * @note This function can be called only after the SPI_Init() function has - * been called. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @note SPI2 is not available for STM32F031 devices. - * @param NewState: new state of the SPIx CRC value calculation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected SPI CRC calculation */ - SPIx->CR1 |= SPI_CR1_CRCEN; - } - else - { - /* Disable the selected SPI CRC calculation */ - SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN); - } -} - -/** - * @brief Transmit the SPIx CRC value. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @note SPI2 is not available for STM32F031 devices. - * @retval None - */ -void SPI_TransmitCRC(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Enable the selected SPI CRC transmission */ - SPIx->CR1 |= SPI_CR1_CRCNEXT; -} - -/** - * @brief Returns the transmit or the receive CRC register value for the specified SPI. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @note SPI2 is not available for STM32F031 devices. - * @param SPI_CRC: specifies the CRC register to be read. - * This parameter can be one of the following values: - * @arg SPI_CRC_Tx: Selects Tx CRC register - * @arg SPI_CRC_Rx: Selects Rx CRC register - * @retval The selected CRC register value.. - */ -uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC) -{ - uint16_t crcreg = 0; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_CRC(SPI_CRC)); - - if (SPI_CRC != SPI_CRC_Rx) - { - /* Get the Tx CRC register */ - crcreg = SPIx->TXCRCR; - } - else - { - /* Get the Rx CRC register */ - crcreg = SPIx->RXCRCR; - } - /* Return the selected CRC register */ - return crcreg; -} - -/** - * @brief Returns the CRC Polynomial register value for the specified SPI. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @note SPI2 is not available for STM32F031 devices. - * @retval The CRC Polynomial register value. - */ -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Return the CRC polynomial register */ - return SPIx->CRCPR; -} - -/** - * @} - */ - -/** @defgroup SPI_Group4 DMA transfers management functions - * @brief DMA transfers management functions - * -@verbatim - =============================================================================== - ##### DMA transfers management functions ##### - =============================================================================== - [..] This section provides two functions that can be used only in DMA mode. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the SPIx/I2Sx DMA interface. - * @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select - * the SPI peripheral. - * @note SPI2 is not available for STM32F031 devices. - * I2S mode is not supported for STM32F030 devices. - * @param SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request - * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request - * @param NewState: new state of the selected SPI DMA transfer request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_SPI_I2S_DMA_REQ(SPI_I2S_DMAReq)); - - if (NewState != DISABLE) - { - /* Enable the selected SPI DMA requests */ - SPIx->CR2 |= SPI_I2S_DMAReq; - } - else - { - /* Disable the selected SPI DMA requests */ - SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq; - } -} - -/** - * @brief Configures the number of data to transfer type(Even/Odd) for the DMA - * last transfers and for the selected SPI. - * @note This function have a meaning only if DMA mode is selected and if - * the packing mode is used (data length <= 8 and DMA transfer size halfword) - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @note SPI2 is not available for STM32F031 devices. - * @param SPI_LastDMATransfer: specifies the SPI last DMA transfers state. - * This parameter can be one of the following values: - * @arg SPI_LastDMATransfer_TxEvenRxEven: Number of data for transmission Even - * and number of data for reception Even. - * @arg SPI_LastDMATransfer_TxOddRxEven: Number of data for transmission Odd - * and number of data for reception Even. - * @arg SPI_LastDMATransfer_TxEvenRxOdd: Number of data for transmission Even - * and number of data for reception Odd. - * @arg SPI_LastDMATransfer_TxOddRxOdd: Number of data for transmission Odd - * and number of data for reception Odd. - * @retval None - */ -void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_LAST_DMA_TRANSFER(SPI_LastDMATransfer)); - - /* Clear LDMA_TX and LDMA_RX bits */ - SPIx->CR2 &= CR2_LDMA_MASK; - - /* Set new LDMA_TX and LDMA_RX bits value */ - SPIx->CR2 |= SPI_LastDMATransfer; -} - -/** - * @} - */ - -/** @defgroup SPI_Group5 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - [..] This section provides a set of functions allowing to configure the SPI/I2S Interrupts - sources and check or clear the flags or pending bits status. - The user should identify which mode will be used in his application to manage - the communication: Polling mode, Interrupt mode or DMA mode. - - *** Polling Mode *** - ==================== - [..] In Polling Mode, the SPI/I2S communication can be managed by 9 flags: - (#) SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register - (#) SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register - (#) SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI. - (#) SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur - (#) SPI_FLAG_MODF : to indicate if a Mode Fault error occur - (#) SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur - (#) SPI_I2S_FLAG_FRE: to indicate a Frame Format error occurs. - (#) I2S_FLAG_UDR: to indicate an Underrun error occurs. - (#) I2S_FLAG_CHSIDE: to indicate Channel Side. - - [..] - (@)Do not use the BSY flag to handle each data transmission or reception. It is better - to use the TXE and RXNE flags instead. - - [..] In this Mode it is advised to use the following functions: - (+) FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); - (+) void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); - - *** Interrupt Mode *** - ====================== - [..] In Interrupt Mode, the SPI/I2S communication can be managed by 3 interrupt sources - and 5 pending bits: - [..] Pending Bits: - (#) SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register - (#) SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register - (#) SPI_I2S_IT_OVR : to indicate if an Overrun error occur - (#) I2S_IT_UDR : to indicate an Underrun Error occurs. - (#) SPI_I2S_FLAG_FRE : to indicate a Frame Format error occurs. - - [..] Interrupt Source: - (#) SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty - interrupt. - (#) SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not - empty interrupt. - (#) SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt. - - [..] In this Mode it is advised to use the following functions: - (+) void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); - (+) ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); - - *** FIFO Status *** - =================== - [..] It is possible to monitor the FIFO status when a transfer is ongoing using the - following function: - (+) uint32_t SPI_GetFIFOStatus(uint8_t SPI_FIFO_Direction); - - *** DMA Mode *** - ================ - [..] In DMA Mode, the SPI communication can be managed by 2 DMA Channel - requests: - (#) SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request. - (#) SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request. - - [..] In this Mode it is advised to use the following function: - (+) void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState). - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified SPI/I2S interrupts. - * @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select - * the SPI peripheral. - * @note SPI2 is not available for STM32F031 devices. - * I2S mode is not supported for STM32F030 devices. - * @param SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled. - * This parameter can be one of the following values: - * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask - * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask - * @arg SPI_I2S_IT_ERR: Error interrupt mask - * @param NewState: new state of the specified SPI interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) -{ - uint16_t itpos = 0, itmask = 0 ; - - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT)); - - /* Get the SPI IT index */ - itpos = SPI_I2S_IT >> 4; - - /* Set the IT mask */ - itmask = (uint16_t)1 << (uint16_t)itpos; - - if (NewState != DISABLE) - { - /* Enable the selected SPI interrupt */ - SPIx->CR2 |= itmask; - } - else - { - /* Disable the selected SPI interrupt */ - SPIx->CR2 &= (uint16_t)~itmask; - } -} - -/** - * @brief Returns the current SPIx Transmission FIFO filled level. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @note SPI2 is not available for STM32F031 devices. - * @retval The Transmission FIFO filling state. - * - SPI_TransmissionFIFOStatus_Empty: when FIFO is empty - * - SPI_TransmissionFIFOStatus_1QuarterFull: if more than 1 quarter-full. - * - SPI_TransmissionFIFOStatus_HalfFull: if more than 1 half-full. - * - SPI_TransmissionFIFOStatus_Full: when FIFO is full. - */ -uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx) -{ - /* Get the SPIx Transmission FIFO level bits */ - return (uint16_t)((SPIx->SR & SPI_SR_FTLVL)); -} - -/** - * @brief Returns the current SPIx Reception FIFO filled level. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @note SPI2 is not available for STM32F031 devices. - * @retval The Reception FIFO filling state. - * - SPI_ReceptionFIFOStatus_Empty: when FIFO is empty - * - SPI_ReceptionFIFOStatus_1QuarterFull: if more than 1 quarter-full. - * - SPI_ReceptionFIFOStatus_HalfFull: if more than 1 half-full. - * - SPI_ReceptionFIFOStatus_Full: when FIFO is full. - */ -uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx) -{ - /* Get the SPIx Reception FIFO level bits */ - return (uint16_t)((SPIx->SR & SPI_SR_FRLVL)); -} - -/** - * @brief Checks whether the specified SPI flag is set or not. - * @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select - * the SPI peripheral. - * @note SPI2 is not available for STM32F031 devices. - * I2S mode is not supported for STM32F030 devices. - * @param SPI_I2S_FLAG: specifies the SPI flag to check. - * This parameter can be one of the following values: - * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag. - * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag. - * @arg SPI_I2S_FLAG_BSY: Busy flag. - * @arg SPI_I2S_FLAG_OVR: Overrun flag. - * @arg SPI_FLAG_MODF: Mode Fault flag. - * @arg SPI_FLAG_CRCERR: CRC Error flag. - * @arg SPI_I2S_FLAG_FRE: TI frame format error flag. - * @arg I2S_FLAG_UDR: Underrun Error flag. - * @arg I2S_FLAG_CHSIDE: Channel Side flag. - * @retval The new state of SPI_I2S_FLAG (SET or RESET). - */ -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG)); - - /* Check the status of the specified SPI flag */ - if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET) - { - /* SPI_I2S_FLAG is set */ - bitstatus = SET; - } - else - { - /* SPI_I2S_FLAG is reset */ - bitstatus = RESET; - } - /* Return the SPI_I2S_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the SPIx CRC Error (CRCERR) flag. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @note SPI2 is not available for STM32F031 devices. - * I2S mode is not supported for STM32F030 devices. - * @param SPI_I2S_FLAG: specifies the SPI flag to clear. - * This function clears only CRCERR flag. - * @note OVR (OverRun error) flag is cleared by software sequence: a read - * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by - * a read operation to SPI_SR register (SPI_I2S_GetFlagStatus()). - * @note MODF (Mode Fault) flag is cleared by software sequence: a read/write - * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by - * a write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI). - * @retval None - */ -void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_CLEAR_FLAG(SPI_I2S_FLAG)); - - /* Clear the selected SPI CRC Error (CRCERR) flag */ - SPIx->SR = (uint16_t)~SPI_I2S_FLAG; -} - -/** - * @brief Checks whether the specified SPI/I2S interrupt has occurred or not. - * @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select - * the SPI peripheral. - * @param SPI_I2S_IT: specifies the SPI interrupt source to check. - * This parameter can be one of the following values: - * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt. - * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt. - * @arg SPI_IT_MODF: Mode Fault interrupt. - * @arg SPI_I2S_IT_OVR: Overrun interrupt. - * @arg I2S_IT_UDR: Underrun interrupt. - * @arg SPI_I2S_IT_FRE: Format Error interrupt. - * @retval The new state of SPI_I2S_IT (SET or RESET). - */ -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itpos = 0, itmask = 0, enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT)); - - /* Get the SPI_I2S_IT index */ - itpos = 0x01 << (SPI_I2S_IT & 0x0F); - - /* Get the SPI_I2S_IT IT mask */ - itmask = SPI_I2S_IT >> 4; - - /* Set the IT mask */ - itmask = 0x01 << itmask; - - /* Get the SPI_I2S_IT enable bit status */ - enablestatus = (SPIx->CR2 & itmask) ; - - /* Check the status of the specified SPI interrupt */ - if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus) - { - /* SPI_I2S_IT is set */ - bitstatus = SET; - } - else - { - /* SPI_I2S_IT is reset */ - bitstatus = RESET; - } - /* Return the SPI_I2S_IT status */ - return bitstatus; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_syscfg.c b/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_syscfg.c deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_syscfg.c +++ /dev/null @@ -1,420 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_syscfg.c - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the SYSCFG peripheral: - * + Remapping the memory mapped at 0x00000000 - * + Remapping the DMA channels - * + Enabling I2C fast mode plus driving capability for I2C pins - * + Configuring the EXTI lines connection to the GPIO port - * + Configuring the CFGR2 features (Connecting some internal signal - * to the break input of TIM1) - * - * @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - The SYSCFG registers can be accessed only when the SYSCFG - interface APB clock is enabled. - To enable SYSCFG APB clock use: - RCC_APBPeriphClockCmd(RCC_APBPeriph_SYSCFG, ENABLE). - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_syscfg.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup SYSCFG - * @brief SYSCFG driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup SYSCFG_Private_Functions - * @{ - */ - -/** @defgroup SYSCFG_Group1 SYSCFG Initialization and Configuration functions - * @brief SYSCFG Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### SYSCFG Initialization and Configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the SYSCFG registers to their default reset values. - * @param None - * @retval None - * @note MEM_MODE bits are not affected by APB reset. - * @note MEM_MODE bits took the value from the user option bytes. - * @note CFGR2 register is not affected by APB reset. - * @note CLABBB configuration bits are locked when set. - * @note To unlock the configuration, perform a system reset. - */ -void SYSCFG_DeInit(void) -{ - /* Set SYSCFG_CFGR1 register to reset value without affecting MEM_MODE bits */ - SYSCFG->CFGR1 &= SYSCFG_CFGR1_MEM_MODE; - /* Set EXTICRx registers to reset value */ - SYSCFG->EXTICR[0] = 0; - SYSCFG->EXTICR[1] = 0; - SYSCFG->EXTICR[2] = 0; - SYSCFG->EXTICR[3] = 0; - /* Set CFGR2 register to reset value: clear SRAM parity error flag */ - SYSCFG->CFGR2 |= (uint32_t) SYSCFG_CFGR2_SRAM_PE; -} - -/** - * @brief Configures the memory mapping at address 0x00000000. - * @param SYSCFG_MemoryRemap: selects the memory remapping. - * This parameter can be one of the following values: - * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000 - * @arg SYSCFG_MemoryRemap_SystemMemory: System Flash memory mapped at 0x00000000 - * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000 - * @retval None - */ -void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap) -{ - uint32_t tmpctrl = 0; - - /* Check the parameter */ - assert_param(IS_SYSCFG_MEMORY_REMAP(SYSCFG_MemoryRemap)); - - /* Get CFGR1 register value */ - tmpctrl = SYSCFG->CFGR1; - - /* Clear MEM_MODE bits */ - tmpctrl &= (uint32_t) (~SYSCFG_CFGR1_MEM_MODE); - - /* Set the new MEM_MODE bits value */ - tmpctrl |= (uint32_t) SYSCFG_MemoryRemap; - - /* Set CFGR1 register with the new memory remap configuration */ - SYSCFG->CFGR1 = tmpctrl; -} - -/** - * @brief Configure the DMA channels remapping. - * @param SYSCFG_DMARemap: selects the DMA channels remap. - * This parameter can be one of the following values: - * @arg SYSCFG_DMARemap_TIM17: Remap TIM17 DMA requests from channel1 to channel2 - * @arg SYSCFG_DMARemap_TIM16: Remap TIM16 DMA requests from channel3 to channel4 - * @arg SYSCFG_DMARemap_USART1Rx: Remap USART1 Rx DMA requests from channel3 to channel5 - * @arg SYSCFG_DMARemap_USART1Tx: Remap USART1 Tx DMA requests from channel2 to channel4 - * @arg SYSCFG_DMARemap_ADC1: Remap ADC1 DMA requests from channel1 to channel2 - * @param NewState: new state of the DMA channel remapping. - * This parameter can be: ENABLE or DISABLE. - * @note When enabled, DMA channel of the selected peripheral is remapped - * @note When disabled, Default DMA channel is mapped to the selected peripheral - * @note By default TIM17 DMA requests is mapped to channel 1, - * use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Enable) to remap - * TIM17 DMA requests to channel 2 and use - * SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Disable) to map - * TIM17 DMA requests to channel 1 (default mapping) - * @note This function is only used for STM32F030, STM32F031, STM32F042, STM32F072 and STM32F051 devices. - * @retval None - */ -void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SYSCFG_DMA_REMAP(SYSCFG_DMARemap)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Remap the DMA channel */ - SYSCFG->CFGR1 |= (uint32_t)SYSCFG_DMARemap; - } - else - { - /* use the default DMA channel mapping */ - SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_DMARemap); - } -} - -/** - * @brief Configure the I2C fast mode plus driving capability. - * @param SYSCFG_I2CFastModePlus: selects the pin. - * This parameter can be one of the following values: - * @arg SYSCFG_I2CFastModePlus_PB6: Configure fast mode plus driving capability for PB6 - * @arg SYSCFG_I2CFastModePlus_PB7: Configure fast mode plus driving capability for PB7 - * @arg SYSCFG_I2CFastModePlus_PB8: Configure fast mode plus driving capability for PB8 - * @arg SYSCFG_I2CFastModePlus_PB9: Configure fast mode plus driving capability for PB9 - * @arg SYSCFG_I2CFastModePlus_PA9: Configure fast mode plus driving capability for PA9 (only for STM32F031 and STM32F030 devices) - * @arg SYSCFG_I2CFastModePlus_PA10: Configure fast mode plus driving capability for PA10 (only for STM32F031 and STM32F030 devices) - * @arg SYSCFG_I2CFastModePlus_I2C1: Configure fast mode plus driving capability for PB10, PB11, PF6 and PF7(only for STM32F031 and STM32F030 devices) - * @arg SYSCFG_I2CFastModePlus_I2C2: Configure fast mode plus driving capability for I2C2 pins, available only for STM32F072 devices - * - * @param NewState: new state of the DMA channel remapping. - * This parameter can be: ENABLE or DISABLE. - * @note ENABLE: Enable fast mode plus driving capability for selected I2C pin - * @note DISABLE: Disable fast mode plus driving capability for selected I2C pin - * @note For I2C1, fast mode plus driving capability can be enabled on all selected - * I2C1 pins using SYSCFG_I2CFastModePlus_I2C1 parameter or independently - * on each one of the following pins PB6, PB7, PB8 and PB9. - * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability - * can be enabled only by using SYSCFG_I2CFastModePlus_I2C1 parameter. - * @note For all I2C2 pins fast mode plus driving capability can be enabled - * only by using SYSCFG_I2CFastModePlus_I2C2 parameter. - * @retval None - */ -void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SYSCFG_I2C_FMP(SYSCFG_I2CFastModePlus)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable fast mode plus driving capability for selected pin */ - SYSCFG->CFGR1 |= (uint32_t)SYSCFG_I2CFastModePlus; - } - else - { - /* Disable fast mode plus driving capability for selected pin */ - SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_I2CFastModePlus); - } -} - -/** @brief select the modulation envelope source - * @param SYSCFG_IRDAEnv: select the envelope source. - * This parameter can be a value - * @arg SYSCFG_IRDA_ENV_SEL_TIM16 - * @arg SYSCFG_IRDA_ENV_SEL_USART1 - * @arg SYSCFG_IRDA_ENV_SEL_USART4 - * @retval None - */ -void SYSCFG_IRDAEnvSelection(uint32_t SYSCFG_IRDAEnv) -{ - /* Check the parameters */ - assert_param(IS_SYSCFG_IRDA_ENV(SYSCFG_IRDAEnv)); - - SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_IRDA_ENV_SEL); - SYSCFG->CFGR1 |= (SYSCFG_IRDAEnv); -} - -/** - * @brief Selects the GPIO pin used as EXTI Line. - * @param EXTI_PortSourceGPIOx: selects the GPIO port to be used as source - * for EXTI lines where x can be (A, B, C, D, E or F). - * @note GPIOE is available only for STM32F072. - * @note GPIOD is not available for STM32F031. - * @param EXTI_PinSourcex: specifies the EXTI line to be configured. - * @note This parameter can be EXTI_PinSourcex where x can be: - * For STM32F051 and STM32F030: (0..15) for GPIOA, GPIOB, GPIOC, (2) for GPIOD and (0..1, 4..7) for GIIOF. - * For STM32F072: (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF. - * For STM32F031: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOF. - * @retval None - */ -void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex) -{ - uint32_t tmp = 0x00; - - /* Check the parameters */ - assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx)); - assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex)); - - tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)); - SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp; - SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03))); -} - -/** - * @brief check ISR wrapper: Allow to determine interrupt source per line . - * @param IT_Source: specifies the interrupt source to check. - * This parameter can be one of the following values: - * @arg ITLINE_EWDG EWDG has expired - * @arg ITLINE_PVDOUT Power voltage detection Interrupt - * @arg ITLINE_VDDIO2 VDDIO2 Interrupt - * @arg ITLINE_RTC_WAKEUP RTC WAKEUP -> exti[20] Interrupt - * @arg ITLINE_RTC_TSTAMP RTC Time Stamp -> exti[19] interrupt - * @arg ITLINE_RTC_ALRA RTC Alarm -> exti[17] interrupt - * @arg ITLINE_FLASH_ITF Flash ITF Interrupt - * @arg ITLINE_CRS CRS Interrupt - * @arg ITLINE_CLK_CTRL CLK Control Interrupt - * @arg ITLINE_EXTI0 External Interrupt 0 - * @arg ITLINE_EXTI1 External Interrupt 1 - * @arg ITLINE_EXTI2 External Interrupt 2 - * @arg ITLINE_EXTI3 External Interrupt 3 - * @arg ITLINE_EXTI4 External Interrupt 4 - * @arg ITLINE_EXTI5 External Interrupt 5 - * @arg ITLINE_EXTI6 External Interrupt 6 - * @arg ITLINE_EXTI7 External Interrupt 7 - * @arg ITLINE_EXTI8 External Interrupt 8 - * @arg ITLINE_EXTI9 External Interrupt 9 - * @arg ITLINE_EXTI10 External Interrupt 10 - * @arg ITLINE_EXTI11 External Interrupt 11 - * @arg ITLINE_EXTI12 External Interrupt 12 - * @arg ITLINE_EXTI13 External Interrupt 13 - * @arg ITLINE_EXTI14 External Interrupt 14 - * @arg ITLINE_EXTI15 External Interrupt 15 - * @arg ITLINE_TSC_EOA Touch control EOA Interrupt - * @arg ITLINE_TSC_MCE Touch control MCE Interrupt - * @arg ITLINE_DMA1_CH1 DMA1 Channel 1 Interrupt - * @arg ITLINE_DMA1_CH2 DMA1 Channel 2 Interrupt - * @arg ITLINE_DMA1_CH3 DMA1 Channel 3 Interrupt - * @arg ITLINE_DMA2_CH1 DMA2 Channel 1 Interrupt - * @arg ITLINE_DMA2_CH2 DMA2 Channel 2 Interrupt - * @arg ITLINE_DMA1_CH4 DMA1 Channel 4 Interrupt - * @arg ITLINE_DMA1_CH5 DMA1 Channel 5 Interrupt - * @arg ITLINE_DMA1_CH6 DMA1 Channel 6 Interrupt - * @arg ITLINE_DMA1_CH7 DMA1 Channel 7 Interrupt - * @arg ITLINE_DMA2_CH3 DMA2 Channel 3 Interrupt - * @arg ITLINE_DMA2_CH4 DMA2 Channel 4 Interrupt - * @arg ITLINE_DMA2_CH5 DMA2 Channel 5 Interrupt - * @arg ITLINE_ADC ADC Interrupt - * @arg ITLINE_COMP1 COMP1 Interrupt -> exti[21] - * @arg ITLINE_COMP2 COMP2 Interrupt -> exti[21] - * @arg ITLINE_TIM1_BRK TIM1 BRK Interrupt - * @arg ITLINE_TIM1_UPD TIM1 UPD Interrupt - * @arg ITLINE_TIM1_TRG TIM1 TRG Interrupt - * @arg ITLINE_TIM1_CCU TIM1 CCU Interrupt - * @arg ITLINE_TIM1_CC TIM1 CC Interrupt - * @arg ITLINE_TIM2 TIM2 Interrupt - * @arg ITLINE_TIM3 TIM3 Interrupt - * @arg ITLINE_DAC DAC Interrupt - * @arg ITLINE_TIM6 TIM6 Interrupt - * @arg ITLINE_TIM7 TIM7 Interrupt - * @arg ITLINE_TIM14 TIM14 Interrupt - * @arg ITLINE_TIM15 TIM15 Interrupt - * @arg ITLINE_TIM16 TIM16 Interrupt - * @arg ITLINE_TIM17 TIM17 Interrupt - * @arg ITLINE_I2C1 I2C1 Interrupt -> exti[23] - * @arg ITLINE_I2C2 I2C2 Interrupt - * @arg ITLINE_SPI1 I2C1 Interrupt -> exti[23] - * @arg ITLINE_SPI2 SPI1 Interrupt - * @arg ITLINE_USART1 USART1 GLB Interrupt -> exti[25] - * @arg ITLINE_USART2 USART2 GLB Interrupt -> exti[26] - * @arg ITLINE_USART3 USART3 Interrupt - * @arg ITLINE_USART4 USART4 Interrupt - * @arg ITLINE_USART5 USART5 Interrupt - * @arg ITLINE_USART6 USART6 Interrupt - * @arg ITLINE_USART7 USART7 Interrupt - * @arg ITLINE_USART8 USART8 Interrupt - * @arg ITLINE_CAN CAN Interrupt - * @arg ITLINE_CEC CEC Interrupt - * @retval The new state of IT_LINE_SR. - */ -uint32_t SYSCFG_GetPendingIT(uint32_t ITSourceLine) -{ - assert_param(IS_SYSCFG_ITLINE(ITSourceLine)); - return(SYSCFG->IT_LINE_SR[(ITSourceLine >> 0x18)] & (ITSourceLine & 0x00FFFFFF)); -} - -/** - * @brief Connect the selected parameter to the break input of TIM1. - * @note The selected configuration is locked and can be unlocked by system reset - * @param SYSCFG_Break: selects the configuration to be connected to break - * input of TIM1 - * This parameter can be any combination of the following values: - * @arg SYSCFG_Break_PVD: Connects the PVD event to the Break Input of TIM1,, not available for STM32F030 devices. - * @arg SYSCFG_Break_SRAMParity: Connects the SRAM_PARITY error signal to the Break Input of TIM1 . - * @arg SYSCFG_Break_Lockup: Connects Lockup output of CortexM0 to the break input of TIM1. - * @retval None - */ -void SYSCFG_BreakConfig(uint32_t SYSCFG_Break) -{ - /* Check the parameter */ - assert_param(IS_SYSCFG_LOCK_CONFIG(SYSCFG_Break)); - - SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Break; -} - -/** - * @brief Checks whether the specified SYSCFG flag is set or not. - * @param SYSCFG_Flag: specifies the SYSCFG flag to check. - * This parameter can be one of the following values: - * @arg SYSCFG_FLAG_PE: SRAM parity error flag. - * @retval The new state of SYSCFG_Flag (SET or RESET). - */ -FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameter */ - assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag)); - - /* Check the status of the specified SPI flag */ - if ((SYSCFG->CFGR2 & SYSCFG_CFGR2_SRAM_PE) != (uint32_t)RESET) - { - /* SYSCFG_Flag is set */ - bitstatus = SET; - } - else - { - /* SYSCFG_Flag is reset */ - bitstatus = RESET; - } - /* Return the SYSCFG_Flag status */ - return bitstatus; -} - -/** - * @brief Clear the selected SYSCFG flag. - * @param SYSCFG_Flag: selects the flag to be cleared. - * This parameter can be any combination of the following values: - * @arg SYSCFG_FLAG_PE: SRAM parity error flag. - * @retval None - */ -void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag) -{ - /* Check the parameter */ - assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag)); - - SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Flag; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_tim.c b/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_tim.c deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_tim.c +++ /dev/null @@ -1,3349 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_tim.c - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the TIM peripheral: - * + TimeBase management - * + Output Compare management - * + Input Capture management - * + Interrupts, DMA and flags management - * + Clocks management - * + Synchronization management - * + Specific interface management - * + Specific remapping management - * - * @verbatim - - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] This driver provides functions to configure and program the TIM - of all STM32F0xx devices These functions are split in 8 groups: - (#) TIM TimeBase management: this group includes all needed functions - to configure the TM Timebase unit: - (++) Set/Get Prescaler. - (++) Set/Get Autoreload. - (++) Counter modes configuration. - (++) Set Clock division. - (++) Select the One Pulse mode. - (++) Update Request Configuration. - (++) Update Disable Configuration. - (++) Auto-Preload Configuration. - (++) Enable/Disable the counter. - - (#) TIM Output Compare management: this group includes all needed - functions to configure the Capture/Compare unit used in Output - compare mode: - (++) Configure each channel, independently, in Output Compare mode. - (++) Select the output compare modes. - (++) Select the Polarities of each channel. - (++) Set/Get the Capture/Compare register values. - (++) Select the Output Compare Fast mode. - (++) Select the Output Compare Forced mode. - (++) Output Compare-Preload Configuration. - (++) Clear Output Compare Reference. - (++) Select the OCREF Clear signal. - (++) Enable/Disable the Capture/Compare Channels. - - (#) TIM Input Capture management: this group includes all needed - functions to configure the Capture/Compare unit used in - Input Capture mode: - (++) Configure each channel in input capture mode. - (++) Configure Channel1/2 in PWM Input mode. - (++) Set the Input Capture Prescaler. - (++) Get the Capture/Compare values. - - (#) Advanced-control timers (TIM1) specific features - (++) Configures the Break input, dead time, Lock level, the OSSI, - the OSSR State and the AOE(automatic output enable) - (++) Enable/Disable the TIM peripheral Main Outputs - (++) Select the Commutation event - (++) Set/Reset the Capture Compare Preload Control bit - - (#) TIM interrupts, DMA and flags management. - (++) Enable/Disable interrupt sources. - (++) Get flags status. - (++) Clear flags/ Pending bits. - (++) Enable/Disable DMA requests. - (++) Configure DMA burst mode. - (++) Select CaptureCompare DMA request. - - (#) TIM clocks management: this group includes all needed functions - to configure the clock controller unit: - (++) Select internal/External clock. - (++) Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx. - - (#) TIM synchronization management: this group includes all needed. - functions to configure the Synchronization unit: - (++) Select Input Trigger. - (++) Select Output Trigger. - (++) Select Master Slave Mode. - (++) ETR Configuration when used as external trigger. - - (#) TIM specific interface management, this group includes all - needed functions to use the specific TIM interface: - (++) Encoder Interface Configuration. - (++) Select Hall Sensor. - - (#) TIM specific remapping management includes the Remapping - configuration of specific timers - -@endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_tim.h" -#include "stm32f0xx_rcc.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup TIM - * @brief TIM driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* ---------------------- TIM registers bit mask ------------------------ */ -#define SMCR_ETR_MASK ((uint16_t)0x00FF) -#define CCMR_OFFSET ((uint16_t)0x0018) -#define CCER_CCE_SET ((uint16_t)0x0001) -#define CCER_CCNE_SET ((uint16_t)0x0004) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ - -static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup TIM_Private_Functions - * @{ - */ - -/** @defgroup TIM_Group1 TimeBase management functions - * @brief TimeBase management functions - * -@verbatim - =============================================================================== - ##### TimeBase management functions ##### - =============================================================================== - - *** TIM Driver: how to use it in Timing(Time base) Mode *** - =============================================================================== - [..] To use the Timer in Timing(Time base) mode, the following steps are - mandatory: - (#) Enable TIM clock using - RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function. - (#) Fill the TIM_TimeBaseInitStruct with the desired parameters. - (#) Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure - the Time Base unit with the corresponding configuration. - (#) Enable the NVIC if you need to generate the update interrupt. - (#) Enable the corresponding interrupt using the function - TIM_ITConfig(TIMx, TIM_IT_Update). - (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. - [..] - (@) All other functions can be used seperatly to modify, if needed, - a specific feature of the Timer. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the TIMx peripheral registers to their default reset values. - * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM peripheral. - * @note TIM7 is applicable only for STM32F072 devices - * @note TIM6 is not applivable for STM32F031 devices. - * @note TIM2 is not applicable for STM32F030 devices. - * @retval None - * - */ -void TIM_DeInit(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - if (TIMx == TIM1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); - } - else if (TIMx == TIM2) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); - } - else if (TIMx == TIM3) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); - } - else if (TIMx == TIM6) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); - } - else if (TIMx == TIM7) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); - } - else if (TIMx == TIM14) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE); - } - else if (TIMx == TIM15) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE); - } - else if (TIMx == TIM16) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE); - } - else - { - if (TIMx == TIM17) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE); - } - } - -} - -/** - * @brief Initializes the TIMx Time Base Unit peripheral according to - * the specified parameters in the TIM_TimeBaseInitStruct. - * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM - * peripheral. - * @note TIM7 is applicable only for STM32F072 devices - * @note TIM6 is not applivable for STM32F031 devices. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef - * structure that contains the configuration information for - * the specified TIM peripheral. - * @retval None - */ -void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) -{ - uint16_t tmpcr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); - assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); - - tmpcr1 = TIMx->CR1; - - if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3)) - { - /* Select the Counter Mode */ - tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS))); - tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; - } - - if(TIMx != TIM6) - { - /* Set the clock division */ - tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD)); - tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; - } - - TIMx->CR1 = tmpcr1; - - /* Set the Autoreload value */ - TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; - - /* Set the Prescaler value */ - TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; - - if ((TIMx == TIM1) || (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17)) - { - /* Set the Repetition Counter value */ - TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; - } - - /* Generate an update event to reload the Prescaler and the Repetition counter - values immediately */ - TIMx->EGR = TIM_PSCReloadMode_Immediate; -} - -/** - * @brief Fills each TIM_TimeBaseInitStruct member with its default value. - * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef structure - * which will be initialized. - * @retval None - */ -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) -{ - /* Set the default configuration */ - TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF; - TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; - TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; - TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; - TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; -} - -/** - * @brief Configures the TIMx Prescaler. - * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM peripheral. - * @note TIM7 is applicable only for STM32F072 devices - * @note TIM6 is not applivable for STM32F031 devices. - * @note TIM2 is not applicable for STM32F030 devices. - * @param Prescaler: specifies the Prescaler Register value - * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode - * This parameter can be one of the following values: - * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event. - * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly. - * @retval None - */ -void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode)); - - /* Set the Prescaler value */ - TIMx->PSC = Prescaler; - /* Set or reset the UG Bit */ - TIMx->EGR = TIM_PSCReloadMode; -} - -/** - * @brief Specifies the TIMx Counter Mode to be used. - * @param TIMx: where x can be 1, 2, or 3 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_CounterMode: specifies the Counter Mode to be used - * This parameter can be one of the following values: - * @arg TIM_CounterMode_Up: TIM Up Counting Mode - * @arg TIM_CounterMode_Down: TIM Down Counting Mode - * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 - * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 - * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 - * @retval None - */ -void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode) -{ - uint16_t tmpcr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode)); - - tmpcr1 = TIMx->CR1; - /* Reset the CMS and DIR Bits */ - tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS))); - /* Set the Counter Mode */ - tmpcr1 |= TIM_CounterMode; - /* Write to TIMx CR1 register */ - TIMx->CR1 = tmpcr1; -} - -/** - * @brief Sets the TIMx Counter Register value - * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM - * peripheral. - * @note TIM7 is applicable only for STM32F072 devices - * @note TIM6 is not applivable for STM32F031 devices. - * @note TIM2 is not applicable for STM32F030 devices. - * @param Counter: specifies the Counter register new value. - * @retval None - */ -void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Set the Counter Register value */ - TIMx->CNT = Counter; -} - -/** - * @brief Sets the TIMx Autoreload Register value - * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM peripheral. - * @note TIM7 is applicable only for STM32F072 devices - * @note TIM6 is not applivable for STM32F031 devices. - * @note TIM2 is not applicable for STM32F030 devices. - * @param Autoreload: specifies the Autoreload register new value. - * @retval None - */ -void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Set the Autoreload Register value */ - TIMx->ARR = Autoreload; -} - -/** - * @brief Gets the TIMx Counter value. - * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM - * peripheral. - * @note TIM7 is applicable only for STM32F072 devices - * @note TIM6 is not applivable for STM32F031 devices. - * @note TIM2 is not applicable for STM32F030 devices. - * @retval Counter Register value. - */ -uint32_t TIM_GetCounter(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Get the Counter Register value */ - return TIMx->CNT; -} - -/** - * @brief Gets the TIMx Prescaler value. - * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM - * peripheral. - * @note TIM7 is applicable only for STM32F072 devices - * @note TIM6 is not applivable for STM32F031 devices. - * @note TIM2 is not applicable for STM32F030 devices. - * @retval Prescaler Register value. - */ -uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Get the Prescaler Register value */ - return TIMx->PSC; -} - -/** - * @brief Enables or Disables the TIMx Update event. - * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM - * peripheral. - * @note TIM7 is applicable only for STM32F072 devices - * @note TIM6 is not applivable for STM32F031 devices. - * @note TIM2 is not applicable for STM32F030 devices. - * @param NewState: new state of the TIMx UDIS bit - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the Update Disable Bit */ - TIMx->CR1 |= TIM_CR1_UDIS; - } - else - { - /* Reset the Update Disable Bit */ - TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS); - } -} - -/** - * @brief Configures the TIMx Update Request Interrupt source. - * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM - * peripheral. - * @note TIM7 is applicable only for STM32F072 devices - * @note TIM6 is not applivable for STM32F031 devices. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_UpdateSource: specifies the Update source. - * This parameter can be one of the following values: - * @arg TIM_UpdateSource_Regular: Source of update is the counter - * overflow/underflow or the setting of UG bit, or an update - * generation through the slave mode controller. - * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow. - * @retval None - */ -void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource)); - - if (TIM_UpdateSource != TIM_UpdateSource_Global) - { - /* Set the URS Bit */ - TIMx->CR1 |= TIM_CR1_URS; - } - else - { - /* Reset the URS Bit */ - TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS); - } -} - -/** - * @brief Enables or disables TIMx peripheral Preload register on ARR. - * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM - * peripheral. - * @note TIM7 is applicable only for STM32F072 devices - * @note TIM6 is not applivable for STM32F031 devices. - * @note TIM2 is not applicable for STM32F030 devices. - * @param NewState: new state of the TIMx peripheral Preload register - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the ARR Preload Bit */ - TIMx->CR1 |= TIM_CR1_ARPE; - } - else - { - /* Reset the ARR Preload Bit */ - TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE); - } -} - -/** - * @brief Selects the TIMx's One Pulse Mode. - * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM - * peripheral. - * @note TIM7 is applicable only for STM32F072 devices - * @note TIM6 is not applivable for STM32F031 devices. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_OPMode: specifies the OPM Mode to be used. - * This parameter can be one of the following values: - * @arg TIM_OPMode_Single - * @arg TIM_OPMode_Repetitive - * @retval None - */ -void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_OPM_MODE(TIM_OPMode)); - - /* Reset the OPM Bit */ - TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM); - /* Configure the OPM Mode */ - TIMx->CR1 |= TIM_OPMode; -} - -/** - * @brief Sets the TIMx Clock Division value. - * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 and 17 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_CKD: specifies the clock division value. - * This parameter can be one of the following value: - * @arg TIM_CKD_DIV1: TDTS = Tck_tim - * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim - * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim - * @retval None - */ -void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_CKD_DIV(TIM_CKD)); - - /* Reset the CKD Bits */ - TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD); - /* Set the CKD value */ - TIMx->CR1 |= TIM_CKD; -} - -/** - * @brief Enables or disables the specified TIM peripheral. - * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17to select the TIMx - * peripheral. - * @note TIM7 is applicable only for STM32F072 devices - * @note TIM6 is not applivable for STM32F031 devices. - * @note TIM2 is not applicable for STM32F030 devices. - * @param NewState: new state of the TIMx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the TIM Counter */ - TIMx->CR1 |= TIM_CR1_CEN; - } - else - { - /* Disable the TIM Counter */ - TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN)); - } -} - -/** - * @} - */ - -/** @defgroup TIM_Group2 Advanced-control timers (TIM1) specific features - * @brief Advanced-control timers (TIM1) specific features - * -@verbatim - =============================================================================== - ##### Advanced-control timers (TIM1) specific features ##### - =============================================================================== - - =================================================================== - *** TIM Driver: how to use the Break feature *** - =================================================================== - [..] After configuring the Timer channel(s) in the appropriate Output Compare mode: - - (#) Fill the TIM_BDTRInitStruct with the desired parameters for the Timer - Break Polarity, dead time, Lock level, the OSSI/OSSR State and the - AOE(automatic output enable). - - (#) Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer - - (#) Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE) - - (#) Once the break even occurs, the Timer's output signals are put in reset - state or in a known state (according to the configuration made in - TIM_BDTRConfig() function). - -@endverbatim - * @{ - */ -/** - * @brief Configures the: Break feature, dead time, Lock level, OSSI/OSSR State - * and the AOE(automatic output enable). - * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIM - * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that - * contains the BDTR Register configuration information for the TIM peripheral. - * @retval None - */ -void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState)); - assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState)); - assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel)); - assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break)); - assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity)); - assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput)); - /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State, - the OSSI State, the dead time value and the Automatic Output Enable Bit */ - TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | - TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | - TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | - TIM_BDTRInitStruct->TIM_AutomaticOutput; -} - -/** - * @brief Fills each TIM_BDTRInitStruct member with its default value. - * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which - * will be initialized. - * @retval None - */ -void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct) -{ - /* Set the default configuration */ - TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; - TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; - TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; - TIM_BDTRInitStruct->TIM_DeadTime = 0x00; - TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; - TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; - TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; -} - -/** - * @brief Enables or disables the TIM peripheral Main Outputs. - * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIMx peripheral. - * @param NewState: new state of the TIM peripheral Main Outputs. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the TIM Main Output */ - TIMx->BDTR |= TIM_BDTR_MOE; - } - else - { - /* Disable the TIM Main Output */ - TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE)); - } -} - -/** - * @} - */ - -/** @defgroup TIM_Group3 Output Compare management functions - * @brief Output Compare management functions - * -@verbatim - =============================================================================== - ##### Output Compare management functions ##### - =============================================================================== - *** TIM Driver: how to use it in Output Compare Mode *** - =============================================================================== - [..] To use the Timer in Output Compare mode, the following steps are mandatory: - (#) Enable TIM clock using - RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function. - (#) Configure the TIM pins by configuring the corresponding GPIO pins - (#) Configure the Time base unit as described in the first part of this - driver, if needed, else the Timer will run with the default - configuration: - (++) Autoreload value = 0xFFFF. - (++) Prescaler value = 0x0000. - (++) Counter mode = Up counting. - (++) Clock Division = TIM_CKD_DIV1. - (#) Fill the TIM_OCInitStruct with the desired parameters including: - (++) The TIM Output Compare mode: TIM_OCMode. - (++) TIM Output State: TIM_OutputState. - (++) TIM Pulse value: TIM_Pulse. - (++) TIM Output Compare Polarity : TIM_OCPolarity. - (#) Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired - channel with the corresponding configuration. - (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. - [..] - (@) All other functions can be used separately to modify, if needed, - a specific feature of the Timer. - (@) In case of PWM mode, this function is mandatory: - TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE). - (@) If the corresponding interrupt or DMA request are needed, the user should: - (#@) Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests). - (#@) Enable the corresponding interrupt (or DMA request) using the function - TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)). - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the TIMx Channel1 according to the specified - * parameters in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 and 17 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure - * that contains the configuration information for the specified TIM - * peripheral. - * @retval None - */ -void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E); - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare Mode Bits */ - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S)); - - /* Select the Output Compare Mode */ - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P)); - /* Set the Output Compare Polarity */ - tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; - - /* Set the Output State */ - tmpccer |= TIM_OCInitStruct->TIM_OutputState; - - if((TIMx == TIM1) || (TIMx == TIM15) || (TIMx == TIM16) || (TIMx == TIM17)) - { - assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - - /* Reset the Output N Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP)); - /* Set the Output N Polarity */ - tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; - - /* Reset the Output N State */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE)); - /* Set the Output N State */ - tmpccer |= TIM_OCInitStruct->TIM_OutputNState; - - /* Reset the Ouput Compare and Output Compare N IDLE State */ - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1)); - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N)); - - /* Set the Output Idle state */ - tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; - /* Set the Output N Idle state */ - tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel2 according to the specified - * parameters in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure - * that contains the configuration information for the specified TIM - * peripheral. - * @retval None - */ -void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E)); - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)); - - /* Select the Output Compare Mode */ - tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P)); - /* Set the Output Compare Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); - - /* Set the Output State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); - - if((TIMx == TIM1) || (TIMx == TIM15)) - { - /* Check the parameters */ - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - - /* Reset the Ouput Compare State */ - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2)); - - /* Set the Output Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); - - if (TIMx == TIM1) - { - /* Check the parameters */ - assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); - - /* Reset the Output N Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP)); - /* Set the Output N Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); - - /* Reset the Output N State */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE)); - /* Set the Output N State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); - - /* Reset the Output Compare N IDLE State */ - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N)); - - /* Set the Output N Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); - } - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel3 according to the specified - * parameters in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure - * that contains the configuration information for the specified TIM - * peripheral. - * @retval None - */ -void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E)); - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S)); - /* Select the Output Compare Mode */ - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P)); - /* Set the Output Compare Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); - - /* Set the Output State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); - - if(TIMx == TIM1) - { - assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - - /* Reset the Output N Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP)); - /* Set the Output N Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); - /* Reset the Output N State */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE)); - - /* Set the Output N State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); - /* Reset the Ouput Compare and Output Compare N IDLE State */ - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3)); - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N)); - /* Set the Output Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); - /* Set the Output N Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel4 according to the specified - * parameters in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure - * that contains the configuration information for the specified TIM - * peripheral. - * @retval None - */ -void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - /* Disable the Channel 2: Reset the CC4E Bit */ - TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E)); - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S)); - - /* Select the Output Compare Mode */ - tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P)); - /* Set the Output Compare Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); - - /* Set the Output State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); - - if(TIMx == TIM1) - { - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - /* Reset the Ouput Compare IDLE State */ - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4)); - /* Set the Output Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Fills each TIM_OCInitStruct member with its default value. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure which will - * be initialized. - * @retval None - */ -void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - /* Set the default configuration */ - TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; - TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; - TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; - TIM_OCInitStruct->TIM_Pulse = 0x0000000; - TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; - TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; - TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; - TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; -} - -/** - * @brief Selects the TIM Output Compare Mode. - * @note This function disables the selected channel before changing the Output - * Compare Mode. - * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions. - * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_Channel: specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @arg TIM_Channel_4: TIM Channel 4 - * @param TIM_OCMode: specifies the TIM Output Compare Mode. - * This parameter can be one of the following values: - * @arg TIM_OCMode_Timing - * @arg TIM_OCMode_Active - * @arg TIM_OCMode_Toggle - * @arg TIM_OCMode_PWM1 - * @arg TIM_OCMode_PWM2 - * @arg TIM_ForcedAction_Active - * @arg TIM_ForcedAction_InActive - * @retval None - */ -void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) -{ - uint32_t tmp = 0; - uint16_t tmp1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OCM(TIM_OCMode)); - - tmp = (uint32_t) TIMx; - tmp += CCMR_OFFSET; - - tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel; - - /* Disable the Channel: Reset the CCxE Bit */ - TIMx->CCER &= (uint16_t) ~tmp1; - - if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3)) - { - tmp += (TIM_Channel>>1); - - /* Reset the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M); - - /* Configure the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp |= TIM_OCMode; - } - else - { - tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1; - - /* Reset the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M); - - /* Configure the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8); - } -} - -/** - * @brief Sets the TIMx Capture Compare1 Register value - * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param Compare1: specifies the Capture Compare1 register new value. - * @retval None - */ -void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - - /* Set the Capture Compare1 Register value */ - TIMx->CCR1 = Compare1; -} - -/** - * @brief Sets the TIMx Capture Compare2 Register value - * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param Compare2: specifies the Capture Compare2 register new value. - * @retval None - */ -void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - - /* Set the Capture Compare2 Register value */ - TIMx->CCR2 = Compare2; -} - -/** - * @brief Sets the TIMx Capture Compare3 Register value - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @param Compare3: specifies the Capture Compare3 register new value. - * @retval None - */ -void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - - /* Set the Capture Compare3 Register value */ - TIMx->CCR3 = Compare3; -} - -/** - * @brief Sets the TIMx Capture Compare4 Register value - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param Compare4: specifies the Capture Compare4 register new value. - * @retval None - */ -void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - - /* Set the Capture Compare4 Register value */ - TIMx->CCR4 = Compare4; -} - -/** - * @brief Forces the TIMx output 1 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC1REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF. - * @retval None - */ -void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC1M Bits */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M); - /* Configure The Forced output Mode */ - tmpccmr1 |= TIM_ForcedAction; - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Forces the TIMx output 2 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC2REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF. - * @retval None - */ -void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC2M Bits */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M); - /* Configure The Forced output Mode */ - tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Forces the TIMx output 3 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC3REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF. - * @retval None - */ -void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC1M Bits */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M); - /* Configure The Forced output Mode */ - tmpccmr2 |= TIM_ForcedAction; - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Forces the TIMx output 4 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC4REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF. - * @retval None - */ -void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr2 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC2M Bits */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M); - /* Configure The Forced output Mode */ - tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit. - * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIMx peripheral - * @note TIM2 is not applicable for STM32F030 devices. - * @param NewState: new state of the Capture Compare Preload Control bit - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the CCPC Bit */ - TIMx->CR2 |= TIM_CR2_CCPC; - } - else - { - /* Reset the CCPC Bit */ - TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC); - } -} - - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR1. - * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 and 17 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC1PE Bit */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE); - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr1 |= TIM_OCPreload; - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR2. - * @param TIMx: where x can be 1, 2, 3 and 15 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC2PE Bit */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE); - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR3. - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC3PE Bit */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE); - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr2 |= TIM_OCPreload; - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR4. - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC4PE Bit */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE); - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx Output Compare 1 Fast feature. - * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC1FE Bit */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE); - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr1 |= TIM_OCFast; - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Configures the TIMx Output Compare 2 Fast feature. - * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC2FE Bit */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE); - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Configures the TIMx Output Compare 3 Fast feature. - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - - /* Get the TIMx CCMR2 register value */ - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC3FE Bit */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE); - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr2 |= TIM_OCFast; - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx Output Compare 4 Fast feature. - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - - /* Get the TIMx CCMR2 register value */ - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC4FE Bit */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE); - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Clears or safeguards the OCREF1 signal on an external event - * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC1CE Bit */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE); - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr1 |= TIM_OCClear; - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Clears or safeguards the OCREF2 signal on an external event - * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC2CE Bit */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE); - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Clears or safeguards the OCREF3 signal on an external event - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC3CE Bit */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE); - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr2 |= TIM_OCClear; - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Clears or safeguards the OCREF4 signal on an external event - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC4CE Bit */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE); - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx channel 1 polarity. - * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_OCPolarity: specifies the OC1 Polarity - * This parmeter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - /* Set or Reset the CC1P Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P); - tmpccer |= TIM_OCPolarity; - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx Channel 1N polarity. - * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_OCNPolarity: specifies the OC1N Polarity - * This parmeter can be one of the following values: - * @arg TIM_OCNPolarity_High: Output Compare active high - * @arg TIM_OCNPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); - - tmpccer = TIMx->CCER; - /* Set or Reset the CC1NP Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP); - tmpccer |= TIM_OCNPolarity; - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 2 polarity. - * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_OCPolarity: specifies the OC2 Polarity - * This parmeter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - /* Set or Reset the CC2P Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 4); - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx Channel 2N polarity. - * @param TIMx: where x can be 1 to select the TIM peripheral. - * @param TIM_OCNPolarity: specifies the OC2N Polarity - * This parmeter can be one of the following values: - * @arg TIM_OCNPolarity_High: Output Compare active high - * @arg TIM_OCNPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); - - tmpccer = TIMx->CCER; - /* Set or Reset the CC2NP Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP); - tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 3 polarity. - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_OCPolarity: specifies the OC3 Polarity - * This parmeter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - /* Set or Reset the CC3P Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 8); - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx Channel 3N polarity. - * @param TIMx: where x can be 1 to select the TIM peripheral. - * @param TIM_OCNPolarity: specifies the OC3N Polarity - * This parmeter can be one of the following values: - * @arg TIM_OCNPolarity_High: Output Compare active high - * @arg TIM_OCNPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); - - tmpccer = TIMx->CCER; - /* Set or Reset the CC3NP Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP); - tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 4 polarity. - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_OCPolarity: specifies the OC4 Polarity - * This parmeter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - /* Set or Reset the CC4P Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 12); - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Selects the OCReference Clear source. - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_OCReferenceClear: specifies the OCReference Clear source. - * This parameter can be one of the following values: - * @arg TIM_OCReferenceClear_ETRF: The internal OCreference clear input is connected to ETRF. - * @arg TIM_OCReferenceClear_OCREFCLR: The internal OCreference clear input is connected to OCREF_CLR input. - * @retval None - */ -void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(TIM_OCREFERENCECECLEAR_SOURCE(TIM_OCReferenceClear)); - - /* Set the TIM_OCReferenceClear source */ - TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_OCCS); - TIMx->SMCR |= TIM_OCReferenceClear; -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel x. - * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_Channel: specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @arg TIM_Channel_4: TIM Channel 4 - * @param TIM_CCx: specifies the TIM Channel CCxE bit new state. - * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. - * @retval None - */ -void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) -{ - uint16_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_CCX(TIM_CCx)); - - tmp = CCER_CCE_SET << TIM_Channel; - - /* Reset the CCxE Bit */ - TIMx->CCER &= (uint16_t)~ tmp; - - /* Set or reset the CCxE Bit */ - TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel xN. - * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_Channel: specifies the TIM Channel - * This parmeter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state. - * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. - * @retval None - */ -void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) -{ - uint16_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel)); - assert_param(IS_TIM_CCXN(TIM_CCxN)); - - tmp = CCER_CCNE_SET << TIM_Channel; - - /* Reset the CCxNE Bit */ - TIMx->CCER &= (uint16_t) ~tmp; - - /* Set or reset the CCxNE Bit */ - TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); -} - -/** - * @brief Selects the TIM peripheral Commutation event. - * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIMx peripheral - * @param NewState: new state of the Commutation event. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the COM Bit */ - TIMx->CR2 |= TIM_CR2_CCUS; - } - else - { - /* Reset the COM Bit */ - TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS); - } -} - -/** - * @} - */ - -/** @defgroup TIM_Group4 Input Capture management functions - * @brief Input Capture management functions - * -@verbatim - =============================================================================== - ##### Input Capture management functions ##### - =============================================================================== - - *** TIM Driver: how to use it in Input Capture Mode *** - =============================================================================== - [..] To use the Timer in Input Capture mode, the following steps are mandatory: - (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) - function. - (#) Configure the TIM pins by configuring the corresponding GPIO pins. - (#) Configure the Time base unit as described in the first part of this - driver, if needed, else the Timer will run with the default configuration: - (++) Autoreload value = 0xFFFF. - (++) Prescaler value = 0x0000. - (++) Counter mode = Up counting. - (++) Clock Division = TIM_CKD_DIV1. - (#) Fill the TIM_ICInitStruct with the desired parameters including: - (++) TIM Channel: TIM_Channel. - (++) TIM Input Capture polarity: TIM_ICPolarity. - (++) TIM Input Capture selection: TIM_ICSelection. - (++) TIM Input Capture Prescaler: TIM_ICPrescaler. - (++) TIM Input CApture filter value: TIM_ICFilter. - (#) Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired - channel with the corresponding configuration and to measure only - frequency or duty cycle of the input signal,or, Call - TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired - channels with the corresponding configuration and to measure the - frequency and the duty cycle of the input signal. - (#) Enable the NVIC or the DMA to read the measured frequency. - (#) Enable the corresponding interrupt (or DMA request) to read - the Captured value, using the function TIM_ITConfig(TIMx, TIM_IT_CCx) - (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)). - (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. - (#) Use TIM_GetCapturex(TIMx); to read the captured value. - [..] - (@) All other functions can be used separately to modify, if needed, - a specific feature of the Timer. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the TIM peripheral according to the specified - * parameters in the TIM_ICInitStruct. - * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure - * that contains the configuration information for the specified TIM - * peripheral. - * @retval None - */ -void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel)); - assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler)); - assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter)); - assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); - - if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - /* TI1 Configuration */ - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) - { - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - /* TI2 Configuration */ - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) - { - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - /* TI3 Configuration */ - TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - /* TI4 Configuration */ - TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/** - * @brief Fills each TIM_ICInitStruct member with its default value. - * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will - * be initialized. - * @retval None - */ -void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - /* Set the default configuration */ - TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; - TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; - TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; - TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; - TIM_ICInitStruct->TIM_ICFilter = 0x00; -} - -/** - * @brief Configures the TIM peripheral according to the specified - * parameters in the TIM_ICInitStruct to measure an external PWM signal. - * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure - * that contains the configuration information for the specified TIM - * peripheral. - * @retval None - */ -void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - uint16_t icoppositepolarity = TIM_ICPolarity_Rising; - uint16_t icoppositeselection = TIM_ICSelection_DirectTI; - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - /* Select the Opposite Input Polarity */ - if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) - { - icoppositepolarity = TIM_ICPolarity_Falling; - } - else - { - icoppositepolarity = TIM_ICPolarity_Rising; - } - /* Select the Opposite Input */ - if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) - { - icoppositeselection = TIM_ICSelection_IndirectTI; - } - else - { - icoppositeselection = TIM_ICSelection_DirectTI; - } - if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - /* TI1 Configuration */ - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - /* TI2 Configuration */ - TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - /* TI2 Configuration */ - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - /* TI1 Configuration */ - TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/** - * @brief Gets the TIMx Input Capture 1 value. - * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @retval Capture Compare 1 Register value. - */ -uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - - /* Get the Capture 1 Register value */ - return TIMx->CCR1; -} - -/** - * @brief Gets the TIMx Input Capture 2 value. - * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. - * @retval Capture Compare 2 Register value. - */ -uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - - /* Get the Capture 2 Register value */ - return TIMx->CCR2; -} - -/** - * @brief Gets the TIMx Input Capture 3 value. - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @retval Capture Compare 3 Register value. - */ -uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - - /* Get the Capture 3 Register value */ - return TIMx->CCR3; -} - -/** - * @brief Gets the TIMx Input Capture 4 value. - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @retval Capture Compare 4 Register value. - */ -uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - - /* Get the Capture 4 Register value */ - return TIMx->CCR4; -} - -/** - * @brief Sets the TIMx Input Capture 1 prescaler. - * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - - /* Reset the IC1PSC Bits */ - TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC); - /* Set the IC1PSC value */ - TIMx->CCMR1 |= TIM_ICPSC; -} - -/** - * @brief Sets the TIMx Input Capture 2 prescaler. - * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - - /* Reset the IC2PSC Bits */ - TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC); - /* Set the IC2PSC value */ - TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8); -} - -/** - * @brief Sets the TIMx Input Capture 3 prescaler. - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - - /* Reset the IC3PSC Bits */ - TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC); - /* Set the IC3PSC value */ - TIMx->CCMR2 |= TIM_ICPSC; -} - -/** - * @brief Sets the TIMx Input Capture 4 prescaler. - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - - /* Reset the IC4PSC Bits */ - TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC); - /* Set the IC4PSC value */ - TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8); -} - -/** - * @} - */ - -/** @defgroup TIM_Group5 Interrupts DMA and flags management functions - * @brief Interrupts, DMA and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts, DMA and flags management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified TIM interrupts. - * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the TIMx peripheral. - * @note TIM7 is applicable only for STM32F072 devices - * @note TIM6 is not applivable for STM32F031 devices. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg TIM_IT_Update: TIM update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_COM: TIM Commutation Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @arg TIM_IT_Break: TIM Break Interrupt source - * - * @note TIM6 and TIM7 can only generate an update interrupt. - * @note TIM15 can have only TIM_IT_Update, TIM_IT_CC1,TIM_IT_CC2 or TIM_IT_Trigger. - * @note TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. - * @note TIM_IT_Break is used only with TIM1 and TIM15. - * @note TIM_IT_COM is used only with TIM1, TIM15, TIM16 and TIM17. - * - * @param NewState: new state of the TIM interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_IT(TIM_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Interrupt sources */ - TIMx->DIER |= TIM_IT; - } - else - { - /* Disable the Interrupt sources */ - TIMx->DIER &= (uint16_t)~TIM_IT; - } -} - -/** - * @brief Configures the TIMx event to be generate by software. - * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the - * TIM peripheral. - * @note TIM7 is applicable only for STM32F072 devices - * @note TIM6 is not applivable for STM32F031 devices. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_EventSource: specifies the event source. - * This parameter can be one or more of the following values: - * @arg TIM_EventSource_Update: Timer update Event source - * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source - * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source - * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source - * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source - * @arg TIM_EventSource_COM: Timer COM event source - * @arg TIM_EventSource_Trigger: Timer Trigger Event source - * @arg TIM_EventSource_Break: Timer Break event source - * - * @note TIM6 and TIM7 can only generate an update event. - * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1. - * - * @retval None - */ -void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); - /* Set the event sources */ - TIMx->EGR = TIM_EventSource; -} - -/** - * @brief Checks whether the specified TIM flag is set or not. - * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the TIM peripheral. - * @note TIM7 is applicable only for STM32F072 devices - * @note TIM6 is not applivable for STM32F031 devices. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg TIM_FLAG_Update: TIM update Flag - * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag - * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag - * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag - * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag - * @arg TIM_FLAG_COM: TIM Commutation Flag - * @arg TIM_FLAG_Trigger: TIM Trigger Flag - * @arg TIM_FLAG_Break: TIM Break Flag - * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag - * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag - * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag - * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag - * - * @note TIM6 and TIM7 can have only one update flag. - * @note TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1, TIM_FLAG_CC2 or TIM_FLAG_Trigger. - * @note TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. - * @note TIM_FLAG_Break is used only with TIM1 and TIM15. - * @note TIM_FLAG_COM is used only with TIM1 TIM15, TIM16 and TIM17. - * - * @retval The new state of TIM_FLAG (SET or RESET). - */ -FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) -{ - ITStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_GET_FLAG(TIM_FLAG)); - - if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the TIMx's pending flags. - * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the TIM peripheral. - * @note TIM7 is applicable only for STM32F072 devices - * @note TIM6 is not applivable for STM32F031 devices. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_FLAG: specifies the flag bit to clear. - * This parameter can be any combination of the following values: - * @arg TIM_FLAG_Update: TIM update Flag - * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag - * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag - * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag - * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag - * @arg TIM_FLAG_COM: TIM Commutation Flag - * @arg TIM_FLAG_Trigger: TIM Trigger Flag - * @arg TIM_FLAG_Break: TIM Break Flag - * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag - * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag - * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag - * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag - * - * @note TIM6 and TIM7 can have only one update flag. - * @note TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,TIM_FLAG_CC2 or - * TIM_FLAG_Trigger. - * @note TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. - * @note TIM_FLAG_Break is used only with TIM1 and TIM15. - * @note TIM_FLAG_COM is used only with TIM1, TIM15, TIM16 and TIM17. - * - * @retval None - */ -void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG)); - - /* Clear the flags */ - TIMx->SR = (uint16_t)~TIM_FLAG; -} - -/** - * @brief Checks whether the TIM interrupt has occurred or not. - * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the TIM peripheral. - * @note TIM7 is applicable only for STM32F072 devices - * @note TIM6 is not applivable for STM32F031 devices. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_IT: specifies the TIM interrupt source to check. - * This parameter can be one of the following values: - * @arg TIM_IT_Update: TIM update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_COM: TIM Commutation Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @arg TIM_IT_Break: TIM Break Interrupt source - * - * @note TIM6 and TIM7 can generate only an update interrupt. - * @note TIM15 can have only TIM_IT_Update, TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger. - * @note TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. - * @note TIM_IT_Break is used only with TIM1 and TIM15. - * @note TIM_IT_COM is used only with TIM1, TIM15, TIM16 and TIM17. - * - * @retval The new state of the TIM_IT(SET or RESET). - */ -ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itstatus = 0x0, itenable = 0x0; - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_GET_IT(TIM_IT)); - - itstatus = TIMx->SR & TIM_IT; - - itenable = TIMx->DIER & TIM_IT; - if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the TIMx's interrupt pending bits. - * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the TIM peripheral. - * @note TIM7 is applicable only for STM32F072 devices - * @note TIM6 is not applivable for STM32F031 devices. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_IT: specifies the pending bit to clear. - * This parameter can be any combination of the following values: - * @arg TIM_IT_Update: TIM1 update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_COM: TIM Commutation Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @arg TIM_IT_Break: TIM Break Interrupt source - * - * @note TIM6 and TIM7 can generate only an update interrupt. - * @note TIM15 can have only TIM_IT_Update, TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger. - * @note TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. - * @note TIM_IT_Break is used only with TIM1 and TIM15. - * @note TIM_IT_COM is used only with TIM1, TIM15, TIM16 and TIM17. - * - * @retval None - */ -void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_IT(TIM_IT)); - - /* Clear the IT pending Bit */ - TIMx->SR = (uint16_t)~TIM_IT; -} - -/** - * @brief Configures the TIMx's DMA interface. - * @param TIMx: where x can be 1, 2, 3, 15, 16 or 17 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_DMABase: DMA Base address. - * This parameter can be one of the following values: - * @arg TIM_DMABase_CR1 - * @arg TIM_DMABase_CR2 - * @arg TIM_DMABase_SMCR - * @arg TIM_DMABase_DIER - * @arg TIM_DMABase_SR - * @arg TIM_DMABase_EGR - * @arg TIM_DMABase_CCMR1 - * @arg TIM_DMABase_CCMR2 - * @arg TIM_DMABase_CCER - * @arg TIM_DMABase_CNT - * @arg TIM_DMABase_PSC - * @arg TIM_DMABase_ARR - * @arg TIM_DMABase_CCR1 - * @arg TIM_DMABase_CCR2 - * @arg TIM_DMABase_CCR3 - * @arg TIM_DMABase_CCR4 - * @arg TIM_DMABase_DCR - * @arg TIM_DMABase_OR - * @param TIM_DMABurstLength: DMA Burst length. This parameter can be one value - * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. - * @retval None - */ -void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); - assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength)); - /* Set the DMA Base and the DMA Burst Length */ - TIMx->DCR = TIM_DMABase | TIM_DMABurstLength; -} - -/** - * @brief Enables or disables the TIMx's DMA Requests. - * @param TIMx: where x can be 1, 2, 3, 6, 7, 15, 16 or 17 to select the TIM peripheral. - * @note TIM7 is applicable only for STM32F072 devices - * @note TIM6 is not applivable for STM32F031 devices. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_DMASource: specifies the DMA Request sources. - * This parameter can be any combination of the following values: - * @arg TIM_DMA_Update: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_COM: TIM Commutation DMA source - * @arg TIM_DMA_Trigger: TIM Trigger DMA source - * @param NewState: new state of the DMA Request sources. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST10_PERIPH(TIMx)); - assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DMA sources */ - TIMx->DIER |= TIM_DMASource; - } - else - { - /* Disable the DMA sources */ - TIMx->DIER &= (uint16_t)~TIM_DMASource; - } -} - -/** - * @brief Selects the TIMx peripheral Capture Compare DMA source. - * @param TIMx: where x can be 1, 2, 3, 15, 16 or 17 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param NewState: new state of the Capture Compare DMA source - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST5_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the CCDS Bit */ - TIMx->CR2 |= TIM_CR2_CCDS; - } - else - { - /* Reset the CCDS Bit */ - TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS); - } -} - -/** - * @} - */ - -/** @defgroup TIM_Group6 Clocks management functions - * @brief Clocks management functions - * -@verbatim - =============================================================================== - ##### Clocks management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the TIMx internal Clock - * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @retval None - */ -void TIM_InternalClockConfig(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - /* Disable slave mode to clock the prescaler directly with the internal clock */ - TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); -} - -/** - * @brief Configures the TIMx Internal Trigger as External Clock - * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_ITRSource: Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal Trigger 0 - * @arg TIM_TS_ITR1: Internal Trigger 1 - * @arg TIM_TS_ITR2: Internal Trigger 2 - * @arg TIM_TS_ITR3: Internal Trigger 3 - * @retval None - */ -void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); - /* Select the Internal Trigger */ - TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); - /* Select the External clock mode1 */ - TIMx->SMCR |= TIM_SlaveMode_External1; -} - -/** - * @brief Configures the TIMx Trigger as External Clock - * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_TIxExternalCLKSource: Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector - * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1 - * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2 - * @param TIM_ICPolarity: specifies the TIx Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param ICFilter: specifies the filter value. - * This parameter must be a value between 0x0 and 0xF. - * @retval None - */ -void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, - uint16_t TIM_ICPolarity, uint16_t ICFilter) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity)); - assert_param(IS_TIM_IC_FILTER(ICFilter)); - - /* Configure the Timer Input Clock Source */ - if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) - { - TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - else - { - TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - /* Select the Trigger source */ - TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); - /* Select the External clock mode1 */ - TIMx->SMCR |= TIM_SlaveMode_External1; -} - -/** - * @brief Configures the External clock Mode1 - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter) -{ - uint16_t tmpsmcr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - - /* Configure the ETR Clock source */ - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - /* Reset the SMS Bits */ - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); - /* Select the External clock mode1 */ - tmpsmcr |= TIM_SlaveMode_External1; - /* Select the Trigger selection : ETRF */ - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS)); - tmpsmcr |= TIM_TS_ETRF; - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Configures the External clock Mode2 - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - - /* Configure the ETR Clock source */ - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - /* Enable the External clock mode2 */ - TIMx->SMCR |= TIM_SMCR_ECE; -} - -/** - * @} - */ - -/** @defgroup TIM_Group7 Synchronization management functions - * @brief Synchronization management functions - * -@verbatim - =============================================================================== - ##### Synchronization management functions ##### - =============================================================================== - *** TIM Driver: how to use it in synchronization Mode *** - =============================================================================== - [..] Case of two/several Timers - (#) Configure the Master Timers using the following functions: - (++) void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, - uint16_t TIM_TRGOSource). - (++) void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, - uint16_t TIM_MasterSlaveMode); - (#) Configure the Slave Timers using the following functions: - (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, - uint16_t TIM_InputTriggerSource); - (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); - [..] Case of Timers and external trigger(ETR pin) - (#) Configure the Etrenal trigger using this function: - (++) void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); - (#) Configure the Slave Timers using the following functions: - (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, - uint16_t TIM_InputTriggerSource); - (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); - -@endverbatim - * @{ - */ -/** - * @brief Selects the Input Trigger source - * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_InputTriggerSource: The Input Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal Trigger 0 - * @arg TIM_TS_ITR1: Internal Trigger 1 - * @arg TIM_TS_ITR2: Internal Trigger 2 - * @arg TIM_TS_ITR3: Internal Trigger 3 - * @arg TIM_TS_TI1F_ED: TI1 Edge Detector - * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 - * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 - * @arg TIM_TS_ETRF: External Trigger input - * @retval None - */ -void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) -{ - uint16_t tmpsmcr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - /* Reset the TS Bits */ - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS)); - /* Set the Input Trigger source */ - tmpsmcr |= TIM_InputTriggerSource; - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Selects the TIMx Trigger Output Mode. - * @param TIMx: where x can be 1, 2, 3, 6, 7, or 15 to select the TIM peripheral. - * @note TIM7 is applicable only for STM32F072 devices - * @note TIM6 is not applivable for STM32F031 devices. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_TRGOSource: specifies the Trigger Output source. - * This parameter can be one of the following values: - * - * - For all TIMx - * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO). - * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO). - * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO). - * - * - For all TIMx except TIM6 and TIM7 - * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag - * is to be set, as soon as a capture or compare match occurs (TRGO). - * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO). - * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO). - * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO). - * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO). - * - * @retval None - */ -void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST9_PERIPH(TIMx)); - assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource)); - - /* Reset the MMS Bits */ - TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS); - /* Select the TRGO source */ - TIMx->CR2 |= TIM_TRGOSource; -} - -/** - * @brief Selects the TIMx Slave Mode. - * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_SlaveMode: specifies the Timer Slave Mode. - * This parameter can be one of the following values: - * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes - * the counter and triggers an update of the registers. - * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high. - * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI. - * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter. - * @retval None - */ -void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); - - /* Reset the SMS Bits */ - TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS); - /* Select the Slave Mode */ - TIMx->SMCR |= TIM_SlaveMode; -} - -/** - * @brief Sets or Resets the TIMx Master/Slave Mode. - * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode. - * This parameter can be one of the following values: - * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer - * and its slaves (through TRGO). - * @arg TIM_MasterSlaveMode_Disable: No action - * @retval None - */ -void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); - - /* Reset the MSM Bit */ - TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM); - - /* Set or Reset the MSM Bit */ - TIMx->SMCR |= TIM_MasterSlaveMode; -} - -/** - * @brief Configures the TIMx External Trigger (ETR). - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter) -{ - uint16_t tmpsmcr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - - tmpsmcr = TIMx->SMCR; - /* Reset the ETR Bits */ - tmpsmcr &= SMCR_ETR_MASK; - /* Set the Prescaler, the Filter value and the Polarity */ - tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @} - */ - -/** @defgroup TIM_Group8 Specific interface management functions - * @brief Specific interface management functions - * -@verbatim - =============================================================================== - ##### Specific interface management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the TIMx Encoder Interface. - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_EncoderMode: specifies the TIMx Encoder Mode. - * This parameter can be one of the following values: - * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level. - * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level. - * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending - * on the level of the other input. - * @param TIM_IC1Polarity: specifies the IC1 Polarity - * This parmeter can be one of the following values: - * @arg TIM_ICPolarity_Falling: IC Falling edge. - * @arg TIM_ICPolarity_Rising: IC Rising edge. - * @param TIM_IC2Polarity: specifies the IC2 Polarity - * This parmeter can be one of the following values: - * @arg TIM_ICPolarity_Falling: IC Falling edge. - * @arg TIM_ICPolarity_Rising: IC Rising edge. - * @retval None - */ -void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, - uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) -{ - uint16_t tmpsmcr = 0; - uint16_t tmpccmr1 = 0; - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); - assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); - assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Set the encoder Mode */ - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); - tmpsmcr |= TIM_EncoderMode; - /* Select the Capture Compare 1 and the Capture Compare 2 as input */ - tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S))); - tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; - /* Set the TI1 and the TI2 Polarities */ - tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP)) & (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP)); - tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Enables or disables the TIMx's Hall sensor interface. - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param NewState: new state of the TIMx Hall sensor interface. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the TI1S Bit */ - TIMx->CR2 |= TIM_CR2_TI1S; - } - else - { - /* Reset the TI1S Bit */ - TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S); - } -} - -/** - * @} - */ - -/** @defgroup TIM_Group9 Specific remapping management function - * @brief Specific remapping management function - * -@verbatim - =============================================================================== - ##### Specific remapping management function ##### - =============================================================================== - -@endverbatim - * @{ - */ -/** - * @brief Configures the TIM14 Remapping input Capabilities. - * @param TIMx: where x can be 14 to select the TIM peripheral. - * @param TIM_Remap: specifies the TIM input reampping source. - * This parameter can be one of the following values: - * @arg TIM14_GPIO: TIM14 Channel 1 is connected to GPIO. - * @arg TIM14_RTC_CLK: TIM14 Channel 1 is connected to RTC input clock. - * RTC input clock can be LSE, LSI or HSE/div128. - * @arg TIM14_HSE_DIV32: TIM14 Channel 1 is connected to HSE/32 clock. - * @arg TIM14_MCO: TIM14 Channel 1 is connected to MCO clock. - * MCO clock can be HSI14, SYSCLK, HSI, HSE or PLL/2. - * @retval None - */ -void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST11_PERIPH(TIMx)); - assert_param(IS_TIM_REMAP(TIM_Remap)); - - /* Set the Timer remapping configuration */ - TIMx->OR = TIM_Remap; -} - -/** - * @} - */ - -/** - * @brief Configure the TI1 as Input. - * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_ICPolarity: The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. - * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. - * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr1 = 0, tmpccer = 0; - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E); - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - /* Select the Input and set the filter */ - tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F))); - tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); - - /* Select the Polarity and set the CC1E Bit */ - tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI2 as Input. - * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_ICPolarity: The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. - * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. - * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E); - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 4); - /* Select the Input and set the filter */ - tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F))); - tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); - tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); - /* Select the Polarity and set the CC2E Bit */ - tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP)); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E); - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1 ; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI3 as Input. - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_ICPolarity: The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. - * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. - * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - /* Disable the Channel 3: Reset the CC3E Bit */ - TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E); - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 8); - /* Select the Input and set the filter */ - tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F))); - tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); - /* Select the Polarity and set the CC3E Bit */ - tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP)); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E); - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI4 as Input. - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @note TIM2 is not applicable for STM32F030 devices. - * @param TIM_ICPolarity: The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. - * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. - * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E); - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 12); - /* Select the Input and set the filter */ - tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F))); - tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); - tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); - /* Select the Polarity and set the CC4E Bit */ - tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P | TIM_CCER_CC4NP)); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E); - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_usart.c b/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_usart.c deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_usart.c +++ /dev/null @@ -1,2168 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_usart.c - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the Universal synchronous asynchronous receiver - * transmitter (USART): - * + Initialization and Configuration - * + STOP Mode - * + AutoBaudRate - * + Data transfers - * + Multi-Processor Communication - * + LIN mode - * + Half-duplex mode - * + Smartcard mode - * + IrDA mode - * + RS485 mode - * + DMA transfers management - * + Interrupts and flags management - * - * @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - (#) Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE) - function for USART1 or using RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE) - function for USART2 and USART3. - (#) According to the USART mode, enable the GPIO clocks using - RCC_AHBPeriphClockCmd() function. (The I/O can be TX, RX, CTS, - or and SCLK). - (#) Peripheral's alternate function: - (++) Connect the pin to the desired peripherals' Alternate - Function (AF) using GPIO_PinAFConfig() function. - (++) Configure the desired pin in alternate function by: - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF. - (++) Select the type, pull-up/pull-down and output speed via - GPIO_PuPd, GPIO_OType and GPIO_Speed members. - (++) Call GPIO_Init() function. - (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware - flow control and Mode(Receiver/Transmitter) using the SPI_Init() - function. - (#) For synchronous mode, enable the clock and program the polarity, - phase and last bit using the USART_ClockInit() function. - (#) Enable the NVIC and the corresponding interrupt using the function - USART_ITConfig() if you need to use interrupt mode. - (#) When using the DMA mode: - (++) Configure the DMA using DMA_Init() function. - (++) Active the needed channel Request using USART_DMACmd() function. - (#) Enable the USART using the USART_Cmd() function. - (#) Enable the DMA using the DMA_Cmd() function, when using DMA mode. - [..] - Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections - for more details. - -@endverbatim - - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_usart.h" -#include "stm32f0xx_rcc.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup USART - * @brief USART driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/*!< USART CR1 register clear Mask ((~(uint32_t)0xFFFFE6F3)) */ -#define CR1_CLEAR_MASK ((uint32_t)(USART_CR1_M | USART_CR1_PCE | \ - USART_CR1_PS | USART_CR1_TE | \ - USART_CR1_RE)) - -/*!< USART CR2 register clock bits clear Mask ((~(uint32_t)0xFFFFF0FF)) */ -#define CR2_CLOCK_CLEAR_MASK ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \ - USART_CR2_CPHA | USART_CR2_LBCL)) - -/*!< USART CR3 register clear Mask ((~(uint32_t)0xFFFFFCFF)) */ -#define CR3_CLEAR_MASK ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE)) - -/*!< USART Interrupts mask */ -#define IT_MASK ((uint32_t)0x000000FF) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup USART_Private_Functions - * @{ - */ - -/** @defgroup USART_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to initialize the USART - in asynchronous and in synchronous modes. - (+) For the asynchronous mode only these parameters can be configured: - (++) Baud Rate. - (++) Word Length. - (++) Stop Bit. - (++) Parity: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - Depending on the frame length defined by the M bit (8-bits or 9-bits), - the possible USART frame formats are as listed in the following table: - - +-------------------------------------------------------------+ - | M bit | PCE bit | USART frame | - |---------------------|---------------------------------------| - | 0 | 0 | | SB | 8 bit data | STB | | - |---------|-----------|---------------------------------------| - | 0 | 1 | | SB | 7 bit data | PB | STB | | - |---------|-----------|---------------------------------------| - | 1 | 0 | | SB | 9 bit data | STB | | - |---------|-----------|---------------------------------------| - | 1 | 1 | | SB | 8 bit data | PB | STB | | - +-------------------------------------------------------------+ - - (++) Hardware flow control. - (++) Receiver/transmitter modes. - [..] The USART_Init() function follows the USART asynchronous configuration - procedure(details for the procedure are available in reference manual. - (+) For the synchronous mode in addition to the asynchronous mode parameters - these parameters should be also configured: - (++) USART Clock Enabled. - (++) USART polarity. - (++) USART phase. - (++) USART LastBit. - [..] These parameters can be configured using the USART_ClockInit() function. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the USARTx peripheral registers to their default reset values. - * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. - * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. - * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. - * @note USART2 is not available for STM32F031 devices. - * @retval None - */ -void USART_DeInit(USART_TypeDef* USARTx) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - if (USARTx == USART1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); - } - else if (USARTx == USART2) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); - } - else if (USARTx == USART3) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); - } - else if (USARTx == USART4) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART4, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART4, DISABLE); - } - else if (USARTx == USART5) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART5, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART5, DISABLE); - } - else if (USARTx == USART6) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, DISABLE); - } - else if (USARTx == USART7) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART7, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART7, DISABLE); - } - else - { - if (USARTx == USART8) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART8, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART8, DISABLE); - } - } -} - -/** - * @brief Initializes the USARTx peripheral according to the specified - * parameters in the USART_InitStruct . - * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. - * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. - * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. - * @note USART2 is not available for STM32F031 devices. - * @param USART_InitStruct: pointer to a USART_InitTypeDef structure that contains - * the configuration information for the specified USART peripheral. - * @retval None - */ -void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) -{ - uint32_t divider = 0, apbclock = 0, tmpreg = 0; - RCC_ClocksTypeDef RCC_ClocksStatus; - - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); - assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength)); - assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits)); - assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity)); - assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode)); - assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl)); - - /* Disable USART */ - USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_UE); - - /*---------------------------- USART CR2 Configuration -----------------------*/ - tmpreg = USARTx->CR2; - /* Clear STOP[13:12] bits */ - tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP); - - /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/ - /* Set STOP[13:12] bits according to USART_StopBits value */ - tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; - - /* Write to USART CR2 */ - USARTx->CR2 = tmpreg; - - /*---------------------------- USART CR1 Configuration -----------------------*/ - tmpreg = USARTx->CR1; - /* Clear M, PCE, PS, TE and RE bits */ - tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK); - - /* Configure the USART Word Length, Parity and mode ----------------------- */ - /* Set the M bits according to USART_WordLength value */ - /* Set PCE and PS bits according to USART_Parity value */ - /* Set TE and RE bits according to USART_Mode value */ - tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | - USART_InitStruct->USART_Mode; - - /* Write to USART CR1 */ - USARTx->CR1 = tmpreg; - - /*---------------------------- USART CR3 Configuration -----------------------*/ - tmpreg = USARTx->CR3; - /* Clear CTSE and RTSE bits */ - tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK); - - /* Configure the USART HFC -------------------------------------------------*/ - /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */ - tmpreg |= USART_InitStruct->USART_HardwareFlowControl; - - /* Write to USART CR3 */ - USARTx->CR3 = tmpreg; - - /*---------------------------- USART BRR Configuration -----------------------*/ - /* Configure the USART Baud Rate -------------------------------------------*/ - RCC_GetClocksFreq(&RCC_ClocksStatus); - - if (USARTx == USART1) - { - apbclock = RCC_ClocksStatus.USART1CLK_Frequency; - } - else if (USARTx == USART2) - { - apbclock = RCC_ClocksStatus.USART2CLK_Frequency; - } - else if (USARTx == USART3) - { - apbclock = RCC_ClocksStatus.USART3CLK_Frequency; - } - else - { - apbclock = RCC_ClocksStatus.PCLK_Frequency; - } - - /* Determine the integer part */ - if ((USARTx->CR1 & USART_CR1_OVER8) != 0) - { - /* (divider * 10) computing in case Oversampling mode is 8 Samples */ - divider = (uint32_t)((2 * apbclock) / (USART_InitStruct->USART_BaudRate)); - tmpreg = (uint32_t)((2 * apbclock) % (USART_InitStruct->USART_BaudRate)); - } - else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */ - { - /* (divider * 10) computing in case Oversampling mode is 16 Samples */ - divider = (uint32_t)((apbclock) / (USART_InitStruct->USART_BaudRate)); - tmpreg = (uint32_t)((apbclock) % (USART_InitStruct->USART_BaudRate)); - } - - /* round the divider : if fractional part i greater than 0.5 increment divider */ - if (tmpreg >= (USART_InitStruct->USART_BaudRate) / 2) - { - divider++; - } - - /* Implement the divider in case Oversampling mode is 8 Samples */ - if ((USARTx->CR1 & USART_CR1_OVER8) != 0) - { - /* get the LSB of divider and shift it to the right by 1 bit */ - tmpreg = (divider & (uint16_t)0x000F) >> 1; - - /* update the divider value */ - divider = (divider & (uint16_t)0xFFF0) | tmpreg; - } - - /* Write to USART BRR */ - USARTx->BRR = (uint16_t)divider; -} - -/** - * @brief Fills each USART_InitStruct member with its default value. - * @param USART_InitStruct: pointer to a USART_InitTypeDef structure - * which will be initialized. - * @retval None - */ -void USART_StructInit(USART_InitTypeDef* USART_InitStruct) -{ - /* USART_InitStruct members default value */ - USART_InitStruct->USART_BaudRate = 9600; - USART_InitStruct->USART_WordLength = USART_WordLength_8b; - USART_InitStruct->USART_StopBits = USART_StopBits_1; - USART_InitStruct->USART_Parity = USART_Parity_No ; - USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; - USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; -} - -/** - * @brief Initializes the USARTx peripheral Clock according to the - * specified parameters in the USART_ClockInitStruct. - * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. - * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. - * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. - * @note USART2 is not available for STM32F031 devices. - * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef - * structure that contains the configuration information for the specified - * USART peripheral. - * @retval None - */ -void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock)); - assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL)); - assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA)); - assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit)); -/*---------------------------- USART CR2 Configuration -----------------------*/ - tmpreg = USARTx->CR2; - /* Clear CLKEN, CPOL, CPHA, LBCL and SSM bits */ - tmpreg &= (uint32_t)~((uint32_t)CR2_CLOCK_CLEAR_MASK); - /* Configure the USART Clock, CPOL, CPHA, LastBit and SSM ------------*/ - /* Set CLKEN bit according to USART_Clock value */ - /* Set CPOL bit according to USART_CPOL value */ - /* Set CPHA bit according to USART_CPHA value */ - /* Set LBCL bit according to USART_LastBit value */ - tmpreg |= (uint32_t)(USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | - USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit); - /* Write to USART CR2 */ - USARTx->CR2 = tmpreg; -} - -/** - * @brief Fills each USART_ClockInitStruct member with its default value. - * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef - * structure which will be initialized. - * @retval None - */ -void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct) -{ - /* USART_ClockInitStruct members default value */ - USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; - USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; - USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; - USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; -} - -/** - * @brief Enables or disables the specified USART peripheral. - * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. - * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. - * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. - * @note USART2 is not available for STM32F031 devices. - * @param NewState: new state of the USARTx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected USART by setting the UE bit in the CR1 register */ - USARTx->CR1 |= USART_CR1_UE; - } - else - { - /* Disable the selected USART by clearing the UE bit in the CR1 register */ - USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_UE); - } -} - -/** - * @brief Enables or disables the USART's transmitter or receiver. - * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. - * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. - * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. - * @note USART2 is not available for STM32F031 devices. - * @param USART_Direction: specifies the USART direction. - * This parameter can be any combination of the following values: - * @arg USART_Mode_Tx: USART Transmitter - * @arg USART_Mode_Rx: USART Receiver - * @param NewState: new state of the USART transfer direction. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_DirectionModeCmd(USART_TypeDef* USARTx, uint32_t USART_DirectionMode, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_MODE(USART_DirectionMode)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the USART's transfer interface by setting the TE and/or RE bits - in the USART CR1 register */ - USARTx->CR1 |= USART_DirectionMode; - } - else - { - /* Disable the USART's transfer interface by clearing the TE and/or RE bits - in the USART CR3 register */ - USARTx->CR1 &= (uint32_t)~USART_DirectionMode; - } -} - -/** - * @brief Enables or disables the USART's 8x oversampling mode. - * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. - * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. - * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. - * @note USART2 is not available for STM32F031 devices. - * @param NewState: new state of the USART 8x oversampling mode. - * This parameter can be: ENABLE or DISABLE. - * @note This function has to be called before calling USART_Init() function - * in order to have correct baudrate Divider value. - * @retval None - */ -void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */ - USARTx->CR1 |= USART_CR1_OVER8; - } - else - { - /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */ - USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_OVER8); - } -} - -/** - * @brief Enables or disables the USART's one bit sampling method. - * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. - * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. - * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. - * @note USART2 is not available for STM32F031 devices. - * @param NewState: new state of the USART one bit sampling method. - * This parameter can be: ENABLE or DISABLE. - * @note This function has to be called before calling USART_Cmd() function. - * @retval None - */ -void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_ONEBIT; - } - else - { - /* Disable the one bit method by clearing the ONEBITE bit in the CR3 register */ - USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT); - } -} - -/** - * @brief Enables or disables the USART's most significant bit first - * transmitted/received following the start bit. - * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. - * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. - * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. - * @note USART2 is not available for STM32F031 devices. - * @param NewState: new state of the USART most significant bit first - * transmitted/received following the start bit. - * This parameter can be: ENABLE or DISABLE. - * @note This function has to be called before calling USART_Cmd() function. - * @retval None - */ -void USART_MSBFirstCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the most significant bit first transmitted/received following the - start bit by setting the MSBFIRST bit in the CR2 register */ - USARTx->CR2 |= USART_CR2_MSBFIRST; - } - else - { - /* Disable the most significant bit first transmitted/received following the - start bit by clearing the MSBFIRST bit in the CR2 register */ - USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_MSBFIRST); - } -} - -/** - * @brief Enables or disables the binary data inversion. - * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. - * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. - * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. - * @note USART2 is not available for STM32F031 devices. - * @param NewState: new defined levels for the USART data. - * This parameter can be: - * @arg ENABLE: Logical data from the data register are send/received in negative - * logic (1=L, 0=H). The parity bit is also inverted. - * @arg DISABLE: Logical data from the data register are send/received in positive - * logic (1=H, 0=L) - * @note This function has to be called before calling USART_Cmd() function. - * @retval None - */ -void USART_DataInvCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the binary data inversion feature by setting the DATAINV bit in - the CR2 register */ - USARTx->CR2 |= USART_CR2_DATAINV; - } - else - { - /* Disable the binary data inversion feature by clearing the DATAINV bit in - the CR2 register */ - USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_DATAINV); - } -} - -/** - * @brief Enables or disables the Pin(s) active level inversion. - * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. - * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. - * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. - * @note USART2 is not available for STM32F031 devices. - * @param USART_InvPin: specifies the USART pin(s) to invert. - * This parameter can be any combination of the following values: - * @arg USART_InvPin_Tx: USART Tx pin active level inversion. - * @arg USART_InvPin_Rx: USART Rx pin active level inversion. - * @param NewState: new active level status for the USART pin(s). - * This parameter can be: - * @arg ENABLE: pin(s) signal values are inverted (Vdd =0, Gnd =1). - * @arg DISABLE: pin(s) signal works using the standard logic levels (Vdd =1, Gnd =0). - * @note This function has to be called before calling USART_Cmd() function. - * @retval None - */ -void USART_InvPinCmd(USART_TypeDef* USARTx, uint32_t USART_InvPin, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_INVERSTION_PIN(USART_InvPin)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the active level inversion for selected pins by setting the TXINV - and/or RXINV bits in the USART CR2 register */ - USARTx->CR2 |= USART_InvPin; - } - else - { - /* Disable the active level inversion for selected requests by clearing the - TXINV and/or RXINV bits in the USART CR2 register */ - USARTx->CR2 &= (uint32_t)~USART_InvPin; - } -} - -/** - * @brief Enables or disables the swap Tx/Rx pins. - * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. - * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. - * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. - * @note USART2 is not available for STM32F031 devices. - * @param NewState: new state of the USARTx TX/RX pins pinout. - * This parameter can be: - * @arg ENABLE: The TX and RX pins functions are swapped. - * @arg DISABLE: TX/RX pins are used as defined in standard pinout - * @note This function has to be called before calling USART_Cmd() function. - * @retval None - */ -void USART_SWAPPinCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the SWAP feature by setting the SWAP bit in the CR2 register */ - USARTx->CR2 |= USART_CR2_SWAP; - } - else - { - /* Disable the SWAP feature by clearing the SWAP bit in the CR2 register */ - USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_SWAP); - } -} - -/** - * @brief Enables or disables the receiver Time Out feature. - * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. - * @note USART2 is available only for STM32F072 and STM32F091 devices. - * @note USART3 is available only for STM32F091 devices. - * @param NewState: new state of the USARTx receiver Time Out. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_ReceiverTimeOutCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the receiver time out feature by setting the RTOEN bit in the CR2 - register */ - USARTx->CR2 |= USART_CR2_RTOEN; - } - else - { - /* Disable the receiver time out feature by clearing the RTOEN bit in the CR2 - register */ - USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_RTOEN); - } -} - -/** - * @brief Sets the receiver Time Out value. - * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. - * @note USART2 is available only for STM32F072 and STM32F091 devices. - * @note USART3 is available only for STM32F091 devices. - * @param USART_ReceiverTimeOut: specifies the Receiver Time Out value. - * @retval None - */ -void USART_SetReceiverTimeOut(USART_TypeDef* USARTx, uint32_t USART_ReceiverTimeOut) -{ - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - assert_param(IS_USART_TIMEOUT(USART_ReceiverTimeOut)); - - /* Clear the receiver Time Out value by clearing the RTO[23:0] bits in the RTOR - register */ - USARTx->RTOR &= (uint32_t)~((uint32_t)USART_RTOR_RTO); - /* Set the receiver Time Out value by setting the RTO[23:0] bits in the RTOR - register */ - USARTx->RTOR |= USART_ReceiverTimeOut; -} - -/** - * @brief Sets the system clock prescaler. - * @note This function is not available for STM32F030 devices. - * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. - * @note USART2 is available only for STM32F072 and STM32F091 devices. - * @note USART3 is available only for STM32F091 devices. - * @param USART_Prescaler: specifies the prescaler clock. - * @note This function has to be called before calling USART_Cmd() function. - * @retval None - */ -void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler) -{ - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - - /* Clear the USART prescaler */ - USARTx->GTPR &= USART_GTPR_GT; - /* Set the USART prescaler */ - USARTx->GTPR |= USART_Prescaler; -} - -/** - * @} - */ - - -/** @defgroup USART_Group2 STOP Mode functions - * @brief STOP Mode functions - * -@verbatim - =============================================================================== - ##### STOP Mode functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to manage - WakeUp from STOP mode. - - [..] The USART is able to WakeUp from Stop Mode if USART clock is set to HSI - or LSI. - - [..] The WakeUp source is configured by calling USART_StopModeWakeUpSourceConfig() - function. - - [..] After configuring the source of WakeUp and before entering in Stop Mode - USART_STOPModeCmd() function should be called to allow USART WakeUp. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified USART peripheral in STOP Mode. - * @param USARTx: where x can be 1 or 2 or 3 to select the USART peripheral. - * @note USART2 is available only for STM32F072 and STM32F091 devices. - * @note USART3 is available only for STM32F091 devices. - * @param NewState: new state of the USARTx peripheral state in stop mode. - * This parameter can be: ENABLE or DISABLE. - * @note This function has to be called when USART clock is set to HSI or LSE. - * @retval None - */ -void USART_STOPModeCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected USART in STOP mode by setting the UESM bit in the CR1 - register */ - USARTx->CR1 |= USART_CR1_UESM; - } - else - { - /* Disable the selected USART in STOP mode by clearing the UE bit in the CR1 - register */ - USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_UESM); - } -} - -/** - * @brief Selects the USART WakeUp method form stop mode. - * @note This function is not available for STM32F030 devices. - * @param USARTx: where x can be 1 or 2 or 3 to select the USART peripheral. - * @note USART2 is available only for STM32F072 and STM32F091 devices. - * @note USART3 is available only for STM32F091 devices. - * @param USART_WakeUp: specifies the selected USART wakeup method. - * This parameter can be one of the following values: - * @arg USART_WakeUpSource_AddressMatch: WUF active on address match. - * @arg USART_WakeUpSource_StartBit: WUF active on Start bit detection. - * @arg USART_WakeUpSource_RXNE: WUF active on RXNE. - * @note This function has to be called before calling USART_Cmd() function. - * @retval None - */ -void USART_StopModeWakeUpSourceConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUpSource) -{ - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - assert_param(IS_USART_STOPMODE_WAKEUPSOURCE(USART_WakeUpSource)); - - USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_WUS); - USARTx->CR3 |= USART_WakeUpSource; -} - -/** - * @} - */ - - -/** @defgroup USART_Group3 AutoBaudRate functions - * @brief AutoBaudRate functions - * -@verbatim - =============================================================================== - ##### AutoBaudRate functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to manage - the AutoBaudRate detections. - - [..] Before Enabling AutoBaudRate detection using USART_AutoBaudRateCmd () - The character patterns used to calculate baudrate must be chosen by calling - USART_AutoBaudRateConfig() function. These function take as parameter : - (#)USART_AutoBaudRate_StartBit : any character starting with a bit 1. - (#)USART_AutoBaudRate_FallingEdge : any character starting with a 10xx bit pattern. - - [..] At any later time, another request for AutoBaudRate detection can be performed - using USART_RequestCmd() function. - - [..] The AutoBaudRate detection is monitored by the status of ABRF flag which indicate - that the AutoBaudRate detection is completed. In addition to ABRF flag, the ABRE flag - indicate that this procedure is completed without success. USART_GetFlagStatus () - function should be used to monitor the status of these flags. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the Auto Baud Rate. - * @param USARTx: where x can be 1or 2 to select the USART peripheral. - * @note USART2 is available only for STM32F072 and STM32F091 devices. - * @note USART3 is available only for STM32F091 devices. - * @param NewState: new state of the USARTx auto baud rate. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_AutoBaudRateCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the auto baud rate feature by setting the ABREN bit in the CR2 - register */ - USARTx->CR2 |= USART_CR2_ABREN; - } - else - { - /* Disable the auto baud rate feature by clearing the ABREN bit in the CR2 - register */ - USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ABREN); - } -} - -/** - * @brief Selects the USART auto baud rate method. - * @param USARTx: where x can be 1or 2 to select the USART peripheral. - * @note USART2 is available only for STM32F072 and STM32F091 devices. - * @note USART3 is available only for STM32F091 devices. - * @param USART_AutoBaudRate: specifies the selected USART auto baud rate method. - * This parameter can be one of the following values: - * @arg USART_AutoBaudRate_StartBit: Start Bit duration measurement. - * @arg USART_AutoBaudRate_FallingEdge: Falling edge to falling edge measurement. - * @note This function has to be called before calling USART_Cmd() function. - * @retval None - */ -void USART_AutoBaudRateConfig(USART_TypeDef* USARTx, uint32_t USART_AutoBaudRate) -{ - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - assert_param(IS_USART_AUTOBAUDRATE_MODE(USART_AutoBaudRate)); - - USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ABRMODE); - USARTx->CR2 |= USART_AutoBaudRate; -} - -/** - * @} - */ - - -/** @defgroup USART_Group4 Data transfers functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### Data transfers functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to manage - the USART data transfers. - [..] During an USART reception, data shifts in least significant bit first - through the RX pin. When a transmission is taking place, a write instruction to - the USART_TDR register stores the data in the shift register. - [..] The read access of the USART_RDR register can be done using - the USART_ReceiveData() function and returns the RDR value. - Whereas a write access to the USART_TDR can be done using USART_SendData() - function and stores the written data into TDR. - -@endverbatim - * @{ - */ - -/** - * @brief Transmits single data through the USARTx peripheral. - * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. - * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. - * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. - * @note USART2 is not available for STM32F031 devices. - * @param Data: the data to transmit. - * @retval None - */ -void USART_SendData(USART_TypeDef* USARTx, uint16_t Data) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_DATA(Data)); - - /* Transmit Data */ - USARTx->TDR = (Data & (uint16_t)0x01FF); -} - -/** - * @brief Returns the most recent received data by the USARTx peripheral. - * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. - * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. - * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. - * @note USART2 is not available for STM32F031 devices. - * @retval The received data. - */ -uint16_t USART_ReceiveData(USART_TypeDef* USARTx) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - /* Receive Data */ - return (uint16_t)(USARTx->RDR & (uint16_t)0x01FF); -} - -/** - * @} - */ - -/** @defgroup USART_Group5 MultiProcessor Communication functions - * @brief Multi-Processor Communication functions - * -@verbatim - =============================================================================== - ##### Multi-Processor Communication functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to manage the USART - multiprocessor communication. - [..] For instance one of the USARTs can be the master, its TX output is - connected to the RX input of the other USART. The others are slaves, - their respective TX outputs are logically ANDed together and connected - to the RX input of the master. USART multiprocessor communication is - possible through the following procedure: - (#) Program the Baud rate, Word length = 9 bits, Stop bits, Parity, - Mode transmitter or Mode receiver and hardware flow control values - using the USART_Init() function. - (#) Configures the USART address using the USART_SetAddress() function. - (#) Configures the wake up methode (USART_WakeUp_IdleLine or - USART_WakeUp_AddressMark) using USART_WakeUpConfig() function only - for the slaves. - (#) Enable the USART using the USART_Cmd() function. - (#) Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd() - function. - [..] The USART Slave exit from mute mode when receive the wake up condition. - -@endverbatim - * @{ - */ - -/** - * @brief Sets the address of the USART node. - * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. - * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. - * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. - * @note USART2 is not available for STM32F031 devices. - * @param USART_Address: Indicates the address of the USART node. - * @retval None - */ -void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - /* Clear the USART address */ - USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ADD); - /* Set the USART address node */ - USARTx->CR2 |=((uint32_t)USART_Address << (uint32_t)0x18); -} - -/** - * @brief Enables or disables the USART's mute mode. - * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. - * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. - * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. - * @note USART2 is not available for STM32F031 devices. - * @param NewState: new state of the USART mute mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_MuteModeCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the USART mute mode by setting the MME bit in the CR1 register */ - USARTx->CR1 |= USART_CR1_MME; - } - else - { - /* Disable the USART mute mode by clearing the MME bit in the CR1 register */ - USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_MME); - } -} - -/** - * @brief Selects the USART WakeUp method from mute mode. - * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. - * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. - * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. - * @note USART2 is not available for STM32F031 devices. - * @param USART_WakeUp: specifies the USART wakeup method. - * This parameter can be one of the following values: - * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection - * @arg USART_WakeUp_AddressMark: WakeUp by an address mark - * @retval None - */ -void USART_MuteModeWakeUpConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUp) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_MUTEMODE_WAKEUP(USART_WakeUp)); - - USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_WAKE); - USARTx->CR1 |= USART_WakeUp; -} - -/** - * @brief Configure the the USART Address detection length. - * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. - * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. - * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. - * @note USART2 is not available for STM32F031 devices. - * @param USART_AddressLength: specifies the USART address length detection. - * This parameter can be one of the following values: - * @arg USART_AddressLength_4b: 4-bit address length detection - * @arg USART_AddressLength_7b: 7-bit address length detection - * @retval None - */ -void USART_AddressDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_AddressLength) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_ADDRESS_DETECTION(USART_AddressLength)); - - USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ADDM7); - USARTx->CR2 |= USART_AddressLength; -} - -/** - * @} - */ - -/** @defgroup USART_Group6 LIN mode functions - * @brief LIN mode functions - * -@verbatim - =============================================================================== - ##### LIN mode functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to manage the USART - LIN Mode communication. - [..] In LIN mode, 8-bit data format with 1 stop bit is required in accordance - with the LIN standard. - [..] Only this LIN Feature is supported by the USART IP: - (+) LIN Master Synchronous Break send capability and LIN slave break - detection capability : 13-bit break generation and 10/11 bit break - detection. - [..] USART LIN Master transmitter communication is possible through the - following procedure: - (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, - Mode transmitter or Mode receiver and hardware flow control values - using the USART_Init() function. - (#) Enable the LIN mode using the USART_LINCmd() function. - (#) Enable the USART using the USART_Cmd() function. - (#) Send the break character using USART_SendBreak() function. - [..] USART LIN Master receiver communication is possible through the - following procedure: - (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, - Mode transmitter or Mode receiver and hardware flow control values - using the USART_Init() function. - (#) Configures the break detection length - using the USART_LINBreakDetectLengthConfig() function. - (#) Enable the LIN mode using the USART_LINCmd() function. - -@- In LIN mode, the following bits must be kept cleared: - (+@) CLKEN in the USART_CR2 register. - (+@) STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register. - (#) Enable the USART using the USART_Cmd() function. - -@endverbatim - * @{ - */ - -/** - * @brief Sets the USART LIN Break detection length. - * @note This function is not available for STM32F030 devices. - * @param USARTx: where x can be 1or 2 to select the USART peripheral. - * @note USART2 is available only for STM32F072 and STM32F091 devices. - * @note USART3 is available only for STM32F091 devices. - * @param USART_LINBreakDetectLength: specifies the LIN break detection length. - * This parameter can be one of the following values: - * @arg USART_LINBreakDetectLength_10b: 10-bit break detection - * @arg USART_LINBreakDetectLength_11b: 11-bit break detection - * @retval None - */ -void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint32_t USART_LINBreakDetectLength) -{ - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength)); - - USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_LBDL); - USARTx->CR2 |= USART_LINBreakDetectLength; -} - -/** - * @brief Enables or disables the USART's LIN mode. - * @note This function is not available for STM32F030 devices. - * @param USARTx: where x can be 1or 2 to select the USART peripheral. - * @note USART2 is available only for STM32F072 and STM32F091 devices. - * @note USART3 is available only for STM32F091 devices. - * @param NewState: new state of the USART LIN mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ - USARTx->CR2 |= USART_CR2_LINEN; - } - else - { - /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */ - USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_LINEN); - } -} - -/** - * @} - */ - -/** @defgroup USART_Group7 Halfduplex mode function - * @brief Half-duplex mode function - * -@verbatim - =============================================================================== - ##### Half-duplex mode function ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to manage the USART - Half-duplex communication. - [..] The USART can be configured to follow a single-wire half-duplex protocol - where the TX and RX lines are internally connected. - [..] USART Half duplex communication is possible through the following procedure: - (#) Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter - or Mode receiver and hardware flow control values using the USART_Init() - function. - (#) Configures the USART address using the USART_SetAddress() function. - (#) Enable the half duplex mode using USART_HalfDuplexCmd() function. - (#) Enable the USART using the USART_Cmd() function. - -@- The RX pin is no longer used. - -@- In Half-duplex mode the following bits must be kept cleared: - (+@) LINEN and CLKEN bits in the USART_CR2 register. - (+@) SCEN and IREN bits in the USART_CR3 register. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the USART's Half Duplex communication. - * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. - * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. - * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. - * @note USART2 is not available for STM32F031 devices. - * @param NewState: new state of the USART Communication. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_HDSEL; - } - else - { - /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */ - USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_HDSEL); - } -} - -/** - * @} - */ - - -/** @defgroup USART_Group8 Smartcard mode functions - * @brief Smartcard mode functions - * -@verbatim - =============================================================================== - ##### Smartcard mode functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to manage the USART - Smartcard communication. - [..] The Smartcard interface is designed to support asynchronous protocol - Smartcards as defined in the ISO 7816-3 standard. The USART can provide - a clock to the smartcard through the SCLK output. In smartcard mode, - SCLK is not associated to the communication but is simply derived from - the internal peripheral input clock through a 5-bit prescaler. - [..] Smartcard communication is possible through the following procedure: - (#) Configures the Smartcard Prsecaler using the USART_SetPrescaler() - function. - (#) Configures the Smartcard Guard Time using the USART_SetGuardTime() - function. - (#) Program the USART clock using the USART_ClockInit() function as following: - (++) USART Clock enabled. - (++) USART CPOL Low. - (++) USART CPHA on first edge. - (++) USART Last Bit Clock Enabled. - (#) Program the Smartcard interface using the USART_Init() function as - following: - (++) Word Length = 9 Bits. - (++) 1.5 Stop Bit. - (++) Even parity. - (++) BaudRate = 12096 baud. - (++) Hardware flow control disabled (RTS and CTS signals). - (++) Tx and Rx enabled - (#) Optionally you can enable the parity error interrupt using - the USART_ITConfig() function. - (#) Enable the Smartcard NACK using the USART_SmartCardNACKCmd() function. - (#) Enable the Smartcard interface using the USART_SmartCardCmd() function. - (#) Enable the USART using the USART_Cmd() function. - [..] - Please refer to the ISO 7816-3 specification for more details. - [..] - (@) It is also possible to choose 0.5 stop bit for receiving but it is - recommended to use 1.5 stop bits for both transmitting and receiving - to avoid switching between the two configurations. - (@) In smartcard mode, the following bits must be kept cleared: - (+@) LINEN bit in the USART_CR2 register. - (+@) HDSEL and IREN bits in the USART_CR3 register. - -@endverbatim - * @{ - */ - -/** - * @brief Sets the specified USART guard time. - * @note This function is not available for STM32F030 devices. - * @param USARTx: where x can be 1or 2 to select the USART peripheral. - * @note USART2 is available only for STM32F072 and STM32F091 devices. - * @note USART3 is available only for STM32F091 devices. - * @param USART_GuardTime: specifies the guard time. - * @retval None - */ -void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime) -{ - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - - /* Clear the USART Guard time */ - USARTx->GTPR &= USART_GTPR_PSC; - /* Set the USART guard time */ - USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); -} - -/** - * @brief Enables or disables the USART's Smart Card mode. - * @note This function is not available for STM32F030 devices. - * @param USARTx: where x can be 1or 2 to select the USART peripheral. - * @note USART2 is available only for STM32F072 and STM32F091 devices. - * @note USART3 is available only for STM32F091 devices. - * @param NewState: new state of the Smart Card mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the SC mode by setting the SCEN bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_SCEN; - } - else - { - /* Disable the SC mode by clearing the SCEN bit in the CR3 register */ - USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_SCEN); - } -} - -/** - * @brief Enables or disables NACK transmission. - * @note This function is not available for STM32F030 devices. - * @param USARTx: where x can be 1or 2 to select the USART peripheral. - * @note USART2 is available only for STM32F072 and STM32F091 devices. - * @note USART3 is available only for STM32F091 devices. - * @param NewState: new state of the NACK transmission. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the NACK transmission by setting the NACK bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_NACK; - } - else - { - /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */ - USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_NACK); - } -} - -/** - * @brief Sets the Smart Card number of retries in transmit and receive. - * @note This function is not available for STM32F030 devices. - * @param USARTx: where x can be 1or 3 to select the USART peripheral. - * @note USART2 is available only for STM32F072 and STM32F091 devices. - * @note USART3 is available only for STM32F091 devices. - * @param USART_AutoCount: specifies the Smart Card auto retry count. - * @retval None - */ -void USART_SetAutoRetryCount(USART_TypeDef* USARTx, uint8_t USART_AutoCount) -{ - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - assert_param(IS_USART_AUTO_RETRY_COUNTER(USART_AutoCount)); - /* Clear the USART auto retry count */ - USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_SCARCNT); - /* Set the USART auto retry count*/ - USARTx->CR3 |= (uint32_t)((uint32_t)USART_AutoCount << 0x11); -} - -/** - * @brief Sets the Smart Card Block length. - * @note This function is not available for STM32F030 devices. - * @param USARTx: where x can be 1or 3 to select the USART peripheral. - * @note USART2 is available only for STM32F072 and STM32F091 devices. - * @note USART3 is available only for STM32F091 devices. - * @param USART_BlockLength: specifies the Smart Card block length. - * @retval None - */ -void USART_SetBlockLength(USART_TypeDef* USARTx, uint8_t USART_BlockLength) -{ - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - - /* Clear the Smart card block length */ - USARTx->RTOR &= (uint32_t)~((uint32_t)USART_RTOR_BLEN); - /* Set the Smart Card block length */ - USARTx->RTOR |= (uint32_t)((uint32_t)USART_BlockLength << 0x18); -} - -/** - * @} - */ - -/** @defgroup USART_Group9 IrDA mode functions - * @brief IrDA mode functions - * -@verbatim - =============================================================================== - ##### IrDA mode functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to manage the USART - IrDA communication. - [..] IrDA is a half duplex communication protocol. If the Transmitter is busy, - any data on the IrDA receive line will be ignored by the IrDA decoder - and if the Receiver is busy, data on the TX from the USART to IrDA will - not be encoded by IrDA. While receiving data, transmission should be - avoided as the data to be transmitted could be corrupted. - [..] IrDA communication is possible through the following procedure: - (#) Program the Baud rate, Word length = 8 bits, Stop bits, Parity, - Transmitter/Receiver modes and hardware flow control values using - the USART_Init() function. - (#) Configures the IrDA pulse width by configuring the prescaler using - the USART_SetPrescaler() function. - (#) Configures the IrDA USART_IrDAMode_LowPower or USART_IrDAMode_Normal - mode using the USART_IrDAConfig() function. - (#) Enable the IrDA using the USART_IrDACmd() function. - (#) Enable the USART using the USART_Cmd() function. - [..] - (@) A pulse of width less than two and greater than one PSC period(s) may or - may not be rejected. - (@) The receiver set up time should be managed by software. The IrDA physical - layer specification specifies a minimum of 10 ms delay between - transmission and reception (IrDA is a half duplex protocol). - (@) In IrDA mode, the following bits must be kept cleared: - (+@) LINEN, STOP and CLKEN bits in the USART_CR2 register. - (+@) SCEN and HDSEL bits in the USART_CR3 register. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the USART's IrDA interface. - * @note This function is not available for STM32F030 devices. - * @param USARTx: where x can be 1or 2 to select the USART peripheral. - * @note USART2 is available only for STM32F072 and STM32F091 devices. - * @note USART3 is available only for STM32F091 devices. - * @param USART_IrDAMode: specifies the IrDA mode. - * This parameter can be one of the following values: - * @arg USART_IrDAMode_LowPower - * @arg USART_IrDAMode_Normal - * @retval None - */ -void USART_IrDAConfig(USART_TypeDef* USARTx, uint32_t USART_IrDAMode) -{ - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - assert_param(IS_USART_IRDA_MODE(USART_IrDAMode)); - - USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_IRLP); - USARTx->CR3 |= USART_IrDAMode; -} - -/** - * @brief Enables or disables the USART's IrDA interface. - * @note This function is not available for STM32F030 devices. - * @param USARTx: where x can be 1or 2 to select the USART peripheral. - * @note USART2 is available only for STM32F072 and STM32F091 devices. - * @note USART3 is available only for STM32F091 devices. - * @param NewState: new state of the IrDA mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the IrDA mode by setting the IREN bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_IREN; - } - else - { - /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */ - USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_IREN); - } -} -/** - * @} - */ - -/** @defgroup USART_Group10 RS485 mode function - * @brief RS485 mode function - * -@verbatim - =============================================================================== - ##### RS485 mode functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to manage the USART - RS485 flow control. - [..] RS485 flow control (Driver enable feature) handling is possible through - the following procedure: - (#) Program the Baud rate, Word length = 8 bits, Stop bits, Parity, - Transmitter/Receiver modes and hardware flow control values using - the USART_Init() function. - (#) Enable the Driver Enable using the USART_DECmd() function. - (#) Configures the Driver Enable polarity using the USART_DEPolarityConfig() - function. - (#) Configures the Driver Enable assertion time using USART_SetDEAssertionTime() - function and deassertion time using the USART_SetDEDeassertionTime() - function. - (#) Enable the USART using the USART_Cmd() function. - -@- - (+@) The assertion and dessertion times are expressed in sample time units (1/8 or - 1/16 bit time, depending on the oversampling rate). - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the USART's DE functionality. - * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. - * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. - * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. - * @note USART2 is not available for STM32F031 devices. - * @param NewState: new state of the driver enable mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_DECmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the DE functionality by setting the DEM bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_DEM; - } - else - { - /* Disable the DE functionality by clearing the DEM bit in the CR3 register */ - USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DEM); - } -} - -/** - * @brief Configures the USART's DE polarity - * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. - * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. - * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. - * @note USART2 is not available for STM32F031 devices. - * @param USART_DEPolarity: specifies the DE polarity. - * This parameter can be one of the following values: - * @arg USART_DEPolarity_Low - * @arg USART_DEPolarity_High - * @retval None - */ -void USART_DEPolarityConfig(USART_TypeDef* USARTx, uint32_t USART_DEPolarity) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_DE_POLARITY(USART_DEPolarity)); - - USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DEP); - USARTx->CR3 |= USART_DEPolarity; -} - -/** - * @brief Sets the specified RS485 DE assertion time - * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. - * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. - * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. - * @note USART2 is not available for STM32F031 devices. - * @param USART_DEAssertionTime: specifies the time between the activation of - * the DE signal and the beginning of the start bit - * @retval None - */ -void USART_SetDEAssertionTime(USART_TypeDef* USARTx, uint32_t USART_DEAssertionTime) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_DE_ASSERTION_DEASSERTION_TIME(USART_DEAssertionTime)); - - /* Clear the DE assertion time */ - USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_DEAT); - /* Set the new value for the DE assertion time */ - USARTx->CR1 |=((uint32_t)USART_DEAssertionTime << (uint32_t)0x15); -} - -/** - * @brief Sets the specified RS485 DE deassertion time - * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. - * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. - * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. - * @note USART2 is not available for STM32F031 devices. - * @param USART_DeassertionTime: specifies the time between the middle of the last - * stop bit in a transmitted message and the de-activation of the DE signal - * @retval None - */ -void USART_SetDEDeassertionTime(USART_TypeDef* USARTx, uint32_t USART_DEDeassertionTime) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_DE_ASSERTION_DEASSERTION_TIME(USART_DEDeassertionTime)); - - /* Clear the DE deassertion time */ - USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_DEDT); - /* Set the new value for the DE deassertion time */ - USARTx->CR1 |=((uint32_t)USART_DEDeassertionTime << (uint32_t)0x10); -} - -/** - * @} - */ - -/** @defgroup USART_Group11 DMA transfers management functions - * @brief DMA transfers management functions - * -@verbatim - =============================================================================== - ##### DMA transfers management functions ##### - =============================================================================== - [..] This section provides two functions that can be used only in DMA mode. - [..] In DMA Mode, the USART communication can be managed by 2 DMA Channel - requests: - (#) USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request. - (#) USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request. - [..] In this Mode it is advised to use the following function: - (+) void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, - FunctionalState NewState). -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the USART's DMA interface. - * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. - * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. - * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. - * @note USART2 is not available for STM32F031 devices. - * @param USART_DMAReq: specifies the DMA request. - * This parameter can be any combination of the following values: - * @arg USART_DMAReq_Tx: USART DMA transmit request - * @arg USART_DMAReq_Rx: USART DMA receive request - * @param NewState: new state of the DMA Request sources. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_DMACmd(USART_TypeDef* USARTx, uint32_t USART_DMAReq, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_DMAREQ(USART_DMAReq)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DMA transfer for selected requests by setting the DMAT and/or - DMAR bits in the USART CR3 register */ - USARTx->CR3 |= USART_DMAReq; - } - else - { - /* Disable the DMA transfer for selected requests by clearing the DMAT and/or - DMAR bits in the USART CR3 register */ - USARTx->CR3 &= (uint32_t)~USART_DMAReq; - } -} - -/** - * @brief Enables or disables the USART's DMA interface when reception error occurs. - * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. - * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. - * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. - * @note USART2 is not available for STM32F031 devices. - * @param USART_DMAOnError: specifies the DMA status in case of reception error. - * This parameter can be any combination of the following values: - * @arg USART_DMAOnError_Enable: DMA receive request enabled when the USART DMA - * reception error is asserted. - * @arg USART_DMAOnError_Disable: DMA receive request disabled when the USART DMA - * reception error is asserted. - * @retval None - */ -void USART_DMAReceptionErrorConfig(USART_TypeDef* USARTx, uint32_t USART_DMAOnError) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_DMAONERROR(USART_DMAOnError)); - - /* Clear the DMA Reception error detection bit */ - USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DDRE); - /* Set the new value for the DMA Reception error detection bit */ - USARTx->CR3 |= USART_DMAOnError; -} - -/** - * @} - */ - -/** @defgroup USART_Group12 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to configure the - USART Interrupts sources, Requests and check or clear the flags or pending bits status. - The user should identify which mode will be used in his application to - manage the communication: Polling mode, Interrupt mode. - - *** Polling Mode *** - ==================== - [..] In Polling Mode, the SPI communication can be managed by these flags: - (#) USART_FLAG_REACK: to indicate the status of the Receive Enable - acknowledge flag - (#) USART_FLAG_TEACK: to indicate the status of the Transmit Enable - acknowledge flag. - (#) USART_FLAG_WU: to indicate the status of the Wake up flag. - (#) USART_FLAG_RWU: to indicate the status of the Receive Wake up flag. - (#) USART_FLAG_SBK: to indicate the status of the Send Break flag. - (#) USART_FLAG_CM: to indicate the status of the Character match flag. - (#) USART_FLAG_BUSY: to indicate the status of the Busy flag. - (#) USART_FLAG_ABRF: to indicate the status of the Auto baud rate flag. - (#) USART_FLAG_ABRE: to indicate the status of the Auto baud rate error flag. - (#) USART_FLAG_EOB: to indicate the status of the End of block flag. - (#) USART_FLAG_RTO: to indicate the status of the Receive time out flag. - (#) USART_FLAG_nCTSS: to indicate the status of the Inverted nCTS input - bit status. - (#) USART_FLAG_TXE: to indicate the status of the transmit buffer register. - (#) USART_FLAG_RXNE: to indicate the status of the receive buffer register. - (#) USART_FLAG_TC: to indicate the status of the transmit operation. - (#) USART_FLAG_IDLE: to indicate the status of the Idle Line. - (#) USART_FLAG_CTS: to indicate the status of the nCTS input. - (#) USART_FLAG_LBD: to indicate the status of the LIN break detection. - (#) USART_FLAG_NE: to indicate if a noise error occur. - (#) USART_FLAG_FE: to indicate if a frame error occur. - (#) USART_FLAG_PE: to indicate if a parity error occur. - (#) USART_FLAG_ORE: to indicate if an Overrun error occur. - [..] In this Mode it is advised to use the following functions: - (+) FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG). - (+) void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG). - - *** Interrupt Mode *** - ====================== - [..] In Interrupt Mode, the USART communication can be managed by 8 interrupt - sources and 10 pending bits: - (+) Pending Bits: - (##) USART_IT_WU: to indicate the status of the Wake up interrupt. - (##) USART_IT_CM: to indicate the status of Character match interrupt. - (##) USART_IT_EOB: to indicate the status of End of block interrupt. - (##) USART_IT_RTO: to indicate the status of Receive time out interrupt. - (##) USART_IT_CTS: to indicate the status of CTS change interrupt. - (##) USART_IT_LBD: to indicate the status of LIN Break detection interrupt. - (##) USART_IT_TC: to indicate the status of Transmission complete interrupt. - (##) USART_IT_IDLE: to indicate the status of IDLE line detected interrupt. - (##) USART_IT_ORE: to indicate the status of OverRun Error interrupt. - (##) USART_IT_NE: to indicate the status of Noise Error interrupt. - (##) USART_IT_FE: to indicate the status of Framing Error interrupt. - (##) USART_IT_PE: to indicate the status of Parity Error interrupt. - - (+) Interrupt Source: - (##) USART_IT_WU: specifies the interrupt source for Wake up interrupt. - (##) USART_IT_CM: specifies the interrupt source for Character match - interrupt. - (##) USART_IT_EOB: specifies the interrupt source for End of block - interrupt. - (##) USART_IT_RTO: specifies the interrupt source for Receive time-out - interrupt. - (##) USART_IT_CTS: specifies the interrupt source for CTS change interrupt. - (##) USART_IT_LBD: specifies the interrupt source for LIN Break - detection interrupt. - (##) USART_IT_TXE: specifies the interrupt source for Tansmit Data - Register empty interrupt. - (##) USART_IT_TC: specifies the interrupt source for Transmission - complete interrupt. - (##) USART_IT_RXNE: specifies the interrupt source for Receive Data - register not empty interrupt. - (##) USART_IT_IDLE: specifies the interrupt source for Idle line - detection interrupt. - (##) USART_IT_PE: specifies the interrupt source for Parity Error interrupt. - (##) USART_IT_ERR: specifies the interrupt source for Error interrupt - (Frame error, noise error, overrun error) - -@@- Some parameters are coded in order to use them as interrupt - source or as pending bits. - [..] In this Mode it is advised to use the following functions: - (+) void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState). - (+) ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT). - (+) void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT). - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified USART interrupts. - * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. - * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. - * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. - * @note USART2 is not available for STM32F031 devices. - * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg USART_IT_WU: Wake up interrupt, not available for STM32F030 devices. - * @arg USART_IT_CM: Character match interrupt. - * @arg USART_IT_EOB: End of block interrupt, not available for STM32F030 devices. - * @arg USART_IT_RTO: Receive time out interrupt. - * @arg USART_IT_CTS: CTS change interrupt. - * @arg USART_IT_LBD: LIN Break detection interrupt, not available for STM32F030 devices. - * @arg USART_IT_TXE: Tansmit Data Register empty interrupt. - * @arg USART_IT_TC: Transmission complete interrupt. - * @arg USART_IT_RXNE: Receive Data register not empty interrupt. - * @arg USART_IT_IDLE: Idle line detection interrupt. - * @arg USART_IT_PE: Parity Error interrupt. - * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) - * @param NewState: new state of the specified USARTx interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_ITConfig(USART_TypeDef* USARTx, uint32_t USART_IT, FunctionalState NewState) -{ - uint32_t usartreg = 0, itpos = 0, itmask = 0; - uint32_t usartxbase = 0; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CONFIG_IT(USART_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - usartxbase = (uint32_t)USARTx; - - /* Get the USART register index */ - usartreg = (((uint16_t)USART_IT) >> 0x08); - - /* Get the interrupt position */ - itpos = USART_IT & IT_MASK; - itmask = (((uint32_t)0x01) << itpos); - - if (usartreg == 0x02) /* The IT is in CR2 register */ - { - usartxbase += 0x04; - } - else if (usartreg == 0x03) /* The IT is in CR3 register */ - { - usartxbase += 0x08; - } - else /* The IT is in CR1 register */ - { - } - if (NewState != DISABLE) - { - *(__IO uint32_t*)usartxbase |= itmask; - } - else - { - *(__IO uint32_t*)usartxbase &= ~itmask; - } -} - -/** - * @brief Enables the specified USART's Request. - * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. - * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. - * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. - * @note USART2 is not available for STM32F031 devices. - * @param USART_Request: specifies the USART request. - * This parameter can be any combination of the following values: - * @arg USART_Request_TXFRQ: Transmit data flush ReQuest - * @arg USART_Request_RXFRQ: Receive data flush ReQuest - * @arg USART_Request_MMRQ: Mute Mode ReQuest - * @arg USART_Request_SBKRQ: Send Break ReQuest - * @arg USART_Request_ABRRQ: Auto Baud Rate ReQuest - * @param NewState: new state of the DMA interface when reception error occurs. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_RequestCmd(USART_TypeDef* USARTx, uint32_t USART_Request, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_REQUEST(USART_Request)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the USART ReQuest by setting the dedicated request bit in the RQR - register.*/ - USARTx->RQR |= USART_Request; - } - else - { - /* Disable the USART ReQuest by clearing the dedicated request bit in the RQR - register.*/ - USARTx->RQR &= (uint32_t)~USART_Request; - } -} - -/** - * @brief Enables or disables the USART's Overrun detection. - * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. - * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. - * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. - * @note USART2 is not available for STM32F031 devices. - * @param USART_OVRDetection: specifies the OVR detection status in case of OVR error. - * This parameter can be any combination of the following values: - * @arg USART_OVRDetection_Enable: OVR error detection enabled when - * the USART OVR error is asserted. - * @arg USART_OVRDetection_Disable: OVR error detection disabled when - * the USART OVR error is asserted. - * @retval None - */ -void USART_OverrunDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_OVRDetection) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_OVRDETECTION(USART_OVRDetection)); - - /* Clear the OVR detection bit */ - USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_OVRDIS); - /* Set the new value for the OVR detection bit */ - USARTx->CR3 |= USART_OVRDetection; -} - -/** - * @brief Checks whether the specified USART flag is set or not. - * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. - * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. - * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. - * @note USART2 is not available for STM32F031 devices. - * @param USART_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg USART_FLAG_REACK: Receive Enable acknowledge flag. - * @arg USART_FLAG_TEACK: Transmit Enable acknowledge flag. - * @arg USART_FLAG_WU: Wake up flag, not available for STM32F030 devices. - * @arg USART_FLAG_RWU: Receive Wake up flag, not available for STM32F030 devices. - * @arg USART_FLAG_SBK: Send Break flag. - * @arg USART_FLAG_CM: Character match flag. - * @arg USART_FLAG_BUSY: Busy flag. - * @arg USART_FLAG_ABRF: Auto baud rate flag. - * @arg USART_FLAG_ABRE: Auto baud rate error flag. - * @arg USART_FLAG_EOB: End of block flag, not available for STM32F030 devices. - * @arg USART_FLAG_RTO: Receive time out flag. - * @arg USART_FLAG_nCTSS: Inverted nCTS input bit status. - * @arg USART_FLAG_CTS: CTS Change flag. - * @arg USART_FLAG_LBD: LIN Break detection flag, not available for STM32F030 devices. - * @arg USART_FLAG_TXE: Transmit data register empty flag. - * @arg USART_FLAG_TC: Transmission Complete flag. - * @arg USART_FLAG_RXNE: Receive data register not empty flag. - * @arg USART_FLAG_IDLE: Idle Line detection flag. - * @arg USART_FLAG_ORE: OverRun Error flag. - * @arg USART_FLAG_NE: Noise Error flag. - * @arg USART_FLAG_FE: Framing Error flag. - * @arg USART_FLAG_PE: Parity Error flag. - * @retval The new state of USART_FLAG (SET or RESET). - */ -FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint32_t USART_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_FLAG(USART_FLAG)); - - if ((USARTx->ISR & USART_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the USARTx's pending flags. - * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. - * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. - * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. - * @note USART2 is not available for STM32F031 devices. - * @param USART_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg USART_FLAG_WU: Wake up flag, not available for STM32F030 devices. - * @arg USART_FLAG_CM: Character match flag. - * @arg USART_FLAG_EOB: End of block flag, not available for STM32F030 devices. - * @arg USART_FLAG_RTO: Receive time out flag. - * @arg USART_FLAG_CTS: CTS Change flag. - * @arg USART_FLAG_LBD: LIN Break detection flag, not available for STM32F030 devices. - * @arg USART_FLAG_TC: Transmission Complete flag. - * @arg USART_FLAG_IDLE: IDLE line detected flag. - * @arg USART_FLAG_ORE: OverRun Error flag. - * @arg USART_FLAG_NE: Noise Error flag. - * @arg USART_FLAG_FE: Framing Error flag. - * @arg USART_FLAG_PE: Parity Errorflag. - * - * @note RXNE pending bit is cleared by a read to the USART_RDR register - * (USART_ReceiveData()) or by writing 1 to the RXFRQ in the register - * USART_RQR (USART_RequestCmd()). - * @note TC flag can be also cleared by software sequence: a read operation - * to USART_SR register (USART_GetFlagStatus()) followed by a write - * operation to USART_TDR register (USART_SendData()). - * @note TXE flag is cleared by a write to the USART_TDR register (USART_SendData()) - * or by writing 1 to the TXFRQ in the register USART_RQR (USART_RequestCmd()). - * @note SBKF flag is cleared by 1 to the SBKRQ in the register USART_RQR - * (USART_RequestCmd()). - * @retval None - */ -void USART_ClearFlag(USART_TypeDef* USARTx, uint32_t USART_FLAG) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CLEAR_FLAG(USART_FLAG)); - - USARTx->ICR = USART_FLAG; -} - -/** - * @brief Checks whether the specified USART interrupt has occurred or not. - * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. - * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. - * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. - * @note USART2 is not available for STM32F031 devices. - * @param USART_IT: specifies the USART interrupt source to check. - * This parameter can be one of the following values: - * @arg USART_IT_WU: Wake up interrupt, not available for STM32F030 devices. - * @arg USART_IT_CM: Character match interrupt. - * @arg USART_IT_EOB: End of block interrupt, not available for STM32F030 devices. - * @arg USART_IT_RTO: Receive time out interrupt. - * @arg USART_IT_CTS: CTS change interrupt. - * @arg USART_IT_LBD: LIN Break detection interrupt, not available for STM32F030 devices. - * @arg USART_IT_TXE: Tansmit Data Register empty interrupt. - * @arg USART_IT_TC: Transmission complete interrupt. - * @arg USART_IT_RXNE: Receive Data register not empty interrupt. - * @arg USART_IT_IDLE: Idle line detection interrupt. - * @arg USART_IT_ORE: OverRun Error interrupt. - * @arg USART_IT_NE: Noise Error interrupt. - * @arg USART_IT_FE: Framing Error interrupt. - * @arg USART_IT_PE: Parity Error interrupt. - * @retval The new state of USART_IT (SET or RESET). - */ -ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint32_t USART_IT) -{ - uint32_t bitpos = 0, itmask = 0, usartreg = 0; - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_GET_IT(USART_IT)); - - /* Get the USART register index */ - usartreg = (((uint16_t)USART_IT) >> 0x08); - /* Get the interrupt position */ - itmask = USART_IT & IT_MASK; - itmask = (uint32_t)0x01 << itmask; - - if (usartreg == 0x01) /* The IT is in CR1 register */ - { - itmask &= USARTx->CR1; - } - else if (usartreg == 0x02) /* The IT is in CR2 register */ - { - itmask &= USARTx->CR2; - } - else /* The IT is in CR3 register */ - { - itmask &= USARTx->CR3; - } - - bitpos = USART_IT >> 0x10; - bitpos = (uint32_t)0x01 << bitpos; - bitpos &= USARTx->ISR; - if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/** - * @brief Clears the USARTx's interrupt pending bits. - * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. - * @note USART3 and USART4 are available only for STM32F072 and STM32F091 devices. - * @note USART5, USART6, USART7 and USART8 are available only for STM32F091 devices. - * @note USART2 is not available for STM32F031 devices. - * @param USART_IT: specifies the interrupt pending bit to clear. - * This parameter can be one of the following values: - * @arg USART_IT_WU: Wake up interrupt, not available for STM32F030 devices. - * @arg USART_IT_CM: Character match interrupt. - * @arg USART_IT_EOB: End of block interrupt, not available for STM32F030 devices. - * @arg USART_IT_RTO: Receive time out interrupt. - * @arg USART_IT_CTS: CTS change interrupt. - * @arg USART_IT_LBD: LIN Break detection interrupt, not available for STM32F030 devices. - * @arg USART_IT_TC: Transmission complete interrupt. - * @arg USART_IT_IDLE: IDLE line detected interrupt. - * @arg USART_IT_ORE: OverRun Error interrupt. - * @arg USART_IT_NE: Noise Error interrupt. - * @arg USART_IT_FE: Framing Error interrupt. - * @arg USART_IT_PE: Parity Error interrupt. - * - * @note RXNE pending bit is cleared by a read to the USART_RDR register - * (USART_ReceiveData()) or by writing 1 to the RXFRQ in the register - * USART_RQR (USART_RequestCmd()). - * @note TC pending bit can be also cleared by software sequence: a read - * operation to USART_SR register (USART_GetITStatus()) followed by - * a write operation to USART_TDR register (USART_SendData()). - * @note TXE pending bit is cleared by a write to the USART_TDR register - * (USART_SendData()) or by writing 1 to the TXFRQ in the register - * USART_RQR (USART_RequestCmd()). - * @retval None - */ -void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint32_t USART_IT) -{ - uint32_t bitpos = 0, itmask = 0; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CLEAR_IT(USART_IT)); - - bitpos = USART_IT >> 0x10; - itmask = ((uint32_t)0x01 << (uint32_t)bitpos); - USARTx->ICR = (uint32_t)itmask; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_wwdg.c b/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_wwdg.c deleted file mode 100644 --- a/libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_wwdg.c +++ /dev/null @@ -1,303 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_wwdg.c - * @author MCD Application Team - * @version V1.4.0 - * @date 24-July-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the Window watchdog (WWDG) peripheral: - * + Prescaler, Refresh window and Counter configuration - * + WWDG activation - * + Interrupts and flags management - * - * @verbatim - * - ============================================================================== - ##### WWDG features ##### - ============================================================================== - [..] Once enabled the WWDG generates a system reset on expiry of a programmed - time period, unless the program refreshes the counter (downcounter) - before to reach 0x3F value (i.e. a reset is generated when the counter - value rolls over from 0x40 to 0x3F). - [..] An MCU reset is also generated if the counter value is refreshed - before the counter has reached the refresh window value. This - implies that the counter must be refreshed in a limited window. - - [..] Once enabled the WWDG cannot be disabled except by a system reset. - - [..] WWDGRST flag in RCC_CSR register can be used to inform when a WWDG - reset occurs. - - [..] The WWDG counter input clock is derived from the APB clock divided - by a programmable prescaler. - - [..] WWDG counter clock = PCLK1 / Prescaler. - [..] WWDG timeout = (WWDG counter clock) * (counter value). - - [..] Min-max timeout value @32MHz (PCLK1): ~85us / ~43ms. - - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE) - function. - - (#) Configure the WWDG prescaler using WWDG_SetPrescaler() function. - - (#) Configure the WWDG refresh window using WWDG_SetWindowValue() function. - - (#) Set the WWDG counter value and start it using WWDG_Enable() function. - When the WWDG is enabled the counter value should be configured to - a value greater than 0x40 to prevent generating an immediate reset. - - (#) Optionally you can enable the Early wakeup interrupt which is - generated when the counter reach 0x40. - Once enabled this interrupt cannot be disabled except by a system reset. - - (#) Then the application program must refresh the WWDG counter at regular - intervals during normal operation to prevent an MCU reset, using - WWDG_SetCounter() function. This operation must occur only when - the counter value is lower than the refresh window value, - programmed using WWDG_SetWindowValue(). - - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_wwdg.h" -#include "stm32f0xx_rcc.h" - -/** @addtogroup STM32F0xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup WWDG - * @brief WWDG driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* --------------------- WWDG registers bit mask ---------------------------- */ -/* CFR register bit mask */ -#define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F) -#define CFR_W_MASK ((uint32_t)0xFFFFFF80) -#define BIT_MASK ((uint8_t)0x7F) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup WWDG_Private_Functions - * @{ - */ - -/** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions - * @brief Prescaler, Refresh window and Counter configuration functions - * -@verbatim - ============================================================================== - ##### Prescaler, Refresh window and Counter configuration functions ##### - ============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the WWDG peripheral registers to their default reset values. - * @param None - * @retval None - */ -void WWDG_DeInit(void) -{ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); -} - -/** - * @brief Sets the WWDG Prescaler. - * @param WWDG_Prescaler: specifies the WWDG Prescaler. - * This parameter can be one of the following values: - * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1 - * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2 - * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4 - * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8 - * @retval None - */ -void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler)); - /* Clear WDGTB[1:0] bits */ - tmpreg = WWDG->CFR & CFR_WDGTB_MASK; - /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */ - tmpreg |= WWDG_Prescaler; - /* Store the new value */ - WWDG->CFR = tmpreg; -} - -/** - * @brief Sets the WWDG window value. - * @param WindowValue: specifies the window value to be compared to the downcounter. - * This parameter value must be lower than 0x80. - * @retval None - */ -void WWDG_SetWindowValue(uint8_t WindowValue) -{ - __IO uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_WWDG_WINDOW_VALUE(WindowValue)); - /* Clear W[6:0] bits */ - - tmpreg = WWDG->CFR & CFR_W_MASK; - - /* Set W[6:0] bits according to WindowValue value */ - tmpreg |= WindowValue & (uint32_t) BIT_MASK; - - /* Store the new value */ - WWDG->CFR = tmpreg; -} - -/** - * @brief Enables the WWDG Early Wakeup interrupt(EWI). - * @note Once enabled this interrupt cannot be disabled except by a system reset. - * @param None - * @retval None - */ -void WWDG_EnableIT(void) -{ - WWDG->CFR |= WWDG_CFR_EWI; -} - -/** - * @brief Sets the WWDG counter value. - * @param Counter: specifies the watchdog counter value. - * This parameter must be a number between 0x40 and 0x7F (to prevent - * generating an immediate reset). - * @retval None - */ -void WWDG_SetCounter(uint8_t Counter) -{ - /* Check the parameters */ - assert_param(IS_WWDG_COUNTER(Counter)); - /* Write to T[6:0] bits to configure the counter value, no need to do - a read-modify-write; writing a 0 to WDGA bit does nothing */ - WWDG->CR = Counter & BIT_MASK; -} - -/** - * @} - */ - -/** @defgroup WWDG_Group2 WWDG activation functions - * @brief WWDG activation functions - * -@verbatim - ============================================================================== - ##### WWDG activation function ##### - ============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables WWDG and load the counter value. - * @param Counter: specifies the watchdog counter value. - * This parameter must be a number between 0x40 and 0x7F (to prevent - * generating an immediate reset). - * @retval None - */ -void WWDG_Enable(uint8_t Counter) -{ - /* Check the parameters */ - assert_param(IS_WWDG_COUNTER(Counter)); - WWDG->CR = WWDG_CR_WDGA | Counter; -} - -/** - * @} - */ - -/** @defgroup WWDG_Group3 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - ============================================================================== - ##### Interrupts and flags management functions ##### - ============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Checks whether the Early Wakeup interrupt flag is set or not. - * @param None - * @retval The new state of the Early Wakeup interrupt flag (SET or RESET). - */ -FlagStatus WWDG_GetFlagStatus(void) -{ - FlagStatus bitstatus = RESET; - - if ((WWDG->SR) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears Early Wakeup interrupt flag. - * @param None - * @retval None - */ -void WWDG_ClearFlag(void) -{ - WWDG->SR = (uint32_t)RESET; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32_USB_Device_Library/Class/CDC/usbd_cdc.c b/libraries/STM32_USB_Device_Library/Class/CDC/usbd_cdc.c new file mode 100644 --- /dev/null +++ b/libraries/STM32_USB_Device_Library/Class/CDC/usbd_cdc.c @@ -0,0 +1,911 @@ +/** + ****************************************************************************** + * @file usbd_cdc.c + * @author MCD Application Team + * @version V2.2.0 + * @date 13-June-2014 + * @brief This file provides the high layer firmware functions to manage the + * following functionalities of the USB CDC Class: + * - Initialization and Configuration of high and low layer + * - Enumeration as CDC Device (and enumeration for each implemented memory interface) + * - OUT/IN data transfer + * - Command IN transfer (class requests management) + * - Error management + * + * @verbatim + * + * =================================================================== + * CDC Class Driver Description + * =================================================================== + * This driver manages the "Universal Serial Bus Class Definitions for Communications Devices + * Revision 1.2 November 16, 2007" and the sub-protocol specification of "Universal Serial Bus + * Communications Class Subclass Specification for PSTN Devices Revision 1.2 February 9, 2007" + * This driver implements the following aspects of the specification: + * - Device descriptor management + * - Configuration descriptor management + * - Enumeration as CDC device with 2 data endpoints (IN and OUT) and 1 command endpoint (IN) + * - Requests management (as described in section 6.2 in specification) + * - Abstract Control Model compliant + * - Union Functional collection (using 1 IN endpoint for control) + * - Data interface class + * + * These aspects may be enriched or modified for a specific user application. + * + * This driver doesn't implement the following aspects of the specification + * (but it is possible to manage these features with some modifications on this driver): + * - Any class-specific aspect relative to communication classes should be managed by user application. + * - All communication classes other than PSTN are not managed + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "USBD_CDC.h" +#include "usbd_desc.h" +#include "usbd_ctlreq.h" + + +/** @addtogroup STM32_USB_DEVICE_LIBRARY + * @{ + */ + + +/** @defgroup USBD_CDC + * @brief usbd core module + * @{ + */ + +/** @defgroup USBD_CDC_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_CDC_Private_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_CDC_Private_Macros + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_CDC_Private_FunctionPrototypes + * @{ + */ + + +static uint8_t USBD_CDC_Init (USBD_HandleTypeDef *pdev, + uint8_t cfgidx); + +static uint8_t USBD_CDC_DeInit (USBD_HandleTypeDef *pdev, + uint8_t cfgidx); + +static uint8_t USBD_CDC_Setup (USBD_HandleTypeDef *pdev, + USBD_SetupReqTypedef *req); + +static uint8_t USBD_CDC_DataIn (USBD_HandleTypeDef *pdev, + uint8_t epnum); + +static uint8_t USBD_CDC_DataOut (USBD_HandleTypeDef *pdev, + uint8_t epnum); + +static uint8_t USBD_CDC_EP0_RxReady (USBD_HandleTypeDef *pdev); + +static uint8_t *USBD_CDC_GetFSCfgDesc (uint16_t *length); + +static uint8_t *USBD_CDC_GetHSCfgDesc (uint16_t *length); + +static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc (uint16_t *length); + +static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc (uint16_t *length); + +uint8_t *USBD_CDC_GetDeviceQualifierDescriptor (uint16_t *length); + +/* USB Standard Device Descriptor */ +__ALIGN_BEGIN static uint8_t USBD_CDC_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END = +{ + USB_LEN_DEV_QUALIFIER_DESC, + USB_DESC_TYPE_DEVICE_QUALIFIER, + 0x00, + 0x02, + 0x00, + 0x00, + 0x00, + 0x40, + 0x01, + 0x00, +}; + +/** + * @} + */ + +/** @defgroup USBD_CDC_Private_Variables + * @{ + */ + + +/* CDC interface class callbacks structure */ +USBD_ClassTypeDef USBD_CDC = +{ + USBD_CDC_Init, + USBD_CDC_DeInit, + USBD_CDC_Setup, + NULL, /* EP0_TxSent, */ + USBD_CDC_EP0_RxReady, + USBD_CDC_DataIn, + USBD_CDC_DataOut, + NULL, + NULL, + NULL, + USBD_CDC_GetHSCfgDesc, + USBD_CDC_GetFSCfgDesc, + USBD_CDC_GetOtherSpeedCfgDesc, + USBD_CDC_GetDeviceQualifierDescriptor, +}; + +/* USB CDC device Configuration Descriptor */ +__ALIGN_BEGIN uint8_t USBD_CDC_CfgHSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = +{ + /*Configuration Descriptor*/ + 0x09, /* bLength: Configuration Descriptor size */ + USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ + USB_CDC_CONFIG_DESC_SIZ, /* wTotalLength:no of returned bytes */ + 0x00, + 0x02, /* bNumInterfaces: 2 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ + 0xC0, /* bmAttributes: self powered */ + 0x32, /* MaxPower 0 mA */ + + /*---------------------------------------------------------------------------*/ + + /*Interface Descriptor */ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ + /* Interface descriptor type */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints: One endpoints used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x02, /* bInterfaceSubClass: Abstract Control Model */ + 0x01, /* bInterfaceProtocol: Common AT commands */ + 0x00, /* iInterface: */ + + /*Header Functional Descriptor*/ + 0x05, /* bLength: Endpoint Descriptor size */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x00, /* bDescriptorSubtype: Header Func Desc */ + 0x10, /* bcdCDC: spec release number */ + 0x01, + + /*Call Management Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x01, /* bDescriptorSubtype: Call Management Func Desc */ + 0x00, /* bmCapabilities: D0+D1 */ + 0x01, /* bDataInterface: 1 */ + + /*ACM Functional Descriptor*/ + 0x04, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ + 0x02, /* bmCapabilities */ + + /*Union Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x06, /* bDescriptorSubtype: Union func desc */ + 0x00, /* bMasterInterface: Communication class interface */ + 0x01, /* bSlaveInterface0: Data Class Interface */ + + /*Endpoint 2 Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_CMD_EP, /* bEndpointAddress */ + 0x03, /* bmAttributes: Interrupt */ + LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_CMD_PACKET_SIZE), + 0x10, /* bInterval: */ + /*---------------------------------------------------------------------------*/ + + /*Data class interface descriptor*/ + 0x09, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ + 0x01, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints: Two endpoints used */ + 0x0A, /* bInterfaceClass: CDC */ + 0x00, /* bInterfaceSubClass: */ + 0x00, /* bInterfaceProtocol: */ + 0x00, /* iInterface: */ + + /*Endpoint OUT Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_OUT_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), + 0x00, /* bInterval: ignore for Bulk transfer */ + + /*Endpoint IN Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_IN_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), + 0x00 /* bInterval: ignore for Bulk transfer */ +} ; + + +/* USB CDC device Configuration Descriptor */ +__ALIGN_BEGIN uint8_t USBD_CDC_CfgFSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = +{ + /*Configuration Descriptor*/ + 0x09, /* bLength: Configuration Descriptor size */ + USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ + USB_CDC_CONFIG_DESC_SIZ, /* wTotalLength:no of returned bytes */ + 0x00, + 0x02, /* bNumInterfaces: 2 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ + 0xC0, /* bmAttributes: self powered */ + 0x32, /* MaxPower 0 mA */ + + /*---------------------------------------------------------------------------*/ + + /*Interface Descriptor */ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ + /* Interface descriptor type */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints: One endpoints used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x02, /* bInterfaceSubClass: Abstract Control Model */ + 0x01, /* bInterfaceProtocol: Common AT commands */ + 0x00, /* iInterface: */ + + /*Header Functional Descriptor*/ + 0x05, /* bLength: Endpoint Descriptor size */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x00, /* bDescriptorSubtype: Header Func Desc */ + 0x10, /* bcdCDC: spec release number */ + 0x01, + + /*Call Management Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x01, /* bDescriptorSubtype: Call Management Func Desc */ + 0x00, /* bmCapabilities: D0+D1 */ + 0x01, /* bDataInterface: 1 */ + + /*ACM Functional Descriptor*/ + 0x04, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ + 0x02, /* bmCapabilities */ + + /*Union Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x06, /* bDescriptorSubtype: Union func desc */ + 0x00, /* bMasterInterface: Communication class interface */ + 0x01, /* bSlaveInterface0: Data Class Interface */ + + /*Endpoint 2 Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_CMD_EP, /* bEndpointAddress */ + 0x03, /* bmAttributes: Interrupt */ + LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_CMD_PACKET_SIZE), + 0x10, /* bInterval: */ + /*---------------------------------------------------------------------------*/ + + /*Data class interface descriptor*/ + 0x09, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ + 0x01, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints: Two endpoints used */ + 0x0A, /* bInterfaceClass: CDC */ + 0x00, /* bInterfaceSubClass: */ + 0x00, /* bInterfaceProtocol: */ + 0x00, /* iInterface: */ + + /*Endpoint OUT Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_OUT_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), + 0x00, /* bInterval: ignore for Bulk transfer */ + + /*Endpoint IN Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_IN_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), + 0x00 /* bInterval: ignore for Bulk transfer */ +} ; + +__ALIGN_BEGIN uint8_t USBD_CDC_OtherSpeedCfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = +{ + 0x09, /* bLength: Configuation Descriptor size */ + USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION, + USB_CDC_CONFIG_DESC_SIZ, + 0x00, + 0x02, /* bNumInterfaces: 2 interfaces */ + 0x01, /* bConfigurationValue: */ + 0x04, /* iConfiguration: */ + 0xC0, /* bmAttributes: */ + 0x32, /* MaxPower 100 mA */ + + /*Interface Descriptor */ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ + /* Interface descriptor type */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints: One endpoints used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x02, /* bInterfaceSubClass: Abstract Control Model */ + 0x01, /* bInterfaceProtocol: Common AT commands */ + 0x00, /* iInterface: */ + + /*Header Functional Descriptor*/ + 0x05, /* bLength: Endpoint Descriptor size */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x00, /* bDescriptorSubtype: Header Func Desc */ + 0x10, /* bcdCDC: spec release number */ + 0x01, + + /*Call Management Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x01, /* bDescriptorSubtype: Call Management Func Desc */ + 0x00, /* bmCapabilities: D0+D1 */ + 0x01, /* bDataInterface: 1 */ + + /*ACM Functional Descriptor*/ + 0x04, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ + 0x02, /* bmCapabilities */ + + /*Union Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x06, /* bDescriptorSubtype: Union func desc */ + 0x00, /* bMasterInterface: Communication class interface */ + 0x01, /* bSlaveInterface0: Data Class Interface */ + + /*Endpoint 2 Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT , /* bDescriptorType: Endpoint */ + CDC_CMD_EP, /* bEndpointAddress */ + 0x03, /* bmAttributes: Interrupt */ + LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_CMD_PACKET_SIZE), + 0xFF, /* bInterval: */ + + /*---------------------------------------------------------------------------*/ + + /*Data class interface descriptor*/ + 0x09, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ + 0x01, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints: Two endpoints used */ + 0x0A, /* bInterfaceClass: CDC */ + 0x00, /* bInterfaceSubClass: */ + 0x00, /* bInterfaceProtocol: */ + 0x00, /* iInterface: */ + + /*Endpoint OUT Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_OUT_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + 0x40, /* wMaxPacketSize: */ + 0x00, + 0x00, /* bInterval: ignore for Bulk transfer */ + + /*Endpoint IN Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_IN_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + 0x40, /* wMaxPacketSize: */ + 0x00, + 0x00 /* bInterval */ +}; + +/** + * @} + */ + +/** @defgroup USBD_CDC_Private_Functions + * @{ + */ + +/** + * @brief USBD_CDC_Init + * Initilaize the CDC interface + * @param pdev: device instance + * @param cfgidx: Configuration index + * @retval status + */ +static uint8_t USBD_CDC_Init (USBD_HandleTypeDef *pdev, + uint8_t cfgidx) +{ + uint8_t ret = 0; + USBD_CDC_HandleTypeDef *hcdc; + + if(pdev->dev_speed == USBD_SPEED_HIGH ) + { + /* Open EP IN */ + USBD_LL_OpenEP(pdev, + CDC_IN_EP, + USBD_EP_TYPE_BULK, + CDC_DATA_HS_IN_PACKET_SIZE); + + /* Open EP OUT */ + USBD_LL_OpenEP(pdev, + CDC_OUT_EP, + USBD_EP_TYPE_BULK, + CDC_DATA_HS_OUT_PACKET_SIZE); + + } + else + { + /* Open EP IN */ + USBD_LL_OpenEP(pdev, + CDC_IN_EP, + USBD_EP_TYPE_BULK, + CDC_DATA_FS_IN_PACKET_SIZE); + + /* Open EP OUT */ + USBD_LL_OpenEP(pdev, + CDC_OUT_EP, + USBD_EP_TYPE_BULK, + CDC_DATA_FS_OUT_PACKET_SIZE); + } + /* Open Command IN EP */ + USBD_LL_OpenEP(pdev, + CDC_CMD_EP, + USBD_EP_TYPE_INTR, + CDC_CMD_PACKET_SIZE); + + + pdev->pClassData = USBD_malloc(sizeof (USBD_CDC_HandleTypeDef)); + + if(pdev->pClassData == NULL) + { + ret = 1; + } + else + { + hcdc = pdev->pClassData; + + /* Init physical Interface components */ + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Init(); + + /* Init Xfer states */ + hcdc->TxState =0; + hcdc->RxState =0; + + if(pdev->dev_speed == USBD_SPEED_HIGH ) + { + /* Prepare Out endpoint to receive next packet */ + USBD_LL_PrepareReceive(pdev, + CDC_OUT_EP, + hcdc->RxBuffer, + CDC_DATA_HS_OUT_PACKET_SIZE); + } + else + { + /* Prepare Out endpoint to receive next packet */ + USBD_LL_PrepareReceive(pdev, + CDC_OUT_EP, + hcdc->RxBuffer, + CDC_DATA_FS_OUT_PACKET_SIZE); + } + + + } + return ret; +} + +/** + * @brief USBD_CDC_Init + * DeInitialize the CDC layer + * @param pdev: device instance + * @param cfgidx: Configuration index + * @retval status + */ +static uint8_t USBD_CDC_DeInit (USBD_HandleTypeDef *pdev, + uint8_t cfgidx) +{ + uint8_t ret = 0; + + /* Open EP IN */ + USBD_LL_CloseEP(pdev, + CDC_IN_EP); + + /* Open EP OUT */ + USBD_LL_CloseEP(pdev, + CDC_OUT_EP); + + /* Open Command IN EP */ + USBD_LL_CloseEP(pdev, + CDC_CMD_EP); + + + /* DeInit physical Interface components */ + if(pdev->pClassData != NULL) + { + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->DeInit(); + USBD_free(pdev->pClassData); + pdev->pClassData = NULL; + } + + return ret; +} + +/** + * @brief USBD_CDC_Setup + * Handle the CDC specific requests + * @param pdev: instance + * @param req: usb requests + * @retval status + */ +static uint8_t USBD_CDC_Setup (USBD_HandleTypeDef *pdev, + USBD_SetupReqTypedef *req) +{ + USBD_CDC_HandleTypeDef *hcdc = pdev->pClassData; + + switch (req->bmRequest & USB_REQ_TYPE_MASK) + { + case USB_REQ_TYPE_CLASS : + if (req->wLength) + { + if (req->bmRequest & 0x80) + { + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest, + (uint8_t *)hcdc->data, + req->wLength); + USBD_CtlSendData (pdev, + (uint8_t *)hcdc->data, + req->wLength); + } + else + { + hcdc->CmdOpCode = req->bRequest; + hcdc->CmdLength = req->wLength; + + USBD_CtlPrepareRx (pdev, + (uint8_t *)hcdc->data, + req->wLength); + } + + } + else + { + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest, + NULL, + 0); + } + break; + + default: + break; + } + return USBD_OK; +} + +/** + * @brief usbd_audio_DataIn + * Data sent on non-control IN endpoint + * @param pdev: device instance + * @param epnum: endpoint number + * @retval status + */ +static uint8_t USBD_CDC_DataIn (USBD_HandleTypeDef *pdev, uint8_t epnum) +{ + USBD_CDC_HandleTypeDef *hcdc = pdev->pClassData; + + if(pdev->pClassData != NULL) + { + + hcdc->TxState = 0; + + return USBD_OK; + } + else + { + return USBD_FAIL; + } +} + +/** + * @brief USBD_CDC_DataOut + * Data received on non-control Out endpoint + * @param pdev: device instance + * @param epnum: endpoint number + * @retval status + */ +static uint8_t USBD_CDC_DataOut (USBD_HandleTypeDef *pdev, uint8_t epnum) +{ + USBD_CDC_HandleTypeDef *hcdc = pdev->pClassData; + + /* Get the received data length */ + hcdc->RxLength = USBD_LL_GetRxDataSize (pdev, epnum); + + /* USB data will be immediately processed, this allow next USB traffic being + NAKed till the end of the application Xfer */ + if(pdev->pClassData != NULL) + { + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Receive(hcdc->RxBuffer, &hcdc->RxLength); + + return USBD_OK; + } + else + { + return USBD_FAIL; + } +} + + + +/** + * @brief USBD_CDC_DataOut + * Data received on non-control Out endpoint + * @param pdev: device instance + * @param epnum: endpoint number + * @retval status + */ +static uint8_t USBD_CDC_EP0_RxReady (USBD_HandleTypeDef *pdev) +{ + USBD_CDC_HandleTypeDef *hcdc = pdev->pClassData; + + if((pdev->pUserData != NULL) && (hcdc->CmdOpCode != 0xFF)) + { + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(hcdc->CmdOpCode, + (uint8_t *)hcdc->data, + hcdc->CmdLength); + hcdc->CmdOpCode = 0xFF; + + } + return USBD_OK; +} + +/** + * @brief USBD_CDC_GetFSCfgDesc + * Return configuration descriptor + * @param speed : current device speed + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +static uint8_t *USBD_CDC_GetFSCfgDesc (uint16_t *length) +{ + *length = sizeof (USBD_CDC_CfgFSDesc); + return USBD_CDC_CfgFSDesc; +} + +/** + * @brief USBD_CDC_GetHSCfgDesc + * Return configuration descriptor + * @param speed : current device speed + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +static uint8_t *USBD_CDC_GetHSCfgDesc (uint16_t *length) +{ + *length = sizeof (USBD_CDC_CfgHSDesc); + return USBD_CDC_CfgHSDesc; +} + +/** + * @brief USBD_CDC_GetCfgDesc + * Return configuration descriptor + * @param speed : current device speed + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc (uint16_t *length) +{ + *length = sizeof (USBD_CDC_OtherSpeedCfgDesc); + return USBD_CDC_OtherSpeedCfgDesc; +} + +/** +* @brief DeviceQualifierDescriptor +* return Device Qualifier descriptor +* @param length : pointer data length +* @retval pointer to descriptor buffer +*/ +uint8_t *USBD_CDC_GetDeviceQualifierDescriptor (uint16_t *length) +{ + *length = sizeof (USBD_CDC_DeviceQualifierDesc); + return USBD_CDC_DeviceQualifierDesc; +} + +/** +* @brief USBD_CDC_RegisterInterface + * @param pdev: device instance + * @param fops: CD Interface callback + * @retval status + */ +uint8_t USBD_CDC_RegisterInterface (USBD_HandleTypeDef *pdev, + USBD_CDC_ItfTypeDef *fops) +{ + uint8_t ret = USBD_FAIL; + + if(fops != NULL) + { + pdev->pUserData= fops; + ret = USBD_OK; + } + + return ret; +} + +/** + * @brief USBD_CDC_SetTxBuffer + * @param pdev: device instance + * @param pbuff: Tx Buffer + * @retval status + */ +uint8_t USBD_CDC_SetTxBuffer (USBD_HandleTypeDef *pdev, + uint8_t *pbuff, + uint16_t length) +{ + USBD_CDC_HandleTypeDef *hcdc = pdev->pClassData; + + hcdc->TxBuffer = pbuff; + hcdc->TxLength = length; + + return USBD_OK; +} + + +/** + * @brief USBD_CDC_SetRxBuffer + * @param pdev: device instance + * @param pbuff: Rx Buffer + * @retval status + */ +uint8_t USBD_CDC_SetRxBuffer (USBD_HandleTypeDef *pdev, + uint8_t *pbuff) +{ + USBD_CDC_HandleTypeDef *hcdc = pdev->pClassData; + + hcdc->RxBuffer = pbuff; + + return USBD_OK; +} + +/** + * @brief USBD_CDC_DataOut + * Data received on non-control Out endpoint + * @param pdev: device instance + * @param epnum: endpoint number + * @retval status + */ +uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev) +{ + USBD_CDC_HandleTypeDef *hcdc = pdev->pClassData; + + if(pdev->pClassData != NULL) + { + if(hcdc->TxState == 0) + { + + /* Transmit next packet */ + USBD_LL_Transmit(pdev, + CDC_IN_EP, + hcdc->TxBuffer, + hcdc->TxLength); + + /* Tx Transfer in progress */ + hcdc->TxState = 1; + return USBD_OK; + } + else + { + return USBD_BUSY; + } + } + else + { + return USBD_FAIL; + } +} + + +/** + * @brief USBD_CDC_ReceivePacket + * prepare OUT Endpoint for reception + * @param pdev: device instance + * @retval status + */ +uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev) +{ + USBD_CDC_HandleTypeDef *hcdc = pdev->pClassData; + + /* Suspend or Resume USB Out process */ + if(pdev->pClassData != NULL) + { + if(pdev->dev_speed == USBD_SPEED_HIGH ) + { + /* Prepare Out endpoint to receive next packet */ + USBD_LL_PrepareReceive(pdev, + CDC_OUT_EP, + hcdc->RxBuffer, + CDC_DATA_HS_OUT_PACKET_SIZE); + } + else + { + /* Prepare Out endpoint to receive next packet */ + USBD_LL_PrepareReceive(pdev, + CDC_OUT_EP, + hcdc->RxBuffer, + CDC_DATA_FS_OUT_PACKET_SIZE); + } + return USBD_OK; + } + else + { + return USBD_FAIL; + } +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32_USB_Device_Library/Class/CDC/usbd_cdc.h b/libraries/STM32_USB_Device_Library/Class/CDC/usbd_cdc.h new file mode 100644 --- /dev/null +++ b/libraries/STM32_USB_Device_Library/Class/CDC/usbd_cdc.h @@ -0,0 +1,172 @@ +/** + ****************************************************************************** + * @file usbd_cdc.h + * @author MCD Application Team + * @version V2.2.0 + * @date 13-June-2014 + * @brief header file for the usbd_cdc.c file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ + +#ifndef __USB_CDC_CORE_H_ +#define __USB_CDC_CORE_H_ + +#include "usbd_ioreq.h" + +/** @addtogroup STM32_USB_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup usbd_cdc + * @brief This file is the Header file for USBD_cdc.c + * @{ + */ + + +/** @defgroup usbd_cdc_Exported_Defines + * @{ + */ +#define CDC_IN_EP 0x81 /* EP1 for data IN */ +#define CDC_OUT_EP 0x01 /* EP1 for data OUT */ +#define CDC_CMD_EP 0x82 /* EP2 for CDC commands */ + +/* CDC Endpoints parameters: you can fine tune these values depending on the needed baudrates and performance. */ +#define CDC_DATA_HS_MAX_PACKET_SIZE 512 /* Endpoint IN & OUT Packet size */ +#define CDC_DATA_FS_MAX_PACKET_SIZE 64 /* Endpoint IN & OUT Packet size */ +#define CDC_CMD_PACKET_SIZE 8 /* Control Endpoint Packet size */ + +#define USB_CDC_CONFIG_DESC_SIZ 67 +#define CDC_DATA_HS_IN_PACKET_SIZE CDC_DATA_HS_MAX_PACKET_SIZE +#define CDC_DATA_HS_OUT_PACKET_SIZE CDC_DATA_HS_MAX_PACKET_SIZE + +#define CDC_DATA_FS_IN_PACKET_SIZE CDC_DATA_FS_MAX_PACKET_SIZE +#define CDC_DATA_FS_OUT_PACKET_SIZE CDC_DATA_FS_MAX_PACKET_SIZE + +/*---------------------------------------------------------------------*/ +/* CDC definitions */ +/*---------------------------------------------------------------------*/ + +#define CDC_SEND_ENCAPSULATED_COMMAND 0x00 +#define CDC_GET_ENCAPSULATED_RESPONSE 0x01 +#define CDC_SET_COMM_FEATURE 0x02 +#define CDC_GET_COMM_FEATURE 0x03 +#define CDC_CLEAR_COMM_FEATURE 0x04 +#define CDC_SET_LINE_CODING 0x20 +#define CDC_GET_LINE_CODING 0x21 +#define CDC_SET_CONTROL_LINE_STATE 0x22 +#define CDC_SEND_BREAK 0x23 + +/** + * @} + */ + + +/** @defgroup USBD_CORE_Exported_TypesDefinitions + * @{ + */ + +/** + * @} + */ +typedef struct +{ + uint32_t bitrate; + uint8_t format; + uint8_t paritytype; + uint8_t datatype; +}USBD_CDC_LineCodingTypeDef; + +typedef struct _USBD_CDC_Itf +{ + int8_t (* Init) (void); + int8_t (* DeInit) (void); + int8_t (* Control) (uint8_t, uint8_t * , uint16_t); + int8_t (* Receive) (uint8_t *, uint32_t *); + +}USBD_CDC_ItfTypeDef; + + +typedef struct +{ + uint32_t data[CDC_DATA_HS_MAX_PACKET_SIZE/4]; /* Force 32bits alignment */ + uint8_t CmdOpCode; + uint8_t CmdLength; + uint8_t *RxBuffer; + uint8_t *TxBuffer; + uint32_t RxLength; + uint32_t TxLength; + + __IO uint32_t TxState; + __IO uint32_t RxState; +} +USBD_CDC_HandleTypeDef; + + + +/** @defgroup USBD_CORE_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_CORE_Exported_Variables + * @{ + */ + +extern USBD_ClassTypeDef USBD_CDC; +#define USBD_CDC_CLASS &USBD_CDC +/** + * @} + */ + +/** @defgroup USB_CORE_Exported_Functions + * @{ + */ +uint8_t USBD_CDC_RegisterInterface (USBD_HandleTypeDef *pdev, + USBD_CDC_ItfTypeDef *fops); + +uint8_t USBD_CDC_SetTxBuffer (USBD_HandleTypeDef *pdev, + uint8_t *pbuff, + uint16_t length); + +uint8_t USBD_CDC_SetRxBuffer (USBD_HandleTypeDef *pdev, + uint8_t *pbuff); + +uint8_t USBD_CDC_ReceivePacket (USBD_HandleTypeDef *pdev); + +uint8_t USBD_CDC_TransmitPacket (USBD_HandleTypeDef *pdev); +/** + * @} + */ + +#endif // __USB_CDC_CORE_H_ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32_USB_Device_Library/Class/CDC/usbd_cdc_if_template.c b/libraries/STM32_USB_Device_Library/Class/CDC/usbd_cdc_if_template.c new file mode 100644 --- /dev/null +++ b/libraries/STM32_USB_Device_Library/Class/CDC/usbd_cdc_if_template.c @@ -0,0 +1,225 @@ +/** + ****************************************************************************** + * @file usbd_cdc_if_template.c + * @author MCD Application Team + * @version V2.2.0 + * @date 13-June-2014 + * @brief Generic media access Layer. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_cdc_if_template.h" + +/** @addtogroup STM32_USB_DEVICE_LIBRARY + * @{ + */ + + +/** @defgroup USBD_CDC + * @brief usbd core module + * @{ + */ + +/** @defgroup USBD_CDC_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_CDC_Private_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_CDC_Private_Macros + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_CDC_Private_FunctionPrototypes + * @{ + */ + +static int8_t TEMPLATE_Init (void); +static int8_t TEMPLATE_DeInit (void); +static int8_t TEMPLATE_Control (uint8_t cmd, uint8_t* pbuf, uint16_t length); +static int8_t TEMPLATE_Receive (uint8_t* pbuf, uint32_t *Len); + +USBD_CDC_ItfTypeDef USBD_CDC_Template_fops = +{ + TEMPLATE_Init, + TEMPLATE_DeInit, + TEMPLATE_Control, + TEMPLATE_Receive +}; + +USBD_CDC_LineCodingTypeDef linecoding = + { + 115200, /* baud rate*/ + 0x00, /* stop bits-1*/ + 0x00, /* parity - none*/ + 0x08 /* nb. of bits 8*/ + }; + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief TEMPLATE_Init + * Initializes the CDC media low layer + * @param None + * @retval Result of the opeartion: USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t TEMPLATE_Init(void) +{ + /* + Add your initialization code here + */ + return (0); +} + +/** + * @brief TEMPLATE_DeInit + * DeInitializes the CDC media low layer + * @param None + * @retval Result of the opeartion: USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t TEMPLATE_DeInit(void) +{ + /* + Add your deinitialization code here + */ + return (0); +} + + +/** + * @brief TEMPLATE_Control + * Manage the CDC class requests + * @param Cmd: Command code + * @param Buf: Buffer containing command data (request parameters) + * @param Len: Number of data to be sent (in bytes) + * @retval Result of the opeartion: USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t TEMPLATE_Control (uint8_t cmd, uint8_t* pbuf, uint16_t length) +{ + switch (cmd) + { + case CDC_SEND_ENCAPSULATED_COMMAND: + /* Add your code here */ + break; + + case CDC_GET_ENCAPSULATED_RESPONSE: + /* Add your code here */ + break; + + case CDC_SET_COMM_FEATURE: + /* Add your code here */ + break; + + case CDC_GET_COMM_FEATURE: + /* Add your code here */ + break; + + case CDC_CLEAR_COMM_FEATURE: + /* Add your code here */ + break; + + case CDC_SET_LINE_CODING: + linecoding.bitrate = (uint32_t)(pbuf[0] | (pbuf[1] << 8) |\ + (pbuf[2] << 16) | (pbuf[3] << 24)); + linecoding.format = pbuf[4]; + linecoding.paritytype = pbuf[5]; + linecoding.datatype = pbuf[6]; + + /* Add your code here */ + break; + + case CDC_GET_LINE_CODING: + pbuf[0] = (uint8_t)(linecoding.bitrate); + pbuf[1] = (uint8_t)(linecoding.bitrate >> 8); + pbuf[2] = (uint8_t)(linecoding.bitrate >> 16); + pbuf[3] = (uint8_t)(linecoding.bitrate >> 24); + pbuf[4] = linecoding.format; + pbuf[5] = linecoding.paritytype; + pbuf[6] = linecoding.datatype; + + /* Add your code here */ + break; + + case CDC_SET_CONTROL_LINE_STATE: + /* Add your code here */ + break; + + case CDC_SEND_BREAK: + /* Add your code here */ + break; + + default: + break; + } + + return (0); +} + +/** + * @brief TEMPLATE_DataRx + * Data received over USB OUT endpoint are sent over CDC interface + * through this function. + * + * @note + * This function will block any OUT packet reception on USB endpoint + * untill exiting this function. If you exit this function before transfer + * is complete on CDC interface (ie. using DMA controller) it will result + * in receiving more data while previous ones are still not sent. + * + * @param Buf: Buffer of data to be received + * @param Len: Number of data received (in bytes) + * @retval Result of the opeartion: USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t TEMPLATE_Receive (uint8_t* Buf, uint32_t *Len) +{ + + return (0); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/STM32_USB_Device_Library/Class/CDC/usbd_cdc_if_template.h b/libraries/STM32_USB_Device_Library/Class/CDC/usbd_cdc_if_template.h new file mode 100644 --- /dev/null +++ b/libraries/STM32_USB_Device_Library/Class/CDC/usbd_cdc_if_template.h @@ -0,0 +1,44 @@ +/** + ****************************************************************************** + * @file usbd_cdc_if_template.h + * @author MCD Application Team + * @version V2.2.0 + * @date 13-June-2014 + * @brief Header for dfu_mal.c file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_CDC_IF_TEMPLATE_H +#define __USBD_CDC_IF_TEMPLATE_H + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_cdc.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +extern USBD_CDC_ItfTypeDef USBD_CDC_Template_fops; + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +#endif /* __USBD_CDC_IF_TEMPLATE_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32_USB_Device_Library/Core/usbd_conf_template.c b/libraries/STM32_USB_Device_Library/Core/usbd_conf_template.c new file mode 100644 --- /dev/null +++ b/libraries/STM32_USB_Device_Library/Core/usbd_conf_template.c @@ -0,0 +1,212 @@ +/** + ****************************************************************************** + * @file usbd_conf_template.c + * @author MCD Application Team + * @version V2.2.0 + * @date 13-June-2014 + * @brief USB Device configuration and interface file + * This template should be copied to the user folder, renamed and customized + * following user needs. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_core.h" +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** + * @brief Initializes the Low Level portion of the Device driver. + * @param pdev: Device handle + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev) +{ + return USBD_OK; +} + +/** + * @brief De-Initializes the Low Level portion of the Device driver. + * @param pdev: Device handle + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_LL_DeInit(USBD_HandleTypeDef *pdev) +{ + return USBD_OK; +} + +/** + * @brief Starts the Low Level portion of the Device driver. + * @param pdev: Device handle + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev) +{ + return USBD_OK; +} + +/** + * @brief Stops the Low Level portion of the Device driver. + * @param pdev: Device handle + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_LL_Stop(USBD_HandleTypeDef *pdev) +{ + return USBD_OK; +} + +/** + * @brief Opens an endpoint of the Low Level Driver. + * @param pdev: Device handle + * @param ep_addr: Endpoint Number + * @param ep_type: Endpoint Type + * @param ep_mps: Endpoint Max Packet Size + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, + uint8_t ep_addr, + uint8_t ep_type, + uint16_t ep_mps) +{ + return USBD_OK; +} + +/** + * @brief Closes an endpoint of the Low Level Driver. + * @param pdev: Device handle + * @param ep_addr: Endpoint Number + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + return USBD_OK; +} + +/** + * @brief Flushes an endpoint of the Low Level Driver. + * @param pdev: Device handle + * @param ep_addr: Endpoint Number + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_LL_FlushEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + return USBD_OK; +} + +/** + * @brief Sets a Stall condition on an endpoint of the Low Level Driver. + * @param pdev: Device handle + * @param ep_addr: Endpoint Number + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + return USBD_OK; +} + +/** + * @brief Clears a Stall condition on an endpoint of the Low Level Driver. + * @param pdev: Device handle + * @param ep_addr: Endpoint Number + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + return USBD_OK; +} + +/** + * @brief Returns Stall condition. + * @param pdev: Device handle + * @param ep_addr: Endpoint Number + * @retval Stall (1: Yes, 0: No) + */ +uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + return 0; +} + +/** + * @brief Assigns a USB address to the device. + * @param pdev: Device handle + * @param ep_addr: Endpoint Number + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr) +{ + return USBD_OK; +} + +/** + * @brief Transmits data over an endpoint. + * @param pdev: Device handle + * @param ep_addr: Endpoint Number + * @param pbuf: Pointer to data to be sent + * @param size: Data size + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, + uint8_t ep_addr, + uint8_t *pbuf, + uint16_t size) +{ + return USBD_OK; +} + +/** + * @brief Prepares an endpoint for reception. + * @param pdev: Device handle + * @param ep_addr: Endpoint Number + * @param pbuf: Pointer to data to be received + * @param size: Data size + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, + uint8_t ep_addr, + uint8_t *pbuf, + uint16_t size) +{ + return USBD_OK; +} + +/** + * @brief Returns the last transfered packet size. + * @param pdev: Device handle + * @param ep_addr: Endpoint Number + * @retval Recived Data Size + */ +uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + return 0; +} + +/** + * @brief Delays routine for the USB Device Library. + * @param Delay: Delay in ms + * @retval None + */ +void USBD_LL_Delay(uint32_t Delay) +{ +} +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/STM32_USB_Device_Library/Core/usbd_conf_template.h b/libraries/STM32_USB_Device_Library/Core/usbd_conf_template.h new file mode 100644 --- /dev/null +++ b/libraries/STM32_USB_Device_Library/Core/usbd_conf_template.h @@ -0,0 +1,163 @@ +/** + ****************************************************************************** + * @file usbd_conf_template.h + * @author MCD Application Team + * @version V2.2.0 + * @date 13-June-2014 + * @brief USB device low level driver configuration + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_CONF__H__ +#define __USBD_CONF__H__ + +#include "stm32fxxx.h" /* replace 'stm32xxx' with your HAL driver header filename, ex: stm32f4xx.h */ +#include +#include +#include + +/* Includes ------------------------------------------------------------------*/ + +/** @addtogroup STM32_USB_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USBD_CONF + * @brief USB device low level driver configuration file + * @{ + */ + +/** @defgroup USBD_CONF_Exported_Defines + * @{ + */ + +#define USBD_MAX_NUM_INTERFACES 1 +#define USBD_MAX_NUM_CONFIGURATION 1 +#define USBD_MAX_STR_DESC_SIZ 0x100 +#define USBD_SUPPORT_USER_STRING 0 +#define USBD_SELF_POWERED 1 +#define USBD_DEBUG_LEVEL 2 + +/* MSC Class Config */ +#define MSC_MEDIA_PACKET 8192 + +/* CDC Class Config */ +#define USBD_CDC_INTERVAL 2000 + + /* DFU Class Config */ +#define USBD_DFU_MAX_ITF_NUM 1 +#define USBD_DFU_XFERS_IZE 1024 + + /* AUDIO Class Config */ +#define USBD_AUDIO_FREQ 22100 + +/** @defgroup USBD_Exported_Macros + * @{ + */ + + /* Memory management macros */ +#define USBD_malloc malloc +#define USBD_free free +#define USBD_memset memset +#define USBD_memcpy memcpy + + /* DEBUG macros */ + + +#if (USBD_DEBUG_LEVEL > 0) +#define USBD_UsrLog(...) printf(__VA_ARGS__);\ + printf("\n"); +#else +#define USBD_UsrLog(...) +#endif + + +#if (USBD_DEBUG_LEVEL > 1) + +#define USBD_ErrLog(...) printf("ERROR: ") ;\ + printf(__VA_ARGS__);\ + printf("\n"); +#else +#define USBD_ErrLog(...) +#endif + + +#if (USBD_DEBUG_LEVEL > 2) +#define USBD_DbgLog(...) printf("DEBUG : ") ;\ + printf(__VA_ARGS__);\ + printf("\n"); +#else +#define USBD_DbgLog(...) +#endif + +/** + * @} + */ + + + +/** + * @} + */ + + +/** @defgroup USBD_CONF_Exported_Types + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_CONF_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup USBD_CONF_Exported_Variables + * @{ + */ +/** + * @} + */ + +/** @defgroup USBD_CONF_Exported_FunctionsPrototype + * @{ + */ +/** + * @} + */ + + +#endif //__USBD_CONF__H__ + + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/STM32_USB_Device_Library/Core/usbd_core.c b/libraries/STM32_USB_Device_Library/Core/usbd_core.c new file mode 100644 --- /dev/null +++ b/libraries/STM32_USB_Device_Library/Core/usbd_core.c @@ -0,0 +1,553 @@ +/** + ****************************************************************************** + * @file usbd_core.c + * @author MCD Application Team + * @version V2.2.0 + * @date 13-June-2014 + * @brief This file provides all the USBD core functions. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_core.h" + +/** @addtogroup STM32_USBD_DEVICE_LIBRARY +* @{ +*/ + + +/** @defgroup USBD_CORE +* @brief usbd core module +* @{ +*/ + +/** @defgroup USBD_CORE_Private_TypesDefinitions +* @{ +*/ +/** +* @} +*/ + + +/** @defgroup USBD_CORE_Private_Defines +* @{ +*/ + +/** +* @} +*/ + + +/** @defgroup USBD_CORE_Private_Macros +* @{ +*/ +/** +* @} +*/ + + + + +/** @defgroup USBD_CORE_Private_FunctionPrototypes +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup USBD_CORE_Private_Variables +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup USBD_CORE_Private_Functions +* @{ +*/ + +/** +* @brief USBD_Init +* Initailizes the device stack and load the class driver +* @param pdev: device instance +* @param pdesc: Descriptor structure address +* @param id: Low level core index +* @retval None +*/ +USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id) +{ + /* Check whether the USB Host handle is valid */ + if(pdev == NULL) + { + USBD_ErrLog("Invalid Device handle"); + return USBD_FAIL; + } + + /* Unlink previous class*/ + if(pdev->pClass != NULL) + { + pdev->pClass = NULL; + } + + /* Assign USBD Descriptors */ + if(pdesc != NULL) + { + pdev->pDesc = pdesc; + } + + /* Set Device initial State */ + pdev->dev_state = USBD_STATE_DEFAULT; + pdev->id = id; + /* Initialize low level driver */ + USBD_LL_Init(pdev); + + return USBD_OK; +} + +/** +* @brief USBD_DeInit +* Re-Initialize th device library +* @param pdev: device instance +* @retval status: status +*/ +USBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev) +{ + /* Set Default State */ + pdev->dev_state = USBD_STATE_DEFAULT; + + /* Free Class Resources */ + pdev->pClass->DeInit(pdev, pdev->dev_config); + + /* Stop the low level driver */ + USBD_LL_Stop(pdev); + + /* Initialize low level driver */ + USBD_LL_DeInit(pdev); + + return USBD_OK; +} + + +/** + * @brief USBD_RegisterClass + * Link class driver to Device Core. + * @param pDevice : Device Handle + * @param pclass: Class handle + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass) +{ + USBD_StatusTypeDef status = USBD_OK; + if(pclass != 0) + { + /* link the class tgo the USB Device handle */ + pdev->pClass = pclass; + status = USBD_OK; + } + else + { + USBD_ErrLog("Invalid Class handle"); + status = USBD_FAIL; + } + + return status; +} + +/** + * @brief USBD_Start + * Start the USB Device Core. + * @param pdev: Device Handle + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_Start (USBD_HandleTypeDef *pdev) +{ + + /* Start the low level driver */ + USBD_LL_Start(pdev); + + return USBD_OK; +} + +/** + * @brief USBD_Stop + * Stop the USB Device Core. + * @param pdev: Device Handle + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_Stop (USBD_HandleTypeDef *pdev) +{ + /* Free Class Resources */ + pdev->pClass->DeInit(pdev, pdev->dev_config); + + /* Stop the low level driver */ + USBD_LL_Stop(pdev); + + return USBD_OK; +} + +/** +* @brief USBD_RunTestMode +* Launch test mode process +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_RunTestMode (USBD_HandleTypeDef *pdev) +{ + return USBD_OK; +} + + +/** +* @brief USBD_SetClassConfig +* Configure device and start the interface +* @param pdev: device instance +* @param cfgidx: configuration index +* @retval status +*/ + +USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) +{ + USBD_StatusTypeDef ret = USBD_FAIL; + + if(pdev->pClass != NULL) + { + /* Set configuration and Start the Class*/ + if(pdev->pClass->Init(pdev, cfgidx) == 0) + { + ret = USBD_OK; + } + } + return ret; +} + +/** +* @brief USBD_ClrClassConfig +* Clear current configuration +* @param pdev: device instance +* @param cfgidx: configuration index +* @retval status: USBD_StatusTypeDef +*/ +USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) +{ + /* Clear configuration and Deinitialize the Class process*/ + pdev->pClass->DeInit(pdev, cfgidx); + return USBD_OK; +} + + +/** +* @brief USBD_SetupStage +* Handle the setup stage +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup) +{ + + USBD_ParseSetupRequest(&pdev->request, psetup); + + pdev->ep0_state = USBD_EP0_SETUP; + pdev->ep0_data_len = pdev->request.wLength; + + switch (pdev->request.bmRequest & 0x1F) + { + case USB_REQ_RECIPIENT_DEVICE: + USBD_StdDevReq (pdev, &pdev->request); + break; + + case USB_REQ_RECIPIENT_INTERFACE: + USBD_StdItfReq(pdev, &pdev->request); + break; + + case USB_REQ_RECIPIENT_ENDPOINT: + USBD_StdEPReq(pdev, &pdev->request); + break; + + default: + USBD_LL_StallEP(pdev , pdev->request.bmRequest & 0x80); + break; + } + return USBD_OK; +} + +/** +* @brief USBD_DataOutStage +* Handle data OUT stage +* @param pdev: device instance +* @param epnum: endpoint index +* @retval status +*/ +USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev , uint8_t epnum, uint8_t *pdata) +{ + USBD_EndpointTypeDef *pep; + + if(epnum == 0) + { + pep = &pdev->ep_out[0]; + + if ( pdev->ep0_state == USBD_EP0_DATA_OUT) + { + if(pep->rem_length > pep->maxpacket) + { + pep->rem_length -= pep->maxpacket; + + USBD_CtlContinueRx (pdev, + pdata, + MIN(pep->rem_length ,pep->maxpacket)); + } + else + { + if((pdev->pClass->EP0_RxReady != NULL)&& + (pdev->dev_state == USBD_STATE_CONFIGURED)) + { + pdev->pClass->EP0_RxReady(pdev); + } + USBD_CtlSendStatus(pdev); + } + } + } + else if((pdev->pClass->DataOut != NULL)&& + (pdev->dev_state == USBD_STATE_CONFIGURED)) + { + pdev->pClass->DataOut(pdev, epnum); + } + return USBD_OK; +} + +/** +* @brief USBD_DataInStage +* Handle data in stage +* @param pdev: device instance +* @param epnum: endpoint index +* @retval status +*/ +USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev ,uint8_t epnum, uint8_t *pdata) +{ + USBD_EndpointTypeDef *pep; + + if(epnum == 0) + { + pep = &pdev->ep_in[0]; + + if ( pdev->ep0_state == USBD_EP0_DATA_IN) + { + if(pep->rem_length > pep->maxpacket) + { + pep->rem_length -= pep->maxpacket; + + USBD_CtlContinueSendData (pdev, + pdata, + pep->rem_length); + } + else + { /* last packet is MPS multiple, so send ZLP packet */ + if((pep->total_length % pep->maxpacket == 0) && + (pep->total_length >= pep->maxpacket) && + (pep->total_length < pdev->ep0_data_len )) + { + + USBD_CtlContinueSendData(pdev , NULL, 0); + pdev->ep0_data_len = 0; + } + else + { + if((pdev->pClass->EP0_TxSent != NULL)&& + (pdev->dev_state == USBD_STATE_CONFIGURED)) + { + pdev->pClass->EP0_TxSent(pdev); + } + USBD_CtlReceiveStatus(pdev); + } + } + } + if (pdev->dev_test_mode == 1) + { + USBD_RunTestMode(pdev); + pdev->dev_test_mode = 0; + } + } + else if((pdev->pClass->DataIn != NULL)&& + (pdev->dev_state == USBD_STATE_CONFIGURED)) + { + pdev->pClass->DataIn(pdev, epnum); + } + return USBD_OK; +} + +/** +* @brief USBD_LL_Reset +* Handle Reset event +* @param pdev: device instance +* @retval status +*/ + +USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev) +{ + /* Open EP0 OUT */ + USBD_LL_OpenEP(pdev, + 0x00, + USBD_EP_TYPE_CTRL, + USB_MAX_EP0_SIZE); + + pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE; + + /* Open EP0 IN */ + USBD_LL_OpenEP(pdev, + 0x80, + USBD_EP_TYPE_CTRL, + USB_MAX_EP0_SIZE); + + pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE; + /* Upon Reset call usr call back */ + pdev->dev_state = USBD_STATE_DEFAULT; + + if (pdev->pClassData) + pdev->pClass->DeInit(pdev, pdev->dev_config); + + + return USBD_OK; +} + + + + +/** +* @brief USBD_LL_Reset +* Handle Reset event +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_SpeedTypeDef speed) +{ + pdev->dev_speed = speed; + return USBD_OK; +} + +/** +* @brief USBD_Suspend +* Handle Suspend event +* @param pdev: device instance +* @retval status +*/ + +USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev) +{ + pdev->dev_old_state = pdev->dev_state; + pdev->dev_state = USBD_STATE_SUSPENDED; + return USBD_OK; +} + +/** +* @brief USBD_Resume +* Handle Resume event +* @param pdev: device instance +* @retval status +*/ + +USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev) +{ + pdev->dev_state = pdev->dev_old_state; + return USBD_OK; +} + +/** +* @brief USBD_SOF +* Handle SOF event +* @param pdev: device instance +* @retval status +*/ + +USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev) +{ + if(pdev->dev_state == USBD_STATE_CONFIGURED) + { + if(pdev->pClass->SOF != NULL) + { + pdev->pClass->SOF(pdev); + } + } + return USBD_OK; +} + +/** +* @brief USBD_IsoINIncomplete +* Handle iso in incomplete event +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) +{ + return USBD_OK; +} + +/** +* @brief USBD_IsoOUTIncomplete +* Handle iso out incomplete event +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) +{ + return USBD_OK; +} + +/** +* @brief USBD_DevConnected +* Handle device connection event +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev) +{ + return USBD_OK; +} + +/** +* @brief USBD_DevDisconnected +* Handle device disconnection event +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev) +{ + /* Free Class Resources */ + pdev->dev_state = USBD_STATE_DEFAULT; + pdev->pClass->DeInit(pdev, pdev->dev_config); + + return USBD_OK; +} +/** +* @} +*/ + + +/** +* @} +*/ + + +/** +* @} +*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/STM32_USB_Device_Library/Core/usbd_core.h b/libraries/STM32_USB_Device_Library/Core/usbd_core.h new file mode 100644 --- /dev/null +++ b/libraries/STM32_USB_Device_Library/Core/usbd_core.h @@ -0,0 +1,159 @@ +/** + ****************************************************************************** + * @file usbd_core.h + * @author MCD Application Team + * @version V2.2.0 + * @date 13-June-2014 + * @brief Header file for usbd_core.c + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_CORE_H +#define __USBD_CORE_H + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_conf.h" +#include "usbd_def.h" +#include "usbd_ioreq.h" +#include "usbd_ctlreq.h" + +/** @addtogroup STM32_USB_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USBD_CORE + * @brief This file is the Header file for usbd_core.c file + * @{ + */ + + +/** @defgroup USBD_CORE_Exported_Defines + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_CORE_Exported_TypesDefinitions + * @{ + */ + + +/** + * @} + */ + + + +/** @defgroup USBD_CORE_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_CORE_Exported_Variables + * @{ + */ +#define USBD_SOF USBD_LL_SOF +/** + * @} + */ + +/** @defgroup USBD_CORE_Exported_FunctionsPrototype + * @{ + */ +USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id); +USBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_Start (USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_Stop (USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass); + +USBD_StatusTypeDef USBD_RunTestMode (USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx); +USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx); + +USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup); +USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev , uint8_t epnum, uint8_t *pdata); +USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev , uint8_t epnum, uint8_t *pdata); + +USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_SpeedTypeDef speed); +USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev); + +USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum); +USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum); + +USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev); + +/* USBD Low Level Driver */ +USBD_StatusTypeDef USBD_LL_Init (USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_DeInit (USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_Stop (USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_OpenEP (USBD_HandleTypeDef *pdev, + uint8_t ep_addr, + uint8_t ep_type, + uint16_t ep_mps); + +USBD_StatusTypeDef USBD_LL_CloseEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr); +USBD_StatusTypeDef USBD_LL_FlushEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr); +USBD_StatusTypeDef USBD_LL_StallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr); +USBD_StatusTypeDef USBD_LL_ClearStallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr); +uint8_t USBD_LL_IsStallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr); +USBD_StatusTypeDef USBD_LL_SetUSBAddress (USBD_HandleTypeDef *pdev, uint8_t dev_addr); +USBD_StatusTypeDef USBD_LL_Transmit (USBD_HandleTypeDef *pdev, + uint8_t ep_addr, + uint8_t *pbuf, + uint16_t size); + +USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, + uint8_t ep_addr, + uint8_t *pbuf, + uint16_t size); + +uint32_t USBD_LL_GetRxDataSize (USBD_HandleTypeDef *pdev, uint8_t ep_addr); +void USBD_LL_Delay (uint32_t Delay); + +/** + * @} + */ + +#endif /* __USBD_CORE_H */ + +/** + * @} + */ + +/** +* @} +*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + + + diff --git a/libraries/STM32_USB_Device_Library/Core/usbd_ctlreq.c b/libraries/STM32_USB_Device_Library/Core/usbd_ctlreq.c new file mode 100644 --- /dev/null +++ b/libraries/STM32_USB_Device_Library/Core/usbd_ctlreq.c @@ -0,0 +1,769 @@ +/** + ****************************************************************************** + * @file usbd_req.c + * @author MCD Application Team + * @version V2.2.0 + * @date 13-June-2014 + * @brief This file provides the standard USB requests following chapter 9. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_ctlreq.h" +#include "usbd_ioreq.h" + + +/** @addtogroup STM32_USBD_STATE_DEVICE_LIBRARY + * @{ + */ + + +/** @defgroup USBD_REQ + * @brief USB standard requests module + * @{ + */ + +/** @defgroup USBD_REQ_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_REQ_Private_Defines + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_REQ_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_REQ_Private_Variables + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_REQ_Private_FunctionPrototypes + * @{ + */ +static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev , + USBD_SetupReqTypedef *req); + +static void USBD_SetAddress(USBD_HandleTypeDef *pdev , + USBD_SetupReqTypedef *req); + +static void USBD_SetConfig(USBD_HandleTypeDef *pdev , + USBD_SetupReqTypedef *req); + +static void USBD_GetConfig(USBD_HandleTypeDef *pdev , + USBD_SetupReqTypedef *req); + +static void USBD_GetStatus(USBD_HandleTypeDef *pdev , + USBD_SetupReqTypedef *req); + +static void USBD_SetFeature(USBD_HandleTypeDef *pdev , + USBD_SetupReqTypedef *req); + +static void USBD_ClrFeature(USBD_HandleTypeDef *pdev , + USBD_SetupReqTypedef *req); + +static uint8_t USBD_GetLen(uint8_t *buf); + +/** + * @} + */ + + +/** @defgroup USBD_REQ_Private_Functions + * @{ + */ + + +/** +* @brief USBD_StdDevReq +* Handle standard usb device requests +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +USBD_StatusTypeDef USBD_StdDevReq (USBD_HandleTypeDef *pdev , USBD_SetupReqTypedef *req) +{ + USBD_StatusTypeDef ret = USBD_OK; + + switch (req->bRequest) + { + case USB_REQ_GET_DESCRIPTOR: + + USBD_GetDescriptor (pdev, req) ; + break; + + case USB_REQ_SET_ADDRESS: + USBD_SetAddress(pdev, req); + break; + + case USB_REQ_SET_CONFIGURATION: + USBD_SetConfig (pdev , req); + break; + + case USB_REQ_GET_CONFIGURATION: + USBD_GetConfig (pdev , req); + break; + + case USB_REQ_GET_STATUS: + USBD_GetStatus (pdev , req); + break; + + + case USB_REQ_SET_FEATURE: + USBD_SetFeature (pdev , req); + break; + + case USB_REQ_CLEAR_FEATURE: + USBD_ClrFeature (pdev , req); + break; + + default: + USBD_CtlError(pdev , req); + break; + } + + return ret; +} + +/** +* @brief USBD_StdItfReq +* Handle standard usb interface requests +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +USBD_StatusTypeDef USBD_StdItfReq (USBD_HandleTypeDef *pdev , USBD_SetupReqTypedef *req) +{ + USBD_StatusTypeDef ret = USBD_OK; + + switch (pdev->dev_state) + { + case USBD_STATE_CONFIGURED: + + if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES) + { + pdev->pClass->Setup (pdev, req); + + if((req->wLength == 0)&& (ret == USBD_OK)) + { + USBD_CtlSendStatus(pdev); + } + } + else + { + USBD_CtlError(pdev , req); + } + break; + + default: + USBD_CtlError(pdev , req); + break; + } + return USBD_OK; +} + +/** +* @brief USBD_StdEPReq +* Handle standard usb endpoint requests +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +USBD_StatusTypeDef USBD_StdEPReq (USBD_HandleTypeDef *pdev , USBD_SetupReqTypedef *req) +{ + + uint8_t ep_addr; + USBD_StatusTypeDef ret = USBD_OK; + USBD_EndpointTypeDef *pep; + ep_addr = LOBYTE(req->wIndex); + + switch (req->bRequest) + { + + case USB_REQ_SET_FEATURE : + + switch (pdev->dev_state) + { + case USBD_STATE_ADDRESSED: + if ((ep_addr != 0x00) && (ep_addr != 0x80)) + { + USBD_LL_StallEP(pdev , ep_addr); + } + break; + + case USBD_STATE_CONFIGURED: + if (req->wValue == USB_FEATURE_EP_HALT) + { + if ((ep_addr != 0x00) && (ep_addr != 0x80)) + { + USBD_LL_StallEP(pdev , ep_addr); + + } + } + pdev->pClass->Setup (pdev, req); + USBD_CtlSendStatus(pdev); + + break; + + default: + USBD_CtlError(pdev , req); + break; + } + break; + + case USB_REQ_CLEAR_FEATURE : + + switch (pdev->dev_state) + { + case USBD_STATE_ADDRESSED: + if ((ep_addr != 0x00) && (ep_addr != 0x80)) + { + USBD_LL_StallEP(pdev , ep_addr); + } + break; + + case USBD_STATE_CONFIGURED: + if (req->wValue == USB_FEATURE_EP_HALT) + { + if ((ep_addr & 0x7F) != 0x00) + { + USBD_LL_ClearStallEP(pdev , ep_addr); + pdev->pClass->Setup (pdev, req); + } + USBD_CtlSendStatus(pdev); + } + break; + + default: + USBD_CtlError(pdev , req); + break; + } + break; + + case USB_REQ_GET_STATUS: + switch (pdev->dev_state) + { + case USBD_STATE_ADDRESSED: + if ((ep_addr & 0x7F) != 0x00) + { + USBD_LL_StallEP(pdev , ep_addr); + } + break; + + case USBD_STATE_CONFIGURED: + pep = ((ep_addr & 0x80) == 0x80) ? &pdev->ep_in[ep_addr & 0x7F]:\ + &pdev->ep_out[ep_addr & 0x7F]; + if(USBD_LL_IsStallEP(pdev, ep_addr)) + { + pep->status = 0x0001; + } + else + { + pep->status = 0x0000; + } + + USBD_CtlSendData (pdev, + (uint8_t *)&pep->status, + 2); + break; + + default: + USBD_CtlError(pdev , req); + break; + } + break; + + default: + break; + } + return ret; +} +/** +* @brief USBD_GetDescriptor +* Handle Get Descriptor requests +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev , + USBD_SetupReqTypedef *req) +{ + uint16_t len; + uint8_t *pbuf; + + + switch (req->wValue >> 8) + { + case USB_DESC_TYPE_DEVICE: + pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len); + break; + + case USB_DESC_TYPE_CONFIGURATION: + if(pdev->dev_speed == USBD_SPEED_HIGH ) + { + pbuf = (uint8_t *)pdev->pClass->GetHSConfigDescriptor(&len); + pbuf[1] = USB_DESC_TYPE_CONFIGURATION; + } + else + { + pbuf = (uint8_t *)pdev->pClass->GetFSConfigDescriptor(&len); + pbuf[1] = USB_DESC_TYPE_CONFIGURATION; + } + break; + + case USB_DESC_TYPE_STRING: + switch ((uint8_t)(req->wValue)) + { + case USBD_IDX_LANGID_STR: + pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len); + break; + + case USBD_IDX_MFC_STR: + pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len); + break; + + case USBD_IDX_PRODUCT_STR: + pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len); + break; + + case USBD_IDX_SERIAL_STR: + pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len); + break; + + case USBD_IDX_CONFIG_STR: + pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len); + break; + + case USBD_IDX_INTERFACE_STR: + pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len); + break; + + default: +#if (USBD_SUPPORT_USER_STRING == 1) + pbuf = pdev->pClass->GetUsrStrDescriptor(pdev, (req->wValue) , &len); + break; +#else + USBD_CtlError(pdev , req); + return; +#endif + } + break; + case USB_DESC_TYPE_DEVICE_QUALIFIER: + + if(pdev->dev_speed == USBD_SPEED_HIGH ) + { + pbuf = (uint8_t *)pdev->pClass->GetDeviceQualifierDescriptor(&len); + break; + } + else + { + USBD_CtlError(pdev , req); + return; + } + + case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION: + if(pdev->dev_speed == USBD_SPEED_HIGH ) + { + pbuf = (uint8_t *)pdev->pClass->GetOtherSpeedConfigDescriptor(&len); + pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION; + break; + } + else + { + USBD_CtlError(pdev , req); + return; + } + + default: + USBD_CtlError(pdev , req); + return; + } + + if((len != 0)&& (req->wLength != 0)) + { + + len = MIN(len , req->wLength); + + USBD_CtlSendData (pdev, + pbuf, + len); + } + +} + +/** +* @brief USBD_SetAddress +* Set device address +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_SetAddress(USBD_HandleTypeDef *pdev , + USBD_SetupReqTypedef *req) +{ + uint8_t dev_addr; + + if ((req->wIndex == 0) && (req->wLength == 0)) + { + dev_addr = (uint8_t)(req->wValue) & 0x7F; + + if (pdev->dev_state == USBD_STATE_CONFIGURED) + { + USBD_CtlError(pdev , req); + } + else + { + pdev->dev_address = dev_addr; + USBD_LL_SetUSBAddress(pdev, dev_addr); + USBD_CtlSendStatus(pdev); + + if (dev_addr != 0) + { + pdev->dev_state = USBD_STATE_ADDRESSED; + } + else + { + pdev->dev_state = USBD_STATE_DEFAULT; + } + } + } + else + { + USBD_CtlError(pdev , req); + } +} + +/** +* @brief USBD_SetConfig +* Handle Set device configuration request +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_SetConfig(USBD_HandleTypeDef *pdev , + USBD_SetupReqTypedef *req) +{ + + static uint8_t cfgidx; + + cfgidx = (uint8_t)(req->wValue); + + if (cfgidx > USBD_MAX_NUM_CONFIGURATION ) + { + USBD_CtlError(pdev , req); + } + else + { + switch (pdev->dev_state) + { + case USBD_STATE_ADDRESSED: + if (cfgidx) + { + pdev->dev_config = cfgidx; + pdev->dev_state = USBD_STATE_CONFIGURED; + if(USBD_SetClassConfig(pdev , cfgidx) == USBD_FAIL) + { + USBD_CtlError(pdev , req); + return; + } + USBD_CtlSendStatus(pdev); + } + else + { + USBD_CtlSendStatus(pdev); + } + break; + + case USBD_STATE_CONFIGURED: + if (cfgidx == 0) + { + pdev->dev_state = USBD_STATE_ADDRESSED; + pdev->dev_config = cfgidx; + USBD_ClrClassConfig(pdev , cfgidx); + USBD_CtlSendStatus(pdev); + + } + else if (cfgidx != pdev->dev_config) + { + /* Clear old configuration */ + USBD_ClrClassConfig(pdev , pdev->dev_config); + + /* set new configuration */ + pdev->dev_config = cfgidx; + if(USBD_SetClassConfig(pdev , cfgidx) == USBD_FAIL) + { + USBD_CtlError(pdev , req); + return; + } + USBD_CtlSendStatus(pdev); + } + else + { + USBD_CtlSendStatus(pdev); + } + break; + + default: + USBD_CtlError(pdev , req); + break; + } + } +} + +/** +* @brief USBD_GetConfig +* Handle Get device configuration request +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_GetConfig(USBD_HandleTypeDef *pdev , + USBD_SetupReqTypedef *req) +{ + + if (req->wLength != 1) + { + USBD_CtlError(pdev , req); + } + else + { + switch (pdev->dev_state ) + { + case USBD_STATE_ADDRESSED: + pdev->dev_default_config = 0; + USBD_CtlSendData (pdev, + (uint8_t *)&pdev->dev_default_config, + 1); + break; + + case USBD_STATE_CONFIGURED: + + USBD_CtlSendData (pdev, + (uint8_t *)&pdev->dev_config, + 1); + break; + + default: + USBD_CtlError(pdev , req); + break; + } + } +} + +/** +* @brief USBD_GetStatus +* Handle Get Status request +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_GetStatus(USBD_HandleTypeDef *pdev , + USBD_SetupReqTypedef *req) +{ + + + switch (pdev->dev_state) + { + case USBD_STATE_ADDRESSED: + case USBD_STATE_CONFIGURED: + +#if ( USBD_SELF_POWERED == 1) + pdev->dev_config_status = USB_CONFIG_SELF_POWERED; +#else + pdev->dev_config_status = 0; +#endif + + if (pdev->dev_remote_wakeup) + { + pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP; + } + + USBD_CtlSendData (pdev, + (uint8_t *)& pdev->dev_config_status, + 2); + break; + + default : + USBD_CtlError(pdev , req); + break; + } +} + + +/** +* @brief USBD_SetFeature +* Handle Set device feature request +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_SetFeature(USBD_HandleTypeDef *pdev , + USBD_SetupReqTypedef *req) +{ + + if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) + { + pdev->dev_remote_wakeup = 1; + pdev->pClass->Setup (pdev, req); + USBD_CtlSendStatus(pdev); + } + +} + + +/** +* @brief USBD_ClrFeature +* Handle clear device feature request +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_ClrFeature(USBD_HandleTypeDef *pdev , + USBD_SetupReqTypedef *req) +{ + switch (pdev->dev_state) + { + case USBD_STATE_ADDRESSED: + case USBD_STATE_CONFIGURED: + if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) + { + pdev->dev_remote_wakeup = 0; + pdev->pClass->Setup (pdev, req); + USBD_CtlSendStatus(pdev); + } + break; + + default : + USBD_CtlError(pdev , req); + break; + } +} + +/** +* @brief USBD_ParseSetupRequest +* Copy buffer into setup structure +* @param pdev: device instance +* @param req: usb request +* @retval None +*/ + +void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata) +{ + req->bmRequest = *(uint8_t *) (pdata); + req->bRequest = *(uint8_t *) (pdata + 1); + req->wValue = SWAPBYTE (pdata + 2); + req->wIndex = SWAPBYTE (pdata + 4); + req->wLength = SWAPBYTE (pdata + 6); + +} + +/** +* @brief USBD_CtlError +* Handle USB low level Error +* @param pdev: device instance +* @param req: usb request +* @retval None +*/ + +void USBD_CtlError( USBD_HandleTypeDef *pdev , + USBD_SetupReqTypedef *req) +{ + USBD_LL_StallEP(pdev , 0x80); + USBD_LL_StallEP(pdev , 0); +} + + +/** + * @brief USBD_GetString + * Convert Ascii string into unicode one + * @param desc : descriptor buffer + * @param unicode : Formatted string buffer (unicode) + * @param len : descriptor length + * @retval None + */ +void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len) +{ + uint8_t idx = 0; + + if (desc != NULL) + { + *len = USBD_GetLen(desc) * 2 + 2; + unicode[idx++] = *len; + unicode[idx++] = USB_DESC_TYPE_STRING; + + while (*desc != '\0') + { + unicode[idx++] = *desc++; + unicode[idx++] = 0x00; + } + } +} + +/** + * @brief USBD_GetLen + * return the string length + * @param buf : pointer to the ascii string buffer + * @retval string length + */ +static uint8_t USBD_GetLen(uint8_t *buf) +{ + uint8_t len = 0; + + while (*buf != '\0') + { + len++; + buf++; + } + + return len; +} +/** + * @} + */ + + +/** + * @} + */ + + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32_USB_Device_Library/Core/usbd_ctlreq.h b/libraries/STM32_USB_Device_Library/Core/usbd_ctlreq.h new file mode 100644 --- /dev/null +++ b/libraries/STM32_USB_Device_Library/Core/usbd_ctlreq.h @@ -0,0 +1,106 @@ +/** + ****************************************************************************** + * @file usbd_req.h + * @author MCD Application Team + * @version V2.2.0 + * @date 13-June-2014 + * @brief header file for the usbd_req.c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ + +#ifndef __USB_REQUEST_H_ +#define __USB_REQUEST_H_ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_def.h" + + +/** @addtogroup STM32_USB_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USBD_REQ + * @brief header file for the usbd_ioreq.c file + * @{ + */ + +/** @defgroup USBD_REQ_Exported_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_REQ_Exported_Types + * @{ + */ +/** + * @} + */ + + + +/** @defgroup USBD_REQ_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup USBD_REQ_Exported_Variables + * @{ + */ +/** + * @} + */ + +/** @defgroup USBD_REQ_Exported_FunctionsPrototype + * @{ + */ + +USBD_StatusTypeDef USBD_StdDevReq (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +USBD_StatusTypeDef USBD_StdItfReq (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +USBD_StatusTypeDef USBD_StdEPReq (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); + + +void USBD_CtlError (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); + +void USBD_ParseSetupRequest (USBD_SetupReqTypedef *req, uint8_t *pdata); + +void USBD_GetString (uint8_t *desc, uint8_t *unicode, uint16_t *len); +/** + * @} + */ + +#endif /* __USB_REQUEST_H_ */ + +/** + * @} + */ + +/** +* @} +*/ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32_USB_Device_Library/Core/usbd_def.h b/libraries/STM32_USB_Device_Library/Core/usbd_def.h new file mode 100644 --- /dev/null +++ b/libraries/STM32_USB_Device_Library/Core/usbd_def.h @@ -0,0 +1,319 @@ +/** + ****************************************************************************** + * @file usbd_def.h + * @author MCD Application Team + * @version V2.2.0 + * @date 13-June-2014 + * @brief general defines for the usb device library + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ + +#ifndef __USBD_DEF_H +#define __USBD_DEF_H + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_conf.h" + +/** @addtogroup STM32_USBD_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USB_DEF + * @brief general defines for the usb device library file + * @{ + */ + +/** @defgroup USB_DEF_Exported_Defines + * @{ + */ + +#ifndef NULL +#define NULL ((void *)0) +#endif + + +#define USB_LEN_DEV_QUALIFIER_DESC 0x0A +#define USB_LEN_DEV_DESC 0x12 +#define USB_LEN_CFG_DESC 0x09 +#define USB_LEN_IF_DESC 0x09 +#define USB_LEN_EP_DESC 0x07 +#define USB_LEN_OTG_DESC 0x03 +#define USB_LEN_LANGID_STR_DESC 0x04 +#define USB_LEN_OTHER_SPEED_DESC_SIZ 0x09 + +#define USBD_IDX_LANGID_STR 0x00 +#define USBD_IDX_MFC_STR 0x01 +#define USBD_IDX_PRODUCT_STR 0x02 +#define USBD_IDX_SERIAL_STR 0x03 +#define USBD_IDX_CONFIG_STR 0x04 +#define USBD_IDX_INTERFACE_STR 0x05 + +#define USB_REQ_TYPE_STANDARD 0x00 +#define USB_REQ_TYPE_CLASS 0x20 +#define USB_REQ_TYPE_VENDOR 0x40 +#define USB_REQ_TYPE_MASK 0x60 + +#define USB_REQ_RECIPIENT_DEVICE 0x00 +#define USB_REQ_RECIPIENT_INTERFACE 0x01 +#define USB_REQ_RECIPIENT_ENDPOINT 0x02 +#define USB_REQ_RECIPIENT_MASK 0x03 + +#define USB_REQ_GET_STATUS 0x00 +#define USB_REQ_CLEAR_FEATURE 0x01 +#define USB_REQ_SET_FEATURE 0x03 +#define USB_REQ_SET_ADDRESS 0x05 +#define USB_REQ_GET_DESCRIPTOR 0x06 +#define USB_REQ_SET_DESCRIPTOR 0x07 +#define USB_REQ_GET_CONFIGURATION 0x08 +#define USB_REQ_SET_CONFIGURATION 0x09 +#define USB_REQ_GET_INTERFACE 0x0A +#define USB_REQ_SET_INTERFACE 0x0B +#define USB_REQ_SYNCH_FRAME 0x0C + +#define USB_DESC_TYPE_DEVICE 1 +#define USB_DESC_TYPE_CONFIGURATION 2 +#define USB_DESC_TYPE_STRING 3 +#define USB_DESC_TYPE_INTERFACE 4 +#define USB_DESC_TYPE_ENDPOINT 5 +#define USB_DESC_TYPE_DEVICE_QUALIFIER 6 +#define USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION 7 + + +#define USB_CONFIG_REMOTE_WAKEUP 2 +#define USB_CONFIG_SELF_POWERED 1 + +#define USB_FEATURE_EP_HALT 0 +#define USB_FEATURE_REMOTE_WAKEUP 1 +#define USB_FEATURE_TEST_MODE 2 + + +#define USB_HS_MAX_PACKET_SIZE 512 +#define USB_FS_MAX_PACKET_SIZE 64 +#define USB_MAX_EP0_SIZE 64 + +/* Device Status */ +#define USBD_STATE_DEFAULT 1 +#define USBD_STATE_ADDRESSED 2 +#define USBD_STATE_CONFIGURED 3 +#define USBD_STATE_SUSPENDED 4 + + +/* EP0 State */ +#define USBD_EP0_IDLE 0 +#define USBD_EP0_SETUP 1 +#define USBD_EP0_DATA_IN 2 +#define USBD_EP0_DATA_OUT 3 +#define USBD_EP0_STATUS_IN 4 +#define USBD_EP0_STATUS_OUT 5 +#define USBD_EP0_STALL 6 + +#define USBD_EP_TYPE_CTRL 0 +#define USBD_EP_TYPE_ISOC 1 +#define USBD_EP_TYPE_BULK 2 +#define USBD_EP_TYPE_INTR 3 + + +/** + * @} + */ + + +/** @defgroup USBD_DEF_Exported_TypesDefinitions + * @{ + */ + +typedef struct usb_setup_req +{ + + uint8_t bmRequest; + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; +}USBD_SetupReqTypedef; + +struct _USBD_HandleTypeDef; + +typedef struct _Device_cb +{ + uint8_t (*Init) (struct _USBD_HandleTypeDef *pdev , uint8_t cfgidx); + uint8_t (*DeInit) (struct _USBD_HandleTypeDef *pdev , uint8_t cfgidx); + /* Control Endpoints*/ + uint8_t (*Setup) (struct _USBD_HandleTypeDef *pdev , USBD_SetupReqTypedef *req); + uint8_t (*EP0_TxSent) (struct _USBD_HandleTypeDef *pdev ); + uint8_t (*EP0_RxReady) (struct _USBD_HandleTypeDef *pdev ); + /* Class Specific Endpoints*/ + uint8_t (*DataIn) (struct _USBD_HandleTypeDef *pdev , uint8_t epnum); + uint8_t (*DataOut) (struct _USBD_HandleTypeDef *pdev , uint8_t epnum); + uint8_t (*SOF) (struct _USBD_HandleTypeDef *pdev); + uint8_t (*IsoINIncomplete) (struct _USBD_HandleTypeDef *pdev , uint8_t epnum); + uint8_t (*IsoOUTIncomplete) (struct _USBD_HandleTypeDef *pdev , uint8_t epnum); + + uint8_t *(*GetHSConfigDescriptor)(uint16_t *length); + uint8_t *(*GetFSConfigDescriptor)(uint16_t *length); + uint8_t *(*GetOtherSpeedConfigDescriptor)(uint16_t *length); + uint8_t *(*GetDeviceQualifierDescriptor)(uint16_t *length); +#if (USBD_SUPPORT_USER_STRING == 1) + uint8_t *(*GetUsrStrDescriptor)(struct _USBD_HandleTypeDef *pdev ,uint8_t index, uint16_t *length); +#endif + +} USBD_ClassTypeDef; + +/* Following USB Device Speed */ +typedef enum +{ + USBD_SPEED_HIGH = 0, + USBD_SPEED_FULL = 1, + USBD_SPEED_LOW = 2, +}USBD_SpeedTypeDef; + +/* Following USB Device status */ +typedef enum { + USBD_OK = 0, + USBD_BUSY, + USBD_FAIL, +}USBD_StatusTypeDef; + +/* USB Device descriptors structure */ +typedef struct +{ + uint8_t *(*GetDeviceDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); + uint8_t *(*GetLangIDStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); + uint8_t *(*GetManufacturerStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); + uint8_t *(*GetProductStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); + uint8_t *(*GetSerialStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); + uint8_t *(*GetConfigurationStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); + uint8_t *(*GetInterfaceStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); +} USBD_DescriptorsTypeDef; + +/* USB Device handle structure */ +typedef struct +{ + uint32_t status; + uint32_t total_length; + uint32_t rem_length; + uint32_t maxpacket; +} USBD_EndpointTypeDef; + +/* USB Device handle structure */ +typedef struct _USBD_HandleTypeDef +{ + uint8_t id; + uint32_t dev_config; + uint32_t dev_default_config; + uint32_t dev_config_status; + USBD_SpeedTypeDef dev_speed; + USBD_EndpointTypeDef ep_in[15]; + USBD_EndpointTypeDef ep_out[15]; + uint32_t ep0_state; + uint32_t ep0_data_len; + uint8_t dev_state; + uint8_t dev_old_state; + uint8_t dev_address; + uint8_t dev_connection_status; + uint8_t dev_test_mode; + uint32_t dev_remote_wakeup; + + USBD_SetupReqTypedef request; + USBD_DescriptorsTypeDef *pDesc; + USBD_ClassTypeDef *pClass; + void *pClassData; + void *pUserData; + void *pData; +} USBD_HandleTypeDef; + +/** + * @} + */ + + + +/** @defgroup USBD_DEF_Exported_Macros + * @{ + */ +#define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \ + (((uint16_t)(*(((uint8_t *)(addr)) + 1))) << 8)) + +#define LOBYTE(x) ((uint8_t)(x & 0x00FF)) +#define HIBYTE(x) ((uint8_t)((x & 0xFF00) >>8)) +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) + + +#if defined ( __GNUC__ ) + #ifndef __weak + #define __weak __attribute__((weak)) + #endif /* __weak */ + #ifndef __packed + #define __packed __attribute__((__packed__)) + #endif /* __packed */ +#endif /* __GNUC__ */ + + +/* In HS mode and when the DMA is used, all variables and data structures dealing + with the DMA during the transaction process should be 4-bytes aligned */ + +#if defined (__GNUC__) /* GNU Compiler */ + #define __ALIGN_END __attribute__ ((aligned (4))) + #define __ALIGN_BEGIN +#else + #define __ALIGN_END + #if defined (__CC_ARM) /* ARM Compiler */ + #define __ALIGN_BEGIN __align(4) + #elif defined (__ICCARM__) /* IAR Compiler */ + #define __ALIGN_BEGIN + #elif defined (__TASKING__) /* TASKING Compiler */ + #define __ALIGN_BEGIN __align(4) + #endif /* __CC_ARM */ +#endif /* __GNUC__ */ + + +/** + * @} + */ + +/** @defgroup USBD_DEF_Exported_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_DEF_Exported_FunctionsPrototype + * @{ + */ + +/** + * @} + */ + +#endif /* __USBD_DEF_H */ + +/** + * @} + */ + +/** +* @} +*/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32_USB_Device_Library/Core/usbd_ioreq.c b/libraries/STM32_USB_Device_Library/Core/usbd_ioreq.c new file mode 100644 --- /dev/null +++ b/libraries/STM32_USB_Device_Library/Core/usbd_ioreq.c @@ -0,0 +1,236 @@ +/** + ****************************************************************************** + * @file usbd_ioreq.c + * @author MCD Application Team + * @version V2.2.0 + * @date 13-June-2014 + * @brief This file provides the IO requests APIs for control endpoints. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_ioreq.h" + +/** @addtogroup STM32_USB_DEVICE_LIBRARY + * @{ + */ + + +/** @defgroup USBD_IOREQ + * @brief control I/O requests module + * @{ + */ + +/** @defgroup USBD_IOREQ_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_IOREQ_Private_Defines + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_IOREQ_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_IOREQ_Private_Variables + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_IOREQ_Private_FunctionPrototypes + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_IOREQ_Private_Functions + * @{ + */ + +/** +* @brief USBD_CtlSendData +* send data on the ctl pipe +* @param pdev: device instance +* @param buff: pointer to data buffer +* @param len: length of data to be sent +* @retval status +*/ +USBD_StatusTypeDef USBD_CtlSendData (USBD_HandleTypeDef *pdev, + uint8_t *pbuf, + uint16_t len) +{ + /* Set EP0 State */ + pdev->ep0_state = USBD_EP0_DATA_IN; + pdev->ep_in[0].total_length = len; + pdev->ep_in[0].rem_length = len; + /* Start the transfer */ + USBD_LL_Transmit (pdev, 0x00, pbuf, len); + + return USBD_OK; +} + +/** +* @brief USBD_CtlContinueSendData +* continue sending data on the ctl pipe +* @param pdev: device instance +* @param buff: pointer to data buffer +* @param len: length of data to be sent +* @retval status +*/ +USBD_StatusTypeDef USBD_CtlContinueSendData (USBD_HandleTypeDef *pdev, + uint8_t *pbuf, + uint16_t len) +{ + /* Start the next transfer */ + USBD_LL_Transmit (pdev, 0x00, pbuf, len); + + return USBD_OK; +} + +/** +* @brief USBD_CtlPrepareRx +* receive data on the ctl pipe +* @param pdev: device instance +* @param buff: pointer to data buffer +* @param len: length of data to be received +* @retval status +*/ +USBD_StatusTypeDef USBD_CtlPrepareRx (USBD_HandleTypeDef *pdev, + uint8_t *pbuf, + uint16_t len) +{ + /* Set EP0 State */ + pdev->ep0_state = USBD_EP0_DATA_OUT; + pdev->ep_out[0].total_length = len; + pdev->ep_out[0].rem_length = len; + /* Start the transfer */ + USBD_LL_PrepareReceive (pdev, + 0, + pbuf, + len); + + return USBD_OK; +} + +/** +* @brief USBD_CtlContinueRx +* continue receive data on the ctl pipe +* @param pdev: device instance +* @param buff: pointer to data buffer +* @param len: length of data to be received +* @retval status +*/ +USBD_StatusTypeDef USBD_CtlContinueRx (USBD_HandleTypeDef *pdev, + uint8_t *pbuf, + uint16_t len) +{ + + USBD_LL_PrepareReceive (pdev, + 0, + pbuf, + len); + return USBD_OK; +} +/** +* @brief USBD_CtlSendStatus +* send zero lzngth packet on the ctl pipe +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_CtlSendStatus (USBD_HandleTypeDef *pdev) +{ + + /* Set EP0 State */ + pdev->ep0_state = USBD_EP0_STATUS_IN; + + /* Start the transfer */ + USBD_LL_Transmit (pdev, 0x00, NULL, 0); + + return USBD_OK; +} + +/** +* @brief USBD_CtlReceiveStatus +* receive zero lzngth packet on the ctl pipe +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_CtlReceiveStatus (USBD_HandleTypeDef *pdev) +{ + /* Set EP0 State */ + pdev->ep0_state = USBD_EP0_STATUS_OUT; + + /* Start the transfer */ + USBD_LL_PrepareReceive ( pdev, + 0, + NULL, + 0); + + return USBD_OK; +} + + +/** +* @brief USBD_GetRxCount +* returns the received data length +* @param pdev: device instance +* @param ep_addr: endpoint address +* @retval Rx Data blength +*/ +uint16_t USBD_GetRxCount (USBD_HandleTypeDef *pdev , uint8_t ep_addr) +{ + return USBD_LL_GetRxDataSize(pdev, ep_addr); +} + +/** + * @} + */ + + +/** + * @} + */ + + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/STM32_USB_Device_Library/Core/usbd_ioreq.h b/libraries/STM32_USB_Device_Library/Core/usbd_ioreq.h new file mode 100644 --- /dev/null +++ b/libraries/STM32_USB_Device_Library/Core/usbd_ioreq.h @@ -0,0 +1,121 @@ +/** + ****************************************************************************** + * @file usbd_ioreq.h + * @author MCD Application Team + * @version V2.2.0 + * @date 13-June-2014 + * @brief header file for the usbd_ioreq.c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ + +#ifndef __USBD_IOREQ_H_ +#define __USBD_IOREQ_H_ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_def.h" +#include "usbd_core.h" + +/** @addtogroup STM32_USB_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USBD_IOREQ + * @brief header file for the usbd_ioreq.c file + * @{ + */ + +/** @defgroup USBD_IOREQ_Exported_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_IOREQ_Exported_Types + * @{ + */ + + +/** + * @} + */ + + + +/** @defgroup USBD_IOREQ_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_IOREQ_Exported_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_IOREQ_Exported_FunctionsPrototype + * @{ + */ + +USBD_StatusTypeDef USBD_CtlSendData (USBD_HandleTypeDef *pdev, + uint8_t *buf, + uint16_t len); + +USBD_StatusTypeDef USBD_CtlContinueSendData (USBD_HandleTypeDef *pdev, + uint8_t *pbuf, + uint16_t len); + +USBD_StatusTypeDef USBD_CtlPrepareRx (USBD_HandleTypeDef *pdev, + uint8_t *pbuf, + uint16_t len); + +USBD_StatusTypeDef USBD_CtlContinueRx (USBD_HandleTypeDef *pdev, + uint8_t *pbuf, + uint16_t len); + +USBD_StatusTypeDef USBD_CtlSendStatus (USBD_HandleTypeDef *pdev); + +USBD_StatusTypeDef USBD_CtlReceiveStatus (USBD_HandleTypeDef *pdev); + +uint16_t USBD_GetRxCount (USBD_HandleTypeDef *pdev , + uint8_t epnum); + +/** + * @} + */ + +#endif /* __USBD_IOREQ_H_ */ + +/** + * @} + */ + +/** +* @} +*/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/USB/usb_core.c b/libraries/USB/usb_core.c deleted file mode 100644 --- a/libraries/USB/usb_core.c +++ /dev/null @@ -1,1033 +0,0 @@ -/** - ****************************************************************************** - * @file usb_core.c - * @author MCD Application Team - * @version V4.0.0 - * @date 28-August-2012 - * @brief Standard protocol processing (USB v2.0) - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - - -/* Includes ------------------------------------------------------------------*/ -#include "usb_lib.h" -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define ValBit(VAR,Place) (VAR & (1 << Place)) -#define SetBit(VAR,Place) (VAR |= (1 << Place)) -#define ClrBit(VAR,Place) (VAR &= ((1 << Place) ^ 255)) -#define Send0LengthData() { _SetEPTxCount(ENDP0, 0); \ - vSetEPTxStatus(EP_TX_VALID); \ - } - -#define vSetEPRxStatus(st) (SaveRState = st) -#define vSetEPTxStatus(st) (SaveTState = st) - -#define USB_StatusIn() Send0LengthData() -#define USB_StatusOut() vSetEPRxStatus(EP_RX_VALID) - -#define StatusInfo0 StatusInfo.bw.bb1 /* Reverse bb0 & bb1 */ -#define StatusInfo1 StatusInfo.bw.bb0 - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -uint16_t_uint8_t StatusInfo; - -bool Data_Mul_MaxPacketSize = FALSE; -/* Private function prototypes -----------------------------------------------*/ -static void DataStageOut(void); -static void DataStageIn(void); -static void NoData_Setup0(void); -static void Data_Setup0(void); -/* Private functions ---------------------------------------------------------*/ - -/******************************************************************************* -* Function Name : Standard_GetConfiguration. -* Description : Return the current configuration variable address. -* Input : Length - How many bytes are needed. -* Output : None. -* Return : Return 1 , if the request is invalid when "Length" is 0. -* Return "Buffer" if the "Length" is not 0. -*******************************************************************************/ -uint8_t *Standard_GetConfiguration(uint16_t Length) -{ - if (Length == 0) - { - pInformation->Ctrl_Info.Usb_wLength = - sizeof(pInformation->Current_Configuration); - return 0; - } - pUser_Standard_Requests->User_GetConfiguration(); - return (uint8_t *)&pInformation->Current_Configuration; -} - -/******************************************************************************* -* Function Name : Standard_SetConfiguration. -* Description : This routine is called to set the configuration value -* Then each class should configure device itself. -* Input : None. -* Output : None. -* Return : Return USB_SUCCESS, if the request is performed. -* Return USB_UNSUPPORT, if the request is invalid. -*******************************************************************************/ -RESULT Standard_SetConfiguration(void) -{ - - if ((pInformation->USBwValue0 <= - Device_Table.Total_Configuration) && (pInformation->USBwValue1 == 0) - && (pInformation->USBwIndex == 0)) /*call Back usb spec 2.0*/ - { - pInformation->Current_Configuration = pInformation->USBwValue0; - pUser_Standard_Requests->User_SetConfiguration(); - return USB_SUCCESS; - } - else - { - return USB_UNSUPPORT; - } -} - -/******************************************************************************* -* Function Name : Standard_GetInterface. -* Description : Return the Alternate Setting of the current interface. -* Input : Length - How many bytes are needed. -* Output : None. -* Return : Return 0, if the request is invalid when "Length" is 0. -* Return "Buffer" if the "Length" is not 0. -*******************************************************************************/ -uint8_t *Standard_GetInterface(uint16_t Length) -{ - if (Length == 0) - { - pInformation->Ctrl_Info.Usb_wLength = - sizeof(pInformation->Current_AlternateSetting); - return 0; - } - pUser_Standard_Requests->User_GetInterface(); - return (uint8_t *)&pInformation->Current_AlternateSetting; -} - -/******************************************************************************* -* Function Name : Standard_SetInterface. -* Description : This routine is called to set the interface. -* Then each class should configure the interface them self. -* Input : None. -* Output : None. -* Return : - Return USB_SUCCESS, if the request is performed. -* - Return USB_UNSUPPORT, if the request is invalid. -*******************************************************************************/ -RESULT Standard_SetInterface(void) -{ - RESULT Re; - /*Test if the specified Interface and Alternate Setting are supported by - the application Firmware*/ - Re = (*pProperty->Class_Get_Interface_Setting)(pInformation->USBwIndex0, pInformation->USBwValue0); - - if (pInformation->Current_Configuration != 0) - { - if ((Re != USB_SUCCESS) || (pInformation->USBwIndex1 != 0) - || (pInformation->USBwValue1 != 0)) - { - return USB_UNSUPPORT; - } - else if (Re == USB_SUCCESS) - { - pUser_Standard_Requests->User_SetInterface(); - pInformation->Current_Interface = pInformation->USBwIndex0; - pInformation->Current_AlternateSetting = pInformation->USBwValue0; - return USB_SUCCESS; - } - - } - - return USB_UNSUPPORT; -} - -/******************************************************************************* -* Function Name : Standard_GetStatus. -* Description : Copy the device request data to "StatusInfo buffer". -* Input : - Length - How many bytes are needed. -* Output : None. -* Return : Return 0, if the request is at end of data block, -* or is invalid when "Length" is 0. -*******************************************************************************/ -uint8_t *Standard_GetStatus(uint16_t Length) -{ - if (Length == 0) - { - pInformation->Ctrl_Info.Usb_wLength = 2; - return 0; - } - - /* Reset Status Information */ - StatusInfo.w = 0; - - if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT)) - { - /*Get Device Status */ - uint8_t Feature = pInformation->Current_Feature; - - /* Remote Wakeup enabled */ - if (ValBit(Feature, 5)) - { - SetBit(StatusInfo0, 1); - } - else - { - ClrBit(StatusInfo0, 1); - } - - /* Bus-powered */ - if (ValBit(Feature, 6)) - { - SetBit(StatusInfo0, 0); - } - else /* Self-powered */ - { - ClrBit(StatusInfo0, 0); - } - } - /*Interface Status*/ - else if (Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT)) - { - return (uint8_t *)&StatusInfo; - } - /*Get EndPoint Status*/ - else if (Type_Recipient == (STANDARD_REQUEST | ENDPOINT_RECIPIENT)) - { - uint8_t Related_Endpoint; - uint8_t wIndex0 = pInformation->USBwIndex0; - - Related_Endpoint = (wIndex0 & 0x0f); - if (ValBit(wIndex0, 7)) - { - /* IN endpoint */ - if (_GetTxStallStatus(Related_Endpoint)) - { - SetBit(StatusInfo0, 0); /* IN Endpoint stalled */ - } - } - else - { - /* OUT endpoint */ - if (_GetRxStallStatus(Related_Endpoint)) - { - SetBit(StatusInfo0, 0); /* OUT Endpoint stalled */ - } - } - - } - else - { - return NULL; - } - pUser_Standard_Requests->User_GetStatus(); - return (uint8_t *)&StatusInfo; -} - -/******************************************************************************* -* Function Name : Standard_ClearFeature. -* Description : Clear or disable a specific feature. -* Input : None. -* Output : None. -* Return : - Return USB_SUCCESS, if the request is performed. -* - Return USB_UNSUPPORT, if the request is invalid. -*******************************************************************************/ -RESULT Standard_ClearFeature(void) -{ - uint32_t Type_Rec = Type_Recipient; - uint32_t Status; - - - if (Type_Rec == (STANDARD_REQUEST | DEVICE_RECIPIENT)) - {/*Device Clear Feature*/ - ClrBit(pInformation->Current_Feature, 5); - return USB_SUCCESS; - } - else if (Type_Rec == (STANDARD_REQUEST | ENDPOINT_RECIPIENT)) - {/*EndPoint Clear Feature*/ - DEVICE* pDev; - uint32_t Related_Endpoint; - uint32_t wIndex0; - uint32_t rEP; - - if ((pInformation->USBwValue != ENDPOINT_STALL) - || (pInformation->USBwIndex1 != 0)) - { - return USB_UNSUPPORT; - } - - pDev = &Device_Table; - wIndex0 = pInformation->USBwIndex0; - rEP = wIndex0 & ~0x80; - Related_Endpoint = ENDP0 + rEP; - - if (ValBit(pInformation->USBwIndex0, 7)) - { - /*Get Status of endpoint & stall the request if the related_ENdpoint - is Disabled*/ - Status = _GetEPTxStatus(Related_Endpoint); - } - else - { - Status = _GetEPRxStatus(Related_Endpoint); - } - - if ((rEP >= pDev->Total_Endpoint) || (Status == 0) - || (pInformation->Current_Configuration == 0)) - { - return USB_UNSUPPORT; - } - - - if (wIndex0 & 0x80) - { - /* IN endpoint */ - if (_GetTxStallStatus(Related_Endpoint )) - { - ClearDTOG_TX(Related_Endpoint); - SetEPTxStatus(Related_Endpoint, EP_TX_VALID); - } - } - else - { - /* OUT endpoint */ - if (_GetRxStallStatus(Related_Endpoint)) - { - if (Related_Endpoint == ENDP0) - { - /* After clear the STALL, enable the default endpoint receiver */ - SetEPRxCount(Related_Endpoint, Device_Property.MaxPacketSize); - _SetEPRxStatus(Related_Endpoint, EP_RX_VALID); - } - else - { - ClearDTOG_RX(Related_Endpoint); - _SetEPRxStatus(Related_Endpoint, EP_RX_VALID); - } - } - } - pUser_Standard_Requests->User_ClearFeature(); - return USB_SUCCESS; - } - - return USB_UNSUPPORT; -} - -/******************************************************************************* -* Function Name : Standard_SetEndPointFeature -* Description : Set or enable a specific feature of EndPoint -* Input : None. -* Output : None. -* Return : - Return USB_SUCCESS, if the request is performed. -* - Return USB_UNSUPPORT, if the request is invalid. -*******************************************************************************/ -RESULT Standard_SetEndPointFeature(void) -{ - uint32_t wIndex0; - uint32_t Related_Endpoint; - uint32_t rEP; - uint32_t Status; - - wIndex0 = pInformation->USBwIndex0; - rEP = wIndex0 & ~0x80; - Related_Endpoint = ENDP0 + rEP; - - if (ValBit(pInformation->USBwIndex0, 7)) - { - /* get Status of endpoint & stall the request if the related_ENdpoint - is Disabled*/ - Status = _GetEPTxStatus(Related_Endpoint); - } - else - { - Status = _GetEPRxStatus(Related_Endpoint); - } - - if (Related_Endpoint >= Device_Table.Total_Endpoint - || pInformation->USBwValue != 0 || Status == 0 - || pInformation->Current_Configuration == 0) - { - return USB_UNSUPPORT; - } - else - { - if (wIndex0 & 0x80) - { - /* IN endpoint */ - _SetEPTxStatus(Related_Endpoint, EP_TX_STALL); - } - - else - { - /* OUT endpoint */ - _SetEPRxStatus(Related_Endpoint, EP_RX_STALL); - } - } - pUser_Standard_Requests->User_SetEndPointFeature(); - return USB_SUCCESS; -} - -/******************************************************************************* -* Function Name : Standard_SetDeviceFeature. -* Description : Set or enable a specific feature of Device. -* Input : None. -* Output : None. -* Return : - Return USB_SUCCESS, if the request is performed. -* - Return USB_UNSUPPORT, if the request is invalid. -*******************************************************************************/ -RESULT Standard_SetDeviceFeature(void) -{ - SetBit(pInformation->Current_Feature, 5); - pUser_Standard_Requests->User_SetDeviceFeature(); - return USB_SUCCESS; -} - -/******************************************************************************* -* Function Name : Standard_GetDescriptorData. -* Description : Standard_GetDescriptorData is used for descriptors transfer. -* : This routine is used for the descriptors resident in Flash -* or RAM -* pDesc can be in either Flash or RAM -* The purpose of this routine is to have a versatile way to -* response descriptors request. It allows user to generate -* certain descriptors with software or read descriptors from -* external storage part by part. -* Input : - Length - Length of the data in this transfer. -* - pDesc - A pointer points to descriptor struct. -* The structure gives the initial address of the descriptor and -* its original size. -* Output : None. -* Return : Address of a part of the descriptor pointed by the Usb_ -* wOffset The buffer pointed by this address contains at least -* Length bytes. -*******************************************************************************/ -uint8_t *Standard_GetDescriptorData(uint16_t Length, ONE_DESCRIPTOR *pDesc) -{ - uint32_t wOffset; - - wOffset = pInformation->Ctrl_Info.Usb_wOffset; - if (Length == 0) - { - pInformation->Ctrl_Info.Usb_wLength = pDesc->Descriptor_Size - wOffset; - return 0; - } - - return pDesc->Descriptor + wOffset; -} - -/******************************************************************************* -* Function Name : DataStageOut. -* Description : Data stage of a Control Write Transfer. -* Input : None. -* Output : None. -* Return : None. -*******************************************************************************/ -void DataStageOut(void) -{ - ENDPOINT_INFO *pEPinfo = &pInformation->Ctrl_Info; - uint32_t save_rLength; - - save_rLength = pEPinfo->Usb_rLength; - - if (pEPinfo->CopyData && save_rLength) - { - uint8_t *Buffer; - uint32_t Length; - - Length = pEPinfo->PacketSize; - if (Length > save_rLength) - { - Length = save_rLength; - } - - Buffer = (*pEPinfo->CopyData)(Length); - pEPinfo->Usb_rLength -= Length; - pEPinfo->Usb_rOffset += Length; - PMAToUserBufferCopy(Buffer, GetEPRxAddr(ENDP0), Length); - - } - - if (pEPinfo->Usb_rLength != 0) - { - vSetEPRxStatus(EP_RX_VALID);/* re-enable for next data reception */ - SetEPTxCount(ENDP0, 0); - vSetEPTxStatus(EP_TX_VALID);/* Expect the host to abort the data OUT stage */ - } - /* Set the next State*/ - if (pEPinfo->Usb_rLength >= pEPinfo->PacketSize) - { - pInformation->ControlState = OUT_DATA; - } - else - { - if (pEPinfo->Usb_rLength > 0) - { - pInformation->ControlState = LAST_OUT_DATA; - } - else if (pEPinfo->Usb_rLength == 0) - { - pInformation->ControlState = WAIT_STATUS_IN; - USB_StatusIn(); - } - } -} - -/******************************************************************************* -* Function Name : DataStageIn. -* Description : Data stage of a Control Read Transfer. -* Input : None. -* Output : None. -* Return : None. -*******************************************************************************/ -void DataStageIn(void) -{ - ENDPOINT_INFO *pEPinfo = &pInformation->Ctrl_Info; - uint32_t save_wLength = pEPinfo->Usb_wLength; - uint32_t ControlState = pInformation->ControlState; - - uint8_t *DataBuffer; - uint32_t Length; - - if ((save_wLength == 0) && (ControlState == LAST_IN_DATA)) - { - if(Data_Mul_MaxPacketSize == TRUE) - { - /* No more data to send and empty packet */ - Send0LengthData(); - ControlState = LAST_IN_DATA; - Data_Mul_MaxPacketSize = FALSE; - } - else - { - /* No more data to send so STALL the TX Status*/ - ControlState = WAIT_STATUS_OUT; - vSetEPTxStatus(EP_TX_STALL); - - } - - goto Expect_Status_Out; - } - - Length = pEPinfo->PacketSize; - ControlState = (save_wLength <= Length) ? LAST_IN_DATA : IN_DATA; - - if (Length > save_wLength) - { - Length = save_wLength; - } - - DataBuffer = (*pEPinfo->CopyData)(Length); - - UserToPMABufferCopy(DataBuffer, GetEPTxAddr(ENDP0), Length); - - SetEPTxCount(ENDP0, Length); - - pEPinfo->Usb_wLength -= Length; - pEPinfo->Usb_wOffset += Length; - vSetEPTxStatus(EP_TX_VALID); - - USB_StatusOut();/* Expect the host to abort the data IN stage */ - -Expect_Status_Out: - pInformation->ControlState = ControlState; -} - -/******************************************************************************* -* Function Name : NoData_Setup0. -* Description : Proceed the processing of setup request without data stage. -* Input : None. -* Output : None. -* Return : None. -*******************************************************************************/ -void NoData_Setup0(void) -{ - RESULT Result = USB_UNSUPPORT; - uint32_t RequestNo = pInformation->USBbRequest; - uint32_t ControlState; - - if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT)) - { - /* Device Request*/ - /* SET_CONFIGURATION*/ - if (RequestNo == SET_CONFIGURATION) - { - Result = Standard_SetConfiguration(); - } - - /*SET ADDRESS*/ - else if (RequestNo == SET_ADDRESS) - { - if ((pInformation->USBwValue0 > 127) || (pInformation->USBwValue1 != 0) - || (pInformation->USBwIndex != 0) - || (pInformation->Current_Configuration != 0)) - /* Device Address should be 127 or less*/ - { - ControlState = STALLED; - goto exit_NoData_Setup0; - } - else - { - Result = USB_SUCCESS; - } - } - /*SET FEATURE for Device*/ - else if (RequestNo == SET_FEATURE) - { - if ((pInformation->USBwValue0 == DEVICE_REMOTE_WAKEUP) \ - && (pInformation->USBwIndex == 0)) - { - Result = Standard_SetDeviceFeature(); - } - else - { - Result = USB_UNSUPPORT; - } - } - /*Clear FEATURE for Device */ - else if (RequestNo == CLEAR_FEATURE) - { - if (pInformation->USBwValue0 == DEVICE_REMOTE_WAKEUP - && pInformation->USBwIndex == 0 - && ValBit(pInformation->Current_Feature, 5)) - { - Result = Standard_ClearFeature(); - } - else - { - Result = USB_UNSUPPORT; - } - } - - } - - /* Interface Request*/ - else if (Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT)) - { - /*SET INTERFACE*/ - if (RequestNo == SET_INTERFACE) - { - Result = Standard_SetInterface(); - } - } - - /* EndPoint Request*/ - else if (Type_Recipient == (STANDARD_REQUEST | ENDPOINT_RECIPIENT)) - { - /*CLEAR FEATURE for EndPoint*/ - if (RequestNo == CLEAR_FEATURE) - { - Result = Standard_ClearFeature(); - } - /* SET FEATURE for EndPoint*/ - else if (RequestNo == SET_FEATURE) - { - Result = Standard_SetEndPointFeature(); - } - } - else - { - Result = USB_UNSUPPORT; - } - - - if (Result != USB_SUCCESS) - { - Result = (*pProperty->Class_NoData_Setup)(RequestNo); - if (Result == USB_NOT_READY) - { - ControlState = PAUSE; - goto exit_NoData_Setup0; - } - } - - if (Result != USB_SUCCESS) - { - ControlState = STALLED; - goto exit_NoData_Setup0; - } - - ControlState = WAIT_STATUS_IN;/* After no data stage SETUP */ - - USB_StatusIn(); - -exit_NoData_Setup0: - pInformation->ControlState = ControlState; - return; -} - -/******************************************************************************* -* Function Name : Data_Setup0. -* Description : Proceed the processing of setup request with data stage. -* Input : None. -* Output : None. -* Return : None. -*******************************************************************************/ -void Data_Setup0(void) -{ - uint8_t *(*CopyRoutine)(uint16_t); - RESULT Result; - uint32_t Request_No = pInformation->USBbRequest; - - uint32_t Related_Endpoint, Reserved; - uint32_t wOffset, Status; - - - - CopyRoutine = NULL; - wOffset = 0; - - /*GET DESCRIPTOR*/ - if (Request_No == GET_DESCRIPTOR) - { - if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT)) - { - uint8_t wValue1 = pInformation->USBwValue1; - if (wValue1 == DEVICE_DESCRIPTOR) - { - CopyRoutine = pProperty->GetDeviceDescriptor; - } - else if (wValue1 == CONFIG_DESCRIPTOR) - { - CopyRoutine = pProperty->GetConfigDescriptor; - } - else if (wValue1 == STRING_DESCRIPTOR) - { - CopyRoutine = pProperty->GetStringDescriptor; - } /* End of GET_DESCRIPTOR */ - } - } - - /*GET STATUS*/ - else if ((Request_No == GET_STATUS) && (pInformation->USBwValue == 0) - && (pInformation->USBwLength == 0x0002) - && (pInformation->USBwIndex1 == 0)) - { - /* GET STATUS for Device*/ - if ((Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT)) - && (pInformation->USBwIndex == 0)) - { - CopyRoutine = Standard_GetStatus; - } - - /* GET STATUS for Interface*/ - else if (Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT)) - { - if (((*pProperty->Class_Get_Interface_Setting)(pInformation->USBwIndex0, 0) == USB_SUCCESS) - && (pInformation->Current_Configuration != 0)) - { - CopyRoutine = Standard_GetStatus; - } - } - - /* GET STATUS for EndPoint*/ - else if (Type_Recipient == (STANDARD_REQUEST | ENDPOINT_RECIPIENT)) - { - Related_Endpoint = (pInformation->USBwIndex0 & 0x0f); - Reserved = pInformation->USBwIndex0 & 0x70; - - if (ValBit(pInformation->USBwIndex0, 7)) - { - /*Get Status of endpoint & stall the request if the related_ENdpoint - is Disabled*/ - Status = _GetEPTxStatus(Related_Endpoint); - } - else - { - Status = _GetEPRxStatus(Related_Endpoint); - } - - if ((Related_Endpoint < Device_Table.Total_Endpoint) && (Reserved == 0) - && (Status != 0)) - { - CopyRoutine = Standard_GetStatus; - } - } - - } - - /*GET CONFIGURATION*/ - else if (Request_No == GET_CONFIGURATION) - { - if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT)) - { - CopyRoutine = Standard_GetConfiguration; - } - } - /*GET INTERFACE*/ - else if (Request_No == GET_INTERFACE) - { - if ((Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT)) - && (pInformation->Current_Configuration != 0) && (pInformation->USBwValue == 0) - && (pInformation->USBwIndex1 == 0) && (pInformation->USBwLength == 0x0001) - && ((*pProperty->Class_Get_Interface_Setting)(pInformation->USBwIndex0, 0) == USB_SUCCESS)) - { - CopyRoutine = Standard_GetInterface; - } - - } - - if (CopyRoutine) - { - pInformation->Ctrl_Info.Usb_wOffset = wOffset; - pInformation->Ctrl_Info.CopyData = CopyRoutine; - /* sb in the original the cast to word was directly */ - /* now the cast is made step by step */ - (*CopyRoutine)(0); - Result = USB_SUCCESS; - } - else - { - Result = (*pProperty->Class_Data_Setup)(pInformation->USBbRequest); - if (Result == USB_NOT_READY) - { - pInformation->ControlState = PAUSE; - return; - } - } - - if (pInformation->Ctrl_Info.Usb_wLength == 0xFFFF) - { - /* Data is not ready, wait it */ - pInformation->ControlState = PAUSE; - return; - } - if ((Result == USB_UNSUPPORT) || (pInformation->Ctrl_Info.Usb_wLength == 0)) - { - /* Unsupported request */ - pInformation->ControlState = STALLED; - return; - } - - - if (ValBit(pInformation->USBbmRequestType, 7)) - { - /* Device ==> Host */ - __IO uint32_t wLength = pInformation->USBwLength; - - /* Restrict the data length to be the one host asks for */ - if (pInformation->Ctrl_Info.Usb_wLength > wLength) - { - pInformation->Ctrl_Info.Usb_wLength = wLength; - } - - else if (pInformation->Ctrl_Info.Usb_wLength < pInformation->USBwLength) - { - if (pInformation->Ctrl_Info.Usb_wLength < pProperty->MaxPacketSize) - { - Data_Mul_MaxPacketSize = FALSE; - } - else if ((pInformation->Ctrl_Info.Usb_wLength % pProperty->MaxPacketSize) == 0) - { - Data_Mul_MaxPacketSize = TRUE; - } - } - - pInformation->Ctrl_Info.PacketSize = pProperty->MaxPacketSize; - DataStageIn(); - } - else - { - pInformation->ControlState = OUT_DATA; - vSetEPRxStatus(EP_RX_VALID); /* enable for next data reception */ - } - - return; -} - -/******************************************************************************* -* Function Name : Setup0_Process -* Description : Get the device request data and dispatch to individual process. -* Input : None. -* Output : None. -* Return : Post0_Process. -*******************************************************************************/ -uint8_t Setup0_Process(void) -{ - - union - { - uint8_t* b; - uint16_t* w; - } pBuf; - uint16_t offset = 1; - - pBuf.b = PMAAddr + (uint8_t *)(_GetEPRxAddr(ENDP0) * 2); /* *2 for 32 bits addr */ - - if (pInformation->ControlState != PAUSE) - { - pInformation->USBbmRequestType = *pBuf.b++; /* bmRequestType */ - pInformation->USBbRequest = *pBuf.b++; /* bRequest */ - pBuf.w += offset; /* word not accessed because of 32 bits addressing */ - pInformation->USBwValue = ByteSwap(*pBuf.w++); /* wValue */ - pBuf.w += offset; /* word not accessed because of 32 bits addressing */ - pInformation->USBwIndex = ByteSwap(*pBuf.w++); /* wIndex */ - pBuf.w += offset; /* word not accessed because of 32 bits addressing */ - pInformation->USBwLength = *pBuf.w; /* wLength */ - } - - pInformation->ControlState = SETTING_UP; - if (pInformation->USBwLength == 0) - { - /* Setup with no data stage */ - NoData_Setup0(); - } - else - { - /* Setup with data stage */ - Data_Setup0(); - } - return Post0_Process(); -} - -/******************************************************************************* -* Function Name : In0_Process -* Description : Process the IN token on all default endpoint. -* Input : None. -* Output : None. -* Return : Post0_Process. -*******************************************************************************/ -uint8_t In0_Process(void) -{ - uint32_t ControlState = pInformation->ControlState; - - if ((ControlState == IN_DATA) || (ControlState == LAST_IN_DATA)) - { - DataStageIn(); - /* ControlState may be changed outside the function */ - ControlState = pInformation->ControlState; - } - - else if (ControlState == WAIT_STATUS_IN) - { - if ((pInformation->USBbRequest == SET_ADDRESS) && - (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))) - { - SetDeviceAddress(pInformation->USBwValue0); - pUser_Standard_Requests->User_SetDeviceAddress(); - } - (*pProperty->Process_Status_IN)(); - ControlState = STALLED; - } - - else - { - ControlState = STALLED; - } - - pInformation->ControlState = ControlState; - - return Post0_Process(); -} - -/******************************************************************************* -* Function Name : Out0_Process -* Description : Process the OUT token on all default endpoint. -* Input : None. -* Output : None. -* Return : Post0_Process. -*******************************************************************************/ -uint8_t Out0_Process(void) -{ - uint32_t ControlState = pInformation->ControlState; - - if ((ControlState == IN_DATA) || (ControlState == LAST_IN_DATA)) - { - /* host aborts the transfer before finish */ - ControlState = STALLED; - } - else if ((ControlState == OUT_DATA) || (ControlState == LAST_OUT_DATA)) - { - DataStageOut(); - ControlState = pInformation->ControlState; /* may be changed outside the function */ - } - - else if (ControlState == WAIT_STATUS_OUT) - { - (*pProperty->Process_Status_OUT)(); - ControlState = STALLED; - } - - - /* Unexpect state, STALL the endpoint */ - else - { - ControlState = STALLED; - } - - pInformation->ControlState = ControlState; - - return Post0_Process(); -} - -/******************************************************************************* -* Function Name : Post0_Process -* Description : Stall the Endpoint 0 in case of error. -* Input : None. -* Output : None. -* Return : - 0 if the control State is in PAUSE -* - 1 if not. -*******************************************************************************/ -uint8_t Post0_Process(void) -{ - - SetEPRxCount(ENDP0, Device_Property.MaxPacketSize); - - if (pInformation->ControlState == STALLED) - { - vSetEPRxStatus(EP_RX_STALL); - vSetEPTxStatus(EP_TX_STALL); - } - - return (pInformation->ControlState == PAUSE); -} - -/******************************************************************************* -* Function Name : SetDeviceAddress. -* Description : Set the device and all the used Endpoints addresses. -* Input : - Val: device address. -* Output : None. -* Return : None. -*******************************************************************************/ -void SetDeviceAddress(uint8_t Val) -{ - uint32_t i; - uint32_t nEP = Device_Table.Total_Endpoint; - - /* set address in every used endpoint */ - for (i = 0; i < nEP; i++) - { - _SetEPAddress((uint8_t)i, (uint8_t)i); - } /* for */ - _SetDADDR(Val | DADDR_EF); /* set device address and enable function */ -} - -/******************************************************************************* -* Function Name : NOP_Process -* Description : No operation function. -* Input : None. -* Output : None. -* Return : None. -*******************************************************************************/ -void NOP_Process(void) -{ -} - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/USB/usb_core.h b/libraries/USB/usb_core.h deleted file mode 100644 --- a/libraries/USB/usb_core.h +++ /dev/null @@ -1,259 +0,0 @@ -/** - ****************************************************************************** - * @file usb_core.h - * @author MCD Application Team - * @version V4.0.0 - * @date 28-August-2012 - * @brief Standard protocol processing functions prototypes - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_CORE_H -#define __USB_CORE_H - -/* Includes ------------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -typedef enum _CONTROL_STATE -{ - WAIT_SETUP, /* 0 */ - SETTING_UP, /* 1 */ - IN_DATA, /* 2 */ - OUT_DATA, /* 3 */ - LAST_IN_DATA, /* 4 */ - LAST_OUT_DATA, /* 5 */ - WAIT_STATUS_IN, /* 7 */ - WAIT_STATUS_OUT, /* 8 */ - STALLED, /* 9 */ - PAUSE /* 10 */ -} CONTROL_STATE; /* The state machine states of a control pipe */ - -typedef struct OneDescriptor -{ - uint8_t *Descriptor; - uint16_t Descriptor_Size; -} -ONE_DESCRIPTOR, *PONE_DESCRIPTOR; -/* All the request process routines return a value of this type - If the return value is not SUCCESS or NOT_READY, - the software will STALL the correspond endpoint */ -typedef enum _RESULT -{ - USB_SUCCESS = 0, /* Process successfully */ - USB_ERROR, - USB_UNSUPPORT, - USB_NOT_READY /* The process has not been finished, endpoint will be - NAK to further request */ -} RESULT; - - -/*-*-*-*-*-*-*-*-*-*-* Definitions for endpoint level -*-*-*-*-*-*-*-*-*-*-*-*/ -typedef struct _ENDPOINT_INFO -{ - /* When send data out of the device, - CopyData() is used to get data buffer 'Length' bytes data - if Length is 0, - CopyData() returns the total length of the data - if the request is not supported, returns 0 - (NEW Feature ) - if CopyData() returns -1, the calling routine should not proceed - further and will resume the SETUP process by the class device - if Length is not 0, - CopyData() returns a pointer to indicate the data location - Usb_wLength is the data remain to be sent, - Usb_wOffset is the Offset of original data - When receive data from the host, - CopyData() is used to get user data buffer which is capable - of Length bytes data to copy data from the endpoint buffer. - if Length is 0, - CopyData() returns the available data length, - if Length is not 0, - CopyData() returns user buffer address - Usb_rLength is the data remain to be received, - Usb_rPointer is the Offset of data buffer - */ - uint16_t Usb_wLength; - uint16_t Usb_wOffset; - uint16_t PacketSize; - uint8_t *(*CopyData)(uint16_t Length); -}ENDPOINT_INFO; - -/*-*-*-*-*-*-*-*-*-*-*-* Definitions for device level -*-*-*-*-*-*-*-*-*-*-*-*/ - -typedef struct _DEVICE -{ - uint8_t Total_Endpoint; /* Number of endpoints that are used */ - uint8_t Total_Configuration;/* Number of configuration available */ -} -DEVICE; - -typedef union -{ - uint16_t w; - struct BW - { - uint8_t bb1; - uint8_t bb0; - } - bw; -} uint16_t_uint8_t; - -typedef struct _DEVICE_INFO -{ - uint8_t USBbmRequestType; /* bmRequestType */ - uint8_t USBbRequest; /* bRequest */ - uint16_t_uint8_t USBwValues; /* wValue */ - uint16_t_uint8_t USBwIndexs; /* wIndex */ - uint16_t_uint8_t USBwLengths; /* wLength */ - - uint8_t ControlState; /* of type CONTROL_STATE */ - uint8_t Current_Feature; - uint8_t Current_Configuration; /* Selected configuration */ - uint8_t Current_Interface; /* Selected interface of current configuration */ - uint8_t Current_AlternateSetting;/* Selected Alternate Setting of current - interface*/ - - ENDPOINT_INFO Ctrl_Info; -}DEVICE_INFO; - -typedef struct _DEVICE_PROP -{ - void (*Init)(void); /* Initialize the device */ - void (*Reset)(void); /* Reset routine of this device */ - - /* Device dependent process after the status stage */ - void (*Process_Status_IN)(void); - void (*Process_Status_OUT)(void); - - /* Procedure of process on setup stage of a class specified request with data stage */ - /* All class specified requests with data stage are processed in Class_Data_Setup - Class_Data_Setup() - responses to check all special requests and fills ENDPOINT_INFO - according to the request - If IN tokens are expected, then wLength & wOffset will be filled - with the total transferring bytes and the starting position - If OUT tokens are expected, then rLength & rOffset will be filled - with the total expected bytes and the starting position in the buffer - - If the request is valid, Class_Data_Setup returns SUCCESS, else UNSUPPORT - - CAUTION: - Since GET_CONFIGURATION & GET_INTERFACE are highly related to - the individual classes, they will be checked and processed here. - */ - RESULT (*Class_Data_Setup)(uint8_t RequestNo); - - /* Procedure of process on setup stage of a class specified request without data stage */ - /* All class specified requests without data stage are processed in Class_NoData_Setup - Class_NoData_Setup - responses to check all special requests and perform the request - - CAUTION: - Since SET_CONFIGURATION & SET_INTERFACE are highly related to - the individual classes, they will be checked and processed here. - */ - RESULT (*Class_NoData_Setup)(uint8_t RequestNo); - - /*Class_Get_Interface_Setting - This function is used by the file usb_core.c to test if the selected Interface - and Alternate Setting (uint8_t Interface, uint8_t AlternateSetting) are supported by - the application. - This function is writing by user. It should return "SUCCESS" if the Interface - and Alternate Setting are supported by the application or "UNSUPPORT" if they - are not supported. */ - - RESULT (*Class_Get_Interface_Setting)(uint8_t Interface, uint8_t AlternateSetting); - - uint8_t* (*GetDeviceDescriptor)(uint16_t Length); - uint8_t* (*GetConfigDescriptor)(uint16_t Length); - uint8_t* (*GetStringDescriptor)(uint16_t Length); - - /* This field is not used in current library version. It is kept only for - compatibility with previous versions */ - void* RxEP_buffer; - - uint8_t MaxPacketSize; - -}DEVICE_PROP; - -typedef struct _USER_STANDARD_REQUESTS -{ - void (*User_GetConfiguration)(void); /* Get Configuration */ - void (*User_SetConfiguration)(void); /* Set Configuration */ - void (*User_GetInterface)(void); /* Get Interface */ - void (*User_SetInterface)(void); /* Set Interface */ - void (*User_GetStatus)(void); /* Get Status */ - void (*User_ClearFeature)(void); /* Clear Feature */ - void (*User_SetEndPointFeature)(void); /* Set Endpoint Feature */ - void (*User_SetDeviceFeature)(void); /* Set Device Feature */ - void (*User_SetDeviceAddress)(void); /* Set Device Address */ -} -USER_STANDARD_REQUESTS; - -/* Exported constants --------------------------------------------------------*/ -#define Type_Recipient (pInformation->USBbmRequestType & (REQUEST_TYPE | RECIPIENT)) - -#define Usb_rLength Usb_wLength -#define Usb_rOffset Usb_wOffset - -#define USBwValue USBwValues.w -#define USBwValue0 USBwValues.bw.bb0 -#define USBwValue1 USBwValues.bw.bb1 -#define USBwIndex USBwIndexs.w -#define USBwIndex0 USBwIndexs.bw.bb0 -#define USBwIndex1 USBwIndexs.bw.bb1 -#define USBwLength USBwLengths.w -#define USBwLength0 USBwLengths.bw.bb0 -#define USBwLength1 USBwLengths.bw.bb1 - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -uint8_t Setup0_Process(void); -uint8_t Post0_Process(void); -uint8_t Out0_Process(void); -uint8_t In0_Process(void); - -RESULT Standard_SetEndPointFeature(void); -RESULT Standard_SetDeviceFeature(void); - -uint8_t *Standard_GetConfiguration(uint16_t Length); -RESULT Standard_SetConfiguration(void); -uint8_t *Standard_GetInterface(uint16_t Length); -RESULT Standard_SetInterface(void); -uint8_t *Standard_GetDescriptorData(uint16_t Length, PONE_DESCRIPTOR pDesc); - -uint8_t *Standard_GetStatus(uint16_t Length); -RESULT Standard_ClearFeature(void); -void SetDeviceAddress(uint8_t); -void NOP_Process(void); - -extern DEVICE_PROP Device_Property; -extern USER_STANDARD_REQUESTS User_Standard_Requests; -extern DEVICE Device_Table; -extern DEVICE_INFO Device_Info; - -/* cells saving status during interrupt servicing */ -extern __IO uint16_t SaveRState; -extern __IO uint16_t SaveTState; - -#endif /* __USB_CORE_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/USB/usb_def.h b/libraries/USB/usb_def.h deleted file mode 100644 --- a/libraries/USB/usb_def.h +++ /dev/null @@ -1,92 +0,0 @@ -/** - ****************************************************************************** - * @file usb_def.h - * @author MCD Application Team - * @version V4.0.0 - * @date 28-August-2012 - * @brief Definitions related to USB Core - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_DEF_H -#define __USB_DEF_H - -/* Includes ------------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -typedef enum _RECIPIENT_TYPE -{ - DEVICE_RECIPIENT, /* Recipient device */ - INTERFACE_RECIPIENT, /* Recipient interface */ - ENDPOINT_RECIPIENT, /* Recipient endpoint */ - OTHER_RECIPIENT -} RECIPIENT_TYPE; - - -typedef enum _STANDARD_REQUESTS -{ - GET_STATUS = 0, - CLEAR_FEATURE, - RESERVED1, - SET_FEATURE, - RESERVED2, - SET_ADDRESS, - GET_DESCRIPTOR, - SET_DESCRIPTOR, - GET_CONFIGURATION, - SET_CONFIGURATION, - GET_INTERFACE, - SET_INTERFACE, - TOTAL_sREQUEST, /* Total number of Standard request */ - SYNCH_FRAME = 12 -} STANDARD_REQUESTS; - -/* Definition of "USBwValue" */ -typedef enum _DESCRIPTOR_TYPE -{ - DEVICE_DESCRIPTOR = 1, - CONFIG_DESCRIPTOR, - STRING_DESCRIPTOR, - INTERFACE_DESCRIPTOR, - ENDPOINT_DESCRIPTOR -} DESCRIPTOR_TYPE; - -/* Feature selector of a SET_FEATURE or CLEAR_FEATURE */ -typedef enum _FEATURE_SELECTOR -{ - ENDPOINT_STALL, - DEVICE_REMOTE_WAKEUP -} FEATURE_SELECTOR; - -/* Exported constants --------------------------------------------------------*/ -/* Definition of "USBbmRequestType" */ -#define REQUEST_TYPE 0x60 /* Mask to get request type */ -#define STANDARD_REQUEST 0x00 /* Standard request */ -#define CLASS_REQUEST 0x20 /* Class request */ -#define VENDOR_REQUEST 0x40 /* Vendor request */ - -#define RECIPIENT 0x1F /* Mask to get recipient */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -#endif /* __USB_DEF_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/USB/usb_init.c b/libraries/USB/usb_init.c deleted file mode 100644 --- a/libraries/USB/usb_init.c +++ /dev/null @@ -1,76 +0,0 @@ -/** - ****************************************************************************** - * @file usb_init.c - * @author MCD Application Team - * @version V4.0.0 - * @date 28-August-2012 - * @brief Initialization routines & global variables - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - - -/* Includes ------------------------------------------------------------------*/ -#include "usb_lib.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* The number of current endpoint, it will be used to specify an endpoint */ - uint8_t EPindex; -/* The number of current device, it is an index to the Device_Table */ -/* uint8_t Device_no; */ -/* Points to the DEVICE_INFO structure of current device */ -/* The purpose of this register is to speed up the execution */ -DEVICE_INFO *pInformation; -/* Points to the DEVICE_PROP structure of current device */ -/* The purpose of this register is to speed up the execution */ -DEVICE_PROP *pProperty; -/* Temporary save the state of Rx & Tx status. */ -/* Whenever the Rx or Tx state is changed, its value is saved */ -/* in this variable first and will be set to the EPRB or EPRA */ -/* at the end of interrupt process */ -uint16_t SaveState ; -uint16_t wInterrupt_Mask; -DEVICE_INFO Device_Info; -USER_STANDARD_REQUESTS *pUser_Standard_Requests; - -/* Extern variables ----------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/******************************************************************************* -* Function Name : USB_Init -* Description : USB system initialization -* Input : None. -* Output : None. -* Return : None. -*******************************************************************************/ -void USB_Init(void) -{ - pInformation = &Device_Info; - pInformation->ControlState = 2; - pProperty = &Device_Property; - pUser_Standard_Requests = &User_Standard_Requests; - /* Initialize devices one by one */ - pProperty->Init(); -} - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/USB/usb_init.h b/libraries/USB/usb_init.h deleted file mode 100644 --- a/libraries/USB/usb_init.h +++ /dev/null @@ -1,62 +0,0 @@ -/** - ****************************************************************************** - * @file usb_init.h - * @author MCD Application Team - * @version V4.0.0 - * @date 28-August-2012 - * @brief Initialization routines & global variables - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_INIT_H -#define __USB_INIT_H - -/* Includes ------------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -void USB_Init(void); - -/* External variables --------------------------------------------------------*/ -/* The number of current endpoint, it will be used to specify an endpoint */ -extern uint8_t EPindex; -/* The number of current device, it is an index to the Device_Table */ -/*extern uint8_t Device_no; */ -/* Points to the DEVICE_INFO structure of current device */ -/* The purpose of this register is to speed up the execution */ -extern DEVICE_INFO* pInformation; -/* Points to the DEVICE_PROP structure of current device */ -/* The purpose of this register is to speed up the execution */ -extern DEVICE_PROP* pProperty; -/* Temporary save the state of Rx & Tx status. */ -/* Whenever the Rx or Tx state is changed, its value is saved */ -/* in this variable first and will be set to the EPRB or EPRA */ -/* at the end of interrupt process */ -extern USER_STANDARD_REQUESTS *pUser_Standard_Requests; - -extern uint16_t SaveState ; -extern uint16_t wInterrupt_Mask; - -#endif /* __USB_INIT_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/USB/usb_int.c b/libraries/USB/usb_int.c deleted file mode 100644 --- a/libraries/USB/usb_int.c +++ /dev/null @@ -1,195 +0,0 @@ -/** - ****************************************************************************** - * @file usb_int.c - * @author MCD Application Team - * @version V4.0.0 - * @date 28-August-2012 - * @brief Endpoint CTR (Low and High) interrupt's service routines - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_lib.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -__IO uint16_t SaveRState; -__IO uint16_t SaveTState; - -/* Extern variables ----------------------------------------------------------*/ -extern void (*pEpInt_IN[7])(void); /* Handles IN interrupts */ -extern void (*pEpInt_OUT[7])(void); /* Handles OUT interrupts */ - -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/******************************************************************************* -* Function Name : CTR_LP. -* Description : Low priority Endpoint Correct Transfer interrupt's service -* routine. -* Input : None. -* Output : None. -* Return : None. -*******************************************************************************/ -void CTR_LP(void) -{ - __IO uint16_t wEPVal = 0; - /* stay in loop while pending interrupts */ - while (((wIstr = _GetISTR()) & ISTR_CTR) != 0) - { - /* extract highest priority endpoint number */ - EPindex = (uint8_t)(wIstr & ISTR_EP_ID); - if (EPindex == 0) - { - /* Decode and service control endpoint interrupt */ - /* calling related service routine */ - /* (Setup0_Process, In0_Process, Out0_Process) */ - - /* save RX & TX status */ - /* and set both to NAK */ - - SaveRState = _GetENDPOINT(ENDP0); - SaveTState = SaveRState & EPTX_STAT; - SaveRState &= EPRX_STAT; - - _SetEPRxTxStatus(ENDP0,EP_RX_NAK,EP_TX_NAK); - - /* DIR bit = origin of the interrupt */ - - if ((wIstr & ISTR_DIR) == 0) - { - /* DIR = 0 */ - - /* DIR = 0 => IN int */ - /* DIR = 0 implies that (EP_CTR_TX = 1) always */ - - _ClearEP_CTR_TX(ENDP0); - In0_Process(); - - /* before terminate set Tx & Rx status */ - - _SetEPRxTxStatus(ENDP0,SaveRState,SaveTState); - return; - } - else - { - /* DIR = 1 */ - - /* DIR = 1 & CTR_RX => SETUP or OUT int */ - /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */ - - wEPVal = _GetENDPOINT(ENDP0); - - if ((wEPVal &EP_SETUP) != 0) - { - _ClearEP_CTR_RX(ENDP0); /* SETUP bit kept frozen while CTR_RX = 1 */ - Setup0_Process(); - /* before terminate set Tx & Rx status */ - - _SetEPRxTxStatus(ENDP0,SaveRState,SaveTState); - return; - } - - else if ((wEPVal & EP_CTR_RX) != 0) - { - _ClearEP_CTR_RX(ENDP0); - Out0_Process(); - /* before terminate set Tx & Rx status */ - - _SetEPRxTxStatus(ENDP0,SaveRState,SaveTState); - return; - } - } - }/* if(EPindex == 0) */ - else - { - /* Decode and service non control endpoints interrupt */ - - /* process related endpoint register */ - wEPVal = _GetENDPOINT(EPindex); - if ((wEPVal & EP_CTR_RX) != 0) - { - /* clear int flag */ - _ClearEP_CTR_RX(EPindex); - - /* call OUT service function */ - (*pEpInt_OUT[EPindex-1])(); - - } /* if((wEPVal & EP_CTR_RX) */ - - if ((wEPVal & EP_CTR_TX) != 0) - { - /* clear int flag */ - _ClearEP_CTR_TX(EPindex); - - /* call IN service function */ - (*pEpInt_IN[EPindex-1])(); - } /* if((wEPVal & EP_CTR_TX) != 0) */ - - }/* if(EPindex == 0) else */ - - }/* while(...) */ -} - -/******************************************************************************* -* Function Name : CTR_HP. -* Description : High Priority Endpoint Correct Transfer interrupt's service -* routine. -* Input : None. -* Output : None. -* Return : None. -*******************************************************************************/ -void CTR_HP(void) -{ - uint32_t wEPVal = 0; - - while (((wIstr = _GetISTR()) & ISTR_CTR) != 0) - { - _SetISTR((uint16_t)CLR_CTR); /* clear CTR flag */ - /* extract highest priority endpoint number */ - EPindex = (uint8_t)(wIstr & ISTR_EP_ID); - /* process related endpoint register */ - wEPVal = _GetENDPOINT(EPindex); - if ((wEPVal & EP_CTR_RX) != 0) - { - /* clear int flag */ - _ClearEP_CTR_RX(EPindex); - - /* call OUT service function */ - (*pEpInt_OUT[EPindex-1])(); - - } /* if((wEPVal & EP_CTR_RX) */ - else if ((wEPVal & EP_CTR_TX) != 0) - { - /* clear int flag */ - _ClearEP_CTR_TX(EPindex); - - /* call IN service function */ - (*pEpInt_IN[EPindex-1])(); - - - } /* if((wEPVal & EP_CTR_TX) != 0) */ - - }/* while(...) */ -} - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/USB/usb_int.h b/libraries/USB/usb_int.h deleted file mode 100644 --- a/libraries/USB/usb_int.h +++ /dev/null @@ -1,45 +0,0 @@ -/** - ****************************************************************************** - * @file usb_int.h - * @author MCD Application Team - * @version V4.0.0 - * @date 28-August-2012 - * @brief Endpoint CTR (Low and High) interrupt's service routines prototypes - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_INT_H -#define __USB_INT_H - -/* Includes ------------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -void CTR_LP(void); -void CTR_HP(void); - -/* External variables --------------------------------------------------------*/ - -#endif /* __USB_INT_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/USB/usb_lib.h b/libraries/USB/usb_lib.h deleted file mode 100644 --- a/libraries/USB/usb_lib.h +++ /dev/null @@ -1,52 +0,0 @@ -/** - ****************************************************************************** - * @file usb_lib.h - * @author MCD Application Team - * @version V4.0.0 - * @date 28-August-2012 - * @brief USB library include files - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_LIB_H -#define __USB_LIB_H - -/* Includes ------------------------------------------------------------------*/ -#include "hw_config.h" -#include "usb_type.h" -#include "usb_regs.h" -#include "usb_def.h" -#include "usb_core.h" -#include "usb_init.h" -#include "usb_sil.h" -#include "usb_mem.h" -#include "usb_int.h" - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -/* External variables --------------------------------------------------------*/ - -#endif /* __USB_LIB_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/USB/usb_mem.c b/libraries/USB/usb_mem.c deleted file mode 100644 --- a/libraries/USB/usb_mem.c +++ /dev/null @@ -1,87 +0,0 @@ -/** - ****************************************************************************** - * @file usb_mem.c - * @author MCD Application Team - * @version V4.0.0 - * @date 28-August-2012 - * @brief Utility functions for memory transfers to/from PMA - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_lib.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Extern variables ----------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/******************************************************************************* -* Function Name : UserToPMABufferCopy -* Description : Copy a buffer from user memory area to packet memory area (PMA) -* Input : - pbUsrBuf: pointer to user memory area. -* - wPMABufAddr: address into PMA. -* - wNBytes: no. of bytes to be copied. -* Output : None. -* Return : None . -*******************************************************************************/ -void UserToPMABufferCopy(uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) -{ - uint32_t n = (wNBytes + 1) >> 1; /* n = (wNBytes + 1) / 2 */ - uint32_t i, temp1, temp2; - uint16_t *pdwVal; - pdwVal = (uint16_t *)(wPMABufAddr * 2 + PMAAddr); - for (i = n; i != 0; i--) - { - temp1 = (uint16_t) * pbUsrBuf; - pbUsrBuf++; - temp2 = temp1 | (uint16_t) * pbUsrBuf << 8; - *pdwVal++ = temp2; - pdwVal++; - pbUsrBuf++; - } -} - -/******************************************************************************* -* Function Name : PMAToUserBufferCopy -* Description : Copy a buffer from user memory area to packet memory area (PMA) -* Input : - pbUsrBuf = pointer to user memory area. -* - wPMABufAddr = address into PMA. -* - wNBytes = no. of bytes to be copied. -* Output : None. -* Return : None. -*******************************************************************************/ -void PMAToUserBufferCopy(uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) -{ - uint32_t n = (wNBytes + 1) >> 1;/* /2*/ - uint32_t i; - uint32_t *pdwVal; - pdwVal = (uint32_t *)(wPMABufAddr * 2 + PMAAddr); - for (i = n; i != 0; i--) - { - *(uint16_t*)pbUsrBuf++ = *pdwVal++; - pbUsrBuf++; - } -} - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/USB/usb_mem.h b/libraries/USB/usb_mem.h deleted file mode 100644 --- a/libraries/USB/usb_mem.h +++ /dev/null @@ -1,45 +0,0 @@ -/** - ****************************************************************************** - * @file usb_mem.h - * @author MCD Application Team - * @version V4.0.0 - * @date 28-August-2012 - * @brief Utility prototypes functions for memory/PMA transfers - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_MEM_H -#define __USB_MEM_H - -/* Includes ------------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -void UserToPMABufferCopy(uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); -void PMAToUserBufferCopy(uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); - -/* External variables --------------------------------------------------------*/ - -#endif /*__USB_MEM_H*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/USB/usb_regs.c b/libraries/USB/usb_regs.c deleted file mode 100644 --- a/libraries/USB/usb_regs.c +++ /dev/null @@ -1,760 +0,0 @@ -/** - ****************************************************************************** - * @file usb_regs.c - * @author MCD Application Team - * @version V4.0.0 - * @date 28-August-2012 - * @brief Interface functions to USB cell registers - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_lib.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Extern variables ----------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/******************************************************************************* -* Function Name : SetCNTR. -* Description : Set the CNTR register value. -* Input : wRegValue: new register value. -* Output : None. -* Return : None. -*******************************************************************************/ -void SetCNTR(uint16_t wRegValue) -{ - _SetCNTR(wRegValue); -} - -/******************************************************************************* -* Function Name : GetCNTR. -* Description : returns the CNTR register value. -* Input : None. -* Output : None. -* Return : CNTR register Value. -*******************************************************************************/ -uint16_t GetCNTR(void) -{ - return(_GetCNTR()); -} - -/******************************************************************************* -* Function Name : SetISTR. -* Description : Set the ISTR register value. -* Input : wRegValue: new register value. -* Output : None. -* Return : None. -*******************************************************************************/ -void SetISTR(uint16_t wRegValue) -{ - _SetISTR(wRegValue); -} - -/******************************************************************************* -* Function Name : GetISTR -* Description : Returns the ISTR register value. -* Input : None. -* Output : None. -* Return : ISTR register Value -*******************************************************************************/ -uint16_t GetISTR(void) -{ - return(_GetISTR()); -} - -/******************************************************************************* -* Function Name : GetFNR -* Description : Returns the FNR register value. -* Input : None. -* Output : None. -* Return : FNR register Value -*******************************************************************************/ -uint16_t GetFNR(void) -{ - return(_GetFNR()); -} - -/******************************************************************************* -* Function Name : SetDADDR -* Description : Set the DADDR register value. -* Input : wRegValue: new register value. -* Output : None. -* Return : None. -*******************************************************************************/ -void SetDADDR(uint16_t wRegValue) -{ - _SetDADDR(wRegValue); -} - -/******************************************************************************* -* Function Name : GetDADDR -* Description : Returns the DADDR register value. -* Input : None. -* Output : None. -* Return : DADDR register Value -*******************************************************************************/ -uint16_t GetDADDR(void) -{ - return(_GetDADDR()); -} - -/******************************************************************************* -* Function Name : SetBTABLE -* Description : Set the BTABLE. -* Input : wRegValue: New register value. -* Output : None. -* Return : None. -*******************************************************************************/ -void SetBTABLE(uint16_t wRegValue) -{ - _SetBTABLE(wRegValue); -} - -/******************************************************************************* -* Function Name : GetBTABLE. -* Description : Returns the BTABLE register value. -* Input : None. -* Output : None. -* Return : BTABLE address. -*******************************************************************************/ -uint16_t GetBTABLE(void) -{ - return(_GetBTABLE()); -} - -/******************************************************************************* -* Function Name : SetENDPOINT -* Description : Set the Endpoint register value. -* Input : bEpNum: Endpoint Number. -* wRegValue. -* Output : None. -* Return : None. -*******************************************************************************/ -void SetENDPOINT(uint8_t bEpNum, uint16_t wRegValue) -{ - _SetENDPOINT(bEpNum, wRegValue); -} - -/******************************************************************************* -* Function Name : GetENDPOINT -* Description : Return the Endpoint register value. -* Input : bEpNum: Endpoint Number. -* Output : None. -* Return : Endpoint register value. -*******************************************************************************/ -uint16_t GetENDPOINT(uint8_t bEpNum) -{ - return(_GetENDPOINT(bEpNum)); -} - -/******************************************************************************* -* Function Name : SetEPType -* Description : sets the type in the endpoint register. -* Input : bEpNum: Endpoint Number. -* wType: type definition. -* Output : None. -* Return : None. -*******************************************************************************/ -void SetEPType(uint8_t bEpNum, uint16_t wType) -{ - _SetEPType(bEpNum, wType); -} - -/******************************************************************************* -* Function Name : GetEPType -* Description : Returns the endpoint type. -* Input : bEpNum: Endpoint Number. -* Output : None. -* Return : Endpoint Type -*******************************************************************************/ -uint16_t GetEPType(uint8_t bEpNum) -{ - return(_GetEPType(bEpNum)); -} - -/******************************************************************************* -* Function Name : SetEPTxStatus -* Description : Set the status of Tx endpoint. -* Input : bEpNum: Endpoint Number. -* wState: new state. -* Output : None. -* Return : None. -*******************************************************************************/ -void SetEPTxStatus(uint8_t bEpNum, uint16_t wState) -{ - _SetEPTxStatus(bEpNum, wState); -} - -/******************************************************************************* -* Function Name : SetEPRxStatus -* Description : Set the status of Rx endpoint. -* Input : bEpNum: Endpoint Number. -* wState: new state. -* Output : None. -* Return : None. -*******************************************************************************/ -void SetEPRxStatus(uint8_t bEpNum, uint16_t wState) -{ - _SetEPRxStatus(bEpNum, wState); -} - -/******************************************************************************* -* Function Name : SetDouBleBuffEPStall -* Description : sets the status for Double Buffer Endpoint to STALL -* Input : bEpNum: Endpoint Number. -* bDir: Endpoint direction. -* Output : None. -* Return : None. -*******************************************************************************/ -void SetDouBleBuffEPStall(uint8_t bEpNum, uint8_t bDir) -{ - uint16_t Endpoint_DTOG_Status; - Endpoint_DTOG_Status = GetENDPOINT(bEpNum); - if (bDir == EP_DBUF_OUT) - { /* OUT double buffered endpoint */ - _SetENDPOINT(bEpNum, Endpoint_DTOG_Status & ~EPRX_DTOG1); - } - else if (bDir == EP_DBUF_IN) - { /* IN double buffered endpoint */ - _SetENDPOINT(bEpNum, Endpoint_DTOG_Status & ~EPTX_DTOG1); - } -} - -/******************************************************************************* -* Function Name : GetEPTxStatus -* Description : Returns the endpoint Tx status. -* Input : bEpNum: Endpoint Number. -* Output : None. -* Return : Endpoint TX Status -*******************************************************************************/ -uint16_t GetEPTxStatus(uint8_t bEpNum) -{ - return(_GetEPTxStatus(bEpNum)); -} - -/******************************************************************************* -* Function Name : GetEPRxStatus -* Description : Returns the endpoint Rx status. -* Input : bEpNum: Endpoint Number. -* Output : None. -* Return : Endpoint RX Status -*******************************************************************************/ -uint16_t GetEPRxStatus(uint8_t bEpNum) -{ - return(_GetEPRxStatus(bEpNum)); -} - -/******************************************************************************* -* Function Name : SetEPTxValid -* Description : Valid the endpoint Tx Status. -* Input : bEpNum: Endpoint Number. -* Output : None. -* Return : None. -*******************************************************************************/ -void SetEPTxValid(uint8_t bEpNum) -{ - _SetEPTxStatus(bEpNum, EP_TX_VALID); -} - -/******************************************************************************* -* Function Name : SetEPRxValid -* Description : Valid the endpoint Rx Status. -* Input : bEpNum: Endpoint Number. -* Output : None. -* Return : None. -*******************************************************************************/ -void SetEPRxValid(uint8_t bEpNum) -{ - _SetEPRxStatus(bEpNum, EP_RX_VALID); -} - -/******************************************************************************* -* Function Name : SetEP_KIND -* Description : Clear the EP_KIND bit. -* Input : bEpNum: Endpoint Number. -* Output : None. -* Return : None. -*******************************************************************************/ -void SetEP_KIND(uint8_t bEpNum) -{ - _SetEP_KIND(bEpNum); -} - -/******************************************************************************* -* Function Name : ClearEP_KIND -* Description : set the EP_KIND bit. -* Input : bEpNum: Endpoint Number. -* Output : None. -* Return : None. -*******************************************************************************/ -void ClearEP_KIND(uint8_t bEpNum) -{ - _ClearEP_KIND(bEpNum); -} -/******************************************************************************* -* Function Name : Clear_Status_Out -* Description : Clear the Status Out of the related Endpoint -* Input : bEpNum: Endpoint Number. -* Output : None. -* Return : None. -*******************************************************************************/ -void Clear_Status_Out(uint8_t bEpNum) -{ - _ClearEP_KIND(bEpNum); -} -/******************************************************************************* -* Function Name : Set_Status_Out -* Description : Set the Status Out of the related Endpoint -* Input : bEpNum: Endpoint Number. -* Output : None. -* Return : None. -*******************************************************************************/ -void Set_Status_Out(uint8_t bEpNum) -{ - _SetEP_KIND(bEpNum); -} -/******************************************************************************* -* Function Name : SetEPDoubleBuff -* Description : Enable the double buffer feature for the endpoint. -* Input : bEpNum: Endpoint Number. -* Output : None. -* Return : None. -*******************************************************************************/ -void SetEPDoubleBuff(uint8_t bEpNum) -{ - _SetEP_KIND(bEpNum); -} -/******************************************************************************* -* Function Name : ClearEPDoubleBuff -* Description : Disable the double buffer feature for the endpoint. -* Input : bEpNum: Endpoint Number. -* Output : None. -* Return : None. -*******************************************************************************/ -void ClearEPDoubleBuff(uint8_t bEpNum) -{ - _ClearEP_KIND(bEpNum); -} -/******************************************************************************* -* Function Name : GetTxStallStatus -* Description : Returns the Stall status of the Tx endpoint. -* Input : bEpNum: Endpoint Number. -* Output : None. -* Return : Tx Stall status. -*******************************************************************************/ -uint16_t GetTxStallStatus(uint8_t bEpNum) -{ - return(_GetTxStallStatus(bEpNum)); -} -/******************************************************************************* -* Function Name : GetRxStallStatus -* Description : Returns the Stall status of the Rx endpoint. -* Input : bEpNum: Endpoint Number. -* Output : None. -* Return : Rx Stall status. -*******************************************************************************/ -uint16_t GetRxStallStatus(uint8_t bEpNum) -{ - return(_GetRxStallStatus(bEpNum)); -} -/******************************************************************************* -* Function Name : ClearEP_CTR_RX -* Description : Clear the CTR_RX bit. -* Input : bEpNum: Endpoint Number. -* Output : None. -* Return : None. -*******************************************************************************/ -void ClearEP_CTR_RX(uint8_t bEpNum) -{ - _ClearEP_CTR_RX(bEpNum); -} -/******************************************************************************* -* Function Name : ClearEP_CTR_TX -* Description : Clear the CTR_TX bit. -* Input : bEpNum: Endpoint Number. -* Output : None. -* Return : None. -*******************************************************************************/ -void ClearEP_CTR_TX(uint8_t bEpNum) -{ - _ClearEP_CTR_TX(bEpNum); -} -/******************************************************************************* -* Function Name : ToggleDTOG_RX -* Description : Toggle the DTOG_RX bit. -* Input : bEpNum: Endpoint Number. -* Output : None. -* Return : None. -*******************************************************************************/ -void ToggleDTOG_RX(uint8_t bEpNum) -{ - _ToggleDTOG_RX(bEpNum); -} -/******************************************************************************* -* Function Name : ToggleDTOG_TX -* Description : Toggle the DTOG_TX bit. -* Input : bEpNum: Endpoint Number. -* Output : None. -* Return : None. -*******************************************************************************/ -void ToggleDTOG_TX(uint8_t bEpNum) -{ - _ToggleDTOG_TX(bEpNum); -} -/******************************************************************************* -* Function Name : ClearDTOG_RX. -* Description : Clear the DTOG_RX bit. -* Input : bEpNum: Endpoint Number. -* Output : None. -* Return : None. -*******************************************************************************/ -void ClearDTOG_RX(uint8_t bEpNum) -{ - _ClearDTOG_RX(bEpNum); -} -/******************************************************************************* -* Function Name : ClearDTOG_TX. -* Description : Clear the DTOG_TX bit. -* Input : bEpNum: Endpoint Number. -* Output : None. -* Return : None. -*******************************************************************************/ -void ClearDTOG_TX(uint8_t bEpNum) -{ - _ClearDTOG_TX(bEpNum); -} -/******************************************************************************* -* Function Name : SetEPAddress -* Description : Set the endpoint address. -* Input : bEpNum: Endpoint Number. -* bAddr: New endpoint address. -* Output : None. -* Return : None. -*******************************************************************************/ -void SetEPAddress(uint8_t bEpNum, uint8_t bAddr) -{ - _SetEPAddress(bEpNum, bAddr); -} -/******************************************************************************* -* Function Name : GetEPAddress -* Description : Get the endpoint address. -* Input : bEpNum: Endpoint Number. -* Output : None. -* Return : Endpoint address. -*******************************************************************************/ -uint8_t GetEPAddress(uint8_t bEpNum) -{ - return(_GetEPAddress(bEpNum)); -} -/******************************************************************************* -* Function Name : SetEPTxAddr -* Description : Set the endpoint Tx buffer address. -* Input : bEpNum: Endpoint Number. -* wAddr: new address. -* Output : None. -* Return : None. -*******************************************************************************/ -void SetEPTxAddr(uint8_t bEpNum, uint16_t wAddr) -{ - _SetEPTxAddr(bEpNum, wAddr); -} -/******************************************************************************* -* Function Name : SetEPRxAddr -* Description : Set the endpoint Rx buffer address. -* Input : bEpNum: Endpoint Number. -* wAddr: new address. -* Output : None. -* Return : None. -*******************************************************************************/ -void SetEPRxAddr(uint8_t bEpNum, uint16_t wAddr) -{ - _SetEPRxAddr(bEpNum, wAddr); -} -/******************************************************************************* -* Function Name : GetEPTxAddr -* Description : Returns the endpoint Tx buffer address. -* Input : bEpNum: Endpoint Number. -* Output : None. -* Return : Rx buffer address. -*******************************************************************************/ -uint16_t GetEPTxAddr(uint8_t bEpNum) -{ - return(_GetEPTxAddr(bEpNum)); -} -/******************************************************************************* -* Function Name : GetEPRxAddr. -* Description : Returns the endpoint Rx buffer address. -* Input : bEpNum: Endpoint Number. -* Output : None. -* Return : Rx buffer address. -*******************************************************************************/ -uint16_t GetEPRxAddr(uint8_t bEpNum) -{ - return(_GetEPRxAddr(bEpNum)); -} -/******************************************************************************* -* Function Name : SetEPTxCount. -* Description : Set the Tx count. -* Input : bEpNum: Endpoint Number. -* wCount: new count value. -* Output : None. -* Return : None. -*******************************************************************************/ -void SetEPTxCount(uint8_t bEpNum, uint16_t wCount) -{ - _SetEPTxCount(bEpNum, wCount); -} -/******************************************************************************* -* Function Name : SetEPCountRxReg. -* Description : Set the Count Rx Register value. -* Input : *pdwReg: point to the register. -* wCount: the new register value. -* Output : None. -* Return : None. -*******************************************************************************/ -void SetEPCountRxReg(uint32_t *pdwReg, uint16_t wCount) -{ - _SetEPCountRxReg(dwReg, wCount); -} -/******************************************************************************* -* Function Name : SetEPRxCount -* Description : Set the Rx count. -* Input : bEpNum: Endpoint Number. -* wCount: the new count value. -* Output : None. -* Return : None. -*******************************************************************************/ -void SetEPRxCount(uint8_t bEpNum, uint16_t wCount) -{ - _SetEPRxCount(bEpNum, wCount); -} -/******************************************************************************* -* Function Name : GetEPTxCount -* Description : Get the Tx count. -* Input : bEpNum: Endpoint Number. -* Output : None -* Return : Tx count value. -*******************************************************************************/ -uint16_t GetEPTxCount(uint8_t bEpNum) -{ - return(_GetEPTxCount(bEpNum)); -} -/******************************************************************************* -* Function Name : GetEPRxCount -* Description : Get the Rx count. -* Input : bEpNum: Endpoint Number. -* Output : None. -* Return : Rx count value. -*******************************************************************************/ -uint16_t GetEPRxCount(uint8_t bEpNum) -{ - return(_GetEPRxCount(bEpNum)); -} -/******************************************************************************* -* Function Name : SetEPDblBuffAddr -* Description : Set the addresses of the buffer 0 and 1. -* Input : bEpNum: Endpoint Number. -* wBuf0Addr: new address of buffer 0. -* wBuf1Addr: new address of buffer 1. -* Output : None. -* Return : None. -*******************************************************************************/ -void SetEPDblBuffAddr(uint8_t bEpNum, uint16_t wBuf0Addr, uint16_t wBuf1Addr) -{ - _SetEPDblBuffAddr(bEpNum, wBuf0Addr, wBuf1Addr); -} -/******************************************************************************* -* Function Name : SetEPDblBuf0Addr -* Description : Set the Buffer 1 address. -* Input : bEpNum: Endpoint Number -* wBuf0Addr: new address. -* Output : None. -* Return : None. -*******************************************************************************/ -void SetEPDblBuf0Addr(uint8_t bEpNum, uint16_t wBuf0Addr) -{ - _SetEPDblBuf0Addr(bEpNum, wBuf0Addr); -} -/******************************************************************************* -* Function Name : SetEPDblBuf1Addr -* Description : Set the Buffer 1 address. -* Input : bEpNum: Endpoint Number -* wBuf1Addr: new address. -* Output : None. -* Return : None. -*******************************************************************************/ -void SetEPDblBuf1Addr(uint8_t bEpNum, uint16_t wBuf1Addr) -{ - _SetEPDblBuf1Addr(bEpNum, wBuf1Addr); -} -/******************************************************************************* -* Function Name : GetEPDblBuf0Addr -* Description : Returns the address of the Buffer 0. -* Input : bEpNum: Endpoint Number. -* Output : None. -* Return : None. -*******************************************************************************/ -uint16_t GetEPDblBuf0Addr(uint8_t bEpNum) -{ - return(_GetEPDblBuf0Addr(bEpNum)); -} -/******************************************************************************* -* Function Name : GetEPDblBuf1Addr -* Description : Returns the address of the Buffer 1. -* Input : bEpNum: Endpoint Number. -* Output : None. -* Return : Address of the Buffer 1. -*******************************************************************************/ -uint16_t GetEPDblBuf1Addr(uint8_t bEpNum) -{ - return(_GetEPDblBuf1Addr(bEpNum)); -} -/******************************************************************************* -* Function Name : SetEPDblBuffCount -* Description : Set the number of bytes for a double Buffer -* endpoint. -* Input : bEpNum,bDir, wCount -* Output : None. -* Return : None. -*******************************************************************************/ -void SetEPDblBuffCount(uint8_t bEpNum, uint8_t bDir, uint16_t wCount) -{ - _SetEPDblBuffCount(bEpNum, bDir, wCount); -} -/******************************************************************************* -* Function Name : SetEPDblBuf0Count -* Description : Set the number of bytes in the buffer 0 of a double Buffer -* endpoint. -* Input : bEpNum, bDir, wCount -* Output : None. -* Return : None. -*******************************************************************************/ -void SetEPDblBuf0Count(uint8_t bEpNum, uint8_t bDir, uint16_t wCount) -{ - _SetEPDblBuf0Count(bEpNum, bDir, wCount); -} -/******************************************************************************* -* Function Name : SetEPDblBuf1Count -* Description : Set the number of bytes in the buffer 0 of a double Buffer -* endpoint. -* Input : bEpNum, bDir, wCount -* Output : None. -* Return : None. -*******************************************************************************/ -void SetEPDblBuf1Count(uint8_t bEpNum, uint8_t bDir, uint16_t wCount) -{ - _SetEPDblBuf1Count(bEpNum, bDir, wCount); -} -/******************************************************************************* -* Function Name : GetEPDblBuf0Count -* Description : Returns the number of byte received in the buffer 0 of a double -* Buffer endpoint. -* Input : bEpNum: Endpoint Number. -* Output : None. -* Return : Endpoint Buffer 0 count -*******************************************************************************/ -uint16_t GetEPDblBuf0Count(uint8_t bEpNum) -{ - return(_GetEPDblBuf0Count(bEpNum)); -} -/******************************************************************************* -* Function Name : GetEPDblBuf1Count -* Description : Returns the number of data received in the buffer 1 of a double -* Buffer endpoint. -* Input : bEpNum: Endpoint Number. -* Output : None. -* Return : Endpoint Buffer 1 count. -*******************************************************************************/ -uint16_t GetEPDblBuf1Count(uint8_t bEpNum) -{ - return(_GetEPDblBuf1Count(bEpNum)); -} -/******************************************************************************* -* Function Name : GetEPDblBufDir -* Description : gets direction of the double buffered endpoint -* Input : bEpNum: Endpoint Number. -* Output : None. -* Return : EP_DBUF_OUT, EP_DBUF_IN, -* EP_DBUF_ERR if the endpoint counter not yet programmed. -*******************************************************************************/ -EP_DBUF_DIR GetEPDblBufDir(uint8_t bEpNum) -{ - if ((uint16_t)(*_pEPRxCount(bEpNum) & 0xFC00) != 0) - return(EP_DBUF_OUT); - else if (((uint16_t)(*_pEPTxCount(bEpNum)) & 0x03FF) != 0) - return(EP_DBUF_IN); - else - return(EP_DBUF_ERR); -} -/******************************************************************************* -* Function Name : FreeUserBuffer -* Description : free buffer used from the application realizing it to the line - toggles bit SW_BUF in the double buffered endpoint register -* Input : bEpNum, bDir -* Output : None. -* Return : None. -*******************************************************************************/ -void FreeUserBuffer(uint8_t bEpNum, uint8_t bDir) -{ - if (bDir == EP_DBUF_OUT) - { /* OUT double buffered endpoint */ - _ToggleDTOG_TX(bEpNum); - } - else if (bDir == EP_DBUF_IN) - { /* IN double buffered endpoint */ - _ToggleDTOG_RX(bEpNum); - } -} - -/******************************************************************************* -* Function Name : ToWord -* Description : merge two byte in a word. -* Input : bh: byte high, bl: bytes low. -* Output : None. -* Return : resulted word. -*******************************************************************************/ -uint16_t ToWord(uint8_t bh, uint8_t bl) -{ - uint16_t wRet; - wRet = (uint16_t)bl | ((uint16_t)bh << 8); - return(wRet); -} -/******************************************************************************* -* Function Name : ByteSwap -* Description : Swap two byte in a word. -* Input : wSwW: word to Swap. -* Output : None. -* Return : resulted word. -*******************************************************************************/ -uint16_t ByteSwap(uint16_t wSwW) -{ - uint8_t bTemp; - uint16_t wRet; - bTemp = (uint8_t)(wSwW & 0xff); - wRet = (wSwW >> 8) | ((uint16_t)bTemp << 8); - return(wRet); -} - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/USB/usb_regs.h b/libraries/USB/usb_regs.h deleted file mode 100644 --- a/libraries/USB/usb_regs.h +++ /dev/null @@ -1,680 +0,0 @@ -/** - ****************************************************************************** - * @file usb_regs.h - * @author MCD Application Team - * @version V4.0.0 - * @date 28-August-2012 - * @brief Interface prototype functions to USB cell registers - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_REGS_H -#define __USB_REGS_H - -/* Includes ------------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -typedef enum _EP_DBUF_DIR -{ - /* double buffered endpoint direction */ - EP_DBUF_ERR, - EP_DBUF_OUT, - EP_DBUF_IN -}EP_DBUF_DIR; - -/* endpoint buffer number */ -enum EP_BUF_NUM -{ - EP_NOBUF, - EP_BUF0, - EP_BUF1 -}; - -/* Exported constants --------------------------------------------------------*/ -#define RegBase (0x40005C00L) /* USB_IP Peripheral Registers base address */ -#define PMAAddr (0x40006000L) /* USB_IP Packet Memory Area base address */ - -/******************************************************************************/ -/* General registers */ -/******************************************************************************/ - -/* Control register */ -#define CNTR ((__IO unsigned *)(RegBase + 0x40)) -/* Interrupt status register */ -#define ISTR ((__IO unsigned *)(RegBase + 0x44)) -/* Frame number register */ -#define FNR ((__IO unsigned *)(RegBase + 0x48)) -/* Device address register */ -#define DADDR ((__IO unsigned *)(RegBase + 0x4C)) -/* Buffer Table address register */ -#define BTABLE ((__IO unsigned *)(RegBase + 0x50)) -/******************************************************************************/ -/* Endpoint registers */ -/******************************************************************************/ -#define EP0REG ((__IO unsigned *)(RegBase)) /* endpoint 0 register address */ - -/* Endpoint Addresses (w/direction) */ -#define EP0_OUT ((uint8_t)0x00) -#define EP0_IN ((uint8_t)0x80) -#define EP1_OUT ((uint8_t)0x01) -#define EP1_IN ((uint8_t)0x81) -#define EP2_OUT ((uint8_t)0x02) -#define EP2_IN ((uint8_t)0x82) -#define EP3_OUT ((uint8_t)0x03) -#define EP3_IN ((uint8_t)0x83) -#define EP4_OUT ((uint8_t)0x04) -#define EP4_IN ((uint8_t)0x84) -#define EP5_OUT ((uint8_t)0x05) -#define EP5_IN ((uint8_t)0x85) -#define EP6_OUT ((uint8_t)0x06) -#define EP6_IN ((uint8_t)0x86) -#define EP7_OUT ((uint8_t)0x07) -#define EP7_IN ((uint8_t)0x87) - -/* endpoints enumeration */ -#define ENDP0 ((uint8_t)0) -#define ENDP1 ((uint8_t)1) -#define ENDP2 ((uint8_t)2) -#define ENDP3 ((uint8_t)3) -#define ENDP4 ((uint8_t)4) -#define ENDP5 ((uint8_t)5) -#define ENDP6 ((uint8_t)6) -#define ENDP7 ((uint8_t)7) - -/******************************************************************************/ -/* ISTR interrupt events */ -/******************************************************************************/ -#define ISTR_CTR (0x8000) /* Correct TRansfer (clear-only bit) */ -#define ISTR_DOVR (0x4000) /* DMA OVeR/underrun (clear-only bit) */ -#define ISTR_ERR (0x2000) /* ERRor (clear-only bit) */ -#define ISTR_WKUP (0x1000) /* WaKe UP (clear-only bit) */ -#define ISTR_SUSP (0x0800) /* SUSPend (clear-only bit) */ -#define ISTR_RESET (0x0400) /* RESET (clear-only bit) */ -#define ISTR_SOF (0x0200) /* Start Of Frame (clear-only bit) */ -#define ISTR_ESOF (0x0100) /* Expected Start Of Frame (clear-only bit) */ - - -#define ISTR_DIR (0x0010) /* DIRection of transaction (read-only bit) */ -#define ISTR_EP_ID (0x000F) /* EndPoint IDentifier (read-only bit) */ - -#define CLR_CTR (~ISTR_CTR) /* clear Correct TRansfer bit */ -#define CLR_DOVR (~ISTR_DOVR) /* clear DMA OVeR/underrun bit*/ -#define CLR_ERR (~ISTR_ERR) /* clear ERRor bit */ -#define CLR_WKUP (~ISTR_WKUP) /* clear WaKe UP bit */ -#define CLR_SUSP (~ISTR_SUSP) /* clear SUSPend bit */ -#define CLR_RESET (~ISTR_RESET) /* clear RESET bit */ -#define CLR_SOF (~ISTR_SOF) /* clear Start Of Frame bit */ -#define CLR_ESOF (~ISTR_ESOF) /* clear Expected Start Of Frame bit */ - -/******************************************************************************/ -/* CNTR control register bits definitions */ -/******************************************************************************/ -#define CNTR_CTRM (0x8000) /* Correct TRansfer Mask */ -#define CNTR_DOVRM (0x4000) /* DMA OVeR/underrun Mask */ -#define CNTR_ERRM (0x2000) /* ERRor Mask */ -#define CNTR_WKUPM (0x1000) /* WaKe UP Mask */ -#define CNTR_SUSPM (0x0800) /* SUSPend Mask */ -#define CNTR_RESETM (0x0400) /* RESET Mask */ -#define CNTR_SOFM (0x0200) /* Start Of Frame Mask */ -#define CNTR_ESOFM (0x0100) /* Expected Start Of Frame Mask */ - - -#define CNTR_RESUME (0x0010) /* RESUME request */ -#define CNTR_FSUSP (0x0008) /* Force SUSPend */ -#define CNTR_LPMODE (0x0004) /* Low-power MODE */ -#define CNTR_PDWN (0x0002) /* Power DoWN */ -#define CNTR_FRES (0x0001) /* Force USB RESet */ - -/******************************************************************************/ -/* FNR Frame Number Register bit definitions */ -/******************************************************************************/ -#define FNR_RXDP (0x8000) /* status of D+ data line */ -#define FNR_RXDM (0x4000) /* status of D- data line */ -#define FNR_LCK (0x2000) /* LoCKed */ -#define FNR_LSOF (0x1800) /* Lost SOF */ -#define FNR_FN (0x07FF) /* Frame Number */ -/******************************************************************************/ -/* DADDR Device ADDRess bit definitions */ -/******************************************************************************/ -#define DADDR_EF (0x80) -#define DADDR_ADD (0x7F) -/******************************************************************************/ -/* Endpoint register */ -/******************************************************************************/ -/* bit positions */ -#define EP_CTR_RX (0x8000) /* EndPoint Correct TRansfer RX */ -#define EP_DTOG_RX (0x4000) /* EndPoint Data TOGGLE RX */ -#define EPRX_STAT (0x3000) /* EndPoint RX STATus bit field */ -#define EP_SETUP (0x0800) /* EndPoint SETUP */ -#define EP_T_FIELD (0x0600) /* EndPoint TYPE */ -#define EP_KIND (0x0100) /* EndPoint KIND */ -#define EP_CTR_TX (0x0080) /* EndPoint Correct TRansfer TX */ -#define EP_DTOG_TX (0x0040) /* EndPoint Data TOGGLE TX */ -#define EPTX_STAT (0x0030) /* EndPoint TX STATus bit field */ -#define EPADDR_FIELD (0x000F) /* EndPoint ADDRess FIELD */ - -/* EndPoint REGister MASK (no toggle fields) */ -#define EPREG_MASK (EP_CTR_RX|EP_SETUP|EP_T_FIELD|EP_KIND|EP_CTR_TX|EPADDR_FIELD) - -/* EP_TYPE[1:0] EndPoint TYPE */ -#define EP_TYPE_MASK (0x0600) /* EndPoint TYPE Mask */ -#define EP_BULK (0x0000) /* EndPoint BULK */ -#define EP_CONTROL (0x0200) /* EndPoint CONTROL */ -#define EP_ISOCHRONOUS (0x0400) /* EndPoint ISOCHRONOUS */ -#define EP_INTERRUPT (0x0600) /* EndPoint INTERRUPT */ -#define EP_T_MASK (~EP_T_FIELD & EPREG_MASK) - - -/* EP_KIND EndPoint KIND */ -#define EPKIND_MASK (~EP_KIND & EPREG_MASK) - -/* STAT_TX[1:0] STATus for TX transfer */ -#define EP_TX_DIS (0x0000) /* EndPoint TX DISabled */ -#define EP_TX_STALL (0x0010) /* EndPoint TX STALLed */ -#define EP_TX_NAK (0x0020) /* EndPoint TX NAKed */ -#define EP_TX_VALID (0x0030) /* EndPoint TX VALID */ -#define EPTX_DTOG1 (0x0010) /* EndPoint TX Data TOGgle bit1 */ -#define EPTX_DTOG2 (0x0020) /* EndPoint TX Data TOGgle bit2 */ -#define EPTX_DTOGMASK (EPTX_STAT|EPREG_MASK) - -/* STAT_RX[1:0] STATus for RX transfer */ -#define EP_RX_DIS (0x0000) /* EndPoint RX DISabled */ -#define EP_RX_STALL (0x1000) /* EndPoint RX STALLed */ -#define EP_RX_NAK (0x2000) /* EndPoint RX NAKed */ -#define EP_RX_VALID (0x3000) /* EndPoint RX VALID */ -#define EPRX_DTOG1 (0x1000) /* EndPoint RX Data TOGgle bit1 */ -#define EPRX_DTOG2 (0x2000) /* EndPoint RX Data TOGgle bit1 */ -#define EPRX_DTOGMASK (EPRX_STAT|EPREG_MASK) -/* Exported macro ------------------------------------------------------------*/ -/* SetCNTR */ -#define _SetCNTR(wRegValue) (*CNTR = (uint16_t)wRegValue) - -/* SetISTR */ -#define _SetISTR(wRegValue) (*ISTR = (uint16_t)wRegValue) - -/* SetDADDR */ -#define _SetDADDR(wRegValue) (*DADDR = (uint16_t)wRegValue) - -/* SetBTABLE */ -#define _SetBTABLE(wRegValue)(*BTABLE = (uint16_t)(wRegValue & 0xFFF8)) - -/* GetCNTR */ -#define _GetCNTR() ((uint16_t) *CNTR) - -/* GetISTR */ -#define _GetISTR() ((uint16_t) *ISTR) - -/* GetFNR */ -#define _GetFNR() ((uint16_t) *FNR) - -/* GetDADDR */ -#define _GetDADDR() ((uint16_t) *DADDR) - -/* GetBTABLE */ -#define _GetBTABLE() ((uint16_t) *BTABLE) - -/* SetENDPOINT */ -#define _SetENDPOINT(bEpNum,wRegValue) (*(EP0REG + bEpNum)= \ - (uint16_t)wRegValue) - -/* GetENDPOINT */ -#define _GetENDPOINT(bEpNum) ((uint16_t)(*(EP0REG + bEpNum))) - -/******************************************************************************* -* Macro Name : SetEPType -* Description : sets the type in the endpoint register(bits EP_TYPE[1:0]) -* Input : bEpNum: Endpoint Number. -* wType -* Output : None. -* Return : None. -*******************************************************************************/ -#define _SetEPType(bEpNum,wType) (_SetENDPOINT(bEpNum,\ - ((_GetENDPOINT(bEpNum) & EP_T_MASK) | wType ))) - -/******************************************************************************* -* Macro Name : GetEPType -* Description : gets the type in the endpoint register(bits EP_TYPE[1:0]) -* Input : bEpNum: Endpoint Number. -* Output : None. -* Return : Endpoint Type -*******************************************************************************/ -#define _GetEPType(bEpNum) (_GetENDPOINT(bEpNum) & EP_T_FIELD) - -/******************************************************************************* -* Macro Name : SetEPTxStatus -* Description : sets the status for tx transfer (bits STAT_TX[1:0]). -* Input : bEpNum: Endpoint Number. -* wState: new state -* Output : None. -* Return : None. -*******************************************************************************/ -#define _SetEPTxStatus(bEpNum,wState) {\ - register uint16_t _wRegVal; \ - _wRegVal = _GetENDPOINT(bEpNum) & EPTX_DTOGMASK;\ - /* toggle first bit ? */ \ - if((EPTX_DTOG1 & wState)!= 0) \ - _wRegVal ^= EPTX_DTOG1; \ - /* toggle second bit ? */ \ - if((EPTX_DTOG2 & wState)!= 0) \ - _wRegVal ^= EPTX_DTOG2; \ - _SetENDPOINT(bEpNum, (_wRegVal | EP_CTR_RX|EP_CTR_TX)); \ - } /* _SetEPTxStatus */ - -/******************************************************************************* -* Macro Name : SetEPRxStatus -* Description : sets the status for rx transfer (bits STAT_TX[1:0]) -* Input : bEpNum: Endpoint Number. -* wState: new state. -* Output : None. -* Return : None. -*******************************************************************************/ -#define _SetEPRxStatus(bEpNum,wState) {\ - register uint16_t _wRegVal; \ - \ - _wRegVal = _GetENDPOINT(bEpNum) & EPRX_DTOGMASK;\ - /* toggle first bit ? */ \ - if((EPRX_DTOG1 & wState)!= 0) \ - _wRegVal ^= EPRX_DTOG1; \ - /* toggle second bit ? */ \ - if((EPRX_DTOG2 & wState)!= 0) \ - _wRegVal ^= EPRX_DTOG2; \ - _SetENDPOINT(bEpNum, (_wRegVal | EP_CTR_RX|EP_CTR_TX)); \ - } /* _SetEPRxStatus */ - -/******************************************************************************* -* Macro Name : SetEPRxTxStatus -* Description : sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0]) -* Input : bEpNum: Endpoint Number. -* wStaterx: new state. -* wStatetx: new state. -* Output : None. -* Return : None. -*******************************************************************************/ -#define _SetEPRxTxStatus(bEpNum,wStaterx,wStatetx) {\ - register uint32_t _wRegVal; \ - \ - _wRegVal = _GetENDPOINT(bEpNum) & (EPRX_DTOGMASK |EPTX_STAT) ;\ - /* toggle first bit ? */ \ - if((EPRX_DTOG1 & wStaterx)!= 0) \ - _wRegVal ^= EPRX_DTOG1; \ - /* toggle second bit ? */ \ - if((EPRX_DTOG2 & wStaterx)!= 0) \ - _wRegVal ^= EPRX_DTOG2; \ - /* toggle first bit ? */ \ - if((EPTX_DTOG1 & wStatetx)!= 0) \ - _wRegVal ^= EPTX_DTOG1; \ - /* toggle second bit ? */ \ - if((EPTX_DTOG2 & wStatetx)!= 0) \ - _wRegVal ^= EPTX_DTOG2; \ - _SetENDPOINT(bEpNum, _wRegVal | EP_CTR_RX|EP_CTR_TX); \ - } /* _SetEPRxTxStatus */ -/******************************************************************************* -* Macro Name : GetEPTxStatus / GetEPRxStatus -* Description : gets the status for tx/rx transfer (bits STAT_TX[1:0] -* /STAT_RX[1:0]) -* Input : bEpNum: Endpoint Number. -* Output : None. -* Return : status . -*******************************************************************************/ -#define _GetEPTxStatus(bEpNum) ((uint16_t)_GetENDPOINT(bEpNum) & EPTX_STAT) - -#define _GetEPRxStatus(bEpNum) ((uint16_t)_GetENDPOINT(bEpNum) & EPRX_STAT) - -/******************************************************************************* -* Macro Name : SetEPTxValid / SetEPRxValid -* Description : sets directly the VALID tx/rx-status into the enpoint register -* Input : bEpNum: Endpoint Number. -* Output : None. -* Return : None. -*******************************************************************************/ -#define _SetEPTxValid(bEpNum) (_SetEPTxStatus(bEpNum, EP_TX_VALID)) - -#define _SetEPRxValid(bEpNum) (_SetEPRxStatus(bEpNum, EP_RX_VALID)) - -/******************************************************************************* -* Macro Name : GetTxStallStatus / GetRxStallStatus. -* Description : checks stall condition in an endpoint. -* Input : bEpNum: Endpoint Number. -* Output : None. -* Return : TRUE = endpoint in stall condition. -*******************************************************************************/ -#define _GetTxStallStatus(bEpNum) (_GetEPTxStatus(bEpNum) \ - == EP_TX_STALL) -#define _GetRxStallStatus(bEpNum) (_GetEPRxStatus(bEpNum) \ - == EP_RX_STALL) - -/******************************************************************************* -* Macro Name : SetEP_KIND / ClearEP_KIND. -* Description : set & clear EP_KIND bit. -* Input : bEpNum: Endpoint Number. -* Output : None. -* Return : None. -*******************************************************************************/ -#define _SetEP_KIND(bEpNum) (_SetENDPOINT(bEpNum, \ - (EP_CTR_RX|EP_CTR_TX|((_GetENDPOINT(bEpNum) | EP_KIND) & EPREG_MASK)))) -#define _ClearEP_KIND(bEpNum) (_SetENDPOINT(bEpNum, \ - (EP_CTR_RX|EP_CTR_TX|(_GetENDPOINT(bEpNum) & EPKIND_MASK)))) - -/******************************************************************************* -* Macro Name : Set_Status_Out / Clear_Status_Out. -* Description : Sets/clears directly STATUS_OUT bit in the endpoint register. -* Input : bEpNum: Endpoint Number. -* Output : None. -* Return : None. -*******************************************************************************/ -#define _Set_Status_Out(bEpNum) _SetEP_KIND(bEpNum) -#define _Clear_Status_Out(bEpNum) _ClearEP_KIND(bEpNum) - -/******************************************************************************* -* Macro Name : SetEPDoubleBuff / ClearEPDoubleBuff. -* Description : Sets/clears directly EP_KIND bit in the endpoint register. -* Input : bEpNum: Endpoint Number. -* Output : None. -* Return : None. -*******************************************************************************/ -#define _SetEPDoubleBuff(bEpNum) _SetEP_KIND(bEpNum) -#define _ClearEPDoubleBuff(bEpNum) _ClearEP_KIND(bEpNum) - -/******************************************************************************* -* Macro Name : ClearEP_CTR_RX / ClearEP_CTR_TX. -* Description : Clears bit CTR_RX / CTR_TX in the endpoint register. -* Input : bEpNum: Endpoint Number. -* Output : None. -* Return : None. -*******************************************************************************/ -#define _ClearEP_CTR_RX(bEpNum) (_SetENDPOINT(bEpNum,\ - _GetENDPOINT(bEpNum) & 0x7FFF & EPREG_MASK)) -#define _ClearEP_CTR_TX(bEpNum) (_SetENDPOINT(bEpNum,\ - _GetENDPOINT(bEpNum) & 0xFF7F & EPREG_MASK)) - -/******************************************************************************* -* Macro Name : ToggleDTOG_RX / ToggleDTOG_TX . -* Description : Toggles DTOG_RX / DTOG_TX bit in the endpoint register. -* Input : bEpNum: Endpoint Number. -* Output : None. -* Return : None. -*******************************************************************************/ -#define _ToggleDTOG_RX(bEpNum) (_SetENDPOINT(bEpNum, \ - EP_CTR_RX|EP_CTR_TX|EP_DTOG_RX | (_GetENDPOINT(bEpNum) & EPREG_MASK))) -#define _ToggleDTOG_TX(bEpNum) (_SetENDPOINT(bEpNum, \ - EP_CTR_RX|EP_CTR_TX|EP_DTOG_TX | (_GetENDPOINT(bEpNum) & EPREG_MASK))) - -/******************************************************************************* -* Macro Name : ClearDTOG_RX / ClearDTOG_TX. -* Description : Clears DTOG_RX / DTOG_TX bit in the endpoint register. -* Input : bEpNum: Endpoint Number. -* Output : None. -* Return : None. -*******************************************************************************/ -#define _ClearDTOG_RX(bEpNum) if((_GetENDPOINT(bEpNum) & EP_DTOG_RX) != 0)\ - _ToggleDTOG_RX(bEpNum) -#define _ClearDTOG_TX(bEpNum) if((_GetENDPOINT(bEpNum) & EP_DTOG_TX) != 0)\ - _ToggleDTOG_TX(bEpNum) -/******************************************************************************* -* Macro Name : SetEPAddress. -* Description : Sets address in an endpoint register. -* Input : bEpNum: Endpoint Number. -* bAddr: Address. -* Output : None. -* Return : None. -*******************************************************************************/ -#define _SetEPAddress(bEpNum,bAddr) _SetENDPOINT(bEpNum,\ - EP_CTR_RX|EP_CTR_TX|(_GetENDPOINT(bEpNum) & EPREG_MASK) | bAddr) - -/******************************************************************************* -* Macro Name : GetEPAddress. -* Description : Gets address in an endpoint register. -* Input : bEpNum: Endpoint Number. -* Output : None. -* Return : None. -*******************************************************************************/ -#define _GetEPAddress(bEpNum) ((uint8_t)(_GetENDPOINT(bEpNum) & EPADDR_FIELD)) - -#define _pEPTxAddr(bEpNum) ((uint32_t *)((_GetBTABLE()+bEpNum*8 )*2 + PMAAddr)) -#define _pEPTxCount(bEpNum) ((uint32_t *)((_GetBTABLE()+bEpNum*8+2)*2 + PMAAddr)) -#define _pEPRxAddr(bEpNum) ((uint32_t *)((_GetBTABLE()+bEpNum*8+4)*2 + PMAAddr)) -#define _pEPRxCount(bEpNum) ((uint32_t *)((_GetBTABLE()+bEpNum*8+6)*2 + PMAAddr)) - -/******************************************************************************* -* Macro Name : SetEPTxAddr / SetEPRxAddr. -* Description : sets address of the tx/rx buffer. -* Input : bEpNum: Endpoint Number. -* wAddr: address to be set (must be word aligned). -* Output : None. -* Return : None. -*******************************************************************************/ -#define _SetEPTxAddr(bEpNum,wAddr) (*_pEPTxAddr(bEpNum) = ((wAddr >> 1) << 1)) -#define _SetEPRxAddr(bEpNum,wAddr) (*_pEPRxAddr(bEpNum) = ((wAddr >> 1) << 1)) - -/******************************************************************************* -* Macro Name : GetEPTxAddr / GetEPRxAddr. -* Description : Gets address of the tx/rx buffer. -* Input : bEpNum: Endpoint Number. -* Output : None. -* Return : address of the buffer. -*******************************************************************************/ -#define _GetEPTxAddr(bEpNum) ((uint16_t)*_pEPTxAddr(bEpNum)) -#define _GetEPRxAddr(bEpNum) ((uint16_t)*_pEPRxAddr(bEpNum)) - -/******************************************************************************* -* Macro Name : SetEPCountRxReg. -* Description : Sets counter of rx buffer with no. of blocks. -* Input : pdwReg: pointer to counter. -* wCount: Counter. -* Output : None. -* Return : None. -*******************************************************************************/ -#define _BlocksOf32(dwReg,wCount,wNBlocks) {\ - wNBlocks = wCount >> 5;\ - if((wCount & 0x1f) == 0)\ - wNBlocks--;\ - *pdwReg = (uint32_t)((wNBlocks << 10) | 0x8000);\ - }/* _BlocksOf32 */ - -#define _BlocksOf2(dwReg,wCount,wNBlocks) {\ - wNBlocks = wCount >> 1;\ - if((wCount & 0x1) != 0)\ - wNBlocks++;\ - *pdwReg = (uint32_t)(wNBlocks << 10);\ - }/* _BlocksOf2 */ - -#define _SetEPCountRxReg(dwReg,wCount) {\ - uint16_t wNBlocks;\ - if(wCount > 62){_BlocksOf32(dwReg,wCount,wNBlocks);}\ - else {_BlocksOf2(dwReg,wCount,wNBlocks);}\ - }/* _SetEPCountRxReg */ - - - -#define _SetEPRxDblBuf0Count(bEpNum,wCount) {\ - uint32_t *pdwReg = _pEPTxCount(bEpNum); \ - _SetEPCountRxReg(pdwReg, wCount);\ - } -/******************************************************************************* -* Macro Name : SetEPTxCount / SetEPRxCount. -* Description : sets counter for the tx/rx buffer. -* Input : bEpNum: endpoint number. -* wCount: Counter value. -* Output : None. -* Return : None. -*******************************************************************************/ -#define _SetEPTxCount(bEpNum,wCount) (*_pEPTxCount(bEpNum) = wCount) -#define _SetEPRxCount(bEpNum,wCount) {\ - uint32_t *pdwReg = _pEPRxCount(bEpNum); \ - _SetEPCountRxReg(pdwReg, wCount);\ - } -/******************************************************************************* -* Macro Name : GetEPTxCount / GetEPRxCount. -* Description : gets counter of the tx buffer. -* Input : bEpNum: endpoint number. -* Output : None. -* Return : Counter value. -*******************************************************************************/ -#define _GetEPTxCount(bEpNum)((uint16_t)(*_pEPTxCount(bEpNum)) & 0x3ff) -#define _GetEPRxCount(bEpNum)((uint16_t)(*_pEPRxCount(bEpNum)) & 0x3ff) - -/******************************************************************************* -* Macro Name : SetEPDblBuf0Addr / SetEPDblBuf1Addr. -* Description : Sets buffer 0/1 address in a double buffer endpoint. -* Input : bEpNum: endpoint number. -* : wBuf0Addr: buffer 0 address. -* Output : None. -* Return : None. -*******************************************************************************/ -#define _SetEPDblBuf0Addr(bEpNum,wBuf0Addr) {_SetEPTxAddr(bEpNum, wBuf0Addr);} -#define _SetEPDblBuf1Addr(bEpNum,wBuf1Addr) {_SetEPRxAddr(bEpNum, wBuf1Addr);} - -/******************************************************************************* -* Macro Name : SetEPDblBuffAddr. -* Description : Sets addresses in a double buffer endpoint. -* Input : bEpNum: endpoint number. -* : wBuf0Addr: buffer 0 address. -* : wBuf1Addr = buffer 1 address. -* Output : None. -* Return : None. -*******************************************************************************/ -#define _SetEPDblBuffAddr(bEpNum,wBuf0Addr,wBuf1Addr) { \ - _SetEPDblBuf0Addr(bEpNum, wBuf0Addr);\ - _SetEPDblBuf1Addr(bEpNum, wBuf1Addr);\ - } /* _SetEPDblBuffAddr */ - -/******************************************************************************* -* Macro Name : GetEPDblBuf0Addr / GetEPDblBuf1Addr. -* Description : Gets buffer 0/1 address of a double buffer endpoint. -* Input : bEpNum: endpoint number. -* Output : None. -* Return : None. -*******************************************************************************/ -#define _GetEPDblBuf0Addr(bEpNum) (_GetEPTxAddr(bEpNum)) -#define _GetEPDblBuf1Addr(bEpNum) (_GetEPRxAddr(bEpNum)) - -/******************************************************************************* -* Macro Name : SetEPDblBuffCount / SetEPDblBuf0Count / SetEPDblBuf1Count. -* Description : Gets buffer 0/1 address of a double buffer endpoint. -* Input : bEpNum: endpoint number. -* : bDir: endpoint dir EP_DBUF_OUT = OUT -* EP_DBUF_IN = IN -* : wCount: Counter value -* Output : None. -* Return : None. -*******************************************************************************/ -#define _SetEPDblBuf0Count(bEpNum, bDir, wCount) { \ - if(bDir == EP_DBUF_OUT)\ - /* OUT endpoint */ \ - {_SetEPRxDblBuf0Count(bEpNum,wCount);} \ - else if(bDir == EP_DBUF_IN)\ - /* IN endpoint */ \ - *_pEPTxCount(bEpNum) = (uint32_t)wCount; \ - } /* SetEPDblBuf0Count*/ - -#define _SetEPDblBuf1Count(bEpNum, bDir, wCount) { \ - if(bDir == EP_DBUF_OUT)\ - /* OUT endpoint */ \ - {_SetEPRxCount(bEpNum,wCount);}\ - else if(bDir == EP_DBUF_IN)\ - /* IN endpoint */\ - *_pEPRxCount(bEpNum) = (uint32_t)wCount; \ - } /* SetEPDblBuf1Count */ - -#define _SetEPDblBuffCount(bEpNum, bDir, wCount) {\ - _SetEPDblBuf0Count(bEpNum, bDir, wCount); \ - _SetEPDblBuf1Count(bEpNum, bDir, wCount); \ - } /* _SetEPDblBuffCount */ - -/******************************************************************************* -* Macro Name : GetEPDblBuf0Count / GetEPDblBuf1Count. -* Description : Gets buffer 0/1 rx/tx counter for double buffering. -* Input : bEpNum: endpoint number. -* Output : None. -* Return : None. -*******************************************************************************/ -#define _GetEPDblBuf0Count(bEpNum) (_GetEPTxCount(bEpNum)) -#define _GetEPDblBuf1Count(bEpNum) (_GetEPRxCount(bEpNum)) - - -/* External variables --------------------------------------------------------*/ -extern __IO uint16_t wIstr; /* ISTR register last read value */ - -/* Exported functions ------------------------------------------------------- */ -void SetCNTR(uint16_t /*wRegValue*/); -void SetISTR(uint16_t /*wRegValue*/); -void SetDADDR(uint16_t /*wRegValue*/); -void SetBTABLE(uint16_t /*wRegValue*/); -void SetBTABLE(uint16_t /*wRegValue*/); -uint16_t GetCNTR(void); -uint16_t GetISTR(void); -uint16_t GetFNR(void); -uint16_t GetDADDR(void); -uint16_t GetBTABLE(void); -void SetENDPOINT(uint8_t /*bEpNum*/, uint16_t /*wRegValue*/); -uint16_t GetENDPOINT(uint8_t /*bEpNum*/); -void SetEPType(uint8_t /*bEpNum*/, uint16_t /*wType*/); -uint16_t GetEPType(uint8_t /*bEpNum*/); -void SetEPTxStatus(uint8_t /*bEpNum*/, uint16_t /*wState*/); -void SetEPRxStatus(uint8_t /*bEpNum*/, uint16_t /*wState*/); -void SetDouBleBuffEPStall(uint8_t /*bEpNum*/, uint8_t bDir); -uint16_t GetEPTxStatus(uint8_t /*bEpNum*/); -uint16_t GetEPRxStatus(uint8_t /*bEpNum*/); -void SetEPTxValid(uint8_t /*bEpNum*/); -void SetEPRxValid(uint8_t /*bEpNum*/); -uint16_t GetTxStallStatus(uint8_t /*bEpNum*/); -uint16_t GetRxStallStatus(uint8_t /*bEpNum*/); -void SetEP_KIND(uint8_t /*bEpNum*/); -void ClearEP_KIND(uint8_t /*bEpNum*/); -void Set_Status_Out(uint8_t /*bEpNum*/); -void Clear_Status_Out(uint8_t /*bEpNum*/); -void SetEPDoubleBuff(uint8_t /*bEpNum*/); -void ClearEPDoubleBuff(uint8_t /*bEpNum*/); -void ClearEP_CTR_RX(uint8_t /*bEpNum*/); -void ClearEP_CTR_TX(uint8_t /*bEpNum*/); -void ToggleDTOG_RX(uint8_t /*bEpNum*/); -void ToggleDTOG_TX(uint8_t /*bEpNum*/); -void ClearDTOG_RX(uint8_t /*bEpNum*/); -void ClearDTOG_TX(uint8_t /*bEpNum*/); -void SetEPAddress(uint8_t /*bEpNum*/, uint8_t /*bAddr*/); -uint8_t GetEPAddress(uint8_t /*bEpNum*/); -void SetEPTxAddr(uint8_t /*bEpNum*/, uint16_t /*wAddr*/); -void SetEPRxAddr(uint8_t /*bEpNum*/, uint16_t /*wAddr*/); -uint16_t GetEPTxAddr(uint8_t /*bEpNum*/); -uint16_t GetEPRxAddr(uint8_t /*bEpNum*/); -void SetEPCountRxReg(uint32_t * /*pdwReg*/, uint16_t /*wCount*/); -void SetEPTxCount(uint8_t /*bEpNum*/, uint16_t /*wCount*/); -void SetEPRxCount(uint8_t /*bEpNum*/, uint16_t /*wCount*/); -uint16_t GetEPTxCount(uint8_t /*bEpNum*/); -uint16_t GetEPRxCount(uint8_t /*bEpNum*/); -void SetEPDblBuf0Addr(uint8_t /*bEpNum*/, uint16_t /*wBuf0Addr*/); -void SetEPDblBuf1Addr(uint8_t /*bEpNum*/, uint16_t /*wBuf1Addr*/); -void SetEPDblBuffAddr(uint8_t /*bEpNum*/, uint16_t /*wBuf0Addr*/, uint16_t /*wBuf1Addr*/); -uint16_t GetEPDblBuf0Addr(uint8_t /*bEpNum*/); -uint16_t GetEPDblBuf1Addr(uint8_t /*bEpNum*/); -void SetEPDblBuffCount(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/); -void SetEPDblBuf0Count(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/); -void SetEPDblBuf1Count(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/); -uint16_t GetEPDblBuf0Count(uint8_t /*bEpNum*/); -uint16_t GetEPDblBuf1Count(uint8_t /*bEpNum*/); -EP_DBUF_DIR GetEPDblBufDir(uint8_t /*bEpNum*/); -void FreeUserBuffer(uint8_t bEpNum/*bEpNum*/, uint8_t bDir); -uint16_t ToWord(uint8_t, uint8_t); -uint16_t ByteSwap(uint16_t); - -#endif /* __USB_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/USB/usb_sil.c b/libraries/USB/usb_sil.c deleted file mode 100644 --- a/libraries/USB/usb_sil.c +++ /dev/null @@ -1,103 +0,0 @@ -/** - ****************************************************************************** - * @file usb_sil.c - * @author MCD Application Team - * @version V4.0.0 - * @date 28-August-2012 - * @brief Simplified Interface Layer for Global Initialization and Endpoint - * Rea/Write operations. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - - -/* Includes ------------------------------------------------------------------*/ -#include "usb_lib.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Extern variables ----------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/******************************************************************************* -* Function Name : USB_SIL_Init -* Description : Initialize the USB Device IP and the Endpoint 0. -* Input : None. -* Output : None. -* Return : Status. -*******************************************************************************/ -uint32_t USB_SIL_Init(void) -{ - /* USB interrupts initialization */ - /* clear pending interrupts */ - _SetISTR(0); - wInterrupt_Mask = IMR_MSK; - /* set interrupts mask */ - _SetCNTR(wInterrupt_Mask); - return 0; -} - -/******************************************************************************* -* Function Name : USB_SIL_Write -* Description : Write a buffer of data to a selected endpoint. -* Input : - bEpAddr: The address of the non control endpoint. -* - pBufferPointer: The pointer to the buffer of data to be written -* to the endpoint. -* - wBufferSize: Number of data to be written (in bytes). -* Output : None. -* Return : Status. -*******************************************************************************/ -uint32_t USB_SIL_Write(uint8_t bEpAddr, uint8_t* pBufferPointer, uint32_t wBufferSize) -{ - /* Use the memory interface function to write to the selected endpoint */ - UserToPMABufferCopy(pBufferPointer, GetEPTxAddr(bEpAddr & 0x7F), wBufferSize); - - /* Update the data length in the control register */ - SetEPTxCount((bEpAddr & 0x7F), wBufferSize); - - return 0; -} - -/******************************************************************************* -* Function Name : USB_SIL_Read -* Description : Write a buffer of data to a selected endpoint. -* Input : - bEpAddr: The address of the non control endpoint. -* - pBufferPointer: The pointer to which will be saved the -* received data buffer. -* Output : None. -* Return : Number of received data (in Bytes). -*******************************************************************************/ -uint32_t USB_SIL_Read(uint8_t bEpAddr, uint8_t* pBufferPointer) -{ - uint32_t DataLength = 0; - - /* Get the number of received data on the selected Endpoint */ - DataLength = GetEPRxCount(bEpAddr & 0x7F); - - /* Use the memory interface function to write to the selected endpoint */ - PMAToUserBufferCopy(pBufferPointer, GetEPRxAddr(bEpAddr & 0x7F), DataLength); - - /* Return the number of received data */ - return DataLength; -} - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/USB/usb_sil.h b/libraries/USB/usb_sil.h deleted file mode 100644 --- a/libraries/USB/usb_sil.h +++ /dev/null @@ -1,47 +0,0 @@ -/** - ****************************************************************************** - * @file usb_sil.h - * @author MCD Application Team - * @version V4.0.0 - * @date 28-August-2012 - * @brief Simplified Interface Layer function prototypes. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_SIL_H -#define __USB_SIL_H - -/* Includes ------------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -uint32_t USB_SIL_Init(void); -uint32_t USB_SIL_Write(uint8_t bEpAddr, uint8_t* pBufferPointer, uint32_t wBufferSize); -uint32_t USB_SIL_Read(uint8_t bEpAddr, uint8_t* pBufferPointer); - -/* External variables --------------------------------------------------------*/ - -#endif /* __USB_SIL_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/USB/usb_type.h b/libraries/USB/usb_type.h deleted file mode 100644 --- a/libraries/USB/usb_type.h +++ /dev/null @@ -1,54 +0,0 @@ -/** - ****************************************************************************** - * @file usb_type.h - * @author MCD Application Team - * @version V4.0.0 - * @date 28-August-2012 - * @brief Type definitions used by the USB Library - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_TYPE_H -#define __USB_TYPE_H - -/* Includes ------------------------------------------------------------------*/ -#include "usb_conf.h" - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -#ifndef NULL -#define NULL ((void *)0) -#endif - -typedef enum -{ - FALSE = 0, TRUE = !FALSE -} -bool; - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -/* External variables --------------------------------------------------------*/ - -#endif /* __USB_TYPE_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/main.c b/main.c --- a/main.c +++ b/main.c @@ -1,12 +1,12 @@ #include "main.h" -#include "stm32f0xx_hal.h" +#include "stm32f0xx_hal_conf.h" #include "usb_device.h" #include "ssd1306.h" #include "config.h" #include "eeprom_min.h" #include "gpio.h" +#include "clock.h" #include "spi.h" -#include "clock.h" // USB includes //#include "hw_config.h" diff --git a/main.h b/main.h --- a/main.h +++ b/main.h @@ -1,8 +1,6 @@ #ifndef __MAIN_H #define __MAIN_H -#include "stm32f0xx.h" - void TimingDelay_Decrement(void); void delay(__IO uint32_t nTime);