diff --git a/main.c b/main.c
--- a/main.c
+++ b/main.c
@@ -27,9 +27,9 @@ int main(void)
     init_gpio();
     init_spi();
 
-    //ssd1306_Init();
-    //SSD1303_DrawPoint(3,3,1);
-    //SSD1303_DrawPoint(5,5,0);
+    ssd1306_Init();
+    ssd1306_DrawPoint(3,3,1);
+    ssd1306_DrawPoint(5,5,0);
 
     GPIO_SetBits(LED_POWER);
     Delay(500);
@@ -37,6 +37,7 @@ int main(void)
 
     while(1)
     {  
+        ssd1306_DrawPoint(5,5,0);
         GPIO_SetBits(LED_POWER);
         Delay(150);
         GPIO_ResetBits(LED_POWER);
diff --git a/libraries/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h b/system_stm32l1xx.h
rename from libraries/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h
rename to system_stm32l1xx.h
diff --git a/system_stm32l1xx.c b/system_stm32l1xx_4meg_extxtal.c
rename from system_stm32l1xx.c
rename to system_stm32l1xx_4meg_extxtal.c
--- a/system_stm32l1xx.c
+++ b/system_stm32l1xx_4meg_extxtal.c
@@ -3,7 +3,7 @@
   * @file    system_stm32l1xx.c
   * @author  MCD Application Team
   * @version V1.2.0
-  * @date    10-July-2014
+  * @date    11-July-2014
   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
   *          This file contains the system clock configuration for STM32L1xx Ultra
   *          Low power devices, and is generated by the clock configuration 
@@ -55,11 +55,11 @@
   *----------------------------------------------------------------------------- 
   *        APB2 Prescaler               | 1
   *----------------------------------------------------------------------------- 
-  *        HSE Frequency                | 8000000 Hz
+  *        HSE Frequency                | 4000000 Hz
   *----------------------------------------------------------------------------- 
   *        PLL DIV                      | 3
   *----------------------------------------------------------------------------- 
-  *        PLL MUL                      | 12
+  *        PLL MUL                      | 24
   *----------------------------------------------------------------------------- 
   *        VDD                          | 3.3 V
   *----------------------------------------------------------------------------- 
@@ -353,7 +353,7 @@ static void SetSysClock(void)
     /*  PLL configuration */
     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL |
                                         RCC_CFGR_PLLDIV));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL12 | RCC_CFGR_PLLDIV3);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL24 | RCC_CFGR_PLLDIV3);
 
     /* Enable PLL */
     RCC->CR |= RCC_CR_PLLON;