+

CMSIS-CORE uses the common coding rules for CMSIS components that are documented under Introduction .

+

CMSIS-CORE violates the following MISRA-C:2004 rules:

+

Required Rule 8.5, object/function definition in header file.
+ Violated since function definitions in header files are used to allow 'inlining'.

+

Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Violated since unions are used for effective representation of core registers.

+

Advisory Rule 19.7, Function-like macro defined.
+ Violated since function-like macros are used to allow more efficient code.

+

CMSIS Register Name	Cortex-M3 and Cortex-M4	Cortex-M0 and Cortex-M0+	Register Name
Nested Vectored Interrupt Controller (NVIC) Register Access
NVIC->ISER[]	NVIC_ISER0..7	ISER	Interrupt Set-Enable Registers
NVIC->ICER[]	NVIC_ICER0..7	ICER	Interrupt Clear-Enable Registers
NVIC->ISPR[]	NVIC_ISPR0..7	ISPR	Interrupt Set-Pending Registers
NVIC->ICPR[]	NVIC_ICPR0..7	ICPR	Interrupt Clear-Pending Registers
NVIC->IABR[]	NVIC_IABR0..7	-	Interrupt Active Bit Register
NVIC->IP[]	NVIC_IPR0..59	IPR0..7	Interrupt Priority Register
NVIC->STIR	STIR	-	Software Triggered Interrupt Register
System Control Block (SCB) Register Access
SCB->CPUID	CPUID	CPUID	CPUID Base Register
SCB->ICSR	ICSR	ICSR	Interrupt Control and State Register
SCB->VTOR	VTOR	-	Vector Table Offset Register
SCB->AIRCR	AIRCR	AIRCR	Application Interrupt and Reset Control Register
SCB->SCR	SCR	SCR	System Control Register
SCB->CCR	CCR	CCR	Configuration and Control Register
SCB->SHP[]	SHPR1..3	SHPR2..3	System Handler Priority Registers
SCB->SHCSR	SHCSR	SHCSR	System Handler Control and State Register
SCB->CFSR	CFSR	-	Configurable Fault Status Registers
SCB->HFSR	HFSR	-	HardFault Status Register
SCB->DFSR	DFSR	-	Debug Fault Status Register
SCB->MMFAR	MMFAR	-	MemManage Fault Address Register
SCB->BFAR	BFAR	-	BusFault Address Register
SCB->AFSR	AFSR	-	Auxiliary Fault Status Register
SCB->PFR[]	ID_PFR0..1	-	Processor Feature Registers
SCB->DFR	ID_DFR0	-	Debug Feature Register
SCB->ADR	ID_AFR0	-	Auxiliary Feature Register
SCB->MMFR[]	ID_MMFR0..3	-	Memory Model Feature Registers
SCB->ISAR[]	ID_ISAR0..4	-	Instruction Set Attributes Registers
SCB->CPACR	CPACR	-	Coprocessor Access Control Register
System Control and ID Registers not in the SCB (SCnSCB) Register Access
SCnSCB->ICTR	ICTR	-	Interrupt Controller Type Register
SCnSCB->ACTLR	ACTLR	-	Auxiliary Control Register
System Timer (SysTick) Control and Status Register Access
SysTick->CTRL	STCSR	SYST_CSR	SysTick Control and Status Register
SysTick->LOAD	STRVR	SYST_RVR	SysTick Reload Value Register
SysTick->VAL	STCVR	SYST_CVR	SysTick Current Value Register
SysTick->CALIB	STCR	SYST_CALIB	SysTick Calibaration Value Register
Data Watchpoint and Trace (DWT) Register Access
DWT->CTRL	DWT_CTRL	-	Control Register
DWT->CYCCNT	DWT_CYCCNT	-	Cycle Count Register
DWT->CPICNT	DWT_CPICNT	-	CPI Count Register
DWT->EXCCNT	DWT_EXCCNT	-	Exception Overhead Count Register
DWT->SLEEPCNT	DWT_SLEEPCNT	-	Sleep Count Register
DWT->LSUCNT	DWT_LSUCNT	-	LSU Count Register
DWT->FOLDCNT	DWT_FOLDCNT	-	Folded-instruction Count Register
DWT->PCSR	DWT_PCSR	-	Program Counter Sample Register
DWT->COMP0..3	DWT_COMP0..3	-	Comparator Register 0..3
DWT->MASK0..3	DWT_MASK0..3	-	Mask Register 0..3
DWT->FUNCTION0..3	DWT_FUNCTION0..3	-	Function Register 0..3
Instrumentation Trace Macrocell (ITM) Register Access
ITM->PORT[]	ITM_STIM0..31	-	Stimulus Port Registers
ITM->TER	ITM_TER	-	Trace Enable Register
ITM->TPR	ITM_TPR	-	ITM Trace Privilege Register
ITM->TCR	ITM_TCR	-	Trace Control Register
Trace Port Interface (TPIU) Register Access
TPI->SSPSR	TPIU_SSPR	-	Supported Parallel Port Size Register
TPI->CSPSR	TPIU_CSPSR	-	Current Parallel Port Size Register
TPI->ACPR	TPIU_ACPR	-	Asynchronous Clock Prescaler Register
TPI->SPPR	TPIU_SPPR	-	Selected Pin Protocol Register
TPI->FFSR	TPIU_FFSR	-	Formatter and Flush Status Register
TPI->FFCR	TPIU_FFCR	-	Formatter and Flush Control Register
TPI->FSCR	TPIU_FSCR	-	Formatter Synchronization Counter Register
TPI->TRIGGER	TRIGGER	-	TRIGGER
TPI->FIFO0	FIFO data 0	-	Integration ETM Data
TPI->ITATBCTR2	ITATBCTR2	-	ITATBCTR2
TPI->ITATBCTR0	ITATBCTR0	-	ITATBCTR0
TPI->FIFO1	FIFO data 1	-	Integration ITM Data
TPI->ITCTRL	TPIU_ITCTRL	-	Integration Mode Control
TPI->CLAIMSET	CLAIMSET	-	Claim tag set
TPI->CLAIMCLR	CLAIMCLR	-	Claim tag clear
TPI->DEVID	TPIU_DEVID	-	TPIU_DEVID
TPI->DEVTYPE	TPIU_DEVTYPE	-	TPIU_DEVTYPE
Memory Protection Unit (MPU) Register Access
MPU->TYPE	MPU_TYPE	-	MPU Type Register
MPU->CTRL	MPU_CTRL	-	MPU Control Register
MPU->RNR	MPU_RNR	-	MPU Region Number Register
MPU->RBAR	MPU_RBAR	-	MPU Region Base Address Register
MPU->RASR	MPU_RASR	-	MPU Region Attribute and Size Register
MPU->RBAR_A1..3	MPU_RBAR_A1..3	-	MPU alias Register
MPU->RSAR_A1..3	MPU_RSAR_A1..3	-	MPU alias Register
Floating Point Unit (FPU) Register Access [only Cortex-M4 with FPU]
FPU->FPCCR	FPCCR	-	FP Context Control Register
FPU->FPCAR	FPCAR	-	FP Context Address Register
FPU->FPDSCR	FPDSCR	-	FP Default Status Control Register
FPU->MVFR0..1	MVFR0..1	-	Media and VFP Feature Registers

Template File	Description
".\Device_Template_Vendor\Vendor\Device\Source\ARM\startup_Device.s"	Startup file template for ARM C/C++ Compiler.
".\Device_Template_Vendor\Vendor\Device\Source\GCC\startup_Device.s"	Startup file template for GNU GCC ARM Embedded Compiler.
".\Device_Template_Vendor\Vendor\Device\Source\G++\startup_Device.s"	Startup file template for GNU Sourcery G++ Compiler.
".\Device_Template_Vendor\Vendor\Device\Source\IAR\startup_Device.s"	Startup file template for IAR C/C++ Compiler.
".\Device_Template_Vendor\Vendor\Device\Source\system_Device.c"	Generic system_Device.c file for system configuration (i.e. processor clock and memory bus system).
".\Device_Template_Vendor\Vendor\Device\Include\Device.h"	Generic device header file. Needs to be extended with the device-specific peripheral registers. Optionally functions that access the peripherals can be part of that file.
".\Device_Template_Vendor\Vendor\Device\Include\system_Device.h"	Generic system device configuration include file.

Core Header Files	Description
core_<cpu>.h	Defines the core peripherals and provides helper functions that access the core registers. This file is available for all supported processors: + core_cm0.h: for the Cortex-M0 processor + core_cm0plus.h: for the Cortex-M0+ processor + core_cm3.h: for the Cortex-M0 processor + core_cm4.h: for the Cortex-M0 processor + core_sc000.h: for the SecurCore SC000 processor + core_sc300.h: for the SecurCore SC300 processor + +
core_cmInstr.h	Defines intrinsic functions to access special Cortex-M instructions.
core_cmFunc.h	Defines functions to access the Cortex-M core peripherals.
core_cm4_simd.h	Defines intrinsic functions to access the Cortex-M4 SIMD instructions.

Placeholder	Replaced with
<Device>	the specific device name or device family name; i.e. LPC17xx.
<DeviceInterrupt>	a specific interrupt name of the device; i.e. TIM1 for Timer 1.
<DeviceAbbreviation>	short name or abbreviation of the device family; i.e. LPC.
Cortex-M#	the specific Cortex-M processor name; i.e. Cortex-M3.

Folder	Processor	Description
".\Device\ARM\ARMCM0"	Cortex-M0	Contains Include and Source template files configured for the Cortex-M0 processor. The device name is ARMCM0 and the name of the Device Header File <device.h> is <ARMCM0.h>.
".\Device\ARM\ARMCM0plus"	Cortex-M0+	Contains Include and Source template files configured for the Cortex-M0+ processor. The device name is ARMCM0plus and the name of the Device Header File <device.h> is <ARMCM0plus.h>.
".\Device\ARM\ARMCM3"	Cortex-M3	Contains Include and Source template files configured for the Cortex-M3 processor. The device name is ARMCM3 and the name of the Device Header File <device.h> is <ARMCM3.h>.
".\Device\ARM\ARMCM4"	Cortex-M4	Contains Include and Source template files configured for the Cortex-M4 processor. The device name is ARMCM4 and the name of the Device Header File <device.h> is <ARMCM4.h>.
".\Device\ARM\ARMSC000"	SecurCore SC000	Contains Include and Source template files configured for the SecurCore SC000 processor. The device name is ARMSC000 and the name of the Device Header File <device.h> is <ARMSC000.h>.
".\Device\ARM\ARMSC300"	SecurCore SC300	Contains Include and Source template files configured for the SecurCore SC300 processor. The device name is ARMSC300 and the name of the Device Header File <device.h> is <ARMSC300.h>.

File	Description
".\ARM\Startup\ST\STM32F10x\startup_stm32f10x_cl.s"	Startup File startup_<device>.s for the STM32F10x Connectivity Line device variants.
".\ARM\Startup\ST\STM32F10x\system_stmf10x.c"	System Configuration Files system_<device>.c and system_<device>.h for the STM32F10x device families.
".\ARM\INC\ST\STM32F10x\stm32f10x.h"	Device Header File <device.h> for the STM32F10x device families.
".\ARM\INC\ST\STM32F10x\system_stm32f10x.h"	system_Device.h Template File for the STM32F10x device families.

APSR_Type	Union type to access the Application Program Status Register (APSR)
CONTROL_Type	Union type to access the Control Registers (CONTROL)
CoreDebug_Type	Structure type to access the Core Debug Register (CoreDebug)
DWT_Type	Structure type to access the Data Watchpoint and Trace Register (DWT)
FPU_Type	Structure type to access the Floating Point Unit (FPU)
IPSR_Type	Union type to access the Interrupt Program Status Register (IPSR)
ITM_Type	Structure type to access the Instrumentation Trace Macrocell Register (ITM)
MPU_Type	Structure type to access the Memory Protection Unit (MPU)
NVIC_Type	Structure type to access the Nested Vectored Interrupt Controller (NVIC)
SCB_Type	Structure type to access the System Control Block (SCB)
SCnSCB_Type	Structure type to access the System Control and ID Register not in the SCB
SysTick_Type	Structure type to access the System Timer (SysTick)
TPI_Type	Structure type to access the Trace Port Interface Register (TPI)
xPSR_Type	Union type to access the Special-Purpose Program Status Registers (xPSR)

#define	Value Range	Default	Description
__CM0_REV	0x0000	0x0000	Core revision number ([15:8] revision number, [7:0] patch number)
__NVIC_PRIO_BITS	2	2	Number of priority bits implemented in the NVIC (device specific)
__Vendor_SysTickConfig	0 .. 1	0	If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.

#define	Value Range	Default	Description
__CM0PLUS_REV	0x0000	0x0000	Core revision number ([15:8] revision number, [7:0] patch number)
__NVIC_PRIO_BITS	2	2	Number of priority bits implemented in the NVIC (device specific)
__Vendor_SysTickConfig	0 .. 1	0	If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.

#define	Value Range	Default	Description
__CM3_REV	0x0101 \| 0x0200	0x0200	Core revision number ([15:8] revision number, [7:0] patch number)
__NVIC_PRIO_BITS	2 .. 8	4	Number of priority bits implemented in the NVIC (device specific)
__MPU_PRESENT	0 .. 1	0	Defines if a MPU is present or not
__Vendor_SysTickConfig	0 .. 1	0	If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.

#define	Value Range	Default	Description
__CM4_REV	0x0000	0x0000	Core revision number ([15:8] revision number, [7:0] patch number)
__NVIC_PRIO_BITS	2 .. 8	4	Number of priority bits implemented in the NVIC (device specific)
__MPU_PRESENT	0 .. 1	0	Defines if a MPU is present or not
__FPU_PRESENT	0 .. 1	0	Defines if a FPU is present or not
__Vendor_SysTickConfig	0 .. 1	0	If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.

#define	Value Range	Default	Description
__SC000_REV	0x0000	0x0000	Core revision number ([15:8] revision number, [7:0] patch number)
__NVIC_PRIO_BITS	2	2	Number of priority bits implemented in the NVIC (device specific)
__MPU_PRESENT	0 .. 1	0	Defines if a MPU is present or not
__Vendor_SysTickConfig	0 .. 1	0	If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.

#define	Value Range	Default	Description
__SC300_REV	0x0000	0x0000	Core revision number ([15:8] revision number, [7:0] patch number)
__NVIC_PRIO_BITS	2 .. 8	4	Number of priority bits implemented in the NVIC (device specific)
__MPU_PRESENT	0 .. 1	0	Defines if a MPU is present or not
__Vendor_SysTickConfig	0 .. 1	0	If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.

+Functions
uint32_t	__get_CONTROL (void)
	Read the CONTROL register. More...

void	__set_CONTROL (uint32_t control)
	Set the CONTROL Register. More...

uint32_t	__get_IPSR (void)
	Read the IPSR register. More...

uint32_t	__get_APSR (void)
	Read the APSR register. More...

uint32_t	__get_xPSR (void)
	Read the xPSR register. More...

uint32_t	__get_PSP (void)
	Read the PSP register. More...

void	__set_PSP (uint32_t topOfProcStack)
	Set the PSP register. More...

uint32_t	__get_MSP (void)
	Read the MSP register. More...

void	__set_MSP (uint32_t topOfMainStack)
	Set the MSP register. More...

uint32_t	__get_PRIMASK (void)
	Read the PRIMASK register bit. More...

void	__set_PRIMASK (uint32_t priMask)
	Set the Priority Mask bit. More...

uint32_t	__get_BASEPRI (void)
	Read the BASEPRI register [not for Cortex-M0 variants]. More...

void	__set_BASEPRI (uint32_t basePri)
	Set the BASEPRI register [not for Cortex-M0 variants]. More...

uint32_t	__get_FAULTMASK (void)
	Read the FAULTMASK register [not for Cortex-M0 variants]. More...

void	__set_FAULTMASK (uint32_t faultMask)
	Set the FAULTMASK register [not for Cortex-M0 variants]. More...

uint32_t	__get_FPSCR (void)
	Read the FPSCR register [only for Cortex-M4]. More...

void	__set_FPSCR (uint32_t fpscr)
	Set the FPSC register [only for Cortex-M4]. More...

void	__enable_irq (void)
	Globally enables interrupts and configurable fault handlers. More...

void	__disable_irq (void)
	Globally disables interrupts and configurable fault handlers. More...

void	__enable_fault_irq (void)
	Enables interrupts and all fault handlers [not for Cortex-M0 variants]. More...

void	__disable_fault_irq (void)
	Disables interrupts and all fault handlers [not for Cortex-M0 variants]. More...

+Functions
uint32_t	ITM_SendChar (uint32_t ch)
	Transmits a character via channel 0. More...

int32_t	ITM_ReceiveChar (void)
	ITM Receive Character. More...

int32_t	ITM_CheckChar (void)
	ITM Check Character. More...

+Variables
volatile int32_t	ITM_RxBuffer
	external variable to receive characters More...

+Enumerations
enum	IRQn_Type { + NonMaskableInt_IRQn = -14, + + HardFault_IRQn = -13, + + MemoryManagement_IRQn = -12, + + BusFault_IRQn = -11, + + UsageFault_IRQn = -10, + + SVCall_IRQn = -5, + + DebugMonitor_IRQn = -4, + + PendSV_IRQn = -2, + + SysTick_IRQn = -1, + + WWDG_STM_IRQn = 0, + + PVD_STM_IRQn = 1 + + }
	Definition of IRQn numbers. More...

+Functions
void	NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
	Set priority grouping [not for Cortex-M0 variants]. More...

uint32_t	NVIC_GetPriorityGrouping (void)
	Read the priority grouping [not for Cortex-M0 variants]. More...

void	NVIC_EnableIRQ (IRQn_Type IRQn)
	Enable an external interrupt. More...

void	NVIC_DisableIRQ (IRQn_Type IRQn)
	Disable an external interrupt. More...

uint32_t	NVIC_GetPendingIRQ (IRQn_Type IRQn)
	Get the pending interrupt. More...

void	NVIC_SetPendingIRQ (IRQn_Type IRQn)
	Set an interrupt to pending. More...

void	NVIC_ClearPendingIRQ (IRQn_Type IRQn)
	Clear an interrupt from pending. More...

uint32_t	NVIC_GetActive (IRQn_Type IRQn)
	Get the interrupt active status [not for Cortex-M0 variants]. More...

void	NVIC_SetPriority (IRQn_Type IRQn, uint32_t priority)
	Set the priority for an interrupt. More...

uint32_t	NVIC_GetPriority (IRQn_Type IRQn)
	Get the priority of an interrupt. More...

uint32_t	NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
	Encodes Priority [not for Cortex-M0 variants]. More...

void	NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t pPreemptPriority, uint32_t pSubPriority)
	Decode the interrupt priority [not for Cortex-M0 variants]. More...

void	NVIC_SystemReset (void)
	Reset the system. More...

Core Exception Name	IRQn Value	M0	M0p	M3	M4	SC000	SC300	Description
NonMaskableInt_IRQn	-14	+ + +	+ + +	+ + +	+ + +	+ + +	+ + +	Non Maskable Interrupt
HardFault_IRQn	-13	+ + +	+ + +	+ + +	+ + +	+ + +	+ + +	Hard Fault Interrupt
MemoryManagement_IRQn	-12			+ + +	+ + +		+ + +	Memory Management Interrupt
BusFault_IRQn	-11			+ + +	+ + +		+ + +	Bus Fault Interrupt
UsageFault_IRQn	-10			+ + +	+ + +		+ + +	Usage Fault Interrupt
SVCall_IRQn	-5	+ + +	+ + +	+ + +	+ + +	+ + +	+ + +	SV Call Interrupt
DebugMonitor_IRQn	-4			+ + +	+ + +		+ + +	Debug Monitor Interrupt
PendSV_IRQn	-2	+ + +	+ + +	+ + +	+ + +	+ + +	+ + +	Pend SV Interrupt
SysTick_IRQn	-1	+ + +	+ + +	+ + +	+ + +	+ + +	+ + +	System Tick Interrupt

Enumerator
NonMaskableInt_IRQn	+ Exception 2: Non Maskable Interrupt. +
HardFault_IRQn	+ Exception 3: Hard Fault Interrupt. +
MemoryManagement_IRQn	+ Exception 4: Memory Management Interrupt [not on Cortex-M0 variants]. +
BusFault_IRQn	+ Exception 5: Bus Fault Interrupt [not on Cortex-M0 variants]. +
UsageFault_IRQn	+ Exception 6: Usage Fault Interrupt [not on Cortex-M0 variants]. +
SVCall_IRQn	+ Exception 11: SV Call Interrupt. +
DebugMonitor_IRQn	+ Exception 12: Debug Monitor Interrupt [not on Cortex-M0 variants]. +
PendSV_IRQn	+ Exception 14: Pend SV Interrupt [not on Cortex-M0 variants]. +
SysTick_IRQn	+ Exception 15: System Tick Interrupt. +
WWDG_STM_IRQn	+ Device Interrupt 0: Window WatchDog Interrupt. +
PVD_STM_IRQn	+ Device Interrupt 1: PVD through EXTI Line detection Interrupt. +

void NVIC_DecodePriority	(	uint32_t	Priority,
		uint32_t	PriorityGroup,
		uint32_t *	pPreemptPriority,
		uint32_t *	pSubPriority
	)

[in]	Priority	Priority
[in]	PriorityGroup	Priority group
[out]	*pPreemptPriority	Preemptive priority value (starting from 0)
[out]	*pSubPriority	Subpriority value (starting from 0)

uint32_t NVIC_EncodePriority	(	uint32_t	PriorityGroup,
		uint32_t	PreemptPriority,
		uint32_t	SubPriority
	)

+Functions
uint32_t	SysTick_Config (uint32_t ticks)
	System Tick Timer Configuration. More...

+Functions
void	__NOP (void)
	No Operation. More...

void	__WFI (void)
	Wait For Interrupt. More...

void	__WFE (void)
	Wait For Event. More...

void	__SEV (void)
	Send Event. More...

void	__BKPT (uint8_t value)
	Set Breakpoint. More...

void	__ISB (void)
	Instruction Synchronization Barrier. More...

void	__DSB (void)
	Data Synchronization Barrier. More...

void	__DMB (void)
	Data Memory Barrier. More...

uint32_t	__REV (uint32_t value)
	Reverse byte order (32 bit) More...

uint32_t	__REV16 (uint32_t value)
	Reverse byte order (16 bit) More...

int32_t	__REVSH (int32_t value)
	Reverse byte order in signed short value. More...

uint32_t	__RBIT (uint32_t value)
	Reverse bit order of value [not for Cortex-M0 variants]. More...

uint32_t	__ROR (uint32_t value, uint32_t shift)
	Rotate a value right by a number of bits. More...

uint8_t	__LDREXB (volatile uint8_t *addr)
	LDR Exclusive (8 bit) [not for Cortex-M0 variants]. More...

uint16_t	__LDREXH (volatile uint16_t *addr)
	LDR Exclusive (16 bit) [not for Cortex-M0 variants]. More...

uint32_t	__LDREXW (volatile uint32_t *addr)
	LDR Exclusive (32 bit) [not for Cortex-M0 variants]. More...

uint32_t	__STREXB (uint8_t value, volatile uint8_t *addr)
	STR Exclusive (8 bit) [not for Cortex-M0 variants]. More...

uint32_t	__STREXH (uint16_t value, volatile uint16_t *addr)
	STR Exclusive (16 bit) [not for Cortex-M0 variants]. More...

uint32_t	__STREXW (uint32_t value, volatile uint32_t *addr)
	STR Exclusive (32 bit) [not for Cortex-M0 variants]. More...

void	__CLREX (void)
	Remove the exclusive lock [not for Cortex-M0 variants]. More...

uint32_t	__SSAT (unint32_t value, uint32_t sat)
	Signed Saturate [not for Cortex-M0 variants]. More...

uint32_t	__USAT (uint32_t value, uint32_t sat)
	Unsigned Saturate [not for Cortex-M0 variants]. More...

uint8_t	__CLZ (uint32_t value)
	Count leading zeros [not for Cortex-M0 variants]. More...

Release +Notes for STM32L1xx CMSIS +

Contents

STM32L1xx CMSIS update history

V1.2.1 / 19-June-2013

V1.2.0 / 22-February-2013

V1.1.1 / 05-March-2012

V1.1.0 / 24-January-2012

V1.0.0 / 31-December-2010

License

© COPYRIGHT 2013 STMicroelectronics

© COPYRIGHT 2013 STMicroelectronics

© COPYRIGHT 2013 STMicroelectronics

© COPYRIGHT 2013 STMicroelectronics

© COPYRIGHT 2013 STMicroelectronics

© COPYRIGHT 2013 STMicroelectronics

© COPYRIGHT 2013 STMicroelectronics

+Template Files

+Adaption of Template Files to Devices

+Create generic Libraries with CMSIS

+Interrupt Number Definition

+Configuration of the Processor and Core Peripherals

+CMSIS Version and Processor Information

+Device Peripheral Access Layer

+Device.h Template File

- _ -

- a -

- b -

- c -

- d -

- e -

- f -

- h -

- i -

- l -

- m -

- n -

- p -

- q -

- r -

- s -

- t -

- u -

- v -

- w -

- z -

- _ -

- a -

- b -

- c -

- d -

- e -

- f -

- h -

- i -

- l -

- m -

- n -

- p -

- q -

- r -

- s -

- t -

- u -

- v -

- w -

- z -

- _ -

- b -

- d -

- h -

- i -

- m -

- n -

- p -

- s -

- u -

- w -

- _ -

- i -

- n -

Release +Notes for STM32L1xx CMSIS
+

[in]	value	Value to be shifted right
[in]	shift	Number of bits in the range [1..31]

[in]	value	Value to be saturated
[in]	sat	Bit position to saturate to [1..32]

uint32_t __STREXH	(	uint16_t	value,
		volatile uint16_t *	addr
	)

uint32_t __STREXW	(	uint32_t	value,
		volatile uint32_t *	addr
	)

+Functions
uint32_t	__SADD8 (uint32_t val1, uint32_t val2)
	GE setting quad 8-bit signed addition. More...

uint32_t	__QADD8 (uint32_t val1, uint32_t val2)
	Q setting quad 8-bit saturating addition. More...

uint32_t	__SHADD8 (uint32_t val1, uint32_t val2)
	Quad 8-bit signed addition with halved results. More...

uint32_t	__UADD8 (uint32_t val1, uint32_t val2)
	GE setting quad 8-bit unsigned addition. More...

uint32_t	__UQADD8 (uint32_t val1, uint32_t val2)
	Quad 8-bit unsigned saturating addition. More...

uint32_t	__UHADD8 (uint32_t val1, uint32_t val2)
	Quad 8-bit unsigned addition with halved results. More...

uint32_t	__SSUB8 (uint32_t val1, uint32_t val2)
	GE setting quad 8-bit signed subtraction. More...

uint32_t	__QSUB8 (uint32_t val1, uint32_t val2)
	Q setting quad 8-bit saturating subtract. More...

uint32_t	__SHSUB8 (uint32_t val1, uint32_t val2)
	Quad 8-bit signed subtraction with halved results. More...

uint32_t	__USUB8 (uint32_t val1, uint32_t val2)
	GE setting quad 8-bit unsigned subtract. More...

uint32_t	__UQSUB8 (uint32_t val1, uint32_t val2)
	Quad 8-bit unsigned saturating subtraction. More...

uint32_t	__UHSUB8 (uint32_t val1, uint32_t val2)
	Quad 8-bit unsigned subtraction with halved results. More...

uint32_t	__SADD16 (uint32_t val1, uint32_t val2)
	GE setting dual 16-bit signed addition. More...

uint32_t	__QADD16 (uint32_t val1, uint32_t val2)
	Q setting dual 16-bit saturating addition. More...

uint32_t	__SHADD16 (uint32_t val1, uint32_t val2)
	Dual 16-bit signed addition with halved results. More...

uint32_t	__UADD16 (uint32_t val1, uint32_t val2)
	GE setting dual 16-bit unsigned addition. More...

uint32_t	__UQADD16 (uint32_t val1, uint32_t val2)
	Dual 16-bit unsigned saturating addition. More...

uint32_t	__UHADD16 (uint32_t val1, uint32_t val2)
	Dual 16-bit unsigned addition with halved results. More...

uint32_t	__SSUB16 (uint32_t val1, uint32_t val2)
	GE setting dual 16-bit signed subtraction. More...

uint32_t	__QSUB16 (uint32_t val1, uint32_t val2)
	Q setting dual 16-bit saturating subtract. More...

uint32_t	__SHSUB16 (uint32_t val1, uint32_t val2)
	Dual 16-bit signed subtraction with halved results. More...

uint32_t	__USUB16 (uint32_t val1, uint32_t val2)
	GE setting dual 16-bit unsigned subtract. More...

uint32_t	__UQSUB16 (uint32_t val1, uint32_t val2)
	Dual 16-bit unsigned saturating subtraction. More...

uint32_t	__UHSUB16 (uint32_t val1, uint32_t val2)
	Dual 16-bit unsigned subtraction with halved results. More...

uint32_t	__SASX (uint32_t val1, uint32_t val2)
	GE setting dual 16-bit addition and subtraction with exchange. More...

uint32_t	__QASX (uint32_t val1, uint32_t val2)
	Q setting dual 16-bit add and subtract with exchange. More...

uint32_t	__SHASX (uint32_t val1, uint32_t val2)
	Dual 16-bit signed addition and subtraction with halved results. More...

uint32_t	__UASX (uint32_t val1, uint32_t val2)
	GE setting dual 16-bit unsigned addition and subtraction with exchange. More...

uint32_t	__UQASX (uint32_t val1, uint32_t val2)
	Dual 16-bit unsigned saturating addition and subtraction with exchange. More...

uint32_t	__UHASX (uint32_t val1, uint32_t val2)
	Dual 16-bit unsigned addition and subtraction with halved results and exchange. More...

uint32_t	__SSAX (uint32_t val1, uint32_t val2)
	GE setting dual 16-bit signed subtraction and addition with exchange. More...

uint32_t	__QSAX (uint32_t val1, uint32_t val2)
	Q setting dual 16-bit subtract and add with exchange. More...

uint32_t	__SHSAX (uint32_t val1, uint32_t val2)
	Dual 16-bit signed subtraction and addition with halved results. More...

uint32_t	__USAX (uint32_t val1, uint32_t val2)
	GE setting dual 16-bit unsigned subtract and add with exchange. More...

uint32_t	__UQSAX (uint32_t val1, uint32_t val2)
	Dual 16-bit unsigned saturating subtraction and addition with exchange. More...

uint32_t	__UHSAX (uint32_t val1, uint32_t val2)
	Dual 16-bit unsigned subtraction and addition with halved results and exchange. More...

uint32_t	__USAD8 (uint32_t val1, uint32_t val2)
	Unsigned sum of quad 8-bit unsigned absolute difference. More...

uint32_t	__USADA8 (uint32_t val1, uint32_t val2, uint32_t val3)
	Unsigned sum of quad 8-bit unsigned absolute difference with 32-bit accumulate. More...

uint32_t	__SSAT16 (uint32_t val1, const uint32_t val2)
	Q setting dual 16-bit saturate. More...

uint32_t	__USAT16 (uint32_t val1, const uint32_t val2)
	Q setting dual 16-bit unsigned saturate. More...

uint32_t	__UXTB16 (uint32_t val)
	Dual extract 8-bits and zero-extend to 16-bits. More...

uint32_t	__UXTAB16 (uint32_t val1, uint32_t val2)
	Extracted 16-bit to 32-bit unsigned addition. More...

uint32_t	__SXTB16 (uint32_t val)
	Dual extract 8-bits and sign extend each to 16-bits. More...

uint32_t	__SXTAB16 (uint32_t val1, uint32_t val2)
	Dual extracted 8-bit to 16-bit signed addition. More...

uint32_t	__SMUAD (uint32_t val1, uint32_t val2)
	Q setting sum of dual 16-bit signed multiply. More...

uint32_t	__SMUADX (uint32_t val1, uint32_t val2)
	Q setting sum of dual 16-bit signed multiply with exchange. More...

uint32_t	__SMMLA (int32_t val1, int32_t val2, int32_t val3)
	32-bit signed multiply with 32-bit truncated accumulator. More...

uint32_t	__SMLAD (uint32_t val1, uint32_t val2, uint32_t val3)
	Q setting dual 16-bit signed multiply with single 32-bit accumulator. More...

uint32_t	__SMLADX (uint32_t val1, uint32_t val2, uint32_t val3)
	Q setting pre-exchanged dual 16-bit signed multiply with single 32-bit accumulator. More...

uint64_t	__SMLALD (uint32_t val1, uint32_t val2, uint64_t val3)
	Dual 16-bit signed multiply with single 64-bit accumulator. More...

unsigned long long	__SMLALDX (uint32_t val1, uint32_t val2, unsigned long long val3)
	Dual 16-bit signed multiply with exchange with single 64-bit accumulator. More...

uint32_t	__SMUSD (uint32_t val1, uint32_t val2)
	Dual 16-bit signed multiply returning difference. More...

uint32_t	__SMUSDX (uint32_t val1, uint32_t val2)
	Dual 16-bit signed multiply with exchange returning difference. More...

uint32_t	__SMLSD (uint32_t val1, uint32_t val2, uint32_t val3)
	Q setting dual 16-bit signed multiply subtract with 32-bit accumulate. More...

uint32_t	__SMLSDX (uint32_t val1, uint32_t val2, uint32_t val3)
	Q setting dual 16-bit signed multiply with exchange subtract with 32-bit accumulate. More...

uint64_t	__SMLSLD (uint32_t val1, uint32_t val2, uint64_t val3)
	Q setting dual 16-bit signed multiply subtract with 64-bit accumulate. More...

unsigned long long	__SMLSLDX (uint32_t val1, uint32_t val2, unsigned long long val3)
	Q setting dual 16-bit signed multiply with exchange subtract with 64-bit accumulate. More...

uint32_t	__SEL (uint32_t val1, uint32_t val2)
	Select bytes based on GE bits. More...

uint32_t	__QADD (uint32_t val1, uint32_t val2)
	Q setting saturating add. More...

uint32_t	__QSUB (uint32_t val1, uint32_t val2)
	Q setting saturating subtract. More...

uint32_t	__PKHBT (uint32_t val1, uint32_t val2, uint32_t val3)
	Halfword packing instruction. Combines bits[15:0] of val1 with bits[31:16] of val2 levitated with the val3. More...

uint32_t	__PKHTB (uint32_t val1, uint32_t val2, uint32_t val3)
	Halfword packing instruction. Combines bits[31:16] of val1 with bits[15:0] of val2 right-shifted with the val3. More...

uint32_t __PKHBT	(	uint32_t	val1,
		uint32_t	val2,
		uint32_t	val3
	)

val1	first 16-bit operands
val2	second 16-bit operands
val3	value for left-shifting val2. Value range [0..31].

uint32_t __PKHTB	(	uint32_t	val1,
		uint32_t	val2,
		uint32_t	val3
	)

val1	first summand of the saturating add operation.
val2	second summand of the saturating add operation.

val1	first two 16-bit summands.
val2	second two 16-bit summands.