# HG changeset patch # User Ethan Zonca # Date 2014-07-03 13:04:24 # Node ID a48d9ffdc5db11f8d5189cc1accb8c6d96dbdee6 # Parent 1c5909c633fa1188f25bddb784378e067b77a4b0 Oled driver updates and pin assignment fixes diff --git a/libraries/oleddrv/bsp.h b/libraries/oleddrv/bsp.h --- a/libraries/oleddrv/bsp.h +++ b/libraries/oleddrv/bsp.h @@ -25,69 +25,44 @@ D1/Data 3 4 D0/Clk RD (Float) */ -#define SSD_Clk GPIOB,GPIO_Pin_13 -#define SSD_Data GPIOB,GPIO_Pin_15 -#define SSD_Reset GPIOD,GPIO_Pin_12 -#define SSD_A0 GPIOD,GPIO_Pin_14 -#define SSD_CS //GPIOG,GPIO_Pin_2 +#define SSD_Clk GPIOA,GPIO_Pin_5 +#define SSD_Data GPIOA,GPIO_Pin_7 +#define SSD_Reset GPIOB,GPIO_Pin_2 +#define SSD_A0 GPIOB,GPIO_Pin_10 +#define SSD_CS GPIOB,GPIO_Pin_1 -#define SSD_Clk_Low() GPIOB->BRR = GPIO_Pin_13 -#define SSD_Clk_High() GPIOB->BSRR = GPIO_Pin_13 -#define SSD_Data_Low() GPIOB->BRR = GPIO_Pin_15 -#define SSD_Data_High() GPIOB->BSRR = GPIO_Pin_15 -#define SSD_Reset_Low() GPIOB->BRR = GPIO_Pin_12 -#define SSD_Reset_High() GPIOB->BSRR = GPIO_Pin_12 -#define SSD_A0_Low() GPIOB->BRR = GPIO_Pin_14 -#define SSD_A0_High() GPIOB->BSRR = GPIO_Pin_14 -#define SSD_CS_Low() //GPIOG->BRR = GPIO_Pin_2 -#define SSD_CS_High() //GPIOG->BSRR = GPIO_Pin_2 +#define SSD_Clk_Low() GPIOA->BRR = GPIO_Pin_5 +#define SSD_Clk_High() GPIOA->ODR |= GPIO_Pin_5 +#define SSD_Data_Low() GPIOA->BRR = GPIO_Pin_7 +#define SSD_Data_High() GPIOA->ODR |= GPIO_Pin_7 +#define SSD_Reset_Low() GPIOB->BRR = GPIO_Pin_2 +#define SSD_Reset_High() GPIOB->ODR |= GPIO_Pin_2 +#define SSD_A0_Low() GPIOB->BRR = GPIO_Pin_10 +#define SSD_A0_High() GPIOB->ODR |= GPIO_Pin_10 +#define SSD_CS_Low() GPIOB->BRR = GPIO_Pin_1 +#define SSD_CS_High() GPIOB->ODR |= GPIO_Pin_1 -#define SPI_SendByte(data) SPI2->DR = (data) -#define SPI_Wait() while(!(SPI2->SR&SPI_I2S_FLAG_TXE));while(SPI2->SR&SPI_I2S_FLAG_BSY); +#define SPI_SendByte(data) SPI1->DR = (data) +#define SPI_Wait() while(!(SPI1->SR&SPI_I2S_FLAG_TXE));while(SPI1->SR&SPI_I2S_FLAG_BSY); #define SSD1303_FPS 50 - - #define IsLedOn() (!(GPIOA->ODR & GPIO_Pin_8)) #define LED_ON() GPIOA->BRR = GPIO_Pin_8 #define LED_OFF() GPIOA->BSRR = GPIO_Pin_8 #define ToggleLED() if(GPIOA->ODR & GPIO_Pin_8){GPIOA->BRR = GPIO_Pin_8;}\ else{GPIOA->BSRR = GPIO_Pin_8;} - -#define IsCHG() (!(GPIOB->IDR & GPIO_Pin_5)) -#define IsPGOOD() (!(GPIOB->IDR & GPIO_Pin_4)) - #define GSel1_High() GPIOB->BSRR = GPIO_Pin_9 #define GSel1_Low() GPIOB->BRR = GPIO_Pin_9 -#define GSel2_High() GPIOB->BSRR = GPIO_Pin_8 -#define GSel2_Low() GPIOB->BRR = GPIO_Pin_8 #define MMA_SLEEP() GPIOB->BRR = GPIO_Pin_11 #define MMA_WAKEUP() GPIOB->BSRR = GPIO_Pin_11 #define Is_MMA_WAKEUP() (GPIOB->ODR & GPIO_Pin_11) -#define AD_CH_BAT ADC_Channel_4 -#define AD_CH_X ADC_Channel_1 -#define AD_CH_Y ADC_Channel_2 -#define AD_CH_Z ADC_Channel_3 -#define AD_CH_CHG ADC_Channel_9 -#define AD_CH_REF ADC_Channel_17 - #define DMA_SSD_1303 DMA1_Channel5 #define DMA_Handler_SSD_1303 DMA1_Channel5_IRQHandler -#define DMA_ADC DMA1_Channel1 + #define Is_Enc_Key_Down() (!(GPIOA->IDR & GPIO_Pin_0)) -typedef struct _ADResult_t -{ - uint16_t ADRef; // ADC1 - uint16_t ADBat; // ADC2 - uint16_t ADX; // ADC1 - uint16_t ADY; // ADC2 - uint16_t ADZ; // ADC1 - uint16_t ADChg; // ADC2 -}ADResult_t; - #endif diff --git a/ssd1306.c b/ssd1306.c --- a/ssd1306.c +++ b/ssd1306.c @@ -83,7 +83,8 @@ void SSD1303_Init(void) { /* Generate a reset */ SSD_Reset_Low(); - for(u32 i=5000;--i;);//—” ±5uS“‘…œ + uint32_t i ; + for(i=5000;--i;); SSD_Reset_High(); /************************************************* @@ -223,7 +224,8 @@ unsigned long SSD1303_OFF(void) { if(iS_SSD_On){ #ifdef DEBUG_UI - for(u32 i=0;iCCR &= ((u32)0xFFFFFFFE); + DMA1_Channel5->CCR &= ((uint32_t)0xFFFFFFFE); DMA1_Channel5->CNDTR = SSD1303_COLUMN_NUMBER+SSD1303_COLUMN_MARGIN_START + SSD1303_COLUMN_MARGIN_END; - DMA1_Channel5->CMAR = (u32)(SSD1303_Buffer+SSD1303_COLUMN_NUMBER*pageIndex - SSD1303_COLUMN_MARGIN_START); - DMA_SSD_1303->CCR |= ((u32)0x00000001); + DMA1_Channel5->CMAR = (uint32_t)(SSD1303_Buffer+SSD1303_COLUMN_NUMBER*pageIndex - SSD1303_COLUMN_MARGIN_START); + DMA_SSD_1303->CCR |= ((uint32_t)0x00000001); pageIndex++; #else SSD_A0_High(); - DMA_SSD_1303->CCR &= ((u32)0xFFFFFFFE); + DMA_SSD_1303->CCR &= ((uint32_t)0xFFFFFFFE); DMA_SSD_1303->CNDTR = SSD1303_COLUMN_NUMBER*SSD1303_PAGE_NUMBER;//+SSD1303_COLUMN_MARGIN_START + SSD1303_COLUMN_MARGIN_END; - DMA_SSD_1303->CMAR = (u32)(SSD1303_Buffer);//+SSD1303_COLUMN_NUMBER*pageIndex); + DMA_SSD_1303->CMAR = (uint32_t)(SSD1303_Buffer);//+SSD1303_COLUMN_NUMBER*pageIndex); //DMA_Cmd(DMA_SSD_1303, ENABLE); - DMA_SSD_1303->CCR |= ((u32)0x00000001); + DMA_SSD_1303->CCR |= ((uint32_t)0x00000001); // pageIndex++; pageIndex = SSD1303_PAGE_NUMBER; #endif @@ -389,7 +391,9 @@ unsigned long SSD1303_DrawBlock( unsigned char mask1 = (1<