LIBDIR:=libraries

HAL_LIB:=$(LIBDIR)/STM32F0xx_HAL_Driver

USB_LIB:=$(LIBDIR)/STM32_USB_Device_Library

# Local libs

# CMSIS

INCLUDE+=-I$(LIBDIR)/CMSIS/Include

INCLUDE+=-I$(LIBDIR)/CMSIS/Device/ST/STM32F0xx/Include

# USB

INCLUDE+=-I$(USB_LIB)/Class/CDC

INCLUDE+=-I$(USB_LIB)/Core

# HAL

INCLUDE+=-I$(HAL_LIB)/Inc

/**

  ******************************************************************************

  * @file    stm32f030x6.h

  * @author  MCD Application Team

  * @version V2.1.0

  * @date    03-Oct-2014

  * @brief   CMSIS STM32F030x4/STM32F030x6 devices Peripheral Access Layer Header File.

  *

  *          This file contains:

  *           - Data structures and the address mapping for all peripherals

  *           - Peripheral's registers declarations and bits definition

  *           - Macros to access peripheral’s registers hardware

  *

  ******************************************************************************

  * @attention

  *

  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>

  *

  * Redistribution and use in source and binary forms, with or without modification,

  * are permitted provided that the following conditions are met:

  *   1. Redistributions of source code must retain the above copyright notice,

  *      this list of conditions and the following disclaimer.

  *   2. Redistributions in binary form must reproduce the above copyright notice,

  *      this list of conditions and the following disclaimer in the documentation

  *      and/or other materials provided with the distribution.

  *   3. Neither the name of STMicroelectronics nor the names of its contributors

  *      may be used to endorse or promote products derived from this software

  *      without specific prior written permission.

  *

  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE

  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR

  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER

  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,

  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

  *

  ******************************************************************************

  */

/** @addtogroup CMSIS_Device

  * @{

  */

/** @addtogroup stm32f030x6

  * @{

  */

#ifndef __STM32F030x6_H

#define __STM32F030x6_H

#ifdef __cplusplus

 extern "C" {

#endif /* __cplusplus */

/** @addtogroup Configuration_section_for_CMSIS

  * @{

  */

/**

 * @brief Configuration of the Cortex-M0 Processor and Core Peripherals

 */

#define __CM0_REV                 0 /*!< Core Revision r0p0                            */

#define __MPU_PRESENT             0 /*!< STM32F0xx do not provide MPU                  */

#define __NVIC_PRIO_BITS          2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */

#define __Vendor_SysTickConfig    0 /*!< Set to 1 if different SysTick Config is used  */

/**

  * @}

  */

/** @addtogroup Peripheral_interrupt_number_definition

  * @{

  */

/**

 * @brief STM32F030x4/STM32F030x6 device Interrupt Number Definition

 */

typedef enum

{

/******  Cortex-M0 Processor Exceptions Numbers **************************************************************/

  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                        */

  HardFault_IRQn              = -13,    /*!< 3 Cortex-M0 Hard Fault Interrupt                                */

  SVC_IRQn                    = -5,     /*!< 11 Cortex-M0 SV Call Interrupt                                  */

  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0 Pend SV Interrupt                                  */

  SysTick_IRQn                = -1,     /*!< 15 Cortex-M0 System Tick Interrupt                              */

/******  STM32F030x4/STM32F030x6 specific Interrupt Numbers **************************************/

  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                       */

  RTC_IRQn                    = 2,      /*!< RTC Interrupt through EXTI Lines 17, 19 and 20                  */

  FLASH_IRQn                  = 3,      /*!< FLASH global Interrupt                                          */

  RCC_IRQn                    = 4,      /*!< RCC Global Interrupts                                           */

  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                                    */

  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                                    */

  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                                    */

  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                        */

  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                         */

  DMA1_Channel4_5_IRQn        = 11,     /*!< DMA1 Channel 4 and Channel 5 Interrupts                         */

  ADC1_IRQn                   = 12,     /*!< ADC1 Interrupts                                                 */

  TIM1_BRK_UP_TRG_COM_IRQn    = 13,     /*!< TIM1 Break, Update, Trigger and Commutation Interrupts          */

  TIM1_CC_IRQn                = 14,     /*!< TIM1 Capture Compare Interrupt                                  */

  TIM3_IRQn                   = 16,     /*!< TIM3 global Interrupt                                           */

  TIM14_IRQn                  = 19,     /*!< TIM14 global Interrupt                                          */

  TIM16_IRQn                  = 21,     /*!< TIM16 global Interrupt                                          */

  TIM17_IRQn                  = 22,     /*!< TIM17 global Interrupt                                          */

  I2C1_IRQn                   = 23,     /*!< I2C1 Event Interrupt                                            */

  SPI1_IRQn                   = 25,     /*!< SPI1 global Interrupt                                           */

  USART1_IRQn                 = 27      /*!< USART1 global Interrupt                                         */

} IRQn_Type;

/**

  * @}

  */

#include "core_cm0.h"            /* Cortex-M0 processor and core peripherals */

#include "system_stm32f0xx.h"    /* STM32F0xx System Header */

#include <stdint.h>

/** @addtogroup Peripheral_registers_structures

  * @{

  */

/**

  * @brief Analog to Digital Converter

  */

typedef struct

{

  __IO uint32_t ISR;          /*!< ADC Interrupt and Status register,                          Address offset:0x00 */

  __IO uint32_t IER;          /*!< ADC Interrupt Enable register,                              Address offset:0x04 */

  __IO uint32_t CR;           /*!< ADC Control register,                                       Address offset:0x08 */

  __IO uint32_t CFGR1;        /*!< ADC Configuration register 1,                               Address offset:0x0C */

  __IO uint32_t CFGR2;        /*!< ADC Configuration register 2,                               Address offset:0x10 */

  __IO uint32_t SMPR;         /*!< ADC Sampling time register,                                 Address offset:0x14 */

  uint32_t   RESERVED1;       /*!< Reserved,                                                                  0x18 */

  uint32_t   RESERVED2;       /*!< Reserved,                                                                  0x1C */

  __IO uint32_t TR;           /*!< ADC watchdog threshold register,                            Address offset:0x20 */

  uint32_t   RESERVED3;       /*!< Reserved,                                                                  0x24 */

  __IO uint32_t CHSELR;       /*!< ADC channel selection register,                             Address offset:0x28 */

  uint32_t   RESERVED4[5];    /*!< Reserved,                                                                  0x2C */

   __IO uint32_t DR;          /*!< ADC data register,                                          Address offset:0x40 */

}ADC_TypeDef;

typedef struct

{

  __IO uint32_t CCR;

}ADC_Common_TypeDef;

/**

  * @brief CRC calculation unit

  */

typedef struct

{

  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */

  __IO uint8_t  IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */

  uint8_t       RESERVED0;   /*!< Reserved,                                                    0x05 */

  uint16_t      RESERVED1;   /*!< Reserved,                                                    0x06 */

  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */

  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */

  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */

  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */

}CRC_TypeDef;

/**

  * @brief Debug MCU

  */

typedef struct

{

  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */

  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */

  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */

  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */

}DBGMCU_TypeDef;

/**

  * @brief DMA Controller

  */

typedef struct

{

  __IO uint32_t CCR;          /*!< DMA channel x configuration register                                           */

  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register                                          */

  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register                                      */

  __IO uint32_t CMAR;         /*!< DMA channel x memory address register                                          */

}DMA_Channel_TypeDef;

typedef struct

{

  __IO uint32_t ISR;          /*!< DMA interrupt status register,                            Address offset: 0x00 */

  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,                        Address offset: 0x04 */

}DMA_TypeDef;

/** 

  * @brief External Interrupt/Event Controller

  */

typedef struct

{

  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                             Address offset: 0x00 */

  __IO uint32_t EMR;          /*!<EXTI Event mask register,                                 Address offset: 0x04 */

  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,                  Address offset: 0x08 */

  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,                  Address offset: 0x0C */

  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,                   Address offset: 0x10 */

  __IO uint32_t PR;           /*!<EXTI Pending register,                                    Address offset: 0x14 */

}EXTI_TypeDef;

/** 

  * @brief FLASH Registers

  */

typedef struct

{

  __IO uint32_t ACR;          /*!<FLASH access control register,                 Address offset: 0x00 */

  __IO uint32_t KEYR;         /*!<FLASH key register,                            Address offset: 0x04 */

  __IO uint32_t OPTKEYR;      /*!<FLASH OPT key register,                        Address offset: 0x08 */

  __IO uint32_t SR;           /*!<FLASH status register,                         Address offset: 0x0C */

  __IO uint32_t CR;           /*!<FLASH control register,                        Address offset: 0x10 */

  __IO uint32_t AR;           /*!<FLASH address register,                        Address offset: 0x14 */

  __IO uint32_t RESERVED;     /*!< Reserved,                                                     0x18 */

  __IO uint32_t OBR;          /*!<FLASH option bytes register,                   Address offset: 0x1C */

  __IO uint32_t WRPR;         /*!<FLASH option bytes register,                   Address offset: 0x20 */

}FLASH_TypeDef;

/** 

  * @brief Option Bytes Registers

  */

typedef struct

{

  __IO uint16_t RDP;          /*!< FLASH option byte Read protection,             Address offset: 0x00 */

  __IO uint16_t USER;         /*!< FLASH option byte user options,                Address offset: 0x02 */

  __IO uint16_t DATA0;        /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */

  __IO uint16_t DATA1;        /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */

  __IO uint16_t WRP0;         /*!< FLASH option byte write protection 0,          Address offset: 0x08 */

  __IO uint16_t WRP1;         /*!< FLASH option byte write protection 1,          Address offset: 0x0A */

  __IO uint16_t WRP2;         /*!< FLASH option byte write protection 2,          Address offset: 0x0C */

  __IO uint16_t WRP3;         /*!< FLASH option byte write protection 3,          Address offset: 0x0E */

}OB_TypeDef;

/**

  * @brief General Purpose I/O

  */

typedef struct

{

  __IO uint32_t MODER;        /*!< GPIO port mode register,               Address offset: 0x00 */

  __IO uint32_t OTYPER;       /*!< GPIO port output type register,        Address offset: 0x04 */

  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,       Address offset: 0x08 */

  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C */

  __IO uint32_t IDR;          /*!< GPIO port input data register,         Address offset: 0x10 */

  __IO uint32_t ODR;          /*!< GPIO port output data register,        Address offset: 0x14 */

  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset register,      Address offset: 0x1A */

  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register, Address offset: 0x1C */

  __IO uint32_t AFR[2];       /*!< GPIO alternate function low register,  Address offset: 0x20-0x24 */

  __IO uint32_t BRR;          /*!< GPIO bit reset register,               Address offset: 0x28 */

}GPIO_TypeDef;

/**

  * @brief SysTem Configuration

  */

typedef struct

{

  __IO uint32_t CFGR1;       /*!< SYSCFG configuration register 1,                           Address offset: 0x00 */

       uint32_t RESERVED;    /*!< Reserved,                                                                  0x04 */

  __IO uint32_t EXTICR[4];   /*!< SYSCFG external interrupt configuration register,     Address offset: 0x14-0x08 */

  __IO uint32_t CFGR2;       /*!< SYSCFG configuration register 2,                           Address offset: 0x18 */

}SYSCFG_TypeDef;

/** 

  * @brief Inter-integrated Circuit Interface

  */

typedef struct

{

  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */

  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */

  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */

  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */

  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */

  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */

  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */

  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */

  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */

  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */

  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */

}I2C_TypeDef;

/**

  * @brief Independent WATCHDOG

  */

typedef struct

{

  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */

  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */

  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */

  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */

  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */

}IWDG_TypeDef;

/**

  * @brief Power Control

  */

typedef struct

{

  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */

  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */

}PWR_TypeDef;

/**

  * @brief Reset and Clock Control

  */

typedef struct

{

  __IO uint32_t CR;         /*!< RCC clock control register,                                  Address offset: 0x00 */

  __IO uint32_t CFGR;       /*!< RCC clock configuration register,                            Address offset: 0x04 */

  __IO uint32_t CIR;        /*!< RCC clock interrupt register,                                Address offset: 0x08 */

  __IO uint32_t APB2RSTR;   /*!< RCC APB2 peripheral reset register,                          Address offset: 0x0C */

  __IO uint32_t APB1RSTR;   /*!< RCC APB1 peripheral reset register,                          Address offset: 0x10 */

  __IO uint32_t AHBENR;     /*!< RCC AHB peripheral clock register,                           Address offset: 0x14 */

  __IO uint32_t APB2ENR;    /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x18 */

  __IO uint32_t APB1ENR;    /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x1C */

  __IO uint32_t BDCR;       /*!< RCC Backup domain control register,                          Address offset: 0x20 */

  __IO uint32_t CSR;        /*!< RCC clock control & status register,                         Address offset: 0x24 */

  __IO uint32_t AHBRSTR;    /*!< RCC AHB peripheral reset register,                           Address offset: 0x28 */

  __IO uint32_t CFGR2;      /*!< RCC clock configuration register 2,                          Address offset: 0x2C */

  __IO uint32_t CFGR3;      /*!< RCC clock configuration register 3,                          Address offset: 0x30 */

  __IO uint32_t CR2;        /*!< RCC clock control register 2,                                Address offset: 0x34 */

}RCC_TypeDef;

/** 

  * @brief Real-Time Clock

  */

typedef struct

{

  __IO uint32_t TR;         /*!< RTC time register,                                        Address offset: 0x00 */

  __IO uint32_t DR;         /*!< RTC date register,                                        Address offset: 0x04 */

  __IO uint32_t CR;         /*!< RTC control register,                                     Address offset: 0x08 */

  __IO uint32_t ISR;        /*!< RTC initialization and status register,                   Address offset: 0x0C */

  __IO uint32_t PRER;       /*!< RTC prescaler register,                                   Address offset: 0x10 */

       uint32_t RESERVED1;  /*!< Reserved,                                                 Address offset: 0x14 */

       uint32_t RESERVED2;  /*!< Reserved,                                                 Address offset: 0x18 */

  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                     Address offset: 0x1C */

       uint32_t RESERVED3;  /*!< Reserved,                                                 Address offset: 0x20 */

  __IO uint32_t WPR;        /*!< RTC write protection register,                            Address offset: 0x24 */

  __IO uint32_t SSR;        /*!< RTC sub second register,                                  Address offset: 0x28 */

  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                               Address offset: 0x2C */

  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                             Address offset: 0x30 */

  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                             Address offset: 0x34 */

  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */

  __IO uint32_t CALR;       /*!< RTC calibration register,                                 Address offset: 0x3C */

  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */

  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                          Address offset: 0x44 */

}RTC_TypeDef;

/**

  * @brief Serial Peripheral Interface

  */

typedef struct

{

  __IO uint16_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */

  uint16_t  RESERVED0;    /*!< Reserved, 0x02                                                            */

  __IO uint16_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */

  uint16_t  RESERVED1;    /*!< Reserved, 0x06                                                            */

  __IO uint16_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */

  uint16_t  RESERVED2;    /*!< Reserved, 0x0A                                                            */

  __IO uint16_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */

  uint16_t  RESERVED3;    /*!< Reserved, 0x0E                                                            */

  __IO uint16_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */

  uint16_t  RESERVED4;    /*!< Reserved, 0x12                                                            */

  __IO uint16_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */

  uint16_t  RESERVED5;    /*!< Reserved, 0x16                                                            */

  __IO uint16_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */

  uint16_t  RESERVED6;    /*!< Reserved, 0x1A                                                            */ 

  __IO uint16_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */

  uint16_t  RESERVED7;    /*!< Reserved, 0x1E                                                            */

  __IO uint16_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */

  uint16_t  RESERVED8;    /*!< Reserved, 0x22                                                            */    

}SPI_TypeDef;

/**

  * @brief TIM

  */

typedef struct

{

  __IO uint32_t CR1;             /*!< TIM control register 1,                      Address offset: 0x00 */

  __IO uint32_t CR2;             /*!< TIM control register 2,                      Address offset: 0x04 */

  __IO uint32_t SMCR;            /*!< TIM slave Mode Control register,             Address offset: 0x08 */

  __IO uint32_t DIER;            /*!< TIM DMA/interrupt enable register,           Address offset: 0x0C */

  __IO uint32_t SR;              /*!< TIM status register,                         Address offset: 0x10 */

  __IO uint32_t EGR;             /*!< TIM event generation register,               Address offset: 0x14 */

  __IO uint32_t CCMR1;           /*!< TIM  capture/compare mode register 1,        Address offset: 0x18 */

  __IO uint32_t CCMR2;           /*!< TIM  capture/compare mode register 2,        Address offset: 0x1C */

  __IO uint32_t CCER;            /*!< TIM capture/compare enable register,         Address offset: 0x20 */

  __IO uint32_t CNT;             /*!< TIM counter register,                        Address offset: 0x24 */

  __IO uint32_t PSC;             /*!< TIM prescaler register,                      Address offset: 0x28 */

  __IO uint32_t ARR;             /*!< TIM auto-reload register,                    Address offset: 0x2C */

  __IO uint32_t RCR;             /*!< TIM  repetition counter register,            Address offset: 0x30 */

  __IO uint32_t CCR1;            /*!< TIM capture/compare register 1,              Address offset: 0x34 */

  __IO uint32_t CCR2;            /*!< TIM capture/compare register 2,              Address offset: 0x38 */

  __IO uint32_t CCR3;            /*!< TIM capture/compare register 3,              Address offset: 0x3C */

  __IO uint32_t CCR4;            /*!< TIM capture/compare register 4,              Address offset: 0x40 */

  __IO uint32_t BDTR;            /*!< TIM break and dead-time register,            Address offset: 0x44 */

  __IO uint32_t DCR;             /*!< TIM DMA control register,                    Address offset: 0x48 */

  __IO uint32_t DMAR;            /*!< TIM DMA address for full transfer register,  Address offset: 0x4C */

  __IO uint32_t OR;              /*!< TIM option register,                         Address offset: 0x50 */

}TIM_TypeDef;

/**

  * @brief Universal Synchronous Asynchronous Receiver Transmitter

  */

typedef struct

{

  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */ 

  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */ 

  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */

  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */

  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */

  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */  

  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */

  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */

  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */

  __IO uint16_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */

  uint16_t  RESERVED1;  /*!< Reserved, 0x26                                                 */

  __IO uint16_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */

  uint16_t  RESERVED2;  /*!< Reserved, 0x2A                                                 */

}USART_TypeDef;

/**

  * @brief Window WATCHDOG

  */

typedef struct

{

  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */

  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */

  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */

}WWDG_TypeDef;

/**

  * @}

  */

/** @addtogroup Peripheral_memory_map

  * @{

  */

#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */

#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */

#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */

/*!< Peripheral memory map */

#define APBPERIPH_BASE        PERIPH_BASE

#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000)

#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000)

#define TIM3_BASE             (APBPERIPH_BASE + 0x00000400)

#define TIM14_BASE            (APBPERIPH_BASE + 0x00002000)

#define RTC_BASE              (APBPERIPH_BASE + 0x00002800)

#define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00)

#define IWDG_BASE             (APBPERIPH_BASE + 0x00003000)

#define I2C1_BASE             (APBPERIPH_BASE + 0x00005400)

#define PWR_BASE              (APBPERIPH_BASE + 0x00007000)

#define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000)

#define EXTI_BASE             (APBPERIPH_BASE + 0x00010400)

#define ADC1_BASE             (APBPERIPH_BASE + 0x00012400)

#define ADC_BASE              (APBPERIPH_BASE + 0x00012708)

#define TIM1_BASE             (APBPERIPH_BASE + 0x00012C00)

#define SPI1_BASE             (APBPERIPH_BASE + 0x00013000)

#define USART1_BASE           (APBPERIPH_BASE + 0x00013800)

#define TIM16_BASE            (APBPERIPH_BASE + 0x00014400)

#define TIM17_BASE            (APBPERIPH_BASE + 0x00014800)

#define DBGMCU_BASE           (APBPERIPH_BASE + 0x00015800)

#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000)

#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008)

#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001C)

#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030)

#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044)

#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058)

#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000)

#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */

#define OB_BASE               ((uint32_t)0x1FFFF800)        /*!< FLASH Option Bytes base address */

#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000)

#define GPIOA_BASE            (AHB2PERIPH_BASE + 0x00000000)

#define GPIOB_BASE            (AHB2PERIPH_BASE + 0x00000400)

#define GPIOC_BASE            (AHB2PERIPH_BASE + 0x00000800)

#define GPIOD_BASE            (AHB2PERIPH_BASE + 0x00000C00)

#define GPIOF_BASE            (AHB2PERIPH_BASE + 0x00001400)

/**

  * @}

  */

/** @addtogroup Peripheral_declaration

  * @{

  */

#define TIM3                ((TIM_TypeDef *) TIM3_BASE)

#define TIM14               ((TIM_TypeDef *) TIM14_BASE)

#define RTC                 ((RTC_TypeDef *) RTC_BASE)

#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)

#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)

#define I2C1                ((I2C_TypeDef *) I2C1_BASE)

#define PWR                 ((PWR_TypeDef *) PWR_BASE)

#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)

#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)

#define ADC1                ((ADC_TypeDef *) ADC1_BASE)

#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)

#define TIM1                ((TIM_TypeDef *) TIM1_BASE)

#define SPI1                ((SPI_TypeDef *) SPI1_BASE)

#define USART1              ((USART_TypeDef *) USART1_BASE)

#define TIM16               ((TIM_TypeDef *) TIM16_BASE)

#define TIM17               ((TIM_TypeDef *) TIM17_BASE)

#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)

#define DMA1                ((DMA_TypeDef *) DMA1_BASE)

#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)

#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)

#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)

#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)

#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)

#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)

#define OB                  ((OB_TypeDef *) OB_BASE) 

#define RCC                 ((RCC_TypeDef *) RCC_BASE)

#define CRC                 ((CRC_TypeDef *) CRC_BASE)

#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)

#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)

#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)

#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)

#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)

/**

  * @}

  */

/** @addtogroup Exported_constants

  * @{

  */

  /** @addtogroup Peripheral_Registers_Bits_Definition

  * @{

  */

/******************************************************************************/

/*                         Peripheral Registers Bits Definition               */

/******************************************************************************/

/******************************************************************************/

/*                                                                            */

/*                      Analog to Digital Converter (ADC)                     */

/*                                                                            */

/******************************************************************************/

/********************  Bits definition for ADC_ISR register  ******************/

#define ADC_ISR_AWD                          ((uint32_t)0x00000080)        /*!< Analog watchdog flag */

#define ADC_ISR_OVR                          ((uint32_t)0x00000010)        /*!< Overrun flag */

#define ADC_ISR_EOSEQ                        ((uint32_t)0x00000008)        /*!< End of Sequence flag */

#define ADC_ISR_EOC                          ((uint32_t)0x00000004)        /*!< End of Conversion */

#define ADC_ISR_EOSMP                        ((uint32_t)0x00000002)        /*!< End of sampling flag */

#define ADC_ISR_ADRDY                        ((uint32_t)0x00000001)        /*!< ADC Ready */

/* Old EOSEQ bit definition, maintained for legacy purpose */

#define ADC_ISR_EOS                          ADC_ISR_EOSEQ

/********************  Bits definition for ADC_IER register  ******************/

#define ADC_IER_AWDIE                        ((uint32_t)0x00000080)        /*!< Analog Watchdog interrupt enable */

#define ADC_IER_OVRIE                        ((uint32_t)0x00000010)        /*!< Overrun interrupt enable */

#define ADC_IER_EOSEQIE                      ((uint32_t)0x00000008)        /*!< End of Sequence of conversion interrupt enable */

#define ADC_IER_EOCIE                        ((uint32_t)0x00000004)        /*!< End of Conversion interrupt enable */

#define ADC_IER_EOSMPIE                      ((uint32_t)0x00000002)        /*!< End of sampling interrupt enable */

#define ADC_IER_ADRDYIE                      ((uint32_t)0x00000001)        /*!< ADC Ready interrupt enable */

/* Old EOSEQIE bit definition, maintained for legacy purpose */

#define ADC_IER_EOSIE                        ADC_IER_EOSEQIE

/********************  Bits definition for ADC_CR register  *******************/

#define ADC_CR_ADCAL                         ((uint32_t)0x80000000)        /*!< ADC calibration */

#define ADC_CR_ADSTP                         ((uint32_t)0x00000010)        /*!< ADC stop of conversion command */

#define ADC_CR_ADSTART                       ((uint32_t)0x00000004)        /*!< ADC start of conversion */

#define ADC_CR_ADDIS                         ((uint32_t)0x00000002)        /*!< ADC disable command */

#define ADC_CR_ADEN                          ((uint32_t)0x00000001)        /*!< ADC enable control */

/*******************  Bits definition for ADC_CFGR1 register  *****************/

#define  ADC_CFGR1_AWDCH                      ((uint32_t)0x7C000000)       /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */

#define  ADC_CFGR1_AWDCH_0                    ((uint32_t)0x04000000)       /*!< Bit 0 */

#define  ADC_CFGR1_AWDCH_1                    ((uint32_t)0x08000000)       /*!< Bit 1 */

#define  ADC_CFGR1_AWDCH_2                    ((uint32_t)0x10000000)       /*!< Bit 2 */

#define  ADC_CFGR1_AWDCH_3                    ((uint32_t)0x20000000)       /*!< Bit 3 */

#define  ADC_CFGR1_AWDCH_4                    ((uint32_t)0x40000000)       /*!< Bit 4 */

#define  ADC_CFGR1_AWDEN                      ((uint32_t)0x00800000)       /*!< Analog watchdog enable on regular channels */

#define  ADC_CFGR1_AWDSGL                     ((uint32_t)0x00400000)       /*!< Enable the watchdog on a single channel or on all channels  */

#define  ADC_CFGR1_DISCEN                     ((uint32_t)0x00010000)       /*!< Discontinuous mode on regular channels */

#define  ADC_CFGR1_AUTOFF                     ((uint32_t)0x00008000)       /*!< ADC auto power off */

#define  ADC_CFGR1_WAIT                       ((uint32_t)0x00004000)       /*!< ADC wait conversion mode */

#define  ADC_CFGR1_CONT                       ((uint32_t)0x00002000)       /*!< Continuous Conversion */

#define  ADC_CFGR1_OVRMOD                     ((uint32_t)0x00001000)       /*!< Overrun mode */

#define  ADC_CFGR1_EXTEN                      ((uint32_t)0x00000C00)       /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */

#define  ADC_CFGR1_EXTEN_0                    ((uint32_t)0x00000400)       /*!< Bit 0 */

#define  ADC_CFGR1_EXTEN_1                    ((uint32_t)0x00000800)       /*!< Bit 1 */

#define  ADC_CFGR1_EXTSEL                     ((uint32_t)0x000001C0)       /*!< EXTSEL[2:0] bits (External Event Select for regular group) */

#define  ADC_CFGR1_EXTSEL_0                   ((uint32_t)0x00000040)       /*!< Bit 0 */

#define  ADC_CFGR1_EXTSEL_1                   ((uint32_t)0x00000080)       /*!< Bit 1 */

#define  ADC_CFGR1_EXTSEL_2                   ((uint32_t)0x00000100)       /*!< Bit 2 */

#define  ADC_CFGR1_ALIGN                      ((uint32_t)0x00000020)       /*!< Data Alignment */

#define  ADC_CFGR1_RES                        ((uint32_t)0x00000018)       /*!< RES[1:0] bits (Resolution) */

#define  ADC_CFGR1_RES_0                      ((uint32_t)0x00000008)       /*!< Bit 0 */

#define  ADC_CFGR1_RES_1                      ((uint32_t)0x00000010)       /*!< Bit 1 */

#define  ADC_CFGR1_SCANDIR                    ((uint32_t)0x00000004)       /*!< Sequence scan direction */

#define  ADC_CFGR1_DMACFG                     ((uint32_t)0x00000002)       /*!< Direct memory access configuration */

#define  ADC_CFGR1_DMAEN                      ((uint32_t)0x00000001)       /*!< Direct memory access enable */

/* Old WAIT bit definition, maintained for legacy purpose */

#define  ADC_CFGR1_AUTDLY                     ADC_CFGR1_WAIT

/*******************  Bits definition for ADC_CFGR2 register  *****************/

#define  ADC_CFGR2_CKMODE                     ((uint32_t)0xC0000000)       /*!< ADC clock mode */

#define  ADC_CFGR2_CKMODE_1                   ((uint32_t)0x80000000)       /*!< ADC clocked by PCLK div4 */

#define  ADC_CFGR2_CKMODE_0                   ((uint32_t)0x40000000)       /*!< ADC clocked by PCLK div2 */

/* Old bit definition, maintained for legacy purpose */

#define  ADC_CFGR2_JITOFFDIV4                 ADC_CFGR2_CKMODE_1           /*!< ADC clocked by PCLK div4 */

#define  ADC_CFGR2_JITOFFDIV2                 ADC_CFGR2_CKMODE_0           /*!< ADC clocked by PCLK div2 */

/******************  Bit definition for ADC_SMPR register  ********************/

#define  ADC_SMPR_SMP                      ((uint32_t)0x00000007)        /*!< SMP[2:0] bits (Sampling time selection) */

#define  ADC_SMPR_SMP_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */

#define  ADC_SMPR_SMP_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */

#define  ADC_SMPR_SMP_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */

/* Old bit definition, maintained for legacy purpose */

#define  ADC_SMPR1_SMPR                      ADC_SMPR_SMP        /*!< SMP[2:0] bits (Sampling time selection) */

#define  ADC_SMPR1_SMPR_0                    ADC_SMPR_SMP_0        /*!< Bit 0 */

#define  ADC_SMPR1_SMPR_1                    ADC_SMPR_SMP_1        /*!< Bit 1 */

#define  ADC_SMPR1_SMPR_2                    ADC_SMPR_SMP_2        /*!< Bit 2 */

/*******************  Bit definition for ADC_TR register  ********************/

#define  ADC_TR_HT                          ((uint32_t)0x0FFF0000)        /*!< Analog watchdog high threshold */

#define  ADC_TR_LT                          ((uint32_t)0x00000FFF)        /*!< Analog watchdog low threshold */

/* Old bit definition, maintained for legacy purpose */

#define  ADC_HTR_HT                          ADC_TR_HT                    /*!< Analog watchdog high threshold */

#define  ADC_LTR_LT                          ADC_TR_LT                    /*!< Analog watchdog low threshold */

/******************  Bit definition for ADC_CHSELR register  ******************/

#define  ADC_CHSELR_CHSEL18                   ((uint32_t)0x00040000)        /*!< Channel 18 selection */

#define  ADC_CHSELR_CHSEL17                   ((uint32_t)0x00020000)        /*!< Channel 17 selection */

#define  ADC_CHSELR_CHSEL16                   ((uint32_t)0x00010000)        /*!< Channel 16 selection */

#define  ADC_CHSELR_CHSEL15                   ((uint32_t)0x00008000)        /*!< Channel 15 selection */

#define  ADC_CHSELR_CHSEL14                   ((uint32_t)0x00004000)        /*!< Channel 14 selection */

#define  ADC_CHSELR_CHSEL13                   ((uint32_t)0x00002000)        /*!< Channel 13 selection */

#define  ADC_CHSELR_CHSEL12                   ((uint32_t)0x00001000)        /*!< Channel 12 selection */

#define  ADC_CHSELR_CHSEL11                   ((uint32_t)0x00000800)        /*!< Channel 11 selection */

#define  ADC_CHSELR_CHSEL10                   ((uint32_t)0x00000400)        /*!< Channel 10 selection */

#define  ADC_CHSELR_CHSEL9                    ((uint32_t)0x00000200)        /*!< Channel 9 selection */

#define  ADC_CHSELR_CHSEL8                    ((uint32_t)0x00000100)        /*!< Channel 8 selection */

#define  ADC_CHSELR_CHSEL7                    ((uint32_t)0x00000080)        /*!< Channel 7 selection */

#define  ADC_CHSELR_CHSEL6                    ((uint32_t)0x00000040)        /*!< Channel 6 selection */

#define  ADC_CHSELR_CHSEL5                    ((uint32_t)0x00000020)        /*!< Channel 5 selection */

#define  ADC_CHSELR_CHSEL4                    ((uint32_t)0x00000010)        /*!< Channel 4 selection */

#define  ADC_CHSELR_CHSEL3                    ((uint32_t)0x00000008)        /*!< Channel 3 selection */

#define  ADC_CHSELR_CHSEL2                    ((uint32_t)0x00000004)        /*!< Channel 2 selection */

#define  ADC_CHSELR_CHSEL1                    ((uint32_t)0x00000002)        /*!< Channel 1 selection */

#define  ADC_CHSELR_CHSEL0                    ((uint32_t)0x00000001)        /*!< Channel 0 selection */

/********************  Bit definition for ADC_DR register  ********************/

#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!< Regular data */