therm Changeset - c941d532caa0 · protofusion repositories

Changeset - c941d532caa0

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cortex-f0

0 2 2

Ethan Zonca - 10 years ago 2015-01-03 00:21:07
ez@ethanzonca.com

Added dummy system files, need to generate with the cube or spreadsheet

4 files changed with 492 insertions and 0 deletions:

main.c

ssd1306.c

system_stm32f0xx.c

385

system_stm32f0xx.h

105

0 comments (0 inline, 0 general)

main.c

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 #include "main.h"
 #include "stm32f0xx_conf.h"
 #include "ssd1306.h"
 #include "config.h"
 #include "eeprom_min.h"
 #include "gpio.h"
 #include "spi.h"
 // USB includes
 //#include "hw_config.h"
 //#include "usb_lib.h"
 //#include "usb_desc.h"
 //#include "usb_pwr.h"
 //#include "stringhelpers.h"
 // TODO: Grab buttonpresses with interrupts
 // USB Supporting Vars
 extern __IO uint8_t Receive_Buffer[64];
 extern __IO  uint32_t Receive_length ;
 extern __IO  uint32_t length ;
 uint8_t Send_Buffer[64];
 uint32_t packet_sent=1;
 uint32_t packet_receive=1;
 enum tempunits {
     TEMP_UNITS_CELSIUS = 0,
     TEMP_UNITS_FAHRENHEIT,
 };
 // Globalish setting vars
 uint8_t boottobrew = 0;
 uint8_t temp_units = TEMP_UNITS_CELSIUS;
 uint16_t windup_guard = 1;
 uint16_t k_p = 1;
 uint16_t k_i = 1;
 uint16_t k_d = 1;
 uint8_t ignore_tc_error  = 0;
 // ISR ticks var
 volatile uint32_t ticks = 0;
 int16_t setpoint_brew = 0;
 int16_t setpoint_steam = 0;
 // State definition
 enum state {
     STATE_IDLE = 0,
     STATE_SETP,
     STATE_SETI,
     STATE_SETD,
     STATE_SETSTEPS,
     STATE_SETWINDUP,
     STATE_SETBOOTTOBREW,
     STATE_SETUNITS,
     STATE_PREHEAT_BREW,
     STATE_MAINTAIN_BREW,
     STATE_PREHEAT_STEAM,
     STATE_MAINTAIN_STEAM,
     STATE_TC_ERROR
 };
 uint8_t state = STATE_IDLE;
 static __IO uint32_t TimingDelay;
 // Move to header file
 void process();
 void machine();
 void restore_settings();
 void save_settings();
 void save_setpoints();
 int main(void)
+{
     // Init clocks
     SystemInit();
     // Init GPIO
     init_gpio();
     // Turn on power LED
     GPIO_SetBits(LED_POWER);
     // TODO: Awesome pwm of power LED (TIM4_CH4 or TIM11_CH1)
     // Configure 1ms SysTick (change if more temporal resolution needed)
     RCC_ClocksTypeDef RCC_Clocks;
     RCC_GetClocksFreq(&RCC_Clocks);
     SysTick_Config(RCC_Clocks.HCLK_Frequency / 1000);
     // Init SPI busses
     init_spi();

ssd1306.c

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 #include "stm32f0xx_conf.h"
 #include "ssd1306.h"
 // Write command to OLED
 void WriteCommand(unsigned char command)
+{
   SSD_A0_Low();
   SPI_SendByte(command);
   SPI_Wait();
+}
 // Write data to OLED
 void WriteData(unsigned char data)
+{
   SSD_A0_High();
   SPI_SendByte(data);
   SPI_Wait();
+}
 // Initialize OLED
 void ssd1306_Init(void)
+{
   /* Generate a reset */
   SSD_Reset_Low();
   uint32_t i;
   for(i=5000; i>1; i--)
   SSD_Reset_High();
   WriteCommand(0xAE);
   WriteCommand(0xD5);
   WriteCommand(0x80);
   WriteCommand(0xA8);
   WriteCommand(0x1F);
   WriteCommand(0xD3);
   WriteCommand(0x00);
   WriteCommand(0x40 | 0x00); // line #0
   WriteCommand(0x8D);
   WriteCommand(0x14); //10 or 14 if not externalvcc
   WriteCommand(0x20);
   WriteCommand(0x00);
 //  WriteCommand(0xA0 | 0x1); // segremap (normal)
   WriteCommand(0xA0); // segremap (flip)
 //  WriteCommand(0xC8); // comscandec (normal)
   WriteCommand(0xC0); // comscandec (flip)
   WriteCommand(0xDA); // setcompins
   WriteCommand(0x02);
   WriteCommand(0x81); // contrast
   WriteCommand(0x0F); // contrast value. 8f is a good one.
   WriteCommand(0xD9);
   WriteCommand(0xF1); //22 or F1 if not externalvcc
   WriteCommand(0xDB);
   WriteCommand(0x40);
   WriteCommand(0xA4); // dispalyallon_resume
   WriteCommand(0xA6); // normaldisplay
   WriteCommand(0xAF); // display on
+}
 // Times New Roman font
 const char fontData[240][5] =
 {                                       // Refer to "Times New Roman" Font Database
                                         //   Basic Characters
     {0x00,0x00,0x00,0x00,0x00},         //   (  0)    - 0x0020 No-Break Space
     {0x00,0x00,0x4F,0x00,0x00},         //   (  1)  ! - 0x0021 Exclamation Mark
     {0x00,0x07,0x00,0x07,0x00},         //   (  2)  " - 0x0022 Quotation Mark
     {0x14,0x7F,0x14,0x7F,0x14},         //   (  3)  # - 0x0023 Number Sign
     {0x24,0x2A,0x7F,0x2A,0x12},         //   (  4)  $ - 0x0024 Dollar Sign
     {0x23,0x13,0x08,0x64,0x62},         //   (  5)  % - 0x0025 Percent Sign
     {0x36,0x49,0x55,0x22,0x50},         //   (  6)  & - 0x0026 Ampersand
     {0x00,0x05,0x03,0x00,0x00},         //   (  7)  ' - 0x0027 Apostrophe
     {0x00,0x1C,0x22,0x41,0x00},         //   (  8)  ( - 0x0028 Left Parenthesis
     {0x00,0x41,0x22,0x1C,0x00},         //   (  9)  ) - 0x0029 Right Parenthesis
     {0x14,0x08,0x3E,0x08,0x14},         //   ( 10)  * - 0x002A Asterisk
     {0x08,0x08,0x3E,0x08,0x08},         //   ( 11)  + - 0x002B Plus Sign
     {0x00,0x50,0x30,0x00,0x00},         //   ( 12)  , - 0x002C Comma
     {0x08,0x08,0x08,0x08,0x08},         //   ( 13)  - - 0x002D Hyphen-Minus
     {0x00,0x60,0x60,0x00,0x00},         //   ( 14)  . - 0x002E Full Stop
     {0x20,0x10,0x08,0x04,0x02},         //   ( 15)  / - 0x002F Solidus
     {0x3E,0x51,0x49,0x45,0x3E},         //   ( 16)  0 - 0x0030 Digit Zero
     {0x00,0x42,0x7F,0x40,0x00},         //   ( 17)  1 - 0x0031 Digit One
     {0x42,0x61,0x51,0x49,0x46},         //   ( 18)  2 - 0x0032 Digit Two
     {0x21,0x41,0x45,0x4B,0x31},         //   ( 19)  3 - 0x0033 Digit Three
     {0x18,0x14,0x12,0x7F,0x10},         //   ( 20)  4 - 0x0034 Digit Four
     {0x27,0x45,0x45,0x45,0x39},         //   ( 21)  5 - 0x0035 Digit Five
     {0x3C,0x4A,0x49,0x49,0x30},         //   ( 22)  6 - 0x0036 Digit Six
     {0x01,0x71,0x09,0x05,0x03},         //   ( 23)  7 - 0x0037 Digit Seven
     {0x36,0x49,0x49,0x49,0x36},         //   ( 24)  8 - 0x0038 Digit Eight
     {0x06,0x49,0x49,0x29,0x1E},         //   ( 25)  9 - 0x0039 Dight Nine
     {0x00,0x36,0x36,0x00,0x00},         //   ( 26)  : - 0x003A Colon
     {0x00,0x56,0x36,0x00,0x00},         //   ( 27)  ; - 0x003B Semicolon
     {0x08,0x14,0x22,0x41,0x00},         //   ( 28)  < - 0x003C Less-Than Sign
     {0x14,0x14,0x14,0x14,0x14},         //   ( 29)  = - 0x003D Equals Sign
     {0x00,0x41,0x22,0x14,0x08},         //   ( 30)  > - 0x003E Greater-Than Sign
     {0x02,0x01,0x51,0x09,0x06},         //   ( 31)  ? - 0x003F Question Mark

system_stm32f0xx.c

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@@ new file 100644 @@
 /**
   ******************************************************************************
   * @file    system_stm32f0xx.c
   * @author  MCD Application Team
   * @version V1.0.0
   * @date    23-March-2012
   * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
   *          This file contains the system clock configuration for STM32F0xx devices,
   *          and is customized for use with STM32F0-DISCOVERY Kit.
   *          The STM32F0xx is configured to run at 48 MHz, following the three
   *          configuration below:
   *            - PLL_SOURCE_HSI (default): HSI (~8MHz) used to clock the PLL, and
   *                                        the PLL is used as system clock source.
   *            - PLL_SOURCE_HSE          : HSE (8MHz) used to clock the PLL, and
   *                                        the PLL is used as system clock source.
   *            - PLL_SOURCE_HSE_BYPASS   : HSE bypassed with an external clock
   *                                        (8MHz, coming from ST-Link) used to clock
   *                                        the PLL, and the PLL is used as system
   *                                        clock source.
+  *
+  *
   * 1.  This file provides two functions and one global variable to be called from
   *     user application:
   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
   *                      and Divider factors, AHB/APBx prescalers and Flash settings),
   *                      depending on the configuration selected (see above).
   *                      This function is called at startup just after reset and
   *                      before branch to main program. This call is made inside
   *                      the "startup_stm32f0xx.s" file.
+  *
   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
   *                                  by the user application to setup the SysTick
   *                                  timer or configure other parameters.
+  *
   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
   *                                 be called whenever the core clock is changed
   *                                 during program execution.
+  *
   * 2. After each device reset the HSI (8 MHz Range) is used as system clock source.
   *    Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
   *    configure the system clock before to branch to main program.
+  *
   * 3. If the system clock source selected by user fails to startup, the SystemInit()
   *    function will do nothing and HSI still used as system clock source. User can
   *    add some code to deal with this issue inside the SetSysClock() function.
+  *
   * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
   *    in "stm32f0xx.h" file. When HSE is used as system clock source, directly or
   *    through PLL, and you are using different crystal you have to adapt the HSE
   *    value to your own configuration.
+  *
   ******************************************************************************
   * @attention
+  *
   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
   * You may not use this file except in compliance with the License.
   * You may obtain a copy of the License at:
+  *
   *        http://www.st.com/software_license_agreement_liberty_v2
+  *
   * Unless required by applicable law or agreed to in writing, software
   * distributed under the License is distributed on an "AS IS" BASIS,
   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
   * See the License for the specific language governing permissions and
   * limitations under the License.
+  *
   ******************************************************************************
   */
 /** @addtogroup CMSIS
   * @{
   */
 /** @addtogroup stm32f0xx_system
   * @{
   */
 /** @addtogroup STM32F0xx_System_Private_Includes
   * @{
   */
 #include "stm32f0xx.h"
 /**
   * @}
   */
 /** @addtogroup STM32F0xx_System_Private_TypesDefinitions
   * @{
   */
 /**
   * @}
   */
 /** @addtogroup STM32F0xx_System_Private_Defines
   * @{
   */
 /* Select the PLL clock source */
 #define PLL_SOURCE_HSI        // HSI (~8MHz) used to clock the PLL, and the PLL is used as system clock source
 //#define PLL_SOURCE_HSE        // HSE (8MHz) used to clock the PLL, and the PLL is used as system clock source
 //#define PLL_SOURCE_HSE_BYPASS // HSE bypassed with an external clock (8MHz, coming from ST-Link) used to clock
                               // the PLL, and the PLL is used as system clock source
 /**
   * @}
   */
 /** @addtogroup STM32F0xx_System_Private_Macros
   * @{
   */
 /**
   * @}
   */
 /** @addtogroup STM32F0xx_System_Private_Variables
   * @{
   */
 uint32_t SystemCoreClock    = 48000000;
 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 /**
   * @}
   */
 /** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
   * @{
   */
 static void SetSysClock(void);
 /**
   * @}
   */
 /** @addtogroup STM32F0xx_System_Private_Functions
   * @{
   */
 /**
   * @brief  Setup the microcontroller system.
   *         Initialize the Embedded Flash Interface, the PLL and update the
   *         SystemCoreClock variable.
   * @param  None
   * @retval None
   */
 void SystemInit (void)
+{
   /* Set HSION bit */
   RCC->CR |= (uint32_t)0x00000001;
   /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
   RCC->CFGR &= (uint32_t)0xF8FFB80C;
   /* Reset HSEON, CSSON and PLLON bits */
   RCC->CR &= (uint32_t)0xFEF6FFFF;
   /* Reset HSEBYP bit */
   RCC->CR &= (uint32_t)0xFFFBFFFF;
   /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
   RCC->CFGR &= (uint32_t)0xFFC0FFFF;
   /* Reset PREDIV1[3:0] bits */
   RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
   /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */
   RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
   /* Reset HSI14 bit */
   RCC->CR2 &= (uint32_t)0xFFFFFFFE;
   /* Disable all interrupts */
   RCC->CIR = 0x00000000;
   /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
   SetSysClock();
+}
 /**
   * @brief  Update SystemCoreClock according to Clock Register Values
   *         The SystemCoreClock variable contains the core clock (HCLK), it can
   *         be used by the user application to setup the SysTick timer or configure
   *         other parameters.
+  *
   * @note   Each time the core clock (HCLK) changes, this function must be called
   *         to update SystemCoreClock variable value. Otherwise, any configuration
   *         based on this variable will be incorrect.
+  *
   * @note   - The system frequency computed by this function is not the real
   *           frequency in the chip. It is calculated based on the predefined
   *           constant and the selected clock source:
+  *
   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *
   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *
   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
   *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
   *         (*) HSI_VALUE is a constant defined in stm32f0xx.h file (default value
   *             8 MHz) but the real value may vary depending on the variations
   *             in voltage and temperature.
+  *
   *         (**) HSE_VALUE is a constant defined in stm32f0xx.h file (default value
   *              8 MHz), user has to ensure that HSE_VALUE is same as the real
   *              frequency of the crystal used. Otherwise, this function may
   *              have wrong result.
+  *
   *         - The result of this function could be not correct when using fractional
   *           value for HSE crystal.
   * @param  None
   * @retval None
   */
 void SystemCoreClockUpdate (void)
+{
   uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
   /* Get SYSCLK source -------------------------------------------------------*/
   tmp = RCC->CFGR & RCC_CFGR_SWS;
   switch (tmp)
+  {
     case 0x00:  /* HSI used as system clock */
       SystemCoreClock = HSI_VALUE;
       break;
     case 0x04:  /* HSE used as system clock */
       SystemCoreClock = HSE_VALUE;
       break;
     case 0x08:  /* PLL used as system clock */
       /* Get PLL clock source and multiplication factor ----------------------*/
       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
       pllmull = ( pllmull >> 18) + 2;
       if (pllsource == 0x00)
+      {
         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
       else
+      {
         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
         /* HSE oscillator clock selected as PREDIV1 clock entry */
         SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
+      }
       break;
     default: /* HSI used as system clock */
       SystemCoreClock = HSI_VALUE;
       break;
+  }
   /* Compute HCLK clock frequency ----------------*/
   /* Get HCLK prescaler */
   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
   /* HCLK clock frequency */
   SystemCoreClock >>= tmp;
+}
 /**
   * @brief  Configures the System clock frequency, AHB/APBx prescalers and Flash
   *         settings.
   * @note   This function should be called only once the RCC clock configuration
   *         is reset to the default reset state (done in SystemInit() function).
   * @param  None
   * @retval None
   */
 static void SetSysClock(void)
+{
   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
   /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/
 #if defined (PLL_SOURCE_HSI)
   /* At this stage the HSI is already enabled */
   /* Enable Prefetch Buffer and set Flash Latency */
   FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;
   /* HCLK = SYSCLK */
   RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
   /* PCLK = HCLK */
   RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;
   /* PLL configuration = (HSI/2) * 12 = ~48 MHz */
   RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
   RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_Div2 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL12);
   /* Enable PLL */
   RCC->CR |= RCC_CR_PLLON;
   /* Wait till PLL is ready */
   while((RCC->CR & RCC_CR_PLLRDY) == 0)
+  {
+  }
   /* Select PLL as system clock source */
   RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
   RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
   /* Wait till PLL is used as system clock source */
   while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
+  {
+  }
 #else
  #if defined (PLL_SOURCE_HSE)
   /* Enable HSE */
   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
  #elif defined (PLL_SOURCE_HSE_BYPASS)
   /* HSE oscillator bypassed with external clock */
   RCC->CR |= (uint32_t)(RCC_CR_HSEON | RCC_CR_HSEBYP);
  #endif /* PLL_SOURCE_HSE */
   /* Wait till HSE is ready and if Time out is reached exit */
   do
+  {
     HSEStatus = RCC->CR & RCC_CR_HSERDY;
     StartUpCounter++;
   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
     HSEStatus = (uint32_t)0x01;
+  }
   else
+  {
     HSEStatus = (uint32_t)0x00;
+  }
   if (HSEStatus == (uint32_t)0x01)
+  {
     /* Enable Prefetch Buffer and set Flash Latency */
     FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;
     /* HCLK = SYSCLK */
     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
     /* PCLK = HCLK */
     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;
     /* PLL configuration = HSE * 6 = 48 MHz */
     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL6);
     /* Enable PLL */
     RCC->CR |= RCC_CR_PLLON;
     /* Wait till PLL is ready */
     while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
     /* Select PLL as system clock source */
     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
     /* Wait till PLL is used as system clock source */
     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
+    {
+    }
+  }
   else
   { /* If HSE fails to start-up, the application will have wrong clock
          configuration. User can add here some code to deal with this error */
+  }
 #endif /* PLL_SOURCE_HSI */
+}
 /**
   * @}
   */
 /**
   * @}
   */
 /**
   * @}
   */
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

system_stm32f0xx.h

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@@ new file 100644 @@
 /**
   ******************************************************************************
   * @file    system_stm32f0xx.h
   * @author  MCD Application Team
   * @version V1.0.0
   * @date    23-March-2012
   * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer System Header File.
   ******************************************************************************
   * @attention
+  *
   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
   * You may not use this file except in compliance with the License.
   * You may obtain a copy of the License at:
+  *
   *        http://www.st.com/software_license_agreement_liberty_v2
+  *
   * Unless required by applicable law or agreed to in writing, software
   * distributed under the License is distributed on an "AS IS" BASIS,
   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
   * See the License for the specific language governing permissions and
   * limitations under the License.
+  *
   ******************************************************************************
   */
 /** @addtogroup CMSIS
   * @{
   */
 /** @addtogroup stm32f0xx_system
   * @{
   */
 /**
   * @brief Define to prevent recursive inclusion
   */
 #ifndef __SYSTEM_STM32F0XX_H
 #define __SYSTEM_STM32F0XX_H
 #ifdef __cplusplus
  extern "C" {
 #endif
 /** @addtogroup STM32F0xx_System_Includes
   * @{
   */
 /**
   * @}
   */
 /** @addtogroup STM32F0xx_System_Exported_types
   * @{
   */
 extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
 /**
   * @}
   */
 /** @addtogroup STM32F0xx_System_Exported_Constants
   * @{
   */
 /**
   * @}
   */
 /** @addtogroup STM32F0xx_System_Exported_Macros
   * @{
   */
 /**
   * @}
   */
 /** @addtogroup STM32F0xx_System_Exported_Functions
   * @{
   */
 extern void SystemInit(void);
 extern void SystemCoreClockUpdate(void);
 /**
   * @}
   */
 #ifdef __cplusplus
+}
 #endif
 #endif /*__SYSTEM_STM32F0XX_H */
 /**
   * @}
   */
 /**
   * @}
   */
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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