therm Changeset - f7aa98ec64f4 · protofusion repositories

Changeset - f7aa98ec64f4

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Ethan Zonca - 10 years ago 2014-07-10 17:23:37
ez@ethanzonca.com

Added system configuration from ST configuration excel file

4 files changed with 404 insertions and 934 deletions:

libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/system_stm32l1xx.c

533

main.c

ssd1306.c

system_stm32l1xx.c

395

396

0 comments (0 inline, 0 general)

libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/system_stm32l1xx.c

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deleted file

main.c

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 #include "main.h"
 #include "stm32l100c_discovery.h"
 #include "ssd1306.h"
 static __IO uint32_t TimingDelay;
 uint8_t BlinkSpeed = 0;
 /* Main */
 int main(void)
+{
    SystemInit();
    RCC_ClocksTypeDef RCC_Clocks;
   /* Configure LED3 and LED4 on STM32L100C-Discovery */
   STM_EVAL_LEDInit(LED3);
   STM_EVAL_LEDInit(LED4);
   /* Initialize User_Button on STM32L100C-Discovery */
   //STM_EVAL_PBInit(BUTTON_USER, BUTTON_MODE_GPIO);
   /* SysTick end of count event each 1ms */
   RCC_GetClocksFreq(&RCC_Clocks);
   SysTick_Config(RCC_Clocks.HCLK_Frequency / 1000);
  /* Initiate Blink Speed variable */
   BlinkSpeed = 1;
  /* Init lcd driver */
   SSD1303_Init();
   SSD1303_DrawPoint(3,3,1);
   SSD1303_DrawPoint(5,5,0);
 //  SSD1303_Init();
 //  SSD1303_DrawPoint(3,3,1);
 //  SSD1303_DrawPoint(5,5,0);
   STM_EVAL_LEDOn(LED4);
   Delay(1000);
   STM_EVAL_LEDOff(LED4);
   Delay(1000);
   while(1)
+  {
       /* Turn on LD4 Blue LED during 1s each time User button is pressed */
       STM_EVAL_LEDOn(LED4);
       //STM_EVAL_LEDOn(LED3);
       /* wait for 1s */
       Delay(300);
       /* Turn off LD4 Blue LED after 1s each time User button is pressed */
       STM_EVAL_LEDOff(LED4);
       Delay(300);
+  }
+}
 /**
   * @brief  Inserts a delay time.
   * @param  nTime: specifies the delay time length, in 1 ms.
   * @retval None
   */
 void Delay(__IO uint32_t nTime)
+{
   TimingDelay = nTime;
   while(TimingDelay != 0);
+}
 /**
   * @brief  Decrements the TimingDelay variable.
   * @param  None
   * @retval None
   */
 void TimingDelay_Decrement(void)
+{
   if (TimingDelay != 0x00)
+  {
     TimingDelay--;
+  }
+}
 #ifdef  USE_FULL_ASSERT
 /**
   * @brief  Reports the name of the source file and the source line number
   *   where the assert_param error has occurred.
   * @param  file: pointer to the source file name
   * @param  line: assert_param error line source number
   * @retval None
   */
 void assert_failed(uint8_t* file, uint32_t line)
+{
   /* User can add his own implementation to report the file name and line number,
      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
   /* Infinite loop */
   while (1)
   {}
+}
 #endif

ssd1306.c

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 /*******************************************************************************
 * File Name          : SSD1303.c
 * Author             : lxyppc
 * Version            : V1.0
 * Date               : 10-01-21
 * Description        : SSD1303 operations
 *                      the SSH1101A is compatible with SSD1303
 *******************************************************************************/
 /* Includes ------------------------------------------------------------------*/
 #include "stm32l100c_discovery.h"
 #include "bsp.h"
 #include "ssd1306.h"
 #include "DrawText.h"
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
 #define   SSD1303_PAGE_NUMBER           8
 #define   SSD1303_COLUMN_NUMBER         128
 #define   SSD1303_COLUMN_MARGIN_START   2
 #define   SSD1303_COLUMN_MARGIN_END     2
 #define   SSD1303_X_PIXEL   128
 #define   SSD1303_Y_PIXEL   64
 /* Private macro -------------------------------------------------------------*/
 #define   SSD1303_Buffer    (_SSD1303_Buffer + SSD1303_COLUMN_MARGIN_START)
 /* Private variables ---------------------------------------------------------*/
 static  uint8_t  _SSD1303_Buffer[SSD1303_COLUMN_NUMBER*SSD1303_PAGE_NUMBER
 + SSD1303_COLUMN_MARGIN_START + SSD1303_COLUMN_MARGIN_END] = {0};
 static  uint8_t  _SSD1303_Buffer[SSD1303_COLUMN_NUMBER*SSD1303_PAGE_NUMBER + SSD1303_COLUMN_MARGIN_START + SSD1303_COLUMN_MARGIN_END] = {0};
 static  uint8_t  pageIndex = 0;
 static  uint8_t  iS_SSD_On = 0;
 static  uint8_t  pre_on = 0;
 static  uint8_t  curContrast = 0xCC;
 static  uint8_t  lastContrast = 0xCC;
 /* Private function prototypes -----------------------------------------------*/
 void  WriteCommand(unsigned char command);
 void  WriteData(unsigned char data);
 void  OnPageTransferDone(void);
 unsigned long SSD1303_OFF(void);
 unsigned long SSD1303_ON(void);
 unsigned char* SSD1303_GetBuffer()
+{
   return SSD1303_Buffer;
+}
 /*******************************************************************************
 * Function Name  : WriteCommand
 * Description    : Write command to the SSD1303
 * Input          : None
 * Output         : None
 * Return         : None
 *******************************************************************************/
 void WriteCommand(unsigned char command)
+{
   SSD_A0_Low();
   SPI_SendByte(command);
   SPI_Wait();
+}
 /*******************************************************************************
 * Function Name  : WriteData
 * Description    : Write data to the SSD1303
 * Input          : None
 * Output         : None
 * Return         : None
 *******************************************************************************/
 void WriteData(unsigned char data)
+{
   SSD_A0_High();
   SPI_SendByte(data);
   SPI_Wait();
+}
 /*******************************************************************************
 * Function Name  : SSD1303_Init
 * Description    : Initialize the SSD1303
 * Input          : None
 * Output         : None
 * Return         : None
 *******************************************************************************/
 void SSD1303_Init(void)
+{
   /* Initialize SPI2 */
   // TODO
   /* Generate a reset */
   SSD_Reset_Low();
   uint32_t i ;
   for(i=5000;--i;);
   SSD_Reset_High();
   /*************************************************
   // SSD1303 Initialization Command
   *************************************************/
   // Lower Column Address
   WriteCommand(0x00); /* Set Lower Column Address */
   // High Column Address
   WriteCommand(0x10); /* Set Higher Column Address*/
   // Display Start Line
   WriteCommand(0x40); /* Set Display Start Line */
 #ifdef    DEBUG_BOARD
   curContrast = lastContrast = 0x30;
 #else
   curContrast = lastContrast = 0xCF;
 #endif
   // Contrast Control Register
   WriteCommand(0x81); /* Set Contrast Control */
   WriteCommand(lastContrast); /* 0 ~ 255 0x1f*/
   // Re-map
   WriteCommand(0xA1); /* [A0]:column address 0 is map
   to SEG0 , [A1]: columnaddress 131 is map to SEG0*/
   // Entire Display ON/OFF
   WriteCommand(0xA4); /* A4=ON */
   // Normal or Inverse Display
   WriteCommand(0XA6); /* Normal Display*/
   // Multiplex Ratio
   WriteCommand(0xA8); /* Set Multiplex Ratio */
   WriteCommand(0x3f); /* Set to 36 Mux*/
   // Set DC-DC
   WriteCommand(0xAD); /* Set DC-DC */
   WriteCommand(0x8B); /* 8B=ON, 8A=Off */
   // Display ON/OFF
   WriteCommand(0xAE); /* AF=ON , AE=OFF*/
   // Display Offset
   WriteCommand(0xD3); /* Set Display Offset */
   WriteCommand(0x00); /* No offset */
   // Display Clock Divide
   WriteCommand(0xD5); /* Set Clock Divide */
   WriteCommand(0x20); /* Set to 80Hz */
   // Area Color Mode
   WriteCommand(0xD8); /* Set Area Color On or Off*/
   WriteCommand(0x00); /* Mono Mode */
   // COM Pins Hardware Configuration
   WriteCommand(0xDA); /* Set Pins HardwareConfiguration */
   WriteCommand(0x12);
   // VCOMH
   WriteCommand(0xDB); /* Set VCOMH */
   WriteCommand(0x00);
   // VP
   WriteCommand(0xD9); /* Set VP */
   WriteCommand(0x22); /* P1=2 , P2=2 */
   // Set Common output scan direction
   WriteCommand(0xc8);/* Set COM scan direction */
   // For SSD1306 Set the address mode
   WriteCommand(0x20);/* Set address mode */
   WriteCommand(0x00);/* Set address mode horizontal */
   // Set the page start address
   WriteCommand(0xb0);
   WriteCommand(0x00);
   WriteCommand(0x10);
   /* Turn on the controller */
   pre_on = SSD1303_ON();
 //  // Set Charge pump
 //  WriteCommand(0x8D); /* Set Charge pump */
 //  WriteCommand(0x14); /* 0x14=ON, 0x10=Off */
 //
 //  // Turn on the display
 //  WriteCommand(0xaf);
+}
 /*******************************************************************************
 * Function Name  : SSD1303_TurnOff
 * Description    : Turn off the SSD1303 controller
 * Input          : None
 * Output         : None
 * Return         : None
 *******************************************************************************/
 unsigned long SSD1303_TurnOff(void)
+{
   pre_on = 0;
   return iS_SSD_On;
+}
 /*******************************************************************************
 * Function Name  : SSD1303_TurnOn
 * Description    : Turn off the SSD1303 controller
 * Input          : None
 * Output         : None
 * Return         : None
 *******************************************************************************/
 unsigned long SSD1303_TurnOn(void)
+{
   pre_on = 1;
   return iS_SSD_On;
+}
 /*******************************************************************************
 * Function Name  : SSD1303_SetContrast
 * Description    : Set the SSD1303 contrast
 * Input          : None
 * Output         : None
 * Return         : None
 *******************************************************************************/
 unsigned char SSD1303_SetContrast(unsigned char contrast)
+{
   curContrast = contrast;
   return lastContrast;
+}
 /*******************************************************************************
 * Function Name  : SSD1303_GetContrast
 * Description    : Get the SSD1303 contrast
 * Input          : None
 * Output         : None
 * Return         : None
 *******************************************************************************/
 unsigned char SSD1303_GetContrast()
+{
   return lastContrast;
+}
 /*******************************************************************************
 * Function Name  : SSD1303_OFF
 * Description    : Turn off the SSD1303 controller
 * Input          : None
 * Output         : None
 * Return         : None
 *******************************************************************************/
 unsigned long SSD1303_OFF(void)
+{
   if(iS_SSD_On){
 #ifdef  DEBUG_UI
     uint32_t i = 0;
     for(i=0;i<SSD1303_COLUMN_NUMBER*SSD1303_PAGE_NUMBER;i++){
       SSD1303_Buffer[i] = 0;
+    }
 #else
     // Turn off the display
     WriteCommand(0xae);
     // Set Charge pump
     WriteCommand(0x8D); /* Set Charge pump */
     WriteCommand(0x10); /* 0x14=ON, 0x10=Off */
 #endif
     iS_SSD_On = 0;
+  }
   return iS_SSD_On;
+}
 /*******************************************************************************
 * Function Name  : SSD1303_ON
 * Description    : Turn on the SSD1303 controller
 * Input          : None
 * Output         : None
 * Return         : None
 *******************************************************************************/
 unsigned long SSD1303_ON(void)
+{
   if(!iS_SSD_On){
 #ifdef  DEBUG_UI
 #else
   #ifdef    DEBUG_BOARD
   #else
     // Set Charge pump
     WriteCommand(0x8D); /* Set Charge pump */
     WriteCommand(0x14); /* 0x14=ON, 0x10=Off */
   #endif
     // Turn on the display
     WriteCommand(0xaf);
 #endif
     iS_SSD_On = 1;
+  }
   return iS_SSD_On;
+}
 /*******************************************************************************
 * Function Name  : SSD1303_IsOn
 * Description    : Check whether the SSD1303 is on or off
 * Input          : None
 * Output         : None
 * Return         : None
 *******************************************************************************/
 unsigned long SSD1303_IsOn(void)
+{
   return iS_SSD_On;
+}
 /*******************************************************************************
 * Function Name  : OnPageTransferDone
 * Description    : Called when each page transfer done
 * Input          : None
 * Output         : None
 * Return         : None
 *******************************************************************************/
 void  OnPageTransferDone(void)
+{
   if(pageIndex == SSD1303_PAGE_NUMBER){
     pageIndex = 0;
     return;
+  }
 #ifdef    DEBUG_BOARD
   WriteCommand(0xb0 + pageIndex);
   if(pageIndex == 0){
     WriteCommand(0x00);
     WriteCommand(0x10);
+  }
   SSD_A0_High();
   DMA1_Channel5->CCR &= ((uint32_t)0xFFFFFFFE);
   DMA1_Channel5->CNDTR = SSD1303_COLUMN_NUMBER+SSD1303_COLUMN_MARGIN_START + SSD1303_COLUMN_MARGIN_END;
   DMA1_Channel5->CMAR = (uint32_t)(SSD1303_Buffer+SSD1303_COLUMN_NUMBER*pageIndex - SSD1303_COLUMN_MARGIN_START);
   DMA_SSD_1303->CCR |= ((uint32_t)0x00000001);
   pageIndex++;
 #else
   SSD_A0_High();
   DMA_SSD_1303->CCR &= ((uint32_t)0xFFFFFFFE);
   DMA_SSD_1303->CNDTR = SSD1303_COLUMN_NUMBER*SSD1303_PAGE_NUMBER;//+SSD1303_COLUMN_MARGIN_START + SSD1303_COLUMN_MARGIN_END;
   DMA_SSD_1303->CMAR = (uint32_t)(SSD1303_Buffer);//+SSD1303_COLUMN_NUMBER*pageIndex);
   //DMA_Cmd(DMA_SSD_1303, ENABLE);
   DMA_SSD_1303->CCR |= ((uint32_t)0x00000001);
 //  pageIndex++;
   pageIndex = SSD1303_PAGE_NUMBER;
 #endif
+}
 /*******************************************************************************
 * Function Name  : DMA1_Channel5_IRQHandler
 * Description    : This function handles DMA1 Channel 5 interrupt request.
 * Input          : None
 * Output         : None
 * Return         : None
 *******************************************************************************/
 void DMA_Handler_SSD_1303(void) //DMA1_Channel5_IRQHandler(void)
+{
   if(DMA_GetITStatus(DMA1_IT_TC5)){
     DMA_ClearITPendingBit(DMA1_IT_GL5);
     OnPageTransferDone();
+  }
+}
 /*******************************************************************************
 * Function Name  : StartPageTransfer
 * Description    : Start a new page transfer
 * Input          : None
 * Output         : None
 * Return         : None
 *******************************************************************************/
 void StartPageTransfer(void)
+{
   pageIndex = 0;
   if(pre_on){
     if(iS_SSD_On == 0){
       pre_on = SSD1303_ON();
+    }
   }else{
     if(iS_SSD_On){
       pre_on = SSD1303_OFF();
+    }
+  }
   if( curContrast != lastContrast ){
     lastContrast = curContrast;
     WriteCommand(0x81); /* Set Contrast Control */
     WriteCommand(lastContrast); /* 0 ~ 255 0x1f*/
+  }
   if(iS_SSD_On){
     OnPageTransferDone();
+  }
+}
 /*******************************************************************************
   Display related functions
  ******************************************************************************/
 /*******************************************************************************
 * Function Name  : SSD1303_DrawBlock
 * Description    : Draw a block with specify data to SSD1303
 * Input          : None
 * Output         : None
 * Return         : None
 *******************************************************************************/
 unsigned long SSD1303_DrawBlock(
   Pos_t x,
   Pos_t y,
   Pos_t cx,
   Pos_t cy,
   const unsigned char* data)
+{
   if(x >= SSD1303_X_PIXEL)return 0;
   if(y >= SSD1303_Y_PIXEL)return 0;
   if(x+cx > SSD1303_X_PIXEL ) cx = SSD1303_X_PIXEL - x ;
   if(y+cy > SSD1303_Y_PIXEL ) cy = SSD1303_Y_PIXEL - y ;
   unsigned char* pStart = SSD1303_Buffer + (y/8)*SSD1303_COLUMN_NUMBER + x;
   unsigned char offset1 = y%8;
   unsigned char offset2 = (cy+y)%8;
   if(data){
     unsigned char mask1 = (1<<offset1)-1;
     unsigned char mask2 = ~((1<<offset2)-1);
     cy = (cy+offset1)/8;
     Pos_t i = 0;
     for(i=0;i<cx;i++){
       Pos_t j = 0;
       unsigned short tmp = *pStart & mask1;
       for(;j<cy;j++){
         tmp |= (((unsigned short)data[j*cx])<<offset1);
         *(pStart + j*SSD1303_COLUMN_NUMBER) = tmp;
         tmp>>=8;
+      }
       if(offset2){
         tmp |= ((((unsigned short)data[j*cx])<<offset1) & (~mask2))
             | *(pStart + j*SSD1303_COLUMN_NUMBER) & mask2;
         *(pStart + j*SSD1303_COLUMN_NUMBER) = tmp;
+      }
       data++;
       pStart++;
+    }
   }else{
     unsigned char mask1 = ~((1<<offset1)-1);
     unsigned char mask2 = ((1<<offset2)-1);
     cy = (cy+offset1)/8;
     Pos_t i = 0;
     for(i=0;i<cx;i++){
       Pos_t j = 1;
       *pStart ^= mask1;
       for(;j<cy;j++){
         *(pStart + j*SSD1303_COLUMN_NUMBER) ^= 0xFF;
+      }
       if(offset2){
         *(pStart + j*SSD1303_COLUMN_NUMBER) ^= mask2;
+      }
       pStart++;
+    }
+  }
 //  if(!offset){
 //    for(Pos_t i=0;i<cx;i++){
 //      unsigned char tmp;
 //      Pos_t j = 0;
 //      for(;j<cy/8;j++){
 //        tmp = data[i+j*cx];
 //        *(pStart + j*SSD1303_COLUMN_NUMBER + i + x) = tmp;
 //      }
 //      if(cy&0x7){
 //        unsigned char mask1 = (1<<(cy&7)) - 1;
 //        unsigned char mask2 = 0xFF - mask1;
 //        tmp = (data[i+j*cx] & mask1)
 //            | (*(pStart + j*SSD1303_COLUMN_NUMBER + i + x) & mask2);
 //        *(pStart + j*SSD1303_COLUMN_NUMBER + i + x) = tmp;
 //      }
 //    }
 //  }else{
 //    for(Pos_t i=0;i<cx;i++){
 //      unsigned short tmp;
 //      for(Pos_t j=0;j<cy/8;j++){
 //        if(j == 0){
 //          // First line
 //          tmp = *(pStart + j*SSD1303_COLUMN_NUMBER + i + x) & mask;
 //        }
 //        tmp |= (((unsigned short)data[i+j*cx])<<offset);
 //        *(pStart + j*SSD1303_COLUMN_NUMBER + i + x) = tmp;
 //        tmp>>=8;
 //        if(j == (cy/8)-1){
 //          // Last line
 //          *(pStart + (j+1)*SSD1303_COLUMN_NUMBER + i + x) &= ~mask;
 //          *(pStart + (j+1)*SSD1303_COLUMN_NUMBER + i + x) |= tmp;
 //        }
 //      }
 //    }
 //  }

system_stm32l1xx.c

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 /**
   ******************************************************************************
   * @file    system_stm32l1xx.c
   * @author  MCD Application Team
   * @version V1.0.0
   * @date    29-July-2013
   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
   *          This file contains the system clock configuration for STM32L1xx Ultra
   *          Low power devices, and is generated by the clock configuration
   *          tool STM32L1xx_Clock_Configuration_V1.1.0.xls
+  *
   * 1.  This file provides two functions and one global variable to be called from
   *     user application:
   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
   *                      and Divider factors, AHB/APBx prescalers and Flash settings),
   *                      depending on the configuration made in the clock xls tool.
   *                      This function is called at startup just after reset and
   *                      before branch to main program. This call is made inside
   *                      the "startup_stm32l1xx_xx.s" file.
+  *
   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
   *                                  by the user application to setup the SysTick
   *                                  timer or configure other parameters.
+  *
   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
   *                                 be called whenever the core clock is changed
   *                                 during program execution.
+  *
   * 2. After each device reset the MSI (2.1 MHz Range) is used as system clock source.
   *    Then SystemInit() function is called, in "startup_stm32l1xx_xx.s" file, to
   *    configure the system clock before to branch to main program.
+  *
   * 3. If the system clock source selected by user fails to startup, the SystemInit()
   *    function will do nothing and MSI still used as system clock source. User can
   *    add some code to deal with this issue inside the SetSysClock() function.
+  *
   * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
   *    in "stm32l1xx.h" file. When HSE is used as system clock source, directly or
   *    through PLL, and you are using different crystal you have to adapt the HSE
   *    value to your own configuration.
+  *
   * 5. This file configures the system clock as follows:
   *=============================================================================
   *                         System Clock Configuration
   *=============================================================================
   *        System Clock source          | PLL(HSI)
   *-----------------------------------------------------------------------------
   *        SYSCLK                       | 32000000 Hz
   *-----------------------------------------------------------------------------
   *        HCLK                         | 32000000 Hz
   *-----------------------------------------------------------------------------
   *        AHB Prescaler                | 1
   *-----------------------------------------------------------------------------
   *        APB1 Prescaler               | 1
   *-----------------------------------------------------------------------------
   *        APB2 Prescaler               | 1
   *-----------------------------------------------------------------------------
   *        HSE Frequency                | 8000000 Hz
   *-----------------------------------------------------------------------------
   *        PLL DIV                      | 2
   *-----------------------------------------------------------------------------
   *        PLL MUL                      | 4
   *-----------------------------------------------------------------------------
   *        VDD                          | 3.3 V
   *-----------------------------------------------------------------------------
   *        Vcore                        | 1.8 V (Range 1)
   *-----------------------------------------------------------------------------
   *        Flash Latency                | 1 WS
   *-----------------------------------------------------------------------------
   *        Require 48MHz for USB clock  | Disabled
   *-----------------------------------------------------------------------------
   *=============================================================================
   ******************************************************************************
   * @attention
+  *
   * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
   * You may not use this file except in compliance with the License.
   * You may obtain a copy of the License at:
+  *
   *        http://www.st.com/software_license_agreement_liberty_v2
+  *
   * Unless required by applicable law or agreed to in writing, software
   * distributed under the License is distributed on an "AS IS" BASIS,
   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
   * See the License for the specific language governing permissions and
   * limitations under the License.
+  *
   ******************************************************************************
   */
 /** @addtogroup CMSIS
   * @{
   */
 /** @addtogroup stm32l1xx_system
   * @{
   */
 /** @addtogroup STM32L1xx_System_Private_Includes
   * @{
   */
 #include "stm32l1xx.h"
 /**
   * @}
   */
 /** @addtogroup STM32L1xx_System_Private_TypesDefinitions
   * @{
   */
 /**
   * @}
   */
 /** @addtogroup STM32L1xx_System_Private_Defines
   * @{
   */
 /*!< Uncomment the following line if you need to relocate your vector Table in
      Internal SRAM. */
 /* #define VECT_TAB_SRAM */
 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
                                   This value must be a multiple of 0x200. */
 /**
   * @}
   */
 /** @addtogroup STM32L1xx_System_Private_Macros
   * @{
   */
 /**
   * @}
   */
 /** @addtogroup STM32L1xx_System_Private_Variables
   * @{
   */
 uint32_t SystemCoreClock    = 32000000;
 __I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 /**
   * @}
   */
 /** @addtogroup STM32L1xx_System_Private_FunctionPrototypes
   * @{
   */
 static void SetSysClock(void);
 /**
   * @}
   */
 /** @addtogroup STM32L1xx_System_Private_Functions
   * @{
   */
 /**
   * @brief  Setup the microcontroller system.
   *         Initialize the Embedded Flash Interface, the PLL and update the
   *         SystemCoreClock variable.
   * @param  None
   * @retval None
   */
 void SystemInit (void)
+{
   /*!< Set MSION bit */
   RCC->CR |= (uint32_t)0x00000100;
   /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
   RCC->CFGR &= (uint32_t)0x88FFC00C;
   /*!< Reset HSION, HSEON, CSSON and PLLON bits */
   RCC->CR &= (uint32_t)0xEEFEFFFE;
   /*!< Reset HSEBYP bit */
   RCC->CR &= (uint32_t)0xFFFBFFFF;
   /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
   RCC->CFGR &= (uint32_t)0xFF02FFFF;
   /*!< Disable all interrupts */
   RCC->CIR = 0x00000000;
   /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
   SetSysClock();
 #ifdef VECT_TAB_SRAM
   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
 #else
   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
 #endif
+}
 /**
   * @brief  Update SystemCoreClock according to Clock Register Values
   *         The SystemCoreClock variable contains the core clock (HCLK), it can
   *         be used by the user application to setup the SysTick timer or configure
   *         other parameters.
+  *
   * @note   Each time the core clock (HCLK) changes, this function must be called
   *         to update SystemCoreClock variable value. Otherwise, any configuration
   *         based on this variable will be incorrect.
+  *
   * @note   - The system frequency computed by this function is not the real
   *           frequency in the chip. It is calculated based on the predefined
   *           constant and the selected clock source:
+  *
   *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
   *             value as defined by the MSI range.
+  *
   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *
   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *
   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
   *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
   *         (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value
   *             16 MHz) but the real value may vary depending on the variations
   *             in voltage and temperature.
+  *
   *         (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value
   *              8 MHz), user has to ensure that HSE_VALUE is same as the real
   *              frequency of the crystal used. Otherwise, this function may
   *              have wrong result.
+  *
   *         - The result of this function could be not correct when using fractional
   *           value for HSE crystal.
   * @param  None
   * @retval None
   */
 void SystemCoreClockUpdate (void)
+{
   uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
   /* Get SYSCLK source -------------------------------------------------------*/
   tmp = RCC->CFGR & RCC_CFGR_SWS;
   switch (tmp)
+  {
     case 0x00:  /* MSI used as system clock */
       msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
       SystemCoreClock = (32768 * (1 << (msirange + 1)));
       break;
     case 0x04:  /* HSI used as system clock */
       SystemCoreClock = HSI_VALUE;
       break;
     case 0x08:  /* HSE used as system clock */
       SystemCoreClock = HSE_VALUE;
       break;
     case 0x0C:  /* PLL used as system clock */
       /* Get PLL clock source and multiplication factor ----------------------*/
       pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
       plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
       pllmul = PLLMulTable[(pllmul >> 18)];
       plldiv = (plldiv >> 22) + 1;
       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
       if (pllsource == 0x00)
+      {
         /* HSI oscillator clock selected as PLL clock entry */
         SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
+      }
       else
+      {
         /* HSE selected as PLL clock entry */
         SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
+      }
       break;
     default: /* MSI used as system clock */
       msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
       SystemCoreClock = (32768 * (1 << (msirange + 1)));
       break;
+  }
   /* Compute HCLK clock frequency --------------------------------------------*/
   /* Get HCLK prescaler */
   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
   /* HCLK clock frequency */
   SystemCoreClock >>= tmp;
+}
 /**
   * @brief  Configures the System clock frequency, AHB/APBx prescalers and Flash
   *         settings.
   * @note   This function should be called only once the RCC clock configuration
   *         is reset to the default reset state (done in SystemInit() function).
   * @param  None
   * @retval None
   */
 static void SetSysClock(void)
+{
   __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
   /* Enable HSI */
   RCC->CR |= ((uint32_t)RCC_CR_HSION);
   /* Wait till HSI is ready and if Time out is reached exit */
   do
+  {
     HSIStatus = RCC->CR & RCC_CR_HSIRDY;
   } while((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT));
   if ((RCC->CR & RCC_CR_HSIRDY) != RESET)
+  {
     HSIStatus = (uint32_t)0x01;
+  }
   else
+  {
     HSIStatus = (uint32_t)0x00;
+  }
   if (HSIStatus == (uint32_t)0x01)
+  {
     /* Enable 64-bit access */
     FLASH->ACR |= FLASH_ACR_ACC64;
     /* Enable Prefetch Buffer */
     FLASH->ACR |= FLASH_ACR_PRFTEN;
     /* Flash 1 wait state */
     FLASH->ACR |= FLASH_ACR_LATENCY;
     /* Power enable */
     RCC->APB1ENR |= RCC_APB1ENR_PWREN;
     /* Select the Voltage Range 1 (1.8 V) */
     PWR->CR = PWR_CR_VOS_0;
     /* Wait Until the Voltage Regulator is ready */
     while((PWR->CSR & PWR_CSR_VOSF) != RESET)
+    {
+    }
     /* HCLK = SYSCLK /1*/
     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
     /* PCLK2 = HCLK /1*/
     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
     /* PCLK1 = HCLK /1*/
     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
     /*  PLL configuration */
     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL |
                                         RCC_CFGR_PLLDIV));
     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI | RCC_CFGR_PLLMUL4 | RCC_CFGR_PLLDIV2);
     /* Enable PLL */
     RCC->CR |= RCC_CR_PLLON;
     /* Wait till PLL is ready */
     while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
     /* Select PLL as system clock source */
     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
     /* Wait till PLL is used as system clock source */
     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
+    {
+    }
+  }
   else
+  {
     /* If HSI fails to start-up, the application will have wrong clock
        configuration. User can add here some code to deal with this error */
+  }
+}
 /**
   * @}
   */
 /**
   * @}
   */
 /**
   * @}
   */
 /******************* (C) COPYRIGHT 2013 STMicroelectronics *****END OF FILE****/
 /**
   ******************************************************************************
   * @file    system_stm32l1xx.c
   * @author  MCD Application Team
   * @version V1.2.0
   * @date    10-July-2014
   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
   *          This file contains the system clock configuration for STM32L1xx Ultra
   *          Low power devices, and is generated by the clock configuration
   *          tool  STM32L1xx_Clock_Configuration_V1.2.0.xls
+  *
   * 1.  This file provides two functions and one global variable to be called from
   *     user application:
   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
   *                      and Divider factors, AHB/APBx prescalers and Flash settings),
   *                      depending on the configuration made in the clock xls tool.
   *                      This function is called at startup just after reset and
   *                      before branch to main program. This call is made inside
   *                      the "startup_stm32l1xx_xx.s" file.
+  *
   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
   *                                  by the user application to setup the SysTick
   *                                  timer or configure other parameters.
+  *
   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
   *                                 be called whenever the core clock is changed
   *                                 during program execution.
+  *
   * 2. After each device reset the MSI (2.1 MHz Range) is used as system clock source.
   *    Then SystemInit() function is called, in "startup_stm32l1xx_xx.s" file, to
   *    configure the system clock before to branch to main program.
+  *
   * 3. If the system clock source selected by user fails to startup, the SystemInit()
   *    function will do nothing and MSI still used as system clock source. User can
   *    add some code to deal with this issue inside the SetSysClock() function.
+  *
   * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
   *    in "stm32l1xx.h" file. When HSE is used as system clock source, directly or
   *    through PLL, and you are using different crystal you have to adapt the HSE
   *    value to your own configuration.
+  *
   * 5. This file configures the system clock as follows:
   *=============================================================================
   *                         System Clock Configuration
   *=============================================================================
   *        System Clock source          | PLL(HSE)
   *-----------------------------------------------------------------------------
   *        SYSCLK                       | 32000000 Hz
   *-----------------------------------------------------------------------------
   *        HCLK                         | 32000000 Hz
   *-----------------------------------------------------------------------------
   *        AHB Prescaler                | 1
   *-----------------------------------------------------------------------------
   *        APB1 Prescaler               | 1
   *-----------------------------------------------------------------------------
   *        APB2 Prescaler               | 1
   *-----------------------------------------------------------------------------
   *        HSE Frequency                | 8000000 Hz
   *-----------------------------------------------------------------------------
   *        PLL DIV                      | 3
   *-----------------------------------------------------------------------------
   *        PLL MUL                      | 12
   *-----------------------------------------------------------------------------
   *        VDD                          | 3.3 V
   *-----------------------------------------------------------------------------
   *        Vcore                        | 1.8 V (Range 1)
   *-----------------------------------------------------------------------------
   *        Flash Latency                | 1 WS
   *-----------------------------------------------------------------------------
   *        Require 48MHz for USB clock  | Enabled
   *-----------------------------------------------------------------------------
   *=============================================================================
   * @attention
+  *
   * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
   * You may not use this file except in compliance with the License.
   * You may obtain a copy of the License at:
+  *
   *        http://www.st.com/software_license_agreement_liberty_v2
+  *
   * Unless required by applicable law or agreed to in writing, software
   * distributed under the License is distributed on an "AS IS" BASIS,
   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
   * See the License for the specific language governing permissions and
   * limitations under the License.
+  *
   ******************************************************************************
   */
 /** @addtogroup CMSIS
   * @{
   */
 /** @addtogroup stm32l1xx_system
   * @{
   */
 /** @addtogroup STM32L1xx_System_Private_Includes
   * @{
   */
 #include "stm32l1xx.h"
 /**
   * @}
   */
 /** @addtogroup STM32L1xx_System_Private_TypesDefinitions
   * @{
   */
 /**
   * @}
   */
 /** @addtogroup STM32L1xx_System_Private_Defines
   * @{
   */
 /*!< Uncomment the following line if you need to relocate your vector Table in
      Internal SRAM. */
 /* #define VECT_TAB_SRAM */
 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
                                   This value must be a multiple of 0x200. */
 /**
   * @}
   */
 /** @addtogroup STM32L1xx_System_Private_Macros
   * @{
   */
 /**
   * @}
   */
 /** @addtogroup STM32L1xx_System_Private_Variables
   * @{
   */
 uint32_t SystemCoreClock    = 32000000;
 __I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 /**
   * @}
   */
 /** @addtogroup STM32L1xx_System_Private_FunctionPrototypes
   * @{
   */
 static void SetSysClock(void);
 /**
   * @}
   */
 /** @addtogroup STM32L1xx_System_Private_Functions
   * @{
   */
 /**
   * @brief  Setup the microcontroller system.
   *         Initialize the Embedded Flash Interface, the PLL and update the
   *         SystemCoreClock variable.
   * @param  None
   * @retval None
   */
 void SystemInit (void)
+{
   /*!< Set MSION bit */
   RCC->CR |= (uint32_t)0x00000100;
   /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
   RCC->CFGR &= (uint32_t)0x88FFC00C;
   /*!< Reset HSION, HSEON, CSSON and PLLON bits */
   RCC->CR &= (uint32_t)0xEEFEFFFE;
   /*!< Reset HSEBYP bit */
   RCC->CR &= (uint32_t)0xFFFBFFFF;
   /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
   RCC->CFGR &= (uint32_t)0xFF02FFFF;
   /*!< Disable all interrupts */
   RCC->CIR = 0x00000000;
   /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
   SetSysClock();
 #ifdef VECT_TAB_SRAM
   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
 #else
   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
 #endif
+}
 /**
   * @brief  Update SystemCoreClock according to Clock Register Values
   *         The SystemCoreClock variable contains the core clock (HCLK), it can
   *         be used by the user application to setup the SysTick timer or configure
   *         other parameters.
+  *
   * @note   Each time the core clock (HCLK) changes, this function must be called
   *         to update SystemCoreClock variable value. Otherwise, any configuration
   *         based on this variable will be incorrect.
+  *
   * @note   - The system frequency computed by this function is not the real
   *           frequency in the chip. It is calculated based on the predefined
   *           constant and the selected clock source:
+  *
   *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
   *             value as defined by the MSI range.
+  *
   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *
   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *
   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
   *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
   *         (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value
   *             16 MHz) but the real value may vary depending on the variations
   *             in voltage and temperature.
+  *
   *         (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value
   *              8 MHz), user has to ensure that HSE_VALUE is same as the real
   *              frequency of the crystal used. Otherwise, this function may
   *              have wrong result.
+  *
   *         - The result of this function could be not correct when using fractional
   *           value for HSE crystal.
   * @param  None
   * @retval None
   */
 void SystemCoreClockUpdate (void)
+{
   uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
   /* Get SYSCLK source -------------------------------------------------------*/
   tmp = RCC->CFGR & RCC_CFGR_SWS;
   switch (tmp)
+  {
     case 0x00:  /* MSI used as system clock */
       msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
       SystemCoreClock = (32768 * (1 << (msirange + 1)));
       break;
     case 0x04:  /* HSI used as system clock */
       SystemCoreClock = HSI_VALUE;
       break;
     case 0x08:  /* HSE used as system clock */
       SystemCoreClock = HSE_VALUE;
       break;
     case 0x0C:  /* PLL used as system clock */
       /* Get PLL clock source and multiplication factor ----------------------*/
       pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
       plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
       pllmul = PLLMulTable[(pllmul >> 18)];
       plldiv = (plldiv >> 22) + 1;
       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
       if (pllsource == 0x00)
+      {
         /* HSI oscillator clock selected as PLL clock entry */
         SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
+      }
       else
+      {
         /* HSE selected as PLL clock entry */
         SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
+      }
       break;
     default: /* MSI used as system clock */
       msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
       SystemCoreClock = (32768 * (1 << (msirange + 1)));
       break;
+  }
   /* Compute HCLK clock frequency --------------------------------------------*/
   /* Get HCLK prescaler */
   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
   /* HCLK clock frequency */
   SystemCoreClock >>= tmp;
+}
 /**
   * @brief  Configures the System clock frequency, AHB/APBx prescalers and Flash
   *         settings.
   * @note   This function should be called only once the RCC clock configuration
   *         is reset to the default reset state (done in SystemInit() function).
   * @param  None
   * @retval None
   */
 static void SetSysClock(void)
+{
   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
   /* Enable HSE */
   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
   /* Wait till HSE is ready and if Time out is reached exit */
   do
+  {
     HSEStatus = RCC->CR & RCC_CR_HSERDY;
     StartUpCounter++;
   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
     HSEStatus = (uint32_t)0x01;
+  }
   else
+  {
     HSEStatus = (uint32_t)0x00;
+  }
   if (HSEStatus == (uint32_t)0x01)
+  {
     /* Enable 64-bit access */
     FLASH->ACR |= FLASH_ACR_ACC64;
     /* Enable Prefetch Buffer */
     FLASH->ACR |= FLASH_ACR_PRFTEN;
     /* Flash 1 wait state */
     FLASH->ACR |= FLASH_ACR_LATENCY;
     /* Power enable */
     RCC->APB1ENR |= RCC_APB1ENR_PWREN;
     /* Select the Voltage Range 1 (1.8 V) */
     PWR->CR = PWR_CR_VOS_0;
     /* Wait Until the Voltage Regulator is ready */
     while((PWR->CSR & PWR_CSR_VOSF) != RESET)
+    {
+    }
     /* HCLK = SYSCLK /1*/
     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
     /* PCLK2 = HCLK /1*/
     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
     /* PCLK1 = HCLK /1*/
     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
     /*  PLL configuration */
     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL |
                                         RCC_CFGR_PLLDIV));
     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL12 | RCC_CFGR_PLLDIV3);
     /* Enable PLL */
     RCC->CR |= RCC_CR_PLLON;
     /* Wait till PLL is ready */
     while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
     /* Select PLL as system clock source */
     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
     /* Wait till PLL is used as system clock source */
     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
+    {
+    }
+  }
   else
+  {
     /* If HSE fails to start-up, the application will have wrong clock
        configuration. User can add here some code to deal with this error */
+  }
+}
 /**
   * @}
   */
 /**
   * @}
   */
 /**
   * @}
   */
 /******************* (C) COPYRIGHT 2013 STMicroelectronics *****END OF FILE****/

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