therm Changeset - f7aa98ec64f4 · protofusion repositories

Changeset - f7aa98ec64f4

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Ethan Zonca - 10 years ago 2014-07-10 17:23:37
ez@ethanzonca.com

Added system configuration from ST configuration excel file

4 files changed with 30 insertions and 560 deletions:

libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/system_stm32l1xx.c

533

main.c

ssd1306.c

system_stm32l1xx.c

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libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/system_stm32l1xx.c

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deleted file

main.c

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@@ @@ -9,6 +9,7 @@ uint8_t BlinkSpeed = 0; @@
 /* Main */
 int main(void)
+{
    SystemInit();
    RCC_ClocksTypeDef RCC_Clocks;
   /* Configure LED3 and LED4 on STM32L100C-Discovery */
@@ @@ -27,9 +28,9 @@ int main(void) @@
   BlinkSpeed = 1;
  /* Init lcd driver */
   SSD1303_Init();
   SSD1303_DrawPoint(3,3,1);
   SSD1303_DrawPoint(5,5,0);
 //  SSD1303_Init();
 //  SSD1303_DrawPoint(3,3,1);
 //  SSD1303_DrawPoint(5,5,0);
   STM_EVAL_LEDOn(LED4);
   Delay(1000);

ssd1306.c

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@@ @@ -26,8 +26,7 @@ @@
 #define   SSD1303_Buffer    (_SSD1303_Buffer + SSD1303_COLUMN_MARGIN_START)
 /* Private variables ---------------------------------------------------------*/
 static  uint8_t  _SSD1303_Buffer[SSD1303_COLUMN_NUMBER*SSD1303_PAGE_NUMBER
 + SSD1303_COLUMN_MARGIN_START + SSD1303_COLUMN_MARGIN_END] = {0};
 static  uint8_t  _SSD1303_Buffer[SSD1303_COLUMN_NUMBER*SSD1303_PAGE_NUMBER + SSD1303_COLUMN_MARGIN_START + SSD1303_COLUMN_MARGIN_END] = {0};
 static  uint8_t  pageIndex = 0;
 static  uint8_t  iS_SSD_On = 0;
 static  uint8_t  pre_on = 0;
@@ @@ -81,6 +80,10 @@ void WriteData(unsigned char data) @@
 *******************************************************************************/
 void SSD1303_Init(void)
+{
   /* Initialize SPI2 */
   // TODO
   /* Generate a reset */
   SSD_Reset_Low();
   uint32_t i ;

system_stm32l1xx.c

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@@ @@ -2,12 +2,12 @@ @@
   ******************************************************************************
   * @file    system_stm32l1xx.c
   * @author  MCD Application Team
   * @version V1.0.0
   * @date    29-July-2013
   * @version V1.2.0
   * @date    10-July-2014
   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
   *          This file contains the system clock configuration for STM32L1xx Ultra
   *          Low power devices, and is generated by the clock configuration
-  *          tool STM32L1xx_Clock_Configuration_V1.1.0.xls
+  *          tool  STM32L1xx_Clock_Configuration_V1.2.0.xls
+  *
   * 1.  This file provides two functions and one global variable to be called from
   *     user application:
@@ @@ -43,7 +43,7 @@ @@
   *=============================================================================
   *                         System Clock Configuration
   *=============================================================================
-  *        System Clock source          | PLL(HSI)
+  *        System Clock source          | PLL(HSE)
   *-----------------------------------------------------------------------------
   *        SYSCLK                       | 32000000 Hz
   *-----------------------------------------------------------------------------
@@ @@ -57,9 +57,9 @@ @@
   *-----------------------------------------------------------------------------
   *        HSE Frequency                | 8000000 Hz
   *-----------------------------------------------------------------------------
-  *        PLL DIV                      | 2
+  *        PLL DIV                      | 3
   *-----------------------------------------------------------------------------
-  *        PLL MUL                      | 4
+  *        PLL MUL                      | 12
   *-----------------------------------------------------------------------------
   *        VDD                          | 3.3 V
   *-----------------------------------------------------------------------------
@@ @@ -67,10 +67,9 @@ @@
   *-----------------------------------------------------------------------------
   *        Flash Latency                | 1 WS
   *-----------------------------------------------------------------------------
-  *        Require 48MHz for USB clock  | Disabled
+  *        Require 48MHz for USB clock  | Enabled
   *-----------------------------------------------------------------------------
   *=============================================================================
   ******************************************************************************
   * @attention
+  *
   * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
@@ @@ -298,28 +297,29 @@ void SystemCoreClockUpdate (void) @@
   */
 static void SetSysClock(void)
+{
-  __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
   /* Enable HSI */
   RCC->CR |= ((uint32_t)RCC_CR_HSION);
   /* Enable HSE */
   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-  /* Wait till HSI is ready and if Time out is reached exit */
+  /* Wait till HSE is ready and if Time out is reached exit */
   do
+  {
     HSIStatus = RCC->CR & RCC_CR_HSIRDY;
   } while((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT));
     HSEStatus = RCC->CR & RCC_CR_HSERDY;
     StartUpCounter++;
   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-  if ((RCC->CR & RCC_CR_HSIRDY) != RESET)
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
-    HSIStatus = (uint32_t)0x01;
+    HSEStatus = (uint32_t)0x01;
+  }
   else
+  {
-    HSIStatus = (uint32_t)0x00;
+    HSEStatus = (uint32_t)0x00;
+  }
-  if (HSIStatus == (uint32_t)0x01)
+  if (HSEStatus == (uint32_t)0x01)
+  {
     /* Enable 64-bit access */
     FLASH->ACR |= FLASH_ACR_ACC64;
@@ @@ -330,14 +330,12 @@ static void SetSysClock(void) @@
     /* Flash 1 wait state */
     FLASH->ACR |= FLASH_ACR_LATENCY;
     /* Power enable */
     RCC->APB1ENR |= RCC_APB1ENR_PWREN;
     /* Select the Voltage Range 1 (1.8 V) */
     PWR->CR = PWR_CR_VOS_0;
     /* Wait Until the Voltage Regulator is ready */
     while((PWR->CSR & PWR_CSR_VOSF) != RESET)
+    {
@@ @@ -355,7 +353,7 @@ static void SetSysClock(void) @@
     /*  PLL configuration */
     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL |
                                         RCC_CFGR_PLLDIV));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI | RCC_CFGR_PLLMUL4 | RCC_CFGR_PLLDIV2);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL12 | RCC_CFGR_PLLDIV3);
     /* Enable PLL */
     RCC->CR |= RCC_CR_PLLON;
@@ @@ -376,7 +374,7 @@ static void SetSysClock(void) @@
+  }
   else
+  {
-    /* If HSI fails to start-up, the application will have wrong clock
+    /* If HSE fails to start-up, the application will have wrong clock
        configuration. User can add here some code to deal with this error */
+  }
+}
@@ @@ -394,3 +392,4 @@ static void SetSysClock(void) @@
   */
 /******************* (C) COPYRIGHT 2013 STMicroelectronics *****END OF FILE****/

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