Files
@ ab94f8a0a0c6
Branch filter:
Location: HydroBot/protomodule-firmware/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_usart.c - annotation
ab94f8a0a0c6
89.0 KiB
text/plain
Read analog ph sensor
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 | 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 3970a40efdc5 | /**
******************************************************************************
* @file stm32f0xx_hal_usart.c
* @author MCD Application Team
* @brief USART HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Universal Synchronous Asynchronous Receiver Transmitter
* Peripheral (USART).
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral Control functions
* + Peripheral State and Error functions
*
@verbatim
===============================================================================
##### How to use this driver #####
===============================================================================
[..]
The USART HAL driver can be used as follows:
(#) Declare a USART_HandleTypeDef handle structure (eg. USART_HandleTypeDef husart).
(#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API:
(++) Enable the USARTx interface clock.
(++) USART pins configuration:
(+++) Enable the clock for the USART GPIOs.
(+++) Configure these USART pins as alternate function pull-up.
(++) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
(+++) Configure the USARTx interrupt priority.
(+++) Enable the NVIC USART IRQ handle.
(++) USART interrupts handling:
-@@- The specific USART interrupts (Transmission complete interrupt,
RXNE interrupt and Error Interrupts) will be managed using the macros
__HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
(++) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs):
(+++) Declare a DMA handle structure for the Tx/Rx channel.
(+++) Enable the DMAx interface clock.
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
(+++) Configure the DMA Tx/Rx channel.
(+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
(#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
flow control and Mode (Receiver/Transmitter) in the husart handle Init structure.
(#) Initialize the USART registers by calling the HAL_USART_Init() API:
(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
by calling the customized HAL_USART_MspInit(&husart) API.
(#) Three operation modes are available within this driver :
*** Polling mode IO operation ***
=================================
[..]
(+) Send an amount of data in blocking mode using HAL_USART_Transmit()
(+) Receive an amount of data in blocking mode using HAL_USART_Receive()
*** Interrupt mode IO operation ***
===================================
[..]
(+) Send an amount of data in non blocking mode using HAL_USART_Transmit_IT()
(+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can
add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback
(+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can
add his own code by customization of function pointer HAL_USART_TxCpltCallback
(+) Receive an amount of data in non blocking mode using HAL_USART_Receive_IT()
(+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can
add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback
(+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
add his own code by customization of function pointer HAL_USART_RxCpltCallback
(+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_USART_ErrorCallback
*** DMA mode IO operation ***
==============================
[..]
(+) Send an amount of data in non blocking mode (DMA) using HAL_USART_Transmit_DMA()
(+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can
add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback
(+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can
add his own code by customization of function pointer HAL_USART_TxCpltCallback
(+) Receive an amount of data in non blocking mode (DMA) using HAL_USART_Receive_DMA()
(+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can
add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback
(+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
add his own code by customization of function pointer HAL_USART_RxCpltCallback
(+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_USART_ErrorCallback
(+) Pause the DMA Transfer using HAL_USART_DMAPause()
(+) Resume the DMA Transfer using HAL_USART_DMAResume()
(+) Stop the DMA Transfer using HAL_USART_DMAStop()
*** USART HAL driver macros list ***
=============================================
[..]
Below the list of most used macros in USART HAL driver.
(+) __HAL_USART_ENABLE: Enable the USART peripheral
(+) __HAL_USART_DISABLE: Disable the USART peripheral
(+) __HAL_USART_GET_FLAG : Check whether the specified USART flag is set or not
(+) __HAL_USART_CLEAR_FLAG : Clear the specified USART pending flag
(+) __HAL_USART_ENABLE_IT: Enable the specified USART interrupt
(+) __HAL_USART_DISABLE_IT: Disable the specified USART interrupt
[..]
(@) You can refer to the USART HAL driver header file for more useful macros
[..]
(@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to UART API's
HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and
HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal.h"
/** @addtogroup STM32F0xx_HAL_Driver
* @{
*/
/** @defgroup USART USART
* @brief HAL USART Synchronous module driver
* @{
*/
#ifdef HAL_USART_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup USART_Private_Constants USART Private Constants
* @{
*/
#define USART_DUMMY_DATA ((uint16_t) 0xFFFFU) /*!< USART transmitted dummy data */
#define USART_TEACK_REACK_TIMEOUT ( 1000U) /*!< USART TX or RX enable acknowledge time-out value */
#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by USART_SetConfig API */
#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | \
USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by USART_SetConfig API */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @addtogroup USART_Private_Functions
* @{
*/
static void USART_EndTransfer(USART_HandleTypeDef *husart);
static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
static void USART_DMAError(DMA_HandleTypeDef *hdma);
static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart);
static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart);
static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart);
static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart);
static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart);
static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup USART_Exported_Functions USART Exported Functions
* @{
*/
/** @defgroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to initialize the USART
in asynchronous and in synchronous modes.
(+) For the asynchronous mode only these parameters can be configured:
(++) Baud Rate
(++) Word Length
(++) Stop Bit
(++) Parity
(++) USART polarity
(++) USART phase
(++) USART LastBit
(++) Receiver/transmitter modes
[..]
The HAL_USART_Init() function follows the USART synchronous configuration
procedure (details for the procedure are available in reference manual).
@endverbatim
* @{
*/
/*
Additional Table: If the parity is enabled, then the MSB bit of the data written
in the data register is transmitted but is changed by the parity bit.
According to device capability (support or not of 7-bit word length),
frame length is either defined by the M bit (8-bits or 9-bits)
or by the M1 and M0 bits (7-bit, 8-bit or 9-bit).
Possible USART frame formats are as listed in the following table:
Table 1. USART frame format.
+-----------------------------------------------------------------------+
| M bit | PCE bit | USART frame |
|-------------------|-----------|---------------------------------------|
| 0 | 0 | | SB | 8-bit data | STB | |
|-------------------|-----------|---------------------------------------|
| 0 | 1 | | SB | 7-bit data | PB | STB | |
|-------------------|-----------|---------------------------------------|
| 1 | 0 | | SB | 9-bit data | STB | |
|-------------------|-----------|---------------------------------------|
| 1 | 1 | | SB | 8-bit data | PB | STB | |
+-----------------------------------------------------------------------+
| M1 bit | M0 bit | PCE bit | USART frame |
|---------|---------|-----------|---------------------------------------|
| 0 | 0 | 0 | | SB | 8 bit data | STB | |
|---------|---------|-----------|---------------------------------------|
| 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
|---------|---------|-----------|---------------------------------------|
| 0 | 1 | 0 | | SB | 9 bit data | STB | |
|---------|---------|-----------|---------------------------------------|
| 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
|---------|---------|-----------|---------------------------------------|
| 1 | 0 | 0 | | SB | 7 bit data | STB | |
|---------|---------|-----------|---------------------------------------|
| 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
+-----------------------------------------------------------------------+
*/
/**
* @brief Initialize the USART mode according to the specified
* parameters in the USART_InitTypeDef and initialize the associated handle.
* @param husart USART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
{
/* Check the USART handle allocation */
if(husart == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_USART_INSTANCE(husart->Instance));
if(husart->State == HAL_USART_STATE_RESET)
{
/* Allocate lock resource and initialize it */
husart->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK */
HAL_USART_MspInit(husart);
}
husart->State = HAL_USART_STATE_BUSY;
/* Disable the Peripheral */
__HAL_USART_DISABLE(husart);
/* Set the Usart Communication parameters */
if (USART_SetConfig(husart) == HAL_ERROR)
{
return HAL_ERROR;
}
/* In Synchronous mode, the following bits must be kept cleared:
- LINEN bit (if LIN is supported) in the USART_CR2 register
- SCEN (if Smartcard is supported), HDSEL and IREN (if IrDA is supported) bits in the USART_CR3 register. */
#if defined (USART_CR2_LINEN)
husart->Instance->CR2 &= ~USART_CR2_LINEN;
#endif
#if defined (USART_CR3_SCEN)
#if defined (USART_CR3_IREN)
husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
#else
husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL);
#endif
#else
#if defined (USART_CR3_IREN)
husart->Instance->CR3 &= ~(USART_CR3_HDSEL | USART_CR3_IREN);
#else
husart->Instance->CR3 &= ~(USART_CR3_HDSEL);
#endif
#endif
/* Enable the Peripheral */
__HAL_USART_ENABLE(husart);
/* TEACK and/or REACK to check before moving husart->State to Ready */
return (USART_CheckIdleState(husart));
}
/**
* @brief DeInitialize the USART peripheral.
* @param husart USART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
{
/* Check the USART handle allocation */
if(husart == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_USART_INSTANCE(husart->Instance));
husart->State = HAL_USART_STATE_BUSY;
husart->Instance->CR1 = 0x0U;
husart->Instance->CR2 = 0x0U;
husart->Instance->CR3 = 0x0U;
/* DeInit the low level hardware */
HAL_USART_MspDeInit(husart);
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_RESET;
/* Process Unlock */
__HAL_UNLOCK(husart);
return HAL_OK;
}
/**
* @brief Initialize the USART MSP.
* @param husart USART handle.
* @retval None
*/
__weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(husart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_USART_MspInit can be implemented in the user file
*/
}
/**
* @brief DeInitialize the USART MSP.
* @param husart USART handle.
* @retval None
*/
__weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(husart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_USART_MspDeInit can be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup USART_Exported_Functions_Group2 IO operation functions
* @brief USART Transmit and Receive functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
[..] This subsection provides a set of functions allowing to manage the USART synchronous
data transfers.
[..] The USART supports master mode only: it cannot receive or send data related to an input
clock (SCLK is always an output).
(#) There are two modes of transfer:
(++) Blocking mode: The communication is performed in polling mode.
The HAL status of all data processing is returned by the same function
after finishing transfer.
(++) No-Blocking mode: The communication is performed using Interrupts
or DMA, These APIs return the HAL status.
The end of the data processing will be indicated through the
dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
using DMA mode.
The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks
will be executed respectively at the end of the transmit or Receive process
The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected
(#) Blocking mode APIs are :
(++) HAL_USART_Transmit()in simplex mode
(++) HAL_USART_Receive() in full duplex receive only
(++) HAL_USART_TransmitReceive() in full duplex mode
(#) No-Blocking mode APIs with Interrupt are :
(++) HAL_USART_Transmit_IT()in simplex mode
(++) HAL_USART_Receive_IT() in full duplex receive only
(++) HAL_USART_TransmitReceive_IT()in full duplex mode
(++) HAL_USART_IRQHandler()
(#) No-Blocking mode APIs with DMA are :
(++) HAL_USART_Transmit_DMA()in simplex mode
(++) HAL_USART_Receive_DMA() in full duplex receive only
(++) HAL_USART_TransmitReceive_DMA() in full duplex mode
(++) HAL_USART_DMAPause()
(++) HAL_USART_DMAResume()
(++) HAL_USART_DMAStop()
(#) A set of Transfer Complete Callbacks are provided in Non-Blocking mode:
(++) HAL_USART_TxCpltCallback()
(++) HAL_USART_RxCpltCallback()
(++) HAL_USART_TxHalfCpltCallback()
(++) HAL_USART_RxHalfCpltCallback()
(++) HAL_USART_ErrorCallback()
(++) HAL_USART_TxRxCpltCallback()
(#) Non-Blocking mode transfers could be aborted using Abort API's :
(++) HAL_USART_Abort()
(++) HAL_USART_Abort_IT()
(#) For Abort services based on interrupts (HAL_USART_Abort_IT), a Abort Complete Callbacks is provided:
(++) HAL_USART_AbortCpltCallback()
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
Errors are handled as follows :
(++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
and HAL_USART_ErrorCallback() user callback is executed. Transfer is kept ongoing on USART side.
If user wants to abort it, Abort services should be called by user.
(++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
Error code is set to allow user to identify error type, and HAL_USART_ErrorCallback() user callback is executed.
@endverbatim
* @{
*/
/**
* @brief Simplex send an amount of data in blocking mode.
* @param husart USART handle.
* @param pTxData Pointer to data buffer.
* @param Size Amount of data to be sent.
* @param Timeout Timeout duration.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
* (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
{
uint16_t* tmp=0U;
uint32_t tickstart = 0U;
if(husart->State == HAL_USART_STATE_READY)
{
if((pTxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* In case of 9bits/No Parity transfer, pTxData buffer provided as input paramter
should be aligned on a u16 frontier, as data to be filled into TDR will be
handled through a u16 cast. */
if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
{
if((((uint32_t)pTxData)&1U) != 0U)
{
return HAL_ERROR;
}
}
/* Process Locked */
__HAL_LOCK(husart);
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_TX;
/* Init tickstart for timeout managment*/
tickstart = HAL_GetTick();
husart->TxXferSize = Size;
husart->TxXferCount = Size;
/* Check the remaining data to be sent */
while(husart->TxXferCount > 0)
{
husart->TxXferCount--;
if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
{
tmp = (uint16_t*) pTxData;
husart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
pTxData += 2U;
}
else
{
husart->Instance->TDR = (*pTxData++ & (uint8_t)0xFFU);
}
}
if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
/* At end of Tx process, restore husart->State to Ready */
husart->State = HAL_USART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(husart);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Receive an amount of data in blocking mode.
* @note To receive synchronous data, dummy data are simultaneously transmitted.
* @param husart USART handle.
* @param pRxData Pointer to data buffer.
* @param Size Amount of data to be received.
* @param Timeout Timeout duration.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
* (as received data will be handled using u16 pointer cast). Depending on compilation chain,
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pRxData.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
{
uint16_t* tmp=0U;
uint16_t uhMask;
uint32_t tickstart = 0U;
if(husart->State == HAL_USART_STATE_READY)
{
if((pRxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* In case of 9bits/No Parity transfer, pRxData buffer provided as input paramter
should be aligned on a u16 frontier, as data to be received from RDR will be
handled through a u16 cast. */
if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
{
if((((uint32_t)pRxData)&1U) != 0U)
{
return HAL_ERROR;
}
}
/* Process Locked */
__HAL_LOCK(husart);
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_RX;
/* Init tickstart for timeout managment*/
tickstart = HAL_GetTick();
husart->RxXferSize = Size;
husart->RxXferCount = Size;
/* Computation of USART mask to apply to RDR register */
USART_MASK_COMPUTATION(husart);
uhMask = husart->Mask;
/* as long as data have to be received */
while(husart->RxXferCount > 0U)
{
husart->RxXferCount--;
/* Wait until TC flag is set to send dummy byte in order to generate the
* clock for the slave to send data.
* Whatever the frame length (7, 8 or 9-bit long), the same dummy value
* can be written for all the cases. */
if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x0FFU);
/* Wait for RXNE Flag */
if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
{
tmp = (uint16_t*) pRxData ;
*tmp = (uint16_t)(husart->Instance->RDR & uhMask);
pRxData +=2;
}
else
{
*pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
}
}
/* At end of Rx process, restore husart->State to Ready */
husart->State = HAL_USART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(husart);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Full-Duplex Send and Receive an amount of data in blocking mode.
* @param husart USART handle.
* @param pTxData pointer to TX data buffer.
* @param pRxData pointer to RX data buffer.
* @param Size amount of data to be sent (same amount to be received).
* @param Timeout Timeout duration.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* address of user data buffers containing data to be sent/received, should be aligned on a half word frontier (16 bits)
* (as sent/received data will be handled using u16 pointer cast). Depending on compilation chain,
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData and pRxData.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
{
uint16_t* tmp=0U;
uint16_t uhMask;
uint32_t tickstart = 0U;
if(husart->State == HAL_USART_STATE_READY)
{
if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* In case of 9bits/No Parity transfer, pTxData and pRxData buffers provided as input paramter
should be aligned on a u16 frontier, as data to be filled into TDR/retrieved from RDR will be
handled through a u16 cast. */
if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
{
if(((((uint32_t)pTxData)&1U) != 0U) || ((((uint32_t)pRxData)&1U) != 0U))
{
return HAL_ERROR;
}
}
/* Process Locked */
__HAL_LOCK(husart);
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_RX;
/* Init tickstart for timeout managment*/
tickstart = HAL_GetTick();
husart->RxXferSize = Size;
husart->TxXferSize = Size;
husart->TxXferCount = Size;
husart->RxXferCount = Size;
/* Computation of USART mask to apply to RDR register */
USART_MASK_COMPUTATION(husart);
uhMask = husart->Mask;
/* Check the remain data to be sent */
while(husart->TxXferCount > 0U)
{
husart->TxXferCount--;
husart->RxXferCount--;
/* Wait until TC flag is set to send data */
if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
{
tmp = (uint16_t*) pTxData;
husart->Instance->TDR = (*tmp & uhMask);
pTxData += 2U;
}
else
{
husart->Instance->TDR = (*pTxData++ & (uint8_t)uhMask);
}
/* Wait for RXNE Flag */
if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
{
tmp = (uint16_t*) pRxData ;
*tmp = (uint16_t)(husart->Instance->RDR & uhMask);
pRxData +=2U;
}
else
{
*pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
}
}
/* At end of TxRx process, restore husart->State to Ready */
husart->State = HAL_USART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(husart);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Send an amount of data in interrupt mode.
* @param husart USART handle.
* @param pTxData pointer to data buffer.
* @param Size amount of data to be sent.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
* (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
{
if(husart->State == HAL_USART_STATE_READY)
{
if((pTxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* In case of 9bits/No Parity transfer, pTxData buffer provided as input paramter
should be aligned on a u16 frontier, as data to be filled into TDR will be
handled through a u16 cast. */
if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
{
if((((uint32_t)pTxData)&1U) != 0U)
{
return HAL_ERROR;
}
}
/* Process Locked */
__HAL_LOCK(husart);
husart->pTxBuffPtr = pTxData;
husart->TxXferSize = Size;
husart->TxXferCount = Size;
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_TX;
/* The USART Error Interrupts: (Frame error, noise error, overrun error)
are not managed by the USART Transmit Process to avoid the overrun interrupt
when the usart mode is configured for transmit and receive "USART_MODE_TX_RX"
to benefit for the frame error and noise interrupts the usart mode should be
configured only for transmit "USART_MODE_TX" */
/* Process Unlocked */
__HAL_UNLOCK(husart);
/* Enable the USART Transmit Data Register Empty Interrupt */
__HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Receive an amount of data in interrupt mode.
* @note To receive synchronous data, dummy data are simultaneously transmitted.
* @param husart USART handle.
* @param pRxData pointer to data buffer.
* @param Size amount of data to be received.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
* (as received data will be handled using u16 pointer cast). Depending on compilation chain,
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pRxData.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
{
if(husart->State == HAL_USART_STATE_READY)
{
if((pRxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* In case of 9bits/No Parity transfer, pRxData buffer provided as input paramter
should be aligned on a u16 frontier, as data to be received from RDR will be
handled through a u16 cast. */
if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
{
if((((uint32_t)pRxData)&1U) != 0U)
{
return HAL_ERROR;
}
}
/* Process Locked */
__HAL_LOCK(husart);
husart->pRxBuffPtr = pRxData;
husart->RxXferSize = Size;
husart->RxXferCount = Size;
USART_MASK_COMPUTATION(husart);
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_RX;
/* Process Unlocked */
__HAL_UNLOCK(husart);
/* Enable the USART Parity Error and Data Register not empty Interrupts */
SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
/* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
/* Send dummy byte in order to generate the clock for the Slave to send the next data */
if(husart->Init.WordLength == USART_WORDLENGTH_9B)
{
husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x01FFU);
}
else
{
husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FFU);
}
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Full-Duplex Send and Receive an amount of data in interrupt mode.
* @param husart USART handle.
* @param pTxData pointer to TX data buffer.
* @param pRxData pointer to RX data buffer.
* @param Size amount of data to be sent (same amount to be received).
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* address of user data buffers containing data to be sent/received, should be aligned on a half word frontier (16 bits)
* (as sent/received data will be handled using u16 pointer cast). Depending on compilation chain,
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData and pRxData.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
{
if(husart->State == HAL_USART_STATE_READY)
{
if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* In case of 9bits/No Parity transfer, pTxData and pRxData buffers provided as input paramter
should be aligned on a u16 frontier, as data to be filled into TDR/retrieved from RDR will be
handled through a u16 cast. */
if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
{
if(((((uint32_t)pTxData)&1U) != 0U) || ((((uint32_t)pRxData)&1U) != 0U))
{
return HAL_ERROR;
}
}
/* Process Locked */
__HAL_LOCK(husart);
husart->pRxBuffPtr = pRxData;
husart->RxXferSize = Size;
husart->RxXferCount = Size;
husart->pTxBuffPtr = pTxData;
husart->TxXferSize = Size;
husart->TxXferCount = Size;
/* Computation of USART mask to apply to RDR register */
USART_MASK_COMPUTATION(husart);
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_TX_RX;
/* Process Unlocked */
__HAL_UNLOCK(husart);
/* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
/* Enable the USART Parity Error and USART Data Register not empty Interrupts */
SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
/* Enable the USART Transmit Data Register Empty Interrupt */
SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Send an amount of data in DMA mode.
* @param husart USART handle.
* @param pTxData pointer to data buffer.
* @param Size amount of data to be sent.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
* (as sent data will be handled by DMA from halfword frontier). Depending on compilation chain,
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
{
uint32_t *tmp=0U;
if(husart->State == HAL_USART_STATE_READY)
{
if((pTxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* In case of 9bits/No Parity transfer, pTxData buffer provided as input paramter
should be aligned on a u16 frontier, as data copy into TDR will be
handled by DMA from a u16 frontier. */
if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
{
if((((uint32_t)pTxData)&1U) != 0U)
{
return HAL_ERROR;
}
}
/* Process Locked */
__HAL_LOCK(husart);
husart->pTxBuffPtr = pTxData;
husart->TxXferSize = Size;
husart->TxXferCount = Size;
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_TX;
/* Set the USART DMA transfer complete callback */
husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
/* Set the USART DMA Half transfer complete callback */
husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
/* Set the DMA error callback */
husart->hdmatx->XferErrorCallback = USART_DMAError;
/* Enable the USART transmit DMA channel */
tmp = (uint32_t*)&pTxData;
HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
/* Clear the TC flag in the ICR register */
__HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
/* Process Unlocked */
__HAL_UNLOCK(husart);
/* Enable the DMA transfer for transmit request by setting the DMAT bit
in the USART CR3 register */
SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Receive an amount of data in DMA mode.
* @param husart USART handle.
* @param pRxData pointer to data buffer.
* @param Size amount of data to be received.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
* (as received data will be handled by DMA from halfword frontier). Depending on compilation chain,
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pRxData.
* @note The USART DMA transmit channel must be configured in order to generate the clock for the slave.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
{
uint32_t *tmp;
/* Check that a Rx process is not already ongoing */
if(husart->State == HAL_USART_STATE_READY)
{
if((pRxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* In case of 9bits/No Parity transfer, pRxData buffer provided as input paramter
should be aligned on a u16 frontier, as data copy from RDR will be
handled by DMA from a u16 frontier. */
if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
{
if((((uint32_t)pRxData)&1U) != 0U)
{
return HAL_ERROR;
}
}
/* Process Locked */
__HAL_LOCK(husart);
husart->pRxBuffPtr = pRxData;
husart->RxXferSize = Size;
husart->pTxBuffPtr = pRxData;
husart->TxXferSize = Size;
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_RX;
/* Set the USART DMA Rx transfer complete callback */
husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
/* Set the USART DMA Half transfer complete callback */
husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
/* Set the USART DMA Rx transfer error callback */
husart->hdmarx->XferErrorCallback = USART_DMAError;
/* Enable the USART receive DMA channel */
tmp = (uint32_t*)&pRxData;
HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size);
/* Enable the USART transmit DMA channel: the transmit channel is used in order
to generate in the non-blocking mode the clock to the slave device,
this mode isn't a simplex receive mode but a full-duplex receive mode */
/* Set the USART DMA Tx Complete and Error callback to Null */
husart->hdmatx->XferErrorCallback = NULL;
husart->hdmatx->XferHalfCpltCallback = NULL;
husart->hdmatx->XferCpltCallback = NULL;
HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
/* Process Unlocked */
__HAL_UNLOCK(husart);
/* Enable the USART Parity Error Interrupt */
SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
/* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
/* Enable the DMA transfer for the receiver request by setting the DMAR bit
in the USART CR3 register */
SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
/* Enable the DMA transfer for transmit request by setting the DMAT bit
in the USART CR3 register */
SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.
* @param husart USART handle.
* @param pTxData pointer to TX data buffer.
* @param pRxData pointer to RX data buffer.
* @param Size amount of data to be received/sent.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* address of user data buffers containing data to be sent/received, should be aligned on a half word frontier (16 bits)
* (as sent/received data will be handled by DMA from halfword frontier). Depending on compilation chain,
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData and pRxData.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
{
uint32_t *tmp;
if(husart->State == HAL_USART_STATE_READY)
{
if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* In case of 9bits/No Parity transfer, pTxData and pRxData buffers provided as input paramter
should be aligned on a u16 frontier, as data copy to/from TDR/RDR will be
handled by DMA from a u16 frontier. */
if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
{
if(((((uint32_t)pTxData)&1U) != 0U) || ((((uint32_t)pRxData)&1U) != 0U))
{
return HAL_ERROR;
}
}
/* Process Locked */
__HAL_LOCK(husart);
husart->pRxBuffPtr = pRxData;
husart->RxXferSize = Size;
husart->pTxBuffPtr = pTxData;
husart->TxXferSize = Size;
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_TX_RX;
/* Set the USART DMA Rx transfer complete callback */
husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
/* Set the USART DMA Half transfer complete callback */
husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
/* Set the USART DMA Tx transfer complete callback */
husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
/* Set the USART DMA Half transfer complete callback */
husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
/* Set the USART DMA Tx transfer error callback */
husart->hdmatx->XferErrorCallback = USART_DMAError;
/* Set the USART DMA Rx transfer error callback */
husart->hdmarx->XferErrorCallback = USART_DMAError;
/* Enable the USART receive DMA channel */
tmp = (uint32_t*)&pRxData;
HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size);
/* Enable the USART transmit DMA channel */
tmp = (uint32_t*)&pTxData;
HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
/* Process Unlocked */
__HAL_UNLOCK(husart);
/* Enable the USART Parity Error Interrupt */
SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
/* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
/* Clear the TC flag in the ICR register */
__HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
/* Enable the DMA transfer for the receiver request by setting the DMAR bit
in the USART CR3 register */
SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
/* Enable the DMA transfer for transmit request by setting the DMAT bit
in the USART CR3 register */
SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Pause the DMA Transfer.
* @param husart USART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)
{
/* Process Locked */
__HAL_LOCK(husart);
if( (husart->State == HAL_USART_STATE_BUSY_TX) &&
(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)))
{
/* Disable the USART DMA Tx request */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
}
else if( (husart->State == HAL_USART_STATE_BUSY_RX) ||
(husart->State == HAL_USART_STATE_BUSY_TX_RX) )
{
if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
{
/* Disable the USART DMA Tx request */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
}
if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
{
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
/* Disable the USART DMA Rx request */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
}
}
/* Process Unlocked */
__HAL_UNLOCK(husart);
return HAL_OK;
}
/**
* @brief Resume the DMA Transfer.
* @param husart USART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
{
/* Process Locked */
__HAL_LOCK(husart);
if(husart->State == HAL_USART_STATE_BUSY_TX)
{
/* Enable the USART DMA Tx request */
SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
}
else if( (husart->State == HAL_USART_STATE_BUSY_RX) ||
(husart->State == HAL_USART_STATE_BUSY_TX_RX) )
{
/* Clear the Overrun flag before resuming the Rx transfer*/
__HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF);
/* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
/* Enable the USART DMA Rx request before the DMA Tx request */
SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
/* Enable the USART DMA Tx request */
SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
}
/* Process Unlocked */
__HAL_UNLOCK(husart);
return HAL_OK;
}
/**
* @brief Stop the DMA Transfer.
* @param husart USART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
{
/* The Lock is not implemented on this API to allow the user application
to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback() /
HAL_USART_TxHalfCpltCallback() / HAL_USART_RxHalfCpltCallback ():
indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete interrupt is
generated if the DMA transfer interruption occurs at the middle or at the end of the stream
and the corresponding call back is executed.
*/
/* Disable the USART Tx/Rx DMA requests */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
/* Abort the USART DMA tx channel */
if(husart->hdmatx != NULL)
{
HAL_DMA_Abort(husart->hdmatx);
}
/* Abort the USART DMA rx channel */
if(husart->hdmarx != NULL)
{
HAL_DMA_Abort(husart->hdmarx);
}
USART_EndTransfer(husart);
husart->State = HAL_USART_STATE_READY;
return HAL_OK;
}
/**
* @brief Abort ongoing transfers (blocking mode).
* @param husart USART handle.
* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable USART Interrupts (Tx and Rx)
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart)
{
/* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
/* Disable the USART DMA Tx request if enabled */
if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
{
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
/* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */
if(husart->hdmatx != NULL)
{
/* Set the USART DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
husart->hdmatx->XferAbortCallback = NULL;
HAL_DMA_Abort(husart->hdmatx);
}
}
/* Disable the USART DMA Rx request if enabled */
if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
/* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */
if(husart->hdmarx != NULL)
{
/* Set the USART DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
husart->hdmarx->XferAbortCallback = NULL;
HAL_DMA_Abort(husart->hdmarx);
}
}
/* Reset Tx and Rx transfer counters */
husart->TxXferCount = 0U;
husart->RxXferCount = 0U;
/* Clear the Error flags in the ICR register */
__HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
/* Restore husart->State to Ready */
husart->State = HAL_USART_STATE_READY;
/* Reset Handle ErrorCode to No Error */
husart->ErrorCode = HAL_USART_ERROR_NONE;
return HAL_OK;
}
/**
* @brief Abort ongoing transfers (Interrupt mode).
* @param husart USART handle.
* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable USART Interrupts (Tx and Rx)
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
* - Set handle State to READY
* - At abort completion, call user abort complete callback
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart)
{
uint32_t abortcplt = 1U;
/* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
/* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised
before any call to DMA Abort functions */
/* DMA Tx Handle is valid */
if(husart->hdmatx != NULL)
{
/* Set DMA Abort Complete callback if USART DMA Tx request if enabled.
Otherwise, set it to NULL */
if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
{
husart->hdmatx->XferAbortCallback = USART_DMATxAbortCallback;
}
else
{
husart->hdmatx->XferAbortCallback = NULL;
}
}
/* DMA Rx Handle is valid */
if(husart->hdmarx != NULL)
{
/* Set DMA Abort Complete callback if USART DMA Rx request if enabled.
Otherwise, set it to NULL */
if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
{
husart->hdmarx->XferAbortCallback = USART_DMARxAbortCallback;
}
else
{
husart->hdmarx->XferAbortCallback = NULL;
}
}
/* Disable the USART DMA Tx request if enabled */
if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
{
/* Disable DMA Tx at USART level */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
/* Abort the USART DMA Tx channel : use non blocking DMA Abort API (callback) */
if(husart->hdmatx != NULL)
{
/* USART Tx DMA Abort callback has already been initialised :
will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
/* Abort DMA TX */
if(HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK)
{
husart->hdmatx->XferAbortCallback = NULL;
}
else
{
abortcplt = 0U;
}
}
}
/* Disable the USART DMA Rx request if enabled */
if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
/* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */
if(husart->hdmarx != NULL)
{
/* USART Rx DMA Abort callback has already been initialised :
will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
/* Abort DMA RX */
if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
{
husart->hdmarx->XferAbortCallback = NULL;
abortcplt = 1U;
}
else
{
abortcplt = 0U;
}
}
}
/* if no DMA abort complete callback execution is required => call user Abort Complete callback */
if (abortcplt == 1U)
{
/* Reset Tx and Rx transfer counters */
husart->TxXferCount = 0U;
husart->RxXferCount = 0U;
/* Reset errorCode */
husart->ErrorCode = HAL_USART_ERROR_NONE;
/* Clear the Error flags in the ICR register */
__HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
/* Restore husart->State to Ready */
husart->State = HAL_USART_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
HAL_USART_AbortCpltCallback(husart);
}
return HAL_OK;
}
/**
* @brief Handle USART interrupt request.
* @param husart USART handle.
* @retval None
*/
void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
{
uint32_t isrflags = READ_REG(husart->Instance->ISR);
uint32_t cr1its = READ_REG(husart->Instance->CR1);
uint32_t cr3its;
uint32_t errorflags;
/* If no error occurs */
errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
if (errorflags == RESET)
{
/* USART in mode Receiver ---------------------------------------------------*/
if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
{
if(husart->State == HAL_USART_STATE_BUSY_RX)
{
USART_Receive_IT(husart);
}
else
{
USART_TransmitReceive_IT(husart);
}
return;
}
}
/* If some errors occur */
cr3its = READ_REG(husart->Instance->CR3);
if( (errorflags != RESET)
&& ( ((cr3its & USART_CR3_EIE) != RESET)
|| ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) )
{
/* USART parity error interrupt occurred -------------------------------------*/
if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
{
__HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF);
husart->ErrorCode |= HAL_USART_ERROR_PE;
}
/* USART frame error interrupt occurred --------------------------------------*/
if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
{
__HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF);
husart->ErrorCode |= HAL_USART_ERROR_FE;
}
/* USART noise error interrupt occurred --------------------------------------*/
if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
{
__HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF);
husart->ErrorCode |= HAL_USART_ERROR_NE;
}
/* USART Over-Run interrupt occurred -----------------------------------------*/
if(((isrflags & USART_ISR_ORE) != RESET) &&
(((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
{
__HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);
husart->ErrorCode |= HAL_USART_ERROR_ORE;
}
/* Call USART Error Call back function if need be --------------------------*/
if(husart->ErrorCode != HAL_USART_ERROR_NONE)
{
/* USART in mode Receiver ---------------------------------------------------*/
if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
{
if(husart->State == HAL_USART_STATE_BUSY_RX)
{
USART_Receive_IT(husart);
}
else
{
USART_TransmitReceive_IT(husart);
}
}
/* If Overrun error occurs, or if any error occurs in DMA mode reception,
consider error as blocking */
if (((husart->ErrorCode & HAL_USART_ERROR_ORE) != RESET) ||
(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)))
{
/* Blocking error : transfer is aborted
Set the USART state ready to be able to start again the process,
Disable Interrupts, and disable DMA requests, if ongoing */
USART_EndTransfer(husart);
/* Disable the USART DMA Rx request if enabled */
if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR | USART_CR3_DMAR);
/* Abort the USART DMA Tx channel */
if(husart->hdmatx != NULL)
{
/* Set the USART Tx DMA Abort callback to NULL : no callback
executed at end of DMA abort procedure */
husart->hdmatx->XferAbortCallback = NULL;
/* Abort DMA TX */
HAL_DMA_Abort_IT(husart->hdmatx);
}
/* Abort the USART DMA Rx channel */
if(husart->hdmarx != NULL)
{
/* Set the USART Rx DMA Abort callback :
will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */
husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError;
/* Abort DMA RX */
if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
{
/* Call Directly husart->hdmarx->XferAbortCallback function in case of error */
husart->hdmarx->XferAbortCallback(husart->hdmarx);
}
}
else
{
/* Call user error callback */
HAL_USART_ErrorCallback(husart);
}
}
else
{
/* Call user error callback */
HAL_USART_ErrorCallback(husart);
}
}
else
{
/* Non Blocking error : transfer could go on.
Error is notified to user through user error callback */
HAL_USART_ErrorCallback(husart);
husart->ErrorCode = HAL_USART_ERROR_NONE;
}
}
return;
} /* End if some error occurs */
/* USART in mode Transmitter ------------------------------------------------*/
if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
{
if(husart->State == HAL_USART_STATE_BUSY_TX)
{
USART_Transmit_IT(husart);
}
else
{
USART_TransmitReceive_IT(husart);
}
return;
}
/* USART in mode Transmitter (transmission end) -----------------------------*/
if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
{
USART_EndTransmit_IT(husart);
return;
}
}
/**
* @brief Tx Transfer completed callback.
* @param husart USART handle.
* @retval None
*/
__weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(husart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_USART_TxCpltCallback can be implemented in the user file.
*/
}
/**
* @brief Tx Half Transfer completed callback.
* @param husart USART handle.
* @retval None
*/
__weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(husart);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_USART_TxHalfCpltCallback can be implemented in the user file.
*/
}
/**
* @brief Rx Transfer completed callback.
* @param husart USART handle.
* @retval None
*/
__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(husart);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_USART_RxCpltCallback can be implemented in the user file.
*/
}
/**
* @brief Rx Half Transfer completed callback.
* @param husart USART handle.
* @retval None
*/
__weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(husart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_USART_RxHalfCpltCallback can be implemented in the user file
*/
}
/**
* @brief Tx/Rx Transfers completed callback for the non-blocking process.
* @param husart USART handle.
* @retval None
*/
__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(husart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_USART_TxRxCpltCallback can be implemented in the user file
*/
}
/**
* @brief USART error callback.
* @param husart USART handle.
* @retval None
*/
__weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(husart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_USART_ErrorCallback can be implemented in the user file.
*/
}
/**
* @brief USART Abort Complete callback.
* @param husart USART handle.
* @retval None
*/
__weak void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(husart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_USART_AbortCpltCallback can be implemented in the user file.
*/
}
/**
* @}
*/
/** @defgroup USART_Exported_Functions_Group3 Peripheral State and Error functions
* @brief USART Peripheral State and Error functions
*
@verbatim
==============================================================================
##### Peripheral State and Error functions #####
==============================================================================
[..]
This subsection provides functions allowing to :
(+) Return the USART handle state
(+) Return the USART handle error code
@endverbatim
* @{
*/
/**
* @brief Return the USART handle state.
* @param husart pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART.
* @retval USART handle state
*/
HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)
{
return husart->State;
}
/**
* @brief Return the USART error code.
* @param husart pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART.
* @retval USART handle Error Code
*/
uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)
{
return husart->ErrorCode;
}
/**
* @}
*/
/**
* @}
*/
/** @defgroup USART_Private_Functions USART Private Functions
* @brief USART Private functions
*
@verbatim
[..]
This subsection provides a set of functions allowing to control the USART.
(+) USART_SetConfig() API is used to set the USART communication parameters.
(+) USART_CheckIdleState() APi ensures that TEACK and/or REACK bits are set after initialization
@endverbatim
* @{
*/
/**
* @brief End ongoing transfer on USART peripheral (following error detection or Transfer completion).
* @param husart USART handle.
* @retval None
*/
static void USART_EndTransfer(USART_HandleTypeDef *husart)
{
/* Disable TXEIE and TCIE interrupts */
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(husart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | USART_CR1_PEIE));
CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
/* At end of process, restore husart->State to Ready */
husart->State = HAL_USART_STATE_READY;
}
/**
* @brief DMA USART transmit process complete callback.
* @param hdma DMA handle.
* @retval None
*/
static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
/* DMA Normal mode */
if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
{
husart->TxXferCount = 0U;
if(husart->State == HAL_USART_STATE_BUSY_TX)
{
/* Disable the DMA transfer for transmit request by resetting the DMAT bit
in the USART CR3 register */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
/* Enable the USART Transmit Complete Interrupt */
__HAL_USART_ENABLE_IT(husart, USART_IT_TC);
}
}
/* DMA Circular mode */
else
{
if(husart->State == HAL_USART_STATE_BUSY_TX)
{
HAL_USART_TxCpltCallback(husart);
}
}
}
/**
* @brief DMA USART transmit process half complete callback.
* @param hdma DMA handle.
* @retval None
*/
static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
{
USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
HAL_USART_TxHalfCpltCallback(husart);
}
/**
* @brief DMA USART receive process complete callback.
* @param hdma DMA handle.
* @retval None
*/
static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
/* DMA Normal mode */
if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
{
husart->RxXferCount = 0U;
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
/* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit
in USART CR3 register */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
/* similarly, disable the DMA TX transfer that was started to provide the
clock to the slave device */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
if(husart->State == HAL_USART_STATE_BUSY_RX)
{
HAL_USART_RxCpltCallback(husart);
}
/* The USART state is HAL_USART_STATE_BUSY_TX_RX */
else
{
HAL_USART_TxRxCpltCallback(husart);
}
husart->State= HAL_USART_STATE_READY;
}
/* DMA circular mode */
else
{
if(husart->State == HAL_USART_STATE_BUSY_RX)
{
HAL_USART_RxCpltCallback(husart);
}
/* The USART state is HAL_USART_STATE_BUSY_TX_RX */
else
{
HAL_USART_TxRxCpltCallback(husart);
}
}
}
/**
* @brief DMA USART receive process half complete callback.
* @param hdma DMA handle.
* @retval None
*/
static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
{
USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
HAL_USART_RxHalfCpltCallback(husart);
}
/**
* @brief DMA USART communication error callback.
* @param hdma DMA handle.
* @retval None
*/
static void USART_DMAError(DMA_HandleTypeDef *hdma)
{
USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
husart->RxXferCount = 0U;
husart->TxXferCount = 0U;
USART_EndTransfer(husart);
husart->ErrorCode |= HAL_USART_ERROR_DMA;
husart->State= HAL_USART_STATE_READY;
HAL_USART_ErrorCallback(husart);
}
/**
* @brief DMA USART communication abort callback, when initiated by HAL services on Error
* (To be called at end of DMA Abort procedure following error occurrence).
* @param hdma DMA handle.
* @retval None
*/
static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
husart->RxXferCount = 0U;
husart->TxXferCount = 0U;
HAL_USART_ErrorCallback(husart);
}
/**
* @brief DMA USART Tx communication abort callback, when initiated by user
* (To be called at end of DMA Tx Abort procedure following user abort request).
* @note When this callback is executed, User Abort complete call back is called only if no
* Abort still ongoing for Rx DMA Handle.
* @param hdma DMA handle.
* @retval None
*/
static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
{
USART_HandleTypeDef* husart = (USART_HandleTypeDef* )(hdma->Parent);
husart->hdmatx->XferAbortCallback = NULL;
/* Check if an Abort process is still ongoing */
if(husart->hdmarx != NULL)
{
if(husart->hdmarx->XferAbortCallback != NULL)
{
return;
}
}
/* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
husart->TxXferCount = 0U;
husart->RxXferCount = 0U;
/* Reset errorCode */
husart->ErrorCode = HAL_USART_ERROR_NONE;
/* Clear the Error flags in the ICR register */
__HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
/* Restore husart->State to Ready */
husart->State = HAL_USART_STATE_READY;
/* Call user Abort complete callback */
HAL_USART_AbortCpltCallback(husart);
}
/**
* @brief DMA USART Rx communication abort callback, when initiated by user
* (To be called at end of DMA Rx Abort procedure following user abort request).
* @note When this callback is executed, User Abort complete call back is called only if no
* Abort still ongoing for Tx DMA Handle.
* @param hdma DMA handle.
* @retval None
*/
static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
{
USART_HandleTypeDef* husart = (USART_HandleTypeDef* )(hdma->Parent);
husart->hdmarx->XferAbortCallback = NULL;
/* Check if an Abort process is still ongoing */
if(husart->hdmatx != NULL)
{
if(husart->hdmatx->XferAbortCallback != NULL)
{
return;
}
}
/* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
husart->TxXferCount = 0U;
husart->RxXferCount = 0U;
/* Reset errorCode */
husart->ErrorCode = HAL_USART_ERROR_NONE;
/* Clear the Error flags in the ICR register */
__HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
/* Restore husart->State to Ready */
husart->State = HAL_USART_STATE_READY;
/* Call user Abort complete callback */
HAL_USART_AbortCpltCallback(husart);
}
/**
* @brief Handle USART Communication Timeout.
* @param husart USART handle.
* @param Flag Specifies the USART flag to check.
* @param Status the Flag status (SET or RESET).
* @param Tickstart Tick start value
* @param Timeout timeout duration.
* @retval HAL status
*/
static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
{
/* Wait until flag is set */
while((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status)
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
husart->State= HAL_USART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(husart);
return HAL_TIMEOUT;
}
}
}
return HAL_OK;
}
/**
* @brief Configure the USART peripheral.
* @param husart USART handle.
* @retval HAL status
*/
static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)
{
uint32_t tmpreg = 0x0U;
USART_ClockSourceTypeDef clocksource = USART_CLOCKSOURCE_UNDEFINED;
HAL_StatusTypeDef ret = HAL_OK;
uint16_t brrtemp = 0x0000U;
uint16_t usartdiv = 0x0000U;
/* Check the parameters */
assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));
assert_param(IS_USART_PHASE(husart->Init.CLKPhase));
assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit));
assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate));
assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength));
assert_param(IS_USART_STOPBITS(husart->Init.StopBits));
assert_param(IS_USART_PARITY(husart->Init.Parity));
assert_param(IS_USART_MODE(husart->Init.Mode));
/*-------------------------- USART CR1 Configuration -----------------------*/
/* Clear M, PCE, PS, TE and RE bits and configure
* the USART Word Length, Parity and Mode:
* set the M bits according to husart->Init.WordLength value
* set PCE and PS bits according to husart->Init.Parity value
* set TE and RE bits according to husart->Init.Mode value
* force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */
tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8;
MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
/*---------------------------- USART CR2 Configuration ---------------------*/
/* Clear and configure the USART Clock, CPOL, CPHA, LBCL and STOP bits:
* set CPOL bit according to husart->Init.CLKPolarity value
* set CPHA bit according to husart->Init.CLKPhase value
* set LBCL bit according to husart->Init.CLKLastBit value
* set STOP[13:12] bits according to husart->Init.StopBits value */
tmpreg = (uint32_t)(USART_CLOCK_ENABLE);
tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase);
tmpreg |= ((uint32_t)husart->Init.CLKLastBit | (uint32_t)husart->Init.StopBits);
MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg);
/*-------------------------- USART CR3 Configuration -----------------------*/
/* no CR3 register configuration */
/*-------------------------- USART BRR Configuration -----------------------*/
/* BRR is filled-up according to OVER8 bit setting which is forced to 1 */
USART_GETCLOCKSOURCE(husart, clocksource);
switch (clocksource)
{
case USART_CLOCKSOURCE_PCLK1:
usartdiv = (uint16_t)(((2*HAL_RCC_GetPCLK1Freq()) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate);
break;
case USART_CLOCKSOURCE_HSI:
usartdiv = (uint16_t)(((2*HSI_VALUE) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate);
break;
case USART_CLOCKSOURCE_SYSCLK:
usartdiv = (uint16_t)(((2*HAL_RCC_GetSysClockFreq()) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate);
break;
case USART_CLOCKSOURCE_LSE:
usartdiv = (uint16_t)(((2*LSE_VALUE) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate);
break;
case USART_CLOCKSOURCE_UNDEFINED:
default:
ret = HAL_ERROR;
break;
}
brrtemp = usartdiv & 0xFFF0U;
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
husart->Instance->BRR = brrtemp;
return ret;
}
/**
* @brief Check the USART Idle State.
* @param husart USART handle.
* @retval HAL status
*/
static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart)
{
#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
uint32_t tickstart = 0U;
#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
/* Initialize the USART ErrorCode */
husart->ErrorCode = HAL_USART_ERROR_NONE;
#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
/* Init tickstart for timeout managment*/
tickstart = HAL_GetTick();
/* TEACK and REACK bits in ISR are checked only when available (not available on all F0 devices).
Bits are defined for some specific devices, and are available only for UART instances supporting WakeUp from Stop Mode feature.
*/
if (IS_UART_WAKEUP_FROMSTOP_INSTANCE(husart->Instance))
{
/* Check if the Transmitter is enabled */
if((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
{
/* Wait until TEACK flag is set */
if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
{
/* Timeout occurred */
return HAL_TIMEOUT;
}
}
/* Check if the Receiver is enabled */
if((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
{
/* Wait until REACK flag is set */
if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
{
/* Timeout occurred */
return HAL_TIMEOUT;
}
}
}
#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
/* Initialize the USART state*/
husart->State= HAL_USART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(husart);
return HAL_OK;
}
/**
* @brief Simplex send an amount of data in non-blocking mode.
* @note Function called under interruption only, once
* interruptions have been enabled by HAL_USART_Transmit_IT().
* @note The USART errors are not managed to avoid the overrun error.
* @param husart USART handle.
* @retval HAL status
*/
static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)
{
uint16_t* tmp=0U;
/* Check that a Tx process is ongoing */
if(husart->State == HAL_USART_STATE_BUSY_TX)
{
if(husart->TxXferCount == 0U)
{
/* Disable the USART Transmit data register empty interrupt */
__HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
/* Enable the USART Transmit Complete Interrupt */
__HAL_USART_ENABLE_IT(husart, USART_IT_TC);
return HAL_OK;
}
else
{
if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
{
tmp = (uint16_t*) husart->pTxBuffPtr;
husart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
husart->pTxBuffPtr += 2U;
}
else
{
husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFFU);
}
husart->TxXferCount--;
return HAL_OK;
}
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Wraps up transmission in non-blocking mode.
* @param husart Pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval HAL status
*/
static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart)
{
/* Disable the USART Transmit Complete Interrupt */
__HAL_USART_DISABLE_IT(husart, USART_IT_TC);
/* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
/* Tx process is ended, restore husart->State to Ready */
husart->State = HAL_USART_STATE_READY;
HAL_USART_TxCpltCallback(husart);
return HAL_OK;
}
/**
* @brief Simplex receive an amount of data in non-blocking mode.
* @note Function called under interruption only, once
* interruptions have been enabled by HAL_USART_Receive_IT().
* @param husart USART handle
* @retval HAL status
*/
static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
{
uint16_t* tmp=0U;
uint16_t uhMask = husart->Mask;
if(husart->State == HAL_USART_STATE_BUSY_RX)
{
if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
{
tmp = (uint16_t*) husart->pRxBuffPtr;
*tmp = (uint16_t)(husart->Instance->RDR & uhMask);
husart->pRxBuffPtr += 2U;
}
else
{
*husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
}
/* Send dummy byte in order to generate the clock for the Slave to Send the next data */
husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FFU);
if(--husart->RxXferCount == 0U)
{
/* Disable the USART Parity Error Interrupt and RXNE interrupt*/
CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
/* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
/* Rx process is completed, restore husart->State to Ready */
husart->State = HAL_USART_STATE_READY;
HAL_USART_RxCpltCallback(husart);
return HAL_OK;
}
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
* @note Function called under interruption only, once
* interruptions have been enabled by HAL_USART_TransmitReceive_IT().
* @param husart USART handle.
* @retval HAL status
*/
static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
{
uint16_t* tmp=0U;
uint16_t uhMask = husart->Mask;
if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
{
if(husart->TxXferCount != 0x00U)
{
if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET)
{
if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
{
tmp = (uint16_t*) husart->pTxBuffPtr;
husart->Instance->TDR = (uint16_t)(*tmp & uhMask);
husart->pTxBuffPtr += 2U;
}
else
{
husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)uhMask);
}
husart->TxXferCount--;
/* Check the latest data transmitted */
if(husart->TxXferCount == 0U)
{
__HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
}
}
}
if(husart->RxXferCount != 0x00U)
{
if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET)
{
if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
{
tmp = (uint16_t*) husart->pRxBuffPtr;
*tmp = (uint16_t)(husart->Instance->RDR & uhMask);
husart->pRxBuffPtr += 2U;
}
else
{
*husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
}
husart->RxXferCount--;
}
}
/* Check the latest data received */
if(husart->RxXferCount == 0U)
{
/* Disable the USART Parity Error Interrupt and RXNE interrupt*/
CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
/* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
/* Rx process is completed, restore husart->State to Ready */
husart->State = HAL_USART_STATE_READY;
HAL_USART_TxRxCpltCallback(husart);
return HAL_OK;
}
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @}
*/
#endif /* HAL_USART_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|