seniordesign-hardware Changeset - 61860df41747

Changeset - 61860df41747

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kripperger@CL-SEC241-09.cedarville.edu - 13 years ago 2012-11-07 20:30:59
kripperger@CL-SEC241-09.cedarville.edu

minor

3 files changed with 41 insertions and 7 deletions:

master/master.brd

master/master.sch

slave/eagle.epf

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master/master.brd

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@@ @@ -4418,28 +4418,24 @@ Please make sure your boards conform to @@
 <via x="33.3375" y="43.33875" extent="1-16" drill="0.254"/>
 <via x="35.2425" y="43.33875" extent="1-16" drill="0.254"/>
 <via x="37.1475" y="43.33875" extent="1-16" drill="0.254"/>
 <via x="39.0525" y="43.33875" extent="1-16" drill="0.254"/>
 <wire x1="33.34" y1="44.43" x2="33.34" y2="43.5" width="0.4064" layer="1"/>
 <wire x1="33.34" y1="43.5" x2="33.3375" y2="43.33875" width="0.4064" layer="1"/>
 <wire x1="35.24" y1="44.43" x2="35.24" y2="43.5" width="0.4064" layer="1"/>
 <wire x1="35.24" y1="43.5" x2="35.2425" y2="43.33875" width="0.4064" layer="1"/>
 <wire x1="37.15" y1="44.43" x2="37.15" y2="43.65875" width="0.4064" layer="1"/>
 <wire x1="37.15" y1="43.65875" x2="37.1475" y2="43.33875" width="0.4064" layer="1"/>
 <wire x1="39.05" y1="44.43" x2="39.05" y2="43.5" width="0.4064" layer="1"/>
 <wire x1="39.05" y1="43.5" x2="39.0525" y2="43.33875" width="0.4064" layer="1"/>
 <wire x1="43.815" y1="51.55" x2="43.7" y2="51.55" width="0.4064" layer="1"/>
 <wire x1="43.7" y1="51.55" x2="43.18" y2="52.07" width="0.4064" layer="1"/>
 <wire x1="43.18" y1="52.07" x2="40.64" y2="52.07" width="0.4064" layer="1"/>
 <wire x1="40.64" y1="52.07" x2="39.37" y2="50.8" width="0.4064" layer="1"/>
 <via x="43.815" y="38.735" extent="1-16" drill="0.254"/>
 <via x="44.45" y="38.1" extent="1-16" drill="0.254"/>
 <via x="48.73625" y="33.655" extent="1-16" drill="0.254"/>
 <via x="48.73625" y="32.385" extent="1-16" drill="0.254"/>
 <via x="51.7525" y="34.925" extent="1-16" drill="0.254"/>
 <wire x1="51.65" y1="36.195" x2="51.65" y2="35.0275" width="0.6096" layer="1"/>
 <wire x1="51.65" y1="35.0275" x2="51.7525" y2="34.925" width="0.6096" layer="1"/>
 <wire x1="51.65" y1="36.195" x2="51.65" y2="38.05" width="0.6096" layer="1"/>
 <wire x1="51.65" y1="38.05" x2="51.7" y2="38.1" width="0.6096" layer="1"/>
 <polygon width="0.4064" layer="1">
 <vertex x="45.085" y="29.21"/>
 <vertex x="50.4825" y="29.21"/>
@@ @@ -5164,26 +5160,24 @@ Please make sure your boards conform to @@
 <signal name="VBATRAW" class="1">
 <contactref element="Q6" pad="3"/>
 <contactref element="BATT" pad="1"/>
 <wire x1="24.36" y1="48.5575" x2="24.36" y2="47.05" width="0.8128" layer="1"/>
 <wire x1="24.36" y1="47.05" x2="22.86" y2="45.55" width="0.8128" layer="1"/>
 </signal>
 <signal name="VBAT">
 <contactref element="Q6" pad="2"/>
 <contactref element="5V_SWITCHING" pad="8"/>
 <contactref element="C12" pad="1"/>
 <contactref element="5V_SWITCHING" pad="7"/>
 <contactref element="BUZZ" pad="1"/>
 <wire x1="41.85" y1="33.655" x2="40.005" y2="33.655" width="0.4064" layer="1"/>
 <wire x1="40.005" y1="33.655" x2="39.37" y2="33.02" width="0.4064" layer="1"/>
 <contactref element="R29" pad="2"/>
 <contactref element="Q7" pad="2"/>
 <via x="23.8125" y="41.91" extent="1-16" drill="0.254"/>
 <via x="25.0825" y="41.91" extent="1-16" drill="0.254"/>
 <polygon width="0.4064" layer="1">
 <vertex x="23.495" y="43.4975"/>
 <vertex x="25.4" y="43.4975"/>
 <vertex x="25.4" y="41.5925"/>
 <vertex x="23.495" y="41.5925"/>
 </polygon>
 <via x="25.0825" y="43.18" extent="1-16" drill="0.254"/>
 <wire x1="25.4" y1="41.91" x2="33.3375" y2="41.91" width="0.8128" layer="1"/>

master/master.sch

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@@ @@ -18207,25 +18207,24 @@ are free for leds</text> @@
 <wire x1="341.376" y1="83.312" x2="343.916" y2="83.312" width="0.1524" layer="94"/>
 <text x="344.678" y="82.55" size="1.778" layer="94">Radio Output</text>
 <wire x1="203.2" y1="144.78" x2="121.92" y2="144.78" width="0.3048" layer="94"/>
 <wire x1="203.2" y1="68.58" x2="121.92" y2="68.58" width="0.3048" layer="94"/>
 <text x="15.24" y="152.4" size="1.778" layer="91">Use LQG15HS27NJ02D</text>
 <text x="50.8" y="198.12" size="1.778" layer="91">Hold ATMEGA in reset to use this port</text>
 <text x="157.48" y="76.2" size="1.778" layer="91">50M maxfreq</text>
 <text x="309.88" y="180.34" size="1.778" layer="91">Calc value of this res</text>
 <text x="330.2" y="233.68" size="1.778" layer="91">Jumper over RST and GND for gps comms</text>
 <text x="71.12" y="200.66" size="1.778" layer="91">3.3V TOLERANT!</text>
 <text x="0" y="220.98" size="1.778" layer="91">Place by P1</text>
 <text x="68.58" y="7.62" size="1.778" layer="91">FB/Inductor trace must be short, low L (plane)</text>
 <text x="302.26" y="175.26" size="5.08" layer="91" ratio="19" rot="R90">Review</text>
 <text x="353.06" y="208.28" size="1.778" layer="91">Optional</text>
 <text x="281.94" y="35.56" size="1.778" layer="91">Max drive:
 mA / channel
 mA total
 mA * 8 LEDs = 160mA
 Maybe use bigger R's</text>
 <text x="154.94" y="198.12" size="1.778" layer="91">peak power 5ms after EN high</text>
 <text x="50.8" y="119.38" size="5.08" layer="94" font="vector">SPI</text>
 <text x="10.16" y="81.28" size="1.778" layer="91">CLOSE TO CARD</text>
 <text x="55.88" y="86.36" size="1.778" layer="91">spare 4.7k</text>

slave/eagle.epf

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@@ @@ -8,20 +8,61 @@ Desktop="Desktop" @@
 [Globals]
 AutoSaveProject=1
 UsedLibrary="C:/Program Files (x86)/EAGLE-6.3.0/lbr/crystal.lbr"
 UsedLibrary="C:/Users/kripperger/Documents/eagle/seniordesign-hardware/lbr/adafruit.lbr"
 UsedLibrary="C:/Users/kripperger/Documents/eagle/seniordesign-hardware/lbr/dp_devices.lbr"
 UsedLibrary="C:/Users/kripperger/Documents/eagle/seniordesign-hardware/lbr/SeniorDesign.lbr"
 UsedLibrary="C:/Users/kripperger/Documents/eagle/seniordesign-hardware/lbr/SLAT-CON-JST-ZH.lbr"
 UsedLibrary="C:/Users/kripperger/Documents/eagle/seniordesign-hardware/lbr/SLAT-Connector SMD.lbr"
 UsedLibrary="C:/Users/kripperger/Documents/eagle/seniordesign-hardware/lbr/SLAT-Connector TH.lbr"
 UsedLibrary="C:/Users/kripperger/Documents/eagle/seniordesign-hardware/lbr/SparkFun.lbr"
 [Win_1]
 Type="Schematic Editor"
 Loc="332 293 931 692"
 State=0
 Number=2
 File="C:/Users/kripperger/Documents/eagle/seniordesign-hardware/master/master.sch"
 View="-9.45104 -5.82337 451.185 266.173"
 WireWidths=" 0 0.3048 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 6.4516 0.4064 0.1524"
 PadDiameters=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 6.4516 0"
 PadDrills=" 0.5 0.6 0.7 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 2 2.2 2.8 3.2 0.8"
 ViaDiameters=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 6.4516 0"
 ViaDrills=" 0.5 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 2 2.2 2.8 3.2 0.6"
 HoleDrills=" 0.5 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 2 2.2 2.8 3.2 0.6"
 TextSizes=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.9304 2.1844 2.54 3.81 5.08 6.4516 1.778"
 PolygonSpacings=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 5.08 6.4516 1.27"
 PolygonIsolates=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 6.4516 0"
 MiterRadiuss=" 0.254 0.3175 0.635 1.27 2.54 1 2 2.5 5 7.5 10 0"
 SmdSizes=" 0.3048 0.1524 0.4064 0.2032 0.6096 0.3048 0.8128 0.4064 1.016 0.508 1.27 0.6604 1.4224 0.7112 1.6764 0.8128 1.778 0.9144 1.9304 0.9652 2.1844 1.0668 2.54 1.27 3.81 1.9304 5.08 2.54 6.4516 3.2512 1.27 0.635"
 WireBend=0
 WireBendSet=31
 WireCap=1
 MiterStyle=0
 PadShape=0
 ViaShape=0
 PolygonPour=0
 PolygonRank=0
 PolygonThermals=1
 PolygonOrphans=0
 TextRatio=8
 PinDirection=3
 PinFunction=0
 PinLength=2
 PinVisible=3
 SwapLevel=0
 ArcDirection=0
 AddLevel=2
 PadsSameType=0
 Layer=91
 Sheet=1
 [Win_2]
 Type="Control Panel"
 Loc="466 200 1065 599"
 State=2
 Number=0
 [Desktop]
 Screen="2560 1024"
 Window="Win_1"
 Window="Win_2"

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