therm Changeset - 3e00cf5fc57d · protofusion repositories

Changeset - 3e00cf5fc57d

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Ethan Zonca - 10 years ago 2014-07-11 17:44:35
ez@ethanzonca.com

Trying to make clocks work

3 files changed with 8 insertions and 7 deletions:

main.c

system_stm32l1xx.h

rename

system_stm32l1xx_4meg_extxtal.c

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main.c

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@@ @@ -6,58 +6,59 @@ @@
 #define LED_STAT  GPIOA,GPIO_Pin_15
 static __IO uint32_t TimingDelay;
 void init_gpio();
 void init_spi();
 int main(void)
+{
     // Init clocks
     SystemInit();
     RCC_ClocksTypeDef RCC_Clocks;
     // SysTick end of count event each 1ms
     RCC_GetClocksFreq(&RCC_Clocks);
     SysTick_Config(RCC_Clocks.HCLK_Frequency / 1000);
     GPIO_ResetBits(LED_STAT);
     Delay(100);
     init_gpio();
     init_spi();
     //ssd1306_Init();
     //SSD1303_DrawPoint(3,3,1);
     //SSD1303_DrawPoint(5,5,0);
     ssd1306_Init();
     ssd1306_DrawPoint(3,3,1);
     ssd1306_DrawPoint(5,5,0);
     GPIO_SetBits(LED_POWER);
     Delay(500);
     GPIO_ResetBits(LED_POWER);
     while(1)
+    {
         ssd1306_DrawPoint(5,5,0);
         GPIO_SetBits(LED_POWER);
         Delay(150);
         GPIO_ResetBits(LED_POWER);
         Delay(150);
+    }
+}
 /**
   * @brief  Inserts a delay time.
   * @param  nTime: specifies the delay time length, in 1 ms.
   * @retval None
   */
 void Delay(__IO uint32_t nTime)
+{
   TimingDelay = nTime;
   while(TimingDelay != 0);
+}
 /**
   * @brief  Decrements the TimingDelay variable.
   * @param  None
   * @retval None
   */
 void TimingDelay_Decrement(void)

system_stm32l1xx.h

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file renamed from libraries/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h to system_stm32l1xx.h

system_stm32l1xx_4meg_extxtal.c

➞

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@@ file renamed from system_stm32l1xx.c to system_stm32l1xx_4meg_extxtal.c @@
 /**
   ******************************************************************************
   * @file    system_stm32l1xx.c
   * @author  MCD Application Team
   * @version V1.2.0
-  * @date    10-July-2014
+  * @date    11-July-2014
   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
   *          This file contains the system clock configuration for STM32L1xx Ultra
   *          Low power devices, and is generated by the clock configuration
   *          tool  STM32L1xx_Clock_Configuration_V1.2.0.xls
+  *
   * 1.  This file provides two functions and one global variable to be called from
   *     user application:
   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
   *                      and Divider factors, AHB/APBx prescalers and Flash settings),
   *                      depending on the configuration made in the clock xls tool.
   *                      This function is called at startup just after reset and
   *                      before branch to main program. This call is made inside
   *                      the "startup_stm32l1xx_xx.s" file.
+  *
   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
   *                                  by the user application to setup the SysTick
   *                                  timer or configure other parameters.
+  *
   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
   *                                 be called whenever the core clock is changed
   *                                 during program execution.
+  *
   * 2. After each device reset the MSI (2.1 MHz Range) is used as system clock source.
   *    Then SystemInit() function is called, in "startup_stm32l1xx_xx.s" file, to
@@ @@ -34,53 +34,53 @@ @@
   *    function will do nothing and MSI still used as system clock source. User can
   *    add some code to deal with this issue inside the SetSysClock() function.
+  *
   * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
   *    in "stm32l1xx.h" file. When HSE is used as system clock source, directly or
   *    through PLL, and you are using different crystal you have to adapt the HSE
   *    value to your own configuration.
+  *
   * 5. This file configures the system clock as follows:
   *=============================================================================
   *                         System Clock Configuration
   *=============================================================================
   *        System Clock source          | PLL(HSE)
   *-----------------------------------------------------------------------------
   *        SYSCLK                       | 32000000 Hz
   *-----------------------------------------------------------------------------
   *        HCLK                         | 32000000 Hz
   *-----------------------------------------------------------------------------
   *        AHB Prescaler                | 1
   *-----------------------------------------------------------------------------
   *        APB1 Prescaler               | 1
   *-----------------------------------------------------------------------------
   *        APB2 Prescaler               | 1
   *-----------------------------------------------------------------------------
-  *        HSE Frequency                | 8000000 Hz
+  *        HSE Frequency                | 4000000 Hz
   *-----------------------------------------------------------------------------
   *        PLL DIV                      | 3
   *-----------------------------------------------------------------------------
-  *        PLL MUL                      | 12
+  *        PLL MUL                      | 24
   *-----------------------------------------------------------------------------
   *        VDD                          | 3.3 V
   *-----------------------------------------------------------------------------
   *        Vcore                        | 1.8 V (Range 1)
   *-----------------------------------------------------------------------------
   *        Flash Latency                | 1 WS
   *-----------------------------------------------------------------------------
   *        Require 48MHz for USB clock  | Enabled
   *-----------------------------------------------------------------------------
   *=============================================================================
   * @attention
+  *
   * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
   * You may not use this file except in compliance with the License.
   * You may obtain a copy of the License at:
+  *
   *        http://www.st.com/software_license_agreement_liberty_v2
+  *
   * Unless required by applicable law or agreed to in writing, software
   * distributed under the License is distributed on an "AS IS" BASIS,
   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
   * See the License for the specific language governing permissions and
@@ @@ -332,49 +332,49 @@ static void SetSysClock(void) @@
     /* Power enable */
     RCC->APB1ENR |= RCC_APB1ENR_PWREN;
     /* Select the Voltage Range 1 (1.8 V) */
     PWR->CR = PWR_CR_VOS_0;
     /* Wait Until the Voltage Regulator is ready */
     while((PWR->CSR & PWR_CSR_VOSF) != RESET)
+    {
+    }
     /* HCLK = SYSCLK /1*/
     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
     /* PCLK2 = HCLK /1*/
     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
     /* PCLK1 = HCLK /1*/
     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
     /*  PLL configuration */
     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL |
                                         RCC_CFGR_PLLDIV));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL12 | RCC_CFGR_PLLDIV3);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL24 | RCC_CFGR_PLLDIV3);
     /* Enable PLL */
     RCC->CR |= RCC_CR_PLLON;
     /* Wait till PLL is ready */
     while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
     /* Select PLL as system clock source */
     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
     /* Wait till PLL is used as system clock source */
     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
+    {
+    }
+  }
   else
+  {
     /* If HSE fails to start-up, the application will have wrong clock
        configuration. User can add here some code to deal with this error */
+  }
+}

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