therm Changeset - 3e00cf5fc57d · protofusion repositories

Changeset - 3e00cf5fc57d

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Ethan Zonca - 10 years ago 2014-07-11 17:44:35
ez@ethanzonca.com

Trying to make clocks work

3 files changed with 8 insertions and 7 deletions:

main.c

system_stm32l1xx.h

rename

system_stm32l1xx_4meg_extxtal.c

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main.c

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@@ @@ -24,22 +24,23 @@ int main(void) @@
     GPIO_ResetBits(LED_STAT);
     Delay(100);
     init_gpio();
     init_spi();
     //ssd1306_Init();
     //SSD1303_DrawPoint(3,3,1);
     //SSD1303_DrawPoint(5,5,0);
     ssd1306_Init();
     ssd1306_DrawPoint(3,3,1);
     ssd1306_DrawPoint(5,5,0);
     GPIO_SetBits(LED_POWER);
     Delay(500);
     GPIO_ResetBits(LED_POWER);
     while(1)
+    {
         ssd1306_DrawPoint(5,5,0);
         GPIO_SetBits(LED_POWER);
         Delay(150);
         GPIO_ResetBits(LED_POWER);
         Delay(150);
+    }
+}

system_stm32l1xx.h

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file renamed from libraries/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h to system_stm32l1xx.h

system_stm32l1xx_4meg_extxtal.c

➞

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@@ file renamed from system_stm32l1xx.c to system_stm32l1xx_4meg_extxtal.c @@
 /**
   ******************************************************************************
   * @file    system_stm32l1xx.c
   * @author  MCD Application Team
   * @version V1.2.0
-  * @date    10-July-2014
+  * @date    11-July-2014
   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
   *          This file contains the system clock configuration for STM32L1xx Ultra
   *          Low power devices, and is generated by the clock configuration
   *          tool  STM32L1xx_Clock_Configuration_V1.2.0.xls
+  *
   * 1.  This file provides two functions and one global variable to be called from
@@ @@ -52,17 +52,17 @@ @@
   *        AHB Prescaler                | 1
   *-----------------------------------------------------------------------------
   *        APB1 Prescaler               | 1
   *-----------------------------------------------------------------------------
   *        APB2 Prescaler               | 1
   *-----------------------------------------------------------------------------
-  *        HSE Frequency                | 8000000 Hz
+  *        HSE Frequency                | 4000000 Hz
   *-----------------------------------------------------------------------------
   *        PLL DIV                      | 3
   *-----------------------------------------------------------------------------
-  *        PLL MUL                      | 12
+  *        PLL MUL                      | 24
   *-----------------------------------------------------------------------------
   *        VDD                          | 3.3 V
   *-----------------------------------------------------------------------------
   *        Vcore                        | 1.8 V (Range 1)
   *-----------------------------------------------------------------------------
   *        Flash Latency                | 1 WS
@@ @@ -350,13 +350,13 @@ static void SetSysClock(void) @@
     /* PCLK1 = HCLK /1*/
     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
     /*  PLL configuration */
     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL |
                                         RCC_CFGR_PLLDIV));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL12 | RCC_CFGR_PLLDIV3);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL24 | RCC_CFGR_PLLDIV3);
     /* Enable PLL */
     RCC->CR |= RCC_CR_PLLON;
     /* Wait till PLL is ready */
     while((RCC->CR & RCC_CR_PLLRDY) == 0)

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