therm Changeset - 4ae23ddf6c3e · protofusion repositories

Changeset - 4ae23ddf6c3e

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cortex-f0

0 0 47

Ethan Zonca - 11 years ago 2014-11-08 01:11:53
ez@ethanzonca.com

Add F0 CMSIS

47 files changed with 32941 insertions and 0 deletions:

libraries/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h

5555

libraries/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h

104

libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f030.s

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libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f031.s

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libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f042.s

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libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f051.s

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libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f072.s

325

libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f091.s

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libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f0xx.s

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libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f0xx_ld.s

294

libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f030.s

272

libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f031.s

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libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f042.s

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libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f051.s

285

libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f072.s

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libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f091.s

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libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f0xx.s

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libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f0xx_ld.s

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libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f030.s

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libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f031.s

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libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f042.s

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libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f051.s

328

libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f072.s

337

libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f0xx.s

325

libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f030.s

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libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f031.s

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libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f042.s

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libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f051.s

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libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f072.s

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libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f091.s

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libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f0xx.s

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libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f0xx_ld.s

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libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/system_stm32f0xx.c

358

libraries/CMSIS/Include/arm_common_tables.h

libraries/CMSIS/Include/arm_const_structs.h

libraries/CMSIS/Include/arm_math.h

7306

libraries/CMSIS/Include/core_cm0.h

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libraries/CMSIS/Include/core_cm0plus.h

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libraries/CMSIS/Include/core_cm3.h

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libraries/CMSIS/Include/core_cm4.h

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libraries/CMSIS/Include/core_cm4_simd.h

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libraries/CMSIS/Include/core_cmFunc.h

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libraries/CMSIS/Include/core_cmInstr.h

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libraries/CMSIS/Include/core_sc000.h

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libraries/CMSIS/Include/core_sc300.h

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libraries/CMSIS/README.txt

libraries/CMSIS/RTOS/cmsis_os.h

783

0 comments (0 inline, 0 general)

libraries/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h

➞

Show inline comments

@@ new file 100644 @@
 /**
   ******************************************************************************
   * @file    stm32f0xx.h
   * @author  MCD Application Team
   * @version V1.4.0
   * @date    24-July-2014
   * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
   *          This file contains all the peripheral register's definitions, bits
   *          definitions and memory mapping for STM32F0xx devices.
+  *
   *          The file is the unique include file that the application programmer
   *          is using in the C source code, usually in main.c. This file contains:
   *           - Configuration section that allows to select:
   *              - The device used in the target application
   *              - To use or not the peripheral’s drivers in application code(i.e.
   *                code will be based on direct access to peripheral’s registers
   *                rather than drivers API), this option is controlled by
   *                "#define USE_STDPERIPH_DRIVER"
   *              - To change few application-specific parameters such as the HSE
   *                crystal frequency
   *           - Data structures and the address mapping for all peripherals
   *           - Peripheral's registers declarations and bits definition
   *           - Macros to access peripheral’s registers hardware
+  *
   ******************************************************************************
   * @attention
+  *
   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
   * You may not use this file except in compliance with the License.
   * You may obtain a copy of the License at:
+  *
   *        http://www.st.com/software_license_agreement_liberty_v2
+  *
   * Unless required by applicable law or agreed to in writing, software
   * distributed under the License is distributed on an "AS IS" BASIS,
   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
   * See the License for the specific language governing permissions and
   * limitations under the License.
+  *
   ******************************************************************************
   */
 /** @addtogroup CMSIS
   * @{
   */
 /** @addtogroup stm32f0xx
   * @{
   */
 #ifndef __STM32F0XX_H
 #define __STM32F0XX_H
 #ifdef __cplusplus
  extern "C" {
 #endif
 /** @addtogroup Library_configuration_section
   * @{
   */
 /* Uncomment the line below according to the target STM32F0 device used in your
    application
   */
 #if !defined (STM32F030) && !defined (STM32F031) && !defined (STM32F051) && !defined (STM32F072) && !defined (STM32F042) && !defined (STM32F091)
   /* #define STM32F030 */
   /* #define STM32F031 */
   /* #define STM32F051 */
   /* #define STM32F072 */
   /* #define STM32F042 */
   /* #define STM32F091 */
 #endif
 /*  Tip: To avoid modifying this file each time you need to switch between these
         devices, you can define the device in your toolchain compiler preprocessor.
   */
 /* Old STM32F0XX definition, maintained for legacy purpose */
 #if defined(STM32F0XX) || defined(STM32F0XX_MD)
   #define STM32F051
 #endif /* STM32F0XX */
 /* Old STM32F0XX_LD definition, maintained for legacy purpose */
 #ifdef STM32F0XX_LD
   #define     STM32F031
 #endif /* STM32F0XX_LD */
 /* Old STM32F0XX_HD definition, maintained for legacy purpose */
 #ifdef STM32F0XX_HD
    #define   STM32F072
 #endif /* STM32F0XX_HD */
 /* Old STM32F030X6/X8 definition, maintained for legacy purpose */
 #if defined (STM32F030X8) || defined (STM32F030X6)
   #define    STM32F030
 #endif /* STM32F030X8 or  STM32F030X6 */
 #if !defined (STM32F030) && !defined (STM32F031) && !defined (STM32F051) && !defined (STM32F072) && !defined (STM32F042) && !defined (STM32F091)
  #error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
 #endif
 #if !defined  USE_STDPERIPH_DRIVER
 /**
  * @brief Comment the line below if you will not use the peripherals drivers.
    In this case, these drivers will not be included and the application code will
    be based on direct access to peripherals registers
    */
   /*#define USE_STDPERIPH_DRIVER*/
 #endif /* USE_STDPERIPH_DRIVER */
 /**
  * @brief In the following line adjust the value of External High Speed oscillator (HSE)
    used in your application
    Tip: To avoid modifying this file each time you need to use different HSE, you
         can define the HSE value in your toolchain compiler preprocessor.
   */
 #if !defined  (HSE_VALUE)
 #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/
 #endif /* HSE_VALUE */
 /**
  * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
    Timeout value
    */
 #if !defined  (HSE_STARTUP_TIMEOUT)
 #define HSE_STARTUP_TIMEOUT   ((uint16_t)0x5000) /*!< Time out for HSE start up */
 #endif /* HSE_STARTUP_TIMEOUT */
 /**
  * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
    Timeout value
    */
 #if !defined  (HSI_STARTUP_TIMEOUT)
 #define HSI_STARTUP_TIMEOUT   ((uint16_t)0x5000) /*!< Time out for HSI start up */
 #endif /* HSI_STARTUP_TIMEOUT */
 #if !defined  (HSI_VALUE)
 #define HSI_VALUE  ((uint32_t)8000000) /*!< Value of the Internal High Speed oscillator in Hz.
                                              The real value may vary depending on the variations
                                              in voltage and temperature.  */
 #endif /* HSI_VALUE */
 #if !defined  (HSI14_VALUE)
 #define HSI14_VALUE ((uint32_t)14000000) /*!< Value of the Internal High Speed oscillator for ADC in Hz.
                                              The real value may vary depending on the variations
                                              in voltage and temperature.  */
 #endif /* HSI14_VALUE */
 #if !defined  (HSI48_VALUE)
 #define HSI48_VALUE ((uint32_t)48000000) /*!< Value of the Internal High Speed oscillator for USB in Hz.
                                              The real value may vary depending on the variations
                                              in voltage and temperature.  */
 #endif /* HSI48_VALUE */
 #if !defined  (LSI_VALUE)
 #define LSI_VALUE  ((uint32_t)40000)    /*!< Value of the Internal Low Speed oscillator in Hz
                                              The real value may vary depending on the variations
                                              in voltage and temperature.  */
 #endif /* LSI_VALUE */
 #if !defined  (LSE_VALUE)
 #define LSE_VALUE  ((uint32_t)32768)    /*!< Value of the External Low Speed oscillator in Hz */
 #endif /* LSE_VALUE */
 /**
  * @brief STM32F0xx Standard Peripheral Library version number V1.4.0
    */
 #define __STM32F0XX_STDPERIPH_VERSION_MAIN   (0x01) /*!< [31:24] main version */
 #define __STM32F0XX_STDPERIPH_VERSION_SUB1   (0x04) /*!< [23:16] sub1 version */
 #define __STM32F0XX_STDPERIPH_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
 #define __STM32F0XX_STDPERIPH_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
 #define __STM32F0XX_STDPERIPH_VERSION        ((__STM32F0XX_STDPERIPH_VERSION_MAIN << 24)\
                                              |(__STM32F0XX_STDPERIPH_VERSION_SUB1 << 16)\
                                              |(__STM32F0XX_STDPERIPH_VERSION_SUB2 << 8)\
                                              |(__STM32F0XX_STDPERIPH_VERSION_RC))
 /**
   * @}
   */
 /** @addtogroup Configuration_section_for_CMSIS
   * @{
   */
 /**
  * @brief STM32F0xx Interrupt Number Definition, according to the selected device
  *        in @ref Library_configuration_section
  */
 #define __CM0_REV                 0 /*!< Core Revision r0p0                            */
 #define __MPU_PRESENT             0 /*!< STM32F0xx do not provide MPU                  */
 #define __NVIC_PRIO_BITS          2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
 #define __Vendor_SysTickConfig    0 /*!< Set to 1 if different SysTick Config is used  */
 /*!< Interrupt Number Definition */
 typedef enum IRQn
+{
 /******  Cortex-M0 Processor Exceptions Numbers ******************************************************/
   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
   HardFault_IRQn              = -13,    /*!< 3 Cortex-M0 Hard Fault Interrupt                        */
   SVC_IRQn                    = -5,     /*!< 11 Cortex-M0 SV Call Interrupt                          */
   PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0 Pend SV Interrupt                          */
   SysTick_IRQn                = -1,     /*!< 15 Cortex-M0 System Tick Interrupt                      */
 #if defined (STM32F051)
 /******  STM32F051  specific Interrupt Numbers *************************************/
   WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
   PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detect Interrupt                  */
   RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                         */
   FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                         */
   RCC_IRQn                    = 4,      /*!< RCC Interrupt                                           */
   EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                            */
   EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                            */
   EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                            */
   TS_IRQn                     = 8,      /*!< Touch sense controller Interrupt                        */
   DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                */
   DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                 */
   DMA1_Channel4_5_IRQn        = 11,     /*!< DMA1 Channel 4 and Channel 5 Interrupts                 */
   ADC1_COMP_IRQn              = 12,     /*!< ADC1, COMP1 and COMP2 Interrupts                        */
   TIM1_BRK_UP_TRG_COM_IRQn    = 13,     /*!< TIM1 Break, Update, Trigger and Commutation Interrupts  */
   TIM1_CC_IRQn                = 14,     /*!< TIM1 Capture Compare Interrupt                          */
   TIM2_IRQn                   = 15,     /*!< TIM2 Interrupt                                          */
   TIM3_IRQn                   = 16,     /*!< TIM3 Interrupt                                          */
   TIM6_DAC_IRQn               = 17,     /*!< TIM6 and DAC Interrupts                                 */
   TIM14_IRQn                  = 19,     /*!< TIM14 Interrupt                                         */
   TIM15_IRQn                  = 20,     /*!< TIM15 Interrupt                                         */
   TIM16_IRQn                  = 21,     /*!< TIM16 Interrupt                                         */
   TIM17_IRQn                  = 22,     /*!< TIM17 Interrupt                                         */
   I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                          */
   I2C2_IRQn                   = 24,     /*!< I2C2 Interrupt                                          */
   SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                          */
   SPI2_IRQn                   = 26,     /*!< SPI2 Interrupt                                          */
   USART1_IRQn                 = 27,     /*!< USART1 Interrupt                                        */
   USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                        */
   CEC_IRQn                    = 30      /*!< CEC Interrupt                                           */
 #elif defined (STM32F031)
 /******  STM32F031 specific Interrupt Numbers *************************************/
   WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
   PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detect Interrupt                  */
   RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                         */
   FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                         */
   RCC_IRQn                    = 4,      /*!< RCC Interrupt                                           */
   EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                            */
   EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                            */
   EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                            */
   DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                */
   DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                 */
   DMA1_Channel4_5_IRQn        = 11,     /*!< DMA1 Channel 4 and Channel 5 Interrupts                 */
   ADC1_IRQn                   = 12,     /*!< ADC1 Interrupt                                          */
   TIM1_BRK_UP_TRG_COM_IRQn    = 13,     /*!< TIM1 Break, Update, Trigger and Commutation Interrupts  */
   TIM1_CC_IRQn                = 14,     /*!< TIM1 Capture Compare Interrupt                          */
   TIM2_IRQn                   = 15,     /*!< TIM2 Interrupt                                          */
   TIM3_IRQn                   = 16,     /*!< TIM3 Interrupt                                          */
   TIM14_IRQn                  = 19,     /*!< TIM14 Interrupt                                         */
   TIM16_IRQn                  = 21,     /*!< TIM16 Interrupt                                         */
   TIM17_IRQn                  = 22,     /*!< TIM17 Interrupt                                         */
   I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                          */
   SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                          */
   USART1_IRQn                 = 27      /*!< USART1 Interrupt                                        */
 #elif defined (STM32F030)
 /******  STM32F030 specific Interrupt Numbers *************************************/
   WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
   RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                         */
   FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                         */
   RCC_IRQn                    = 4,      /*!< RCC Interrupt                                           */
   EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                            */
   EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                            */
   EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                            */
   DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                */
   DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                 */
   DMA1_Channel4_5_IRQn        = 11,     /*!< DMA1 Channel 4 and Channel 5 Interrupts                 */
   ADC1_IRQn                   = 12,     /*!< ADC1 Interrupt                                          */
   TIM1_BRK_UP_TRG_COM_IRQn    = 13,     /*!< TIM1 Break, Update, Trigger and Commutation Interrupts  */
   TIM1_CC_IRQn                = 14,     /*!< TIM1 Capture Compare Interrupt                          */
   TIM3_IRQn                   = 16,     /*!< TIM3 Interrupt                                          */
   TIM14_IRQn                  = 19,     /*!< TIM14 Interrupt                                         */
   TIM15_IRQn                  = 20,     /*!< TIM15 Interrupt                                         */
   TIM16_IRQn                  = 21,     /*!< TIM16 Interrupt                                         */
   TIM17_IRQn                  = 22,     /*!< TIM17 Interrupt                                         */
   I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                          */
   I2C2_IRQn                   = 24,     /*!< I2C2 Interrupt                                          */
   SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                          */
   SPI2_IRQn                   = 26,     /*!< SPI2 Interrupt                                          */
   USART1_IRQn                 = 27,     /*!< USART1 Interrupt                                        */
   USART2_IRQn                 = 28      /*!< USART2 Interrupt                                        */
 #elif defined (STM32F072)
   WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                     */
   PVD_VDDIO2_IRQn             = 1,      /*!< PVD and VDDIO2 supply comparator through EXTI Line detect Interrupt */
   RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                               */
   FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                               */
   RCC_CRS_IRQn                = 4,      /*!< RCC and CRS Interrupts                                        */
   EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                                  */
   EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                                  */
   EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                                  */
   TSC_IRQn                    = 8,      /*!< TSC Interrupt                                                 */
   DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                      */
   DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                       */
   DMA1_Channel4_5_6_7_IRQn    = 11,     /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
   ADC1_COMP_IRQn              = 12,     /*!< ADC1, COMP1 and COMP2 Interrupts                              */
   TIM1_BRK_UP_TRG_COM_IRQn    = 13,     /*!< TIM1 Break, Update, Trigger and Commutation Interrupts        */
   TIM1_CC_IRQn                = 14,     /*!< TIM1 Capture Compare Interrupt                                */
   TIM2_IRQn                   = 15,     /*!< TIM2 Interrupt                                                */
   TIM3_IRQn                   = 16,     /*!< TIM3 Interrupt                                                */
   TIM6_DAC_IRQn               = 17,     /*!< TIM6 and DAC Interrupts                                       */
   TIM7_IRQn                   = 18,     /*!< TIM7 Interrupts                                               */
   TIM14_IRQn                  = 19,     /*!< TIM14 Interrupt                                               */
   TIM15_IRQn                  = 20,     /*!< TIM15 Interrupt                                               */
   TIM16_IRQn                  = 21,     /*!< TIM16 Interrupt                                               */
   TIM17_IRQn                  = 22,     /*!< TIM17 Interrupt                                               */
   I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                                */
   I2C2_IRQn                   = 24,     /*!< I2C2 Interrupt                                                */
   SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                                */
   SPI2_IRQn                   = 26,     /*!< SPI2 Interrupt                                                */
   USART1_IRQn                 = 27,     /*!< USART1 Interrupt                                              */
   USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                              */
   USART3_4_IRQn               = 29,     /*!< USART3 and USART4 Interrupts                                  */
   CEC_CAN_IRQn                = 30,     /*!< CEC and CAN Interrupts                                        */
   USB_IRQn                    = 31      /*!< USB Low Priority global Interrupt                             */
 #elif defined (STM32F042)
   WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                     */
   PVD_VDDIO2_IRQn             = 1,      /*!< PVD and VDDIO2 supply comparator through EXTI Line detect Interrupt */
   RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                               */
   FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                               */
   RCC_CRS_IRQn                = 4,      /*!< RCC and CRS Interrupts                                        */
   EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                                  */
   EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                                  */
   EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                                  */
   TSC_IRQn                    = 8,      /*!< TSC Interrupt                                                 */
   DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                      */
   DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                       */
   DMA1_Channel4_5_IRQn        = 11,     /*!< DMA1 Channel 4, Channel 5 Interrupts                          */
   ADC1_IRQn                   = 12,     /*!< ADC1 Interrupts                                               */
   TIM1_BRK_UP_TRG_COM_IRQn    = 13,     /*!< TIM1 Break, Update, Trigger and Commutation Interrupts        */
   TIM1_CC_IRQn                = 14,     /*!< TIM1 Capture Compare Interrupt                                */
   TIM2_IRQn                   = 15,     /*!< TIM2 Interrupt                                                */
   TIM3_IRQn                   = 16,     /*!< TIM3 Interrupt                                                */
   TIM14_IRQn                  = 19,     /*!< TIM14 Interrupt                                               */
   TIM16_IRQn                  = 21,     /*!< TIM16 Interrupt                                               */
   TIM17_IRQn                  = 22,     /*!< TIM17 Interrupt                                               */
   I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                                */
   SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                                */
   SPI2_IRQn                   = 26,     /*!< SPI2 Interrupt                                                */
   USART1_IRQn                 = 27,     /*!< USART1 Interrupt                                              */
   USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                              */
   CEC_CAN_IRQn                = 30,     /*!< CEC and CAN Interrupts                                        */
   USB_IRQn                    = 31      /*!< USB Low Priority global Interrupt                             */
 #elif defined (STM32F091)
   WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                       */
   PVD_VDDIO2_IRQn             = 1,      /*!< PVD & VDDIO2 Interrupts through EXTI Lines 16 and 31            */
   RTC_IRQn                    = 2,      /*!< RTC Interrupt through EXTI Lines 17, 19 and 20                  */
   FLASH_IRQn                  = 3,      /*!< FLASH global Interrupt                                          */
   RCC_CRS_IRQn                = 4,      /*!< RCC & CRS Global Interrupts                                     */
   EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                                    */
   EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                                    */
   EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                                    */
   TSC_IRQn                    = 8,      /*!< Touch Sensing Controller Interrupts                             */
   DMA1_Ch1_IRQn               = 9,      /*!< DMA1 Channel 1 Interrupt                                        */
   DMA1_Ch2_3_DMA2_Ch1_2_IRQn  = 10,     /*!< DMA1 Channel 2 and 3 & DMA2 Channel 1 and 2 Interrupts          */
   DMA1_Ch4_7_DMA2_Ch3_5_IRQn  = 11,     /*!< DMA1 Channel 4 to 7 & DMA2 Channel 3 to 5 Interrupts            */
   ADC1_COMP_IRQn               = 12,     /*!< ADC, COMP1 and COMP2 Interrupts (EXTI Lines 21 and 22)          */
   TIM1_BRK_UP_TRG_COM_IRQn    = 13,     /*!< TIM1 Break, Update, Trigger and Commutation Interrupts          */
   TIM1_CC_IRQn                = 14,     /*!< TIM1 Capture Compare Interrupt                                  */
   TIM2_IRQn                   = 15,     /*!< TIM2 global Interrupt                                           */
   TIM3_IRQn                   = 16,     /*!< TIM3 global Interrupt                                           */
   TIM6_DAC_IRQn               = 17,     /*!< TIM6 global and DAC channel underrun error Interrupts           */
   TIM7_IRQn                   = 18,     /*!< TIM7 global Interrupt                                           */
   TIM14_IRQn                  = 19,     /*!< TIM14 global Interrupt                                          */
   TIM15_IRQn                  = 20,     /*!< TIM15 global Interrupt                                          */
   TIM16_IRQn                  = 21,     /*!< TIM16 global Interrupt                                          */
   TIM17_IRQn                  = 22,     /*!< TIM17 global Interrupt                                          */
   I2C1_IRQn                   = 23,     /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup)      */
   I2C2_IRQn                   = 24,     /*!< I2C2 Event Interrupt & EXTI Line24 Interrupt (I2C2 wakeup)      */
   SPI1_IRQn                   = 25,     /*!< SPI1 global Interrupt                                           */
   SPI2_IRQn                   = 26,     /*!< SPI2 global Interrupt                                           */
   USART1_IRQn                 = 27,     /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
   USART2_IRQn                 = 28,     /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
   USART3_8_IRQn               = 29,     /*!< USART3 to USART8 global Interrupts                              */
   CEC_CAN_IRQn                = 30      /*!< CEC and CAN global Interrupts & EXTI Line27 Interrupt           */
 #endif /* STM32F051 */
 } IRQn_Type;
 /**
   * @}
   */
 #include "core_cm0.h"
 #include "system_stm32f0xx.h"
 #include <stdint.h>
 /** @addtogroup Exported_types
   * @{
   */
 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
 /** @addtogroup Peripheral_registers_structures
   * @{
   */
 /**
   * @brief Analog to Digital Converter
   */
 typedef struct
+{
   __IO uint32_t ISR;          /*!< ADC Interrupt and Status register,                          Address offset:0x00 */
   __IO uint32_t IER;          /*!< ADC Interrupt Enable register,                              Address offset:0x04 */
   __IO uint32_t CR;           /*!< ADC Control register,                                       Address offset:0x08 */
   __IO uint32_t CFGR1;        /*!< ADC Configuration register 1,                               Address offset:0x0C */
   __IO uint32_t CFGR2;        /*!< ADC Configuration register 2,                               Address offset:0x10 */
   __IO uint32_t SMPR;         /*!< ADC Sampling time register,                                 Address offset:0x14 */
   uint32_t   RESERVED1;       /*!< Reserved,                                                                  0x18 */
   uint32_t   RESERVED2;       /*!< Reserved,                                                                  0x1C */
   __IO uint32_t TR;           /*!< ADC watchdog threshold register,                            Address offset:0x20 */
   uint32_t   RESERVED3;       /*!< Reserved,                                                                  0x24 */
   __IO uint32_t CHSELR;       /*!< ADC channel selection register,                             Address offset:0x28 */
   uint32_t   RESERVED4[5];    /*!< Reserved,                                                                  0x2C */
    __IO uint32_t DR;          /*!< ADC data register,                                          Address offset:0x40 */
 } ADC_TypeDef;
 typedef struct
+{
   __IO uint32_t CCR;
 } ADC_Common_TypeDef;
 /**
   * @brief Controller Area Network TxMailBox
   */
 typedef struct
+{
   __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
   __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
   __IO uint32_t TDLR; /*!< CAN mailbox data low register */
   __IO uint32_t TDHR; /*!< CAN mailbox data high register */
 } CAN_TxMailBox_TypeDef;
 /**
   * @brief Controller Area Network FIFOMailBox
   */
 typedef struct
+{
   __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
   __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
   __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
   __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
 } CAN_FIFOMailBox_TypeDef;
 /**
   * @brief Controller Area Network FilterRegister
   */
 typedef struct
+{
   __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
   __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
 } CAN_FilterRegister_TypeDef;
 /**
   * @brief Controller Area Network
   */
 typedef struct
+{
   __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
   __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
   __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
   __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
   __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
   __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
   __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
   __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
   uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
   CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
   CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
   uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
   __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
   __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
   uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
   __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
   uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
   __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
   uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
   __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
   uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */
   CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
 } CAN_TypeDef;
 /**
   * @brief HDMI-CEC
   */
 typedef struct
+{
   __IO uint32_t CR;           /*!< CEC control register,                                       Address offset:0x00 */
   __IO uint32_t CFGR;         /*!< CEC configuration register,                                 Address offset:0x04 */
   __IO uint32_t TXDR;         /*!< CEC Tx data register ,                                      Address offset:0x08 */
   __IO uint32_t RXDR;         /*!< CEC Rx Data Register,                                       Address offset:0x0C */
   __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register,                          Address offset:0x10 */
   __IO uint32_t IER;          /*!< CEC interrupt enable register,                              Address offset:0x14 */
 }CEC_TypeDef;
 /**
   * @brief Comparator
   */
 typedef struct
+{
   __IO uint32_t CSR;     /*!< COMP comparator control and status register, Address offset: 0x1C */
 } COMP_TypeDef;
 /**
   * @brief CRC calculation unit
   */
 typedef struct
+{
   __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
   __IO uint8_t  IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
   uint8_t       RESERVED0;   /*!< Reserved,                                                    0x05 */
   uint16_t      RESERVED1;   /*!< Reserved,                                                    0x06 */
   __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
   uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */
   __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
   __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
 } CRC_TypeDef;
 /**
   * @brief Clock Recovery System
   */
 typedef struct
+{
 __IO uint32_t CR;     /*!< CRS ccontrol register,              Address offset: 0x00 */
 __IO uint32_t CFGR;   /*!< CRS configuration register,         Address offset: 0x04 */
 __IO uint32_t ISR;    /*!< CRS interrupt and status register,  Address offset: 0x08 */
 __IO uint32_t ICR;    /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
 } CRS_TypeDef;
 /**
   * @brief Digital to Analog Converter
   */
 typedef struct
+{
   __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
   __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
   __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
   __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
   __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
   __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
   __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
   __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
   __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
   __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
   __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
   __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
   __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
   __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
 } DAC_TypeDef;
 /**
   * @brief Debug MCU
   */
 typedef struct
+{
   __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
   __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
   __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
   __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
 }DBGMCU_TypeDef;
 /**
   * @brief DMA Controller
   */
 typedef struct
+{
   __IO uint32_t CCR;          /*!< DMA channel x configuration register                                           */
   __IO uint32_t CNDTR;        /*!< DMA channel x number of data register                                          */
   __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register                                      */
   __IO uint32_t CMAR;         /*!< DMA channel x memory address register                                          */
 } DMA_Channel_TypeDef;
 typedef struct
+{
   __IO uint32_t ISR;          /*!< DMA interrupt status register,                            Address offset: 0x00 */
   __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,                        Address offset: 0x04 */
   uint32_t      RESERVED0[40];/*!< Reserved as declared by channel typedef                         0x08 - 0xA4*/
   __IO uint32_t RMPCR;        /*!< Remap control register,                                      Address offset: 0xA8 */
 }DMA_TypeDef;
 /**
   * @brief External Interrupt/Event Controller
   */
 typedef struct
+{
   __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                             Address offset: 0x00 */
   __IO uint32_t EMR;          /*!<EXTI Event mask register,                                 Address offset: 0x04 */
   __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,                  Address offset: 0x08 */
   __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,                  Address offset: 0x0C */
   __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,                   Address offset: 0x10 */
   __IO uint32_t PR;           /*!<EXTI Pending register,                                    Address offset: 0x14 */
 }EXTI_TypeDef;
 /**
   * @brief FLASH Registers
   */
 typedef struct
+{
   __IO uint32_t ACR;          /*!<FLASH access control register,                 Address offset: 0x00 */
   __IO uint32_t KEYR;         /*!<FLASH key register,                            Address offset: 0x04 */
   __IO uint32_t OPTKEYR;      /*!<FLASH OPT key register,                        Address offset: 0x08 */
   __IO uint32_t SR;           /*!<FLASH status register,                         Address offset: 0x0C */
   __IO uint32_t CR;           /*!<FLASH control register,                        Address offset: 0x10 */
   __IO uint32_t AR;           /*!<FLASH address register,                        Address offset: 0x14 */
   __IO uint32_t RESERVED;     /*!< Reserved,                                                     0x18 */
   __IO uint32_t OBR;          /*!<FLASH option bytes register,                   Address offset: 0x1C */
   __IO uint32_t WRPR;         /*!<FLASH option bytes register,                   Address offset: 0x20 */
 } FLASH_TypeDef;
 /**
   * @brief Option Bytes Registers
   */
 typedef struct
+{
   __IO uint16_t RDP;          /*!< FLASH option byte Read protection,             Address offset: 0x00 */
   __IO uint16_t USER;         /*!< FLASH option byte user options,                Address offset: 0x02 */
   __IO uint16_t DATA0;        /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
   __IO uint16_t DATA1;        /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
   __IO uint16_t WRP0;         /*!< FLASH option byte write protection 0,          Address offset: 0x08 */
   __IO uint16_t WRP1;         /*!< FLASH option byte write protection 1,          Address offset: 0x0A */
   __IO uint16_t WRP2;         /*!< FLASH option byte write protection 2,          Address offset: 0x0C */
   __IO uint16_t WRP3;         /*!< FLASH option byte write protection 3,          Address offset: 0x0E */
 } OB_TypeDef;
 /**
   * @brief General Purpose IO
   */
 typedef struct
+{
   __IO uint32_t MODER;        /*!< GPIO port mode register,                                  Address offset: 0x00 */
   __IO uint16_t OTYPER;       /*!< GPIO port output type register,                           Address offset: 0x04 */
   uint16_t RESERVED0;         /*!< Reserved,                                                                 0x06 */
   __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,                          Address offset: 0x08 */
   __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,                     Address offset: 0x0C */
   __IO uint16_t IDR;          /*!< GPIO port input data register,                            Address offset: 0x10 */
   uint16_t RESERVED1;         /*!< Reserved,                                                                 0x12 */
   __IO uint16_t ODR;          /*!< GPIO port output data register,                           Address offset: 0x14 */
   uint16_t RESERVED2;         /*!< Reserved,                                                                 0x16 */
   __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,                     Address offset: 0x18 */
   __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,                    Address offset: 0x1C */
   __IO uint32_t AFR[2];       /*!< GPIO alternate function low register,                Address offset: 0x20-0x24 */
   __IO uint16_t BRR;          /*!< GPIO bit reset register,                                  Address offset: 0x28 */
   uint16_t RESERVED3;         /*!< Reserved,                                                                 0x2A */
 }GPIO_TypeDef;
 /**
   * @brief SysTem Configuration
   */
 typedef struct
+{
   __IO uint32_t CFGR1;          /*!< SYSCFG configuration register 1,                        Address offset: 0x00 */
        uint32_t RESERVED;       /*!< Reserved,                                                               0x04 */
   __IO uint32_t EXTICR[4];      /*!< SYSCFG external interrupt configuration register,  Address offset: 0x14-0x08 */
   __IO uint32_t CFGR2;          /*!< SYSCFG configuration register 2,                        Address offset: 0x18 */
        uint32_t RESERVED1[25];  /*!< Reserved + COMP,							                                           0x1C */
   __IO uint32_t IT_LINE_SR[32]; /*!< SYSCFG configuration IT_LINE register,                  Address offset: 0x80 */
 }SYSCFG_TypeDef;
 /**
   * @brief Inter-integrated Circuit Interface
   */
 typedef struct
+{
   __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
   __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
   __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
   __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
   __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
   __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
   __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
   __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
   __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
   __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
   __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
 }I2C_TypeDef;
 /**
   * @brief Independent WATCHDOG
   */
 typedef struct
+{
   __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
   __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
   __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
   __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
   __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
 } IWDG_TypeDef;
 /**
   * @brief Power Control
   */
 typedef struct
+{
   __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
   __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
 } PWR_TypeDef;
 /**
   * @brief Reset and Clock Control
   */
 typedef struct
+{
   __IO uint32_t CR;         /*!< RCC clock control register,                                  Address offset: 0x00 */
   __IO uint32_t CFGR;       /*!< RCC clock configuration register,                            Address offset: 0x04 */
   __IO uint32_t CIR;        /*!< RCC clock interrupt register,                                Address offset: 0x08 */
   __IO uint32_t APB2RSTR;   /*!< RCC APB2 peripheral reset register,                          Address offset: 0x0C */
   __IO uint32_t APB1RSTR;   /*!< RCC APB1 peripheral reset register,                          Address offset: 0x10 */
   __IO uint32_t AHBENR;     /*!< RCC AHB peripheral clock register,                           Address offset: 0x14 */
   __IO uint32_t APB2ENR;    /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x18 */
   __IO uint32_t APB1ENR;    /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x1C */
   __IO uint32_t BDCR;       /*!< RCC Backup domain control register,                          Address offset: 0x20 */
   __IO uint32_t CSR;        /*!< RCC clock control & status register,                         Address offset: 0x24 */
   __IO uint32_t AHBRSTR;    /*!< RCC AHB peripheral reset register,                           Address offset: 0x28 */
   __IO uint32_t CFGR2;      /*!< RCC clock configuration register 2,                          Address offset: 0x2C */
   __IO uint32_t CFGR3;      /*!< RCC clock configuration register 3,                          Address offset: 0x30 */
   __IO uint32_t CR2;        /*!< RCC clock control register 2,                                Address offset: 0x34 */
 } RCC_TypeDef;
 /**
   * @brief Real-Time Clock
   */
 typedef struct
+{
   __IO uint32_t TR;         /*!< RTC time register,                                        Address offset: 0x00 */
   __IO uint32_t DR;         /*!< RTC date register,                                        Address offset: 0x04 */
   __IO uint32_t CR;         /*!< RTC control register,                                     Address offset: 0x08 */
   __IO uint32_t ISR;        /*!< RTC initialization and status register,                   Address offset: 0x0C */
   __IO uint32_t PRER;       /*!< RTC prescaler register,                                   Address offset: 0x10 */
   __IO uint32_t WUTR;       /*!< RTC wakeup timer register,(only for STM32F072 devices)    Address offset: 0x14 */
        uint32_t RESERVED1;  /*!< Reserved,                                                 Address offset: 0x18 */
   __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                     Address offset: 0x1C */
        uint32_t RESERVED2;  /*!< Reserved,                                                 Address offset: 0x20 */
   __IO uint32_t WPR;        /*!< RTC write protection register,                            Address offset: 0x24 */
   __IO uint32_t SSR;        /*!< RTC sub second register,                                  Address offset: 0x28 */
   __IO uint32_t SHIFTR;     /*!< RTC shift control register,                               Address offset: 0x2C */
   __IO uint32_t TSTR;       /*!< RTC time stamp time register,                             Address offset: 0x30 */
   __IO uint32_t TSDR;       /*!< RTC time stamp date register,                             Address offset: 0x34 */
   __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
   __IO uint32_t CALR;       /*!< RTC calibration register,                                 Address offset: 0x3C */
   __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
   __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                          Address offset: 0x44 */
        uint32_t RESERVED3;  /*!< Reserved,                                                 Address offset: 0x48 */
        uint32_t RESERVED4;  /*!< Reserved,                                                 Address offset: 0x4C */
   __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                    Address offset: 0x50 */
   __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                    Address offset: 0x54 */
   __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                    Address offset: 0x58 */
   __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                    Address offset: 0x5C */
   __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                    Address offset: 0x60 */
 } RTC_TypeDef;
 /* Old register name definition maintained for legacy purpose */
 #define CAL   CALR
 /**
   * @brief Serial Peripheral Interface
   */
 typedef struct
+{
   __IO uint16_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
   uint16_t  RESERVED0;    /*!< Reserved, 0x02                                                            */
   __IO uint16_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
   uint16_t  RESERVED1;    /*!< Reserved, 0x06                                                            */
   __IO uint16_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
   uint16_t  RESERVED2;    /*!< Reserved, 0x0A                                                            */
   __IO uint16_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
   uint16_t  RESERVED3;    /*!< Reserved, 0x0E                                                            */
   __IO uint16_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
   uint16_t  RESERVED4;    /*!< Reserved, 0x12                                                            */
   __IO uint16_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
   uint16_t  RESERVED5;    /*!< Reserved, 0x16                                                            */
   __IO uint16_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */
   uint16_t  RESERVED6;    /*!< Reserved, 0x1A                                                            */
   __IO uint16_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
   uint16_t  RESERVED7;    /*!< Reserved, 0x1E                                                            */
   __IO uint16_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
   uint16_t  RESERVED8;    /*!< Reserved, 0x22                                                            */
 } SPI_TypeDef;
 /**
   * @brief TIM
   */
 typedef struct
+{
   __IO uint16_t CR1;             /*!< TIM control register 1,                      Address offset: 0x00 */
   uint16_t      RESERVED0;       /*!< Reserved,                                                    0x02 */
   __IO uint16_t CR2;             /*!< TIM control register 2,                      Address offset: 0x04 */
   uint16_t      RESERVED1;       /*!< Reserved,                                                    0x06 */
   __IO uint16_t SMCR;            /*!< TIM slave Mode Control register,             Address offset: 0x08 */
   uint16_t      RESERVED2;       /*!< Reserved,                                                    0x0A */
   __IO uint16_t DIER;            /*!< TIM DMA/interrupt enable register,           Address offset: 0x0C */
   uint16_t      RESERVED3;       /*!< Reserved,                                                    0x0E */
   __IO uint16_t SR;              /*!< TIM status register,                         Address offset: 0x10 */
   uint16_t      RESERVED4;       /*!< Reserved,                                                    0x12 */
   __IO uint16_t EGR;             /*!< TIM event generation register,               Address offset: 0x14 */
   uint16_t      RESERVED5;       /*!< Reserved,                                                    0x16 */
   __IO uint16_t CCMR1;           /*!< TIM  capture/compare mode register 1,        Address offset: 0x18 */
   uint16_t      RESERVED6;       /*!< Reserved,                                                    0x1A */
   __IO uint16_t CCMR2;           /*!< TIM  capture/compare mode register 2,        Address offset: 0x1C */
   uint16_t      RESERVED7;       /*!< Reserved,                                                    0x1E */
   __IO uint16_t CCER;            /*!< TIM capture/compare enable register,         Address offset: 0x20 */
   uint16_t      RESERVED8;       /*!< Reserved,                                                    0x22 */
   __IO uint32_t CNT;             /*!< TIM counter register,                        Address offset: 0x24 */
   __IO uint16_t PSC;             /*!< TIM prescaler register,                      Address offset: 0x28 */
   uint16_t      RESERVED10;      /*!< Reserved,                                                    0x2A */
   __IO uint32_t ARR;             /*!< TIM auto-reload register,                    Address offset: 0x2C */
   __IO uint16_t RCR;             /*!< TIM  repetition counter register,            Address offset: 0x30 */
   uint16_t      RESERVED12;      /*!< Reserved,                                                    0x32 */
   __IO uint32_t CCR1;            /*!< TIM capture/compare register 1,              Address offset: 0x34 */
   __IO uint32_t CCR2;            /*!< TIM capture/compare register 2,              Address offset: 0x38 */
   __IO uint32_t CCR3;            /*!< TIM capture/compare register 3,              Address offset: 0x3C */
   __IO uint32_t CCR4;            /*!< TIM capture/compare register 4,              Address offset: 0x40 */
   __IO uint16_t BDTR;            /*!< TIM break and dead-time register,            Address offset: 0x44 */
   uint16_t      RESERVED17;      /*!< Reserved,                                                    0x26 */
   __IO uint16_t DCR;             /*!< TIM DMA control register,                    Address offset: 0x48 */
   uint16_t      RESERVED18;      /*!< Reserved,                                                    0x4A */
   __IO uint16_t DMAR;            /*!< TIM DMA address for full transfer register,  Address offset: 0x4C */
   uint16_t      RESERVED19;      /*!< Reserved,                                                    0x4E */
   __IO uint16_t OR;              /*!< TIM option register,                         Address offset: 0x50 */
   uint16_t      RESERVED20;      /*!< Reserved,                                                    0x52 */
 } TIM_TypeDef;
 /**
   * @brief Touch Sensing Controller (TSC)
   */
 typedef struct
+{
   __IO uint32_t CR;        /*!< TSC control register,                                     Address offset: 0x00 */
   __IO uint32_t IER;       /*!< TSC interrupt enable register,                            Address offset: 0x04 */
   __IO uint32_t ICR;       /*!< TSC interrupt clear register,                             Address offset: 0x08 */
   __IO uint32_t ISR;       /*!< TSC interrupt status register,                            Address offset: 0x0C */
   __IO uint32_t IOHCR;     /*!< TSC I/O hysteresis control register,                      Address offset: 0x10 */
   __IO uint32_t RESERVED1; /*!< Reserved,                                                 Address offset: 0x14 */
   __IO uint32_t IOASCR;    /*!< TSC I/O analog switch control register,                   Address offset: 0x18 */
   __IO uint32_t RESERVED2; /*!< Reserved,                                                 Address offset: 0x1C */
   __IO uint32_t IOSCR;     /*!< TSC I/O sampling control register,                        Address offset: 0x20 */
   __IO uint32_t RESERVED3; /*!< Reserved,                                                 Address offset: 0x24 */
   __IO uint32_t IOCCR;     /*!< TSC I/O channel control register,                         Address offset: 0x28 */
   __IO uint32_t RESERVED4; /*!< Reserved,                                                 Address offset: 0x2C */
   __IO uint32_t IOGCSR;    /*!< TSC I/O group control status register,                    Address offset: 0x30 */
   __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register,                         Address offset: 0x34-50 */
 } TSC_TypeDef;
 /**
   * @brief Universal Synchronous Asynchronous Receiver Transmitter
   */
 typedef struct
+{
   __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */
   __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */
   __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
   __IO uint16_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */
   uint16_t  RESERVED1;  /*!< Reserved, 0x0E                                                 */
   __IO uint16_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
   uint16_t  RESERVED2;  /*!< Reserved, 0x12                                                 */
   __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */
   __IO uint16_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
   uint16_t  RESERVED3;  /*!< Reserved, 0x1A                                                 */
   __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
   __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
   __IO uint16_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
   uint16_t  RESERVED4;  /*!< Reserved, 0x26                                                 */
   __IO uint16_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
   uint16_t  RESERVED5;  /*!< Reserved, 0x2A                                                 */
 } USART_TypeDef;
 /**
   * @brief Window WATCHDOG
   */
 typedef struct
+{
   __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
   __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
   __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
 } WWDG_TypeDef;
 /**
   * @}
   */
 /** @addtogroup Peripheral_memory_map
   * @{
   */
 #define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
 #define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
 #define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
 /*!< Peripheral memory map */
 #define APBPERIPH_BASE        PERIPH_BASE
 #define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000)
 #define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000)
 #define TIM2_BASE             (APBPERIPH_BASE + 0x00000000)
 #define TIM3_BASE             (APBPERIPH_BASE + 0x00000400)
 #define TIM6_BASE             (APBPERIPH_BASE + 0x00001000)
 #define TIM7_BASE             (APBPERIPH_BASE + 0x00001400)
 #define TIM14_BASE            (APBPERIPH_BASE + 0x00002000)
 #define RTC_BASE              (APBPERIPH_BASE + 0x00002800)
 #define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00)
 #define IWDG_BASE             (APBPERIPH_BASE + 0x00003000)
 #define SPI2_BASE             (APBPERIPH_BASE + 0x00003800)
 #define USART2_BASE           (APBPERIPH_BASE + 0x00004400)
 #define USART3_BASE           (APBPERIPH_BASE + 0x00004800)
 #define USART4_BASE           (APBPERIPH_BASE + 0x00004C00)
 #define USART5_BASE           (APBPERIPH_BASE + 0x00005000)
 #define I2C1_BASE             (APBPERIPH_BASE + 0x00005400)
 #define I2C2_BASE             (APBPERIPH_BASE + 0x00005800)
 #define CAN_BASE              (APBPERIPH_BASE + 0x00006400)
 #define CRS_BASE              (APBPERIPH_BASE + 0x00006C00)
 #define PWR_BASE              (APBPERIPH_BASE + 0x00007000)
 #define DAC_BASE              (APBPERIPH_BASE + 0x00007400)
 #define CEC_BASE              (APBPERIPH_BASE + 0x00007800)
 #define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000)
 #define COMP_BASE             (APBPERIPH_BASE + 0x0001001C)
 #define EXTI_BASE             (APBPERIPH_BASE + 0x00010400)
 #define USART6_BASE           (APBPERIPH_BASE + 0x00011400)
 #define USART7_BASE           (APBPERIPH_BASE + 0x00011800)
 #define USART8_BASE           (APBPERIPH_BASE + 0x00011C00)
 #define ADC1_BASE             (APBPERIPH_BASE + 0x00012400) /* KVL: TBC*/
 #define ADC_BASE              (APBPERIPH_BASE + 0x00012708) /* KVL: TBC*/
 #define TIM1_BASE             (APBPERIPH_BASE + 0x00012C00)
 #define SPI1_BASE             (APBPERIPH_BASE + 0x00013000)
 #define USART1_BASE           (APBPERIPH_BASE + 0x00013800)
 #define TIM15_BASE            (APBPERIPH_BASE + 0x00014000)
 #define TIM16_BASE            (APBPERIPH_BASE + 0x00014400)
 #define TIM17_BASE            (APBPERIPH_BASE + 0x00014800)
 #define DBGMCU_BASE           (APBPERIPH_BASE + 0x00015800)
 #define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000)
 #define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008)
 #define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001C)
 #define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030)
 #define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044)
 #define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058)
 #define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006C)
 #define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080)
 #define DMA2_BASE             (AHBPERIPH_BASE + 0x00000400)
 #define DMA2_Channel1_BASE    (DMA2_BASE + 0x00000008)
 #define DMA2_Channel2_BASE    (DMA2_BASE + 0x0000001C)
 #define DMA2_Channel3_BASE    (DMA2_BASE + 0x00000030)
 #define DMA2_Channel4_BASE    (DMA2_BASE + 0x00000044)
 #define DMA2_Channel5_BASE    (DMA2_BASE + 0x00000058)
 #define RCC_BASE              (AHBPERIPH_BASE + 0x00001000)
 #define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
 #define OB_BASE               ((uint32_t)0x1FFFF800)        /*!< FLASH Option Bytes base address */
 #define CRC_BASE              (AHBPERIPH_BASE + 0x00003000)
 #define TSC_BASE              (AHBPERIPH_BASE + 0x00004000)
 #define GPIOA_BASE            (AHB2PERIPH_BASE + 0x00000000)
 #define GPIOB_BASE            (AHB2PERIPH_BASE + 0x00000400)
 #define GPIOC_BASE            (AHB2PERIPH_BASE + 0x00000800)
 #define GPIOD_BASE            (AHB2PERIPH_BASE + 0x00000C00)
 #define GPIOE_BASE            (AHB2PERIPH_BASE + 0x00001000)
 #define GPIOF_BASE            (AHB2PERIPH_BASE + 0x00001400)
 /**
   * @}
   */
 /** @addtogroup Peripheral_declaration
   * @{
   */
 #define TIM2                ((TIM_TypeDef *) TIM2_BASE)
 #define TIM3                ((TIM_TypeDef *) TIM3_BASE)
 #define TIM6                ((TIM_TypeDef *) TIM6_BASE)
 #define TIM7                ((TIM_TypeDef *) TIM7_BASE)
 #define TIM14               ((TIM_TypeDef *) TIM14_BASE)
 #define RTC                 ((RTC_TypeDef *) RTC_BASE)
 #define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
 #define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
 #define SPI2                ((SPI_TypeDef *) SPI2_BASE)
 #define USART2              ((USART_TypeDef *) USART2_BASE)
 #define USART3              ((USART_TypeDef *) USART3_BASE)
 #define USART4              ((USART_TypeDef *) USART4_BASE)
 #define USART5              ((USART_TypeDef *) USART5_BASE)
 #define I2C1                ((I2C_TypeDef *) I2C1_BASE)
 #define I2C2                ((I2C_TypeDef *) I2C2_BASE)
 #define CAN                 ((CAN_TypeDef *) CAN_BASE)
 #define CRS                 ((CRS_TypeDef *) CRS_BASE)
 #define PWR                 ((PWR_TypeDef *) PWR_BASE)
 #define DAC                 ((DAC_TypeDef *) DAC_BASE)
 #define CEC                 ((CEC_TypeDef *) CEC_BASE)
 #define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
 #define COMP                ((COMP_TypeDef *) COMP_BASE)
 #define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
 #define USART6              ((USART_TypeDef *) USART6_BASE)
 #define USART7              ((USART_TypeDef *) USART7_BASE)
 #define USART8              ((USART_TypeDef *) USART8_BASE)
 #define ADC1                ((ADC_TypeDef *) ADC1_BASE)
 #define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
 #define TIM1                ((TIM_TypeDef *) TIM1_BASE)
 #define SPI1                ((SPI_TypeDef *) SPI1_BASE)
 #define USART1              ((USART_TypeDef *) USART1_BASE)
 #define TIM15               ((TIM_TypeDef *) TIM15_BASE)
 #define TIM16               ((TIM_TypeDef *) TIM16_BASE)
 #define TIM17               ((TIM_TypeDef *) TIM17_BASE)
 #define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
 #define DMA1                ((DMA_TypeDef *) DMA1_BASE)
 #define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
 #define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
 #define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
 #define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
 #define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
 #define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
 #define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
 #define DMA2                ((DMA_TypeDef *) DMA2_BASE)
 #define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
 #define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
 #define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
 #define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
 #define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
 #define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
 #define OB                  ((OB_TypeDef *) OB_BASE)
 #define RCC                 ((RCC_TypeDef *) RCC_BASE)
 #define CRC                 ((CRC_TypeDef *) CRC_BASE)
 #define TSC                 ((TSC_TypeDef *) TSC_BASE)
 #define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
 #define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
 #define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
 #define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
 #define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
 #define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
 /**
   * @}
   */
 /** @addtogroup Exported_constants
   * @{
   */
   /** @addtogroup Peripheral_Registers_Bits_Definition
   * @{
   */
 /******************************************************************************/
 /*                         Peripheral Registers Bits Definition               */
 /******************************************************************************/
 /******************************************************************************/
 /*                                                                            */
 /*                      Analog to Digital Converter (ADC)                     */
 /*                                                                            */
 /******************************************************************************/
 /********************  Bits definition for ADC_ISR register  ******************/
 #define ADC_ISR_AWD                          ((uint32_t)0x00000080)        /*!< Analog watchdog flag */
 #define ADC_ISR_OVR                          ((uint32_t)0x00000010)        /*!< Overrun flag */
 #define ADC_ISR_EOSEQ                        ((uint32_t)0x00000008)        /*!< End of Sequence flag */
 #define ADC_ISR_EOC                          ((uint32_t)0x00000004)        /*!< End of Conversion */
 #define ADC_ISR_EOSMP                        ((uint32_t)0x00000002)        /*!< End of sampling flag */
 #define ADC_ISR_ADRDY                        ((uint32_t)0x00000001)        /*!< ADC Ready */
 /* Old EOSEQ bit definition, maintained for legacy purpose */
 #define ADC_ISR_EOS                          ADC_ISR_EOSEQ
 /********************  Bits definition for ADC_IER register  ******************/
 #define ADC_IER_AWDIE                        ((uint32_t)0x00000080)        /*!< Analog Watchdog interrupt enable */
 #define ADC_IER_OVRIE                        ((uint32_t)0x00000010)        /*!< Overrun interrupt enable */
 #define ADC_IER_EOSEQIE                      ((uint32_t)0x00000008)        /*!< End of Sequence of conversion interrupt enable */
 #define ADC_IER_EOCIE                        ((uint32_t)0x00000004)        /*!< End of Conversion interrupt enable */
 #define ADC_IER_EOSMPIE                      ((uint32_t)0x00000002)        /*!< End of sampling interrupt enable */
 #define ADC_IER_ADRDYIE                      ((uint32_t)0x00000001)        /*!< ADC Ready interrupt enable */
 /* Old EOSEQIE bit definition, maintained for legacy purpose */
 #define ADC_IER_EOSIE                        ADC_IER_EOSEQIE
 /********************  Bits definition for ADC_CR register  *******************/
 #define ADC_CR_ADCAL                         ((uint32_t)0x80000000)        /*!< ADC calibration */
 #define ADC_CR_ADSTP                         ((uint32_t)0x00000010)        /*!< ADC stop of conversion command */
 #define ADC_CR_ADSTART                       ((uint32_t)0x00000004)        /*!< ADC start of conversion */
 #define ADC_CR_ADDIS                         ((uint32_t)0x00000002)        /*!< ADC disable command */
 #define ADC_CR_ADEN                          ((uint32_t)0x00000001)        /*!< ADC enable control */
 /*******************  Bits definition for ADC_CFGR1 register  *****************/
 #define  ADC_CFGR1_AWDCH                      ((uint32_t)0x7C000000)       /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
 #define  ADC_CFGR1_AWDCH_0                    ((uint32_t)0x04000000)       /*!< Bit 0 */
 #define  ADC_CFGR1_AWDCH_1                    ((uint32_t)0x08000000)       /*!< Bit 1 */
 #define  ADC_CFGR1_AWDCH_2                    ((uint32_t)0x10000000)       /*!< Bit 2 */
 #define  ADC_CFGR1_AWDCH_3                    ((uint32_t)0x20000000)       /*!< Bit 3 */
 #define  ADC_CFGR1_AWDCH_4                    ((uint32_t)0x40000000)       /*!< Bit 4 */
 #define  ADC_CFGR1_AWDEN                      ((uint32_t)0x00800000)       /*!< Analog watchdog enable on regular channels */
 #define  ADC_CFGR1_AWDSGL                     ((uint32_t)0x00400000)       /*!< Enable the watchdog on a single channel or on all channels  */
 #define  ADC_CFGR1_DISCEN                     ((uint32_t)0x00010000)       /*!< Discontinuous mode on regular channels */
 #define  ADC_CFGR1_AUTOFF                     ((uint32_t)0x00008000)       /*!< ADC auto power off */
 #define  ADC_CFGR1_WAIT                       ((uint32_t)0x00004000)       /*!< ADC wait conversion mode */
 #define  ADC_CFGR1_CONT                       ((uint32_t)0x00002000)       /*!< Continuous Conversion */
 #define  ADC_CFGR1_OVRMOD                     ((uint32_t)0x00001000)       /*!< Overrun mode */
 #define  ADC_CFGR1_EXTEN                      ((uint32_t)0x00000C00)       /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
 #define  ADC_CFGR1_EXTEN_0                    ((uint32_t)0x00000400)       /*!< Bit 0 */
 #define  ADC_CFGR1_EXTEN_1                    ((uint32_t)0x00000800)       /*!< Bit 1 */
 #define  ADC_CFGR1_EXTSEL                     ((uint32_t)0x000001C0)       /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
 #define  ADC_CFGR1_EXTSEL_0                   ((uint32_t)0x00000040)       /*!< Bit 0 */
 #define  ADC_CFGR1_EXTSEL_1                   ((uint32_t)0x00000080)       /*!< Bit 1 */
 #define  ADC_CFGR1_EXTSEL_2                   ((uint32_t)0x00000100)       /*!< Bit 2 */
 #define  ADC_CFGR1_ALIGN                      ((uint32_t)0x00000020)       /*!< Data Alignment */
 #define  ADC_CFGR1_RES                        ((uint32_t)0x00000018)       /*!< RES[1:0] bits (Resolution) */
 #define  ADC_CFGR1_RES_0                      ((uint32_t)0x00000008)       /*!< Bit 0 */
 #define  ADC_CFGR1_RES_1                      ((uint32_t)0x00000010)       /*!< Bit 1 */
 #define  ADC_CFGR1_SCANDIR                    ((uint32_t)0x00000004)       /*!< Sequence scan direction */
 #define  ADC_CFGR1_DMACFG                     ((uint32_t)0x00000002)       /*!< Direct memory access configuration */
 #define  ADC_CFGR1_DMAEN                      ((uint32_t)0x00000001)       /*!< Direct memory access enable */
 /* Old WAIT bit definition, maintained for legacy purpose */
 #define  ADC_CFGR1_AUTDLY                     ADC_CFGR1_WAIT
 /*******************  Bits definition for ADC_CFGR2 register  *****************/
 #define  ADC_CFGR2_CKMODE                     ((uint32_t)0xC0000000)       /*!< ADC clock mode */
 #define  ADC_CFGR2_CKMODE_1                   ((uint32_t)0x80000000)       /*!< ADC clocked by PCLK div4 */
 #define  ADC_CFGR2_CKMODE_0                   ((uint32_t)0x40000000)       /*!< ADC clocked by PCLK div2 */
 /* Old bit definition, maintained for legacy purpose */
 #define  ADC_CFGR2_JITOFFDIV4                 ADC_CFGR2_CKMODE_1           /*!< ADC clocked by PCLK div4 */
 #define  ADC_CFGR2_JITOFFDIV2                 ADC_CFGR2_CKMODE_0           /*!< ADC clocked by PCLK div2 */
 /******************  Bit definition for ADC_SMPR register  ********************/
 #define  ADC_SMPR_SMP                      ((uint32_t)0x00000007)        /*!< SMP[2:0] bits (Sampling time selection) */
 #define  ADC_SMPR_SMP_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
 #define  ADC_SMPR_SMP_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
 #define  ADC_SMPR_SMP_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */
 /* Old bit definition, maintained for legacy purpose */
 #define  ADC_SMPR1_SMPR                      ADC_SMPR_SMP        /*!< SMP[2:0] bits (Sampling time selection) */
 #define  ADC_SMPR1_SMPR_0                    ADC_SMPR_SMP_0        /*!< Bit 0 */
 #define  ADC_SMPR1_SMPR_1                    ADC_SMPR_SMP_1        /*!< Bit 1 */
 #define  ADC_SMPR1_SMPR_2                    ADC_SMPR_SMP_2        /*!< Bit 2 */
 /*******************  Bit definition for ADC_TR register  ********************/
 #define  ADC_TR_HT                          ((uint32_t)0x0FFF0000)        /*!< Analog watchdog high threshold */
 #define  ADC_TR_LT                          ((uint32_t)0x00000FFF)        /*!< Analog watchdog low threshold */
 /* Old bit definition, maintained for legacy purpose */
 #define  ADC_HTR_HT                          ADC_TR_HT                    /*!< Analog watchdog high threshold */
 #define  ADC_LTR_LT                          ADC_TR_LT                    /*!< Analog watchdog low threshold */
 /******************  Bit definition for ADC_CHSELR register  ******************/
 #define  ADC_CHSELR_CHSEL18                   ((uint32_t)0x00040000)        /*!< Channel 18 selection */
 #define  ADC_CHSELR_CHSEL17                   ((uint32_t)0x00020000)        /*!< Channel 17 selection */
 #define  ADC_CHSELR_CHSEL16                   ((uint32_t)0x00010000)        /*!< Channel 16 selection */
 #define  ADC_CHSELR_CHSEL15                   ((uint32_t)0x00008000)        /*!< Channel 15 selection */
 #define  ADC_CHSELR_CHSEL14                   ((uint32_t)0x00004000)        /*!< Channel 14 selection */
 #define  ADC_CHSELR_CHSEL13                   ((uint32_t)0x00002000)        /*!< Channel 13 selection */
 #define  ADC_CHSELR_CHSEL12                   ((uint32_t)0x00001000)        /*!< Channel 12 selection */
 #define  ADC_CHSELR_CHSEL11                   ((uint32_t)0x00000800)        /*!< Channel 11 selection */
 #define  ADC_CHSELR_CHSEL10                   ((uint32_t)0x00000400)        /*!< Channel 10 selection */
 #define  ADC_CHSELR_CHSEL9                    ((uint32_t)0x00000200)        /*!< Channel 9 selection */
 #define  ADC_CHSELR_CHSEL8                    ((uint32_t)0x00000100)        /*!< Channel 8 selection */
 #define  ADC_CHSELR_CHSEL7                    ((uint32_t)0x00000080)        /*!< Channel 7 selection */
 #define  ADC_CHSELR_CHSEL6                    ((uint32_t)0x00000040)        /*!< Channel 6 selection */
 #define  ADC_CHSELR_CHSEL5                    ((uint32_t)0x00000020)        /*!< Channel 5 selection */
 #define  ADC_CHSELR_CHSEL4                    ((uint32_t)0x00000010)        /*!< Channel 4 selection */
 #define  ADC_CHSELR_CHSEL3                    ((uint32_t)0x00000008)        /*!< Channel 3 selection */
 #define  ADC_CHSELR_CHSEL2                    ((uint32_t)0x00000004)        /*!< Channel 2 selection */
 #define  ADC_CHSELR_CHSEL1                    ((uint32_t)0x00000002)        /*!< Channel 1 selection */
 #define  ADC_CHSELR_CHSEL0                    ((uint32_t)0x00000001)        /*!< Channel 0 selection */
 /********************  Bit definition for ADC_DR register  ********************/
 #define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!< Regular data */
 /*******************  Bit definition for ADC_CCR register  ********************/
 #define  ADC_CCR_VBATEN                       ((uint32_t)0x01000000)       /*!< Voltage battery enable */
 #define  ADC_CCR_TSEN                         ((uint32_t)0x00800000)       /*!< Tempurature sensore enable */
 #define  ADC_CCR_VREFEN                       ((uint32_t)0x00400000)       /*!< Vrefint enable */
 /******************************************************************************/
 /*                                                                            */
 /*                   Controller Area Network (CAN )                           */
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for CAN_MCR register  ********************/
 #define  CAN_MCR_INRQ                        ((uint16_t)0x0001)            /*!<Initialization Request */
 #define  CAN_MCR_SLEEP                       ((uint16_t)0x0002)            /*!<Sleep Mode Request */
 #define  CAN_MCR_TXFP                        ((uint16_t)0x0004)            /*!<Transmit FIFO Priority */
 #define  CAN_MCR_RFLM                        ((uint16_t)0x0008)            /*!<Receive FIFO Locked Mode */
 #define  CAN_MCR_NART                        ((uint16_t)0x0010)            /*!<No Automatic Retransmission */
 #define  CAN_MCR_AWUM                        ((uint16_t)0x0020)            /*!<Automatic Wakeup Mode */
 #define  CAN_MCR_ABOM                        ((uint16_t)0x0040)            /*!<Automatic Bus-Off Management */
 #define  CAN_MCR_TTCM                        ((uint16_t)0x0080)            /*!<Time Triggered Communication Mode */
 #define  CAN_MCR_RESET                       ((uint16_t)0x8000)            /*!<bxCAN software master reset */
 /*******************  Bit definition for CAN_MSR register  ********************/
 #define  CAN_MSR_INAK                        ((uint16_t)0x0001)            /*!<Initialization Acknowledge */
 #define  CAN_MSR_SLAK                        ((uint16_t)0x0002)            /*!<Sleep Acknowledge */
 #define  CAN_MSR_ERRI                        ((uint16_t)0x0004)            /*!<Error Interrupt */
 #define  CAN_MSR_WKUI                        ((uint16_t)0x0008)            /*!<Wakeup Interrupt */
 #define  CAN_MSR_SLAKI                       ((uint16_t)0x0010)            /*!<Sleep Acknowledge Interrupt */
 #define  CAN_MSR_TXM                         ((uint16_t)0x0100)            /*!<Transmit Mode */
 #define  CAN_MSR_RXM                         ((uint16_t)0x0200)            /*!<Receive Mode */
 #define  CAN_MSR_SAMP                        ((uint16_t)0x0400)            /*!<Last Sample Point */
 #define  CAN_MSR_RX                          ((uint16_t)0x0800)            /*!<CAN Rx Signal */
 /*******************  Bit definition for CAN_TSR register  ********************/
 #define  CAN_TSR_RQCP0                       ((uint32_t)0x00000001)        /*!<Request Completed Mailbox0 */
 #define  CAN_TSR_TXOK0                       ((uint32_t)0x00000002)        /*!<Transmission OK of Mailbox0 */
 #define  CAN_TSR_ALST0                       ((uint32_t)0x00000004)        /*!<Arbitration Lost for Mailbox0 */
 #define  CAN_TSR_TERR0                       ((uint32_t)0x00000008)        /*!<Transmission Error of Mailbox0 */
 #define  CAN_TSR_ABRQ0                       ((uint32_t)0x00000080)        /*!<Abort Request for Mailbox0 */
 #define  CAN_TSR_RQCP1                       ((uint32_t)0x00000100)        /*!<Request Completed Mailbox1 */
 #define  CAN_TSR_TXOK1                       ((uint32_t)0x00000200)        /*!<Transmission OK of Mailbox1 */
 #define  CAN_TSR_ALST1                       ((uint32_t)0x00000400)        /*!<Arbitration Lost for Mailbox1 */
 #define  CAN_TSR_TERR1                       ((uint32_t)0x00000800)        /*!<Transmission Error of Mailbox1 */
 #define  CAN_TSR_ABRQ1                       ((uint32_t)0x00008000)        /*!<Abort Request for Mailbox 1 */
 #define  CAN_TSR_RQCP2                       ((uint32_t)0x00010000)        /*!<Request Completed Mailbox2 */
 #define  CAN_TSR_TXOK2                       ((uint32_t)0x00020000)        /*!<Transmission OK of Mailbox 2 */
 #define  CAN_TSR_ALST2                       ((uint32_t)0x00040000)        /*!<Arbitration Lost for mailbox 2 */
 #define  CAN_TSR_TERR2                       ((uint32_t)0x00080000)        /*!<Transmission Error of Mailbox 2 */
 #define  CAN_TSR_ABRQ2                       ((uint32_t)0x00800000)        /*!<Abort Request for Mailbox 2 */
 #define  CAN_TSR_CODE                        ((uint32_t)0x03000000)        /*!<Mailbox Code */
 #define  CAN_TSR_TME                         ((uint32_t)0x1C000000)        /*!<TME[2:0] bits */
 #define  CAN_TSR_TME0                        ((uint32_t)0x04000000)        /*!<Transmit Mailbox 0 Empty */
 #define  CAN_TSR_TME1                        ((uint32_t)0x08000000)        /*!<Transmit Mailbox 1 Empty */
 #define  CAN_TSR_TME2                        ((uint32_t)0x10000000)        /*!<Transmit Mailbox 2 Empty */
 #define  CAN_TSR_LOW                         ((uint32_t)0xE0000000)        /*!<LOW[2:0] bits */
 #define  CAN_TSR_LOW0                        ((uint32_t)0x20000000)        /*!<Lowest Priority Flag for Mailbox 0 */
 #define  CAN_TSR_LOW1                        ((uint32_t)0x40000000)        /*!<Lowest Priority Flag for Mailbox 1 */
 #define  CAN_TSR_LOW2                        ((uint32_t)0x80000000)        /*!<Lowest Priority Flag for Mailbox 2 */
 /*******************  Bit definition for CAN_RF0R register  *******************/
 #define  CAN_RF0R_FMP0                       ((uint8_t)0x03)               /*!<FIFO 0 Message Pending */
 #define  CAN_RF0R_FULL0                      ((uint8_t)0x08)               /*!<FIFO 0 Full */
 #define  CAN_RF0R_FOVR0                      ((uint8_t)0x10)               /*!<FIFO 0 Overrun */
 #define  CAN_RF0R_RFOM0                      ((uint8_t)0x20)               /*!<Release FIFO 0 Output Mailbox */
 /*******************  Bit definition for CAN_RF1R register  *******************/
 #define  CAN_RF1R_FMP1                       ((uint8_t)0x03)               /*!<FIFO 1 Message Pending */
 #define  CAN_RF1R_FULL1                      ((uint8_t)0x08)               /*!<FIFO 1 Full */
 #define  CAN_RF1R_FOVR1                      ((uint8_t)0x10)               /*!<FIFO 1 Overrun */
 #define  CAN_RF1R_RFOM1                      ((uint8_t)0x20)               /*!<Release FIFO 1 Output Mailbox */
 /********************  Bit definition for CAN_IER register  *******************/
 #define  CAN_IER_TMEIE                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Empty Interrupt Enable */
 #define  CAN_IER_FMPIE0                      ((uint32_t)0x00000002)        /*!<FIFO Message Pending Interrupt Enable */
 #define  CAN_IER_FFIE0                       ((uint32_t)0x00000004)        /*!<FIFO Full Interrupt Enable */
 #define  CAN_IER_FOVIE0                      ((uint32_t)0x00000008)        /*!<FIFO Overrun Interrupt Enable */
 #define  CAN_IER_FMPIE1                      ((uint32_t)0x00000010)        /*!<FIFO Message Pending Interrupt Enable */
 #define  CAN_IER_FFIE1                       ((uint32_t)0x00000020)        /*!<FIFO Full Interrupt Enable */
 #define  CAN_IER_FOVIE1                      ((uint32_t)0x00000040)        /*!<FIFO Overrun Interrupt Enable */
 #define  CAN_IER_EWGIE                       ((uint32_t)0x00000100)        /*!<Error Warning Interrupt Enable */
 #define  CAN_IER_EPVIE                       ((uint32_t)0x00000200)        /*!<Error Passive Interrupt Enable */
 #define  CAN_IER_BOFIE                       ((uint32_t)0x00000400)        /*!<Bus-Off Interrupt Enable */
 #define  CAN_IER_LECIE                       ((uint32_t)0x00000800)        /*!<Last Error Code Interrupt Enable */
 #define  CAN_IER_ERRIE                       ((uint32_t)0x00008000)        /*!<Error Interrupt Enable */
 #define  CAN_IER_WKUIE                       ((uint32_t)0x00010000)        /*!<Wakeup Interrupt Enable */
 #define  CAN_IER_SLKIE                       ((uint32_t)0x00020000)        /*!<Sleep Interrupt Enable */
 /********************  Bit definition for CAN_ESR register  *******************/
 #define  CAN_ESR_EWGF                        ((uint32_t)0x00000001)        /*!<Error Warning Flag */
 #define  CAN_ESR_EPVF                        ((uint32_t)0x00000002)        /*!<Error Passive Flag */
 #define  CAN_ESR_BOFF                        ((uint32_t)0x00000004)        /*!<Bus-Off Flag */
 #define  CAN_ESR_LEC                         ((uint32_t)0x00000070)        /*!<LEC[2:0] bits (Last Error Code) */
 #define  CAN_ESR_LEC_0                       ((uint32_t)0x00000010)        /*!<Bit 0 */
 #define  CAN_ESR_LEC_1                       ((uint32_t)0x00000020)        /*!<Bit 1 */
 #define  CAN_ESR_LEC_2                       ((uint32_t)0x00000040)        /*!<Bit 2 */
 #define  CAN_ESR_TEC                         ((uint32_t)0x00FF0000)        /*!<Least significant byte of the 9-bit Transmit Error Counter */
 #define  CAN_ESR_REC                         ((uint32_t)0xFF000000)        /*!<Receive Error Counter */
 /*******************  Bit definition for CAN_BTR register  ********************/
 #define  CAN_BTR_BRP                         ((uint32_t)0x000003FF)        /*!<Baud Rate Prescaler */
 #define  CAN_BTR_TS1                         ((uint32_t)0x000F0000)        /*!<Time Segment 1 */
 #define  CAN_BTR_TS2                         ((uint32_t)0x00700000)        /*!<Time Segment 2 */
 #define  CAN_BTR_SJW                         ((uint32_t)0x03000000)        /*!<Resynchronization Jump Width */
 #define  CAN_BTR_LBKM                        ((uint32_t)0x40000000)        /*!<Loop Back Mode (Debug) */
 #define  CAN_BTR_SILM                        ((uint32_t)0x80000000)        /*!<Silent Mode */
 /*!<Mailbox registers */
 /******************  Bit definition for CAN_TI0R register  ********************/
 #define  CAN_TI0R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
 #define  CAN_TI0R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
 #define  CAN_TI0R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
 #define  CAN_TI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
 #define  CAN_TI0R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
 /******************  Bit definition for CAN_TDT0R register  *******************/
 #define  CAN_TDT0R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
 #define  CAN_TDT0R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
 #define  CAN_TDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
 /******************  Bit definition for CAN_TDL0R register  *******************/
 #define  CAN_TDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
 #define  CAN_TDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
 #define  CAN_TDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
 #define  CAN_TDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
 /******************  Bit definition for CAN_TDH0R register  *******************/
 #define  CAN_TDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
 #define  CAN_TDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
 #define  CAN_TDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
 #define  CAN_TDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
 /*******************  Bit definition for CAN_TI1R register  *******************/
 #define  CAN_TI1R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
 #define  CAN_TI1R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
 #define  CAN_TI1R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
 #define  CAN_TI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
 #define  CAN_TI1R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
 /*******************  Bit definition for CAN_TDT1R register  ******************/
 #define  CAN_TDT1R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
 #define  CAN_TDT1R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
 #define  CAN_TDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
 /*******************  Bit definition for CAN_TDL1R register  ******************/
 #define  CAN_TDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
 #define  CAN_TDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
 #define  CAN_TDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
 #define  CAN_TDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
 /*******************  Bit definition for CAN_TDH1R register  ******************/
 #define  CAN_TDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
 #define  CAN_TDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
 #define  CAN_TDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
 #define  CAN_TDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
 /*******************  Bit definition for CAN_TI2R register  *******************/
 #define  CAN_TI2R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
 #define  CAN_TI2R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
 #define  CAN_TI2R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
 #define  CAN_TI2R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended identifier */
 #define  CAN_TI2R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
 /*******************  Bit definition for CAN_TDT2R register  ******************/
 #define  CAN_TDT2R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
 #define  CAN_TDT2R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
 #define  CAN_TDT2R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
 /*******************  Bit definition for CAN_TDL2R register  ******************/
 #define  CAN_TDL2R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
 #define  CAN_TDL2R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
 #define  CAN_TDL2R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
 #define  CAN_TDL2R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
 /*******************  Bit definition for CAN_TDH2R register  ******************/
 #define  CAN_TDH2R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
 #define  CAN_TDH2R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
 #define  CAN_TDH2R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
 #define  CAN_TDH2R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
 /*******************  Bit definition for CAN_RI0R register  *******************/
 #define  CAN_RI0R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
 #define  CAN_RI0R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
 #define  CAN_RI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
 #define  CAN_RI0R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
 /*******************  Bit definition for CAN_RDT0R register  ******************/
 #define  CAN_RDT0R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
 #define  CAN_RDT0R_FMI                       ((uint32_t)0x0000FF00)        /*!<Filter Match Index */
 #define  CAN_RDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
 /*******************  Bit definition for CAN_RDL0R register  ******************/
 #define  CAN_RDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
 #define  CAN_RDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
 #define  CAN_RDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
 #define  CAN_RDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
 /*******************  Bit definition for CAN_RDH0R register  ******************/
 #define  CAN_RDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
 #define  CAN_RDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
 #define  CAN_RDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
 #define  CAN_RDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
 /*******************  Bit definition for CAN_RI1R register  *******************/
 #define  CAN_RI1R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
 #define  CAN_RI1R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
 #define  CAN_RI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended identifier */
 #define  CAN_RI1R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
 /*******************  Bit definition for CAN_RDT1R register  ******************/
 #define  CAN_RDT1R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
 #define  CAN_RDT1R_FMI                       ((uint32_t)0x0000FF00)        /*!<Filter Match Index */
 #define  CAN_RDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
 /*******************  Bit definition for CAN_RDL1R register  ******************/
 #define  CAN_RDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
 #define  CAN_RDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
 #define  CAN_RDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
 #define  CAN_RDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
 /*******************  Bit definition for CAN_RDH1R register  ******************/
 #define  CAN_RDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
 #define  CAN_RDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
 #define  CAN_RDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
 #define  CAN_RDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
 /*!<CAN filter registers */
 /*******************  Bit definition for CAN_FMR register  ********************/
 #define  CAN_FMR_FINIT                       ((uint8_t)0x01)               /*!<Filter Init Mode */
 /*******************  Bit definition for CAN_FM1R register  *******************/
 #define  CAN_FM1R_FBM                        ((uint16_t)0x3FFF)            /*!<Filter Mode */
 #define  CAN_FM1R_FBM0                       ((uint16_t)0x0001)            /*!<Filter Init Mode bit 0 */
 #define  CAN_FM1R_FBM1                       ((uint16_t)0x0002)            /*!<Filter Init Mode bit 1 */
 #define  CAN_FM1R_FBM2                       ((uint16_t)0x0004)            /*!<Filter Init Mode bit 2 */
 #define  CAN_FM1R_FBM3                       ((uint16_t)0x0008)            /*!<Filter Init Mode bit 3 */
 #define  CAN_FM1R_FBM4                       ((uint16_t)0x0010)            /*!<Filter Init Mode bit 4 */
 #define  CAN_FM1R_FBM5                       ((uint16_t)0x0020)            /*!<Filter Init Mode bit 5 */
 #define  CAN_FM1R_FBM6                       ((uint16_t)0x0040)            /*!<Filter Init Mode bit 6 */
 #define  CAN_FM1R_FBM7                       ((uint16_t)0x0080)            /*!<Filter Init Mode bit 7 */
 #define  CAN_FM1R_FBM8                       ((uint16_t)0x0100)            /*!<Filter Init Mode bit 8 */
 #define  CAN_FM1R_FBM9                       ((uint16_t)0x0200)            /*!<Filter Init Mode bit 9 */
 #define  CAN_FM1R_FBM10                      ((uint16_t)0x0400)            /*!<Filter Init Mode bit 10 */
 #define  CAN_FM1R_FBM11                      ((uint16_t)0x0800)            /*!<Filter Init Mode bit 11 */
 #define  CAN_FM1R_FBM12                      ((uint16_t)0x1000)            /*!<Filter Init Mode bit 12 */
 #define  CAN_FM1R_FBM13                      ((uint16_t)0x2000)            /*!<Filter Init Mode bit 13 */
 /*******************  Bit definition for CAN_FS1R register  *******************/
 #define  CAN_FS1R_FSC                        ((uint16_t)0x3FFF)            /*!<Filter Scale Configuration */
 #define  CAN_FS1R_FSC0                       ((uint16_t)0x0001)            /*!<Filter Scale Configuration bit 0 */
 #define  CAN_FS1R_FSC1                       ((uint16_t)0x0002)            /*!<Filter Scale Configuration bit 1 */
 #define  CAN_FS1R_FSC2                       ((uint16_t)0x0004)            /*!<Filter Scale Configuration bit 2 */
 #define  CAN_FS1R_FSC3                       ((uint16_t)0x0008)            /*!<Filter Scale Configuration bit 3 */
 #define  CAN_FS1R_FSC4                       ((uint16_t)0x0010)            /*!<Filter Scale Configuration bit 4 */
 #define  CAN_FS1R_FSC5                       ((uint16_t)0x0020)            /*!<Filter Scale Configuration bit 5 */
 #define  CAN_FS1R_FSC6                       ((uint16_t)0x0040)            /*!<Filter Scale Configuration bit 6 */
 #define  CAN_FS1R_FSC7                       ((uint16_t)0x0080)            /*!<Filter Scale Configuration bit 7 */
 #define  CAN_FS1R_FSC8                       ((uint16_t)0x0100)            /*!<Filter Scale Configuration bit 8 */
 #define  CAN_FS1R_FSC9                       ((uint16_t)0x0200)            /*!<Filter Scale Configuration bit 9 */
 #define  CAN_FS1R_FSC10                      ((uint16_t)0x0400)            /*!<Filter Scale Configuration bit 10 */
 #define  CAN_FS1R_FSC11                      ((uint16_t)0x0800)            /*!<Filter Scale Configuration bit 11 */
 #define  CAN_FS1R_FSC12                      ((uint16_t)0x1000)            /*!<Filter Scale Configuration bit 12 */
 #define  CAN_FS1R_FSC13                      ((uint16_t)0x2000)            /*!<Filter Scale Configuration bit 13 */
 /******************  Bit definition for CAN_FFA1R register  *******************/
 #define  CAN_FFA1R_FFA                       ((uint16_t)0x3FFF)            /*!<Filter FIFO Assignment */
 #define  CAN_FFA1R_FFA0                      ((uint16_t)0x0001)            /*!<Filter FIFO Assignment for Filter 0 */
 #define  CAN_FFA1R_FFA1                      ((uint16_t)0x0002)            /*!<Filter FIFO Assignment for Filter 1 */
 #define  CAN_FFA1R_FFA2                      ((uint16_t)0x0004)            /*!<Filter FIFO Assignment for Filter 2 */
 #define  CAN_FFA1R_FFA3                      ((uint16_t)0x0008)            /*!<Filter FIFO Assignment for Filter 3 */
 #define  CAN_FFA1R_FFA4                      ((uint16_t)0x0010)            /*!<Filter FIFO Assignment for Filter 4 */
 #define  CAN_FFA1R_FFA5                      ((uint16_t)0x0020)            /*!<Filter FIFO Assignment for Filter 5 */
 #define  CAN_FFA1R_FFA6                      ((uint16_t)0x0040)            /*!<Filter FIFO Assignment for Filter 6 */
 #define  CAN_FFA1R_FFA7                      ((uint16_t)0x0080)            /*!<Filter FIFO Assignment for Filter 7 */
 #define  CAN_FFA1R_FFA8                      ((uint16_t)0x0100)            /*!<Filter FIFO Assignment for Filter 8 */
 #define  CAN_FFA1R_FFA9                      ((uint16_t)0x0200)            /*!<Filter FIFO Assignment for Filter 9 */
 #define  CAN_FFA1R_FFA10                     ((uint16_t)0x0400)            /*!<Filter FIFO Assignment for Filter 10 */
 #define  CAN_FFA1R_FFA11                     ((uint16_t)0x0800)            /*!<Filter FIFO Assignment for Filter 11 */
 #define  CAN_FFA1R_FFA12                     ((uint16_t)0x1000)            /*!<Filter FIFO Assignment for Filter 12 */
 #define  CAN_FFA1R_FFA13                     ((uint16_t)0x2000)            /*!<Filter FIFO Assignment for Filter 13 */
 /*******************  Bit definition for CAN_FA1R register  *******************/
 #define  CAN_FA1R_FACT                       ((uint16_t)0x3FFF)            /*!<Filter Active */
 #define  CAN_FA1R_FACT0                      ((uint16_t)0x0001)            /*!<Filter 0 Active */
 #define  CAN_FA1R_FACT1                      ((uint16_t)0x0002)            /*!<Filter 1 Active */
 #define  CAN_FA1R_FACT2                      ((uint16_t)0x0004)            /*!<Filter 2 Active */
 #define  CAN_FA1R_FACT3                      ((uint16_t)0x0008)            /*!<Filter 3 Active */
 #define  CAN_FA1R_FACT4                      ((uint16_t)0x0010)            /*!<Filter 4 Active */
 #define  CAN_FA1R_FACT5                      ((uint16_t)0x0020)            /*!<Filter 5 Active */
 #define  CAN_FA1R_FACT6                      ((uint16_t)0x0040)            /*!<Filter 6 Active */
 #define  CAN_FA1R_FACT7                      ((uint16_t)0x0080)            /*!<Filter 7 Active */
 #define  CAN_FA1R_FACT8                      ((uint16_t)0x0100)            /*!<Filter 8 Active */
 #define  CAN_FA1R_FACT9                      ((uint16_t)0x0200)            /*!<Filter 9 Active */
 #define  CAN_FA1R_FACT10                     ((uint16_t)0x0400)            /*!<Filter 10 Active */
 #define  CAN_FA1R_FACT11                     ((uint16_t)0x0800)            /*!<Filter 11 Active */
 #define  CAN_FA1R_FACT12                     ((uint16_t)0x1000)            /*!<Filter 12 Active */
 #define  CAN_FA1R_FACT13                     ((uint16_t)0x2000)            /*!<Filter 13 Active */
 /*******************  Bit definition for CAN_F0R1 register  *******************/
 #define  CAN_F0R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
 #define  CAN_F0R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
 #define  CAN_F0R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
 #define  CAN_F0R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
 #define  CAN_F0R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
 #define  CAN_F0R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
 #define  CAN_F0R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
 #define  CAN_F0R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
 #define  CAN_F0R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
 #define  CAN_F0R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
 #define  CAN_F0R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
 #define  CAN_F0R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
 #define  CAN_F0R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
 #define  CAN_F0R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
 #define  CAN_F0R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
 #define  CAN_F0R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
 #define  CAN_F0R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
 #define  CAN_F0R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
 #define  CAN_F0R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
 #define  CAN_F0R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
 #define  CAN_F0R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
 #define  CAN_F0R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
 #define  CAN_F0R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
 #define  CAN_F0R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
 #define  CAN_F0R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
 #define  CAN_F0R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
 #define  CAN_F0R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
 #define  CAN_F0R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
 #define  CAN_F0R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
 #define  CAN_F0R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
 #define  CAN_F0R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
 #define  CAN_F0R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
 /*******************  Bit definition for CAN_F1R1 register  *******************/
 #define  CAN_F1R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
 #define  CAN_F1R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
 #define  CAN_F1R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
 #define  CAN_F1R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
 #define  CAN_F1R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
 #define  CAN_F1R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
 #define  CAN_F1R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
 #define  CAN_F1R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
 #define  CAN_F1R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
 #define  CAN_F1R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
 #define  CAN_F1R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
 #define  CAN_F1R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
 #define  CAN_F1R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
 #define  CAN_F1R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
 #define  CAN_F1R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
 #define  CAN_F1R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
 #define  CAN_F1R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
 #define  CAN_F1R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
 #define  CAN_F1R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
 #define  CAN_F1R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
 #define  CAN_F1R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
 #define  CAN_F1R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
 #define  CAN_F1R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
 #define  CAN_F1R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
 #define  CAN_F1R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
 #define  CAN_F1R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
 #define  CAN_F1R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
 #define  CAN_F1R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
 #define  CAN_F1R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
 #define  CAN_F1R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
 #define  CAN_F1R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
 #define  CAN_F1R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
 /*******************  Bit definition for CAN_F2R1 register  *******************/
 #define  CAN_F2R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
 #define  CAN_F2R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
 #define  CAN_F2R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
 #define  CAN_F2R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
 #define  CAN_F2R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
 #define  CAN_F2R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
 #define  CAN_F2R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
 #define  CAN_F2R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
 #define  CAN_F2R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
 #define  CAN_F2R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
 #define  CAN_F2R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
 #define  CAN_F2R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
 #define  CAN_F2R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
 #define  CAN_F2R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
 #define  CAN_F2R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
 #define  CAN_F2R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
 #define  CAN_F2R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
 #define  CAN_F2R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
 #define  CAN_F2R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
 #define  CAN_F2R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
 #define  CAN_F2R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
 #define  CAN_F2R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
 #define  CAN_F2R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
 #define  CAN_F2R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
 #define  CAN_F2R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
 #define  CAN_F2R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
 #define  CAN_F2R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
 #define  CAN_F2R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
 #define  CAN_F2R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
 #define  CAN_F2R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
 #define  CAN_F2R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
 #define  CAN_F2R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
 /*******************  Bit definition for CAN_F3R1 register  *******************/
 #define  CAN_F3R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
 #define  CAN_F3R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
 #define  CAN_F3R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
 #define  CAN_F3R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
 #define  CAN_F3R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
 #define  CAN_F3R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
 #define  CAN_F3R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
 #define  CAN_F3R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
 #define  CAN_F3R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
 #define  CAN_F3R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
 #define  CAN_F3R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
 #define  CAN_F3R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
 #define  CAN_F3R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
 #define  CAN_F3R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
 #define  CAN_F3R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
 #define  CAN_F3R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
 #define  CAN_F3R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
 #define  CAN_F3R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
 #define  CAN_F3R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
 #define  CAN_F3R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
 #define  CAN_F3R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
 #define  CAN_F3R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
 #define  CAN_F3R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
 #define  CAN_F3R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
 #define  CAN_F3R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
 #define  CAN_F3R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
 #define  CAN_F3R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
 #define  CAN_F3R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
 #define  CAN_F3R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
 #define  CAN_F3R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
 #define  CAN_F3R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
 #define  CAN_F3R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
 /*******************  Bit definition for CAN_F4R1 register  *******************/
 #define  CAN_F4R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
 #define  CAN_F4R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
 #define  CAN_F4R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
 #define  CAN_F4R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
 #define  CAN_F4R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
 #define  CAN_F4R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
 #define  CAN_F4R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
 #define  CAN_F4R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
 #define  CAN_F4R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
 #define  CAN_F4R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
 #define  CAN_F4R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
 #define  CAN_F4R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
 #define  CAN_F4R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
 #define  CAN_F4R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
 #define  CAN_F4R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
 #define  CAN_F4R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
 #define  CAN_F4R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
 #define  CAN_F4R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
 #define  CAN_F4R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
 #define  CAN_F4R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
 #define  CAN_F4R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
 #define  CAN_F4R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
 #define  CAN_F4R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
 #define  CAN_F4R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
 #define  CAN_F4R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
 #define  CAN_F4R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
 #define  CAN_F4R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
 #define  CAN_F4R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
 #define  CAN_F4R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
 #define  CAN_F4R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
 #define  CAN_F4R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
 #define  CAN_F4R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
 /*******************  Bit definition for CAN_F5R1 register  *******************/
 #define  CAN_F5R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
 #define  CAN_F5R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
 #define  CAN_F5R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
 #define  CAN_F5R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
 #define  CAN_F5R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
 #define  CAN_F5R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
 #define  CAN_F5R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
 #define  CAN_F5R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
 #define  CAN_F5R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
 #define  CAN_F5R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
 #define  CAN_F5R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
 #define  CAN_F5R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
 #define  CAN_F5R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
 #define  CAN_F5R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
 #define  CAN_F5R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
 #define  CAN_F5R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
 #define  CAN_F5R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
 #define  CAN_F5R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
 #define  CAN_F5R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
 #define  CAN_F5R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
 #define  CAN_F5R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
 #define  CAN_F5R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
 #define  CAN_F5R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
 #define  CAN_F5R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
 #define  CAN_F5R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
 #define  CAN_F5R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
 #define  CAN_F5R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
 #define  CAN_F5R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
 #define  CAN_F5R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
 #define  CAN_F5R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
 #define  CAN_F5R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
 #define  CAN_F5R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
 /*******************  Bit definition for CAN_F6R1 register  *******************/
 #define  CAN_F6R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
 #define  CAN_F6R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
 #define  CAN_F6R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
 #define  CAN_F6R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
 #define  CAN_F6R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
 #define  CAN_F6R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
 #define  CAN_F6R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
 #define  CAN_F6R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
 #define  CAN_F6R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
 #define  CAN_F6R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
 #define  CAN_F6R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
 #define  CAN_F6R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
 #define  CAN_F6R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
 #define  CAN_F6R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
 #define  CAN_F6R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
 #define  CAN_F6R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
 #define  CAN_F6R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
 #define  CAN_F6R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
 #define  CAN_F6R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
 #define  CAN_F6R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
 #define  CAN_F6R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
 #define  CAN_F6R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
 #define  CAN_F6R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
 #define  CAN_F6R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
 #define  CAN_F6R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
 #define  CAN_F6R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
 #define  CAN_F6R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
 #define  CAN_F6R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
 #define  CAN_F6R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
 #define  CAN_F6R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
 #define  CAN_F6R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
 #define  CAN_F6R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
 /*******************  Bit definition for CAN_F7R1 register  *******************/
 #define  CAN_F7R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
 #define  CAN_F7R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
 #define  CAN_F7R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
 #define  CAN_F7R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
 #define  CAN_F7R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
 #define  CAN_F7R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
 #define  CAN_F7R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
 #define  CAN_F7R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
 #define  CAN_F7R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
 #define  CAN_F7R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
 #define  CAN_F7R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
 #define  CAN_F7R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
 #define  CAN_F7R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
 #define  CAN_F7R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
 #define  CAN_F7R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
 #define  CAN_F7R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
 #define  CAN_F7R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
 #define  CAN_F7R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
 #define  CAN_F7R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
 #define  CAN_F7R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
 #define  CAN_F7R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
 #define  CAN_F7R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
 #define  CAN_F7R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
 #define  CAN_F7R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
 #define  CAN_F7R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
 #define  CAN_F7R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
 #define  CAN_F7R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
 #define  CAN_F7R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
 #define  CAN_F7R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
 #define  CAN_F7R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
 #define  CAN_F7R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
 #define  CAN_F7R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
 /*******************  Bit definition for CAN_F8R1 register  *******************/
 #define  CAN_F8R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
 #define  CAN_F8R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
 #define  CAN_F8R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
 #define  CAN_F8R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
 #define  CAN_F8R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
 #define  CAN_F8R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
 #define  CAN_F8R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
 #define  CAN_F8R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
 #define  CAN_F8R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
 #define  CAN_F8R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
 #define  CAN_F8R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
 #define  CAN_F8R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
 #define  CAN_F8R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
 #define  CAN_F8R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
 #define  CAN_F8R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
 #define  CAN_F8R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
 #define  CAN_F8R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
 #define  CAN_F8R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
 #define  CAN_F8R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
 #define  CAN_F8R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
 #define  CAN_F8R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
 #define  CAN_F8R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
 #define  CAN_F8R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
 #define  CAN_F8R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
 #define  CAN_F8R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
 #define  CAN_F8R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
 #define  CAN_F8R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
 #define  CAN_F8R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
 #define  CAN_F8R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
 #define  CAN_F8R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
 #define  CAN_F8R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
 #define  CAN_F8R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
 /*******************  Bit definition for CAN_F9R1 register  *******************/
 #define  CAN_F9R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
 #define  CAN_F9R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
 #define  CAN_F9R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
 #define  CAN_F9R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
 #define  CAN_F9R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
 #define  CAN_F9R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
 #define  CAN_F9R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
 #define  CAN_F9R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
 #define  CAN_F9R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
 #define  CAN_F9R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
 #define  CAN_F9R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
 #define  CAN_F9R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
 #define  CAN_F9R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
 #define  CAN_F9R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
 #define  CAN_F9R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
 #define  CAN_F9R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
 #define  CAN_F9R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
 #define  CAN_F9R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
 #define  CAN_F9R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
 #define  CAN_F9R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
 #define  CAN_F9R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
 #define  CAN_F9R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
 #define  CAN_F9R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
 #define  CAN_F9R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
 #define  CAN_F9R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
 #define  CAN_F9R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
 #define  CAN_F9R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
 #define  CAN_F9R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
 #define  CAN_F9R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
 #define  CAN_F9R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
 #define  CAN_F9R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
 #define  CAN_F9R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
 /*******************  Bit definition for CAN_F10R1 register  ******************/
 #define  CAN_F10R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
 #define  CAN_F10R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
 #define  CAN_F10R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
 #define  CAN_F10R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
 #define  CAN_F10R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
 #define  CAN_F10R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
 #define  CAN_F10R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
 #define  CAN_F10R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
 #define  CAN_F10R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
 #define  CAN_F10R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
 #define  CAN_F10R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
 #define  CAN_F10R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
 #define  CAN_F10R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
 #define  CAN_F10R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
 #define  CAN_F10R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
 #define  CAN_F10R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
 #define  CAN_F10R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
 #define  CAN_F10R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
 #define  CAN_F10R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
 #define  CAN_F10R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
 #define  CAN_F10R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
 #define  CAN_F10R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
 #define  CAN_F10R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
 #define  CAN_F10R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
 #define  CAN_F10R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
 #define  CAN_F10R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
 #define  CAN_F10R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
 #define  CAN_F10R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
 #define  CAN_F10R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
 #define  CAN_F10R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
 #define  CAN_F10R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
 #define  CAN_F10R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
 /*******************  Bit definition for CAN_F11R1 register  ******************/
 #define  CAN_F11R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
 #define  CAN_F11R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
 #define  CAN_F11R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
 #define  CAN_F11R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
 #define  CAN_F11R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
 #define  CAN_F11R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
 #define  CAN_F11R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
 #define  CAN_F11R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
 #define  CAN_F11R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
 #define  CAN_F11R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
 #define  CAN_F11R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
 #define  CAN_F11R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
 #define  CAN_F11R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
 #define  CAN_F11R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
 #define  CAN_F11R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
 #define  CAN_F11R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
 #define  CAN_F11R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
 #define  CAN_F11R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
 #define  CAN_F11R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
 #define  CAN_F11R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
 #define  CAN_F11R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
 #define  CAN_F11R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
 #define  CAN_F11R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
 #define  CAN_F11R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
 #define  CAN_F11R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
 #define  CAN_F11R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
 #define  CAN_F11R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
 #define  CAN_F11R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
 #define  CAN_F11R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
 #define  CAN_F11R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
 #define  CAN_F11R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
 #define  CAN_F11R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
 /*******************  Bit definition for CAN_F12R1 register  ******************/
 #define  CAN_F12R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
 #define  CAN_F12R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
 #define  CAN_F12R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
 #define  CAN_F12R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
 #define  CAN_F12R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
 #define  CAN_F12R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
 #define  CAN_F12R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
 #define  CAN_F12R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
 #define  CAN_F12R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
 #define  CAN_F12R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
 #define  CAN_F12R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
 #define  CAN_F12R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
 #define  CAN_F12R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
 #define  CAN_F12R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
 #define  CAN_F12R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
 #define  CAN_F12R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
 #define  CAN_F12R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
 #define  CAN_F12R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
 #define  CAN_F12R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
 #define  CAN_F12R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
 #define  CAN_F12R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
 #define  CAN_F12R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
 #define  CAN_F12R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
 #define  CAN_F12R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
 #define  CAN_F12R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
 #define  CAN_F12R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
 #define  CAN_F12R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
 #define  CAN_F12R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
 #define  CAN_F12R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
 #define  CAN_F12R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
 #define  CAN_F12R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
 #define  CAN_F12R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
 /*******************  Bit definition for CAN_F13R1 register  ******************/
 #define  CAN_F13R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
 #define  CAN_F13R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
 #define  CAN_F13R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
 #define  CAN_F13R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
 #define  CAN_F13R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
 #define  CAN_F13R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
 #define  CAN_F13R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
 #define  CAN_F13R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
 #define  CAN_F13R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
 #define  CAN_F13R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
 #define  CAN_F13R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
 #define  CAN_F13R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
 #define  CAN_F13R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
 #define  CAN_F13R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
 #define  CAN_F13R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
 #define  CAN_F13R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
 #define  CAN_F13R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
 #define  CAN_F13R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
 #define  CAN_F13R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
 #define  CAN_F13R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
 #define  CAN_F13R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
 #define  CAN_F13R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
 #define  CAN_F13R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
 #define  CAN_F13R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
 #define  CAN_F13R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
 #define  CAN_F13R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
 #define  CAN_F13R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
 #define  CAN_F13R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
 #define  CAN_F13R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
 #define  CAN_F13R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
 #define  CAN_F13R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
 #define  CAN_F13R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
 /*******************  Bit definition for CAN_F0R2 register  *******************/
 #define  CAN_F0R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
 #define  CAN_F0R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
 #define  CAN_F0R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
 #define  CAN_F0R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
 #define  CAN_F0R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
 #define  CAN_F0R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
 #define  CAN_F0R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
 #define  CAN_F0R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
 #define  CAN_F0R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
 #define  CAN_F0R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
 #define  CAN_F0R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
 #define  CAN_F0R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
 #define  CAN_F0R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
 #define  CAN_F0R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
 #define  CAN_F0R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
 #define  CAN_F0R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
 #define  CAN_F0R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
 #define  CAN_F0R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
 #define  CAN_F0R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
 #define  CAN_F0R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
 #define  CAN_F0R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
 #define  CAN_F0R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
 #define  CAN_F0R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
 #define  CAN_F0R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
 #define  CAN_F0R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
 #define  CAN_F0R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
 #define  CAN_F0R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
 #define  CAN_F0R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
 #define  CAN_F0R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
 #define  CAN_F0R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
 #define  CAN_F0R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
 #define  CAN_F0R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
 /*******************  Bit definition for CAN_F1R2 register  *******************/
 #define  CAN_F1R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
 #define  CAN_F1R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
 #define  CAN_F1R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
 #define  CAN_F1R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
 #define  CAN_F1R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
 #define  CAN_F1R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
 #define  CAN_F1R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
 #define  CAN_F1R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
 #define  CAN_F1R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
 #define  CAN_F1R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
 #define  CAN_F1R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
 #define  CAN_F1R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
 #define  CAN_F1R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
 #define  CAN_F1R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
 #define  CAN_F1R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
 #define  CAN_F1R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
 #define  CAN_F1R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
 #define  CAN_F1R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
 #define  CAN_F1R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
 #define  CAN_F1R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
 #define  CAN_F1R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
 #define  CAN_F1R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
 #define  CAN_F1R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
 #define  CAN_F1R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
 #define  CAN_F1R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
 #define  CAN_F1R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
 #define  CAN_F1R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
 #define  CAN_F1R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
 #define  CAN_F1R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
 #define  CAN_F1R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
 #define  CAN_F1R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
 #define  CAN_F1R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
 /*******************  Bit definition for CAN_F2R2 register  *******************/
 #define  CAN_F2R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
 #define  CAN_F2R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
 #define  CAN_F2R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
 #define  CAN_F2R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
 #define  CAN_F2R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
 #define  CAN_F2R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
 #define  CAN_F2R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
 #define  CAN_F2R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
 #define  CAN_F2R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
 #define  CAN_F2R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
 #define  CAN_F2R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
 #define  CAN_F2R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
 #define  CAN_F2R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
 #define  CAN_F2R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
 #define  CAN_F2R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
 #define  CAN_F2R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
 #define  CAN_F2R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
 #define  CAN_F2R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
 #define  CAN_F2R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
 #define  CAN_F2R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
 #define  CAN_F2R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
 #define  CAN_F2R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
 #define  CAN_F2R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
 #define  CAN_F2R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
 #define  CAN_F2R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
 #define  CAN_F2R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
 #define  CAN_F2R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
 #define  CAN_F2R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
 #define  CAN_F2R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
 #define  CAN_F2R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
 #define  CAN_F2R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
 #define  CAN_F2R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
 /*******************  Bit definition for CAN_F3R2 register  *******************/
 #define  CAN_F3R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
 #define  CAN_F3R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
 #define  CAN_F3R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
 #define  CAN_F3R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
 #define  CAN_F3R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
 #define  CAN_F3R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
 #define  CAN_F3R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
 #define  CAN_F3R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
 #define  CAN_F3R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
 #define  CAN_F3R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
 #define  CAN_F3R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
 #define  CAN_F3R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
 #define  CAN_F3R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
 #define  CAN_F3R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
 #define  CAN_F3R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
 #define  CAN_F3R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
 #define  CAN_F3R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
 #define  CAN_F3R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
 #define  CAN_F3R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
 #define  CAN_F3R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
 #define  CAN_F3R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
 #define  CAN_F3R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
 #define  CAN_F3R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
 #define  CAN_F3R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
 #define  CAN_F3R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
 #define  CAN_F3R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
 #define  CAN_F3R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
 #define  CAN_F3R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
 #define  CAN_F3R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
 #define  CAN_F3R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
 #define  CAN_F3R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
 #define  CAN_F3R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
 /*******************  Bit definition for CAN_F4R2 register  *******************/
 #define  CAN_F4R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
 #define  CAN_F4R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
 #define  CAN_F4R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
 #define  CAN_F4R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
 #define  CAN_F4R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
 #define  CAN_F4R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
 #define  CAN_F4R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
 #define  CAN_F4R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
 #define  CAN_F4R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
 #define  CAN_F4R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
 #define  CAN_F4R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
 #define  CAN_F4R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
 #define  CAN_F4R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
 #define  CAN_F4R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
 #define  CAN_F4R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
 #define  CAN_F4R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
 #define  CAN_F4R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
 #define  CAN_F4R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
 #define  CAN_F4R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
 #define  CAN_F4R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
 #define  CAN_F4R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
 #define  CAN_F4R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
 #define  CAN_F4R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
 #define  CAN_F4R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
 #define  CAN_F4R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
 #define  CAN_F4R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
 #define  CAN_F4R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
 #define  CAN_F4R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
 #define  CAN_F4R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
 #define  CAN_F4R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
 #define  CAN_F4R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
 #define  CAN_F4R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
 /*******************  Bit definition for CAN_F5R2 register  *******************/
 #define  CAN_F5R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
 #define  CAN_F5R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
 #define  CAN_F5R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
 #define  CAN_F5R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
 #define  CAN_F5R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
 #define  CAN_F5R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
 #define  CAN_F5R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
 #define  CAN_F5R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
 #define  CAN_F5R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
 #define  CAN_F5R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
 #define  CAN_F5R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
 #define  CAN_F5R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
 #define  CAN_F5R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
 #define  CAN_F5R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
 #define  CAN_F5R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
 #define  CAN_F5R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
 #define  CAN_F5R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
 #define  CAN_F5R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
 #define  CAN_F5R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
 #define  CAN_F5R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
 #define  CAN_F5R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
 #define  CAN_F5R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
 #define  CAN_F5R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
 #define  CAN_F5R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
 #define  CAN_F5R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
 #define  CAN_F5R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
 #define  CAN_F5R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
 #define  CAN_F5R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
 #define  CAN_F5R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
 #define  CAN_F5R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
 #define  CAN_F5R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
 #define  CAN_F5R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
 /*******************  Bit definition for CAN_F6R2 register  *******************/
 #define  CAN_F6R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
 #define  CAN_F6R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
 #define  CAN_F6R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
 #define  CAN_F6R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
 #define  CAN_F6R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
 #define  CAN_F6R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
 #define  CAN_F6R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
 #define  CAN_F6R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
 #define  CAN_F6R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
 #define  CAN_F6R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
 #define  CAN_F6R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
 #define  CAN_F6R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
 #define  CAN_F6R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
 #define  CAN_F6R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
 #define  CAN_F6R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
 #define  CAN_F6R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
 #define  CAN_F6R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
 #define  CAN_F6R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
 #define  CAN_F6R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
 #define  CAN_F6R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
 #define  CAN_F6R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
 #define  CAN_F6R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
 #define  CAN_F6R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
 #define  CAN_F6R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
 #define  CAN_F6R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
 #define  CAN_F6R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
 #define  CAN_F6R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
 #define  CAN_F6R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
 #define  CAN_F6R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
 #define  CAN_F6R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
 #define  CAN_F6R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
 #define  CAN_F6R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
 /*******************  Bit definition for CAN_F7R2 register  *******************/
 #define  CAN_F7R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
 #define  CAN_F7R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
 #define  CAN_F7R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
 #define  CAN_F7R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
 #define  CAN_F7R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
 #define  CAN_F7R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
 #define  CAN_F7R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
 #define  CAN_F7R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
 #define  CAN_F7R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
 #define  CAN_F7R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
 #define  CAN_F7R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
 #define  CAN_F7R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
 #define  CAN_F7R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
 #define  CAN_F7R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
 #define  CAN_F7R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
 #define  CAN_F7R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
 #define  CAN_F7R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
 #define  CAN_F7R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
 #define  CAN_F7R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
 #define  CAN_F7R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
 #define  CAN_F7R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
 #define  CAN_F7R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
 #define  CAN_F7R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
 #define  CAN_F7R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
 #define  CAN_F7R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
 #define  CAN_F7R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
 #define  CAN_F7R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
 #define  CAN_F7R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
 #define  CAN_F7R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
 #define  CAN_F7R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
 #define  CAN_F7R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
 #define  CAN_F7R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
 /*******************  Bit definition for CAN_F8R2 register  *******************/
 #define  CAN_F8R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
 #define  CAN_F8R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
 #define  CAN_F8R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
 #define  CAN_F8R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
 #define  CAN_F8R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
 #define  CAN_F8R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
 #define  CAN_F8R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
 #define  CAN_F8R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
 #define  CAN_F8R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
 #define  CAN_F8R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
 #define  CAN_F8R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
 #define  CAN_F8R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
 #define  CAN_F8R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
 #define  CAN_F8R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
 #define  CAN_F8R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
 #define  CAN_F8R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
 #define  CAN_F8R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
 #define  CAN_F8R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
 #define  CAN_F8R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
 #define  CAN_F8R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
 #define  CAN_F8R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
 #define  CAN_F8R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
 #define  CAN_F8R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
 #define  CAN_F8R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
 #define  CAN_F8R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
 #define  CAN_F8R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
 #define  CAN_F8R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
 #define  CAN_F8R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
 #define  CAN_F8R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
 #define  CAN_F8R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
 #define  CAN_F8R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
 #define  CAN_F8R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
 /*******************  Bit definition for CAN_F9R2 register  *******************/
 #define  CAN_F9R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
 #define  CAN_F9R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
 #define  CAN_F9R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
 #define  CAN_F9R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
 #define  CAN_F9R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
 #define  CAN_F9R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
 #define  CAN_F9R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
 #define  CAN_F9R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
 #define  CAN_F9R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
 #define  CAN_F9R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
 #define  CAN_F9R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
 #define  CAN_F9R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
 #define  CAN_F9R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
 #define  CAN_F9R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
 #define  CAN_F9R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
 #define  CAN_F9R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
 #define  CAN_F9R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
 #define  CAN_F9R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
 #define  CAN_F9R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
 #define  CAN_F9R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
 #define  CAN_F9R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
 #define  CAN_F9R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
 #define  CAN_F9R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
 #define  CAN_F9R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
 #define  CAN_F9R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
 #define  CAN_F9R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
 #define  CAN_F9R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
 #define  CAN_F9R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
 #define  CAN_F9R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
 #define  CAN_F9R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
 #define  CAN_F9R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
 #define  CAN_F9R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
 /*******************  Bit definition for CAN_F10R2 register  ******************/
 #define  CAN_F10R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
 #define  CAN_F10R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
 #define  CAN_F10R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
 #define  CAN_F10R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
 #define  CAN_F10R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
 #define  CAN_F10R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
 #define  CAN_F10R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
 #define  CAN_F10R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
 #define  CAN_F10R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
 #define  CAN_F10R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
 #define  CAN_F10R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
 #define  CAN_F10R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
 #define  CAN_F10R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
 #define  CAN_F10R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
 #define  CAN_F10R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
 #define  CAN_F10R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
 #define  CAN_F10R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
 #define  CAN_F10R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
 #define  CAN_F10R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
 #define  CAN_F10R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
 #define  CAN_F10R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
 #define  CAN_F10R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
 #define  CAN_F10R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
 #define  CAN_F10R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
 #define  CAN_F10R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
 #define  CAN_F10R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
 #define  CAN_F10R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
 #define  CAN_F10R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
 #define  CAN_F10R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
 #define  CAN_F10R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
 #define  CAN_F10R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
 #define  CAN_F10R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
 /*******************  Bit definition for CAN_F11R2 register  ******************/
 #define  CAN_F11R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
 #define  CAN_F11R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
 #define  CAN_F11R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
 #define  CAN_F11R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
 #define  CAN_F11R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
 #define  CAN_F11R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
 #define  CAN_F11R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
 #define  CAN_F11R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
 #define  CAN_F11R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
 #define  CAN_F11R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
 #define  CAN_F11R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
 #define  CAN_F11R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
 #define  CAN_F11R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
 #define  CAN_F11R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
 #define  CAN_F11R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
 #define  CAN_F11R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
 #define  CAN_F11R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
 #define  CAN_F11R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
 #define  CAN_F11R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
 #define  CAN_F11R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
 #define  CAN_F11R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
 #define  CAN_F11R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
 #define  CAN_F11R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
 #define  CAN_F11R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
 #define  CAN_F11R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
 #define  CAN_F11R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
 #define  CAN_F11R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
 #define  CAN_F11R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
 #define  CAN_F11R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
 #define  CAN_F11R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
 #define  CAN_F11R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
 #define  CAN_F11R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
 /*******************  Bit definition for CAN_F12R2 register  ******************/
 #define  CAN_F12R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
 #define  CAN_F12R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
 #define  CAN_F12R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
 #define  CAN_F12R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
 #define  CAN_F12R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
 #define  CAN_F12R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
 #define  CAN_F12R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
 #define  CAN_F12R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
 #define  CAN_F12R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
 #define  CAN_F12R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
 #define  CAN_F12R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
 #define  CAN_F12R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
 #define  CAN_F12R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
 #define  CAN_F12R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
 #define  CAN_F12R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
 #define  CAN_F12R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
 #define  CAN_F12R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
 #define  CAN_F12R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
 #define  CAN_F12R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
 #define  CAN_F12R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
 #define  CAN_F12R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
 #define  CAN_F12R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
 #define  CAN_F12R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
 #define  CAN_F12R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
 #define  CAN_F12R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
 #define  CAN_F12R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
 #define  CAN_F12R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
 #define  CAN_F12R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
 #define  CAN_F12R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
 #define  CAN_F12R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
 #define  CAN_F12R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
 #define  CAN_F12R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
 /*******************  Bit definition for CAN_F13R2 register  ******************/
 #define  CAN_F13R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
 #define  CAN_F13R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
 #define  CAN_F13R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
 #define  CAN_F13R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
 #define  CAN_F13R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
 #define  CAN_F13R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
 #define  CAN_F13R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
 #define  CAN_F13R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
 #define  CAN_F13R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
 #define  CAN_F13R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
 #define  CAN_F13R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
 #define  CAN_F13R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
 #define  CAN_F13R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
 #define  CAN_F13R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
 #define  CAN_F13R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
 #define  CAN_F13R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
 #define  CAN_F13R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
 #define  CAN_F13R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
 #define  CAN_F13R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
 #define  CAN_F13R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
 #define  CAN_F13R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
 #define  CAN_F13R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
 #define  CAN_F13R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
 #define  CAN_F13R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
 #define  CAN_F13R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
 #define  CAN_F13R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
 #define  CAN_F13R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
 #define  CAN_F13R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
 #define  CAN_F13R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
 #define  CAN_F13R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
 #define  CAN_F13R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
 #define  CAN_F13R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
 /******************************************************************************/
 /*                                                                            */
 /*                                 HDMI-CEC (CEC)                             */
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for CEC_CR register  *********************/
 #define  CEC_CR_CECEN                        ((uint32_t)0x00000001)       /*!< CEC Enable                         */
 #define  CEC_CR_TXSOM                        ((uint32_t)0x00000002)       /*!< CEC Tx Start Of Message            */
 #define  CEC_CR_TXEOM                        ((uint32_t)0x00000004)       /*!< CEC Tx End Of Message              */
 /*******************  Bit definition for CEC_CFGR register  *******************/
 #define  CEC_CFGR_SFT                        ((uint32_t)0x00000007)       /*!< CEC Signal Free Time               */
 #define  CEC_CFGR_RXTOL                      ((uint32_t)0x00000008)       /*!< CEC Tolerance                      */
 #define  CEC_CFGR_BRESTP                     ((uint32_t)0x00000010)       /*!< CEC Rx Stop                        */
 #define  CEC_CFGR_BREGEN                     ((uint32_t)0x00000020)       /*!< CEC Bit Rising Error generation    */
 #define  CEC_CFGR_LREGEN                     ((uint32_t)0x00000040)       /*!< CEC Long Period Error generation   */
 #define  CEC_CFGR_BRDNOGEN                   ((uint32_t)0x00000080)       /*!< CEC Broadcast no Error generation  */
 #define  CEC_CFGR_SFTOPT                     ((uint32_t)0x00000100)       /*!< CEC Signal Free Time optional      */
 #define  CEC_CFGR_OAR                        ((uint32_t)0x7FFF0000)       /*!< CEC Own Address                    */
 #define  CEC_CFGR_LSTN                       ((uint32_t)0x80000000)       /*!< CEC Listen mode                    */
 /*******************  Bit definition for CEC_TXDR register  *******************/
 #define  CEC_TXDR_TXD                        ((uint32_t)0x000000FF)       /*!< CEC Tx Data                        */
 /*******************  Bit definition for CEC_RXDR register  *******************/
 #define  CEC_TXDR_RXD                        ((uint32_t)0x000000FF)       /*!< CEC Rx Data                        */
 /*******************  Bit definition for CEC_ISR register  ********************/
 #define  CEC_ISR_RXBR                        ((uint32_t)0x00000001)       /*!< CEC Rx-Byte Received                   */
 #define  CEC_ISR_RXEND                       ((uint32_t)0x00000002)       /*!< CEC End Of Reception                   */
 #define  CEC_ISR_RXOVR                       ((uint32_t)0x00000004)       /*!< CEC Rx-Overrun                         */
 #define  CEC_ISR_BRE                         ((uint32_t)0x00000008)       /*!< CEC Rx Bit Rising Error                */
 #define  CEC_ISR_SBPE                        ((uint32_t)0x00000010)       /*!< CEC Rx Short Bit period Error          */
 #define  CEC_ISR_LBPE                        ((uint32_t)0x00000020)       /*!< CEC Rx Long Bit period Error           */
 #define  CEC_ISR_RXACKE                      ((uint32_t)0x00000040)       /*!< CEC Rx Missing Acknowledge             */
 #define  CEC_ISR_ARBLST                      ((uint32_t)0x00000080)       /*!< CEC Arbitration Lost                   */
 #define  CEC_ISR_TXBR                        ((uint32_t)0x00000100)       /*!< CEC Tx Byte Request                    */
 #define  CEC_ISR_TXEND                       ((uint32_t)0x00000200)       /*!< CEC End of Transmission                */
 #define  CEC_ISR_TXUDR                       ((uint32_t)0x00000400)       /*!< CEC Tx-Buffer Underrun                 */
 #define  CEC_ISR_TXERR                       ((uint32_t)0x00000800)       /*!< CEC Tx-Error                           */
 #define  CEC_ISR_TXACKE                      ((uint32_t)0x00001000)       /*!< CEC Tx Missing Acknowledge             */
 /*******************  Bit definition for CEC_IER register  ********************/
 #define  CEC_IER_RXBRIE                      ((uint32_t)0x00000001)       /*!< CEC Rx-Byte Received IT Enable         */
 #define  CEC_IER_RXENDIE                     ((uint32_t)0x00000002)       /*!< CEC End Of Reception IT Enable         */
 #define  CEC_IER_RXOVRIE                     ((uint32_t)0x00000004)       /*!< CEC Rx-Overrun IT Enable               */
 #define  CEC_IER_BREIEIE                     ((uint32_t)0x00000008)       /*!< CEC Rx Bit Rising Error IT Enable      */
 #define  CEC_IER_SBPEIE                      ((uint32_t)0x00000010)       /*!< CEC Rx Short Bit period Error IT Enable*/
 #define  CEC_IER_LBPEIE                      ((uint32_t)0x00000020)       /*!< CEC Rx Long Bit period Error IT Enable */
 #define  CEC_IER_RXACKEIE                    ((uint32_t)0x00000040)       /*!< CEC Rx Missing Acknowledge IT Enable   */
 #define  CEC_IER_ARBLSTIE                    ((uint32_t)0x00000080)       /*!< CEC Arbitration Lost IT Enable         */
 #define  CEC_IER_TXBRIE                      ((uint32_t)0x00000100)       /*!< CEC Tx Byte Request  IT Enable         */
 #define  CEC_IER_TXENDIE                     ((uint32_t)0x00000200)       /*!< CEC End of Transmission IT Enable      */
 #define  CEC_IER_TXUDRIE                     ((uint32_t)0x00000400)       /*!< CEC Tx-Buffer Underrun IT Enable       */
 #define  CEC_IER_TXERRIE                     ((uint32_t)0x00000800)       /*!< CEC Tx-Error IT Enable                 */
 #define  CEC_IER_TXACKEIE                    ((uint32_t)0x00001000)       /*!< CEC Tx Missing Acknowledge IT Enable   */
 /******************************************************************************/
 /*                                                                            */
 /*                      Analog Comparators (COMP)                             */
 /*                                                                            */
 /******************************************************************************/
 /***********************  Bit definition for COMP_CSR register  ***************/
 /* COMP1 bits definition */
 #define COMP_CSR_COMP1EN               ((uint32_t)0x00000001) /*!< COMP1 enable */
 #define COMP_CSR_COMP1SW1              ((uint32_t)0x00000002) /*!< SW1 switch control */
 #define COMP_CSR_COMP1MODE             ((uint32_t)0x0000000C) /*!< COMP1 power mode */
 #define COMP_CSR_COMP1MODE_0           ((uint32_t)0x00000004) /*!< COMP1 power mode bit 0 */
 #define COMP_CSR_COMP1MODE_1           ((uint32_t)0x00000008) /*!< COMP1 power mode bit 1 */
 #define COMP_CSR_COMP1INSEL            ((uint32_t)0x00000070) /*!< COMP1 inverting input select */
 #define COMP_CSR_COMP1INSEL_0          ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
 #define COMP_CSR_COMP1INSEL_1          ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
 #define COMP_CSR_COMP1INSEL_2          ((uint32_t)0x00000040) /*!< COMP1 inverting input select bit 2 */
 #define COMP_CSR_COMP1OUTSEL           ((uint32_t)0x00000700) /*!< COMP1 output select */
 #define COMP_CSR_COMP1OUTSEL_0         ((uint32_t)0x00000100) /*!< COMP1 output select bit 0 */
 #define COMP_CSR_COMP1OUTSEL_1         ((uint32_t)0x00000200) /*!< COMP1 output select bit 1 */
 #define COMP_CSR_COMP1OUTSEL_2         ((uint32_t)0x00000400) /*!< COMP1 output select bit 2 */
 #define COMP_CSR_COMP1POL              ((uint32_t)0x00000800) /*!< COMP1 output polarity */
 #define COMP_CSR_COMP1HYST             ((uint32_t)0x00003000) /*!< COMP1 hysteresis */
 #define COMP_CSR_COMP1HYST_0           ((uint32_t)0x00001000) /*!< COMP1 hysteresis bit 0 */
 #define COMP_CSR_COMP1HYST_1           ((uint32_t)0x00002000) /*!< COMP1 hysteresis bit 1 */
 #define COMP_CSR_COMP1OUT              ((uint32_t)0x00004000) /*!< COMP1 output level */
 #define COMP_CSR_COMP1LOCK             ((uint32_t)0x00008000) /*!< COMP1 lock */
 /* COMP2 bits definition */
 #define COMP_CSR_COMP2EN               ((uint32_t)0x00010000) /*!< COMP2 enable */
 #define COMP_CSR_COMP2MODE             ((uint32_t)0x000C0000) /*!< COMP2 power mode */
 #define COMP_CSR_COMP2MODE_0           ((uint32_t)0x00040000) /*!< COMP2 power mode bit 0 */
 #define COMP_CSR_COMP2MODE_1           ((uint32_t)0x00080000) /*!< COMP2 power mode bit 1 */
 #define COMP_CSR_COMP2INSEL            ((uint32_t)0x00700000) /*!< COMP2 inverting input select */
 #define COMP_CSR_COMP2INSEL_0          ((uint32_t)0x00100000) /*!< COMP2 inverting input select bit 0 */
 #define COMP_CSR_COMP2INSEL_1          ((uint32_t)0x00200000) /*!< COMP2 inverting input select bit 1 */
 #define COMP_CSR_COMP2INSEL_2          ((uint32_t)0x00400000) /*!< COMP2 inverting input select bit 2 */
 #define COMP_CSR_WNDWEN                ((uint32_t)0x00800000) /*!< Comparators window mode enable */
 #define COMP_CSR_COMP2OUTSEL           ((uint32_t)0x07000000) /*!< COMP2 output select */
 #define COMP_CSR_COMP2OUTSEL_0         ((uint32_t)0x01000000) /*!< COMP2 output select bit 0 */
 #define COMP_CSR_COMP2OUTSEL_1         ((uint32_t)0x02000000) /*!< COMP2 output select bit 1 */
 #define COMP_CSR_COMP2OUTSEL_2         ((uint32_t)0x04000000) /*!< COMP2 output select bit 2 */
 #define COMP_CSR_COMP2POL              ((uint32_t)0x08000000) /*!< COMP2 output polarity */
 #define COMP_CSR_COMP2HYST             ((uint32_t)0x30000000) /*!< COMP2 hysteresis */
 #define COMP_CSR_COMP2HYST_0           ((uint32_t)0x10000000) /*!< COMP2 hysteresis bit 0 */
 #define COMP_CSR_COMP2HYST_1           ((uint32_t)0x20000000) /*!< COMP2 hysteresis bit 1 */
 #define COMP_CSR_COMP2OUT              ((uint32_t)0x40000000) /*!< COMP2 output level */
 #define COMP_CSR_COMP2LOCK             ((uint32_t)0x80000000) /*!< COMP2 lock */
 /******************************************************************************/
 /*                                                                            */
 /*                       CRC calculation unit (CRC)                           */
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for CRC_DR register  *********************/
 #define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
 /*******************  Bit definition for CRC_IDR register  ********************/
 #define  CRC_IDR_IDR                         ((uint8_t)0xFF)        /*!< General-purpose 8-bit data register bits */
 /********************  Bit definition for CRC_CR register  ********************/
 #define  CRC_CR_RESET                        ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
 #define  CRC_CR_POLSIZE                      ((uint32_t)0x00000018) /*!< Polynomial size bits (only for STM32F072 devices)*/
 #define  CRC_CR_POLSIZE_0                    ((uint32_t)0x00000008) /*!< Polynomial size bit 0 (only for STM32F072 devices) */
 #define  CRC_CR_POLSIZE_1                    ((uint32_t)0x00000010) /*!< Polynomial size bit 1 (only for STM32F072 devices) */
 #define  CRC_CR_REV_IN                       ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
 #define  CRC_CR_REV_IN_0                     ((uint32_t)0x00000020) /*!< REV_IN Bit 0 */
 #define  CRC_CR_REV_IN_1                     ((uint32_t)0x00000040) /*!< REV_IN Bit 1 */
 #define  CRC_CR_REV_OUT                      ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
 /*******************  Bit definition for CRC_INIT register  *******************/
 #define  CRC_INIT_INIT                       ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
 /*******************  Bit definition for CRC_POL register  ********************/
 #define  CRC_POL_POL                         ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial (only for STM32F072 devices) */
 /******************************************************************************/
 /*                                                                            */
 /*                          CRS Clock Recovery System                         */
 /*                   (Available only for STM32F072 devices)                */
 /******************************************************************************/
 /*******************  Bit definition for CRS_CR register  *********************/
 #define  CRS_CR_SYNCOKIE                     ((uint32_t)0x00000001) /* SYNC event OK interrupt enable        */
 #define  CRS_CR_SYNCWARNIE                   ((uint32_t)0x00000002) /* SYNC warning interrupt enable         */
 #define  CRS_CR_ERRIE                        ((uint32_t)0x00000004) /* SYNC error interrupt enable           */
 #define  CRS_CR_ESYNCIE                      ((uint32_t)0x00000008) /* Expected SYNC(ESYNCF) interrupt Enable*/
 #define  CRS_CR_CEN                          ((uint32_t)0x00000020) /* Frequency error counter enable        */
 #define  CRS_CR_AUTOTRIMEN                   ((uint32_t)0x00000040) /* Automatic trimming enable             */
 #define  CRS_CR_SWSYNC                       ((uint32_t)0x00000080) /* A Software SYNC event is generated    */
 #define  CRS_CR_TRIM                         ((uint32_t)0x00003F00) /* HSI48 oscillator smooth trimming      */
 /*******************  Bit definition for CRS_CFGR register  *********************/
 #define  CRS_CFGR_RELOAD                     ((uint32_t)0x0000FFFF) /* Counter reload value               */
 #define  CRS_CFGR_FELIM                      ((uint32_t)0x00FF0000) /* Frequency error limit              */
 #define  CRS_CFGR_SYNCDIV                    ((uint32_t)0x07000000) /* SYNC divider                       */
 #define  CRS_CFGR_SYNCDIV_0                  ((uint32_t)0x01000000) /* Bit 0                              */
 #define  CRS_CFGR_SYNCDIV_1                  ((uint32_t)0x02000000) /* Bit 1                              */
 #define  CRS_CFGR_SYNCDIV_2                  ((uint32_t)0x04000000) /* Bit 2                              */
 #define  CRS_CFGR_SYNCSRC                    ((uint32_t)0x30000000) /* SYNC signal source selection       */
 #define  CRS_CFGR_SYNCSRC_0                  ((uint32_t)0x10000000) /* Bit 0                              */
 #define  CRS_CFGR_SYNCSRC_1                  ((uint32_t)0x20000000) /* Bit 1                              */
 #define  CRS_CFGR_SYNCPOL                    ((uint32_t)0x80000000) /* SYNC polarity selection            */
 /*******************  Bit definition for CRS_ISR register  *********************/
 #define  CRS_ISR_SYNCOKF                     ((uint32_t)0x00000001) /* SYNC event OK flag             */
 #define  CRS_ISR_SYNCWARNF                   ((uint32_t)0x00000002) /* SYNC warning                   */
 #define  CRS_ISR_ERRF                        ((uint32_t)0x00000004) /* SYNC error flag                */
 #define  CRS_ISR_ESYNCF                      ((uint32_t)0x00000008) /* Expected SYNC flag             */
 #define  CRS_ISR_SYNCERR                     ((uint32_t)0x00000100) /* SYNC error                     */
 #define  CRS_ISR_SYNCMISS                    ((uint32_t)0x00000200) /* SYNC missed                    */
 #define  CRS_ISR_TRIMOVF                     ((uint32_t)0x00000400) /* Trimming overflow or underflow */
 #define  CRS_ISR_FEDIR                       ((uint32_t)0x00008000) /* Frequency error direction      */
 #define  CRS_ISR_FECAP                       ((uint32_t)0xFFFF0000) /* Frequency error capture        */
 /*******************  Bit definition for CRS_ICR register  *********************/
 #define  CRS_ICR_SYNCOKC                     ((uint32_t)0x00000001) /* SYNC event OK clear flag     */
 #define  CRS_ICR_SYNCWARNC                   ((uint32_t)0x00000002) /* SYNC warning clear flag      */
 #define  CRS_ICR_ERRC                        ((uint32_t)0x00000004) /* Error clear flag        */
 #define  CRS_ICR_ESYNCC                      ((uint32_t)0x00000008) /* Expected SYNC clear flag     */
 /******************************************************************************/
 /*                                                                            */
 /*                 Digital to Analog Converter (DAC)                          */
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for DAC_CR register  ********************/
 #define  DAC_CR_EN1                          ((uint32_t)0x00000001)        /*!< DAC channel1 enable */
 #define  DAC_CR_BOFF1                        ((uint32_t)0x00000002)        /*!< DAC channel1 output buffer disable */
 #define  DAC_CR_TEN1                         ((uint32_t)0x00000004)        /*!< DAC channel1 Trigger enable */
 #define  DAC_CR_TSEL1                        ((uint32_t)0x00000038)        /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
 #define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        /*!< Bit 0 */
 #define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        /*!< Bit 1 */
 #define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        /*!< Bit 2 */
 #define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0)        /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable)(only for STM32F072 devices) */
 #define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040)        /*!< Bit 0 */
 #define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080)        /*!< Bit 1 */
 #define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00)        /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) (only for STM32F072 devices) */
 #define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100)        /*!< Bit 0 */
 #define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200)        /*!< Bit 1 */
 #define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400)        /*!< Bit 2 */
 #define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800)        /*!< Bit 3 */
 #define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        /*!< DAC channel1 DMA enable */
 #define  DAC_CR_DMAUDRIE1                    ((uint32_t)0x00002000)        /*!<DAC channel1 DMA Underrun Interrupt enable */
 #define  DAC_CR_EN2                          ((uint32_t)0x00010000)        /*!< DAC channel2 enable */
 #define  DAC_CR_BOFF2                        ((uint32_t)0x00020000)        /*!< DAC channel2 output buffer disable */
 #define  DAC_CR_TEN2                         ((uint32_t)0x00040000)        /*!< DAC channel2 Trigger enable */
 #define  DAC_CR_TSEL2                        ((uint32_t)0x00380000)        /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
 #define  DAC_CR_TSEL2_0                      ((uint32_t)0x00080000)        /*!< Bit 0 */
 #define  DAC_CR_TSEL2_1                      ((uint32_t)0x00100000)        /*!< Bit 1 */
 #define  DAC_CR_TSEL2_2                      ((uint32_t)0x00200000)        /*!< Bit 2 */
 #define  DAC_CR_WAVE2                        ((uint32_t)0x00C00000)        /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
 #define  DAC_CR_WAVE2_0                      ((uint32_t)0x00400000)        /*!< Bit 0 */
 #define  DAC_CR_WAVE2_1                      ((uint32_t)0x00800000)        /*!< Bit 1 */
 #define  DAC_CR_MAMP2                        ((uint32_t)0x0F000000)        /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
 #define  DAC_CR_MAMP2_0                      ((uint32_t)0x01000000)        /*!< Bit 0 */
 #define  DAC_CR_MAMP2_1                      ((uint32_t)0x02000000)        /*!< Bit 1 */
 #define  DAC_CR_MAMP2_2                      ((uint32_t)0x04000000)        /*!< Bit 2 */
 #define  DAC_CR_MAMP2_3                      ((uint32_t)0x08000000)        /*!< Bit 3 */
 #define  DAC_CR_DMAEN2                       ((uint32_t)0x10000000)        /*!< DAC channel2 DMA enabled */
 #define  DAC_CR_DMAUDRIE2                    ((uint32_t)0x20000000)        /*!<DAC channel2 DMA Underrun Interrupt enable */
 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
 #define  DAC_SWTRIGR_SWTRIG1                 ((uint32_t)0x00000001)        /*!<DAC channel1 software trigger */
 #define  DAC_SWTRIGR_SWTRIG2                 ((uint32_t)0x00000002)        /*!<DAC channel2 software trigger */
 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
 #define  DAC_DHR12R1_DACC1DHR                ((uint32_t)0x00000FFF)        /*!<DAC channel1 12-bit Right aligned data */
 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
 #define  DAC_DHR12L1_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!<DAC channel1 12-bit Left aligned data */
 /******************  Bit definition for DAC_DHR8R1 register  ******************/
 #define  DAC_DHR8R1_DACC1DHR                 ((uint32_t)0x000000FF)         /*!<DAC channel1 8-bit Right aligned data */
 /*******************  Bit definition for DAC_DOR1 register  *******************/
 #define  DAC_DOR1_DACC1DOR                   ((uint32_t)0x00000FFF)        /*!<DAC channel1 data output */
 /********************  Bit definition for DAC_SR register  ********************/
 #define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!< DAC channel1 DMA underrun flag */
 #define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000)        /*!< DAC channel2 DMA underrun flag (only for STM32F072 and STM32F042 devices) */
 /******************************************************************************/
 /*                                                                            */
 /*                           Debug MCU (DBGMCU)                               */
 /*                                                                            */
 /******************************************************************************/
 /****************  Bit definition for DBGMCU_IDCODE register  *****************/
 #define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)        /*!< Device Identifier */
 #define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)        /*!< REV_ID[15:0] bits (Revision Identifier) */
 #define  DBGMCU_IDCODE_REV_ID_0              ((uint32_t)0x00010000)        /*!< Bit 0 */
 #define  DBGMCU_IDCODE_REV_ID_1              ((uint32_t)0x00020000)        /*!< Bit 1 */
 #define  DBGMCU_IDCODE_REV_ID_2              ((uint32_t)0x00040000)        /*!< Bit 2 */
 #define  DBGMCU_IDCODE_REV_ID_3              ((uint32_t)0x00080000)        /*!< Bit 3 */
 #define  DBGMCU_IDCODE_REV_ID_4              ((uint32_t)0x00100000)        /*!< Bit 4 */
 #define  DBGMCU_IDCODE_REV_ID_5              ((uint32_t)0x00200000)        /*!< Bit 5 */
 #define  DBGMCU_IDCODE_REV_ID_6              ((uint32_t)0x00400000)        /*!< Bit 6 */
 #define  DBGMCU_IDCODE_REV_ID_7              ((uint32_t)0x00800000)        /*!< Bit 7 */
 #define  DBGMCU_IDCODE_REV_ID_8              ((uint32_t)0x01000000)        /*!< Bit 8 */
 #define  DBGMCU_IDCODE_REV_ID_9              ((uint32_t)0x02000000)        /*!< Bit 9 */
 #define  DBGMCU_IDCODE_REV_ID_10             ((uint32_t)0x04000000)        /*!< Bit 10 */
 #define  DBGMCU_IDCODE_REV_ID_11             ((uint32_t)0x08000000)        /*!< Bit 11 */
 #define  DBGMCU_IDCODE_REV_ID_12             ((uint32_t)0x10000000)        /*!< Bit 12 */
 #define  DBGMCU_IDCODE_REV_ID_13             ((uint32_t)0x20000000)        /*!< Bit 13 */
 #define  DBGMCU_IDCODE_REV_ID_14             ((uint32_t)0x40000000)        /*!< Bit 14 */
 #define  DBGMCU_IDCODE_REV_ID_15             ((uint32_t)0x80000000)        /*!< Bit 15 */
 /******************  Bit definition for DBGMCU_CR register  *******************/
 #define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)        /*!< Debug Stop Mode */
 #define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)        /*!< Debug Standby mode */
 /******************  Bit definition for DBGMCU_APB1_FZ register  **************/
 #define  DBGMCU_APB1_FZ_DBG_TIM2_STOP        ((uint32_t)0x00000001)        /*!< TIM2 counter stopped when core is halted */
 #define  DBGMCU_APB1_FZ_DBG_TIM3_STOP        ((uint32_t)0x00000002)        /*!< TIM3 counter stopped when core is halted */
 #define  DBGMCU_APB1_FZ_DBG_TIM6_STOP        ((uint32_t)0x00000010)        /*!< TIM6 counter stopped when core is halted (not available on STM32F042 devices)*/
 #define  DBGMCU_APB1_FZ_DBG_TIM7_STOP        ((uint32_t)0x00000020)        /*!< TIM7 counter stopped when core is halted (only for STM32F072 devices) */
 #define  DBGMCU_APB1_FZ_DBG_TIM14_STOP       ((uint32_t)0x00000100)        /*!< TIM14 counter stopped when core is halted */
 #define  DBGMCU_APB1_FZ_DBG_RTC_STOP         ((uint32_t)0x00000400)        /*!< RTC Calendar frozen when core is halted */
 #define  DBGMCU_APB1_FZ_DBG_WWDG_STOP        ((uint32_t)0x00000800)        /*!< Debug Window Watchdog stopped when Core is halted */
 #define  DBGMCU_APB1_FZ_DBG_IWDG_STOP        ((uint32_t)0x00001000)        /*!< Debug Independent Watchdog stopped when Core is halted */
 #define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x00200000)   /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
 #define  DBGMCU_APB1_FZ_DBG_CAN_STOP         ((uint32_t)0x02000000)        /*!< CAN debug stopped when Core is halted (only for STM32F072 devices) */
 /******************  Bit definition for DBGMCU_APB2_FZ register  **************/
 #define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        ((uint32_t)0x00000800)        /*!< TIM1 counter stopped when core is halted */
 #define  DBGMCU_APB2_FZ_DBG_TIM15_STOP       ((uint32_t)0x00010000)        /*!< TIM15 counter stopped when core is halted (not available on STM32F042 devices) */
 #define  DBGMCU_APB2_FZ_DBG_TIM16_STOP       ((uint32_t)0x00020000)        /*!< TIM16 counter stopped when core is halted */
 #define  DBGMCU_APB2_FZ_DBG_TIM17_STOP       ((uint32_t)0x00040000)        /*!< TIM17 counter stopped when core is halted */
 /******************************************************************************/
 /*                                                                            */
 /*                           DMA Controller (DMA)                             */
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for DMA_ISR register  ********************/
 #define  DMA_ISR_GIF1                        ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt flag    */
 #define  DMA_ISR_TCIF1                       ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete flag   */
 #define  DMA_ISR_HTIF1                       ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer flag       */
 #define  DMA_ISR_TEIF1                       ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error flag      */
 #define  DMA_ISR_GIF2                        ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt flag    */
 #define  DMA_ISR_TCIF2                       ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete flag   */
 #define  DMA_ISR_HTIF2                       ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer flag       */
 #define  DMA_ISR_TEIF2                       ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error flag      */
 #define  DMA_ISR_GIF3                        ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt flag    */
 #define  DMA_ISR_TCIF3                       ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete flag   */
 #define  DMA_ISR_HTIF3                       ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer flag       */
 #define  DMA_ISR_TEIF3                       ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error flag      */
 #define  DMA_ISR_GIF4                        ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt flag    */
 #define  DMA_ISR_TCIF4                       ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete flag   */
 #define  DMA_ISR_HTIF4                       ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer flag       */
 #define  DMA_ISR_TEIF4                       ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error flag      */
 #define  DMA_ISR_GIF5                        ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt flag    */
 #define  DMA_ISR_TCIF5                       ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete flag   */
 #define  DMA_ISR_HTIF5                       ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer flag       */
 #define  DMA_ISR_TEIF5                       ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error flag      */
 #define  DMA_ISR_GIF6                        ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt flag (only for STM32F072 devices) */
 #define  DMA_ISR_TCIF6                       ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete flag (only for STM32F072 devices) */
 #define  DMA_ISR_HTIF6                       ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer flag (only for STM32F072 devices) */
 #define  DMA_ISR_TEIF6                       ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error flag (only for STM32F072 devices) */
 #define  DMA_ISR_GIF7                        ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt flag (only for STM32F072 devices) */
 #define  DMA_ISR_TCIF7                       ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete flag (only for STM32F072 devices) */
 #define  DMA_ISR_HTIF7                       ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer flag (only for STM32F072 devices) */
 #define  DMA_ISR_TEIF7                       ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error flag (only for STM32F072 devices) */
 /*******************  Bit definition for DMA_IFCR register  *******************/
 #define  DMA_IFCR_CGIF1                      ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt clear    */
 #define  DMA_IFCR_CTCIF1                     ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete clear   */
 #define  DMA_IFCR_CHTIF1                     ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer clear       */
 #define  DMA_IFCR_CTEIF1                     ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error clear      */
 #define  DMA_IFCR_CGIF2                      ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt clear    */
 #define  DMA_IFCR_CTCIF2                     ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete clear   */
 #define  DMA_IFCR_CHTIF2                     ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer clear       */
 #define  DMA_IFCR_CTEIF2                     ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error clear      */
 #define  DMA_IFCR_CGIF3                      ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt clear    */
 #define  DMA_IFCR_CTCIF3                     ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete clear   */
 #define  DMA_IFCR_CHTIF3                     ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer clear       */
 #define  DMA_IFCR_CTEIF3                     ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error clear      */
 #define  DMA_IFCR_CGIF4                      ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt clear    */
 #define  DMA_IFCR_CTCIF4                     ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete clear   */
 #define  DMA_IFCR_CHTIF4                     ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer clear       */
 #define  DMA_IFCR_CTEIF4                     ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error clear      */
 #define  DMA_IFCR_CGIF5                      ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt clear    */
 #define  DMA_IFCR_CTCIF5                     ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete clear   */
 #define  DMA_IFCR_CHTIF5                     ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer clear       */
 #define  DMA_IFCR_CTEIF5                     ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error clear      */
 #define  DMA_IFCR_CGIF6                      ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt clear (only for STM32F072 devices) */
 #define  DMA_IFCR_CTCIF6                     ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete clear (only for STM32F072 devices) */
 #define  DMA_IFCR_CHTIF6                     ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer clear (only for STM32F072 devices) */
 #define  DMA_IFCR_CTEIF6                     ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error clear (only for STM32F072 devices) */
 #define  DMA_IFCR_CGIF7                      ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt clear (only for STM32F072 devices) */
 #define  DMA_IFCR_CTCIF7                     ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete clear (only for STM32F072 devices) */
 #define  DMA_IFCR_CHTIF7                     ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer clear (only for STM32F072 devices) */
 #define  DMA_IFCR_CTEIF7                     ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error clear (only for STM32F072 devices) */
 /*******************  Bit definition for DMA_CCR register  ********************/
 #define  DMA_CCR_EN                          ((uint32_t)0x00000001)        /*!< Channel enable                      */
 #define  DMA_CCR_TCIE                        ((uint32_t)0x00000002)        /*!< Transfer complete interrupt enable  */
 #define  DMA_CCR_HTIE                        ((uint32_t)0x00000004)        /*!< Half Transfer interrupt enable      */
 #define  DMA_CCR_TEIE                        ((uint32_t)0x00000008)        /*!< Transfer error interrupt enable     */
 #define  DMA_CCR_DIR                         ((uint32_t)0x00000010)        /*!< Data transfer direction             */
 #define  DMA_CCR_CIRC                        ((uint32_t)0x00000020)        /*!< Circular mode                       */
 #define  DMA_CCR_PINC                        ((uint32_t)0x00000040)        /*!< Peripheral increment mode           */
 #define  DMA_CCR_MINC                        ((uint32_t)0x00000080)        /*!< Memory increment mode               */
 #define  DMA_CCR_PSIZE                       ((uint32_t)0x00000300)        /*!< PSIZE[1:0] bits (Peripheral size)   */
 #define  DMA_CCR_PSIZE_0                     ((uint32_t)0x00000100)        /*!< Bit 0                               */
 #define  DMA_CCR_PSIZE_1                     ((uint32_t)0x00000200)        /*!< Bit 1                               */
 #define  DMA_CCR_MSIZE                       ((uint32_t)0x00000C00)        /*!< MSIZE[1:0] bits (Memory size)       */
 #define  DMA_CCR_MSIZE_0                     ((uint32_t)0x00000400)        /*!< Bit 0                               */
 #define  DMA_CCR_MSIZE_1                     ((uint32_t)0x00000800)        /*!< Bit 1                               */
 #define  DMA_CCR_PL                          ((uint32_t)0x00003000)        /*!< PL[1:0] bits(Channel Priority level)*/
 #define  DMA_CCR_PL_0                        ((uint32_t)0x00001000)        /*!< Bit 0                               */
 #define  DMA_CCR_PL_1                        ((uint32_t)0x00002000)        /*!< Bit 1                               */
 #define  DMA_CCR_MEM2MEM                     ((uint32_t)0x00004000)        /*!< Memory to memory mode               */
 /******************  Bit definition for DMA_CNDTR register  *******************/
 #define  DMA_CNDTR_NDT                       ((uint32_t)0x0000FFFF)        /*!< Number of data to Transfer          */
 /******************  Bit definition for DMA_CPAR register  ********************/
 #define  DMA_CPAR_PA                         ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */
 /******************  Bit definition for DMA_CMAR register  ********************/
 #define  DMA_CMAR_MA                         ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */
 /******************  Bit definition for DMA_RMPCR1 register  ********************/
 #define DMA_RMPCR1_DEFAULT                  ((uint32_t)0x00000000)        /*!< Default remap position for DMA1 */
 #define DMA_RMPCR1_CH1_ADC                  ((uint32_t)0x00000001)        /*!< Remap ADC on DMA1 Channel 1*/
 #define DMA_RMPCR1_CH1_TIM17_CH1            ((uint32_t)0x00000007)        /*!< Remap TIM17 channel 1 on DMA1 channel 1 */
 #define DMA_RMPCR1_CH1_TIM17_UP             ((uint32_t)0x00000007)        /*!< Remap TIM17 up on DMA1 channel 1 */
 #define DMA_RMPCR1_CH1_USART1_RX            ((uint32_t)0x00000008)        /*!< Remap USART1 Rx on DMA1 channel 1 */
 #define DMA_RMPCR1_CH1_USART2_RX            ((uint32_t)0x00000009)        /*!< Remap USART2 Rx on DMA1 channel 1 */
 #define DMA_RMPCR1_CH1_USART3_RX            ((uint32_t)0x0000000A)        /*!< Remap USART3 Rx on DMA1 channel 1 */
 #define DMA_RMPCR1_CH1_USART4_RX            ((uint32_t)0x0000000B)        /*!< Remap USART4 Rx on DMA1 channel 1 */
 #define DMA_RMPCR1_CH1_USART5_RX            ((uint32_t)0x0000000C)        /*!< Remap USART5 Rx on DMA1 channel 1 */
 #define DMA_RMPCR1_CH1_USART6_RX            ((uint32_t)0x0000000D)        /*!< Remap USART6 Rx on DMA1 channel 1 */
 #define DMA_RMPCR1_CH1_USART7_RX            ((uint32_t)0x0000000E)        /*!< Remap USART7 Rx on DMA1 channel 1 */
 #define DMA_RMPCR1_CH1_USART8_RX            ((uint32_t)0x0000000F)        /*!< Remap USART8 Rx on DMA1 channel 1 */
 #define DMA_RMPCR1_CH2_ADC                  ((uint32_t)0x00000010)        /*!< Remap ADC on DMA1 channel 2 */
 #define DMA_RMPCR1_CH2_I2C1_TX              ((uint32_t)0x00000020)        /*!< Remap I2C1 Tx on DMA1 channel 2 */
 #define DMA_RMPCR1_CH2_SPI_1RX              ((uint32_t)0x00000030)        /*!< Remap SPI1 Rx on DMA1 channel 2 */
 #define DMA_RMPCR1_CH2_TIM1_CH1             ((uint32_t)0x00000040)        /*!< Remap TIM1 channel 1 on DMA1 channel 2 */
 #define DMA_RMPCR1_CH2_TIM17_CH1            ((uint32_t)0x00000070)        /*!< Remap TIM17 channel 1 on DMA1 channel 2 */
 #define DMA_RMPCR1_CH2_TIM17_UP             ((uint32_t)0x00000070)        /*!< Remap TIM17 up on DMA1 channel 2 */
 #define DMA_RMPCR1_CH2_USART1_TX            ((uint32_t)0x00000080)        /*!< Remap USART1 Tx on DMA1 channel 2 */
 #define DMA_RMPCR1_CH2_USART2_TX            ((uint32_t)0x00000090)        /*!< Remap USART2 Tx on DMA1 channel 2 */
 #define DMA_RMPCR1_CH2_USART3_TX            ((uint32_t)0x000000A0)        /*!< Remap USART3 Tx on DMA1 channel 2 */
 #define DMA_RMPCR1_CH2_USART4_TX            ((uint32_t)0x000000B0)        /*!< Remap USART4 Tx on DMA1 channel 2 */
 #define DMA_RMPCR1_CH2_USART5_TX            ((uint32_t)0x000000C0)        /*!< Remap USART5 Tx on DMA1 channel 2 */
 #define DMA_RMPCR1_CH2_USART6_TX            ((uint32_t)0x000000D0)        /*!< Remap USART6 Tx on DMA1 channel 2 */
 #define DMA_RMPCR1_CH2_USART7_TX            ((uint32_t)0x000000E0)        /*!< Remap USART7 Tx on DMA1 channel 2 */
 #define DMA_RMPCR1_CH2_USART8_TX            ((uint32_t)0x000000F0)        /*!< Remap USART8 Tx on DMA1 channel 2 */
 #define DMA_RMPCR1_CH3_TIM6_UP              ((uint32_t)0x00000100)        /*!< Remap TIM6 up on DMA1 channel 3 */
 #define DMA_RMPCR1_CH3_DAC_CH1              ((uint32_t)0x00000100)        /*!< Remap DAC Channel 1on DMA1 channel 3 */
 #define DMA_RMPCR1_CH3_I2C1_RX              ((uint32_t)0x00000200)        /*!< Remap I2C1 Rx on DMA1 channel 3 */
 #define DMA_RMPCR1_CH3_SPI1_TX              ((uint32_t)0x00000300)        /*!< Remap SPI1 Tx on DMA1 channel 3 */
 #define DMA_RMPCR1_CH3_TIM1_CH2             ((uint32_t)0x00000400)        /*!< Remap TIM1 channel 2 on DMA1 channel 3 */
 #define DMA_RMPCR1_CH3_TIM2_CH2             ((uint32_t)0x00000500)        /*!< Remap TIM2 channel 2 on DMA1 channel 3 */
 #define DMA_RMPCR1_CH3_TIM16_CH1            ((uint32_t)0x00000700)        /*!< Remap TIM16 channel 1 on DMA1 channel 3 */
 #define DMA_RMPCR1_CH3_TIM16_UP             ((uint32_t)0x00000700)        /*!< Remap TIM16 up on DMA1 channel 3 */
 #define DMA_RMPCR1_CH3_USART1_RX            ((uint32_t)0x00000800)        /*!< Remap USART1 Rx on DMA1 channel 3 */
 #define DMA_RMPCR1_CH3_USART2_RX            ((uint32_t)0x00000900)        /*!< Remap USART2 Rx on DMA1 channel 3 */
 #define DMA_RMPCR1_CH3_USART3_RX            ((uint32_t)0x00000A00)        /*!< Remap USART3 Rx on DMA1 channel 3 */
 #define DMA_RMPCR1_CH3_USART4_RX            ((uint32_t)0x00000B00)        /*!< Remap USART4 Rx on DMA1 channel 3 */
 #define DMA_RMPCR1_CH3_USART5_RX            ((uint32_t)0x00000C00)        /*!< Remap USART5 Rx on DMA1 channel 3 */
 #define DMA_RMPCR1_CH3_USART6_RX            ((uint32_t)0x00000D00)        /*!< Remap USART6 Rx on DMA1 channel 3 */
 #define DMA_RMPCR1_CH3_USART7_RX            ((uint32_t)0x00000E00)        /*!< Remap USART7 Rx on DMA1 channel 3 */
 #define DMA_RMPCR1_CH3_USART8_RX            ((uint32_t)0x00000F00)        /*!< Remap USART8 Rx on DMA1 channel 3 */
 #define DMA_RMPCR1_CH4_TIM7_UP              ((uint32_t)0x00001000)        /*!< Remap TIM7 up on DMA1 channel 4 */
 #define DMA_RMPCR1_CH4_DAC_CH2              ((uint32_t)0x00001000)        /*!< Remap DAC Channel 2 on DMA1 channel 4 */
 #define DMA_RMPCR1_CH4_I2C2_TX              ((uint32_t)0x00002000)        /*!< Remap I2C2 Tx on DMA1 channel 4 */
 #define DMA_RMPCR1_CH4_SPI2_RX              ((uint32_t)0x00003000)        /*!< Remap SPI2 Rx on DMA1 channel 4 */
 #define DMA_RMPCR1_CH4_TIM2_CH4             ((uint32_t)0x00005000)        /*!< Remap TIM2 channel 4 on DMA1 channel 4 */
 #define DMA_RMPCR1_CH4_TIM3_CH1             ((uint32_t)0x00006000)        /*!< Remap TIM3 channel 1 on DMA1 channel 4 */
 #define DMA_RMPCR1_CH4_TIM3_TRIG            ((uint32_t)0x00006000)        /*!< Remap TIM3 Trig on DMA1 channel 4 */
 #define DMA_RMPCR1_CH4_TIM16_CH1            ((uint32_t)0x00007000)        /*!< Remap TIM16 channel 1 on DMA1 channel 4 */
 #define DMA_RMPCR1_CH4_TIM16_UP             ((uint32_t)0x00007000)        /*!< Remap TIM16 up on DMA1 channel 4 */
 #define DMA_RMPCR1_CH4_USART1_TX            ((uint32_t)0x00008000)        /*!< Remap USART1 Tx on DMA1 channel 4 */
 #define DMA_RMPCR1_CH4_USART2_TX            ((uint32_t)0x00009000)        /*!< Remap USART2 Tx on DMA1 channel 4 */
 #define DMA_RMPCR1_CH4_USART3_TX            ((uint32_t)0x0000A000)        /*!< Remap USART3 Tx on DMA1 channel 4 */
 #define DMA_RMPCR1_CH4_USART4_TX            ((uint32_t)0x0000B000)        /*!< Remap USART4 Tx on DMA1 channel 4 */
 #define DMA_RMPCR1_CH4_USART5_TX            ((uint32_t)0x0000C000)        /*!< Remap USART5 Tx on DMA1 channel 4 */
 #define DMA_RMPCR1_CH4_USART6_TX            ((uint32_t)0x0000D000)        /*!< Remap USART6 Tx on DMA1 channel 4 */
 #define DMA_RMPCR1_CH4_USART7_TX            ((uint32_t)0x0000E000)        /*!< Remap USART7 Tx on DMA1 channel 4 */
 #define DMA_RMPCR1_CH4_USART8_TX            ((uint32_t)0x0000F000)        /*!< Remap USART8 Tx on DMA1 channel 4 */
 #define DMA_RMPCR1_CH5_I2C2_RX              ((uint32_t)0x00020000)        /*!< Remap I2C2 Rx on DMA1 channel 5 */
 #define DMA_RMPCR1_CH5_SPI2_TX              ((uint32_t)0x00030000)        /*!< Remap SPI1 Tx on DMA1 channel 5 */
 #define DMA_RMPCR1_CH5_TIM1_CH3             ((uint32_t)0x00040000)        /*!< Remap TIM1 channel 3 on DMA1 channel 5 */
 #define DMA_RMPCR1_CH5_USART1_RX            ((uint32_t)0x00080000)        /*!< Remap USART1 Rx on DMA1 channel 5 */
 #define DMA_RMPCR1_CH5_USART2_RX            ((uint32_t)0x00090000)        /*!< Remap USART2 Rx on DMA1 channel 5 */
 #define DMA_RMPCR1_CH5_USART3_RX            ((uint32_t)0x000A0000)        /*!< Remap USART3 Rx on DMA1 channel 5 */
 #define DMA_RMPCR1_CH5_USART4_RX            ((uint32_t)0x000B0000)        /*!< Remap USART4 Rx on DMA1 channel 5 */
 #define DMA_RMPCR1_CH5_USART5_RX            ((uint32_t)0x000C0000)        /*!< Remap USART5 Rx on DMA1 channel 5 */
 #define DMA_RMPCR1_CH5_USART6_RX            ((uint32_t)0x000D0000)        /*!< Remap USART6 Rx on DMA1 channel 5 */
 #define DMA_RMPCR1_CH5_USART7_RX            ((uint32_t)0x000E0000)        /*!< Remap USART7 Rx on DMA1 channel 5 */
 #define DMA_RMPCR1_CH5_USART8_RX            ((uint32_t)0x000F0000)        /*!< Remap USART8 Rx on DMA1 channel 5 */
 #define DMA_RMPCR1_CH6_I2C1_TX              ((uint32_t)0x00200000)        /*!< Remap I2C1 Tx on DMA1 channel 6 */
 #define DMA_RMPCR1_CH6_SPI2_RX              ((uint32_t)0x00300000)        /*!< Remap SPI2 Rx on DMA1 channel 6 */
 #define DMA_RMPCR1_CH6_TIM1_CH1             ((uint32_t)0x00400000)        /*!< Remap TIM1 channel 1 on DMA1 channel 6 */
 #define DMA_RMPCR1_CH6_TIM1_CH2             ((uint32_t)0x00400000)        /*!< Remap TIM1 channel 2 on DMA1 channel 6 */
 #define DMA_RMPCR1_CH6_TIM1_CH3             ((uint32_t)0x00400000)        /*!< Remap TIM1 channel 3 on DMA1 channel 6 */
 #define DMA_RMPCR1_CH6_TIM3_CH1             ((uint32_t)0x00600000)        /*!< Remap TIM3 channel 1 on DMA1 channel 6 */
 #define DMA_RMPCR1_CH6_TIM3_TRIG            ((uint32_t)0x00600000)        /*!< Remap TIM3 Trig on DMA1 channel 6 */
 #define DMA_RMPCR1_CH6_TIM16_CH1            ((uint32_t)0x00700000)        /*!< Remap TIM16 channel 1 on DMA1 channel 6 */
 #define DMA_RMPCR1_CH6_TIM16_UP             ((uint32_t)0x00700000)        /*!< Remap TIM16 up on DMA1 channel 6 */
 #define DMA_RMPCR1_CH6_USART1_RX            ((uint32_t)0x00800000)        /*!< Remap USART1 Rx on DMA1 channel 6 */
 #define DMA_RMPCR1_CH6_USART2_RX            ((uint32_t)0x00900000)        /*!< Remap USART2 Rx on DMA1 channel 6 */
 #define DMA_RMPCR1_CH6_USART3_RX            ((uint32_t)0x00A00000)        /*!< Remap USART3 Rx on DMA1 channel 6 */
 #define DMA_RMPCR1_CH6_USART4_RX            ((uint32_t)0x00B00000)        /*!< Remap USART4 Rx on DMA1 channel 6 */
 #define DMA_RMPCR1_CH6_USART5_RX            ((uint32_t)0x00C00000)        /*!< Remap USART5 Rx on DMA1 channel 6 */
 #define DMA_RMPCR1_CH6_USART6_RX            ((uint32_t)0x00D00000)        /*!< Remap USART6 Rx on DMA1 channel 6 */
 #define DMA_RMPCR1_CH6_USART7_RX            ((uint32_t)0x00E00000)        /*!< Remap USART7 Rx on DMA1 channel 6 */
 #define DMA_RMPCR1_CH6_USART8_RX            ((uint32_t)0x00F00000)        /*!< Remap USART8 Rx on DMA1 channel 6 */
 #define DMA_RMPCR1_CH7_I2C1_RX              ((uint32_t)0x02000000)        /*!< Remap I2C1 Rx on DMA1 channel 7 */
 #define DMA_RMPCR1_CH7_SPI2_TX              ((uint32_t)0x03000000)        /*!< Remap SPI2 Tx on DMA1 channel 7 */
 #define DMA_RMPCR1_CH7_TIM2_CH2             ((uint32_t)0x05000000)        /*!< Remap TIM2 channel 2 on DMA1 channel 7 */
 #define DMA_RMPCR1_CH7_TIM2_CH4             ((uint32_t)0x05000000)        /*!< Remap TIM2 channel 4 on DMA1 channel 7 */
 #define DMA_RMPCR1_CH7_TIM17_CH1            ((uint32_t)0x07000000)        /*!< Remap TIM17 channel 1 on DMA1 channel 7 */
 #define DMA_RMPCR1_CH7_TIM17_UP             ((uint32_t)0x07000000)        /*!< Remap TIM17 up on DMA1 channel 7 */
 #define DMA_RMPCR1_CH7_USART1_TX            ((uint32_t)0x08000000)        /*!< Remap USART1 Tx on DMA1 channel 7 */
 #define DMA_RMPCR1_CH7_USART2_TX            ((uint32_t)0x09000000)        /*!< Remap USART2 Tx on DMA1 channel 7 */
 #define DMA_RMPCR1_CH7_USART3_TX            ((uint32_t)0x0A000000)        /*!< Remap USART3 Tx on DMA1 channel 7 */
 #define DMA_RMPCR1_CH7_USART4_TX            ((uint32_t)0x0B000000)        /*!< Remap USART4 Tx on DMA1 channel 7 */
 #define DMA_RMPCR1_CH7_USART5_TX            ((uint32_t)0x0C000000)        /*!< Remap USART5 Tx on DMA1 channel 7 */
 #define DMA_RMPCR1_CH7_USART6_TX            ((uint32_t)0x0D000000)        /*!< Remap USART6 Tx on DMA1 channel 7 */
 #define DMA_RMPCR1_CH7_USART7_TX            ((uint32_t)0x0E000000)        /*!< Remap USART7 Tx on DMA1 channel 7 */
 #define DMA_RMPCR1_CH7_USART8_TX            ((uint32_t)0x0F000000)        /*!< Remap USART8 Tx on DMA1 channel 7 */
 /******************  Bit definition for DMA_RMPCR2 register  ********************/
 #define DMA_RMPCR2_DEFAULT                  ((uint32_t)0x00000000)        /*!< Default remap position for DMA2 */
 #define DMA_RMPCR2_CH1_I2C2_TX              ((uint32_t)0x00000002)        /*!< Remap I2C2 TX on DMA2 channel 1 */
 #define DMA_RMPCR2_CH1_USART1_TX            ((uint32_t)0x00000008)        /*!< Remap USART1 Tx on DMA2 channel 1 */
 #define DMA_RMPCR2_CH1_USART2_TX            ((uint32_t)0x00000009)        /*!< Remap USART2 Tx on DMA2 channel 1 */
 #define DMA_RMPCR2_CH1_USART3_TX            ((uint32_t)0x0000000A)        /*!< Remap USART3 Tx on DMA2 channel 1 */
 #define DMA_RMPCR2_CH1_USART4_TX            ((uint32_t)0x0000000B)        /*!< Remap USART4 Tx on DMA2 channel 1 */
 #define DMA_RMPCR2_CH1_USART5_TX            ((uint32_t)0x0000000C)        /*!< Remap USART5 Tx on DMA2 channel 1 */
 #define DMA_RMPCR2_CH1_USART6_TX            ((uint32_t)0x0000000D)        /*!< Remap USART6 Tx on DMA2 channel 1 */
 #define DMA_RMPCR2_CH1_USART7_TX            ((uint32_t)0x0000000E)        /*!< Remap USART7 Tx on DMA2 channel 1 */
 #define DMA_RMPCR2_CH1_USART8_TX            ((uint32_t)0x0000000F)        /*!< Remap USART8 Tx on DMA2 channel 1 */
 #define DMA_RMPCR2_CH2_I2C2_RX              ((uint32_t)0x00000020)        /*!< Remap I2C2 Rx on DMA2 channel 2 */
 #define DMA_RMPCR2_CH2_USART1_RX            ((uint32_t)0x00000080)        /*!< Remap USART1 Rx on DMA2 channel 2 */
 #define DMA_RMPCR2_CH2_USART2_RX            ((uint32_t)0x00000090)        /*!< Remap USART2 Rx on DMA2 channel 2 */
 #define DMA_RMPCR2_CH2_USART3_RX            ((uint32_t)0x000000A0)        /*!< Remap USART3 Rx on DMA2 channel 2 */
 #define DMA_RMPCR2_CH2_USART4_RX            ((uint32_t)0x000000B0)        /*!< Remap USART4 Rx on DMA2 channel 2 */
 #define DMA_RMPCR2_CH2_USART5_RX            ((uint32_t)0x000000C0)        /*!< Remap USART5 Rx on DMA2 channel 2 */
 #define DMA_RMPCR2_CH2_USART6_RX            ((uint32_t)0x000000D0)        /*!< Remap USART6 Rx on DMA2 channel 2 */
 #define DMA_RMPCR2_CH2_USART7_RX            ((uint32_t)0x000000E0)        /*!< Remap USART7 Rx on DMA2 channel 2 */
 #define DMA_RMPCR2_CH2_USART8_RX            ((uint32_t)0x000000F0)        /*!< Remap USART8 Rx on DMA2 channel 2 */
 #define DMA_RMPCR2_CH3_TIM6_UP              ((uint32_t)0x00000100)        /*!< Remap TIM6 up on DMA2 channel 3 */
 #define DMA_RMPCR2_CH3_DAC_CH1              ((uint32_t)0x00000100)        /*!< Remap DAC channel 1 on DMA2 channel 3 */
 #define DMA_RMPCR2_CH3_SPI1_RX              ((uint32_t)0x00000300)        /*!< Remap SPI1 Rx on DMA2 channel 3 */
 #define DMA_RMPCR2_CH3_USART1_RX            ((uint32_t)0x00000800)        /*!< Remap USART1 Rx on DMA2 channel 3 */
 #define DMA_RMPCR2_CH3_USART2_RX            ((uint32_t)0x00000900)        /*!< Remap USART2 Rx on DMA2 channel 3 */
 #define DMA_RMPCR2_CH3_USART3_RX            ((uint32_t)0x00000A00)        /*!< Remap USART3 Rx on DMA2 channel 3 */
 #define DMA_RMPCR2_CH3_USART4_RX            ((uint32_t)0x00000B00)        /*!< Remap USART4 Rx on DMA2 channel 3 */
 #define DMA_RMPCR2_CH3_USART5_RX            ((uint32_t)0x00000C00)        /*!< Remap USART5 Rx on DMA2 channel 3 */
 #define DMA_RMPCR2_CH3_USART6_RX            ((uint32_t)0x00000D00)        /*!< Remap USART6 Rx on DMA2 channel 3 */
 #define DMA_RMPCR2_CH3_USART7_RX            ((uint32_t)0x00000E00)        /*!< Remap USART7 Rx on DMA2 channel 3 */
 #define DMA_RMPCR2_CH3_USART8_RX            ((uint32_t)0x00000F00)        /*!< Remap USART8 Rx on DMA2 channel 3 */
 #define DMA_RMPCR2_CH4_TIM7_UP              ((uint32_t)0x00001000)        /*!< Remap TIM7 up on DMA2 channel 4 */
 #define DMA_RMPCR2_CH4_DAC_CH2              ((uint32_t)0x00001000)        /*!< Remap DAC channel 2 on DMA2 channel 4 */
 #define DMA_RMPCR2_CH4_SPI1_TX              ((uint32_t)0x00003000)        /*!< Remap SPI1 Tx on DMA2 channel 4 */
 #define DMA_RMPCR2_CH4_USART1_TX            ((uint32_t)0x00008000)        /*!< Remap USART1 Tx on DMA2 channel 4 */
 #define DMA_RMPCR2_CH4_USART2_TX            ((uint32_t)0x00009000)        /*!< Remap USART2 Tx on DMA2 channel 4 */
 #define DMA_RMPCR2_CH4_USART3_TX            ((uint32_t)0x0000A000)        /*!< Remap USART3 Tx on DMA2 channel 4 */
 #define DMA_RMPCR2_CH4_USART4_TX            ((uint32_t)0x0000B000)        /*!< Remap USART4 Tx on DMA2 channel 4 */
 #define DMA_RMPCR2_CH4_USART5_TX            ((uint32_t)0x0000C000)        /*!< Remap USART5 Tx on DMA2 channel 4 */
 #define DMA_RMPCR2_CH4_USART6_TX            ((uint32_t)0x0000D000)        /*!< Remap USART6 Tx on DMA2 channel 4 */
 #define DMA_RMPCR2_CH4_USART7_TX            ((uint32_t)0x0000E000)        /*!< Remap USART7 Tx on DMA2 channel 4 */
 #define DMA_RMPCR2_CH4_USART8_TX            ((uint32_t)0x0000F000)        /*!< Remap USART8 Tx on DMA2 channel 4 */
 #define DMA_RMPCR2_CH5_ADC                  ((uint32_t)0x00010000)        /*!< Remap ADC on DMA2 channel 5 */
 #define DMA_RMPCR2_CH5_USART1_TX            ((uint32_t)0x00080000)        /*!< Remap USART1 Tx on DMA2 channel 5 */
 #define DMA_RMPCR2_CH5_USART2_TX            ((uint32_t)0x00090000)        /*!< Remap USART2 Tx on DMA2 channel 5 */
 #define DMA_RMPCR2_CH5_USART3_TX            ((uint32_t)0x000A0000)        /*!< Remap USART3 Tx on DMA2 channel 5 */
 #define DMA_RMPCR2_CH5_USART4_TX            ((uint32_t)0x000B0000)        /*!< Remap USART4 Tx on DMA2 channel 5 */
 #define DMA_RMPCR2_CH5_USART5_TX            ((uint32_t)0x000C0000)        /*!< Remap USART5 Tx on DMA2 channel 5 */
 #define DMA_RMPCR2_CH5_USART6_TX            ((uint32_t)0x000D0000)        /*!< Remap USART6 Tx on DMA2 channel 5 */
 #define DMA_RMPCR2_CH5_USART7_TX            ((uint32_t)0x000E0000)        /*!< Remap USART7 Tx on DMA2 channel 5 */
 #define DMA_RMPCR2_CH5_USART8_TX            ((uint32_t)0x000F0000)        /*!< Remap USART8 Tx on DMA2 channel 5 */
 /******************************************************************************/
 /*                                                                            */
 /*                 External Interrupt/Event Controller (EXTI)                 */
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for EXTI_IMR register  *******************/
 #define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0  */
 #define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1  */
 #define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2  */
 #define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3  */
 #define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4  */
 #define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5  */
 #define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6  */
 #define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7  */
 #define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8  */
 #define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9  */
 #define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
 #define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
 #define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
 #define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
 #define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
 #define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
 #define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
 #define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
 #define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
 #define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
 #define  EXTI_IMR_MR20                       ((uint32_t)0x00100000)        /*!< Interrupt Mask on line 20 */
 #define  EXTI_IMR_MR21                       ((uint32_t)0x00200000)        /*!< Interrupt Mask on line 21 */
 #define  EXTI_IMR_MR22                       ((uint32_t)0x00400000)        /*!< Interrupt Mask on line 22 */
 #define  EXTI_IMR_MR23                       ((uint32_t)0x00800000)        /*!< Interrupt Mask on line 23 */
 #define  EXTI_IMR_MR24                       ((uint32_t)0x01000000)        /*!< Interrupt Mask on line 24 */
 #define  EXTI_IMR_MR25                       ((uint32_t)0x02000000)        /*!< Interrupt Mask on line 25 */
 #define  EXTI_IMR_MR26                       ((uint32_t)0x04000000)        /*!< Interrupt Mask on line 26 */
 #define  EXTI_IMR_MR27                       ((uint32_t)0x08000000)        /*!< Interrupt Mask on line 27 */
 #define  EXTI_IMR_MR28                       ((uint32_t)0x10000000)        /*!< Interrupt Mask on line 28 */
 #define  EXTI_IMR_MR29                       ((uint32_t)0x20000000)        /*!< Interrupt Mask on line 29 */
 #define  EXTI_IMR_MR30                       ((uint32_t)0x40000000)        /*!< Interrupt Mask on line 30 */
 #define  EXTI_IMR_MR31                       ((uint32_t)0x80000000)        /*!< Interrupt Mask on line 31 */
 /******************  Bit definition for EXTI_EMR register  ********************/
 #define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0  */
 #define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1  */
 #define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2  */
 #define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3  */
 #define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4  */
 #define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5  */
 #define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6  */
 #define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7  */
 #define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8  */
 #define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9  */
 #define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
 #define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
 #define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
 #define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
 #define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
 #define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
 #define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
 #define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
 #define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
 #define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
 #define  EXTI_EMR_MR20                       ((uint32_t)0x00100000)        /*!< Event Mask on line 20 */
 #define  EXTI_EMR_MR21                       ((uint32_t)0x00200000)        /*!< Event Mask on line 21 */
 #define  EXTI_EMR_MR22                       ((uint32_t)0x00400000)        /*!< Event Mask on line 22 */
 #define  EXTI_EMR_MR23                       ((uint32_t)0x00800000)        /*!< Event Mask on line 23 */
 #define  EXTI_EMR_MR24                       ((uint32_t)0x01000000)        /*!< Event Mask on line 24 */
 #define  EXTI_EMR_MR25                       ((uint32_t)0x02000000)        /*!< Event Mask on line 25 */
 #define  EXTI_EMR_MR26                       ((uint32_t)0x04000000)        /*!< Event Mask on line 26 */
 #define  EXTI_EMR_MR27                       ((uint32_t)0x08000000)        /*!< Event Mask on line 27 */
 #define  EXTI_EMR_MR28                       ((uint32_t)0x10000000)        /*!< Event Mask on line 28 */
 #define  EXTI_EMR_MR29                       ((uint32_t)0x20000000)        /*!< Event Mask on line 29 */
 #define  EXTI_EMR_MR30                       ((uint32_t)0x40000000)        /*!< Event Mask on line 30 */
 #define  EXTI_EMR_MR31                       ((uint32_t)0x80000000)        /*!< Event Mask on line 31 */
 /*******************  Bit definition for EXTI_RTSR register  ******************/
 #define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
 #define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
 #define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
 #define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
 #define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
 #define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
 #define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
 #define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
 #define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
 #define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
 #define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
 #define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
 #define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
 #define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
 #define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
 #define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
 #define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
 #define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
 #define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
 #define  EXTI_RTSR_TR20                      ((uint32_t)0x00100000)        /*!< Rising trigger event configuration bit of line 20 */
 #define  EXTI_RTSR_TR21                      ((uint32_t)0x00200000)        /*!< Rising trigger event configuration bit of line 21 */
 #define  EXTI_RTSR_TR22                      ((uint32_t)0x00400000)        /*!< Rising trigger event configuration bit of line 22 */
 /*******************  Bit definition for EXTI_FTSR register *******************/
 #define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
 #define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
 #define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
 #define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
 #define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
 #define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
 #define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
 #define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
 #define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
 #define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
 #define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
 #define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
 #define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
 #define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
 #define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
 #define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
 #define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
 #define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
 #define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
 #define  EXTI_FTSR_TR20                      ((uint32_t)0x00100000)        /*!< Falling trigger event configuration bit of line 20 */
 #define  EXTI_FTSR_TR21                      ((uint32_t)0x00200000)        /*!< Falling trigger event configuration bit of line 21 */
 #define  EXTI_FTSR_TR22                      ((uint32_t)0x00400000)        /*!< Falling trigger event configuration bit of line 22 */
 /******************* Bit definition for EXTI_SWIER register *******************/
 #define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0  */
 #define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1  */
 #define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2  */
 #define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3  */
 #define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4  */
 #define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5  */
 #define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6  */
 #define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7  */
 #define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8  */
 #define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9  */
 #define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
 #define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
 #define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
 #define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
 #define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
 #define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
 #define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
 #define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
 #define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
 #define  EXTI_SWIER_SWIER20                  ((uint32_t)0x00100000)        /*!< Software Interrupt on line 20 */
 #define  EXTI_SWIER_SWIER21                  ((uint32_t)0x00200000)        /*!< Software Interrupt on line 21 */
 #define  EXTI_SWIER_SWIER22                  ((uint32_t)0x00400000)        /*!< Software Interrupt on line 22 */
 /******************  Bit definition for EXTI_PR register  *********************/
 #define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit 0  */
 #define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit 1  */
 #define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit 2  */
 #define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit 3  */
 #define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit 4  */
 #define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit 5  */
 #define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit 6  */
 #define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit 7  */
 #define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit 8  */
 #define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit 9  */
 #define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit 10 */
 #define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit 11 */
 #define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit 12 */
 #define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit 13 */
 #define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit 14 */
 #define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit 15 */
 #define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit 16 */
 #define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit 17 */
 #define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit 19 */
 #define  EXTI_PR_PR20                        ((uint32_t)0x00100000)        /*!< Pending bit 20 */
 #define  EXTI_PR_PR21                        ((uint32_t)0x00200000)        /*!< Pending bit 21 */
 #define  EXTI_PR_PR22                        ((uint32_t)0x00400000)        /*!< Pending bit 22 */
 /******************************************************************************/
 /*                                                                            */
 /*                      FLASH and Option Bytes Registers                      */
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for FLASH_ACR register  ******************/
 #define  FLASH_ACR_LATENCY                   ((uint32_t)0x00000001)        /*!< LATENCY bit (Latency) */
 #define  FLASH_ACR_PRFTBE                    ((uint32_t)0x00000010)        /*!< Prefetch Buffer Enable */
 #define  FLASH_ACR_PRFTBS                    ((uint32_t)0x00000020)        /*!< Prefetch Buffer Status */
 /******************  Bit definition for FLASH_KEYR register  ******************/
 #define  FLASH_KEYR_FKEYR                    ((uint32_t)0xFFFFFFFF)        /*!< FPEC Key */
 /*****************  Bit definition for FLASH_OPTKEYR register  ****************/
 #define  FLASH_OPTKEYR_OPTKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Option Byte Key */
 /******************  FLASH Keys  **********************************************/
 #define FLASH_FKEY1                          ((uint32_t)0x45670123)        /*!< Flash program erase key1 */
 #define FLASH_FKEY2                          ((uint32_t)0xCDEF89AB)        /*!< Flash program erase key2: used with FLASH_PEKEY1
                                                                                 to unlock the write access to the FPEC. */
 #define FLASH_OPTKEY1                        ((uint32_t)0x45670123)        /*!< Flash option key1 */
 #define FLASH_OPTKEY2                        ((uint32_t)0xCDEF89AB)        /*!< Flash option key2: used with FLASH_OPTKEY1 to
                                                                                 unlock the write access to the option byte block */
 /******************  Bit definition for FLASH_SR register  *******************/
 #define  FLASH_SR_BSY                        ((uint32_t)0x00000001)        /*!< Busy */
 #define  FLASH_SR_PGERR                      ((uint32_t)0x00000004)        /*!< Programming Error */
 #define  FLASH_SR_WRPRTERR                   ((uint32_t)0x00000010)        /*!< Write Protection Error */
 #define  FLASH_SR_EOP                        ((uint32_t)0x00000020)        /*!< End of operation */
 #define  FLASH_SR_WRPERR                     FLASH_SR_WRPRTERR             /*!< Legacy of Write Protection Error */
 /*******************  Bit definition for FLASH_CR register  *******************/
 #define  FLASH_CR_PG                         ((uint32_t)0x00000001)        /*!< Programming */
 #define  FLASH_CR_PER                        ((uint32_t)0x00000002)        /*!< Page Erase */
 #define  FLASH_CR_MER                        ((uint32_t)0x00000004)        /*!< Mass Erase */
 #define  FLASH_CR_OPTPG                      ((uint32_t)0x00000010)        /*!< Option Byte Programming */
 #define  FLASH_CR_OPTER                      ((uint32_t)0x00000020)        /*!< Option Byte Erase */
 #define  FLASH_CR_STRT                       ((uint32_t)0x00000040)        /*!< Start */
 #define  FLASH_CR_LOCK                       ((uint32_t)0x00000080)        /*!< Lock */
 #define  FLASH_CR_OPTWRE                     ((uint32_t)0x00000200)        /*!< Option Bytes Write Enable */
 #define  FLASH_CR_ERRIE                      ((uint32_t)0x00000400)        /*!< Error Interrupt Enable */
 #define  FLASH_CR_EOPIE                      ((uint32_t)0x00001000)        /*!< End of operation interrupt enable */
 #define  FLASH_CR_OBL_LAUNCH                 ((uint32_t)0x00002000)        /*!< Option Bytes Loader Launch */
 /*******************  Bit definition for FLASH_AR register  *******************/
 #define  FLASH_AR_FAR                        ((uint32_t)0xFFFFFFFF)        /*!< Flash Address */
 /******************  Bit definition for FLASH_OBR register  *******************/
 #define  FLASH_OBR_OPTERR                    ((uint32_t)0x00000001)        /*!< Option Byte Error */
 #define  FLASH_OBR_RDPRT1                    ((uint32_t)0x00000002)        /*!< Read protection Level bit 1 */
 #define  FLASH_OBR_RDPRT2                    ((uint32_t)0x00000004)        /*!< Read protection Level bit 2 */
 #define  FLASH_OBR_USER                      ((uint32_t)0x00003700)        /*!< User Option Bytes */
 #define  FLASH_OBR_IWDG_SW                   ((uint32_t)0x00000100)        /*!< IWDG SW */
 #define  FLASH_OBR_nRST_STOP                 ((uint32_t)0x00000200)        /*!< nRST_STOP */
 #define  FLASH_OBR_nRST_STDBY                ((uint32_t)0x00000400)        /*!< nRST_STDBY */
 #define  FLASH_OBR_nBOOT0                    ((uint32_t)0x00000800)        /*!< nBOOT0 */
 #define  FLASH_OBR_nBOOT1                    ((uint32_t)0x00001000)        /*!< nBOOT1 */
 #define  FLASH_OBR_VDDA_MONITOR              ((uint32_t)0x00002000)        /*!< VDDA power supply supervisor */
 #define  FLASH_OBR_RAM_PARITY_CHECK          ((uint32_t)0x00004000)        /*!< RAM Parity Check */
 #define  FLASH_OBR_nBOOT0_SW                 ((uint32_t)0x00008000)        /*!< nBOOT0 SW  (available only in the STM32F042 devices)*/
 #define  FLASH_OBR_DATA0                     ((uint32_t)0x00FF0000)        /*!< DATA0 */
 #define  FLASH_OBR_DATA1                     ((uint32_t)0xFF000000)        /*!< DATA0 */
 /* Old BOOT1 bit definition, maintained for legacy purpose */
 #define FLASH_OBR_BOOT1                      FLASH_OBR_nBOOT1
 /* Old OBR_VDDA bit definition, maintained for legacy purpose */
 #define FLASH_OBR_VDDA_ANALOG                FLASH_OBR_VDDA_MONITOR
 /******************  Bit definition for FLASH_WRPR register  ******************/
 #define  FLASH_WRPR_WRP                      ((uint32_t)0xFFFFFFFF)        /*!< Write Protect */
 /*----------------------------------------------------------------------------*/
 /******************  Bit definition for OB_RDP register  **********************/
 #define  OB_RDP_RDP                          ((uint32_t)0x000000FF)        /*!< Read protection option byte */
 #define  OB_RDP_nRDP                         ((uint32_t)0x0000FF00)        /*!< Read protection complemented option byte */
 /******************  Bit definition for OB_USER register  *********************/
 #define  OB_USER_USER                        ((uint32_t)0x00FF0000)        /*!< User option byte */
 #define  OB_USER_nUSER                       ((uint32_t)0xFF000000)        /*!< User complemented option byte */
 /******************  Bit definition for OB_WRP0 register  *********************/
 #define  OB_WRP0_WRP0                        ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes */
 #define  OB_WRP0_nWRP0                       ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes */
 /******************  Bit definition for OB_WRP1 register  *********************/
 #define  OB_WRP1_WRP1                        ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes */
 #define  OB_WRP1_nWRP1                       ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes */
 /******************  Bit definition for OB_WRP2 register  *********************/
 #define  OB_WRP2_WRP2                        ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes (only for STM32F072 devices) */
 #define  OB_WRP2_nWRP2                       ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes (only for STM32F072 devices) */
 /******************  Bit definition for OB_WRP3 register  *********************/
 #define  OB_WRP3_WRP3                        ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes (only for STM32F072 devices) */
 #define  OB_WRP3_nWRP3                       ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes (only for STM32F072 devices) */
 /******************************************************************************/
 /*                                                                            */
 /*                       General Purpose IOs (GPIO)                           */
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for GPIO_MODER register  *****************/
 #define GPIO_MODER_MODER0          ((uint32_t)0x00000003)
 #define GPIO_MODER_MODER0_0        ((uint32_t)0x00000001)
 #define GPIO_MODER_MODER0_1        ((uint32_t)0x00000002)
 #define GPIO_MODER_MODER1          ((uint32_t)0x0000000C)
 #define GPIO_MODER_MODER1_0        ((uint32_t)0x00000004)
 #define GPIO_MODER_MODER1_1        ((uint32_t)0x00000008)
 #define GPIO_MODER_MODER2          ((uint32_t)0x00000030)
 #define GPIO_MODER_MODER2_0        ((uint32_t)0x00000010)
 #define GPIO_MODER_MODER2_1        ((uint32_t)0x00000020)
 #define GPIO_MODER_MODER3          ((uint32_t)0x000000C0)
 #define GPIO_MODER_MODER3_0        ((uint32_t)0x00000040)
 #define GPIO_MODER_MODER3_1        ((uint32_t)0x00000080)
 #define GPIO_MODER_MODER4          ((uint32_t)0x00000300)
 #define GPIO_MODER_MODER4_0        ((uint32_t)0x00000100)
 #define GPIO_MODER_MODER4_1        ((uint32_t)0x00000200)
 #define GPIO_MODER_MODER5          ((uint32_t)0x00000C00)
 #define GPIO_MODER_MODER5_0        ((uint32_t)0x00000400)
 #define GPIO_MODER_MODER5_1        ((uint32_t)0x00000800)
 #define GPIO_MODER_MODER6          ((uint32_t)0x00003000)
 #define GPIO_MODER_MODER6_0        ((uint32_t)0x00001000)
 #define GPIO_MODER_MODER6_1        ((uint32_t)0x00002000)
 #define GPIO_MODER_MODER7          ((uint32_t)0x0000C000)
 #define GPIO_MODER_MODER7_0        ((uint32_t)0x00004000)
 #define GPIO_MODER_MODER7_1        ((uint32_t)0x00008000)
 #define GPIO_MODER_MODER8          ((uint32_t)0x00030000)
 #define GPIO_MODER_MODER8_0        ((uint32_t)0x00010000)
 #define GPIO_MODER_MODER8_1        ((uint32_t)0x00020000)
 #define GPIO_MODER_MODER9          ((uint32_t)0x000C0000)
 #define GPIO_MODER_MODER9_0        ((uint32_t)0x00040000)
 #define GPIO_MODER_MODER9_1        ((uint32_t)0x00080000)
 #define GPIO_MODER_MODER10         ((uint32_t)0x00300000)
 #define GPIO_MODER_MODER10_0       ((uint32_t)0x00100000)
 #define GPIO_MODER_MODER10_1       ((uint32_t)0x00200000)
 #define GPIO_MODER_MODER11         ((uint32_t)0x00C00000)
 #define GPIO_MODER_MODER11_0       ((uint32_t)0x00400000)
 #define GPIO_MODER_MODER11_1       ((uint32_t)0x00800000)
 #define GPIO_MODER_MODER12         ((uint32_t)0x03000000)
 #define GPIO_MODER_MODER12_0       ((uint32_t)0x01000000)
 #define GPIO_MODER_MODER12_1       ((uint32_t)0x02000000)
 #define GPIO_MODER_MODER13         ((uint32_t)0x0C000000)
 #define GPIO_MODER_MODER13_0       ((uint32_t)0x04000000)
 #define GPIO_MODER_MODER13_1       ((uint32_t)0x08000000)
 #define GPIO_MODER_MODER14         ((uint32_t)0x30000000)
 #define GPIO_MODER_MODER14_0       ((uint32_t)0x10000000)
 #define GPIO_MODER_MODER14_1       ((uint32_t)0x20000000)
 #define GPIO_MODER_MODER15         ((uint32_t)0xC0000000)
 #define GPIO_MODER_MODER15_0       ((uint32_t)0x40000000)
 #define GPIO_MODER_MODER15_1       ((uint32_t)0x80000000)
 /******************  Bit definition for GPIO_OTYPER register  *****************/
 #define GPIO_OTYPER_OT_0           ((uint32_t)0x00000001)
 #define GPIO_OTYPER_OT_1           ((uint32_t)0x00000002)
 #define GPIO_OTYPER_OT_2           ((uint32_t)0x00000004)
 #define GPIO_OTYPER_OT_3           ((uint32_t)0x00000008)
 #define GPIO_OTYPER_OT_4           ((uint32_t)0x00000010)
 #define GPIO_OTYPER_OT_5           ((uint32_t)0x00000020)
 #define GPIO_OTYPER_OT_6           ((uint32_t)0x00000040)
 #define GPIO_OTYPER_OT_7           ((uint32_t)0x00000080)
 #define GPIO_OTYPER_OT_8           ((uint32_t)0x00000100)
 #define GPIO_OTYPER_OT_9           ((uint32_t)0x00000200)
 #define GPIO_OTYPER_OT_10          ((uint32_t)0x00000400)
 #define GPIO_OTYPER_OT_11          ((uint32_t)0x00000800)
 #define GPIO_OTYPER_OT_12          ((uint32_t)0x00001000)
 #define GPIO_OTYPER_OT_13          ((uint32_t)0x00002000)
 #define GPIO_OTYPER_OT_14          ((uint32_t)0x00004000)
 #define GPIO_OTYPER_OT_15          ((uint32_t)0x00008000)
 /****************  Bit definition for GPIO_OSPEEDR register  ******************/
 #define GPIO_OSPEEDR_OSPEEDR0     ((uint32_t)0x00000003)
 #define GPIO_OSPEEDR_OSPEEDR0_0   ((uint32_t)0x00000001)
 #define GPIO_OSPEEDR_OSPEEDR0_1   ((uint32_t)0x00000002)
 #define GPIO_OSPEEDR_OSPEEDR1     ((uint32_t)0x0000000C)
 #define GPIO_OSPEEDR_OSPEEDR1_0   ((uint32_t)0x00000004)
 #define GPIO_OSPEEDR_OSPEEDR1_1   ((uint32_t)0x00000008)
 #define GPIO_OSPEEDR_OSPEEDR2     ((uint32_t)0x00000030)
 #define GPIO_OSPEEDR_OSPEEDR2_0   ((uint32_t)0x00000010)
 #define GPIO_OSPEEDR_OSPEEDR2_1   ((uint32_t)0x00000020)
 #define GPIO_OSPEEDR_OSPEEDR3     ((uint32_t)0x000000C0)
 #define GPIO_OSPEEDR_OSPEEDR3_0   ((uint32_t)0x00000040)
 #define GPIO_OSPEEDR_OSPEEDR3_1   ((uint32_t)0x00000080)
 #define GPIO_OSPEEDR_OSPEEDR4     ((uint32_t)0x00000300)
 #define GPIO_OSPEEDR_OSPEEDR4_0   ((uint32_t)0x00000100)
 #define GPIO_OSPEEDR_OSPEEDR4_1   ((uint32_t)0x00000200)
 #define GPIO_OSPEEDR_OSPEEDR5     ((uint32_t)0x00000C00)
 #define GPIO_OSPEEDR_OSPEEDR5_0   ((uint32_t)0x00000400)
 #define GPIO_OSPEEDR_OSPEEDR5_1   ((uint32_t)0x00000800)
 #define GPIO_OSPEEDR_OSPEEDR6     ((uint32_t)0x00003000)
 #define GPIO_OSPEEDR_OSPEEDR6_0   ((uint32_t)0x00001000)
 #define GPIO_OSPEEDR_OSPEEDR6_1   ((uint32_t)0x00002000)
 #define GPIO_OSPEEDR_OSPEEDR7     ((uint32_t)0x0000C000)
 #define GPIO_OSPEEDR_OSPEEDR7_0   ((uint32_t)0x00004000)
 #define GPIO_OSPEEDR_OSPEEDR7_1   ((uint32_t)0x00008000)
 #define GPIO_OSPEEDR_OSPEEDR8     ((uint32_t)0x00030000)
 #define GPIO_OSPEEDR_OSPEEDR8_0   ((uint32_t)0x00010000)
 #define GPIO_OSPEEDR_OSPEEDR8_1   ((uint32_t)0x00020000)
 #define GPIO_OSPEEDR_OSPEEDR9     ((uint32_t)0x000C0000)
 #define GPIO_OSPEEDR_OSPEEDR9_0   ((uint32_t)0x00040000)
 #define GPIO_OSPEEDR_OSPEEDR9_1   ((uint32_t)0x00080000)
 #define GPIO_OSPEEDR_OSPEEDR10    ((uint32_t)0x00300000)
 #define GPIO_OSPEEDR_OSPEEDR10_0  ((uint32_t)0x00100000)
 #define GPIO_OSPEEDR_OSPEEDR10_1  ((uint32_t)0x00200000)
 #define GPIO_OSPEEDR_OSPEEDR11    ((uint32_t)0x00C00000)
 #define GPIO_OSPEEDR_OSPEEDR11_0  ((uint32_t)0x00400000)
 #define GPIO_OSPEEDR_OSPEEDR11_1  ((uint32_t)0x00800000)
 #define GPIO_OSPEEDR_OSPEEDR12    ((uint32_t)0x03000000)
 #define GPIO_OSPEEDR_OSPEEDR12_0  ((uint32_t)0x01000000)
 #define GPIO_OSPEEDR_OSPEEDR12_1  ((uint32_t)0x02000000)
 #define GPIO_OSPEEDR_OSPEEDR13    ((uint32_t)0x0C000000)
 #define GPIO_OSPEEDR_OSPEEDR13_0  ((uint32_t)0x04000000)
 #define GPIO_OSPEEDR_OSPEEDR13_1  ((uint32_t)0x08000000)
 #define GPIO_OSPEEDR_OSPEEDR14    ((uint32_t)0x30000000)
 #define GPIO_OSPEEDR_OSPEEDR14_0  ((uint32_t)0x10000000)
 #define GPIO_OSPEEDR_OSPEEDR14_1  ((uint32_t)0x20000000)
 #define GPIO_OSPEEDR_OSPEEDR15    ((uint32_t)0xC0000000)
 #define GPIO_OSPEEDR_OSPEEDR15_0  ((uint32_t)0x40000000)
 #define GPIO_OSPEEDR_OSPEEDR15_1  ((uint32_t)0x80000000)
 /* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
 #define GPIO_OSPEEDER_OSPEEDR0     GPIO_OSPEEDR_OSPEEDR0
 #define GPIO_OSPEEDER_OSPEEDR0_0   GPIO_OSPEEDR_OSPEEDR0_0
 #define GPIO_OSPEEDER_OSPEEDR0_1   GPIO_OSPEEDR_OSPEEDR0_1
 #define GPIO_OSPEEDER_OSPEEDR1     GPIO_OSPEEDR_OSPEEDR1
 #define GPIO_OSPEEDER_OSPEEDR1_0   GPIO_OSPEEDR_OSPEEDR1_0
 #define GPIO_OSPEEDER_OSPEEDR1_1   GPIO_OSPEEDR_OSPEEDR1_1
 #define GPIO_OSPEEDER_OSPEEDR2     GPIO_OSPEEDR_OSPEEDR2
 #define GPIO_OSPEEDER_OSPEEDR2_0   GPIO_OSPEEDR_OSPEEDR2_0
 #define GPIO_OSPEEDER_OSPEEDR2_1   GPIO_OSPEEDR_OSPEEDR2_1
 #define GPIO_OSPEEDER_OSPEEDR3     GPIO_OSPEEDR_OSPEEDR3
 #define GPIO_OSPEEDER_OSPEEDR3_0   GPIO_OSPEEDR_OSPEEDR3_0
 #define GPIO_OSPEEDER_OSPEEDR3_1   GPIO_OSPEEDR_OSPEEDR3_1
 #define GPIO_OSPEEDER_OSPEEDR4     GPIO_OSPEEDR_OSPEEDR4
 #define GPIO_OSPEEDER_OSPEEDR4_0   GPIO_OSPEEDR_OSPEEDR4_0
 #define GPIO_OSPEEDER_OSPEEDR4_1   GPIO_OSPEEDR_OSPEEDR4_1
 #define GPIO_OSPEEDER_OSPEEDR5     GPIO_OSPEEDR_OSPEEDR5
 #define GPIO_OSPEEDER_OSPEEDR5_0   GPIO_OSPEEDR_OSPEEDR5_0
 #define GPIO_OSPEEDER_OSPEEDR5_1   GPIO_OSPEEDR_OSPEEDR5_1
 #define GPIO_OSPEEDER_OSPEEDR6     GPIO_OSPEEDR_OSPEEDR6
 #define GPIO_OSPEEDER_OSPEEDR6_0   GPIO_OSPEEDR_OSPEEDR6_0
 #define GPIO_OSPEEDER_OSPEEDR6_1   GPIO_OSPEEDR_OSPEEDR6_1
 #define GPIO_OSPEEDER_OSPEEDR7     GPIO_OSPEEDR_OSPEEDR7
 #define GPIO_OSPEEDER_OSPEEDR7_0   GPIO_OSPEEDR_OSPEEDR7_0
 #define GPIO_OSPEEDER_OSPEEDR7_1   GPIO_OSPEEDR_OSPEEDR7_1
 #define GPIO_OSPEEDER_OSPEEDR8     GPIO_OSPEEDR_OSPEEDR8
 #define GPIO_OSPEEDER_OSPEEDR8_0   GPIO_OSPEEDR_OSPEEDR8_0
 #define GPIO_OSPEEDER_OSPEEDR8_1   GPIO_OSPEEDR_OSPEEDR8_1
 #define GPIO_OSPEEDER_OSPEEDR9     GPIO_OSPEEDR_OSPEEDR9
 #define GPIO_OSPEEDER_OSPEEDR9_0   GPIO_OSPEEDR_OSPEEDR9_0
 #define GPIO_OSPEEDER_OSPEEDR9_1   GPIO_OSPEEDR_OSPEEDR9_1
 #define GPIO_OSPEEDER_OSPEEDR10    GPIO_OSPEEDR_OSPEEDR10
 #define GPIO_OSPEEDER_OSPEEDR10_0  GPIO_OSPEEDR_OSPEEDR10_0
 #define GPIO_OSPEEDER_OSPEEDR10_1  GPIO_OSPEEDR_OSPEEDR10_1
 #define GPIO_OSPEEDER_OSPEEDR11    GPIO_OSPEEDR_OSPEEDR11
 #define GPIO_OSPEEDER_OSPEEDR11_0  GPIO_OSPEEDR_OSPEEDR11_0
 #define GPIO_OSPEEDER_OSPEEDR11_1  GPIO_OSPEEDR_OSPEEDR11_1
 #define GPIO_OSPEEDER_OSPEEDR12    GPIO_OSPEEDR_OSPEEDR12
 #define GPIO_OSPEEDER_OSPEEDR12_0  GPIO_OSPEEDR_OSPEEDR12_0
 #define GPIO_OSPEEDER_OSPEEDR12_1  GPIO_OSPEEDR_OSPEEDR12_1
 #define GPIO_OSPEEDER_OSPEEDR13    GPIO_OSPEEDR_OSPEEDR13
 #define GPIO_OSPEEDER_OSPEEDR13_0  GPIO_OSPEEDR_OSPEEDR13_0
 #define GPIO_OSPEEDER_OSPEEDR13_1  GPIO_OSPEEDR_OSPEEDR13_1
 #define GPIO_OSPEEDER_OSPEEDR14    GPIO_OSPEEDR_OSPEEDR14
 #define GPIO_OSPEEDER_OSPEEDR14_0  GPIO_OSPEEDR_OSPEEDR14_0
 #define GPIO_OSPEEDER_OSPEEDR14_1  GPIO_OSPEEDR_OSPEEDR14_1
 #define GPIO_OSPEEDER_OSPEEDR15    GPIO_OSPEEDR_OSPEEDR15
 #define GPIO_OSPEEDER_OSPEEDR15_0  GPIO_OSPEEDR_OSPEEDR15_0
 #define GPIO_OSPEEDER_OSPEEDR15_1  GPIO_OSPEEDR_OSPEEDR15_1
 /*******************  Bit definition for GPIO_PUPDR register ******************/
 #define GPIO_PUPDR_PUPDR0          ((uint32_t)0x00000003)
 #define GPIO_PUPDR_PUPDR0_0        ((uint32_t)0x00000001)
 #define GPIO_PUPDR_PUPDR0_1        ((uint32_t)0x00000002)
 #define GPIO_PUPDR_PUPDR1          ((uint32_t)0x0000000C)
 #define GPIO_PUPDR_PUPDR1_0        ((uint32_t)0x00000004)
 #define GPIO_PUPDR_PUPDR1_1        ((uint32_t)0x00000008)
 #define GPIO_PUPDR_PUPDR2          ((uint32_t)0x00000030)
 #define GPIO_PUPDR_PUPDR2_0        ((uint32_t)0x00000010)
 #define GPIO_PUPDR_PUPDR2_1        ((uint32_t)0x00000020)
 #define GPIO_PUPDR_PUPDR3          ((uint32_t)0x000000C0)
 #define GPIO_PUPDR_PUPDR3_0        ((uint32_t)0x00000040)
 #define GPIO_PUPDR_PUPDR3_1        ((uint32_t)0x00000080)
 #define GPIO_PUPDR_PUPDR4          ((uint32_t)0x00000300)
 #define GPIO_PUPDR_PUPDR4_0        ((uint32_t)0x00000100)
 #define GPIO_PUPDR_PUPDR4_1        ((uint32_t)0x00000200)
 #define GPIO_PUPDR_PUPDR5          ((uint32_t)0x00000C00)
 #define GPIO_PUPDR_PUPDR5_0        ((uint32_t)0x00000400)
 #define GPIO_PUPDR_PUPDR5_1        ((uint32_t)0x00000800)
 #define GPIO_PUPDR_PUPDR6          ((uint32_t)0x00003000)
 #define GPIO_PUPDR_PUPDR6_0        ((uint32_t)0x00001000)
 #define GPIO_PUPDR_PUPDR6_1        ((uint32_t)0x00002000)
 #define GPIO_PUPDR_PUPDR7          ((uint32_t)0x0000C000)
 #define GPIO_PUPDR_PUPDR7_0        ((uint32_t)0x00004000)
 #define GPIO_PUPDR_PUPDR7_1        ((uint32_t)0x00008000)
 #define GPIO_PUPDR_PUPDR8          ((uint32_t)0x00030000)
 #define GPIO_PUPDR_PUPDR8_0        ((uint32_t)0x00010000)
 #define GPIO_PUPDR_PUPDR8_1        ((uint32_t)0x00020000)
 #define GPIO_PUPDR_PUPDR9          ((uint32_t)0x000C0000)
 #define GPIO_PUPDR_PUPDR9_0        ((uint32_t)0x00040000)
 #define GPIO_PUPDR_PUPDR9_1        ((uint32_t)0x00080000)
 #define GPIO_PUPDR_PUPDR10         ((uint32_t)0x00300000)
 #define GPIO_PUPDR_PUPDR10_0       ((uint32_t)0x00100000)
 #define GPIO_PUPDR_PUPDR10_1       ((uint32_t)0x00200000)
 #define GPIO_PUPDR_PUPDR11         ((uint32_t)0x00C00000)
 #define GPIO_PUPDR_PUPDR11_0       ((uint32_t)0x00400000)
 #define GPIO_PUPDR_PUPDR11_1       ((uint32_t)0x00800000)
 #define GPIO_PUPDR_PUPDR12         ((uint32_t)0x03000000)
 #define GPIO_PUPDR_PUPDR12_0       ((uint32_t)0x01000000)
 #define GPIO_PUPDR_PUPDR12_1       ((uint32_t)0x02000000)
 #define GPIO_PUPDR_PUPDR13         ((uint32_t)0x0C000000)
 #define GPIO_PUPDR_PUPDR13_0       ((uint32_t)0x04000000)
 #define GPIO_PUPDR_PUPDR13_1       ((uint32_t)0x08000000)
 #define GPIO_PUPDR_PUPDR14         ((uint32_t)0x30000000)
 #define GPIO_PUPDR_PUPDR14_0       ((uint32_t)0x10000000)
 #define GPIO_PUPDR_PUPDR14_1       ((uint32_t)0x20000000)
 #define GPIO_PUPDR_PUPDR15         ((uint32_t)0xC0000000)
 #define GPIO_PUPDR_PUPDR15_0       ((uint32_t)0x40000000)
 #define GPIO_PUPDR_PUPDR15_1       ((uint32_t)0x80000000)
 /*******************  Bit definition for GPIO_IDR register  *******************/
 #define GPIO_IDR_0                 ((uint32_t)0x00000001)
 #define GPIO_IDR_1                 ((uint32_t)0x00000002)
 #define GPIO_IDR_2                 ((uint32_t)0x00000004)
 #define GPIO_IDR_3                 ((uint32_t)0x00000008)
 #define GPIO_IDR_4                 ((uint32_t)0x00000010)
 #define GPIO_IDR_5                 ((uint32_t)0x00000020)
 #define GPIO_IDR_6                 ((uint32_t)0x00000040)
 #define GPIO_IDR_7                 ((uint32_t)0x00000080)
 #define GPIO_IDR_8                 ((uint32_t)0x00000100)
 #define GPIO_IDR_9                 ((uint32_t)0x00000200)
 #define GPIO_IDR_10                ((uint32_t)0x00000400)
 #define GPIO_IDR_11                ((uint32_t)0x00000800)
 #define GPIO_IDR_12                ((uint32_t)0x00001000)
 #define GPIO_IDR_13                ((uint32_t)0x00002000)
 #define GPIO_IDR_14                ((uint32_t)0x00004000)
 #define GPIO_IDR_15                ((uint32_t)0x00008000)
 /******************  Bit definition for GPIO_ODR register  ********************/
 #define GPIO_ODR_0                 ((uint32_t)0x00000001)
 #define GPIO_ODR_1                 ((uint32_t)0x00000002)
 #define GPIO_ODR_2                 ((uint32_t)0x00000004)
 #define GPIO_ODR_3                 ((uint32_t)0x00000008)
 #define GPIO_ODR_4                 ((uint32_t)0x00000010)
 #define GPIO_ODR_5                 ((uint32_t)0x00000020)
 #define GPIO_ODR_6                 ((uint32_t)0x00000040)
 #define GPIO_ODR_7                 ((uint32_t)0x00000080)
 #define GPIO_ODR_8                 ((uint32_t)0x00000100)
 #define GPIO_ODR_9                 ((uint32_t)0x00000200)
 #define GPIO_ODR_10                ((uint32_t)0x00000400)
 #define GPIO_ODR_11                ((uint32_t)0x00000800)
 #define GPIO_ODR_12                ((uint32_t)0x00001000)
 #define GPIO_ODR_13                ((uint32_t)0x00002000)
 #define GPIO_ODR_14                ((uint32_t)0x00004000)
 #define GPIO_ODR_15                ((uint32_t)0x00008000)
 /****************** Bit definition for GPIO_BSRR register  ********************/
 #define GPIO_BSRR_BS_0             ((uint32_t)0x00000001)
 #define GPIO_BSRR_BS_1             ((uint32_t)0x00000002)
 #define GPIO_BSRR_BS_2             ((uint32_t)0x00000004)
 #define GPIO_BSRR_BS_3             ((uint32_t)0x00000008)
 #define GPIO_BSRR_BS_4             ((uint32_t)0x00000010)
 #define GPIO_BSRR_BS_5             ((uint32_t)0x00000020)
 #define GPIO_BSRR_BS_6             ((uint32_t)0x00000040)
 #define GPIO_BSRR_BS_7             ((uint32_t)0x00000080)
 #define GPIO_BSRR_BS_8             ((uint32_t)0x00000100)
 #define GPIO_BSRR_BS_9             ((uint32_t)0x00000200)
 #define GPIO_BSRR_BS_10            ((uint32_t)0x00000400)
 #define GPIO_BSRR_BS_11            ((uint32_t)0x00000800)
 #define GPIO_BSRR_BS_12            ((uint32_t)0x00001000)
 #define GPIO_BSRR_BS_13            ((uint32_t)0x00002000)
 #define GPIO_BSRR_BS_14            ((uint32_t)0x00004000)
 #define GPIO_BSRR_BS_15            ((uint32_t)0x00008000)
 #define GPIO_BSRR_BR_0             ((uint32_t)0x00010000)
 #define GPIO_BSRR_BR_1             ((uint32_t)0x00020000)
 #define GPIO_BSRR_BR_2             ((uint32_t)0x00040000)
 #define GPIO_BSRR_BR_3             ((uint32_t)0x00080000)
 #define GPIO_BSRR_BR_4             ((uint32_t)0x00100000)
 #define GPIO_BSRR_BR_5             ((uint32_t)0x00200000)
 #define GPIO_BSRR_BR_6             ((uint32_t)0x00400000)
 #define GPIO_BSRR_BR_7             ((uint32_t)0x00800000)
 #define GPIO_BSRR_BR_8             ((uint32_t)0x01000000)
 #define GPIO_BSRR_BR_9             ((uint32_t)0x02000000)
 #define GPIO_BSRR_BR_10            ((uint32_t)0x04000000)
 #define GPIO_BSRR_BR_11            ((uint32_t)0x08000000)
 #define GPIO_BSRR_BR_12            ((uint32_t)0x10000000)
 #define GPIO_BSRR_BR_13            ((uint32_t)0x20000000)
 #define GPIO_BSRR_BR_14            ((uint32_t)0x40000000)
 #define GPIO_BSRR_BR_15            ((uint32_t)0x80000000)
 /****************** Bit definition for GPIO_LCKR register  ********************/
 #define GPIO_LCKR_LCK0             ((uint32_t)0x00000001)
 #define GPIO_LCKR_LCK1             ((uint32_t)0x00000002)
 #define GPIO_LCKR_LCK2             ((uint32_t)0x00000004)
 #define GPIO_LCKR_LCK3             ((uint32_t)0x00000008)
 #define GPIO_LCKR_LCK4             ((uint32_t)0x00000010)
 #define GPIO_LCKR_LCK5             ((uint32_t)0x00000020)
 #define GPIO_LCKR_LCK6             ((uint32_t)0x00000040)
 #define GPIO_LCKR_LCK7             ((uint32_t)0x00000080)
 #define GPIO_LCKR_LCK8             ((uint32_t)0x00000100)
 #define GPIO_LCKR_LCK9             ((uint32_t)0x00000200)
 #define GPIO_LCKR_LCK10            ((uint32_t)0x00000400)
 #define GPIO_LCKR_LCK11            ((uint32_t)0x00000800)
 #define GPIO_LCKR_LCK12            ((uint32_t)0x00001000)
 #define GPIO_LCKR_LCK13            ((uint32_t)0x00002000)
 #define GPIO_LCKR_LCK14            ((uint32_t)0x00004000)
 #define GPIO_LCKR_LCK15            ((uint32_t)0x00008000)
 #define GPIO_LCKR_LCKK             ((uint32_t)0x00010000)
 /****************** Bit definition for GPIO_AFRL register  ********************/
 #define GPIO_AFRL_AFR0            ((uint32_t)0x0000000F)
 #define GPIO_AFRL_AFR1            ((uint32_t)0x000000F0)
 #define GPIO_AFRL_AFR2            ((uint32_t)0x00000F00)
 #define GPIO_AFRL_AFR3            ((uint32_t)0x0000F000)
 #define GPIO_AFRL_AFR4            ((uint32_t)0x000F0000)
 #define GPIO_AFRL_AFR5            ((uint32_t)0x00F00000)
 #define GPIO_AFRL_AFR6            ((uint32_t)0x0F000000)
 #define GPIO_AFRL_AFR7            ((uint32_t)0xF0000000)
 /****************** Bit definition for GPIO_AFRH register  ********************/
 #define GPIO_AFRH_AFR8            ((uint32_t)0x0000000F)
 #define GPIO_AFRH_AFR9            ((uint32_t)0x000000F0)
 #define GPIO_AFRH_AFR10            ((uint32_t)0x00000F00)
 #define GPIO_AFRH_AFR11            ((uint32_t)0x0000F000)
 #define GPIO_AFRH_AFR12            ((uint32_t)0x000F0000)
 #define GPIO_AFRH_AFR13            ((uint32_t)0x00F00000)
 #define GPIO_AFRH_AFR14            ((uint32_t)0x0F000000)
 #define GPIO_AFRH_AFR15            ((uint32_t)0xF0000000)
 /* Old Bit definition for GPIO_AFRL register maintained for legacy purpose ****/
 #define GPIO_AFRL_AFRL0            GPIO_AFRL_AFR0
 #define GPIO_AFRL_AFRL1            GPIO_AFRL_AFR1
 #define GPIO_AFRL_AFRL2            GPIO_AFRL_AFR2
 #define GPIO_AFRL_AFRL3            GPIO_AFRL_AFR3
 #define GPIO_AFRL_AFRL4            GPIO_AFRL_AFR4
 #define GPIO_AFRL_AFRL5            GPIO_AFRL_AFR5
 #define GPIO_AFRL_AFRL6            GPIO_AFRL_AFR6
 #define GPIO_AFRL_AFRL7            GPIO_AFRL_AFR7
 /* Old Bit definition for GPIO_AFRH register maintained for legacy purpose ****/
 #define GPIO_AFRH_AFRH0            GPIO_AFRH_AFR8
 #define GPIO_AFRH_AFRH1            GPIO_AFRH_AFR9
 #define GPIO_AFRH_AFRH2            GPIO_AFRH_AFR10
 #define GPIO_AFRH_AFRH3            GPIO_AFRH_AFR11
 #define GPIO_AFRH_AFRH4            GPIO_AFRH_AFR12
 #define GPIO_AFRH_AFRH5            GPIO_AFRH_AFR13
 #define GPIO_AFRH_AFRH6            GPIO_AFRH_AFR14
 #define GPIO_AFRH_AFRH7            GPIO_AFRH_AFR15
 /****************** Bit definition for GPIO_BRR register  *********************/
 #define GPIO_BRR_BR_0              ((uint32_t)0x00000001)
 #define GPIO_BRR_BR_1              ((uint32_t)0x00000002)
 #define GPIO_BRR_BR_2              ((uint32_t)0x00000004)
 #define GPIO_BRR_BR_3              ((uint32_t)0x00000008)
 #define GPIO_BRR_BR_4              ((uint32_t)0x00000010)
 #define GPIO_BRR_BR_5              ((uint32_t)0x00000020)
 #define GPIO_BRR_BR_6              ((uint32_t)0x00000040)
 #define GPIO_BRR_BR_7              ((uint32_t)0x00000080)
 #define GPIO_BRR_BR_8              ((uint32_t)0x00000100)
 #define GPIO_BRR_BR_9              ((uint32_t)0x00000200)
 #define GPIO_BRR_BR_10             ((uint32_t)0x00000400)
 #define GPIO_BRR_BR_11             ((uint32_t)0x00000800)
 #define GPIO_BRR_BR_12             ((uint32_t)0x00001000)
 #define GPIO_BRR_BR_13             ((uint32_t)0x00002000)
 #define GPIO_BRR_BR_14             ((uint32_t)0x00004000)
 #define GPIO_BRR_BR_15             ((uint32_t)0x00008000)
 /******************************************************************************/
 /*                                                                            */
 /*                   Inter-integrated Circuit Interface (I2C)                 */
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for I2C_CR1 register  *******************/
 #define  I2C_CR1_PE                          ((uint32_t)0x00000001)        /*!< Peripheral enable */
 #define  I2C_CR1_TXIE                        ((uint32_t)0x00000002)        /*!< TX interrupt enable */
 #define  I2C_CR1_RXIE                        ((uint32_t)0x00000004)        /*!< RX interrupt enable */
 #define  I2C_CR1_ADDRIE                      ((uint32_t)0x00000008)        /*!< Address match interrupt enable */
 #define  I2C_CR1_NACKIE                      ((uint32_t)0x00000010)        /*!< NACK received interrupt enable */
 #define  I2C_CR1_STOPIE                      ((uint32_t)0x00000020)        /*!< STOP detection interrupt enable */
 #define  I2C_CR1_TCIE                        ((uint32_t)0x00000040)        /*!< Transfer complete interrupt enable */
 #define  I2C_CR1_ERRIE                       ((uint32_t)0x00000080)        /*!< Errors interrupt enable */
 #define  I2C_CR1_DFN                         ((uint32_t)0x00000F00)        /*!< Digital noise filter */
 #define  I2C_CR1_ANFOFF                      ((uint32_t)0x00001000)        /*!< Analog noise filter OFF */
 #define  I2C_CR1_SWRST                       ((uint32_t)0x00002000)        /*!< Software reset */
 #define  I2C_CR1_TXDMAEN                     ((uint32_t)0x00004000)        /*!< DMA transmission requests enable */
 #define  I2C_CR1_RXDMAEN                     ((uint32_t)0x00008000)        /*!< DMA reception requests enable */
 #define  I2C_CR1_SBC                         ((uint32_t)0x00010000)        /*!< Slave byte control */
 #define  I2C_CR1_NOSTRETCH                   ((uint32_t)0x00020000)        /*!< Clock stretching disable */
 #define  I2C_CR1_WUPEN                       ((uint32_t)0x00040000)        /*!< Wakeup from STOP enable */
 #define  I2C_CR1_GCEN                        ((uint32_t)0x00080000)        /*!< General call enable */
 #define  I2C_CR1_SMBHEN                      ((uint32_t)0x00100000)        /*!< SMBus host address enable */
 #define  I2C_CR1_SMBDEN                      ((uint32_t)0x00200000)        /*!< SMBus device default address enable */
 #define  I2C_CR1_ALERTEN                     ((uint32_t)0x00400000)        /*!< SMBus alert enable */
 #define  I2C_CR1_PECEN                       ((uint32_t)0x00800000)        /*!< PEC enable */
 /******************  Bit definition for I2C_CR2 register  ********************/
 #define  I2C_CR2_SADD                        ((uint32_t)0x000003FF)        /*!< Slave address (master mode) */
 #define  I2C_CR2_RD_WRN                      ((uint32_t)0x00000400)        /*!< Transfer direction (master mode) */
 #define  I2C_CR2_ADD10                       ((uint32_t)0x00000800)        /*!< 10-bit addressing mode (master mode) */
 #define  I2C_CR2_HEAD10R                     ((uint32_t)0x00001000)        /*!< 10-bit address header only read direction (master mode) */
 #define  I2C_CR2_START                       ((uint32_t)0x00002000)        /*!< START generation */
 #define  I2C_CR2_STOP                        ((uint32_t)0x00004000)        /*!< STOP generation (master mode) */
 #define  I2C_CR2_NACK                        ((uint32_t)0x00008000)        /*!< NACK generation (slave mode) */
 #define  I2C_CR2_NBYTES                      ((uint32_t)0x00FF0000)        /*!< Number of bytes */
 #define  I2C_CR2_RELOAD                      ((uint32_t)0x01000000)        /*!< NBYTES reload mode */
 #define  I2C_CR2_AUTOEND                     ((uint32_t)0x02000000)        /*!< Automatic end mode (master mode) */
 #define  I2C_CR2_PECBYTE                     ((uint32_t)0x04000000)        /*!< Packet error checking byte */
 /*******************  Bit definition for I2C_OAR1 register  ******************/
 #define  I2C_OAR1_OA1                        ((uint32_t)0x000003FF)        /*!< Interface own address 1 */
 #define  I2C_OAR1_OA1MODE                    ((uint32_t)0x00000400)        /*!< Own address 1 10-bit mode */
 #define  I2C_OAR1_OA1EN                      ((uint32_t)0x00008000)        /*!< Own address 1 enable */
 /*******************  Bit definition for I2C_OAR2 register  ******************/
 #define  I2C_OAR2_OA2                        ((uint32_t)0x000000FE)        /*!< Interface own address 2 */
 #define  I2C_OAR2_OA2MSK                     ((uint32_t)0x00000700)        /*!< Own address 2 masks */
 #define  I2C_OAR2_OA2EN                      ((uint32_t)0x00008000)        /*!< Own address 2 enable */
 /*******************  Bit definition for I2C_TIMINGR register *******************/
 #define  I2C_TIMINGR_SCLL                    ((uint32_t)0x000000FF)        /*!< SCL low period (master mode) */
 #define  I2C_TIMINGR_SCLH                    ((uint32_t)0x0000FF00)        /*!< SCL high period (master mode) */
 #define  I2C_TIMINGR_SDADEL                  ((uint32_t)0x000F0000)        /*!< Data hold time */
 #define  I2C_TIMINGR_SCLDEL                  ((uint32_t)0x00F00000)        /*!< Data setup time */
 #define  I2C_TIMINGR_PRESC                   ((uint32_t)0xF0000000)        /*!< Timings prescaler */
 /******************* Bit definition for I2C_TIMEOUTR register *******************/
 #define  I2C_TIMEOUTR_TIMEOUTA               ((uint32_t)0x00000FFF)        /*!< Bus timeout A */
 #define  I2C_TIMEOUTR_TIDLE                  ((uint32_t)0x00001000)        /*!< Idle clock timeout detection */
 #define  I2C_TIMEOUTR_TIMOUTEN               ((uint32_t)0x00008000)        /*!< Clock timeout enable */
 #define  I2C_TIMEOUTR_TIMEOUTB               ((uint32_t)0x0FFF0000)        /*!< Bus timeout B*/
 #define  I2C_TIMEOUTR_TEXTEN                 ((uint32_t)0x80000000)        /*!< Extended clock timeout enable */
 /******************  Bit definition for I2C_ISR register  *********************/
 #define  I2C_ISR_TXE                         ((uint32_t)0x00000001)        /*!< Transmit data register empty */
 #define  I2C_ISR_TXIS                        ((uint32_t)0x00000002)        /*!< Transmit interrupt status */
 #define  I2C_ISR_RXNE                        ((uint32_t)0x00000004)        /*!< Receive data register not empty */
 #define  I2C_ISR_ADDR                        ((uint32_t)0x00000008)        /*!< Address matched (slave mode)*/
 #define  I2C_ISR_NACKF                       ((uint32_t)0x00000010)        /*!< NACK received flag */
 #define  I2C_ISR_STOPF                       ((uint32_t)0x00000020)        /*!< STOP detection flag */
 #define  I2C_ISR_TC                          ((uint32_t)0x00000040)        /*!< Transfer complete (master mode) */
 #define  I2C_ISR_TCR                         ((uint32_t)0x00000080)        /*!< Transfer complete reload */
 #define  I2C_ISR_BERR                        ((uint32_t)0x00000100)        /*!< Bus error */
 #define  I2C_ISR_ARLO                        ((uint32_t)0x00000200)        /*!< Arbitration lost */
 #define  I2C_ISR_OVR                         ((uint32_t)0x00000400)        /*!< Overrun/Underrun */
 #define  I2C_ISR_PECERR                      ((uint32_t)0x00000800)        /*!< PEC error in reception */
 #define  I2C_ISR_TIMEOUT                     ((uint32_t)0x00001000)        /*!< Timeout or Tlow detection flag */
 #define  I2C_ISR_ALERT                       ((uint32_t)0x00002000)        /*!< SMBus alert */
 #define  I2C_ISR_BUSY                        ((uint32_t)0x00008000)        /*!< Bus busy */
 #define  I2C_ISR_DIR                         ((uint32_t)0x00010000)        /*!< Transfer direction (slave mode) */
 #define  I2C_ISR_ADDCODE                     ((uint32_t)0x00FE0000)        /*!< Address match code (slave mode) */
 /******************  Bit definition for I2C_ICR register  *********************/
 #define  I2C_ICR_ADDRCF                      ((uint32_t)0x00000008)        /*!< Address matched clear flag */
 #define  I2C_ICR_NACKCF                      ((uint32_t)0x00000010)        /*!< NACK clear flag */
 #define  I2C_ICR_STOPCF                      ((uint32_t)0x00000020)        /*!< STOP detection clear flag */
 #define  I2C_ICR_BERRCF                      ((uint32_t)0x00000100)        /*!< Bus error clear flag */
 #define  I2C_ICR_ARLOCF                      ((uint32_t)0x00000200)        /*!< Arbitration lost clear flag */
 #define  I2C_ICR_OVRCF                       ((uint32_t)0x00000400)        /*!< Overrun/Underrun clear flag */
 #define  I2C_ICR_PECCF                       ((uint32_t)0x00000800)        /*!< PAC error clear flag */
 #define  I2C_ICR_TIMOUTCF                    ((uint32_t)0x00001000)        /*!< Timeout clear flag */
 #define  I2C_ICR_ALERTCF                     ((uint32_t)0x00002000)        /*!< Alert clear flag */
 /******************  Bit definition for I2C_PECR register  *********************/
 #define  I2C_PECR_PEC                        ((uint32_t)0x000000FF)       /*!< PEC register */
 /******************  Bit definition for I2C_RXDR register  *********************/
 #define  I2C_RXDR_RXDATA                     ((uint32_t)0x000000FF)        /*!< 8-bit receive data */
 /******************  Bit definition for I2C_TXDR register  *********************/
 #define  I2C_TXDR_TXDATA                     ((uint32_t)0x000000FF)        /*!< 8-bit transmit data */
 /******************************************************************************/
 /*                                                                            */
 /*                        Independent WATCHDOG (IWDG)                         */
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for IWDG_KR register  ********************/
 #define  IWDG_KR_KEY                         ((uint16_t)0xFFFF)            /*!< Key value (write only, read 0000h) */
 /*******************  Bit definition for IWDG_PR register  ********************/
 #define  IWDG_PR_PR                          ((uint8_t)0x07)               /*!< PR[2:0] (Prescaler divider) */
 #define  IWDG_PR_PR_0                        ((uint8_t)0x01)               /*!< Bit 0 */
 #define  IWDG_PR_PR_1                        ((uint8_t)0x02)               /*!< Bit 1 */
 #define  IWDG_PR_PR_2                        ((uint8_t)0x04)               /*!< Bit 2 */
 /*******************  Bit definition for IWDG_RLR register  *******************/
 #define  IWDG_RLR_RL                         ((uint16_t)0x0FFF)            /*!< Watchdog counter reload value */
 /*******************  Bit definition for IWDG_SR register  ********************/
 #define  IWDG_SR_PVU                         ((uint8_t)0x01)               /*!< Watchdog prescaler value update */
 #define  IWDG_SR_RVU                         ((uint8_t)0x02)               /*!< Watchdog counter reload value update */
 #define  IWDG_SR_WVU                         ((uint8_t)0x04)               /*!< Watchdog counter window value update */
 /*******************  Bit definition for IWDG_KR register  ********************/
 #define  IWDG_WINR_WIN                         ((uint16_t)0x0FFF)            /*!< Watchdog counter window value */
 /******************************************************************************/
 /*                                                                            */
 /*                          Power Control (PWR)                               */
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for PWR_CR register  ********************/
 #define  PWR_CR_LPDS                         ((uint16_t)0x0001)     /*!< Low-power deepsleep/sleep */
 #define  PWR_CR_PDDS                         ((uint16_t)0x0002)     /*!< Power Down Deepsleep */
 #define  PWR_CR_CWUF                         ((uint16_t)0x0004)     /*!< Clear Wakeup Flag */
 #define  PWR_CR_CSBF                         ((uint16_t)0x0008)     /*!< Clear Standby Flag */
 #define  PWR_CR_PVDE                         ((uint16_t)0x0010)     /*!< Power Voltage Detector Enable */
 #define  PWR_CR_PLS                          ((uint16_t)0x00E0)     /*!< PLS[2:0] bits (PVD Level Selection) */
 #define  PWR_CR_PLS_0                        ((uint16_t)0x0020)     /*!< Bit 0 */
 #define  PWR_CR_PLS_1                        ((uint16_t)0x0040)     /*!< Bit 1 */
 #define  PWR_CR_PLS_2                        ((uint16_t)0x0080)     /*!< Bit 2 */
 /* PVD level configuration */
 #define  PWR_CR_PLS_LEV0                     ((uint16_t)0x0000)     /*!< PVD level 0 */
 #define  PWR_CR_PLS_LEV1                     ((uint16_t)0x0020)     /*!< PVD level 1 */
 #define  PWR_CR_PLS_LEV2                     ((uint16_t)0x0040)     /*!< PVD level 2 */
 #define  PWR_CR_PLS_LEV3                     ((uint16_t)0x0060)     /*!< PVD level 3 */
 #define  PWR_CR_PLS_LEV4                     ((uint16_t)0x0080)     /*!< PVD level 4 */
 #define  PWR_CR_PLS_LEV5                     ((uint16_t)0x00A0)     /*!< PVD level 5 */
 #define  PWR_CR_PLS_LEV6                     ((uint16_t)0x00C0)     /*!< PVD level 6 */
 #define  PWR_CR_PLS_LEV7                     ((uint16_t)0x00E0)     /*!< PVD level 7 */
 #define  PWR_CR_DBP                          ((uint16_t)0x0100)     /*!< Disable Backup Domain write protection */
 /* Old Bit definition maintained for legacy purpose ****/
 #define  PWR_CR_LPSDSR                       PWR_CR_LPDS     /*!< Low-power deepsleep */
 /*******************  Bit definition for PWR_CSR register  ********************/
 #define  PWR_CSR_WUF                         ((uint16_t)0x0001)     /*!< Wakeup Flag */
 #define  PWR_CSR_SBF                         ((uint16_t)0x0002)     /*!< Standby Flag */
 #define  PWR_CSR_PVDO                        ((uint16_t)0x0004)     /*!< PVD Output */
 #define  PWR_CSR_VREFINTRDY                  ((uint16_t)0x0008)     /*!< Internal voltage reference (VREFINT) ready */
 #define  PWR_CSR_EWUP1                       ((uint16_t)0x0100)     /*!< Enable WKUP pin 1 */
 #define  PWR_CSR_EWUP2                       ((uint16_t)0x0200)     /*!< Enable WKUP pin 2 */
 #define  PWR_CSR_EWUP3                       ((uint16_t)0x0400)     /*!< Enable WKUP pin 3 */
 #define  PWR_CSR_EWUP4                       ((uint16_t)0x0800)     /*!< Enable WKUP pin 4 */
 #define  PWR_CSR_EWUP5                       ((uint16_t)0x1000)     /*!< Enable WKUP pin 5 */
 #define  PWR_CSR_EWUP6                       ((uint16_t)0x2000)     /*!< Enable WKUP pin 6 */
 #define  PWR_CSR_EWUP7                       ((uint16_t)0x4000)     /*!< Enable WKUP pin 7 */
 #define  PWR_CSR_EWUP8                       ((uint16_t)0x8000)     /*!< Enable WKUP pin 8 */
 /* Old Bit definition maintained for legacy purpose ****/
 #define  PWR_CSR_VREFINTRDYF                 PWR_CSR_VREFINTRDY     /*!< Internal voltage reference (VREFINT) ready flag */
 /******************************************************************************/
 /*                                                                            */
 /*                         Reset and Clock Control                            */
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for RCC_CR register  ********************/
 #define  RCC_CR_HSION                        ((uint32_t)0x00000001)        /*!< Internal High Speed clock enable */
 #define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)        /*!< Internal High Speed clock ready flag */
 #define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8)        /*!< Internal High Speed clock trimming */
 #define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00)        /*!< Internal High Speed clock Calibration */
 #define  RCC_CR_HSEON                        ((uint32_t)0x00010000)        /*!< External High Speed clock enable */
 #define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)        /*!< External High Speed clock ready flag */
 #define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)        /*!< External High Speed clock Bypass */
 #define  RCC_CR_CSSON                        ((uint32_t)0x00080000)        /*!< Clock Security System enable */
 #define  RCC_CR_PLLON                        ((uint32_t)0x01000000)        /*!< PLL enable */
 #define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)        /*!< PLL clock ready flag */
 /*******************  Bit definition for RCC_CFGR register  *******************/
 #define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
 #define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
 #define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
 /* SW configuration */
 #define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000)        /*!< HSI selected as system clock */
 #define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001)        /*!< HSE selected as system clock */
 #define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002)        /*!< PLL selected as system clock */
 #define  RCC_CFGR_SW_HSI48                   ((uint32_t)0x00000003)        /*!< HSI48 selected as system clock */
 #define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
 #define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
 #define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
 /* SWS configuration */
 #define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000)        /*!< HSI oscillator used as system clock */
 #define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004)        /*!< HSE oscillator used as system clock */
 #define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008)        /*!< PLL used as system clock */
 #define  RCC_CFGR_SWS_HSI48                  ((uint32_t)0x0000000C)        /*!< HSI48 used as system clock */
 #define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
 #define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
 #define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
 #define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
 #define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
 /* HPRE configuration */
 #define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
 #define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
 #define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
 #define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
 #define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
 #define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
 #define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
 #define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
 #define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
 #define  RCC_CFGR_PPRE                       ((uint32_t)0x00000700)        /*!< PRE[2:0] bits (APB prescaler) */
 #define  RCC_CFGR_PPRE_0                     ((uint32_t)0x00000100)        /*!< Bit 0 */
 #define  RCC_CFGR_PPRE_1                     ((uint32_t)0x00000200)        /*!< Bit 1 */
 #define  RCC_CFGR_PPRE_2                     ((uint32_t)0x00000400)        /*!< Bit 2 */
 /* PPRE configuration */
 #define  RCC_CFGR_PPRE_DIV1                  ((uint32_t)0x00000000)        /*!< HCLK not divided */
 #define  RCC_CFGR_PPRE_DIV2                  ((uint32_t)0x00000400)        /*!< HCLK divided by 2 */
 #define  RCC_CFGR_PPRE_DIV4                  ((uint32_t)0x00000500)        /*!< HCLK divided by 4 */
 #define  RCC_CFGR_PPRE_DIV8                  ((uint32_t)0x00000600)        /*!< HCLK divided by 8 */
 #define  RCC_CFGR_PPRE_DIV16                 ((uint32_t)0x00000700)        /*!< HCLK divided by 16 */
 #define  RCC_CFGR_ADCPRE                     ((uint32_t)0x00004000)        /*!< ADC prescaler: Obsolete. Proper ADC clock selection is
                                                                                 done inside the ADC_CFGR2 */
 #define  RCC_CFGR_PLLSRC                     ((uint32_t)0x00018000)        /*!< PLL entry clock source */
 #define  RCC_CFGR_PLLSRC_0                   ((uint32_t)0x00008000)        /*!< Bit 0 (available only in the STM32F072 devices) */
 #define  RCC_CFGR_PLLSRC_1                   ((uint32_t)0x00010000)        /*!< Bit 1 */
 #define  RCC_CFGR_PLLSRC_PREDIV1             ((uint32_t)0x00010000)        /*!< PREDIV1 clock selected as PLL entry clock source;
                                                                                 Old PREDIV1 bit definition, maintained for legacy purpose */
 #define  RCC_CFGR_PLLSRC_HSI_DIV2            ((uint32_t)0x00000000)        /*!< HSI clock divided by 2 selected as PLL entry clock source */
 #define  RCC_CFGR_PLLSRC_HSI_PREDIV          ((uint32_t)0x00008000)        /*!< HSI PREDIV clock selected as PLL entry clock source
                                                                                 (This bit and configuration is only available for STM32F072 devices)*/
 #define  RCC_CFGR_PLLSRC_HSE_PREDIV          ((uint32_t)0x00010000)        /*!< HSE PREDIV clock selected as PLL entry clock source */
 #define  RCC_CFGR_PLLSRC_HSI48_PREDIV        ((uint32_t)0x00018000)        /*!< HSI48 PREDIV clock selected as PLL entry clock source */
 #define  RCC_CFGR_PLLXTPRE                   ((uint32_t)0x00020000)        /*!< HSE divider for PLL entry */
 #define  RCC_CFGR_PLLXTPRE_PREDIV1           ((uint32_t)0x00000000)        /*!< PREDIV1 clock not divided for PLL entry */
 #define  RCC_CFGR_PLLXTPRE_PREDIV1_Div2      ((uint32_t)0x00020000)        /*!< PREDIV1 clock divided by 2 for PLL entry */
 /*!< Old bit definition maintained for legacy purposes */
 #define  RCC_CFGR_PLLSRC_HSI_Div2            RCC_CFGR_PLLSRC_HSI_DIV2
 /* PLLMUL configuration */
 #define  RCC_CFGR_PLLMUL                    ((uint32_t)0x003C0000)        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
 #define  RCC_CFGR_PLLMUL_0                  ((uint32_t)0x00040000)        /*!< Bit 0 */
 #define  RCC_CFGR_PLLMUL_1                  ((uint32_t)0x00080000)        /*!< Bit 1 */
 #define  RCC_CFGR_PLLMUL_2                  ((uint32_t)0x00100000)        /*!< Bit 2 */
 #define  RCC_CFGR_PLLMUL_3                  ((uint32_t)0x00200000)        /*!< Bit 3 */
 #define  RCC_CFGR_PLLMUL2                   ((uint32_t)0x00000000)        /*!< PLL input clock*2 */
 #define  RCC_CFGR_PLLMUL3                   ((uint32_t)0x00040000)        /*!< PLL input clock*3 */
 #define  RCC_CFGR_PLLMUL4                   ((uint32_t)0x00080000)        /*!< PLL input clock*4 */
 #define  RCC_CFGR_PLLMUL5                   ((uint32_t)0x000C0000)        /*!< PLL input clock*5 */
 #define  RCC_CFGR_PLLMUL6                   ((uint32_t)0x00100000)        /*!< PLL input clock*6 */
 #define  RCC_CFGR_PLLMUL7                   ((uint32_t)0x00140000)        /*!< PLL input clock*7 */
 #define  RCC_CFGR_PLLMUL8                   ((uint32_t)0x00180000)        /*!< PLL input clock*8 */
 #define  RCC_CFGR_PLLMUL9                   ((uint32_t)0x001C0000)        /*!< PLL input clock*9 */
 #define  RCC_CFGR_PLLMUL10                  ((uint32_t)0x00200000)        /*!< PLL input clock10 */
 #define  RCC_CFGR_PLLMUL11                  ((uint32_t)0x00240000)        /*!< PLL input clock*11 */
 #define  RCC_CFGR_PLLMUL12                  ((uint32_t)0x00280000)        /*!< PLL input clock*12 */
 #define  RCC_CFGR_PLLMUL13                  ((uint32_t)0x002C0000)        /*!< PLL input clock*13 */
 #define  RCC_CFGR_PLLMUL14                  ((uint32_t)0x00300000)        /*!< PLL input clock*14 */
 #define  RCC_CFGR_PLLMUL15                  ((uint32_t)0x00340000)        /*!< PLL input clock*15 */
 #define  RCC_CFGR_PLLMUL16                  ((uint32_t)0x00380000)        /*!< PLL input clock*16 */
 /* Old PLLMUL configuration bit definition maintained for legacy purposes */
 #define  RCC_CFGR_PLLMULL                    RCC_CFGR_PLLMUL        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
 #define  RCC_CFGR_PLLMULL_0                  RCC_CFGR_PLLMUL_0        /*!< Bit 0 */
 #define  RCC_CFGR_PLLMULL_1                  RCC_CFGR_PLLMUL_1        /*!< Bit 1 */
 #define  RCC_CFGR_PLLMULL_2                  RCC_CFGR_PLLMUL_2        /*!< Bit 2 */
 #define  RCC_CFGR_PLLMULL_3                  RCC_CFGR_PLLMUL_3       /*!< Bit 3 */
 #define  RCC_CFGR_PLLMULL2                   RCC_CFGR_PLLMUL2       /*!< PLL input clock*2 */
 #define  RCC_CFGR_PLLMULL3                   RCC_CFGR_PLLMUL3        /*!< PLL input clock*3 */
 #define  RCC_CFGR_PLLMULL4                   RCC_CFGR_PLLMUL4        /*!< PLL input clock*4 */
 #define  RCC_CFGR_PLLMULL5                   RCC_CFGR_PLLMUL5        /*!< PLL input clock*5 */
 #define  RCC_CFGR_PLLMULL6                   RCC_CFGR_PLLMUL6        /*!< PLL input clock*6 */
 #define  RCC_CFGR_PLLMULL7                   RCC_CFGR_PLLMUL7        /*!< PLL input clock*7 */
 #define  RCC_CFGR_PLLMULL8                   RCC_CFGR_PLLMUL8        /*!< PLL input clock*8 */
 #define  RCC_CFGR_PLLMULL9                   RCC_CFGR_PLLMUL9        /*!< PLL input clock*9 */
 #define  RCC_CFGR_PLLMULL10                  RCC_CFGR_PLLMUL10        /*!< PLL input clock10 */
 #define  RCC_CFGR_PLLMULL11                  RCC_CFGR_PLLMUL11        /*!< PLL input clock*11 */
 #define  RCC_CFGR_PLLMULL12                  RCC_CFGR_PLLMUL12        /*!< PLL input clock*12 */
 #define  RCC_CFGR_PLLMULL13                  RCC_CFGR_PLLMUL13        /*!< PLL input clock*13 */
 #define  RCC_CFGR_PLLMULL14                  RCC_CFGR_PLLMUL14        /*!< PLL input clock*14 */
 #define  RCC_CFGR_PLLMULL15                  RCC_CFGR_PLLMUL15        /*!< PLL input clock*15 */
 #define  RCC_CFGR_PLLMULL16                  RCC_CFGR_PLLMUL16        /*!< PLL input clock*16 */
 #define  RCC_CFGR_MCO                        ((uint32_t)0x0F000000)        /*!< MCO[2:0] bits (Microcontroller Clock Output) */
 #define  RCC_CFGR_MCO_0                      ((uint32_t)0x01000000)        /*!< Bit 0 */
 #define  RCC_CFGR_MCO_1                      ((uint32_t)0x02000000)        /*!< Bit 1 */
 #define  RCC_CFGR_MCO_2                      ((uint32_t)0x04000000)        /*!< Bit 2 */
 #define  RCC_CFGR_MCO_3                      ((uint32_t)0x08000000)        /*!< Bit 3 */
 /* MCO configuration */
 #define  RCC_CFGR_MCO_NOCLOCK                ((uint32_t)0x00000000)        /*!< No clock */
 #define  RCC_CFGR_MCO_HSI14                  ((uint32_t)0x01000000)        /*!< HSI14 clock selected as MCO source */
 #define  RCC_CFGR_MCO_LSI                    ((uint32_t)0x02000000)        /*!< LSI clock selected as MCO source */
 #define  RCC_CFGR_MCO_LSE                    ((uint32_t)0x03000000)        /*!< LSE clock selected as MCO source */
 #define  RCC_CFGR_MCO_SYSCLK                 ((uint32_t)0x04000000)        /*!< System clock selected as MCO source */
 #define  RCC_CFGR_MCO_HSI                    ((uint32_t)0x05000000)        /*!< HSI clock selected as MCO source */
 #define  RCC_CFGR_MCO_HSE                    ((uint32_t)0x06000000)        /*!< HSE clock selected as MCO source  */
 #define  RCC_CFGR_MCO_PLL                    ((uint32_t)0x07000000)        /*!< PLL clock selected as MCO source */
 #define  RCC_CFGR_MCO_HSI48                  ((uint32_t)0x08000000)        /*!< HSI48 clock selected as MCO source */
 #define  RCC_CFGR_MCO_PRE                    ((uint32_t)0x70000000)        /*!< MCO prescaler (these bits are not available in the STM32F051 devices)*/
 #define  RCC_CFGR_MCO_PRE_1                  ((uint32_t)0x00000000)        /*!< MCO is divided by 1 (this bit are not available in the STM32F051 devices)*/
 #define  RCC_CFGR_MCO_PRE_2                  ((uint32_t)0x10000000)        /*!< MCO is divided by 2 (this bit are not available in the STM32F051 devices)*/
 #define  RCC_CFGR_MCO_PRE_4                  ((uint32_t)0x20000000)        /*!< MCO is divided by 4 (this bit are not available in the STM32F051 devices)*/
 #define  RCC_CFGR_MCO_PRE_8                  ((uint32_t)0x30000000)        /*!< MCO is divided by 8 (this bit are not available in the STM32F051 devices)*/
 #define  RCC_CFGR_MCO_PRE_16                 ((uint32_t)0x40000000)        /*!< MCO is divided by 16 (this bit are not available in the STM32F051 devices)*/
 #define  RCC_CFGR_MCO_PRE_32                 ((uint32_t)0x50000000)        /*!< MCO is divided by 32 (this bit are not available in the STM32F051 devices)*/
 #define  RCC_CFGR_MCO_PRE_64                 ((uint32_t)0x60000000)        /*!< MCO is divided by 64 (this bit are not available in the STM32F051 devices)*/
 #define  RCC_CFGR_MCO_PRE_128                ((uint32_t)0x70000000)        /*!< MCO is divided by 128 (this bit are not available in the STM32F051 devices)*/
 #define  RCC_CFGR_PLLNODIV                   ((uint32_t)0x80000000)        /*!< PLL is not divided to MCO (this bit are not available in the STM32F051 devices) */
 /*******************  Bit definition for RCC_CIR register  ********************/
 #define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt flag */
 #define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt flag */
 #define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt flag */
 #define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt flag */
 #define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt flag */
 #define  RCC_CIR_HSI14RDYF                   ((uint32_t)0x00000020)        /*!< HSI14 Ready Interrupt flag */
 #define  RCC_CIR_HSI48RDYF                   ((uint32_t)0x00000040)        /*!< HSI48 Ready Interrupt flag */
 #define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)        /*!< Clock Security System Interrupt flag */
 #define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)        /*!< LSI Ready Interrupt Enable */
 #define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)        /*!< LSE Ready Interrupt Enable */
 #define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)        /*!< HSI Ready Interrupt Enable */
 #define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)        /*!< HSE Ready Interrupt Enable */
 #define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)        /*!< PLL Ready Interrupt Enable */
 #define  RCC_CIR_HSI14RDYIE                  ((uint32_t)0x00002000)        /*!< HSI14 Ready Interrupt Enable */
 #define  RCC_CIR_HSI48RDYIE                  ((uint32_t)0x00004000)        /*!< HSI48 Ready Interrupt Enable */
 #define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)        /*!< LSI Ready Interrupt Clear */
 #define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)        /*!< LSE Ready Interrupt Clear */
 #define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)        /*!< HSI Ready Interrupt Clear */
 #define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)        /*!< HSE Ready Interrupt Clear */
 #define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)        /*!< PLL Ready Interrupt Clear */
 #define  RCC_CIR_HSI14RDYC                   ((uint32_t)0x00200000)        /*!< HSI14 Ready Interrupt Clear */
 #define  RCC_CIR_HSI48RDYC                   ((uint32_t)0x00400000)        /*!< HSI48 Ready Interrupt Clear */
 #define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)        /*!< Clock Security System Interrupt Clear */
 /*****************  Bit definition for RCC_APB2RSTR register  *****************/
 #define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00000001)        /*!< SYSCFG clock reset */
 #define  RCC_APB2RSTR_ADCRST                 ((uint32_t)0x00000200)        /*!< ADC clock reset */
 #define  RCC_APB2RSTR_USART8RST              ((uint32_t)0x00000080)        /*!< USART8 clock reset */
 #define  RCC_APB2RSTR_USART7RST              ((uint32_t)0x00000040)        /*!< USART7 clock reset */
 #define  RCC_APB2RSTR_USART6RST              ((uint32_t)0x00000020)        /*!< USART6 clock reset */
 #define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000800)        /*!< TIM1 clock reset */
 #define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)        /*!< SPI1 clock reset */
 #define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00004000)        /*!< USART1 clock reset */
 #define  RCC_APB2RSTR_TIM15RST               ((uint32_t)0x00010000)        /*!< TIM15 clock reset */
 #define  RCC_APB2RSTR_TIM16RST               ((uint32_t)0x00020000)        /*!< TIM16 clock reset */
 #define  RCC_APB2RSTR_TIM17RST               ((uint32_t)0x00040000)        /*!< TIM17 clock reset */
 #define  RCC_APB2RSTR_DBGMCURST              ((uint32_t)0x00400000)        /*!< DBGMCU clock reset */
 /* Old ADC1 clock reset bit definition maintained for legacy purpose */
 #define  RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADCRST
 /*****************  Bit definition for RCC_APB1RSTR register  *****************/
 #define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)        /*!< Timer 2 clock reset */
 #define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)        /*!< Timer 3 clock reset */
 #define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 clock reset */
 #define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)        /*!< Timer 7 clock reset */
 #define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100)        /*!< Timer 14 clock reset */
 #define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)        /*!< Window Watchdog clock reset */
 #define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000)        /*!< SPI2 clock reset */
 #define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)        /*!< USART 2 clock reset */
 #define  RCC_APB1RSTR_USART3RST              ((uint32_t)0x00040000)        /*!< USART 3 clock reset */
 #define  RCC_APB1RSTR_USART4RST              ((uint32_t)0x00080000)        /*!< USART 4 clock reset */
 #define  RCC_APB1RSTR_USART5RST              ((uint32_t)0x00100000)        /*!< USART 5 clock reset */
 #define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)        /*!< I2C 1 clock reset */
 #define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000)        /*!< I2C 2 clock reset */
 #define  RCC_APB1RSTR_USBRST                 ((uint32_t)0x00800000)        /*!< USB clock reset */
 #define  RCC_APB1RSTR_CANRST                 ((uint32_t)0x02000000)        /*!< CAN clock reset */
 #define  RCC_APB1RSTR_CRSRST                 ((uint32_t)0x08000000)        /*!< CRS clock reset */
 #define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)        /*!< PWR clock reset */
 #define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)        /*!< DAC clock reset */
 #define  RCC_APB1RSTR_CECRST                 ((uint32_t)0x40000000)        /*!< CEC clock reset */
 /******************  Bit definition for RCC_AHBENR register  ******************/
 #define  RCC_AHBENR_DMAEN                    ((uint32_t)0x00000001)        /*!< DMA clock enable */
 #define  RCC_AHBENR_DMA2EN                   ((uint32_t)0x00000002)        /*!< DMA2 clock enable */
 #define  RCC_AHBENR_SRAMEN                   ((uint32_t)0x00000004)        /*!< SRAM interface clock enable */
 #define  RCC_AHBENR_FLITFEN                  ((uint32_t)0x00000010)        /*!< FLITF clock enable */
 #define  RCC_AHBENR_CRCEN                    ((uint32_t)0x00000040)        /*!< CRC clock enable */
 #define  RCC_AHBENR_GPIOAEN                  ((uint32_t)0x00020000)        /*!< GPIOA clock enable */
 #define  RCC_AHBENR_GPIOBEN                  ((uint32_t)0x00040000)        /*!< GPIOB clock enable */
 #define  RCC_AHBENR_GPIOCEN                  ((uint32_t)0x00080000)        /*!< GPIOC clock enable */
 #define  RCC_AHBENR_GPIODEN                  ((uint32_t)0x00100000)        /*!< GPIOD clock enable */
 #define  RCC_AHBENR_GPIOEEN                  ((uint32_t)0x00200000)        /*!< GPIOE clock enable */
 #define  RCC_AHBENR_GPIOFEN                  ((uint32_t)0x00400000)        /*!< GPIOF clock enable */
 #define  RCC_AHBENR_TSCEN                    ((uint32_t)0x01000000)        /*!< TS controller clock enable */
 /* Old Bit definition maintained for legacy purpose */
 #define  RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMAEN        /*!< DMA1 clock enable */
 #define  RCC_AHBENR_TSEN                     RCC_AHBENR_TSCEN        /*!< TS clock enable */
 /*****************  Bit definition for RCC_APB2ENR register  ******************/
 #define  RCC_APB2ENR_SYSCFGCOMPEN            ((uint32_t)0x00000001)        /*!< SYSCFG and comparator clock enable */
 #define  RCC_APB2ENR_USART6EN                ((uint32_t)0x00000020)        /*!< USART6 clock enable */
 #define  RCC_APB2ENR_USART7EN                ((uint32_t)0x00000040)        /*!< USART7 clock enable */
 #define  RCC_APB2ENR_USART8EN                ((uint32_t)0x00000080)        /*!< USART8 clock enable */
 #define  RCC_APB2ENR_ADCEN                   ((uint32_t)0x00000200)        /*!< ADC1 clock enable */
 #define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000800)        /*!< TIM1 clock enable */
 #define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)        /*!< SPI1 clock enable */
 #define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00004000)        /*!< USART1 clock enable */
 #define  RCC_APB2ENR_TIM15EN                 ((uint32_t)0x00010000)        /*!< TIM15 clock enable */
 #define  RCC_APB2ENR_TIM16EN                 ((uint32_t)0x00020000)        /*!< TIM16 clock enable */
 #define  RCC_APB2ENR_TIM17EN                 ((uint32_t)0x00040000)        /*!< TIM17 clock enable */
 #define  RCC_APB2ENR_DBGMCUEN                ((uint32_t)0x00400000)        /*!< DBGMCU clock enable */
 /* Old Bit definition maintained for legacy purpose */
 #define  RCC_APB2ENR_SYSCFGEN                RCC_APB2ENR_SYSCFGCOMPEN        /*!< SYSCFG clock enable */
 #define  RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADCEN               /*!< ADC1 clock enable */
 /*****************  Bit definition for RCC_APB1ENR register  ******************/
 #define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)        /*!< Timer 2 clock enable */
 #define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)        /*!< Timer 3 clock enable */
 #define  RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */
 #define  RCC_APB1ENR_TIM7EN                  ((uint32_t)0x00000020)        /*!< Timer 7 clock enable */
 #define  RCC_APB1ENR_TIM14EN                 ((uint32_t)0x00000100)        /*!< Timer 14 clock enable */
 #define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)        /*!< Window Watchdog clock enable */
 #define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000)        /*!< SPI2 clock enable */
 #define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)        /*!< USART2 clock enable */
 #define  RCC_APB1ENR_USART3EN                ((uint32_t)0x00040000)        /*!< USART3 clock enable */
 #define  RCC_APB1ENR_USART4EN                ((uint32_t)0x00080000)        /*!< USART4 clock enable */
 #define  RCC_APB1ENR_USART5EN                ((uint32_t)0x00100000)        /*!< USART5 clock enable */
 #define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)        /*!< I2C1 clock enable */
 #define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000)        /*!< I2C2 clock enable */
 #define  RCC_APB1ENR_USBEN                   ((uint32_t)0x00800000)        /*!< USB clock enable */
 #define  RCC_APB1ENR_CANEN                   ((uint32_t)0x02000000)         /*!< CAN clock enable */
 #define  RCC_APB1ENR_CRSEN                   ((uint32_t)0x08000000)        /*!< CRS clock enable */
 #define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)        /*!< PWR clock enable */
 #define  RCC_APB1ENR_DACEN                   ((uint32_t)0x20000000)        /*!< DAC clock enable */
 #define  RCC_APB1ENR_CECEN                   ((uint32_t)0x40000000)        /*!< CEC clock enable */
 /*******************  Bit definition for RCC_BDCR register  *******************/
 #define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001)        /*!< External Low Speed oscillator enable */
 #define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002)        /*!< External Low Speed oscillator Ready */
 #define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004)        /*!< External Low Speed oscillator Bypass */
 #define  RCC_BDCR_LSEDRV                     ((uint32_t)0x00000018)        /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
 #define  RCC_BDCR_LSEDRV_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */
 #define  RCC_BDCR_LSEDRV_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */
 #define  RCC_BDCR_RTCSEL                     ((uint32_t)0x00000300)        /*!< RTCSEL[1:0] bits (RTC clock source selection) */
 #define  RCC_BDCR_RTCSEL_0                   ((uint32_t)0x00000100)        /*!< Bit 0 */
 #define  RCC_BDCR_RTCSEL_1                   ((uint32_t)0x00000200)        /*!< Bit 1 */
 /* RTC configuration */
 #define  RCC_BDCR_RTCSEL_NOCLOCK             ((uint32_t)0x00000000)        /*!< No clock */
 #define  RCC_BDCR_RTCSEL_LSE                 ((uint32_t)0x00000100)        /*!< LSE oscillator clock used as RTC clock */
 #define  RCC_BDCR_RTCSEL_LSI                 ((uint32_t)0x00000200)        /*!< LSI oscillator clock used as RTC clock */
 #define  RCC_BDCR_RTCSEL_HSE                 ((uint32_t)0x00000300)        /*!< HSE oscillator clock divided by 32 used as RTC clock */
 #define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000)        /*!< RTC clock enable */
 #define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000)        /*!< Backup domain software reset  */
 /*******************  Bit definition for RCC_CSR register  ********************/
 #define  RCC_CSR_LSION                       ((uint32_t)0x00000001)        /*!< Internal Low Speed oscillator enable */
 #define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)        /*!< Internal Low Speed oscillator Ready */
 #define  RCC_CSR_V18PWRRSTF                  ((uint32_t)0x00800000)        /*!< V1.8 power domain reset flag */
 #define  RCC_CSR_RMVF                        ((uint32_t)0x01000000)        /*!< Remove reset flag */
 #define  RCC_CSR_OBLRSTF                     ((uint32_t)0x02000000)        /*!< OBL reset flag */
 #define  RCC_CSR_PINRSTF                     ((uint32_t)0x04000000)        /*!< PIN reset flag */
 #define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)        /*!< POR/PDR reset flag */
 #define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)        /*!< Software Reset flag */
 #define  RCC_CSR_IWDGRSTF                    ((uint32_t)0x20000000)        /*!< Independent Watchdog reset flag */
 #define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)        /*!< Window watchdog reset flag */
 #define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)        /*!< Low-Power reset flag */
 /* Old Bit definition maintained for legacy purpose */
 #define  RCC_CSR_OBL                         RCC_CSR_OBLRSTF        /*!< OBL reset flag */
 /*******************  Bit definition for RCC_AHBRSTR register  ****************/
 #define  RCC_AHBRSTR_GPIOARST                ((uint32_t)0x00020000)         /*!< GPIOA clock reset */
 #define  RCC_AHBRSTR_GPIOBRST                ((uint32_t)0x00040000)         /*!< GPIOB clock reset */
 #define  RCC_AHBRSTR_GPIOCRST                ((uint32_t)0x00080000)         /*!< GPIOC clock reset */
 #define  RCC_AHBRSTR_GPIODRST                ((uint32_t)0x00010000)         /*!< GPIOD clock reset */
 #define  RCC_AHBRSTR_GPIOERST                ((uint32_t)0x00020000)         /*!< GPIOE clock reset */
 #define  RCC_AHBRSTR_GPIOFRST                ((uint32_t)0x00040000)         /*!< GPIOF clock reset */
 #define  RCC_AHBRSTR_TSCRST                  ((uint32_t)0x00100000)         /*!< TS clock reset */
 /* Old Bit definition maintained for legacy purpose */
 #define  RCC_AHBRSTR_TSRST                   RCC_AHBRSTR_TSCRST         /*!< TS clock reset */
 /*******************  Bit definition for RCC_CFGR2 register  ******************/
 /* PREDIV1 configuration */
 #define  RCC_CFGR2_PREDIV1                   ((uint32_t)0x0000000F)        /*!< PREDIV1[3:0] bits */
 #define  RCC_CFGR2_PREDIV1_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
 #define  RCC_CFGR2_PREDIV1_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
 #define  RCC_CFGR2_PREDIV1_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
 #define  RCC_CFGR2_PREDIV1_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
 #define  RCC_CFGR2_PREDIV1_DIV1              ((uint32_t)0x00000000)        /*!< PREDIV1 input clock not divided */
 #define  RCC_CFGR2_PREDIV1_DIV2              ((uint32_t)0x00000001)        /*!< PREDIV1 input clock divided by 2 */
 #define  RCC_CFGR2_PREDIV1_DIV3              ((uint32_t)0x00000002)        /*!< PREDIV1 input clock divided by 3 */
 #define  RCC_CFGR2_PREDIV1_DIV4              ((uint32_t)0x00000003)        /*!< PREDIV1 input clock divided by 4 */
 #define  RCC_CFGR2_PREDIV1_DIV5              ((uint32_t)0x00000004)        /*!< PREDIV1 input clock divided by 5 */
 #define  RCC_CFGR2_PREDIV1_DIV6              ((uint32_t)0x00000005)        /*!< PREDIV1 input clock divided by 6 */
 #define  RCC_CFGR2_PREDIV1_DIV7              ((uint32_t)0x00000006)        /*!< PREDIV1 input clock divided by 7 */
 #define  RCC_CFGR2_PREDIV1_DIV8              ((uint32_t)0x00000007)        /*!< PREDIV1 input clock divided by 8 */
 #define  RCC_CFGR2_PREDIV1_DIV9              ((uint32_t)0x00000008)        /*!< PREDIV1 input clock divided by 9 */
 #define  RCC_CFGR2_PREDIV1_DIV10             ((uint32_t)0x00000009)        /*!< PREDIV1 input clock divided by 10 */
 #define  RCC_CFGR2_PREDIV1_DIV11             ((uint32_t)0x0000000A)        /*!< PREDIV1 input clock divided by 11 */
 #define  RCC_CFGR2_PREDIV1_DIV12             ((uint32_t)0x0000000B)        /*!< PREDIV1 input clock divided by 12 */
 #define  RCC_CFGR2_PREDIV1_DIV13             ((uint32_t)0x0000000C)        /*!< PREDIV1 input clock divided by 13 */
 #define  RCC_CFGR2_PREDIV1_DIV14             ((uint32_t)0x0000000D)        /*!< PREDIV1 input clock divided by 14 */
 #define  RCC_CFGR2_PREDIV1_DIV15             ((uint32_t)0x0000000E)        /*!< PREDIV1 input clock divided by 15 */
 #define  RCC_CFGR2_PREDIV1_DIV16             ((uint32_t)0x0000000F)        /*!< PREDIV1 input clock divided by 16 */
 /*******************  Bit definition for RCC_CFGR3 register  ******************/
 #define  RCC_CFGR3_USART1SW                  ((uint32_t)0x00000003)        /*!< USART1SW[1:0] bits */
 #define  RCC_CFGR3_USART1SW_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
 #define  RCC_CFGR3_USART1SW_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
 #define  RCC_CFGR3_I2C1SW                    ((uint32_t)0x00000010)        /*!< I2C1SW bits */
 #define  RCC_CFGR3_CECSW                     ((uint32_t)0x00000040)        /*!< CECSW bits */
 #define  RCC_CFGR3_USBSW                     ((uint32_t)0x00000080)        /*!< USBSW bits */
 #define  RCC_CFGR3_ADCSW                     ((uint32_t)0x00000100)        /*!< ADCSW bits */
 #define  RCC_CFGR3_USART2SW                  ((uint32_t)0x00030000)        /*!< USART2SW[1:0] bits */
 #define  RCC_CFGR3_USART2SW_0                ((uint32_t)0x00010000)        /*!< Bit 0 */
 #define  RCC_CFGR3_USART2SW_1                ((uint32_t)0x00020000)        /*!< Bit 1 */
 #define  RCC_CFGR3_USART3SW                  ((uint32_t)0x000C0000)        /*!< USART3SW[1:0] bits */
 #define  RCC_CFGR3_USART3SW_0                ((uint32_t)0x00040000)        /*!< Bit 0 */
 #define  RCC_CFGR3_USART3SW_1                ((uint32_t)0x00080000)        /*!< Bit 1 */
 /*******************  Bit definition for RCC_CR2 register  ********************/
 #define  RCC_CR2_HSI14ON                     ((uint32_t)0x00000001)        /*!< Internal High Speed 14MHz clock enable */
 #define  RCC_CR2_HSI14RDY                    ((uint32_t)0x00000002)        /*!< Internal High Speed 14MHz clock ready flag */
 #define  RCC_CR2_HSI14DIS                    ((uint32_t)0x00000004)        /*!< Internal High Speed 14MHz clock disable */
 #define  RCC_CR2_HSI14TRIM                   ((uint32_t)0x000000F8)        /*!< Internal High Speed 14MHz clock trimming */
 #define  RCC_CR2_HSI14CAL                    ((uint32_t)0x0000FF00)        /*!< Internal High Speed 14MHz clock Calibration */
 #define  RCC_CR2_HSI48ON                     ((uint32_t)0x00010000)        /*!< Internal High Speed 48MHz clock enable */
 #define  RCC_CR2_HSI48RDY                    ((uint32_t)0x00020000)        /*!< Internal High Speed 48MHz clock ready flag */
 #define  RCC_CR2_HSI48CAL                    ((uint32_t)0xFF000000)        /*!< Internal High Speed 48MHz clock Calibration */
 /******************************************************************************/
 /*                                                                            */
 /*                           Real-Time Clock (RTC)                            */
 /*                                                                            */
 /******************************************************************************/
 /********************  Bits definition for RTC_TR register  *******************/
 #define RTC_TR_PM                            ((uint32_t)0x00400000)
 #define RTC_TR_HT                            ((uint32_t)0x00300000)
 #define RTC_TR_HT_0                          ((uint32_t)0x00100000)
 #define RTC_TR_HT_1                          ((uint32_t)0x00200000)
 #define RTC_TR_HU                            ((uint32_t)0x000F0000)
 #define RTC_TR_HU_0                          ((uint32_t)0x00010000)
 #define RTC_TR_HU_1                          ((uint32_t)0x00020000)
 #define RTC_TR_HU_2                          ((uint32_t)0x00040000)
 #define RTC_TR_HU_3                          ((uint32_t)0x00080000)
 #define RTC_TR_MNT                           ((uint32_t)0x00007000)
 #define RTC_TR_MNT_0                         ((uint32_t)0x00001000)
 #define RTC_TR_MNT_1                         ((uint32_t)0x00002000)
 #define RTC_TR_MNT_2                         ((uint32_t)0x00004000)
 #define RTC_TR_MNU                           ((uint32_t)0x00000F00)
 #define RTC_TR_MNU_0                         ((uint32_t)0x00000100)
 #define RTC_TR_MNU_1                         ((uint32_t)0x00000200)
 #define RTC_TR_MNU_2                         ((uint32_t)0x00000400)
 #define RTC_TR_MNU_3                         ((uint32_t)0x00000800)
 #define RTC_TR_ST                            ((uint32_t)0x00000070)
 #define RTC_TR_ST_0                          ((uint32_t)0x00000010)
 #define RTC_TR_ST_1                          ((uint32_t)0x00000020)
 #define RTC_TR_ST_2                          ((uint32_t)0x00000040)
 #define RTC_TR_SU                            ((uint32_t)0x0000000F)
 #define RTC_TR_SU_0                          ((uint32_t)0x00000001)
 #define RTC_TR_SU_1                          ((uint32_t)0x00000002)
 #define RTC_TR_SU_2                          ((uint32_t)0x00000004)
 #define RTC_TR_SU_3                          ((uint32_t)0x00000008)
 /********************  Bits definition for RTC_DR register  *******************/
 #define RTC_DR_YT                            ((uint32_t)0x00F00000)
 #define RTC_DR_YT_0                          ((uint32_t)0x00100000)
 #define RTC_DR_YT_1                          ((uint32_t)0x00200000)
 #define RTC_DR_YT_2                          ((uint32_t)0x00400000)
 #define RTC_DR_YT_3                          ((uint32_t)0x00800000)
 #define RTC_DR_YU                            ((uint32_t)0x000F0000)
 #define RTC_DR_YU_0                          ((uint32_t)0x00010000)
 #define RTC_DR_YU_1                          ((uint32_t)0x00020000)
 #define RTC_DR_YU_2                          ((uint32_t)0x00040000)
 #define RTC_DR_YU_3                          ((uint32_t)0x00080000)
 #define RTC_DR_WDU                           ((uint32_t)0x0000E000)
 #define RTC_DR_WDU_0                         ((uint32_t)0x00002000)
 #define RTC_DR_WDU_1                         ((uint32_t)0x00004000)
 #define RTC_DR_WDU_2                         ((uint32_t)0x00008000)
 #define RTC_DR_MT                            ((uint32_t)0x00001000)
 #define RTC_DR_MU                            ((uint32_t)0x00000F00)
 #define RTC_DR_MU_0                          ((uint32_t)0x00000100)
 #define RTC_DR_MU_1                          ((uint32_t)0x00000200)
 #define RTC_DR_MU_2                          ((uint32_t)0x00000400)
 #define RTC_DR_MU_3                          ((uint32_t)0x00000800)
 #define RTC_DR_DT                            ((uint32_t)0x00000030)
 #define RTC_DR_DT_0                          ((uint32_t)0x00000010)
 #define RTC_DR_DT_1                          ((uint32_t)0x00000020)
 #define RTC_DR_DU                            ((uint32_t)0x0000000F)
 #define RTC_DR_DU_0                          ((uint32_t)0x00000001)
 #define RTC_DR_DU_1                          ((uint32_t)0x00000002)
 #define RTC_DR_DU_2                          ((uint32_t)0x00000004)
 #define RTC_DR_DU_3                          ((uint32_t)0x00000008)
 /********************  Bits definition for RTC_CR register  *******************/
 #define RTC_CR_COE                           ((uint32_t)0x00800000)
 #define RTC_CR_OSEL                          ((uint32_t)0x00600000)
 #define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)
 #define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)
 #define RTC_CR_POL                           ((uint32_t)0x00100000)
 #define RTC_CR_COSEL                         ((uint32_t)0x00080000)
 #define RTC_CR_BKP                           ((uint32_t)0x00040000)
 #define RTC_CR_SUB1H                         ((uint32_t)0x00020000)
 #define RTC_CR_ADD1H                         ((uint32_t)0x00010000)
 #define RTC_CR_TSIE                          ((uint32_t)0x00008000)
 #define RTC_CR_WUTIE                         ((uint32_t)0x00004000)
 #define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)
 #define RTC_CR_TSE                           ((uint32_t)0x00000800)
 #define RTC_CR_WUTE                          ((uint32_t)0x00000400)
 #define RTC_CR_ALRAE                         ((uint32_t)0x00000100)
 #define RTC_CR_FMT                           ((uint32_t)0x00000040)
 #define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020)
 #define RTC_CR_REFCKON                       ((uint32_t)0x00000010)
 #define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)
 #define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007)
 #define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001)
 #define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002)
 #define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004)
 /* Old bit definition maintained for legacy purpose */
 #define RTC_CR_BCK                           RTC_CR_BKP
 #define RTC_CR_CALSEL                        RTC_CR_COSEL
 /********************  Bits definition for RTC_ISR register  ******************/
 #define RTC_ISR_RECALPF                      ((uint32_t)0x00010000)
 #define RTC_ISR_TAMP3F                       ((uint32_t)0x00008000)
 #define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000)
 #define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)
 #define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)
 #define RTC_ISR_TSF                          ((uint32_t)0x00000800)
 #define RTC_ISR_WUTF                         ((uint32_t)0x00000400)
 #define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)
 #define RTC_ISR_INIT                         ((uint32_t)0x00000080)
 #define RTC_ISR_INITF                        ((uint32_t)0x00000040)
 #define RTC_ISR_RSF                          ((uint32_t)0x00000020)
 #define RTC_ISR_INITS                        ((uint32_t)0x00000010)
 #define RTC_ISR_SHPF                         ((uint32_t)0x00000008)
 #define RTC_ISR_WUTWF                        ((uint32_t)0x00000004)
 #define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)
 /********************  Bits definition for RTC_PRER register  *****************/
 #define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)
 #define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFF)
 /********************  Bits definition for RTC_WUTR register  *****************/
 #define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFF)
 /********************  Bits definition for RTC_ALRMAR register  ***************/
 #define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)
 #define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)
 #define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)
 #define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)
 #define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)
 #define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)
 #define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)
 #define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)
 #define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)
 #define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)
 #define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)
 #define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)
 #define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)
 #define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)
 #define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)
 #define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)
 #define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)
 #define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)
 #define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)
 #define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)
 #define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)
 #define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)
 #define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)
 #define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)
 #define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)
 #define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)
 #define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)
 #define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)
 #define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)
 #define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)
 #define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)
 #define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)
 #define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)
 #define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)
 #define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)
 #define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)
 #define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)
 #define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)
 #define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)
 #define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)
 /********************  Bits definition for RTC_WPR register  ******************/
 #define RTC_WPR_KEY                          ((uint32_t)0x000000FF)
 /********************  Bits definition for RTC_SSR register  ******************/
 #define RTC_SSR_SS                           ((uint32_t)0x0003FFFF)
 /********************  Bits definition for RTC_SHIFTR register  ***************/
 #define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFF)
 #define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000)
 /********************  Bits definition for RTC_TSTR register  *****************/
 #define RTC_TSTR_PM                          ((uint32_t)0x00400000)
 #define RTC_TSTR_HT                          ((uint32_t)0x00300000)
 #define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)
 #define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)
 #define RTC_TSTR_HU                          ((uint32_t)0x000F0000)
 #define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)
 #define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)
 #define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)
 #define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)
 #define RTC_TSTR_MNT                         ((uint32_t)0x00007000)
 #define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)
 #define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)
 #define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)
 #define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)
 #define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)
 #define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)
 #define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)
 #define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)
 #define RTC_TSTR_ST                          ((uint32_t)0x00000070)
 #define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)
 #define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)
 #define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)
 #define RTC_TSTR_SU                          ((uint32_t)0x0000000F)
 #define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)
 #define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)
 #define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)
 #define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)
 /********************  Bits definition for RTC_TSDR register  *****************/
 #define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)
 #define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)
 #define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)
 #define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)
 #define RTC_TSDR_MT                          ((uint32_t)0x00001000)
 #define RTC_TSDR_MU                          ((uint32_t)0x00000F00)
 #define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)
 #define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)
 #define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)
 #define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)
 #define RTC_TSDR_DT                          ((uint32_t)0x00000030)
 #define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)
 #define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)
 #define RTC_TSDR_DU                          ((uint32_t)0x0000000F)
 #define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)
 #define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)
 #define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)
 #define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)
 /********************  Bits definition for RTC_TSSSR register  ****************/
 #define RTC_TSSSR_SS                         ((uint32_t)0x0003FFFF)
 /********************  Bits definition for RTC_CALR register  ******************/
 #define RTC_CALR_CALP                         ((uint32_t)0x00008000)
 #define RTC_CALR_CALW8                        ((uint32_t)0x00004000)
 #define RTC_CALR_CALW16                       ((uint32_t)0x00002000)
 #define RTC_CALR_CALM                         ((uint32_t)0x000001FF)
 #define RTC_CALR_CALM_0                       ((uint32_t)0x00000001)
 #define RTC_CALR_CALM_1                       ((uint32_t)0x00000002)
 #define RTC_CALR_CALM_2                       ((uint32_t)0x00000004)
 #define RTC_CALR_CALM_3                       ((uint32_t)0x00000008)
 #define RTC_CALR_CALM_4                       ((uint32_t)0x00000010)
 #define RTC_CALR_CALM_5                       ((uint32_t)0x00000020)
 #define RTC_CALR_CALM_6                       ((uint32_t)0x00000040)
 #define RTC_CALR_CALM_7                       ((uint32_t)0x00000080)
 #define RTC_CALR_CALM_8                       ((uint32_t)0x00000100)
 /* Old Bits definition for RTC_CAL register maintained for legacy purpose */
 #define RTC_CAL_CALP                         RTC_CALR_CALP
 #define RTC_CAL_CALW8                        RTC_CALR_CALW8
 #define RTC_CAL_CALW16                       RTC_CALR_CALW16
 #define RTC_CAL_CALM                         RTC_CALR_CALM
 #define RTC_CAL_CALM_0                       RTC_CALR_CALM_0
 #define RTC_CAL_CALM_1                       RTC_CALR_CALM_1
 #define RTC_CAL_CALM_2                       RTC_CALR_CALM_2
 #define RTC_CAL_CALM_3                       RTC_CALR_CALM_3
 #define RTC_CAL_CALM_4                       RTC_CALR_CALM_4
 #define RTC_CAL_CALM_5                       RTC_CALR_CALM_5
 #define RTC_CAL_CALM_6                       RTC_CALR_CALM_6
 #define RTC_CAL_CALM_7                       RTC_CALR_CALM_7
 #define RTC_CAL_CALM_8                       RTC_CALR_CALM_8
 /********************  Bits definition for RTC_TAFCR register  ****************/
 #define RTC_TAFCR_PC15MODE                   ((uint32_t)0x00800000)
 #define RTC_TAFCR_PC15VALUE                  ((uint32_t)0x00400000)
 #define RTC_TAFCR_PC14MODE                   ((uint32_t)0x00200000)
 #define RTC_TAFCR_PC14VALUE                  ((uint32_t)0x00100000)
 #define RTC_TAFCR_PC13MODE                   ((uint32_t)0x00080000)
 #define RTC_TAFCR_PC13VALUE                  ((uint32_t)0x00040000)
 #define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000)
 #define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000)
 #define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000)
 #define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000)
 #define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800)
 #define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800)
 #define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000)
 #define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700)
 #define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100)
 #define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200)
 #define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400)
 #define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080)
 #define RTC_TAFCR_TAMP3EDGE                  ((uint32_t)0x00000040)
 #define RTC_TAFCR_TAMP3E                     ((uint32_t)0x00000020)
 #define RTC_TAFCR_TAMP2EDGE                  ((uint32_t)0x00000010)
 #define RTC_TAFCR_TAMP2E                     ((uint32_t)0x00000008)
 #define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004)
 #define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002)
 #define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001)
 /* Old bit definition maintained for legacy purpose */
 #define RTC_TAFCR_ALARMOUTTYPE               RTC_TAFCR_PC13VALUE
 /********************  Bits definition for RTC_ALRMASSR register  *************/
 #define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000)
 #define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000)
 #define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000)
 #define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000)
 #define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000)
 #define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFF)
 /********************  Bits definition for RTC_BKP0R register  ****************/
 #define RTC_BKP0R                            ((uint32_t)0xFFFFFFFF)
 /********************  Bits definition for RTC_BKP1R register  ****************/
 #define RTC_BKP1R                            ((uint32_t)0xFFFFFFFF)
 /********************  Bits definition for RTC_BKP2R register  ****************/
 #define RTC_BKP2R                            ((uint32_t)0xFFFFFFFF)
 /********************  Bits definition for RTC_BKP3R register  ****************/
 #define RTC_BKP3R                            ((uint32_t)0xFFFFFFFF)
 /********************  Bits definition for RTC_BKP4R register  ****************/
 #define RTC_BKP4R                            ((uint32_t)0xFFFFFFFF)
 /******************************************************************************/
 /*                                                                            */
 /*                        Serial Peripheral Interface (SPI)                   */
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for SPI_CR1 register  ********************/
 #define  SPI_CR1_CPHA                        ((uint16_t)0x0001)            /*!< Clock Phase */
 #define  SPI_CR1_CPOL                        ((uint16_t)0x0002)            /*!< Clock Polarity */
 #define  SPI_CR1_MSTR                        ((uint16_t)0x0004)            /*!< Master Selection */
 #define  SPI_CR1_BR                          ((uint16_t)0x0038)            /*!< BR[2:0] bits (Baud Rate Control) */
 #define  SPI_CR1_BR_0                        ((uint16_t)0x0008)            /*!< Bit 0 */
 #define  SPI_CR1_BR_1                        ((uint16_t)0x0010)            /*!< Bit 1 */
 #define  SPI_CR1_BR_2                        ((uint16_t)0x0020)            /*!< Bit 2 */
 #define  SPI_CR1_SPE                         ((uint16_t)0x0040)            /*!< SPI Enable */
 #define  SPI_CR1_LSBFIRST                    ((uint16_t)0x0080)            /*!< Frame Format */
 #define  SPI_CR1_SSI                         ((uint16_t)0x0100)            /*!< Internal slave select */
 #define  SPI_CR1_SSM                         ((uint16_t)0x0200)            /*!< Software slave management */
 #define  SPI_CR1_RXONLY                      ((uint16_t)0x0400)            /*!< Receive only */
 #define  SPI_CR1_CRCL                        ((uint16_t)0x0800)            /*!< CRC Length */
 #define  SPI_CR1_CRCNEXT                     ((uint16_t)0x1000)            /*!< Transmit CRC next */
 #define  SPI_CR1_CRCEN                       ((uint16_t)0x2000)            /*!< Hardware CRC calculation enable */
 #define  SPI_CR1_BIDIOE                      ((uint16_t)0x4000)            /*!< Output enable in bidirectional mode */
 #define  SPI_CR1_BIDIMODE                    ((uint16_t)0x8000)            /*!< Bidirectional data mode enable */
 /*******************  Bit definition for SPI_CR2 register  ********************/
 #define  SPI_CR2_RXDMAEN                     ((uint16_t)0x0001)            /*!< Rx Buffer DMA Enable */
 #define  SPI_CR2_TXDMAEN                     ((uint16_t)0x0002)            /*!< Tx Buffer DMA Enable */
 #define  SPI_CR2_SSOE                        ((uint16_t)0x0004)            /*!< SS Output Enable */
 #define  SPI_CR2_NSSP                        ((uint16_t)0x0008)            /*!< NSS pulse management Enable */
 #define  SPI_CR2_FRF                         ((uint16_t)0x0010)            /*!< Frame Format Enable */
 #define  SPI_CR2_ERRIE                       ((uint16_t)0x0020)            /*!< Error Interrupt Enable */
 #define  SPI_CR2_RXNEIE                      ((uint16_t)0x0040)            /*!< RX buffer Not Empty Interrupt Enable */
 #define  SPI_CR2_TXEIE                       ((uint16_t)0x0080)            /*!< Tx buffer Empty Interrupt Enable */
 #define  SPI_CR2_DS                          ((uint16_t)0x0F00)            /*!< DS[3:0] Data Size */
 #define  SPI_CR2_DS_0                        ((uint16_t)0x0100)            /*!< Bit 0 */
 #define  SPI_CR2_DS_1                        ((uint16_t)0x0200)            /*!< Bit 1 */
 #define  SPI_CR2_DS_2                        ((uint16_t)0x0400)            /*!< Bit 2 */
 #define  SPI_CR2_DS_3                        ((uint16_t)0x0800)            /*!< Bit 3 */
 #define  SPI_CR2_FRXTH                       ((uint16_t)0x1000)            /*!< FIFO reception Threshold */
 #define  SPI_CR2_LDMARX                      ((uint16_t)0x2000)            /*!< Last DMA transfer for reception */
 #define  SPI_CR2_LDMATX                      ((uint16_t)0x4000)            /*!< Last DMA transfer for transmission */
 /********************  Bit definition for SPI_SR register  ********************/
 #define  SPI_SR_RXNE                         ((uint16_t)0x0001)            /*!< Receive buffer Not Empty */
 #define  SPI_SR_TXE                          ((uint16_t)0x0002)            /*!< Transmit buffer Empty */
 #define  SPI_SR_CHSIDE                       ((uint16_t)0x0004)            /*!< Channel side */
 #define  SPI_SR_UDR                          ((uint16_t)0x0008)            /*!< Underrun flag */
 #define  SPI_SR_CRCERR                       ((uint16_t)0x0010)            /*!< CRC Error flag */
 #define  SPI_SR_MODF                         ((uint16_t)0x0020)            /*!< Mode fault */
 #define  SPI_SR_OVR                          ((uint16_t)0x0040)            /*!< Overrun flag */
 #define  SPI_SR_BSY                          ((uint16_t)0x0080)            /*!< Busy flag */
 #define  SPI_SR_FRE                          ((uint16_t)0x0100)            /*!< TI frame format error */
 #define  SPI_SR_FRLVL                        ((uint16_t)0x0600)            /*!< FIFO Reception Level */
 #define  SPI_SR_FRLVL_0                      ((uint16_t)0x0200)            /*!< Bit 0 */
 #define  SPI_SR_FRLVL_1                      ((uint16_t)0x0400)            /*!< Bit 1 */
 #define  SPI_SR_FTLVL                        ((uint16_t)0x1800)            /*!< FIFO Transmission Level */
 #define  SPI_SR_FTLVL_0                      ((uint16_t)0x0800)            /*!< Bit 0 */
 #define  SPI_SR_FTLVL_1                      ((uint16_t)0x1000)            /*!< Bit 1 */
 /********************  Bit definition for SPI_DR register  ********************/
 #define  SPI_DR_DR                           ((uint16_t)0xFFFF)            /*!< Data Register */
 /*******************  Bit definition for SPI_CRCPR register  ******************/
 #define  SPI_CRCPR_CRCPOLY                   ((uint16_t)0xFFFF)            /*!< CRC polynomial register */
 /******************  Bit definition for SPI_RXCRCR register  ******************/
 #define  SPI_RXCRCR_RXCRC                    ((uint16_t)0xFFFF)            /*!< Rx CRC Register */
 /******************  Bit definition for SPI_TXCRCR register  ******************/
 #define  SPI_TXCRCR_TXCRC                    ((uint16_t)0xFFFF)            /*!< Tx CRC Register */
 /******************  Bit definition for SPI_I2SCFGR register  *****************/
 #define  SPI_I2SCFGR_CHLEN                   ((uint16_t)0x0001)            /*!<Channel length (number of bits per audio channel) */
 #define  SPI_I2SCFGR_DATLEN                  ((uint16_t)0x0006)            /*!<DATLEN[1:0] bits (Data length to be transferred) */
 #define  SPI_I2SCFGR_DATLEN_0                ((uint16_t)0x0002)            /*!<Bit 0 */
 #define  SPI_I2SCFGR_DATLEN_1                ((uint16_t)0x0004)            /*!<Bit 1 */
 #define  SPI_I2SCFGR_CKPOL                   ((uint16_t)0x0008)            /*!<steady state clock polarity */
 #define  SPI_I2SCFGR_I2SSTD                  ((uint16_t)0x0030)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
 #define  SPI_I2SCFGR_I2SSTD_0                ((uint16_t)0x0010)            /*!<Bit 0 */
 #define  SPI_I2SCFGR_I2SSTD_1                ((uint16_t)0x0020)            /*!<Bit 1 */
 #define  SPI_I2SCFGR_PCMSYNC                 ((uint16_t)0x0080)            /*!<PCM frame synchronization */
 #define  SPI_I2SCFGR_I2SCFG                  ((uint16_t)0x0300)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
 #define  SPI_I2SCFGR_I2SCFG_0                ((uint16_t)0x0100)            /*!<Bit 0 */
 #define  SPI_I2SCFGR_I2SCFG_1                ((uint16_t)0x0200)            /*!<Bit 1 */
 #define  SPI_I2SCFGR_I2SE                    ((uint16_t)0x0400)            /*!<I2S Enable */
 #define  SPI_I2SCFGR_I2SMOD                  ((uint16_t)0x0800)            /*!<I2S mode selection */
 /******************  Bit definition for SPI_I2SPR register  *******************/
 #define  SPI_I2SPR_I2SDIV                    ((uint16_t)0x00FF)            /*!<I2S Linear prescaler */
 #define  SPI_I2SPR_ODD                       ((uint16_t)0x0100)            /*!<Odd factor for the prescaler */
 #define  SPI_I2SPR_MCKOE                     ((uint16_t)0x0200)            /*!<Master Clock Output Enable */
 /******************************************************************************/
 /*                                                                            */
 /*                       System Configuration (SYSCFG)                        */
 /*                                                                            */
 /******************************************************************************/
 /*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
 #define SYSCFG_CFGR1_MEM_MODE               ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
 #define SYSCFG_CFGR1_MEM_MODE_0             ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
 #define SYSCFG_CFGR1_MEM_MODE_1             ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
 #define SYSCFG_CFGR1_IRDA_ENV_SEL           ((uint32_t)0x000000C0) /*!< IRDA_SEL_ENV config */
 #define SYSCFG_CFGR1_IRDA_ENV_SEL_0         ((uint32_t)0x00000040) /*!< IRDA_SEL_ENV Bit 0 */
 #define SYSCFG_CFGR1_IRDA_ENV_SEL_1         ((uint32_t)0x00000080) /*!< IRDA_SEL_ENV Bit 1 */
 #define SYSCFG_CFGR1_PA11_PA12_RMP          ((uint32_t)0x00000010) /*!< PA11 and PA12 remap on QFN28 and TSSOP20 packages (only for STM32F042 devices)*/
 #define SYSCFG_CFGR1_ADC_DMA_RMP            ((uint32_t)0x00000100) /*!< ADC DMA remap */
 #define SYSCFG_CFGR1_USART1TX_DMA_RMP       ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
 #define SYSCFG_CFGR1_USART1RX_DMA_RMP       ((uint32_t)0x00000400) /*!< USART1 RX DMA remap */
 #define SYSCFG_CFGR1_TIM16_DMA_RMP          ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
 #define SYSCFG_CFGR1_TIM17_DMA_RMP          ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
 #define SYSCFG_CFGR1_TIM16_DMA_RMP2         ((uint32_t)0x00002000) /*!< Timer 16 DMA remap 2 (only for STM32F072) */
 #define SYSCFG_CFGR1_TIM17_DMA_RMP2         ((uint32_t)0x00004000) /*!< Timer 17 DMA remap 2 (only for STM32F072) */
 #define SYSCFG_CFGR1_I2C_FMP_PB6            ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
 #define SYSCFG_CFGR1_I2C_FMP_PB7            ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
 #define SYSCFG_CFGR1_I2C_FMP_PB8            ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
 #define SYSCFG_CFGR1_I2C_FMP_PB9            ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
 #define SYSCFG_CFGR1_I2C_FMP_I2C1           ((uint32_t)0x00100000) /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7(only for STM32F030, STM32F031 and STM32F072 devices) */
 #define SYSCFG_CFGR1_I2C_FMP_I2C2           ((uint32_t)0x00200000) /*!< Enable I2C2 Fast mode plus (only for STM32F072) */
 #define SYSCFG_CFGR1_I2C_FMP_PA9            ((uint32_t)0x00400000) /*!< Enable Fast Mode Plus on PA9 (only for STM32F030, STM32F031, STM32F042, STM32F072 and STM32F091 devices) */
 #define SYSCFG_CFGR1_I2C_FMP_PA10           ((uint32_t)0x00800000) /*!< Enable Fast Mode Plus on PA10(only for STM32F030, STM32F031, STM32F042, STM32F072 and STM32F091 devices) */
 #define SYSCFG_CFGR1_SPI2_DMA_RMP           ((uint32_t)0x01000000) /*!< SPI2 DMA remap (only for STM32F072) */
 #define SYSCFG_CFGR1_USART2_DMA_RMP         ((uint32_t)0x02000000) /*!< USART2 DMA remap (only for STM32F072) */
 #define SYSCFG_CFGR1_USART3_DMA_RMP         ((uint32_t)0x04000000) /*!< USART3 DMA remap (only for STM32F072) */
 #define SYSCFG_CFGR1_I2C1_DMA_RMP           ((uint32_t)0x08000000) /*!< I2C1 DMA remap (only for STM32F072) */
 #define SYSCFG_CFGR1_TIM1_DMA_RMP           ((uint32_t)0x10000000) /*!< TIM1 DMA remap (only for STM32F072) */
 #define SYSCFG_CFGR1_TIM2_DMA_RMP           ((uint32_t)0x20000000) /*!< TIM2 DMA remap (only for STM32F072) */
 #define SYSCFG_CFGR1_TIM3_DMA_RMP           ((uint32_t)0x40000000) /*!< TIM3 DMA remap (only for STM32F072) */
 /*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
 #define SYSCFG_EXTICR1_EXTI0            ((uint16_t)0x000F) /*!< EXTI 0 configuration */
 #define SYSCFG_EXTICR1_EXTI1            ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
 #define SYSCFG_EXTICR1_EXTI2            ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
 #define SYSCFG_EXTICR1_EXTI3            ((uint16_t)0xF000) /*!< EXTI 3 configuration */
 /**
   * @brief  EXTI0 configuration
   */
 #define SYSCFG_EXTICR1_EXTI0_PA         ((uint16_t)0x0000) /*!< PA[0] pin */
 #define SYSCFG_EXTICR1_EXTI0_PB         ((uint16_t)0x0001) /*!< PB[0] pin */
 #define SYSCFG_EXTICR1_EXTI0_PC         ((uint16_t)0x0002) /*!< PC[0] pin */
 #define SYSCFG_EXTICR1_EXTI0_PD         ((uint16_t)0x0003) /*!< PD[0] pin */
 #define SYSCFG_EXTICR1_EXTI0_PE         ((uint16_t)0x0004) /*!< PE[0] pin */
 #define SYSCFG_EXTICR1_EXTI0_PF         ((uint16_t)0x0005) /*!< PF[0] pin */
 /**
   * @brief  EXTI1 configuration
   */
 #define SYSCFG_EXTICR1_EXTI1_PA         ((uint16_t)0x0000) /*!< PA[1] pin */
 #define SYSCFG_EXTICR1_EXTI1_PB         ((uint16_t)0x0010) /*!< PB[1] pin */
 #define SYSCFG_EXTICR1_EXTI1_PC         ((uint16_t)0x0020) /*!< PC[1] pin */
 #define SYSCFG_EXTICR1_EXTI1_PD         ((uint16_t)0x0030) /*!< PD[1] pin */
 #define SYSCFG_EXTICR1_EXTI1_PE         ((uint16_t)0x0040) /*!< PE[1] pin */
 #define SYSCFG_EXTICR1_EXTI1_PF         ((uint16_t)0x0050) /*!< PF[1] pin */
 /**
   * @brief  EXTI2 configuration
   */
 #define SYSCFG_EXTICR1_EXTI2_PA         ((uint16_t)0x0000) /*!< PA[2] pin */
 #define SYSCFG_EXTICR1_EXTI2_PB         ((uint16_t)0x0100) /*!< PB[2] pin */
 #define SYSCFG_EXTICR1_EXTI2_PC         ((uint16_t)0x0200) /*!< PC[2] pin */
 #define SYSCFG_EXTICR1_EXTI2_PD         ((uint16_t)0x0300) /*!< PD[2] pin */
 #define SYSCFG_EXTICR1_EXTI2_PE         ((uint16_t)0x0400) /*!< PE[2] pin */
 #define SYSCFG_EXTICR1_EXTI2_PF         ((uint16_t)0x0500) /*!< PF[2] pin */
 /**
   * @brief  EXTI3 configuration
   */
 #define SYSCFG_EXTICR1_EXTI3_PA         ((uint16_t)0x0000) /*!< PA[3] pin */
 #define SYSCFG_EXTICR1_EXTI3_PB         ((uint16_t)0x1000) /*!< PB[3] pin */
 #define SYSCFG_EXTICR1_EXTI3_PC         ((uint16_t)0x2000) /*!< PC[3] pin */
 #define SYSCFG_EXTICR1_EXTI3_PD         ((uint16_t)0x3000) /*!< PD[3] pin */
 #define SYSCFG_EXTICR1_EXTI3_PE         ((uint16_t)0x4000) /*!< PE[3] pin */
 #define SYSCFG_EXTICR1_EXTI3_PF         ((uint16_t)0x5000) /*!< PF[3] pin */
 /*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
 #define SYSCFG_EXTICR2_EXTI4            ((uint16_t)0x000F) /*!< EXTI 4 configuration */
 #define SYSCFG_EXTICR2_EXTI5            ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
 #define SYSCFG_EXTICR2_EXTI6            ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
 #define SYSCFG_EXTICR2_EXTI7            ((uint16_t)0xF000) /*!< EXTI 7 configuration */
 /**
   * @brief  EXTI4 configuration
   */
 #define SYSCFG_EXTICR2_EXTI4_PA         ((uint16_t)0x0000) /*!< PA[4] pin */
 #define SYSCFG_EXTICR2_EXTI4_PB         ((uint16_t)0x0001) /*!< PB[4] pin */
 #define SYSCFG_EXTICR2_EXTI4_PC         ((uint16_t)0x0002) /*!< PC[4] pin */
 #define SYSCFG_EXTICR2_EXTI4_PD         ((uint16_t)0x0003) /*!< PD[4] pin */
 #define SYSCFG_EXTICR2_EXTI4_PE         ((uint16_t)0x0004) /*!< PE[4] pin */
 #define SYSCFG_EXTICR2_EXTI4_PF         ((uint16_t)0x0005) /*!< PF[4] pin */
 /**
   * @brief  EXTI5 configuration
   */
 #define SYSCFG_EXTICR2_EXTI5_PA         ((uint16_t)0x0000) /*!< PA[5] pin */
 #define SYSCFG_EXTICR2_EXTI5_PB         ((uint16_t)0x0010) /*!< PB[5] pin */
 #define SYSCFG_EXTICR2_EXTI5_PC         ((uint16_t)0x0020) /*!< PC[5] pin */
 #define SYSCFG_EXTICR2_EXTI5_PD         ((uint16_t)0x0030) /*!< PD[5] pin */
 #define SYSCFG_EXTICR2_EXTI5_PE         ((uint16_t)0x0040) /*!< PE[5] pin */
 #define SYSCFG_EXTICR2_EXTI5_PF         ((uint16_t)0x0050) /*!< PF[5] pin */
 /**
   * @brief  EXTI6 configuration
   */
 #define SYSCFG_EXTICR2_EXTI6_PA         ((uint16_t)0x0000) /*!< PA[6] pin */
 #define SYSCFG_EXTICR2_EXTI6_PB         ((uint16_t)0x0100) /*!< PB[6] pin */
 #define SYSCFG_EXTICR2_EXTI6_PC         ((uint16_t)0x0200) /*!< PC[6] pin */
 #define SYSCFG_EXTICR2_EXTI6_PD         ((uint16_t)0x0300) /*!< PD[6] pin */
 #define SYSCFG_EXTICR2_EXTI6_PE         ((uint16_t)0x0400) /*!< PE[6] pin */
 #define SYSCFG_EXTICR2_EXTI6_PF         ((uint16_t)0x0500) /*!< PF[6] pin */
 /**
   * @brief  EXTI7 configuration
   */
 #define SYSCFG_EXTICR2_EXTI7_PA         ((uint16_t)0x0000) /*!< PA[7] pin */
 #define SYSCFG_EXTICR2_EXTI7_PB         ((uint16_t)0x1000) /*!< PB[7] pin */
 #define SYSCFG_EXTICR2_EXTI7_PC         ((uint16_t)0x2000) /*!< PC[7] pin */
 #define SYSCFG_EXTICR2_EXTI7_PD         ((uint16_t)0x3000) /*!< PD[7] pin */
 #define SYSCFG_EXTICR2_EXTI7_PE         ((uint16_t)0x4000) /*!< PE[7] pin */
 #define SYSCFG_EXTICR2_EXTI7_PF         ((uint16_t)0x5000) /*!< PF[7] pin */
 /*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
 #define SYSCFG_EXTICR3_EXTI8            ((uint16_t)0x000F) /*!< EXTI 8 configuration */
 #define SYSCFG_EXTICR3_EXTI9            ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
 #define SYSCFG_EXTICR3_EXTI10           ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
 #define SYSCFG_EXTICR3_EXTI11           ((uint16_t)0xF000) /*!< EXTI 11 configuration */
 /**
   * @brief  EXTI8 configuration
   */
 #define SYSCFG_EXTICR3_EXTI8_PA         ((uint16_t)0x0000) /*!< PA[8] pin */
 #define SYSCFG_EXTICR3_EXTI8_PB         ((uint16_t)0x0001) /*!< PB[8] pin */
 #define SYSCFG_EXTICR3_EXTI8_PC         ((uint16_t)0x0002) /*!< PC[8] pin */
 #define SYSCFG_EXTICR3_EXTI8_PD         ((uint16_t)0x0003) /*!< PD[8] pin */
 #define SYSCFG_EXTICR3_EXTI8_PE         ((uint16_t)0x0004) /*!< PE[8] pin */
 /**
   * @brief  EXTI9 configuration
   */
 #define SYSCFG_EXTICR3_EXTI9_PA         ((uint16_t)0x0000) /*!< PA[9] pin */
 #define SYSCFG_EXTICR3_EXTI9_PB         ((uint16_t)0x0010) /*!< PB[9] pin */
 #define SYSCFG_EXTICR3_EXTI9_PC         ((uint16_t)0x0020) /*!< PC[9] pin */
 #define SYSCFG_EXTICR3_EXTI9_PD         ((uint16_t)0x0030) /*!< PD[9] pin */
 #define SYSCFG_EXTICR3_EXTI9_PE         ((uint16_t)0x0040) /*!< PE[9] pin */
 #define SYSCFG_EXTICR3_EXTI9_PF         ((uint16_t)0x0050) /*!< PF[9] pin */
 /**
   * @brief  EXTI10 configuration
   */
 #define SYSCFG_EXTICR3_EXTI10_PA        ((uint16_t)0x0000) /*!< PA[10] pin */
 #define SYSCFG_EXTICR3_EXTI10_PB        ((uint16_t)0x0100) /*!< PB[10] pin */
 #define SYSCFG_EXTICR3_EXTI10_PC        ((uint16_t)0x0200) /*!< PC[10] pin */
 #define SYSCFG_EXTICR3_EXTI10_PD        ((uint16_t)0x0300) /*!< PE[10] pin */
 #define SYSCFG_EXTICR3_EXTI10_PE        ((uint16_t)0x0400) /*!< PD[10] pin */
 #define SYSCFG_EXTICR3_EXTI10_PF        ((uint16_t)0x0500) /*!< PF[10] pin */
 /**
   * @brief  EXTI11 configuration
   */
 #define SYSCFG_EXTICR3_EXTI11_PA        ((uint16_t)0x0000) /*!< PA[11] pin */
 #define SYSCFG_EXTICR3_EXTI11_PB        ((uint16_t)0x1000) /*!< PB[11] pin */
 #define SYSCFG_EXTICR3_EXTI11_PC        ((uint16_t)0x2000) /*!< PC[11] pin */
 #define SYSCFG_EXTICR3_EXTI11_PD        ((uint16_t)0x3000) /*!< PD[11] pin */
 #define SYSCFG_EXTICR3_EXTI11_PE        ((uint16_t)0x4000) /*!< PE[11] pin */
 /*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
 #define SYSCFG_EXTICR4_EXTI12           ((uint16_t)0x000F) /*!< EXTI 12 configuration */
 #define SYSCFG_EXTICR4_EXTI13           ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
 #define SYSCFG_EXTICR4_EXTI14           ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
 #define SYSCFG_EXTICR4_EXTI15           ((uint16_t)0xF000) /*!< EXTI 15 configuration */
 /**
   * @brief  EXTI12 configuration
   */
 #define SYSCFG_EXTICR4_EXTI12_PA        ((uint16_t)0x0000) /*!< PA[12] pin */
 #define SYSCFG_EXTICR4_EXTI12_PB        ((uint16_t)0x0001) /*!< PB[12] pin */
 #define SYSCFG_EXTICR4_EXTI12_PC        ((uint16_t)0x0002) /*!< PC[12] pin */
 #define SYSCFG_EXTICR4_EXTI12_PD        ((uint16_t)0x0003) /*!< PD[12] pin */
 #define SYSCFG_EXTICR4_EXTI12_PE        ((uint16_t)0x0004) /*!< PE[12] pin */
 /**
   * @brief  EXTI13 configuration
   */
 #define SYSCFG_EXTICR4_EXTI13_PA        ((uint16_t)0x0000) /*!< PA[13] pin */
 #define SYSCFG_EXTICR4_EXTI13_PB        ((uint16_t)0x0010) /*!< PB[13] pin */
 #define SYSCFG_EXTICR4_EXTI13_PC        ((uint16_t)0x0020) /*!< PC[13] pin */
 #define SYSCFG_EXTICR4_EXTI13_PD        ((uint16_t)0x0030) /*!< PD[13] pin */
 #define SYSCFG_EXTICR4_EXTI13_PE        ((uint16_t)0x0040) /*!< PE[13] pin */
 /**
   * @brief  EXTI14 configuration
   */
 #define SYSCFG_EXTICR4_EXTI14_PA        ((uint16_t)0x0000) /*!< PA[14] pin */
 #define SYSCFG_EXTICR4_EXTI14_PB        ((uint16_t)0x0100) /*!< PB[14] pin */
 #define SYSCFG_EXTICR4_EXTI14_PC        ((uint16_t)0x0200) /*!< PC[14] pin */
 #define SYSCFG_EXTICR4_EXTI14_PD        ((uint16_t)0x0300) /*!< PD[14] pin */
 #define SYSCFG_EXTICR4_EXTI14_PE        ((uint16_t)0x0400) /*!< PE[14] pin */
 /**
   * @brief  EXTI15 configuration
   */
 #define SYSCFG_EXTICR4_EXTI15_PA        ((uint16_t)0x0000) /*!< PA[15] pin */
 #define SYSCFG_EXTICR4_EXTI15_PB        ((uint16_t)0x1000) /*!< PB[15] pin */
 #define SYSCFG_EXTICR4_EXTI15_PC        ((uint16_t)0x2000) /*!< PC[15] pin */
 #define SYSCFG_EXTICR4_EXTI15_PD        ((uint16_t)0x3000) /*!< PD[15] pin */
 #define SYSCFG_EXTICR4_EXTI15_PE        ((uint16_t)0x4000) /*!< PE[15] pin */
 /*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
 #define SYSCFG_CFGR2_LOCKUP_LOCK               ((uint32_t)0x00000001) /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK          ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
 #define SYSCFG_CFGR2_PVD_LOCK                  ((uint32_t)0x00000004) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
 #define SYSCFG_CFGR2_SRAM_PEF                  ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
 /* Old Bit definition maintained for legacy purpose */
 #define SYSCFG_CFGR2_SRAM_PE                   SYSCFG_CFGR2_SRAM_PEF
 /*****************  Bit definition for SYSCFG_xxx ISR Wrapper register  ****************/
 #define SYSCFG_ITLINE0_SR_EWDG                ((uint32_t)0x00000001) /*!< EWDG interrupt */
 #define SYSCFG_ITLINE1_SR_PVDOUT              ((uint32_t)0x00000001) /*!< Power voltage detection -> exti[31] Interrupt */
 #define SYSCFG_ITLINE1_SR_VDDIO2              ((uint32_t)0x00000002) /*!< VDDIO2 -> exti[16] Interrupt */
 #define SYSCFG_ITLINE2_SR_RTC_WAKEUP          ((uint32_t)0x00000001) /*!< RTC WAKEUP -> exti[20] Interrupt */
 #define SYSCFG_ITLINE2_SR_RTC_TSTAMP          ((uint32_t)0x00000002) /*!< RTC Time Stamp -> exti[19] interrupt */
 #define SYSCFG_ITLINE2_SR_RTC_ALRA            ((uint32_t)0x00000003) /*!< RTC Alarm -> exti[17] interrupt .... */
 #define SYSCFG_ITLINE3_SR_FLASH_ITF           ((uint32_t)0x00000001) /*!< Flash ITF Interrupt */
 #define SYSCFG_ITLINE4_SR_CRS                 ((uint32_t)0x00000001) /*!< CRS interrupt */
 #define SYSCFG_ITLINE4_SR_CLK_CTRL            ((uint32_t)0x00000002) /*!< CLK CTRL interrupt */
 #define SYSCFG_ITLINE5_SR_EXTI0               ((uint32_t)0x00000001) /*!< External Interrupt 0 */
 #define SYSCFG_ITLINE5_SR_EXTI1               ((uint32_t)0x00000002) /*!< External Interrupt 1 */
 #define SYSCFG_ITLINE6_SR_EXTI2               ((uint32_t)0x00000001) /*!< External Interrupt 2 */
 #define SYSCFG_ITLINE6_SR_EXTI3               ((uint32_t)0x00000002) /*!< External Interrupt 3 */
 #define SYSCFG_ITLINE7_SR_EXTI4               ((uint32_t)0x00000001) /*!< External Interrupt 15 to 4 */
 #define SYSCFG_ITLINE7_SR_EXTI5               ((uint32_t)0x00000002) /*!< External Interrupt 15 to 4 */
 #define SYSCFG_ITLINE7_SR_EXTI6               ((uint32_t)0x00000004) /*!< External Interrupt 15 to 4 */
 #define SYSCFG_ITLINE7_SR_EXTI7               ((uint32_t)0x00000008) /*!< External Interrupt 15 to 4 */
 #define SYSCFG_ITLINE7_SR_EXTI8               ((uint32_t)0x00000010) /*!< External Interrupt 15 to 4 */
 #define SYSCFG_ITLINE7_SR_EXTI9               ((uint32_t)0x00000020) /*!< External Interrupt 15 to 4 */
 #define SYSCFG_ITLINE7_SR_EXTI10              ((uint32_t)0x00000040) /*!< External Interrupt 15 to 4 */
 #define SYSCFG_ITLINE7_SR_EXTI11              ((uint32_t)0x00000080) /*!< External Interrupt 15 to 4 */
 #define SYSCFG_ITLINE7_SR_EXTI12              ((uint32_t)0x00000100) /*!< External Interrupt 15 to 4 */
 #define SYSCFG_ITLINE7_SR_EXTI13              ((uint32_t)0x00000200) /*!< External Interrupt 15 to 4 */
 #define SYSCFG_ITLINE7_SR_EXTI14              ((uint32_t)0x00000400) /*!< External Interrupt 15 to 4 */
 #define SYSCFG_ITLINE7_SR_EXTI15              ((uint32_t)0x00000800) /*!< External Interrupt 15 to 4 */
 #define SYSCFG_ITLINE8_SR_TSC_EOA             ((uint32_t)0x00000001) /*!< Touch control EOA Interrupt */
 #define SYSCFG_ITLINE8_SR_TSC_MCE             ((uint32_t)0x00000002) /*!< Touch control MCE Interrupt */
 #define SYSCFG_ITLINE9_SR_DMA1_CH1            ((uint32_t)0x00000001) /*!< DMA1 Channel 1 Interrupt */
 #define SYSCFG_ITLINE10_SR_DMA1_CH2           ((uint32_t)0x00000001) /*!< DMA1 Channel 2 Interrupt */
 #define SYSCFG_ITLINE10_SR_DMA1_CH3           ((uint32_t)0x00000002) /*!< DMA2 Channel 3 Interrupt */
 #define SYSCFG_ITLINE10_SR_DMA2_CH1           ((uint32_t)0x00000004) /*!< DMA2 Channel 1 Interrupt */
 #define SYSCFG_ITLINE10_SR_DMA2_CH2           ((uint32_t)0x00000008) /*!< DMA2 Channel 2 Interrupt */
 #define SYSCFG_ITLINE11_SR_DMA1_CH4           ((uint32_t)0x00000001) /*!< DMA1 Channel 4 Interrupt */
 #define SYSCFG_ITLINE11_SR_DMA1_CH5           ((uint32_t)0x00000002) /*!< DMA1 Channel 5 Interrupt */
 #define SYSCFG_ITLINE11_SR_DMA1_CH6           ((uint32_t)0x00000004) /*!< DMA1 Channel 6 Interrupt */
 #define SYSCFG_ITLINE11_SR_DMA1_CH7           ((uint32_t)0x00000008) /*!< DMA1 Channel 7 Interrupt */
 #define SYSCFG_ITLINE11_SR_DMA2_CH3           ((uint32_t)0x00000010) /*!< DMA2 Channel 3 Interrupt */
 #define SYSCFG_ITLINE11_SR_DMA2_CH4           ((uint32_t)0x00000020) /*!< DMA2 Channel 4 Interrupt */
 #define SYSCFG_ITLINE11_SR_DMA2_CH5           ((uint32_t)0x00000040) /*!< DMA2 Channel 5 Interrupt */
 #define SYSCFG_ITLINE12_SR_ADC                ((uint32_t)0x00000001) /*!< ADC Interrupt */
 #define SYSCFG_ITLINE12_SR_COMP1              ((uint32_t)0x00000002) /*!< COMP1 Interrupt -> exti[21] */
 #define SYSCFG_ITLINE12_SR_COMP2              ((uint32_t)0x00000004) /*!< COMP2 Interrupt -> exti[22] */
 #define SYSCFG_ITLINE13_SR_TIM1_BRK           ((uint32_t)0x00000001) /*!< TIM1 BRK Interrupt */
 #define SYSCFG_ITLINE13_SR_TIM1_UPD           ((uint32_t)0x00000002) /*!< TIM1 UPD Interrupt */
 #define SYSCFG_ITLINE13_SR_TIM1_TRG           ((uint32_t)0x00000004) /*!< TIM1 TRG Interrupt */
 #define SYSCFG_ITLINE13_SR_TIM1_CCU           ((uint32_t)0x00000008) /*!< TIM1 CCU Interrupt */
 #define SYSCFG_ITLINE14_SR_TIM1_CC            ((uint32_t)0x00000001) /*!< TIM1 CC Interrupt */
 #define SYSCFG_ITLINE15_SR_TIM2_GLB           ((uint32_t)0x00000001) /*!< TIM2 GLB Interrupt */
 #define SYSCFG_ITLINE16_SR_TIM3_GLB           ((uint32_t)0x00000001) /*!< TIM3 GLB Interrupt */
 #define SYSCFG_ITLINE17_SR_DAC                ((uint32_t)0x00000001) /*!< DAC Interrupt */
 #define SYSCFG_ITLINE17_SR_TIM6_GLB           ((uint32_t)0x00000002) /*!< TIM6 GLB Interrupt */
 #define SYSCFG_ITLINE18_SR_TIM7_GLB           ((uint32_t)0x00000001) /*!< TIM7 GLB Interrupt */
 #define SYSCFG_ITLINE19_SR_TIM14_GLB          ((uint32_t)0x00000001) /*!< TIM14 GLB Interrupt */
 #define SYSCFG_ITLINE20_SR_TIM15_GLB          ((uint32_t)0x00000001) /*!< TIM15 GLB Interrupt */
 #define SYSCFG_ITLINE21_SR_TIM16_GLB          ((uint32_t)0x00000001) /*!< TIM16 GLB Interrupt */
 #define SYSCFG_ITLINE22_SR_TIM17_GLB          ((uint32_t)0x00000001) /*!< TIM17 GLB Interrupt */
 #define SYSCFG_ITLINE23_SR_I2C1_GLB           ((uint32_t)0x00000001) /*!< I2C1 GLB Interrupt -> exti[23] */
 #define SYSCFG_ITLINE24_SR_I2C2_GLB           ((uint32_t)0x00000001) /*!< I2C2 GLB Interrupt */
 #define SYSCFG_ITLINE25_SR_SPI1               ((uint32_t)0x00000001) /*!< SPI1 Interrupt */
 #define SYSCFG_ITLINE26_SR_SPI2               ((uint32_t)0x00000001) /*!< SPI2  Interrupt */
 #define SYSCFG_ITLINE27_SR_USART1_GLB         ((uint32_t)0x00000001) /*!< USART1 GLB Interrupt -> exti[25] */
 #define SYSCFG_ITLINE28_SR_USART2_GLB         ((uint32_t)0x00000001) /*!< USART2 GLB Interrupt -> exti[26] */
 #define SYSCFG_ITLINE29_SR_USART3_GLB         ((uint32_t)0x00000001) /*!< USART3 GLB Interrupt -> exti[28] */
 #define SYSCFG_ITLINE29_SR_USART4_GLB         ((uint32_t)0x00000002) /*!< USART4 GLB Interrupt */
 #define SYSCFG_ITLINE29_SR_USART5_GLB         ((uint32_t)0x00000004) /*!< USART5 GLB Interrupt */
 #define SYSCFG_ITLINE29_SR_USART6_GLB         ((uint32_t)0x00000008) /*!< USART6 GLB Interrupt */
 #define SYSCFG_ITLINE29_SR_USART7_GLB         ((uint32_t)0x00000010) /*!< USART7 GLB Interrupt */
 #define SYSCFG_ITLINE29_SR_USART8_GLB         ((uint32_t)0x00000020) /*!< USART8 GLB Interrupt */
 #define SYSCFG_ITLINE30_SR_CAN                ((uint32_t)0x00000001) /*!< CAN Interrupt */
 #define SYSCFG_ITLINE30_SR_CEC                ((uint32_t)0x00000002) /*!< CEC Interrupt */
 /******************************************************************************/
 /*                                                                            */
 /*                               Timers (TIM)                                 */
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for TIM_CR1 register  ********************/
 #define  TIM_CR1_CEN                         ((uint16_t)0x0001)            /*!<Counter enable */
 #define  TIM_CR1_UDIS                        ((uint16_t)0x0002)            /*!<Update disable */
 #define  TIM_CR1_URS                         ((uint16_t)0x0004)            /*!<Update request source */
 #define  TIM_CR1_OPM                         ((uint16_t)0x0008)            /*!<One pulse mode */
 #define  TIM_CR1_DIR                         ((uint16_t)0x0010)            /*!<Direction */
 #define  TIM_CR1_CMS                         ((uint16_t)0x0060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
 #define  TIM_CR1_CMS_0                       ((uint16_t)0x0020)            /*!<Bit 0 */
 #define  TIM_CR1_CMS_1                       ((uint16_t)0x0040)            /*!<Bit 1 */
 #define  TIM_CR1_ARPE                        ((uint16_t)0x0080)            /*!<Auto-reload preload enable */
 #define  TIM_CR1_CKD                         ((uint16_t)0x0300)            /*!<CKD[1:0] bits (clock division) */
 #define  TIM_CR1_CKD_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
 #define  TIM_CR1_CKD_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
 /*******************  Bit definition for TIM_CR2 register  ********************/
 #define  TIM_CR2_CCPC                        ((uint16_t)0x0001)            /*!<Capture/Compare Preloaded Control */
 #define  TIM_CR2_CCUS                        ((uint16_t)0x0004)            /*!<Capture/Compare Control Update Selection */
 #define  TIM_CR2_CCDS                        ((uint16_t)0x0008)            /*!<Capture/Compare DMA Selection */
 #define  TIM_CR2_MMS                         ((uint16_t)0x0070)            /*!<MMS[2:0] bits (Master Mode Selection) */
 #define  TIM_CR2_MMS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
 #define  TIM_CR2_MMS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
 #define  TIM_CR2_MMS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
 #define  TIM_CR2_TI1S                        ((uint16_t)0x0080)            /*!<TI1 Selection */
 #define  TIM_CR2_OIS1                        ((uint16_t)0x0100)            /*!<Output Idle state 1 (OC1 output) */
 #define  TIM_CR2_OIS1N                       ((uint16_t)0x0200)            /*!<Output Idle state 1 (OC1N output) */
 #define  TIM_CR2_OIS2                        ((uint16_t)0x0400)            /*!<Output Idle state 2 (OC2 output) */
 #define  TIM_CR2_OIS2N                       ((uint16_t)0x0800)            /*!<Output Idle state 2 (OC2N output) */
 #define  TIM_CR2_OIS3                        ((uint16_t)0x1000)            /*!<Output Idle state 3 (OC3 output) */
 #define  TIM_CR2_OIS3N                       ((uint16_t)0x2000)            /*!<Output Idle state 3 (OC3N output) */
 #define  TIM_CR2_OIS4                        ((uint16_t)0x4000)            /*!<Output Idle state 4 (OC4 output) */
 /*******************  Bit definition for TIM_SMCR register  *******************/
 #define  TIM_SMCR_SMS                        ((uint16_t)0x0007)            /*!<SMS[2:0] bits (Slave mode selection) */
 #define  TIM_SMCR_SMS_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
 #define  TIM_SMCR_SMS_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
 #define  TIM_SMCR_SMS_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
 #define  TIM_SMCR_OCCS                       ((uint16_t)0x0008)            /*!< OCREF clear selection */
 #define  TIM_SMCR_TS                         ((uint16_t)0x0070)            /*!<TS[2:0] bits (Trigger selection) */
 #define  TIM_SMCR_TS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
 #define  TIM_SMCR_TS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
 #define  TIM_SMCR_TS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
 #define  TIM_SMCR_MSM                        ((uint16_t)0x0080)            /*!<Master/slave mode */
 #define  TIM_SMCR_ETF                        ((uint16_t)0x0F00)            /*!<ETF[3:0] bits (External trigger filter) */
 #define  TIM_SMCR_ETF_0                      ((uint16_t)0x0100)            /*!<Bit 0 */
 #define  TIM_SMCR_ETF_1                      ((uint16_t)0x0200)            /*!<Bit 1 */
 #define  TIM_SMCR_ETF_2                      ((uint16_t)0x0400)            /*!<Bit 2 */
 #define  TIM_SMCR_ETF_3                      ((uint16_t)0x0800)            /*!<Bit 3 */
 #define  TIM_SMCR_ETPS                       ((uint16_t)0x3000)            /*!<ETPS[1:0] bits (External trigger prescaler) */
 #define  TIM_SMCR_ETPS_0                     ((uint16_t)0x1000)            /*!<Bit 0 */
 #define  TIM_SMCR_ETPS_1                     ((uint16_t)0x2000)            /*!<Bit 1 */
 #define  TIM_SMCR_ECE                        ((uint16_t)0x4000)            /*!<External clock enable */
 #define  TIM_SMCR_ETP                        ((uint16_t)0x8000)            /*!<External trigger polarity */
 /*******************  Bit definition for TIM_DIER register  *******************/
 #define  TIM_DIER_UIE                        ((uint16_t)0x0001)            /*!<Update interrupt enable */
 #define  TIM_DIER_CC1IE                      ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt enable */
 #define  TIM_DIER_CC2IE                      ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt enable */
 #define  TIM_DIER_CC3IE                      ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt enable */
 #define  TIM_DIER_CC4IE                      ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt enable */
 #define  TIM_DIER_COMIE                      ((uint16_t)0x0020)            /*!<COM interrupt enable */
 #define  TIM_DIER_TIE                        ((uint16_t)0x0040)            /*!<Trigger interrupt enable */
 #define  TIM_DIER_BIE                        ((uint16_t)0x0080)            /*!<Break interrupt enable */
 #define  TIM_DIER_UDE                        ((uint16_t)0x0100)            /*!<Update DMA request enable */
 #define  TIM_DIER_CC1DE                      ((uint16_t)0x0200)            /*!<Capture/Compare 1 DMA request enable */
 #define  TIM_DIER_CC2DE                      ((uint16_t)0x0400)            /*!<Capture/Compare 2 DMA request enable */
 #define  TIM_DIER_CC3DE                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 DMA request enable */
 #define  TIM_DIER_CC4DE                      ((uint16_t)0x1000)            /*!<Capture/Compare 4 DMA request enable */
 #define  TIM_DIER_COMDE                      ((uint16_t)0x2000)            /*!<COM DMA request enable */
 #define  TIM_DIER_TDE                        ((uint16_t)0x4000)            /*!<Trigger DMA request enable */
 /********************  Bit definition for TIM_SR register  ********************/
 #define  TIM_SR_UIF                          ((uint16_t)0x0001)            /*!<Update interrupt Flag */
 #define  TIM_SR_CC1IF                        ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt Flag */
 #define  TIM_SR_CC2IF                        ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt Flag */
 #define  TIM_SR_CC3IF                        ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt Flag */
 #define  TIM_SR_CC4IF                        ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt Flag */
 #define  TIM_SR_COMIF                        ((uint16_t)0x0020)            /*!<COM interrupt Flag */
 #define  TIM_SR_TIF                          ((uint16_t)0x0040)            /*!<Trigger interrupt Flag */
 #define  TIM_SR_BIF                          ((uint16_t)0x0080)            /*!<Break interrupt Flag */
 #define  TIM_SR_CC1OF                        ((uint16_t)0x0200)            /*!<Capture/Compare 1 Overcapture Flag */
 #define  TIM_SR_CC2OF                        ((uint16_t)0x0400)            /*!<Capture/Compare 2 Overcapture Flag */
 #define  TIM_SR_CC3OF                        ((uint16_t)0x0800)            /*!<Capture/Compare 3 Overcapture Flag */
 #define  TIM_SR_CC4OF                        ((uint16_t)0x1000)            /*!<Capture/Compare 4 Overcapture Flag */
 /*******************  Bit definition for TIM_EGR register  ********************/
 #define  TIM_EGR_UG                          ((uint8_t)0x01)               /*!<Update Generation */
 #define  TIM_EGR_CC1G                        ((uint8_t)0x02)               /*!<Capture/Compare 1 Generation */
 #define  TIM_EGR_CC2G                        ((uint8_t)0x04)               /*!<Capture/Compare 2 Generation */
 #define  TIM_EGR_CC3G                        ((uint8_t)0x08)               /*!<Capture/Compare 3 Generation */
 #define  TIM_EGR_CC4G                        ((uint8_t)0x10)               /*!<Capture/Compare 4 Generation */
 #define  TIM_EGR_COMG                        ((uint8_t)0x20)               /*!<Capture/Compare Control Update Generation */
 #define  TIM_EGR_TG                          ((uint8_t)0x40)               /*!<Trigger Generation */
 #define  TIM_EGR_BG                          ((uint8_t)0x80)               /*!<Break Generation */
 /******************  Bit definition for TIM_CCMR1 register  *******************/
 #define  TIM_CCMR1_CC1S                      ((uint16_t)0x0003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
 #define  TIM_CCMR1_CC1S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
 #define  TIM_CCMR1_CC1S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
 #define  TIM_CCMR1_OC1FE                     ((uint16_t)0x0004)            /*!<Output Compare 1 Fast enable */
 #define  TIM_CCMR1_OC1PE                     ((uint16_t)0x0008)            /*!<Output Compare 1 Preload enable */
 #define  TIM_CCMR1_OC1M                      ((uint16_t)0x0070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
 #define  TIM_CCMR1_OC1M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
 #define  TIM_CCMR1_OC1M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
 #define  TIM_CCMR1_OC1M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
 #define  TIM_CCMR1_OC1CE                     ((uint16_t)0x0080)            /*!<Output Compare 1Clear Enable */
 #define  TIM_CCMR1_CC2S                      ((uint16_t)0x0300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
 #define  TIM_CCMR1_CC2S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
 #define  TIM_CCMR1_CC2S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
 #define  TIM_CCMR1_OC2FE                     ((uint16_t)0x0400)            /*!<Output Compare 2 Fast enable */
 #define  TIM_CCMR1_OC2PE                     ((uint16_t)0x0800)            /*!<Output Compare 2 Preload enable */
 #define  TIM_CCMR1_OC2M                      ((uint16_t)0x7000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
 #define  TIM_CCMR1_OC2M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
 #define  TIM_CCMR1_OC2M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
 #define  TIM_CCMR1_OC2M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
 #define  TIM_CCMR1_OC2CE                     ((uint16_t)0x8000)            /*!<Output Compare 2 Clear Enable */
 /*----------------------------------------------------------------------------*/
 #define  TIM_CCMR1_IC1PSC                    ((uint16_t)0x000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
 #define  TIM_CCMR1_IC1PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
 #define  TIM_CCMR1_IC1PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
 #define  TIM_CCMR1_IC1F                      ((uint16_t)0x00F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
 #define  TIM_CCMR1_IC1F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
 #define  TIM_CCMR1_IC1F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
 #define  TIM_CCMR1_IC1F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
 #define  TIM_CCMR1_IC1F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
 #define  TIM_CCMR1_IC2PSC                    ((uint16_t)0x0C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
 #define  TIM_CCMR1_IC2PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
 #define  TIM_CCMR1_IC2PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
 #define  TIM_CCMR1_IC2F                      ((uint16_t)0xF000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
 #define  TIM_CCMR1_IC2F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
 #define  TIM_CCMR1_IC2F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
 #define  TIM_CCMR1_IC2F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
 #define  TIM_CCMR1_IC2F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
 /******************  Bit definition for TIM_CCMR2 register  *******************/
 #define  TIM_CCMR2_CC3S                      ((uint16_t)0x0003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
 #define  TIM_CCMR2_CC3S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
 #define  TIM_CCMR2_CC3S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
 #define  TIM_CCMR2_OC3FE                     ((uint16_t)0x0004)            /*!<Output Compare 3 Fast enable */
 #define  TIM_CCMR2_OC3PE                     ((uint16_t)0x0008)            /*!<Output Compare 3 Preload enable */
 #define  TIM_CCMR2_OC3M                      ((uint16_t)0x0070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
 #define  TIM_CCMR2_OC3M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
 #define  TIM_CCMR2_OC3M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
 #define  TIM_CCMR2_OC3M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
 #define  TIM_CCMR2_OC3CE                     ((uint16_t)0x0080)            /*!<Output Compare 3 Clear Enable */
 #define  TIM_CCMR2_CC4S                      ((uint16_t)0x0300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
 #define  TIM_CCMR2_CC4S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
 #define  TIM_CCMR2_CC4S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
 #define  TIM_CCMR2_OC4FE                     ((uint16_t)0x0400)            /*!<Output Compare 4 Fast enable */
 #define  TIM_CCMR2_OC4PE                     ((uint16_t)0x0800)            /*!<Output Compare 4 Preload enable */
 #define  TIM_CCMR2_OC4M                      ((uint16_t)0x7000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
 #define  TIM_CCMR2_OC4M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
 #define  TIM_CCMR2_OC4M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
 #define  TIM_CCMR2_OC4M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
 #define  TIM_CCMR2_OC4CE                     ((uint16_t)0x8000)            /*!<Output Compare 4 Clear Enable */
 /*----------------------------------------------------------------------------*/
 #define  TIM_CCMR2_IC3PSC                    ((uint16_t)0x000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
 #define  TIM_CCMR2_IC3PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
 #define  TIM_CCMR2_IC3PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
 #define  TIM_CCMR2_IC3F                      ((uint16_t)0x00F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
 #define  TIM_CCMR2_IC3F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
 #define  TIM_CCMR2_IC3F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
 #define  TIM_CCMR2_IC3F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
 #define  TIM_CCMR2_IC3F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
 #define  TIM_CCMR2_IC4PSC                    ((uint16_t)0x0C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
 #define  TIM_CCMR2_IC4PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
 #define  TIM_CCMR2_IC4PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
 #define  TIM_CCMR2_IC4F                      ((uint16_t)0xF000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
 #define  TIM_CCMR2_IC4F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
 #define  TIM_CCMR2_IC4F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
 #define  TIM_CCMR2_IC4F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
 #define  TIM_CCMR2_IC4F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
 /*******************  Bit definition for TIM_CCER register  *******************/
 #define  TIM_CCER_CC1E                       ((uint16_t)0x0001)            /*!<Capture/Compare 1 output enable */
 #define  TIM_CCER_CC1P                       ((uint16_t)0x0002)            /*!<Capture/Compare 1 output Polarity */
 #define  TIM_CCER_CC1NE                      ((uint16_t)0x0004)            /*!<Capture/Compare 1 Complementary output enable */
 #define  TIM_CCER_CC1NP                      ((uint16_t)0x0008)            /*!<Capture/Compare 1 Complementary output Polarity */
 #define  TIM_CCER_CC2E                       ((uint16_t)0x0010)            /*!<Capture/Compare 2 output enable */
 #define  TIM_CCER_CC2P                       ((uint16_t)0x0020)            /*!<Capture/Compare 2 output Polarity */
 #define  TIM_CCER_CC2NE                      ((uint16_t)0x0040)            /*!<Capture/Compare 2 Complementary output enable */
 #define  TIM_CCER_CC2NP                      ((uint16_t)0x0080)            /*!<Capture/Compare 2 Complementary output Polarity */
 #define  TIM_CCER_CC3E                       ((uint16_t)0x0100)            /*!<Capture/Compare 3 output enable */
 #define  TIM_CCER_CC3P                       ((uint16_t)0x0200)            /*!<Capture/Compare 3 output Polarity */
 #define  TIM_CCER_CC3NE                      ((uint16_t)0x0400)            /*!<Capture/Compare 3 Complementary output enable */
 #define  TIM_CCER_CC3NP                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 Complementary output Polarity */
 #define  TIM_CCER_CC4E                       ((uint16_t)0x1000)            /*!<Capture/Compare 4 output enable */
 #define  TIM_CCER_CC4P                       ((uint16_t)0x2000)            /*!<Capture/Compare 4 output Polarity */
 #define  TIM_CCER_CC4NP                      ((uint16_t)0x8000)            /*!<Capture/Compare 4 Complementary output Polarity */
 /*******************  Bit definition for TIM_CNT register  ********************/
 #define  TIM_CNT_CNT                         ((uint16_t)0xFFFF)            /*!<Counter Value */
 /*******************  Bit definition for TIM_PSC register  ********************/
 #define  TIM_PSC_PSC                         ((uint16_t)0xFFFF)            /*!<Prescaler Value */
 /*******************  Bit definition for TIM_ARR register  ********************/
 #define  TIM_ARR_ARR                         ((uint16_t)0xFFFF)            /*!<actual auto-reload Value */
 /*******************  Bit definition for TIM_RCR register  ********************/
 #define  TIM_RCR_REP                         ((uint8_t)0xFF)               /*!<Repetition Counter Value */
 /*******************  Bit definition for TIM_CCR1 register  *******************/
 #define  TIM_CCR1_CCR1                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 1 Value */
 /*******************  Bit definition for TIM_CCR2 register  *******************/
 #define  TIM_CCR2_CCR2                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 2 Value */
 /*******************  Bit definition for TIM_CCR3 register  *******************/
 #define  TIM_CCR3_CCR3                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 3 Value */
 /*******************  Bit definition for TIM_CCR4 register  *******************/
 #define  TIM_CCR4_CCR4                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 4 Value */
 /*******************  Bit definition for TIM_BDTR register  *******************/
 #define  TIM_BDTR_DTG                        ((uint16_t)0x00FF)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
 #define  TIM_BDTR_DTG_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
 #define  TIM_BDTR_DTG_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
 #define  TIM_BDTR_DTG_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
 #define  TIM_BDTR_DTG_3                      ((uint16_t)0x0008)            /*!<Bit 3 */
 #define  TIM_BDTR_DTG_4                      ((uint16_t)0x0010)            /*!<Bit 4 */
 #define  TIM_BDTR_DTG_5                      ((uint16_t)0x0020)            /*!<Bit 5 */
 #define  TIM_BDTR_DTG_6                      ((uint16_t)0x0040)            /*!<Bit 6 */
 #define  TIM_BDTR_DTG_7                      ((uint16_t)0x0080)            /*!<Bit 7 */
 #define  TIM_BDTR_LOCK                       ((uint16_t)0x0300)            /*!<LOCK[1:0] bits (Lock Configuration) */
 #define  TIM_BDTR_LOCK_0                     ((uint16_t)0x0100)            /*!<Bit 0 */
 #define  TIM_BDTR_LOCK_1                     ((uint16_t)0x0200)            /*!<Bit 1 */
 #define  TIM_BDTR_OSSI                       ((uint16_t)0x0400)            /*!<Off-State Selection for Idle mode */
 #define  TIM_BDTR_OSSR                       ((uint16_t)0x0800)            /*!<Off-State Selection for Run mode */
 #define  TIM_BDTR_BKE                        ((uint16_t)0x1000)            /*!<Break enable */
 #define  TIM_BDTR_BKP                        ((uint16_t)0x2000)            /*!<Break Polarity */
 #define  TIM_BDTR_AOE                        ((uint16_t)0x4000)            /*!<Automatic Output enable */
 #define  TIM_BDTR_MOE                        ((uint16_t)0x8000)            /*!<Main Output enable */
 /*******************  Bit definition for TIM_DCR register  ********************/
 #define  TIM_DCR_DBA                         ((uint16_t)0x001F)            /*!<DBA[4:0] bits (DMA Base Address) */
 #define  TIM_DCR_DBA_0                       ((uint16_t)0x0001)            /*!<Bit 0 */
 #define  TIM_DCR_DBA_1                       ((uint16_t)0x0002)            /*!<Bit 1 */
 #define  TIM_DCR_DBA_2                       ((uint16_t)0x0004)            /*!<Bit 2 */
 #define  TIM_DCR_DBA_3                       ((uint16_t)0x0008)            /*!<Bit 3 */
 #define  TIM_DCR_DBA_4                       ((uint16_t)0x0010)            /*!<Bit 4 */
 #define  TIM_DCR_DBL                         ((uint16_t)0x1F00)            /*!<DBL[4:0] bits (DMA Burst Length) */
 #define  TIM_DCR_DBL_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
 #define  TIM_DCR_DBL_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
 #define  TIM_DCR_DBL_2                       ((uint16_t)0x0400)            /*!<Bit 2 */
 #define  TIM_DCR_DBL_3                       ((uint16_t)0x0800)            /*!<Bit 3 */
 #define  TIM_DCR_DBL_4                       ((uint16_t)0x1000)            /*!<Bit 4 */
 /*******************  Bit definition for TIM_DMAR register  *******************/
 #define  TIM_DMAR_DMAB                       ((uint16_t)0xFFFF)            /*!<DMA register for burst accesses */
 /*******************  Bit definition for TIM_OR register  *********************/
 #define TIM14_OR_TI1_RMP                       ((uint16_t)0x0003)            /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
 #define TIM14_OR_TI1_RMP_0                     ((uint16_t)0x0001)            /*!<Bit 0 */
 #define TIM14_OR_TI1_RMP_1                     ((uint16_t)0x0002)            /*!<Bit 1 */
 /******************************************************************************/
 /*                                                                            */
 /*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
 /*                                                                            */
 /******************************************************************************/
 /******************  Bit definition for USART_CR1 register  *******************/
 #define  USART_CR1_UE                        ((uint32_t)0x00000001)            /*!< USART Enable */
 #define  USART_CR1_UESM                      ((uint32_t)0x00000002)            /*!< USART Enable in STOP Mode */
 #define  USART_CR1_RE                        ((uint32_t)0x00000004)            /*!< Receiver Enable */
 #define  USART_CR1_TE                        ((uint32_t)0x00000008)            /*!< Transmitter Enable */
 #define  USART_CR1_IDLEIE                    ((uint32_t)0x00000010)            /*!< IDLE Interrupt Enable */
 #define  USART_CR1_RXNEIE                    ((uint32_t)0x00000020)            /*!< RXNE Interrupt Enable */
 #define  USART_CR1_TCIE                      ((uint32_t)0x00000040)            /*!< Transmission Complete Interrupt Enable */
 #define  USART_CR1_TXEIE                     ((uint32_t)0x00000080)            /*!< TXE Interrupt Enable */
 #define  USART_CR1_PEIE                      ((uint32_t)0x00000100)            /*!< PE Interrupt Enable */
 #define  USART_CR1_PS                        ((uint32_t)0x00000200)            /*!< Parity Selection */
 #define  USART_CR1_PCE                       ((uint32_t)0x00000400)            /*!< Parity Control Enable */
 #define  USART_CR1_WAKE                      ((uint32_t)0x00000800)            /*!< Receiver Wakeup method */
 #define  USART_CR1_M                         ((uint32_t)0x00001000)            /*!< Word length */
 #define  USART_CR1_MME                       ((uint32_t)0x00002000)            /*!< Mute Mode Enable */
 #define  USART_CR1_CMIE                      ((uint32_t)0x00004000)            /*!< Character match interrupt enable */
 #define  USART_CR1_OVER8                     ((uint32_t)0x00008000)            /*!< Oversampling by 8-bit or 16-bit mode */
 #define  USART_CR1_DEDT                      ((uint32_t)0x001F0000)            /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
 #define  USART_CR1_DEDT_0                    ((uint32_t)0x00010000)            /*!< Bit 0 */
 #define  USART_CR1_DEDT_1                    ((uint32_t)0x00020000)            /*!< Bit 1 */
 #define  USART_CR1_DEDT_2                    ((uint32_t)0x00040000)            /*!< Bit 2 */
 #define  USART_CR1_DEDT_3                    ((uint32_t)0x00080000)            /*!< Bit 3 */
 #define  USART_CR1_DEDT_4                    ((uint32_t)0x00100000)            /*!< Bit 4 */
 #define  USART_CR1_DEAT                      ((uint32_t)0x03E00000)            /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
 #define  USART_CR1_DEAT_0                    ((uint32_t)0x00200000)            /*!< Bit 0 */
 #define  USART_CR1_DEAT_1                    ((uint32_t)0x00400000)            /*!< Bit 1 */
 #define  USART_CR1_DEAT_2                    ((uint32_t)0x00800000)            /*!< Bit 2 */
 #define  USART_CR1_DEAT_3                    ((uint32_t)0x01000000)            /*!< Bit 3 */
 #define  USART_CR1_DEAT_4                    ((uint32_t)0x02000000)            /*!< Bit 4 */
 #define  USART_CR1_RTOIE                     ((uint32_t)0x04000000)            /*!< Receive Time Out interrupt enable */
 #define  USART_CR1_EOBIE                     ((uint32_t)0x08000000)            /*!< End of Block interrupt enable */
 /******************  Bit definition for USART_CR2 register  *******************/
 #define  USART_CR2_ADDM7                     ((uint32_t)0x00000010)            /*!< 7-bit or 4-bit Address Detection */
 #define  USART_CR2_LBDL                      ((uint32_t)0x00000020)            /*!< LIN Break Detection Length */
 #define  USART_CR2_LBDIE                     ((uint32_t)0x00000040)            /*!< LIN Break Detection Interrupt Enable */
 #define  USART_CR2_LBCL                      ((uint32_t)0x00000100)            /*!< Last Bit Clock pulse */
 #define  USART_CR2_CPHA                      ((uint32_t)0x00000200)            /*!< Clock Phase */
 #define  USART_CR2_CPOL                      ((uint32_t)0x00000400)            /*!< Clock Polarity */
 #define  USART_CR2_CLKEN                     ((uint32_t)0x00000800)            /*!< Clock Enable */
 #define  USART_CR2_STOP                      ((uint32_t)0x00003000)            /*!< STOP[1:0] bits (STOP bits) */
 #define  USART_CR2_STOP_0                    ((uint32_t)0x00001000)            /*!< Bit 0 */
 #define  USART_CR2_STOP_1                    ((uint32_t)0x00002000)            /*!< Bit 1 */
 #define  USART_CR2_LINEN                     ((uint32_t)0x00004000)            /*!< LIN mode enable */
 #define  USART_CR2_SWAP                      ((uint32_t)0x00008000)            /*!< SWAP TX/RX pins */
 #define  USART_CR2_RXINV                     ((uint32_t)0x00010000)            /*!< RX pin active level inversion */
 #define  USART_CR2_TXINV                     ((uint32_t)0x00020000)            /*!< TX pin active level inversion */
 #define  USART_CR2_DATAINV                   ((uint32_t)0x00040000)            /*!< Binary data inversion */
 #define  USART_CR2_MSBFIRST                  ((uint32_t)0x00080000)            /*!< Most Significant Bit First */
 #define  USART_CR2_ABREN                     ((uint32_t)0x00100000)            /*!< Auto Baud-Rate Enable*/
 #define  USART_CR2_ABRMODE                   ((uint32_t)0x00600000)            /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
 #define  USART_CR2_ABRMODE_0                 ((uint32_t)0x00200000)            /*!< Bit 0 */
 #define  USART_CR2_ABRMODE_1                 ((uint32_t)0x00400000)            /*!< Bit 1 */
 #define  USART_CR2_RTOEN                     ((uint32_t)0x00800000)            /*!< Receiver Time-Out enable */
 #define  USART_CR2_ADD                       ((uint32_t)0xFF000000)            /*!< Address of the USART node */
 /******************  Bit definition for USART_CR3 register  *******************/
 #define  USART_CR3_EIE                       ((uint32_t)0x00000001)            /*!< Error Interrupt Enable */
 #define  USART_CR3_IREN                      ((uint32_t)0x00000002)            /*!< IrDA mode Enable */
 #define  USART_CR3_IRLP                      ((uint32_t)0x00000004)            /*!< IrDA Low-Power */
 #define  USART_CR3_HDSEL                     ((uint32_t)0x00000008)            /*!< Half-Duplex Selection */
 #define  USART_CR3_NACK                      ((uint32_t)0x00000010)            /*!< SmartCard NACK enable */
 #define  USART_CR3_SCEN                      ((uint32_t)0x00000020)            /*!< SmartCard mode enable */
 #define  USART_CR3_DMAR                      ((uint32_t)0x00000040)            /*!< DMA Enable Receiver */
 #define  USART_CR3_DMAT                      ((uint32_t)0x00000080)            /*!< DMA Enable Transmitter */
 #define  USART_CR3_RTSE                      ((uint32_t)0x00000100)            /*!< RTS Enable */
 #define  USART_CR3_CTSE                      ((uint32_t)0x00000200)            /*!< CTS Enable */
 #define  USART_CR3_CTSIE                     ((uint32_t)0x00000400)            /*!< CTS Interrupt Enable */
 #define  USART_CR3_ONEBIT                    ((uint32_t)0x00000800)            /*!< One sample bit method enable */
 #define  USART_CR3_OVRDIS                    ((uint32_t)0x00001000)            /*!< Overrun Disable */
 #define  USART_CR3_DDRE                      ((uint32_t)0x00002000)            /*!< DMA Disable on Reception Error */
 #define  USART_CR3_DEM                       ((uint32_t)0x00004000)            /*!< Driver Enable Mode */
 #define  USART_CR3_DEP                       ((uint32_t)0x00008000)            /*!< Driver Enable Polarity Selection */
 #define  USART_CR3_SCARCNT                   ((uint32_t)0x000E0000)            /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
 #define  USART_CR3_SCARCNT_0                 ((uint32_t)0x00020000)            /*!< Bit 0 */
 #define  USART_CR3_SCARCNT_1                 ((uint32_t)0x00040000)            /*!< Bit 1 */
 #define  USART_CR3_SCARCNT_2                 ((uint32_t)0x00080000)            /*!< Bit 2 */
 #define  USART_CR3_WUS                       ((uint32_t)0x00300000)            /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
 #define  USART_CR3_WUS_0                     ((uint32_t)0x00100000)            /*!< Bit 0 */
 #define  USART_CR3_WUS_1                     ((uint32_t)0x00200000)            /*!< Bit 1 */
 #define  USART_CR3_WUFIE                     ((uint32_t)0x00400000)            /*!< Wake Up Interrupt Enable */
 /******************  Bit definition for USART_BRR register  *******************/
 #define  USART_BRR_DIV_FRACTION              ((uint16_t)0x000F)                /*!< Fraction of USARTDIV */
 #define  USART_BRR_DIV_MANTISSA              ((uint16_t)0xFFF0)                /*!< Mantissa of USARTDIV */
 /******************  Bit definition for USART_GTPR register  ******************/
 #define  USART_GTPR_PSC                      ((uint16_t)0x00FF)                /*!< PSC[7:0] bits (Prescaler value) */
 #define  USART_GTPR_GT                       ((uint16_t)0xFF00)                /*!< GT[7:0] bits (Guard time value) */
 /*******************  Bit definition for USART_RTOR register  *****************/
 #define  USART_RTOR_RTO                      ((uint32_t)0x00FFFFFF)            /*!< Receiver Time Out Value */
 #define  USART_RTOR_BLEN                     ((uint32_t)0xFF000000)            /*!< Block Length */
 /*******************  Bit definition for USART_RQR register  ******************/
 #define  USART_RQR_ABRRQ                    ((uint16_t)0x0001)                /*!< Auto-Baud Rate Request */
 #define  USART_RQR_SBKRQ                    ((uint16_t)0x0002)                /*!< Send Break Request */
 #define  USART_RQR_MMRQ                     ((uint16_t)0x0004)                /*!< Mute Mode Request */
 #define  USART_RQR_RXFRQ                    ((uint16_t)0x0008)                /*!< Receive Data flush Request */
 #define  USART_RQR_TXFRQ                    ((uint16_t)0x0010)                /*!< Transmit data flush Request */
 /*******************  Bit definition for USART_ISR register  ******************/
 #define  USART_ISR_PE                        ((uint32_t)0x00000001)            /*!< Parity Error */
 #define  USART_ISR_FE                        ((uint32_t)0x00000002)            /*!< Framing Error */
 #define  USART_ISR_NE                        ((uint32_t)0x00000004)            /*!< Noise detected Flag */
 #define  USART_ISR_ORE                       ((uint32_t)0x00000008)            /*!< OverRun Error */
 #define  USART_ISR_IDLE                      ((uint32_t)0x00000010)            /*!< IDLE line detected */
 #define  USART_ISR_RXNE                      ((uint32_t)0x00000020)            /*!< Read Data Register Not Empty */
 #define  USART_ISR_TC                        ((uint32_t)0x00000040)            /*!< Transmission Complete */
 #define  USART_ISR_TXE                       ((uint32_t)0x00000080)            /*!< Transmit Data Register Empty */
 #define  USART_ISR_LBD                       ((uint32_t)0x00000100)            /*!< LIN Break Detection Flag */
 #define  USART_ISR_CTSIF                     ((uint32_t)0x00000200)            /*!< CTS interrupt flag */
 #define  USART_ISR_CTS                       ((uint32_t)0x00000400)            /*!< CTS flag */
 #define  USART_ISR_RTOF                      ((uint32_t)0x00000800)            /*!< Receiver Time Out */
 #define  USART_ISR_EOBF                      ((uint32_t)0x00001000)            /*!< End Of Block Flag */
 #define  USART_ISR_ABRE                      ((uint32_t)0x00004000)            /*!< Auto-Baud Rate Error */
 #define  USART_ISR_ABRF                      ((uint32_t)0x00008000)            /*!< Auto-Baud Rate Flag */
 #define  USART_ISR_BUSY                      ((uint32_t)0x00010000)            /*!< Busy Flag */
 #define  USART_ISR_CMF                       ((uint32_t)0x00020000)            /*!< Character Match Flag */
 #define  USART_ISR_SBKF                      ((uint32_t)0x00040000)            /*!< Send Break Flag */
 #define  USART_ISR_RWU                       ((uint32_t)0x00080000)            /*!< Receive Wake Up from mute mode Flag */
 #define  USART_ISR_WUF                       ((uint32_t)0x00100000)            /*!< Wake Up from stop mode Flag */
 #define  USART_ISR_TEACK                     ((uint32_t)0x00200000)            /*!< Transmit Enable Acknowledge Flag */
 #define  USART_ISR_REACK                     ((uint32_t)0x00400000)            /*!< Receive Enable Acknowledge Flag */
 /*******************  Bit definition for USART_ICR register  ******************/
 #define  USART_ICR_PECF                      ((uint32_t)0x00000001)            /*!< Parity Error Clear Flag */
 #define  USART_ICR_FECF                      ((uint32_t)0x00000002)            /*!< Framing Error Clear Flag */
 #define  USART_ICR_NCF                      ((uint32_t)0x00000004)             /*!< Noise detected Clear Flag */
 #define  USART_ICR_ORECF                     ((uint32_t)0x00000008)            /*!< OverRun Error Clear Flag */
 #define  USART_ICR_IDLECF                    ((uint32_t)0x00000010)            /*!< IDLE line detected Clear Flag */
 #define  USART_ICR_TCCF                      ((uint32_t)0x00000040)            /*!< Transmission Complete Clear Flag */
 #define  USART_ICR_LBDCF                     ((uint32_t)0x00000100)            /*!< LIN Break Detection Clear Flag */
 #define  USART_ICR_CTSCF                     ((uint32_t)0x00000200)            /*!< CTS Interrupt Clear Flag */
 #define  USART_ICR_RTOCF                     ((uint32_t)0x00000800)            /*!< Receiver Time Out Clear Flag */
 #define  USART_ICR_EOBCF                     ((uint32_t)0x00001000)            /*!< End Of Block Clear Flag */
 #define  USART_ICR_CMCF                      ((uint32_t)0x00020000)            /*!< Character Match Clear Flag */
 #define  USART_ICR_WUCF                      ((uint32_t)0x00100000)            /*!< Wake Up from stop mode Clear Flag */
 /*******************  Bit definition for USART_RDR register  ******************/
 #define  USART_RDR_RDR                       ((uint16_t)0x01FF)                /*!< RDR[8:0] bits (Receive Data value) */
 /*******************  Bit definition for USART_TDR register  ******************/
 #define  USART_TDR_TDR                       ((uint16_t)0x01FF)                /*!< TDR[8:0] bits (Transmit Data value) */
 /******************************************************************************/
 /*                                                                            */
 /*                         Window WATCHDOG (WWDG)                             */
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bit definition for WWDG_CR register  ********************/
 #define  WWDG_CR_T                           ((uint8_t)0x7F)               /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
 #define  WWDG_CR_T0                          ((uint8_t)0x01)               /*!< Bit 0 */
 #define  WWDG_CR_T1                          ((uint8_t)0x02)               /*!< Bit 1 */
 #define  WWDG_CR_T2                          ((uint8_t)0x04)               /*!< Bit 2 */
 #define  WWDG_CR_T3                          ((uint8_t)0x08)               /*!< Bit 3 */
 #define  WWDG_CR_T4                          ((uint8_t)0x10)               /*!< Bit 4 */
 #define  WWDG_CR_T5                          ((uint8_t)0x20)               /*!< Bit 5 */
 #define  WWDG_CR_T6                          ((uint8_t)0x40)               /*!< Bit 6 */
 #define  WWDG_CR_WDGA                        ((uint8_t)0x80)               /*!< Activation bit */
 /*******************  Bit definition for WWDG_CFR register  *******************/
 #define  WWDG_CFR_W                          ((uint16_t)0x007F)            /*!< W[6:0] bits (7-bit window value) */
 #define  WWDG_CFR_W0                         ((uint16_t)0x0001)            /*!< Bit 0 */
 #define  WWDG_CFR_W1                         ((uint16_t)0x0002)            /*!< Bit 1 */
 #define  WWDG_CFR_W2                         ((uint16_t)0x0004)            /*!< Bit 2 */
 #define  WWDG_CFR_W3                         ((uint16_t)0x0008)            /*!< Bit 3 */
 #define  WWDG_CFR_W4                         ((uint16_t)0x0010)            /*!< Bit 4 */
 #define  WWDG_CFR_W5                         ((uint16_t)0x0020)            /*!< Bit 5 */
 #define  WWDG_CFR_W6                         ((uint16_t)0x0040)            /*!< Bit 6 */
 #define  WWDG_CFR_WDGTB                      ((uint16_t)0x0180)            /*!< WDGTB[1:0] bits (Timer Base) */
 #define  WWDG_CFR_WDGTB0                     ((uint16_t)0x0080)            /*!< Bit 0 */
 #define  WWDG_CFR_WDGTB1                     ((uint16_t)0x0100)            /*!< Bit 1 */
 #define  WWDG_CFR_EWI                        ((uint16_t)0x0200)            /*!< Early Wakeup Interrupt */
 /*******************  Bit definition for WWDG_SR register  ********************/
 #define  WWDG_SR_EWIF                        ((uint8_t)0x01)               /*!< Early Wakeup Interrupt Flag */
 #if defined (STM32F091)
 /******************************************************************************/
 /*  For a painless codes migration between the STM32F0xx device product       */
 /*  lines, the aliases defined below are put in place to overcome the         */
 /*  differences in the interrupt handlers and IRQn definitions.               */
 /*  No need to update developed interrupt code when moving across             */
 /*  product lines within the same STM32L0 Family                              */
 /******************************************************************************/
 /* Aliases for __IRQn */
 #define PVD_IRQn                          PVD_VDDIO2_IRQn
 #define RCC_IRQn                          RCC_CRS_IRQn
 #define TS_IRQn                           TSC_IRQn
 #define DMA1_Channel1_IRQn                DMA1_Ch1_IRQn
 #define DMA1_Channel2_3_IRQn              DMA1_Ch2_3_DMA2_Ch1_2_IRQn
 #define DMA1_Channel4_5_IRQn              DMA1_Ch4_7_DMA2_Ch3_5_IRQn
 #define DMA1_Channel4_5_6_7_IRQn          DMA1_Ch4_7_DMA2_Ch3_5_IRQn
 #define ADC1_IRQn                         ADC1_COMP_IRQn
 #define USART3_4_IRQn                     USART3_8_IRQn
 #define CEC_IRQn                          CEC_CAN_IRQn
 /* Aliases for __IRQHandler */
 #define PVD_IRQHandler                    PVD_VDDIO2_IRQHandler
 #define RCC_IRQHandler                    RCC_CRS_IRQHandler
 #define TS_IRQHandler                     TSC_IRQHandler
 #define DMA1_Channel1_IRQHandler          DMA1_Ch1_IRQHandler
 #define DMA1_Channel2_3_IRQHandler        DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
 #define DMA1_Channel4_5_IRQHandler        DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
 #define DMA1_Channel4_5_6_7_IRQHandler    DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
 #define ADC1_IRQHandler                   ADC1_COMP_IRQHandler
 #define USART3_4_IRQHandler               USART3_8_IRQHandler
 #define CEC_IRQHandler                    CEC_CAN_IRQHandler
 #elif defined (STM32F072)
 /* Aliases for __IRQn */
 #define PVD_IRQn                          PVD_VDDIO2_IRQn
 #define RCC_IRQn                          RCC_CRS_IRQn
 #define TS_IRQn                           TSC_IRQn
 #define DMA1_Ch1_IRQn                     DMA1_Channel1_IRQn
 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQn        DMA1_Channel2_3_IRQn
 #define DMA1_Channel4_5_IRQn              DMA1_Channel4_5_6_7_IRQn
 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn        DMA1_Channel4_5_6_7_IRQn
 #define ADC1_IRQn                         ADC1_COMP_IRQn
 #define USART3_8_IRQn                     USART3_4_IRQn
 #define CEC_IRQn                          CEC_CAN_IRQn
 /* Aliases for __IRQHandler */
 #define PVD_IRQHandler                    PVD_VDDIO2_IRQHandler
 #define RCC_IRQHandler                    RCC_CRS_IRQHandler
 #define TS_IRQHandler                     TSC_IRQHandler
 #define DMA1_Ch1_IRQHandler               DMA1_Channel1_IRQHandler
 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler  DMA1_Channel2_3_IRQHandler
 #define DMA1_Channel4_5_IRQHandler        DMA1_Channel4_5_6_7_IRQHandler
 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler  DMA1_Channel4_5_6_7_IRQHandler
 #define ADC1_IRQHandler                   ADC1_COMP_IRQHandler
 #define USART3_8_IRQHandler               USART3_4_IRQHandler
 #define CEC_IRQHandler                    CEC_CAN_IRQHandler
 #elif defined (STM32F051)
 /* Aliases for __IRQn */
 #define PVD_VDDIO2_IRQn                   PVD_IRQn
 #define RCC_CRS_IRQn                      RCC_IRQn
 #define TSC_IRQn                          TS_IRQn
 #define DMA1_Ch1_IRQn                     DMA1_Channel1_IRQn
 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQn        DMA1_Channel2_3_IRQn
 #define DMA1_Channel4_5_6_7_IRQn          DMA1_Channel4_5_IRQn
 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn        DMA1_Channel4_5_IRQn
 #define ADC1_IRQn                         ADC1_COMP_IRQn
 #define CEC_CAN_IRQn                      CEC_IRQn
 /* Aliases for __IRQHandler */
 #define PVD_VDDIO2_IRQHandler             PVD_IRQHandler
 #define RCC_CRS_IRQHandler                RCC_IRQHandler
 #define TSC_IRQHandler                    TS_IRQHandler
 #define DMA1_Ch1_IRQHandler               DMA1_Channel1_IRQHandler
 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler  DMA1_Channel2_3_IRQHandler
 #define DMA1_Channel4_5_6_7_IRQHandler    DMA1_Channel4_5_IRQHandler
 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler  DMA1_Channel4_5_IRQHandler
 #define ADC1_IRQHandler                   ADC1_COMP_IRQHandler
 #define CEC_CAN_IRQHandler                CEC_IRQHandler
 #elif defined (STM32F042)
 /* Aliases for __IRQn */
 #define PVD_IRQn                          PVD_VDDIO2_IRQn
 #define RCC_IRQn                          RCC_CRS_IRQn
 #define TS_IRQn                           TSC_IRQn
 #define DMA1_Ch1_IRQn                     DMA1_Channel1_IRQn
 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQn        DMA1_Channel2_3_IRQn
 #define DMA1_Channel4_5_IRQn              DMA1_Channel4_5_6_7_IRQn
 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn        DMA1_Channel4_5_6_7_IRQn
 #define ADC1_COMP_IRQn                    ADC1_IRQn
 #define CEC_IRQn                          CEC_CAN_IRQn
 /* Aliases for __IRQHandler */
 #define PVD_IRQHandler                    PVD_VDDIO2_IRQHandler
 #define RCC_IRQHandler                    RCC_CRS_IRQHandler
 #define TS_IRQHandler                     TSC_IRQHandler
 #define DMA1_Ch1_IRQHandler               DMA1_Channel1_IRQHandler
 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler  DMA1_Channel2_3_IRQHandler
 #define DMA1_Channel4_5_IRQHandler        DMA1_Channel4_5_6_7_IRQHandler
 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler  DMA1_Channel4_5_6_7_IRQHandler
 #define ADC1_COMP_IRQHandler              ADC1_IRQHandler
 #define CEC_IRQHandler                    CEC_CAN_IRQHandler
 #elif defined (STM32F031)
 /* Aliases for __IRQn */
 #define PVD_VDDIO2_IRQn                   PVD_IRQn
 #define RCC_CRS_IRQn                      RCC_IRQn
 #define DMA1_Ch1_IRQn                     DMA1_Channel1_IRQn
 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQn        DMA1_Channel2_3_IRQn
 #define DMA1_Channel4_5_6_7_IRQn          DMA1_Channel4_5_IRQn
 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn        DMA1_Channel4_5_IRQn
 #define ADC1_COMP_IRQn                    ADC1_IRQn
 /* Aliases for __IRQHandler */
 #define PVD_VDDIO2_IRQHandler             PVD_IRQHandler
 #define RCC_CRS_IRQHandler                RCC_IRQHandler
 #define DMA1_Ch1_IRQHandler               DMA1_Channel1_IRQHandler
 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler  DMA1_Channel2_3_IRQHandler
 #define DMA1_Channel4_5_6_7_IRQHandler    DMA1_Channel4_5_IRQHandler
 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler  DMA1_Channel4_5_IRQHandler
 #define ADC1_COMP_IRQHandler              ADC1_IRQHandler
 #elif defined (STM32F030)
 /* Aliases for __IRQn */
 #define RCC_CRS_IRQn                      RCC_IRQn
 #define DMA1_Ch1_IRQn                     DMA1_Channel1_IRQn
 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQn        DMA1_Channel2_3_IRQn
 #define DMA1_Channel4_5_6_7_IRQn          DMA1_Channel4_5_IRQn
 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn        DMA1_Channel4_5_IRQn
 #define ADC1_COMP_IRQn                    ADC1_IRQn
 /* Aliases for __IRQHandler */
 #define RCC_CRS_IRQHandler                RCC_IRQHandler
 #define DMA1_Ch1_IRQHandler               DMA1_Channel1_IRQHandler
 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler  DMA1_Channel2_3_IRQHandler
 #define DMA1_Channel4_5_6_7_IRQHandler    DMA1_Channel4_5_IRQHandler
 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler  DMA1_Channel4_5_IRQHandler
 #define ADC1_COMP_IRQHandler              ADC1_IRQHandler
 #endif /* STM32F091 */
 /**
   * @}
   */
  /**
   * @}
   */
 #ifdef USE_STDPERIPH_DRIVER
   #include "stm32f0xx_conf.h"
 #endif
 /** @addtogroup Exported_macro
   * @{
   */
 /**
   * @}
   */
 #ifdef __cplusplus
+}
 #endif
 #endif /* __STM32F0XX_H */
 /**
   * @}
   */
   /**
   * @}
   */
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

libraries/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h

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Show inline comments

@@ new file 100644 @@
 /**
   ******************************************************************************
   * @file    system_stm32f0xx.h
   * @author  MCD Application Team
   * @version V1.4.0
   * @date    24-July-2014
   * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer System Header File.
   ******************************************************************************
   * @attention
+  *
   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
   * You may not use this file except in compliance with the License.
   * You may obtain a copy of the License at:
+  *
   *        http://www.st.com/software_license_agreement_liberty_v2
+  *
   * Unless required by applicable law or agreed to in writing, software
   * distributed under the License is distributed on an "AS IS" BASIS,
   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
   * See the License for the specific language governing permissions and
   * limitations under the License.
+  *
   ******************************************************************************
   */
 /** @addtogroup CMSIS
   * @{
   */
 /** @addtogroup stm32f0xx_system
   * @{
   */
 /**
   * @brief Define to prevent recursive inclusion
   */
 #ifndef __SYSTEM_STM32F0XX_H
 #define __SYSTEM_STM32F0XX_H
 #ifdef __cplusplus
  extern "C" {
 #endif
 /** @addtogroup STM32F0xx_System_Includes
   * @{
   */
 /**
   * @}
   */
 /** @addtogroup STM32F0xx_System_Exported_types
   * @{
   */
 extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
 /**
   * @}
   */
 /** @addtogroup STM32F0xx_System_Exported_Constants
   * @{
   */
 /**
   * @}
   */
 /** @addtogroup STM32F0xx_System_Exported_Macros
   * @{
   */
 /**
   * @}
   */
 /** @addtogroup STM32F0xx_System_Exported_Functions
   * @{
   */
 extern void SystemInit(void);
 extern void SystemCoreClockUpdate(void);
 /**
   * @}
   */
 #ifdef __cplusplus
+}
 #endif
 #endif /*__SYSTEM_STM32F0XX_H */
 /**
   * @}
   */
 /**
   * @}
   */
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f030.s

➞

Show inline comments

@@ new file 100644 @@
 /**
   ******************************************************************************
   * @file      startup_stm32f030.s
   * @author    MCD Application Team
   * @version   V1.4.0
   * @date      24-July-2014
   * @brief     STM32F030 Devices vector table for Atollic toolchain.
   *            This module performs:
   *                - Set the initial SP
   *                - Set the initial PC == Reset_Handler,
   *                - Set the vector table entries with the exceptions ISR address
   *                - Configure the system clock
   *                - Branches to main in the C library (which eventually
   *                  calls main()).
   *            After Reset the Cortex-M0 processor is in Thread mode,
   *            priority is Privileged, and the Stack is set to Main.
   ******************************************************************************
   * @attention
+  *
   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
   * You may not use this file except in compliance with the License.
   * You may obtain a copy of the License at:
+  *
   *        http://www.st.com/software_license_agreement_liberty_v2
+  *
   * Unless required by applicable law or agreed to in writing, software
   * distributed under the License is distributed on an "AS IS" BASIS,
   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
   * See the License for the specific language governing permissions and
   * limitations under the License.
+  *
   ******************************************************************************
   */
   .syntax unified
   .cpu cortex-m0
   .fpu softvfp
   .thumb
 .global g_pfnVectors
 .global Default_Handler
 /* start address for the initialization values of the .data section.
 defined in linker script */
 .word _sidata
 /* start address for the .data section. defined in linker script */
 .word _sdata
 /* end address for the .data section. defined in linker script */
 .word _edata
 /* start address for the .bss section. defined in linker script */
 .word _sbss
 /* end address for the .bss section. defined in linker script */
 .word _ebss
   .section .text.Reset_Handler
   .weak Reset_Handler
   .type Reset_Handler, %function
 Reset_Handler:
   ldr   r0, =_estack
   mov   sp, r0          /* set stack pointer */
 /*Check if boot space corresponds to test memory*/
     LDR R0,=0x00000004
     LDR R1, [R0]
     LSRS R1, R1, #24
     LDR R2,=0x1F
     CMP R1, R2
     BNE ApplicationStart
  /*SYSCFG clock enable*/
     LDR R0,=0x40021018
     LDR R1,=0x00000001
     STR R1, [R0]
 /*Set CFGR1 register with flash memory remap at address 0*/
     LDR R0,=0x40010000
     LDR R1,=0x00000000
     STR R1, [R0]
 ApplicationStart:
 /* Copy the data segment initializers from flash to SRAM */
   movs r1, #0
   b LoopCopyDataInit
 CopyDataInit:
   ldr r3, =_sidata
   ldr r3, [r3, r1]
   str r3, [r0, r1]
   adds r1, r1, #4
 LoopCopyDataInit:
   ldr r0, =_sdata
   ldr r3, =_edata
   adds r2, r0, r1
   cmp r2, r3
   bcc CopyDataInit
   ldr r2, =_sbss
   b LoopFillZerobss
 /* Zero fill the bss segment. */
 FillZerobss:
   movs r3, #0
   str  r3, [r2]
   adds r2, r2, #4
 LoopFillZerobss:
   ldr r3, = _ebss
   cmp r2, r3
   bcc FillZerobss
 /* Call the clock system intitialization function.*/
     bl  SystemInit
 /* Call static constructors */
     bl __libc_init_array
 /* Call the application's entry point.*/
   bl main
 LoopForever:
     b LoopForever
 .size Reset_Handler, .-Reset_Handler
 /**
  * @brief  This is the code that gets called when the processor receives an
  *         unexpected interrupt.  This simply enters an infinite loop, preserving
  *         the system state for examination by a debugger.
+ *
  * @param  None
  * @retval : None
 */
     .section .text.Default_Handler,"ax",%progbits
 Default_Handler:
 Infinite_Loop:
   b Infinite_Loop
   .size Default_Handler, .-Default_Handler
 /******************************************************************************
+*
 * The minimal vector table for a Cortex M0.  Note that the proper constructs
 * must be placed on this to ensure that it ends up at physical address
 * 0x0000.0000.
+*
 ******************************************************************************/
    .section .isr_vector,"a",%progbits
   .type g_pfnVectors, %object
   .size g_pfnVectors, .-g_pfnVectors
 g_pfnVectors:
   .word _estack
   .word Reset_Handler
   .word NMI_Handler
   .word HardFault_Handler
   .word 0
   .word 0
   .word 0
   .word 0
   .word 0
   .word 0
   .word 0
   .word SVC_Handler
   .word 0
   .word 0
   .word PendSV_Handler
   .word SysTick_Handler
   .word WWDG_IRQHandler
   .word 0
   .word RTC_IRQHandler
   .word FLASH_IRQHandler
   .word RCC_IRQHandler
   .word EXTI0_1_IRQHandler
   .word EXTI2_3_IRQHandler
   .word EXTI4_15_IRQHandler
   .word 0
   .word DMA1_Channel1_IRQHandler
   .word DMA1_Channel2_3_IRQHandler
   .word DMA1_Channel4_5_IRQHandler
   .word ADC1_IRQHandler
   .word TIM1_BRK_UP_TRG_COM_IRQHandler
   .word TIM1_CC_IRQHandler
   .word 0
   .word TIM3_IRQHandler
   .word 0
   .word 0
   .word TIM14_IRQHandler
   .word TIM15_IRQHandler
   .word TIM16_IRQHandler
   .word TIM17_IRQHandler
   .word I2C1_IRQHandler
   .word I2C2_IRQHandler
   .word SPI1_IRQHandler
   .word SPI2_IRQHandler
   .word USART1_IRQHandler
   .word USART2_IRQHandler
   .word 0
   .word 0
   .word 0
 /*******************************************************************************
+*
 * Provide weak aliases for each Exception handler to the Default_Handler.
 * As they are weak aliases, any function with the same name will override
 * this definition.
+*
 *******************************************************************************/
   .weak NMI_Handler
   .thumb_set NMI_Handler,Default_Handler
   .weak HardFault_Handler
   .thumb_set HardFault_Handler,Default_Handler
   .weak SVC_Handler
   .thumb_set SVC_Handler,Default_Handler
   .weak PendSV_Handler
   .thumb_set PendSV_Handler,Default_Handler
   .weak SysTick_Handler
   .thumb_set SysTick_Handler,Default_Handler
   .weak WWDG_IRQHandler
   .thumb_set WWDG_IRQHandler,Default_Handler
   .weak RTC_IRQHandler
   .thumb_set RTC_IRQHandler,Default_Handler
   .weak FLASH_IRQHandler
   .thumb_set FLASH_IRQHandler,Default_Handler
   .weak RCC_IRQHandler
   .thumb_set RCC_IRQHandler,Default_Handler
   .weak EXTI0_1_IRQHandler
   .thumb_set EXTI0_1_IRQHandler,Default_Handler
   .weak EXTI2_3_IRQHandler
   .thumb_set EXTI2_3_IRQHandler,Default_Handler
   .weak EXTI4_15_IRQHandler
   .thumb_set EXTI4_15_IRQHandler,Default_Handler
   .weak DMA1_Channel1_IRQHandler
   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
   .weak DMA1_Channel2_3_IRQHandler
   .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
   .weak DMA1_Channel4_5_IRQHandler
   .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
   .weak ADC1_IRQHandler
   .thumb_set ADC1_IRQHandler,Default_Handler
   .weak TIM1_BRK_UP_TRG_COM_IRQHandler
   .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
   .weak TIM1_CC_IRQHandler
   .thumb_set TIM1_CC_IRQHandler,Default_Handler
   .weak TIM3_IRQHandler
   .thumb_set TIM3_IRQHandler,Default_Handler
   .weak TIM14_IRQHandler
   .thumb_set TIM14_IRQHandler,Default_Handler
   .weak TIM15_IRQHandler
   .thumb_set TIM15_IRQHandler,Default_Handler
   .weak TIM16_IRQHandler
   .thumb_set TIM16_IRQHandler,Default_Handler
   .weak TIM17_IRQHandler
   .thumb_set TIM17_IRQHandler,Default_Handler
   .weak I2C1_IRQHandler
   .thumb_set I2C1_IRQHandler,Default_Handler
   .weak I2C2_IRQHandler
   .thumb_set I2C2_IRQHandler,Default_Handler
   .weak SPI1_IRQHandler
   .thumb_set SPI1_IRQHandler,Default_Handler
   .weak SPI2_IRQHandler
   .thumb_set SPI2_IRQHandler,Default_Handler
   .weak USART1_IRQHandler
   .thumb_set USART1_IRQHandler,Default_Handler
   .weak USART2_IRQHandler
   .thumb_set USART2_IRQHandler,Default_Handler
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f031.s

➞

Show inline comments

@@ new file 100644 @@
 /**
   ******************************************************************************
   * @file      startup_stm32f031.s
   * @author    MCD Application Team
   * @version   V1.4.0
   * @date      24-July-2014
   * @brief     STM32F031 Devices vector table for Atollic toolchain.
   *            This module performs:
   *                - Set the initial SP
   *                - Set the initial PC == Reset_Handler,
   *                - Set the vector table entries with the exceptions ISR address
   *                - Configure the system clock
   *                - Branches to main in the C library (which eventually
   *                  calls main()).
   *            After Reset the Cortex-M0 processor is in Thread mode,
   *            priority is Privileged, and the Stack is set to Main.
   ******************************************************************************
   * @attention
+  *
   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
   * You may not use this file except in compliance with the License.
   * You may obtain a copy of the License at:
+  *
   *        http://www.st.com/software_license_agreement_liberty_v2
+  *
   * Unless required by applicable law or agreed to in writing, software
   * distributed under the License is distributed on an "AS IS" BASIS,
   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
   * See the License for the specific language governing permissions and
   * limitations under the License.
+  *
   ******************************************************************************
   */
   .syntax unified
   .cpu cortex-m0
   .fpu softvfp
   .thumb
 .global g_pfnVectors
 .global Default_Handler
 /* start address for the initialization values of the .data section.
 defined in linker script */
 .word _sidata
 /* start address for the .data section. defined in linker script */
 .word _sdata
 /* end address for the .data section. defined in linker script */
 .word _edata
 /* start address for the .bss section. defined in linker script */
 .word _sbss
 /* end address for the .bss section. defined in linker script */
 .word _ebss
   .section .text.Reset_Handler
   .weak Reset_Handler
   .type Reset_Handler, %function
 Reset_Handler:
   ldr   r0, =_estack
   mov   sp, r0          /* set stack pointer */
 /*Check if boot space corresponds to test memory*/
     LDR R0,=0x00000004
     LDR R1, [R0]
     LSRS R1, R1, #24
     LDR R2,=0x1F
     CMP R1, R2
     BNE ApplicationStart
  /*SYSCFG clock enable*/
     LDR R0,=0x40021018
     LDR R1,=0x00000001
     STR R1, [R0]
 /*Set CFGR1 register with flash memory remap at address 0*/
     LDR R0,=0x40010000
     LDR R1,=0x00000000
     STR R1, [R0]
 ApplicationStart:
 /* Copy the data segment initializers from flash to SRAM */
   movs r1, #0
   b LoopCopyDataInit
 CopyDataInit:
   ldr r3, =_sidata
   ldr r3, [r3, r1]
   str r3, [r0, r1]
   adds r1, r1, #4
 LoopCopyDataInit:
   ldr r0, =_sdata
   ldr r3, =_edata
   adds r2, r0, r1
   cmp r2, r3
   bcc CopyDataInit
   ldr r2, =_sbss
   b LoopFillZerobss
 /* Zero fill the bss segment. */
 FillZerobss:
   movs r3, #0
   str  r3, [r2]
   adds r2, r2, #4
 LoopFillZerobss:
   ldr r3, = _ebss
   cmp r2, r3
   bcc FillZerobss
 /* Call the clock system intitialization function.*/
     bl  SystemInit
 /* Call static constructors */
     bl __libc_init_array
 /* Call the application's entry point.*/
   bl main
 LoopForever:
     b LoopForever
 .size Reset_Handler, .-Reset_Handler
 /**
  * @brief  This is the code that gets called when the processor receives an
  *         unexpected interrupt.  This simply enters an infinite loop, preserving
  *         the system state for examination by a debugger.
+ *
  * @param  None
  * @retval : None
 */
     .section .text.Default_Handler,"ax",%progbits
 Default_Handler:
 Infinite_Loop:
   b Infinite_Loop
   .size Default_Handler, .-Default_Handler
 /******************************************************************************
+*
 * The minimal vector table for a Cortex M0.  Note that the proper constructs
 * must be placed on this to ensure that it ends up at physical address
 * 0x0000.0000.
+*
 ******************************************************************************/
    .section .isr_vector,"a",%progbits
   .type g_pfnVectors, %object
   .size g_pfnVectors, .-g_pfnVectors
 g_pfnVectors:
   .word _estack
   .word Reset_Handler
   .word NMI_Handler
   .word HardFault_Handler
   .word 0
   .word 0
   .word 0
   .word 0
   .word 0
   .word 0
   .word 0
   .word SVC_Handler
   .word 0
   .word 0
   .word PendSV_Handler
   .word SysTick_Handler
   .word WWDG_IRQHandler
   .word PVD_IRQHandler
   .word RTC_IRQHandler
   .word FLASH_IRQHandler
   .word RCC_IRQHandler
   .word EXTI0_1_IRQHandler
   .word EXTI2_3_IRQHandler
   .word EXTI4_15_IRQHandler
   .word 0
   .word DMA1_Channel1_IRQHandler
   .word DMA1_Channel2_3_IRQHandler
   .word DMA1_Channel4_5_IRQHandler
   .word ADC1_IRQHandler
   .word TIM1_BRK_UP_TRG_COM_IRQHandler
   .word TIM1_CC_IRQHandler
   .word TIM2_IRQHandler
   .word TIM3_IRQHandler
   .word 0
   .word 0
   .word TIM14_IRQHandler
   .word 0
   .word TIM16_IRQHandler
   .word TIM17_IRQHandler
   .word I2C1_IRQHandler
   .word 0
   .word SPI1_IRQHandler
   .word 0
   .word USART1_IRQHandler
   .word 0
   .word 0
   .word 0
   .word 0
 /*******************************************************************************
+*
 * Provide weak aliases for each Exception handler to the Default_Handler.
 * As they are weak aliases, any function with the same name will override
 * this definition.
+*
 *******************************************************************************/
   .weak NMI_Handler
   .thumb_set NMI_Handler,Default_Handler
   .weak HardFault_Handler
   .thumb_set HardFault_Handler,Default_Handler
   .weak SVC_Handler
   .thumb_set SVC_Handler,Default_Handler
   .weak PendSV_Handler
   .thumb_set PendSV_Handler,Default_Handler
   .weak SysTick_Handler
   .thumb_set SysTick_Handler,Default_Handler
   .weak WWDG_IRQHandler
   .thumb_set WWDG_IRQHandler,Default_Handler
   .weak PVD_IRQHandler
   .thumb_set PVD_IRQHandler,Default_Handler
   .weak RTC_IRQHandler
   .thumb_set RTC_IRQHandler,Default_Handler
   .weak FLASH_IRQHandler
   .thumb_set FLASH_IRQHandler,Default_Handler
   .weak RCC_IRQHandler
   .thumb_set RCC_IRQHandler,Default_Handler
   .weak EXTI0_1_IRQHandler
   .thumb_set EXTI0_1_IRQHandler,Default_Handler
   .weak EXTI2_3_IRQHandler
   .thumb_set EXTI2_3_IRQHandler,Default_Handler
   .weak EXTI4_15_IRQHandler
   .thumb_set EXTI4_15_IRQHandler,Default_Handler
   .weak DMA1_Channel1_IRQHandler
   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
   .weak DMA1_Channel2_3_IRQHandler
   .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
   .weak DMA1_Channel4_5_IRQHandler
   .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
   .weak ADC1_IRQHandler
   .thumb_set ADC1_IRQHandler,Default_Handler
   .weak TIM1_BRK_UP_TRG_COM_IRQHandler
   .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
   .weak TIM1_CC_IRQHandler
   .thumb_set TIM1_CC_IRQHandler,Default_Handler
   .weak TIM2_IRQHandler
   .thumb_set TIM2_IRQHandler,Default_Handler
   .weak TIM3_IRQHandler
   .thumb_set TIM3_IRQHandler,Default_Handler
   .weak TIM14_IRQHandler
   .thumb_set TIM14_IRQHandler,Default_Handler
   .weak TIM16_IRQHandler
   .thumb_set TIM16_IRQHandler,Default_Handler
   .weak TIM17_IRQHandler
   .thumb_set TIM17_IRQHandler,Default_Handler
   .weak I2C1_IRQHandler
   .thumb_set I2C1_IRQHandler,Default_Handler
   .weak SPI1_IRQHandler
   .thumb_set SPI1_IRQHandler,Default_Handler
   .weak USART1_IRQHandler
   .thumb_set USART1_IRQHandler,Default_Handler
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
@@ \ No newline at end of file @@

libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f042.s

➞

Show inline comments

@@ new file 100644 @@
 /**
   ******************************************************************************
   * @file      startup_stm32f042.s
   * @author    MCD Application Team
   * @version   V1.4.0
   * @date      24-July-2014
   * @brief     STM32F042 Devices vector table for Atollic toolchain.
   *            This module performs:
   *                - Set the initial SP
   *                - Set the initial PC == Reset_Handler,
   *                - Set the vector table entries with the exceptions ISR address
   *                - Configure the system clock
   *                - Branches to main in the C library (which eventually
   *                  calls main()).
   *            After Reset the Cortex-M0 processor is in Thread mode,
   *            priority is Privileged, and the Stack is set to Main.
   ******************************************************************************
   * @attention
+  *
   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
   * You may not use this file except in compliance with the License.
   * You may obtain a copy of the License at:
+  *
   *        http://www.st.com/software_license_agreement_liberty_v2
+  *
   * Unless required by applicable law or agreed to in writing, software
   * distributed under the License is distributed on an "AS IS" BASIS,
   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
   * See the License for the specific language governing permissions and
   * limitations under the License.
+  *
   ******************************************************************************
   */
   .syntax unified
   .cpu cortex-m0
   .fpu softvfp
   .thumb
 .global g_pfnVectors
 .global Default_Handler
 /* start address for the initialization values of the .data section.
 defined in linker script */
 .word _sidata
 /* start address for the .data section. defined in linker script */
 .word _sdata
 /* end address for the .data section. defined in linker script */
 .word _edata
 /* start address for the .bss section. defined in linker script */
 .word _sbss
 /* end address for the .bss section. defined in linker script */
 .word _ebss
   .section .text.Reset_Handler
   .weak Reset_Handler
   .type Reset_Handler, %function
 Reset_Handler:
   ldr   r0, =_estack
   mov   sp, r0          /* set stack pointer */
 /*Check if boot space corresponds to test memory*/
     LDR R0,=0x00000004
     LDR R1, [R0]
     LSRS R1, R1, #24
     LDR R2,=0x1F
     CMP R1, R2
     BNE ApplicationStart
  /*SYSCFG clock enable*/
     LDR R0,=0x40021018
     LDR R1,=0x00000001
     STR R1, [R0]
 /*Set CFGR1 register with flash memory remap at address 0*/
     LDR R0,=0x40010000
     LDR R1,=0x00000000
     STR R1, [R0]
 ApplicationStart:
 /* Copy the data segment initializers from flash to SRAM */
   movs r1, #0
   b LoopCopyDataInit
 CopyDataInit:
   ldr r3, =_sidata
   ldr r3, [r3, r1]
   str r3, [r0, r1]
   adds r1, r1, #4
 LoopCopyDataInit:
   ldr r0, =_sdata
   ldr r3, =_edata
   adds r2, r0, r1
   cmp r2, r3
   bcc CopyDataInit
   ldr r2, =_sbss
   b LoopFillZerobss
 /* Zero fill the bss segment. */
 FillZerobss:
   movs r3, #0
   str  r3, [r2]
   adds r2, r2, #4
 LoopFillZerobss:
   ldr r3, = _ebss
   cmp r2, r3
   bcc FillZerobss
 /* Call the clock system intitialization function.*/
     bl  SystemInit
 /* Call static constructors */
     bl __libc_init_array
 /* Call the application's entry point.*/
   bl main
 LoopForever:
     b LoopForever
 .size Reset_Handler, .-Reset_Handler
 /**
  * @brief  This is the code that gets called when the processor receives an
  *         unexpected interrupt.  This simply enters an infinite loop, preserving
  *         the system state for examination by a debugger.
+ *
  * @param  None
  * @retval : None
 */
     .section .text.Default_Handler,"ax",%progbits
 Default_Handler:
 Infinite_Loop:
   b Infinite_Loop
   .size Default_Handler, .-Default_Handler
 /******************************************************************************
+*
 * The minimal vector table for a Cortex M0.  Note that the proper constructs
 * must be placed on this to ensure that it ends up at physical address
 * 0x0000.0000.
+*
 ******************************************************************************/
    .section .isr_vector,"a",%progbits
   .type g_pfnVectors, %object
   .size g_pfnVectors, .-g_pfnVectors
 g_pfnVectors:
   .word _estack
   .word Reset_Handler
   .word NMI_Handler
   .word HardFault_Handler
   .word 0
   .word 0
   .word 0
   .word 0
   .word 0
   .word 0
   .word 0
   .word SVC_Handler
   .word 0
   .word 0
   .word PendSV_Handler
   .word SysTick_Handler
   .word WWDG_IRQHandler
   .word PVD_VDDIO2_IRQHandler
   .word RTC_IRQHandler
   .word FLASH_IRQHandler
   .word RCC_CRS_IRQHandler
   .word EXTI0_1_IRQHandler
   .word EXTI2_3_IRQHandler
   .word EXTI4_15_IRQHandler
   .word TSC_IRQHandler
   .word DMA1_Channel1_IRQHandler
   .word DMA1_Channel2_3_IRQHandler
   .word DMA1_Channel4_5_IRQHandler
   .word ADC1_IRQHandler
   .word TIM1_BRK_UP_TRG_COM_IRQHandler
   .word TIM1_CC_IRQHandler
   .word TIM2_IRQHandler
   .word TIM3_IRQHandler
   .word 0
   .word 0
   .word TIM14_IRQHandler
   .word 0
   .word TIM16_IRQHandler
   .word TIM17_IRQHandler
   .word I2C1_IRQHandler
   .word 0
   .word SPI1_IRQHandler
   .word SPI2_IRQHandler
   .word USART1_IRQHandler
   .word USART2_IRQHandler
   .word 0
   .word CEC_CAN_IRQHandler
   .word USB_IRQHandler
 /*******************************************************************************
+*
 * Provide weak aliases for each Exception handler to the Default_Handler.
 * As they are weak aliases, any function with the same name will override
 * this definition.
+*
 *******************************************************************************/
   .weak NMI_Handler
   .thumb_set NMI_Handler,Default_Handler
   .weak HardFault_Handler
   .thumb_set HardFault_Handler,Default_Handler
   .weak SVC_Handler
   .thumb_set SVC_Handler,Default_Handler
   .weak PendSV_Handler
   .thumb_set PendSV_Handler,Default_Handler
   .weak SysTick_Handler
   .thumb_set SysTick_Handler,Default_Handler
   .weak WWDG_IRQHandler
   .thumb_set WWDG_IRQHandler,Default_Handler
   .weak PVD_VDDIO2_IRQHandler
   .thumb_set PVD_VDDIO2_IRQHandler,Default_Handler
   .weak RTC_IRQHandler
   .thumb_set RTC_IRQHandler,Default_Handler
   .weak FLASH_IRQHandler
   .thumb_set FLASH_IRQHandler,Default_Handler
   .weak RCC_CRS_IRQHandler
   .thumb_set RCC_CRS_IRQHandler,Default_Handler
   .weak EXTI0_1_IRQHandler
   .thumb_set EXTI0_1_IRQHandler,Default_Handler
   .weak EXTI2_3_IRQHandler
   .thumb_set EXTI2_3_IRQHandler,Default_Handler
   .weak EXTI4_15_IRQHandler
   .thumb_set EXTI4_15_IRQHandler,Default_Handler
   .weak TSC_IRQHandler
   .thumb_set TSC_IRQHandler,Default_Handler
   .weak DMA1_Channel1_IRQHandler
   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
   .weak DMA1_Channel2_3_IRQHandler
   .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
   .weak DMA1_Channel4_5_IRQHandler
   .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
   .weak ADC1_IRQHandler
   .thumb_set ADC1_IRQHandler,Default_Handler
   .weak TIM1_BRK_UP_TRG_COM_IRQHandler
   .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
   .weak TIM1_CC_IRQHandler
   .thumb_set TIM1_CC_IRQHandler,Default_Handler
   .weak TIM2_IRQHandler
   .thumb_set TIM2_IRQHandler,Default_Handler
   .weak TIM3_IRQHandler
   .thumb_set TIM3_IRQHandler,Default_Handler
   .weak TIM14_IRQHandler
   .thumb_set TIM14_IRQHandler,Default_Handler
   .weak TIM16_IRQHandler
   .thumb_set TIM16_IRQHandler,Default_Handler
   .weak TIM17_IRQHandler
   .thumb_set TIM17_IRQHandler,Default_Handler
   .weak I2C1_IRQHandler
   .thumb_set I2C1_IRQHandler,Default_Handler
   .weak SPI1_IRQHandler
   .thumb_set SPI1_IRQHandler,Default_Handler
   .weak SPI2_IRQHandler
   .thumb_set SPI2_IRQHandler,Default_Handler
   .weak USART1_IRQHandler
   .thumb_set USART1_IRQHandler,Default_Handler
   .weak USART2_IRQHandler
   .thumb_set USART2_IRQHandler,Default_Handler
   .weak CEC_CAN_IRQHandler
   .thumb_set CEC_CAN_IRQHandler,Default_Handler
   .weak USB_IRQHandler
   .thumb_set USB_IRQHandler,Default_Handler
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f051.s

➞

Show inline comments

@@ new file 100644 @@
 /**
   ******************************************************************************
   * @file      startup_stm32f051.s
   * @author    MCD Application Team
   * @version   V1.4.0
   * @date      24-July-2014
   * @brief     STM32F051 Devices vector table for Atollic toolchain.
   *            This module performs:
   *                - Set the initial SP
   *                - Set the initial PC == Reset_Handler,
   *                - Set the vector table entries with the exceptions ISR address
   *                - Configure the system clock
   *                - Branches to main in the C library (which eventually
   *                  calls main()).
   *            After Reset the Cortex-M0 processor is in Thread mode,
   *            priority is Privileged, and the Stack is set to Main.
   ******************************************************************************
   * @attention
+  *
   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
   * You may not use this file except in compliance with the License.
   * You may obtain a copy of the License at:
+  *
   *        http://www.st.com/software_license_agreement_liberty_v2
+  *
   * Unless required by applicable law or agreed to in writing, software
   * distributed under the License is distributed on an "AS IS" BASIS,
   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
   * See the License for the specific language governing permissions and
   * limitations under the License.
+  *
   ******************************************************************************
   */
   .syntax unified
   .cpu cortex-m0
   .fpu softvfp
   .thumb
 .global g_pfnVectors
 .global Default_Handler
 /* start address for the initialization values of the .data section.
 defined in linker script */
 .word _sidata
 /* start address for the .data section. defined in linker script */
 .word _sdata
 /* end address for the .data section. defined in linker script */
 .word _edata
 /* start address for the .bss section. defined in linker script */
 .word _sbss
 /* end address for the .bss section. defined in linker script */
 .word _ebss
   .section .text.Reset_Handler
   .weak Reset_Handler
   .type Reset_Handler, %function
 Reset_Handler:
   ldr   r0, =_estack
   mov   sp, r0          /* set stack pointer */
 /*Check if boot space corresponds to test memory*/
     LDR R0,=0x00000004
     LDR R1, [R0]
     LSRS R1, R1, #24
     LDR R2,=0x1F
     CMP R1, R2
     BNE ApplicationStart
  /*SYSCFG clock enable*/
     LDR R0,=0x40021018
     LDR R1,=0x00000001
     STR R1, [R0]
 /*Set CFGR1 register with flash memory remap at address 0*/
     LDR R0,=0x40010000
     LDR R1,=0x00000000
     STR R1, [R0]
 ApplicationStart:
 /* Copy the data segment initializers from flash to SRAM */
   movs r1, #0
   b LoopCopyDataInit
 CopyDataInit:
   ldr r3, =_sidata
   ldr r3, [r3, r1]
   str r3, [r0, r1]
   adds r1, r1, #4
 LoopCopyDataInit:
   ldr r0, =_sdata
   ldr r3, =_edata
   adds r2, r0, r1
   cmp r2, r3
   bcc CopyDataInit
   ldr r2, =_sbss
   b LoopFillZerobss
 /* Zero fill the bss segment. */
 FillZerobss:
   movs r3, #0
   str  r3, [r2]
   adds r2, r2, #4
 LoopFillZerobss:
   ldr r3, = _ebss
   cmp r2, r3
   bcc FillZerobss
 /* Call the clock system intitialization function.*/
     bl  SystemInit
 /* Call static constructors */
     bl __libc_init_array
 /* Call the application's entry point.*/
   bl main
 LoopForever:
     b LoopForever
 .size Reset_Handler, .-Reset_Handler
 /**
  * @brief  This is the code that gets called when the processor receives an
  *         unexpected interrupt.  This simply enters an infinite loop, preserving
  *         the system state for examination by a debugger.
+ *
  * @param  None
  * @retval : None
 */
     .section .text.Default_Handler,"ax",%progbits
 Default_Handler:
 Infinite_Loop:
   b Infinite_Loop
   .size Default_Handler, .-Default_Handler
 /******************************************************************************
+*
 * The minimal vector table for a Cortex M0.  Note that the proper constructs
 * must be placed on this to ensure that it ends up at physical address
 * 0x0000.0000.
+*
 ******************************************************************************/
    .section .isr_vector,"a",%progbits
   .type g_pfnVectors, %object
   .size g_pfnVectors, .-g_pfnVectors
 g_pfnVectors:
   .word _estack
   .word Reset_Handler
   .word NMI_Handler
   .word HardFault_Handler
   .word 0
   .word 0
   .word 0
   .word 0
   .word 0
   .word 0
   .word 0
   .word SVC_Handler
   .word 0
   .word 0
   .word PendSV_Handler
   .word SysTick_Handler
   .word WWDG_IRQHandler
   .word PVD_IRQHandler
   .word RTC_IRQHandler
   .word FLASH_IRQHandler
   .word RCC_IRQHandler
   .word EXTI0_1_IRQHandler
   .word EXTI2_3_IRQHandler
   .word EXTI4_15_IRQHandler
   .word TS_IRQHandler
   .word DMA1_Channel1_IRQHandler
   .word DMA1_Channel2_3_IRQHandler
   .word DMA1_Channel4_5_IRQHandler
   .word ADC1_COMP_IRQHandler
   .word TIM1_BRK_UP_TRG_COM_IRQHandler
   .word TIM1_CC_IRQHandler
   .word TIM2_IRQHandler
   .word TIM3_IRQHandler
   .word TIM6_DAC_IRQHandler
   .word 0
   .word TIM14_IRQHandler
   .word TIM15_IRQHandler
   .word TIM16_IRQHandler
   .word TIM17_IRQHandler
   .word I2C1_IRQHandler
   .word I2C2_IRQHandler
   .word SPI1_IRQHandler
   .word SPI2_IRQHandler
   .word USART1_IRQHandler
   .word USART2_IRQHandler
   .word 0
   .word CEC_IRQHandler
   .word 0
 /*******************************************************************************
+*
 * Provide weak aliases for each Exception handler to the Default_Handler.
 * As they are weak aliases, any function with the same name will override
 * this definition.
+*
 *******************************************************************************/
   .weak NMI_Handler
   .thumb_set NMI_Handler,Default_Handler
   .weak HardFault_Handler
   .thumb_set HardFault_Handler,Default_Handler
   .weak SVC_Handler
   .thumb_set SVC_Handler,Default_Handler
   .weak PendSV_Handler
   .thumb_set PendSV_Handler,Default_Handler
   .weak SysTick_Handler
   .thumb_set SysTick_Handler,Default_Handler
   .weak WWDG_IRQHandler
   .thumb_set WWDG_IRQHandler,Default_Handler
   .weak PVD_IRQHandler
   .thumb_set PVD_IRQHandler,Default_Handler
   .weak RTC_IRQHandler
   .thumb_set RTC_IRQHandler,Default_Handler
   .weak FLASH_IRQHandler
   .thumb_set FLASH_IRQHandler,Default_Handler
   .weak RCC_IRQHandler
   .thumb_set RCC_IRQHandler,Default_Handler
   .weak EXTI0_1_IRQHandler
   .thumb_set EXTI0_1_IRQHandler,Default_Handler
   .weak EXTI2_3_IRQHandler
   .thumb_set EXTI2_3_IRQHandler,Default_Handler
   .weak EXTI4_15_IRQHandler
   .thumb_set EXTI4_15_IRQHandler,Default_Handler
   .weak TS_IRQHandler
   .thumb_set TS_IRQHandler,Default_Handler
   .weak DMA1_Channel1_IRQHandler
   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
   .weak DMA1_Channel2_3_IRQHandler
   .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
   .weak DMA1_Channel4_5_IRQHandler
   .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
   .weak ADC1_COMP_IRQHandler
   .thumb_set ADC1_COMP_IRQHandler,Default_Handler
   .weak TIM1_BRK_UP_TRG_COM_IRQHandler
   .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
   .weak TIM1_CC_IRQHandler
   .thumb_set TIM1_CC_IRQHandler,Default_Handler
   .weak TIM2_IRQHandler
   .thumb_set TIM2_IRQHandler,Default_Handler
   .weak TIM3_IRQHandler
   .thumb_set TIM3_IRQHandler,Default_Handler
   .weak TIM6_DAC_IRQHandler
   .thumb_set TIM6_DAC_IRQHandler,Default_Handler
   .weak TIM14_IRQHandler
   .thumb_set TIM14_IRQHandler,Default_Handler
   .weak TIM15_IRQHandler
   .thumb_set TIM15_IRQHandler,Default_Handler
   .weak TIM16_IRQHandler
   .thumb_set TIM16_IRQHandler,Default_Handler
   .weak TIM17_IRQHandler
   .thumb_set TIM17_IRQHandler,Default_Handler
   .weak I2C1_IRQHandler
   .thumb_set I2C1_IRQHandler,Default_Handler
   .weak I2C2_IRQHandler
   .thumb_set I2C2_IRQHandler,Default_Handler
   .weak SPI1_IRQHandler
   .thumb_set SPI1_IRQHandler,Default_Handler
   .weak SPI2_IRQHandler
   .thumb_set SPI2_IRQHandler,Default_Handler
   .weak USART1_IRQHandler
   .thumb_set USART1_IRQHandler,Default_Handler
   .weak USART2_IRQHandler
   .thumb_set USART2_IRQHandler,Default_Handler
   .weak CEC_IRQHandler
   .thumb_set CEC_IRQHandler,Default_Handler
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f072.s

➞

Show inline comments

@@ new file 100644 @@
 /**
   ******************************************************************************
   * @file      startup_stm32f072.s
   * @author    MCD Application Team
   * @version   V1.4.0
   * @date      24-July-2014
   * @brief     STM32F072 Devices vector table for Atollic toolchain.
   *            This module performs:
   *                - Set the initial SP
   *                - Set the initial PC == Reset_Handler,
   *                - Set the vector table entries with the exceptions ISR address
   *                - Configure the system clock
   *                - Branches to main in the C library (which eventually
   *                  calls main()).
   *            After Reset the Cortex-M0 processor is in Thread mode,
   *            priority is Privileged, and the Stack is set to Main.
   ******************************************************************************
   * @attention
+  *
   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
   * You may not use this file except in compliance with the License.
   * You may obtain a copy of the License at:
+  *
   *        http://www.st.com/software_license_agreement_liberty_v2
+  *
   * Unless required by applicable law or agreed to in writing, software
   * distributed under the License is distributed on an "AS IS" BASIS,
   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
   * See the License for the specific language governing permissions and
   * limitations under the License.
+  *
   ******************************************************************************
   */
   .syntax unified
   .cpu cortex-m0
   .fpu softvfp
   .thumb
 .global g_pfnVectors
 .global Default_Handler
 /* start address for the initialization values of the .data section.
 defined in linker script */
 .word _sidata
 /* start address for the .data section. defined in linker script */
 .word _sdata
 /* end address for the .data section. defined in linker script */
 .word _edata
 /* start address for the .bss section. defined in linker script */
 .word _sbss
 /* end address for the .bss section. defined in linker script */
 .word _ebss
   .section .text.Reset_Handler
   .weak Reset_Handler
   .type Reset_Handler, %function
 Reset_Handler:
   ldr   r0, =_estack
   mov   sp, r0          /* set stack pointer */
 /*Check if boot space corresponds to test memory*/
     LDR R0,=0x00000004
     LDR R1, [R0]
     LSRS R1, R1, #24
     LDR R2,=0x1F
     CMP R1, R2
     BNE ApplicationStart
  /*SYSCFG clock enable*/
     LDR R0,=0x40021018
     LDR R1,=0x00000001
     STR R1, [R0]
 /*Set CFGR1 register with flash memory remap at address 0*/
     LDR R0,=0x40010000
     LDR R1,=0x00000000
     STR R1, [R0]
 ApplicationStart:
 /* Copy the data segment initializers from flash to SRAM */
   movs r1, #0
   b LoopCopyDataInit
 CopyDataInit:
   ldr r3, =_sidata
   ldr r3, [r3, r1]
   str r3, [r0, r1]
   adds r1, r1, #4
 LoopCopyDataInit:
   ldr r0, =_sdata
   ldr r3, =_edata
   adds r2, r0, r1
   cmp r2, r3
   bcc CopyDataInit
   ldr r2, =_sbss
   b LoopFillZerobss
 /* Zero fill the bss segment. */
 FillZerobss:
   movs r3, #0
   str  r3, [r2]
   adds r2, r2, #4
 LoopFillZerobss:
   ldr r3, = _ebss
   cmp r2, r3
   bcc FillZerobss
 /* Call the clock system intitialization function.*/
     bl  SystemInit
 /* Call static constructors */
     bl __libc_init_array
 /* Call the application's entry point.*/
   bl main
 LoopForever:
     b LoopForever
 .size Reset_Handler, .-Reset_Handler
 /**
  * @brief  This is the code that gets called when the processor receives an
  *         unexpected interrupt.  This simply enters an infinite loop, preserving
  *         the system state for examination by a debugger.
+ *
  * @param  None
  * @retval : None
 */
     .section .text.Default_Handler,"ax",%progbits
 Default_Handler:
 Infinite_Loop:
   b Infinite_Loop
   .size Default_Handler, .-Default_Handler
 /******************************************************************************
+*
 * The minimal vector table for a Cortex M0.  Note that the proper constructs
 * must be placed on this to ensure that it ends up at physical address
 * 0x0000.0000.
+*
 ******************************************************************************/
    .section .isr_vector,"a",%progbits
   .type g_pfnVectors, %object
   .size g_pfnVectors, .-g_pfnVectors
 g_pfnVectors:
   .word _estack
   .word Reset_Handler
   .word NMI_Handler
   .word HardFault_Handler
   .word 0
   .word 0
   .word 0
   .word 0
   .word 0
   .word 0
   .word 0
   .word SVC_Handler
   .word 0
   .word 0
   .word PendSV_Handler
   .word SysTick_Handler
   .word WWDG_IRQHandler
   .word PVD_VDDIO2_IRQHandler
   .word RTC_IRQHandler
   .word FLASH_IRQHandler
   .word RCC_CRS_IRQHandler
   .word EXTI0_1_IRQHandler
   .word EXTI2_3_IRQHandler
   .word EXTI4_15_IRQHandler
   .word TSC_IRQHandler
   .word DMA1_Channel1_IRQHandler
   .word DMA1_Channel2_3_IRQHandler
   .word DMA1_Channel4_5_6_7_IRQHandler
   .word ADC1_COMP_IRQHandler
   .word TIM1_BRK_UP_TRG_COM_IRQHandler
   .word TIM1_CC_IRQHandler
   .word TIM2_IRQHandler
   .word TIM3_IRQHandler
   .word TIM6_DAC_IRQHandler
   .word TIM7_IRQHandler
   .word TIM14_IRQHandler
   .word TIM15_IRQHandler
   .word TIM16_IRQHandler
   .word TIM17_IRQHandler
   .word I2C1_IRQHandler
   .word I2C2_IRQHandler
   .word SPI1_IRQHandler
   .word SPI2_IRQHandler
   .word USART1_IRQHandler
   .word USART2_IRQHandler
   .word USART3_4_IRQHandler
   .word CEC_CAN_IRQHandler
   .word USB_IRQHandler
 /*******************************************************************************
+*
 * Provide weak aliases for each Exception handler to the Default_Handler.
 * As they are weak aliases, any function with the same name will override
 * this definition.
+*
 *******************************************************************************/
   .weak NMI_Handler
   .thumb_set NMI_Handler,Default_Handler
   .weak HardFault_Handler
   .thumb_set HardFault_Handler,Default_Handler
   .weak SVC_Handler
   .thumb_set SVC_Handler,Default_Handler
   .weak PendSV_Handler
   .thumb_set PendSV_Handler,Default_Handler
   .weak SysTick_Handler
   .thumb_set SysTick_Handler,Default_Handler
   .weak WWDG_IRQHandler
   .thumb_set WWDG_IRQHandler,Default_Handler
   .weak PVD_VDDIO2_IRQHandler
   .thumb_set PVD_VDDIO2_IRQHandler,Default_Handler
   .weak RTC_IRQHandler
   .thumb_set RTC_IRQHandler,Default_Handler
   .weak FLASH_IRQHandler
   .thumb_set FLASH_IRQHandler,Default_Handler
   .weak RCC_CRS_IRQHandler
   .thumb_set RCC_CRS_IRQHandler,Default_Handler
   .weak EXTI0_1_IRQHandler
   .thumb_set EXTI0_1_IRQHandler,Default_Handler
   .weak EXTI2_3_IRQHandler
   .thumb_set EXTI2_3_IRQHandler,Default_Handler
   .weak EXTI4_15_IRQHandler
   .thumb_set EXTI4_15_IRQHandler,Default_Handler
   .weak TSC_IRQHandler
   .thumb_set TSC_IRQHandler,Default_Handler
   .weak DMA1_Channel1_IRQHandler
   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
   .weak DMA1_Channel2_3_IRQHandler
   .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
   .weak DMA1_Channel4_5_6_7_IRQHandler
   .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
   .weak ADC1_COMP_IRQHandler
   .thumb_set ADC1_COMP_IRQHandler,Default_Handler
   .weak TIM1_BRK_UP_TRG_COM_IRQHandler
   .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
   .weak TIM1_CC_IRQHandler
   .thumb_set TIM1_CC_IRQHandler,Default_Handler
   .weak TIM2_IRQHandler
   .thumb_set TIM2_IRQHandler,Default_Handler
   .weak TIM3_IRQHandler
   .thumb_set TIM3_IRQHandler,Default_Handler
   .weak TIM6_DAC_IRQHandler
   .thumb_set TIM6_DAC_IRQHandler,Default_Handler
   .weak TIM7_IRQHandler
   .thumb_set TIM7_IRQHandler,Default_Handler
   .weak TIM14_IRQHandler
   .thumb_set TIM14_IRQHandler,Default_Handler
   .weak TIM15_IRQHandler
   .thumb_set TIM15_IRQHandler,Default_Handler
   .weak TIM16_IRQHandler
   .thumb_set TIM16_IRQHandler,Default_Handler
   .weak TIM17_IRQHandler
   .thumb_set TIM17_IRQHandler,Default_Handler
   .weak I2C1_IRQHandler
   .thumb_set I2C1_IRQHandler,Default_Handler
   .weak I2C2_IRQHandler
   .thumb_set I2C2_IRQHandler,Default_Handler
   .weak SPI1_IRQHandler
   .thumb_set SPI1_IRQHandler,Default_Handler
   .weak SPI2_IRQHandler
   .thumb_set SPI2_IRQHandler,Default_Handler
   .weak USART1_IRQHandler
   .thumb_set USART1_IRQHandler,Default_Handler
   .weak USART2_IRQHandler
   .thumb_set USART2_IRQHandler,Default_Handler
   .weak USART3_4_IRQHandler
   .thumb_set USART3_4_IRQHandler,Default_Handler
   .weak CEC_CAN_IRQHandler
   .thumb_set CEC_CAN_IRQHandler,Default_Handler
   .weak USB_IRQHandler
   .thumb_set USB_IRQHandler,Default_Handler
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f091.s

➞

Show inline comments

@@ new file 100644 @@
 /**
   ******************************************************************************
   * @file      startup_stm32f091.s
   * @author    MCD Application Team
   * @version   V1.4.0
   * @date      24-July-2014
   * @brief     STM32F091 Devices vector table for Atollic toolchain.
   *            This module performs:
   *                - Set the initial SP
   *                - Set the initial PC == Reset_Handler,
   *                - Set the vector table entries with the exceptions ISR address
   *                - Configure the system clock
   *                - Branches to main in the C library (which eventually
   *                  calls main()).
   *            After Reset the Cortex-M0 processor is in Thread mode,
   *            priority is Privileged, and the Stack is set to Main.
   ******************************************************************************
   * @attention
+  *
   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
   * You may not use this file except in compliance with the License.
   * You may obtain a copy of the License at:
+  *
   *        http://www.st.com/software_license_agreement_liberty_v2
+  *
   * Unless required by applicable law or agreed to in writing, software
   * distributed under the License is distributed on an "AS IS" BASIS,
   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
   * See the License for the specific language governing permissions and
   * limitations under the License.
+  *
   ******************************************************************************
   */
   .syntax unified
   .cpu cortex-m0
   .fpu softvfp
   .thumb
 .global g_pfnVectors
 .global Default_Handler
 /* start address for the initialization values of the .data section.
 defined in linker script */
 .word _sidata
 /* start address for the .data section. defined in linker script */
 .word _sdata
 /* end address for the .data section. defined in linker script */
 .word _edata
 /* start address for the .bss section. defined in linker script */
 .word _sbss
 /* end address for the .bss section. defined in linker script */
 .word _ebss
   .section .text.Reset_Handler
   .weak Reset_Handler
   .type Reset_Handler, %function
 Reset_Handler:
   ldr   r0, =_estack
   mov   sp, r0          /* set stack pointer */
 /*Check if boot space corresponds to test memory*/
     LDR R0,=0x00000004
     LDR R1, [R0]
     LSRS R1, R1, #24
     LDR R2,=0x1F
     CMP R1, R2
     BNE ApplicationStart
  /*SYSCFG clock enable*/
     LDR R0,=0x40021018
     LDR R1,=0x00000001
     STR R1, [R0]
 /*Set CFGR1 register with flash memory remap at address 0*/
     LDR R0,=0x40010000
     LDR R1,=0x00000000
     STR R1, [R0]
 ApplicationStart:
 /* Copy the data segment initializers from flash to SRAM */
   movs r1, #0
   b LoopCopyDataInit
 CopyDataInit:
   ldr r3, =_sidata
   ldr r3, [r3, r1]
   str r3, [r0, r1]
   adds r1, r1, #4
 LoopCopyDataInit:
   ldr r0, =_sdata
   ldr r3, =_edata
   adds r2, r0, r1
   cmp r2, r3
   bcc CopyDataInit
   ldr r2, =_sbss
   b LoopFillZerobss
 /* Zero fill the bss segment. */
 FillZerobss:
   movs r3, #0
   str  r3, [r2]
   adds r2, r2, #4
 LoopFillZerobss:
   ldr r3, = _ebss
   cmp r2, r3
   bcc FillZerobss
 /* Call the clock system intitialization function.*/
     bl  SystemInit
 /* Call static constructors */
     bl __libc_init_array
 /* Call the application's entry point.*/
   bl main
 LoopForever:
     b LoopForever
 .size Reset_Handler, .-Reset_Handler
 /**
  * @brief  This is the code that gets called when the processor receives an
  *         unexpected interrupt.  This simply enters an infinite loop, preserving
  *         the system state for examination by a debugger.
+ *
  * @param  None
  * @retval : None
 */
     .section .text.Default_Handler,"ax",%progbits
 Default_Handler:
 Infinite_Loop:
   b Infinite_Loop
   .size Default_Handler, .-Default_Handler
 /******************************************************************************
+*
 * The minimal vector table for a Cortex M0.  Note that the proper constructs
 * must be placed on this to ensure that it ends up at physical address
 * 0x0000.0000.
+*
 ******************************************************************************/
    .section .isr_vector,"a",%progbits
   .type g_pfnVectors, %object
   .size g_pfnVectors, .-g_pfnVectors
 g_pfnVectors:
   .word _estack
   .word Reset_Handler
   .word NMI_Handler
   .word HardFault_Handler
   .word 0
   .word 0
   .word 0
   .word 0
   .word 0
   .word 0
   .word 0
   .word SVC_Handler
   .word 0
   .word 0
   .word PendSV_Handler
   .word SysTick_Handler
   .word WWDG_IRQHandler
   .word PVD_VDDIO2_IRQHandler
   .word RTC_IRQHandler
   .word FLASH_IRQHandler
   .word RCC_CRS_IRQHandler
   .word EXTI0_1_IRQHandler
   .word EXTI2_3_IRQHandler
   .word EXTI4_15_IRQHandler
   .word TSC_IRQHandler
   .word DMA1_Ch1_IRQHandler
   .word DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
   .word DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
   .word ADC1_COMP_IRQHandler
   .word TIM1_BRK_UP_TRG_COM_IRQHandler
   .word TIM1_CC_IRQHandler
   .word TIM2_IRQHandler
   .word TIM3_IRQHandler
   .word TIM6_DAC_IRQHandler
   .word TIM7_IRQHandler
   .word TIM14_IRQHandler
   .word TIM15_IRQHandler
   .word TIM16_IRQHandler
   .word TIM17_IRQHandler
   .word I2C1_IRQHandler
   .word I2C2_IRQHandler
   .word SPI1_IRQHandler
   .word SPI2_IRQHandler
   .word USART1_IRQHandler
   .word USART2_IRQHandler
   .word USART3_8_IRQHandler
   .word CEC_CAN_IRQHandler
 /*******************************************************************************
+*
 * Provide weak aliases for each Exception handler to the Default_Handler.
 * As they are weak aliases, any function with the same name will override
 * this definition.
+*
 *******************************************************************************/
   .weak NMI_Handler
   .thumb_set NMI_Handler,Default_Handler
   .weak HardFault_Handler
   .thumb_set HardFault_Handler,Default_Handler
   .weak SVC_Handler
   .thumb_set SVC_Handler,Default_Handler
   .weak PendSV_Handler
   .thumb_set PendSV_Handler,Default_Handler
   .weak SysTick_Handler
   .thumb_set SysTick_Handler,Default_Handler
   .weak WWDG_IRQHandler
   .thumb_set WWDG_IRQHandler,Default_Handler
   .weak PVD_VDDIO2_IRQHandler
   .thumb_set PVD_VDDIO2_IRQHandler,Default_Handler
   .weak RTC_IRQHandler
   .thumb_set RTC_IRQHandler,Default_Handler
   .weak FLASH_IRQHandler
   .thumb_set FLASH_IRQHandler,Default_Handler
   .weak RCC_CRS_IRQHandler
   .thumb_set RCC_CRS_IRQHandler,Default_Handler
   .weak EXTI0_1_IRQHandler
   .thumb_set EXTI0_1_IRQHandler,Default_Handler
   .weak EXTI2_3_IRQHandler
   .thumb_set EXTI2_3_IRQHandler,Default_Handler
   .weak EXTI4_15_IRQHandler
   .thumb_set EXTI4_15_IRQHandler,Default_Handler
   .weak TSC_IRQHandler
   .thumb_set TSC_IRQHandler,Default_Handler
   .weak DMA1_Ch1_IRQHandler
   .thumb_set DMA1_Ch1_IRQHandler,Default_Handler
   .weak DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
   .thumb_set DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler,Default_Handler
   .weak DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
   .thumb_set DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler,Default_Handler
   .weak ADC1_COMP_IRQHandler
   .thumb_set ADC1_COMP_IRQHandler,Default_Handler
   .weak TIM1_BRK_UP_TRG_COM_IRQHandler
   .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
   .weak TIM1_CC_IRQHandler
   .thumb_set TIM1_CC_IRQHandler,Default_Handler
   .weak TIM2_IRQHandler
   .thumb_set TIM2_IRQHandler,Default_Handler
   .weak TIM3_IRQHandler
   .thumb_set TIM3_IRQHandler,Default_Handler
   .weak TIM6_DAC_IRQHandler
   .thumb_set TIM6_DAC_IRQHandler,Default_Handler
   .weak TIM7_IRQHandler
   .thumb_set TIM7_IRQHandler,Default_Handler
   .weak TIM14_IRQHandler
   .thumb_set TIM14_IRQHandler,Default_Handler
   .weak TIM15_IRQHandler
   .thumb_set TIM15_IRQHandler,Default_Handler
   .weak TIM16_IRQHandler
   .thumb_set TIM16_IRQHandler,Default_Handler
   .weak TIM17_IRQHandler
   .thumb_set TIM17_IRQHandler,Default_Handler
   .weak I2C1_IRQHandler
   .thumb_set I2C1_IRQHandler,Default_Handler
   .weak I2C2_IRQHandler
   .thumb_set I2C2_IRQHandler,Default_Handler
   .weak SPI1_IRQHandler
   .thumb_set SPI1_IRQHandler,Default_Handler
   .weak SPI2_IRQHandler
   .thumb_set SPI2_IRQHandler,Default_Handler
   .weak USART1_IRQHandler
   .thumb_set USART1_IRQHandler,Default_Handler
   .weak USART2_IRQHandler
   .thumb_set USART2_IRQHandler,Default_Handler
   .weak USART3_8_IRQHandler
   .thumb_set USART3_8_IRQHandler,Default_Handler
   .weak CEC_CAN_IRQHandler
   .thumb_set CEC_CAN_IRQHandler,Default_Handler
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f0xx.s

➞

Show inline comments

@@ new file 100644 @@
 /**
   ******************************************************************************
   * @file      startup_stm32f0xx.s
   * @author    MCD Application Team
   * @version   V1.4.0
   * @date      24-July-2014
   * @brief     STM32F0xx Devices vector table for Atollic toolchain.
   *            This module performs:
   *                - Set the initial SP
   *                - Set the initial PC == Reset_Handler,
   *                - Set the vector table entries with the exceptions ISR address
   *                - Configure the system clock
   *                - Branches to main in the C library (which eventually
   *                  calls main()).
   *            After Reset the Cortex-M0 processor is in Thread mode,
   *            priority is Privileged, and the Stack is set to Main.
   ******************************************************************************
   * @attention
+  *
   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
   * You may not use this file except in compliance with the License.
   * You may obtain a copy of the License at:
+  *
   *        http://www.st.com/software_license_agreement_liberty_v2
+  *
   * Unless required by applicable law or agreed to in writing, software
   * distributed under the License is distributed on an "AS IS" BASIS,
   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
   * See the License for the specific language governing permissions and
   * limitations under the License.
+  *
   ******************************************************************************
   */
   .syntax unified
   .cpu cortex-m0
   .fpu softvfp
   .thumb
 .global g_pfnVectors
 .global Default_Handler
 /* start address for the initialization values of the .data section.
 defined in linker script */
 .word _sidata
 /* start address for the .data section. defined in linker script */
 .word _sdata
 /* end address for the .data section. defined in linker script */
 .word _edata
 /* start address for the .bss section. defined in linker script */
 .word _sbss
 /* end address for the .bss section. defined in linker script */
 .word _ebss
   .section .text.Reset_Handler
   .weak Reset_Handler
   .type Reset_Handler, %function
 Reset_Handler:
   ldr   r0, =_estack
   mov   sp, r0          /* set stack pointer */
 /*Check if boot space corresponds to test memory*/
     LDR R0,=0x00000004
     LDR R1, [R0]
     LSRS R1, R1, #24
     LDR R2,=0x1F
     CMP R1, R2
     BNE ApplicationStart
  /*SYSCFG clock enable*/
     LDR R0,=0x40021018
     LDR R1,=0x00000001
     STR R1, [R0]
 /*Set CFGR1 register with flash memory remap at address 0*/
     LDR R0,=0x40010000
     LDR R1,=0x00000000
     STR R1, [R0]
 ApplicationStart:
 /* Copy the data segment initializers from flash to SRAM */
   movs r1, #0
   b LoopCopyDataInit
 CopyDataInit:
   ldr r3, =_sidata
   ldr r3, [r3, r1]
   str r3, [r0, r1]
   adds r1, r1, #4
 LoopCopyDataInit:
   ldr r0, =_sdata
   ldr r3, =_edata
   adds r2, r0, r1
   cmp r2, r3
   bcc CopyDataInit
   ldr r2, =_sbss
   b LoopFillZerobss
 /* Zero fill the bss segment. */
 FillZerobss:
   movs r3, #0
   str  r3, [r2]
   adds r2, r2, #4
 LoopFillZerobss:
   ldr r3, = _ebss
   cmp r2, r3
   bcc FillZerobss
 /* Call the clock system intitialization function.*/
     bl  SystemInit
 /* Call static constructors */
     bl __libc_init_array
 /* Call the application's entry point.*/
   bl main
 LoopForever:
     b LoopForever
 .size Reset_Handler, .-Reset_Handler
 /**
  * @brief  This is the code that gets called when the processor receives an
  *         unexpected interrupt.  This simply enters an infinite loop, preserving
  *         the system state for examination by a debugger.
+ *
  * @param  None
  * @retval : None
 */
     .section .text.Default_Handler,"ax",%progbits
 Default_Handler:
 Infinite_Loop:
   b Infinite_Loop
   .size Default_Handler, .-Default_Handler
 /******************************************************************************
+*
 * The minimal vector table for a Cortex M0.  Note that the proper constructs
 * must be placed on this to ensure that it ends up at physical address
 * 0x0000.0000.
+*
 ******************************************************************************/
    .section .isr_vector,"a",%progbits
   .type g_pfnVectors, %object
   .size g_pfnVectors, .-g_pfnVectors
 g_pfnVectors:
   .word _estack
   .word Reset_Handler
   .word NMI_Handler
   .word HardFault_Handler
   .word 0
   .word 0
   .word 0
   .word 0
   .word 0
   .word 0
   .word 0
   .word SVC_Handler
   .word 0
   .word 0
   .word PendSV_Handler
   .word SysTick_Handler
   .word WWDG_IRQHandler
   .word PVD_IRQHandler
   .word RTC_IRQHandler
   .word FLASH_IRQHandler
   .word RCC_IRQHandler
   .word EXTI0_1_IRQHandler
   .word EXTI2_3_IRQHandler
   .word EXTI4_15_IRQHandler
   .word TS_IRQHandler
   .word DMA1_Channel1_IRQHandler
   .word DMA1_Channel2_3_IRQHandler
   .word DMA1_Channel4_5_IRQHandler
   .word ADC1_COMP_IRQHandler
   .word TIM1_BRK_UP_TRG_COM_IRQHandler
   .word TIM1_CC_IRQHandler
   .word TIM2_IRQHandler
   .word TIM3_IRQHandler
   .word TIM6_DAC_IRQHandler
   .word 0
   .word TIM14_IRQHandler
   .word TIM15_IRQHandler
   .word TIM16_IRQHandler
   .word TIM17_IRQHandler
   .word I2C1_IRQHandler
   .word I2C2_IRQHandler
   .word SPI1_IRQHandler
   .word SPI2_IRQHandler
   .word USART1_IRQHandler
   .word USART2_IRQHandler
   .word 0
   .word CEC_IRQHandler
   .word 0
 /*******************************************************************************
+*
 * Provide weak aliases for each Exception handler to the Default_Handler.
 * As they are weak aliases, any function with the same name will override
 * this definition.
+*
 *******************************************************************************/
   .weak NMI_Handler
   .thumb_set NMI_Handler,Default_Handler
   .weak HardFault_Handler
   .thumb_set HardFault_Handler,Default_Handler
   .weak SVC_Handler
   .thumb_set SVC_Handler,Default_Handler
   .weak PendSV_Handler
   .thumb_set PendSV_Handler,Default_Handler
   .weak SysTick_Handler
   .thumb_set SysTick_Handler,Default_Handler
   .weak WWDG_IRQHandler
   .thumb_set WWDG_IRQHandler,Default_Handler
   .weak PVD_IRQHandler
   .thumb_set PVD_IRQHandler,Default_Handler
   .weak RTC_IRQHandler
   .thumb_set RTC_IRQHandler,Default_Handler
   .weak FLASH_IRQHandler
   .thumb_set FLASH_IRQHandler,Default_Handler
   .weak RCC_IRQHandler
   .thumb_set RCC_IRQHandler,Default_Handler
   .weak EXTI0_1_IRQHandler
   .thumb_set EXTI0_1_IRQHandler,Default_Handler
   .weak EXTI2_3_IRQHandler
   .thumb_set EXTI2_3_IRQHandler,Default_Handler
   .weak EXTI4_15_IRQHandler
   .thumb_set EXTI4_15_IRQHandler,Default_Handler
   .weak TS_IRQHandler
   .thumb_set TS_IRQHandler,Default_Handler
   .weak DMA1_Channel1_IRQHandler
   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
   .weak DMA1_Channel2_3_IRQHandler
   .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
   .weak DMA1_Channel4_5_IRQHandler
   .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
   .weak ADC1_COMP_IRQHandler
   .thumb_set ADC1_COMP_IRQHandler,Default_Handler
   .weak TIM1_BRK_UP_TRG_COM_IRQHandler
   .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
   .weak TIM1_CC_IRQHandler
   .thumb_set TIM1_CC_IRQHandler,Default_Handler
   .weak TIM2_IRQHandler
   .thumb_set TIM2_IRQHandler,Default_Handler
   .weak TIM3_IRQHandler
   .thumb_set TIM3_IRQHandler,Default_Handler
   .weak TIM6_DAC_IRQHandler
   .thumb_set TIM6_DAC_IRQHandler,Default_Handler
   .weak TIM14_IRQHandler
   .thumb_set TIM14_IRQHandler,Default_Handler
   .weak TIM15_IRQHandler
   .thumb_set TIM15_IRQHandler,Default_Handler
   .weak TIM16_IRQHandler
   .thumb_set TIM16_IRQHandler,Default_Handler
   .weak TIM17_IRQHandler
   .thumb_set TIM17_IRQHandler,Default_Handler
   .weak I2C1_IRQHandler
   .thumb_set I2C1_IRQHandler,Default_Handler
   .weak I2C2_IRQHandler
   .thumb_set I2C2_IRQHandler,Default_Handler
   .weak SPI1_IRQHandler
   .thumb_set SPI1_IRQHandler,Default_Handler
   .weak SPI2_IRQHandler
   .thumb_set SPI2_IRQHandler,Default_Handler
   .weak USART1_IRQHandler
   .thumb_set USART1_IRQHandler,Default_Handler
   .weak USART2_IRQHandler
   .thumb_set USART2_IRQHandler,Default_Handler
   .weak CEC_IRQHandler
   .thumb_set CEC_IRQHandler,Default_Handler
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f0xx_ld.s

➞

Show inline comments

@@ new file 100644 @@
 /**
   ******************************************************************************
   * @file      startup_stm32f0xx_ld.s
   * @author    MCD Application Team
   * @version   V1.4.0
   * @date      24-July-2014
   * @brief     STM32F031 devices vector table for Atollic toolchain.
   *            This module performs:
   *                - Set the initial SP
   *                - Set the initial PC == Reset_Handler,
   *                - Set the vector table entries with the exceptions ISR address
   *                - Configure the system clock
   *                - Branches to main in the C library (which eventually
   *                  calls main()).
   *            After Reset the Cortex-M0 processor is in Thread mode,
   *            priority is Privileged, and the Stack is set to Main.
   ******************************************************************************
   * @attention
+  *
   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
   * You may not use this file except in compliance with the License.
   * You may obtain a copy of the License at:
+  *
   *        http://www.st.com/software_license_agreement_liberty_v2
+  *
   * Unless required by applicable law or agreed to in writing, software
   * distributed under the License is distributed on an "AS IS" BASIS,
   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
   * See the License for the specific language governing permissions and
   * limitations under the License.
+  *
   ******************************************************************************
   */
   .syntax unified
   .cpu cortex-m0
   .fpu softvfp
   .thumb
 .global g_pfnVectors
 .global Default_Handler
 /* start address for the initialization values of the .data section.
 defined in linker script */
 .word _sidata
 /* start address for the .data section. defined in linker script */
 .word _sdata
 /* end address for the .data section. defined in linker script */
 .word _edata
 /* start address for the .bss section. defined in linker script */
 .word _sbss
 /* end address for the .bss section. defined in linker script */
 .word _ebss
   .section .text.Reset_Handler
   .weak Reset_Handler
   .type Reset_Handler, %function
 Reset_Handler:
   ldr   r0, =_estack
   mov   sp, r0          /* set stack pointer */
 /*Check if boot space corresponds to test memory*/
     LDR R0,=0x00000004
     LDR R1, [R0]
     LSRS R1, R1, #24
     LDR R2,=0x1F
     CMP R1, R2
     BNE ApplicationStart
  /*SYSCFG clock enable*/
     LDR R0,=0x40021018
     LDR R1,=0x00000001
     STR R1, [R0]
 /*Set CFGR1 register with flash memory remap at address 0*/
     LDR R0,=0x40010000
     LDR R1,=0x00000000
     STR R1, [R0]
 ApplicationStart:
 /* Copy the data segment initializers from flash to SRAM */
   movs r1, #0
   b LoopCopyDataInit
 CopyDataInit:
   ldr r3, =_sidata
   ldr r3, [r3, r1]
   str r3, [r0, r1]
   adds r1, r1, #4
 LoopCopyDataInit:
   ldr r0, =_sdata
   ldr r3, =_edata
   adds r2, r0, r1
   cmp r2, r3
   bcc CopyDataInit
   ldr r2, =_sbss
   b LoopFillZerobss
 /* Zero fill the bss segment. */
 FillZerobss:
   movs r3, #0
   str  r3, [r2]
   adds r2, r2, #4
 LoopFillZerobss:
   ldr r3, = _ebss
   cmp r2, r3
   bcc FillZerobss
 /* Call the clock system intitialization function.*/
     bl  SystemInit
 /* Call static constructors */
     bl __libc_init_array
 /* Call the application's entry point.*/
   bl main
 LoopForever:
     b LoopForever
 .size Reset_Handler, .-Reset_Handler
 /**
  * @brief  This is the code that gets called when the processor receives an
  *         unexpected interrupt.  This simply enters an infinite loop, preserving
  *         the system state for examination by a debugger.
+ *
  * @param  None
  * @retval : None
 */
     .section .text.Default_Handler,"ax",%progbits
 Default_Handler:
 Infinite_Loop:
   b Infinite_Loop
   .size Default_Handler, .-Default_Handler
 /******************************************************************************
+*
 * The minimal vector table for a Cortex M0.  Note that the proper constructs
 * must be placed on this to ensure that it ends up at physical address
 * 0x0000.0000.
+*
 ******************************************************************************/
    .section .isr_vector,"a",%progbits
   .type g_pfnVectors, %object
   .size g_pfnVectors, .-g_pfnVectors
 g_pfnVectors:
   .word _estack
   .word Reset_Handler
   .word NMI_Handler
   .word HardFault_Handler
   .word 0
   .word 0
   .word 0
   .word 0
   .word 0
   .word 0
   .word 0
   .word SVC_Handler
   .word 0
   .word 0
   .word PendSV_Handler
   .word SysTick_Handler
   .word WWDG_IRQHandler
   .word PVD_IRQHandler
   .word RTC_IRQHandler
   .word FLASH_IRQHandler
   .word RCC_IRQHandler
   .word EXTI0_1_IRQHandler
   .word EXTI2_3_IRQHandler
   .word EXTI4_15_IRQHandler
   .word 0
   .word DMA1_Channel1_IRQHandler
   .word DMA1_Channel2_3_IRQHandler
   .word DMA1_Channel4_5_IRQHandler
   .word ADC1_IRQHandler
   .word TIM1_BRK_UP_TRG_COM_IRQHandler
   .word TIM1_CC_IRQHandler
   .word TIM2_IRQHandler
   .word TIM3_IRQHandler
   .word 0
   .word 0
   .word TIM14_IRQHandler
   .word 0
   .word TIM16_IRQHandler
   .word TIM17_IRQHandler
   .word I2C1_IRQHandler
   .word 0
   .word SPI1_IRQHandler
   .word 0
   .word USART1_IRQHandler
   .word 0
   .word 0
   .word 0
   .word 0
 /*******************************************************************************
+*
 * Provide weak aliases for each Exception handler to the Default_Handler.
 * As they are weak aliases, any function with the same name will override
 * this definition.
+*
 *******************************************************************************/
   .weak NMI_Handler
   .thumb_set NMI_Handler,Default_Handler
   .weak HardFault_Handler
   .thumb_set HardFault_Handler,Default_Handler
   .weak SVC_Handler
   .thumb_set SVC_Handler,Default_Handler
   .weak PendSV_Handler
   .thumb_set PendSV_Handler,Default_Handler
   .weak SysTick_Handler
   .thumb_set SysTick_Handler,Default_Handler
   .weak WWDG_IRQHandler
   .thumb_set WWDG_IRQHandler,Default_Handler
   .weak PVD_IRQHandler
   .thumb_set PVD_IRQHandler,Default_Handler
   .weak RTC_IRQHandler
   .thumb_set RTC_IRQHandler,Default_Handler
   .weak FLASH_IRQHandler
   .thumb_set FLASH_IRQHandler,Default_Handler
   .weak RCC_IRQHandler
   .thumb_set RCC_IRQHandler,Default_Handler
   .weak EXTI0_1_IRQHandler
   .thumb_set EXTI0_1_IRQHandler,Default_Handler
   .weak EXTI2_3_IRQHandler
   .thumb_set EXTI2_3_IRQHandler,Default_Handler
   .weak EXTI4_15_IRQHandler
   .thumb_set EXTI4_15_IRQHandler,Default_Handler
   .weak DMA1_Channel1_IRQHandler
   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
   .weak DMA1_Channel2_3_IRQHandler
   .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
   .weak DMA1_Channel4_5_IRQHandler
   .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
   .weak ADC1_IRQHandler
   .thumb_set ADC1_IRQHandler,Default_Handler
   .weak TIM1_BRK_UP_TRG_COM_IRQHandler
   .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
   .weak TIM1_CC_IRQHandler
   .thumb_set TIM1_CC_IRQHandler,Default_Handler
   .weak TIM2_IRQHandler
   .thumb_set TIM2_IRQHandler,Default_Handler
   .weak TIM3_IRQHandler
   .thumb_set TIM3_IRQHandler,Default_Handler
   .weak TIM14_IRQHandler
   .thumb_set TIM14_IRQHandler,Default_Handler
   .weak TIM16_IRQHandler
   .thumb_set TIM16_IRQHandler,Default_Handler
   .weak TIM17_IRQHandler
   .thumb_set TIM17_IRQHandler,Default_Handler
   .weak I2C1_IRQHandler
   .thumb_set I2C1_IRQHandler,Default_Handler
   .weak SPI1_IRQHandler
   .thumb_set SPI1_IRQHandler,Default_Handler
   .weak USART1_IRQHandler
   .thumb_set USART1_IRQHandler,Default_Handler
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f030.s

➞

Show inline comments

@@ new file 100644 @@
 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
 ;* File Name          : startup_stm32f030.s
 ;* Author             : MCD Application Team
 ;* Version            : V1.4.0
 ;* Date               : 24-July-2014
 ;* Description        : STM32F030 devices vector table for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
 ;*                      - Set the initial PC == Reset_Handler
 ;*                      - Set the vector table entries with the exceptions ISR address
 ;*                      - Configure the system clock
 ;*                      - Branches to __main in the C library (which eventually
 ;*                        calls main()).
 ;*                      After Reset the CortexM0 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;* <<< Use Configuration Wizard in Context Menu >>>
 ;*******************************************************************************
 ;  @attention
+;
 ;  Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 ;  You may not use this file except in compliance with the License.
 ;  You may obtain a copy of the License at:
+;
 ;         http://www.st.com/software_license_agreement_liberty_v2
+;
 ;  Unless required by applicable law or agreed to in writing, software
 ;  distributed under the License is distributed on an "AS IS" BASIS,
 ;  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 ;  See the License for the specific language governing permissions and
 ;  limitations under the License.
+;
 ;*******************************************************************************
+;
 ; Amount of memory (in bytes) allocated for Stack
 ; Tailor this value to your application needs
 ; <h> Stack Configuration
 ;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
 ; </h>
 Stack_Size      EQU     0x00000400
                 AREA    STACK, NOINIT, READWRITE, ALIGN=3
 Stack_Mem       SPACE   Stack_Size
 __initial_sp
 ; <h> Heap Configuration
 ;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
 ; </h>
 Heap_Size       EQU     0x00000200
                 AREA    HEAP, NOINIT, READWRITE, ALIGN=3
 __heap_base
 Heap_Mem        SPACE   Heap_Size
 __heap_limit
                 PRESERVE8
                 THUMB
 ; Vector Table Mapped to Address 0 at Reset
                 AREA    RESET, DATA, READONLY
                 EXPORT  __Vectors
                 EXPORT  __Vectors_End
                 EXPORT  __Vectors_Size
 __Vectors       DCD     __initial_sp                   ; Top of Stack
                 DCD     Reset_Handler                  ; Reset Handler
                 DCD     NMI_Handler                    ; NMI Handler
                 DCD     HardFault_Handler              ; Hard Fault Handler
                 DCD     0                              ; Reserved
                 DCD     0                              ; Reserved
                 DCD     0                              ; Reserved
                 DCD     0                              ; Reserved
                 DCD     0                              ; Reserved
                 DCD     0                              ; Reserved
                 DCD     0                              ; Reserved
                 DCD     SVC_Handler                    ; SVCall Handler
                 DCD     0                              ; Reserved
                 DCD     0                              ; Reserved
                 DCD     PendSV_Handler                 ; PendSV Handler
                 DCD     SysTick_Handler                ; SysTick Handler
                 ; External Interrupts
                 DCD     WWDG_IRQHandler                ; Window Watchdog
                 DCD     0                              ; Reserved
                 DCD     RTC_IRQHandler                 ; RTC through EXTI Line
                 DCD     FLASH_IRQHandler               ; FLASH
                 DCD     RCC_IRQHandler                 ; RCC
                 DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
                 DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
                 DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
                 DCD     0                              ; Reserved
                 DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
                 DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
                 DCD     DMA1_Channel4_5_IRQHandler     ; DMA1 Channel 4 and Channel 5
                 DCD     ADC1_IRQHandler                ; ADC1
                 DCD     TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
                 DCD     TIM1_CC_IRQHandler             ; TIM1 Capture Compare
                 DCD     0                              ; Reserved
                 DCD     TIM3_IRQHandler                ; TIM3
                 DCD     0                              ; Reserved
                 DCD     0                              ; Reserved
                 DCD     TIM14_IRQHandler               ; TIM14
                 DCD     TIM15_IRQHandler               ; TIM15
                 DCD     TIM16_IRQHandler               ; TIM16
                 DCD     TIM17_IRQHandler               ; TIM17
                 DCD     I2C1_IRQHandler                ; I2C1
                 DCD     I2C2_IRQHandler                ; I2C2
                 DCD     SPI1_IRQHandler                ; SPI1
                 DCD     SPI2_IRQHandler                ; SPI2
                 DCD     USART1_IRQHandler              ; USART1
                 DCD     USART2_IRQHandler              ; USART2
 __Vectors_End
 __Vectors_Size  EQU  __Vectors_End - __Vectors
                 AREA    |.text|, CODE, READONLY
 ; Reset handler routine
 Reset_Handler    PROC
                  EXPORT  Reset_Handler                 [WEAK]
         IMPORT  __main
         IMPORT  SystemInit
         LDR     R0, =__initial_sp          ; set stack pointer
         MSR     MSP, R0
 ;;Check if boot space corresponds to test memory
         LDR R0,=0x00000004
         LDR R1, [R0]
         LSRS R1, R1, #24
         LDR R2,=0x1F
         CMP R1, R2
         BNE ApplicationStart
 ;; SYSCFG clock enable
         LDR R0,=0x40021018
         LDR R1,=0x00000001
         STR R1, [R0]
 ;; Set CFGR1 register with flash memory remap at address 0
         LDR R0,=0x40010000
         LDR R1,=0x00000000
         STR R1, [R0]
 ApplicationStart
                  LDR     R0, =SystemInit
                  BLX     R0
                  LDR     R0, =__main
                  BX      R0
                  ENDP
 ; Dummy Exception Handlers (infinite loops which can be modified)
 NMI_Handler     PROC
                 EXPORT  NMI_Handler                    [WEAK]
                 B       .
                 ENDP
 HardFault_Handler\
                 PROC
                 EXPORT  HardFault_Handler              [WEAK]
                 B       .
                 ENDP
 SVC_Handler     PROC
                 EXPORT  SVC_Handler                    [WEAK]
                 B       .
                 ENDP
 PendSV_Handler  PROC
                 EXPORT  PendSV_Handler                 [WEAK]
                 B       .
                 ENDP
 SysTick_Handler PROC
                 EXPORT  SysTick_Handler                [WEAK]
                 B       .
                 ENDP
 Default_Handler PROC
                 EXPORT  WWDG_IRQHandler                [WEAK]
                 EXPORT  RTC_IRQHandler                 [WEAK]
                 EXPORT  FLASH_IRQHandler               [WEAK]
                 EXPORT  RCC_IRQHandler                 [WEAK]
                 EXPORT  EXTI0_1_IRQHandler             [WEAK]
                 EXPORT  EXTI2_3_IRQHandler             [WEAK]
                 EXPORT  EXTI4_15_IRQHandler            [WEAK]
                 EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
                 EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
                 EXPORT  DMA1_Channel4_5_IRQHandler     [WEAK]
                 EXPORT  ADC1_IRQHandler                [WEAK]
                 EXPORT  TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
                 EXPORT  TIM1_CC_IRQHandler             [WEAK]
                 EXPORT  TIM3_IRQHandler                [WEAK]
                 EXPORT  TIM14_IRQHandler               [WEAK]
                 EXPORT  TIM15_IRQHandler               [WEAK]
                 EXPORT  TIM16_IRQHandler               [WEAK]
                 EXPORT  TIM17_IRQHandler               [WEAK]
                 EXPORT  I2C1_IRQHandler                [WEAK]
                 EXPORT  I2C2_IRQHandler                [WEAK]
                 EXPORT  SPI1_IRQHandler                [WEAK]
                 EXPORT  SPI2_IRQHandler                [WEAK]
                 EXPORT  USART1_IRQHandler              [WEAK]
                 EXPORT  USART2_IRQHandler              [WEAK]
 WWDG_IRQHandler
 RTC_IRQHandler
 FLASH_IRQHandler
 RCC_IRQHandler
 EXTI0_1_IRQHandler
 EXTI2_3_IRQHandler
 EXTI4_15_IRQHandler
 DMA1_Channel1_IRQHandler
 DMA1_Channel2_3_IRQHandler
 DMA1_Channel4_5_IRQHandler
 ADC1_IRQHandler
 TIM1_BRK_UP_TRG_COM_IRQHandler
 TIM1_CC_IRQHandler
 TIM3_IRQHandler
 TIM14_IRQHandler
 TIM15_IRQHandler
 TIM16_IRQHandler
 TIM17_IRQHandler
 I2C1_IRQHandler
 I2C2_IRQHandler
 SPI1_IRQHandler
 SPI2_IRQHandler
 USART1_IRQHandler
 USART2_IRQHandler
                 B       .
                 ENDP
                 ALIGN
 ;*******************************************************************************
 ; User Stack and Heap initialization
 ;*******************************************************************************
                  IF      :DEF:__MICROLIB
                  EXPORT  __initial_sp
                  EXPORT  __heap_base
                  EXPORT  __heap_limit
                  ELSE
                  IMPORT  __use_two_region_memory
                  EXPORT  __user_initial_stackheap
 __user_initial_stackheap
                  LDR     R0, =  Heap_Mem
                  LDR     R1, =(Stack_Mem + Stack_Size)
                  LDR     R2, = (Heap_Mem +  Heap_Size)
                  LDR     R3, = Stack_Mem
                  BX      LR
                  ALIGN
                  ENDIF
                  END
 ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f031.s

➞

Show inline comments

@@ new file 100644 @@
 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
 ;* File Name          : startup_stm32f031.s
 ;* Author             : MCD Application Team
 ;* Version            : V1.4.0
 ;* Date               : 24-July-2014
 ;* Description        : STM32F031 devices vector table for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
 ;*                      - Set the initial PC == Reset_Handler
 ;*                      - Set the vector table entries with the exceptions ISR address
 ;*                      - Configure the system clock
 ;*                      - Branches to __main in the C library (which eventually
 ;*                        calls main()).
 ;*                      After Reset the CortexM0 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;* <<< Use Configuration Wizard in Context Menu >>>
 ;*******************************************************************************
 ;  @attention
+;
 ;  Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 ;  You may not use this file except in compliance with the License.
 ;  You may obtain a copy of the License at:
+;
 ;         http://www.st.com/software_license_agreement_liberty_v2
+;
 ;  Unless required by applicable law or agreed to in writing, software
 ;  distributed under the License is distributed on an "AS IS" BASIS,
 ;  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 ;  See the License for the specific language governing permissions and
 ;  limitations under the License.
+;
 ;*******************************************************************************
+;
 ; Amount of memory (in bytes) allocated for Stack
 ; Tailor this value to your application needs
 ; <h> Stack Configuration
 ;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
 ; </h>
 Stack_Size      EQU     0x00000400
                 AREA    STACK, NOINIT, READWRITE, ALIGN=3
 Stack_Mem       SPACE   Stack_Size
 __initial_sp
 ; <h> Heap Configuration
 ;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
 ; </h>
 Heap_Size       EQU     0x00000200
                 AREA    HEAP, NOINIT, READWRITE, ALIGN=3
 __heap_base
 Heap_Mem        SPACE   Heap_Size
 __heap_limit
                 PRESERVE8
                 THUMB
 ; Vector Table Mapped to Address 0 at Reset
                 AREA    RESET, DATA, READONLY
                 EXPORT  __Vectors
                 EXPORT  __Vectors_End
                 EXPORT  __Vectors_Size
 __Vectors       DCD     __initial_sp                   ; Top of Stack
                 DCD     Reset_Handler                  ; Reset Handler
                 DCD     NMI_Handler                    ; NMI Handler
                 DCD     HardFault_Handler              ; Hard Fault Handler
                 DCD     0                              ; Reserved
                 DCD     0                              ; Reserved
                 DCD     0                              ; Reserved
                 DCD     0                              ; Reserved
                 DCD     0                              ; Reserved
                 DCD     0                              ; Reserved
                 DCD     0                              ; Reserved
                 DCD     SVC_Handler                    ; SVCall Handler
                 DCD     0                              ; Reserved
                 DCD     0                              ; Reserved
                 DCD     PendSV_Handler                 ; PendSV Handler
                 DCD     SysTick_Handler                ; SysTick Handler
                 ; External Interrupts
                 DCD     WWDG_IRQHandler                ; Window Watchdog
                 DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
                 DCD     RTC_IRQHandler                 ; RTC through EXTI Line
                 DCD     FLASH_IRQHandler               ; FLASH
                 DCD     RCC_IRQHandler                 ; RCC
                 DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
                 DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
                 DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
                 DCD     0                              ; Reserved
                 DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
                 DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
                 DCD     DMA1_Channel4_5_IRQHandler     ; DMA1 Channel 4 and Channel 5
                 DCD     ADC1_IRQHandler                ; ADC1
                 DCD     TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
                 DCD     TIM1_CC_IRQHandler             ; TIM1 Capture Compare
                 DCD     TIM2_IRQHandler                ; TIM2
                 DCD     TIM3_IRQHandler                ; TIM3
                 DCD     0                              ; Reserved
                 DCD     0                              ; Reserved
                 DCD     TIM14_IRQHandler               ; TIM14
                 DCD     0                              ; Reserved
                 DCD     TIM16_IRQHandler               ; TIM16
                 DCD     TIM17_IRQHandler               ; TIM17
                 DCD     I2C1_IRQHandler                ; I2C1
                 DCD     0                              ; Reserved
                 DCD     SPI1_IRQHandler                ; SPI1
                 DCD     0                              ; Reserved
                 DCD     USART1_IRQHandler              ; USART1
 __Vectors_End
 __Vectors_Size  EQU  __Vectors_End - __Vectors
                 AREA    |.text|, CODE, READONLY
 ; Reset handler routine
 Reset_Handler    PROC
                  EXPORT  Reset_Handler                 [WEAK]
         IMPORT  __main
         IMPORT  SystemInit
         LDR     R0, =__initial_sp          ; set stack pointer
         MSR     MSP, R0
 ;;Check if boot space corresponds to test memory
         LDR R0,=0x00000004
         LDR R1, [R0]
         LSRS R1, R1, #24
         LDR R2,=0x1F
         CMP R1, R2
         BNE ApplicationStart
 ;; SYSCFG clock enable
         LDR R0,=0x40021018
         LDR R1,=0x00000001
         STR R1, [R0]
 ;; Set CFGR1 register with flash memory remap at address 0
         LDR R0,=0x40010000
         LDR R1,=0x00000000
         STR R1, [R0]
 ApplicationStart
                  LDR     R0, =SystemInit
                  BLX     R0
                  LDR     R0, =__main
                  BX      R0
                  ENDP
 ; Dummy Exception Handlers (infinite loops which can be modified)
 NMI_Handler     PROC
                 EXPORT  NMI_Handler                    [WEAK]
                 B       .
                 ENDP
 HardFault_Handler\
                 PROC
                 EXPORT  HardFault_Handler              [WEAK]
                 B       .
                 ENDP
 SVC_Handler     PROC
                 EXPORT  SVC_Handler                    [WEAK]
                 B       .
                 ENDP
 PendSV_Handler  PROC
                 EXPORT  PendSV_Handler                 [WEAK]
                 B       .
                 ENDP
 SysTick_Handler PROC
                 EXPORT  SysTick_Handler                [WEAK]
                 B       .
                 ENDP
 Default_Handler PROC
                 EXPORT  WWDG_IRQHandler                [WEAK]
                 EXPORT  PVD_IRQHandler                 [WEAK]
                 EXPORT  RTC_IRQHandler                 [WEAK]
                 EXPORT  FLASH_IRQHandler               [WEAK]
                 EXPORT  RCC_IRQHandler                 [WEAK]
                 EXPORT  EXTI0_1_IRQHandler             [WEAK]
                 EXPORT  EXTI2_3_IRQHandler             [WEAK]
                 EXPORT  EXTI4_15_IRQHandler            [WEAK]
                 EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
                 EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
                 EXPORT  DMA1_Channel4_5_IRQHandler     [WEAK]
                 EXPORT  ADC1_IRQHandler                [WEAK]
                 EXPORT  TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
                 EXPORT  TIM1_CC_IRQHandler             [WEAK]
                 EXPORT  TIM2_IRQHandler                [WEAK]
                 EXPORT  TIM3_IRQHandler                [WEAK]
                 EXPORT  TIM14_IRQHandler               [WEAK]
                 EXPORT  TIM16_IRQHandler               [WEAK]
                 EXPORT  TIM17_IRQHandler               [WEAK]
                 EXPORT  I2C1_IRQHandler                [WEAK]
                 EXPORT  SPI1_IRQHandler                [WEAK]
                 EXPORT  USART1_IRQHandler              [WEAK]
 WWDG_IRQHandler
 PVD_IRQHandler
 RTC_IRQHandler
 FLASH_IRQHandler
 RCC_IRQHandler
 EXTI0_1_IRQHandler
 EXTI2_3_IRQHandler
 EXTI4_15_IRQHandler
 DMA1_Channel1_IRQHandler
 DMA1_Channel2_3_IRQHandler
 DMA1_Channel4_5_IRQHandler
 ADC1_IRQHandler
 TIM1_BRK_UP_TRG_COM_IRQHandler
 TIM1_CC_IRQHandler
 TIM2_IRQHandler
 TIM3_IRQHandler
 TIM14_IRQHandler
 TIM16_IRQHandler
 TIM17_IRQHandler
 I2C1_IRQHandler
 SPI1_IRQHandler
 USART1_IRQHandler
                 B       .
                 ENDP
                 ALIGN
 ;*******************************************************************************
 ; User Stack and Heap initialization
 ;*******************************************************************************
                  IF      :DEF:__MICROLIB
                  EXPORT  __initial_sp
                  EXPORT  __heap_base
                  EXPORT  __heap_limit
                  ELSE
                  IMPORT  __use_two_region_memory
                  EXPORT  __user_initial_stackheap
 __user_initial_stackheap
                  LDR     R0, =  Heap_Mem
                  LDR     R1, =(Stack_Mem + Stack_Size)
                  LDR     R2, = (Heap_Mem +  Heap_Size)
                  LDR     R3, = Stack_Mem
                  BX      LR
                  ALIGN
                  ENDIF
                  END
 ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f042.s

➞

Show inline comments

@@ new file 100644 @@
 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
 ;* File Name          : startup_stm32f042.s
 ;* Author             : MCD Application Team
 ;* Version            : V1.4.0
 ;* Date               : 24-July-2014
 ;* Description        : STM32F042 Devices vector table for
 ;*                      for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
 ;*                      - Set the initial PC == Reset_Handler
 ;*                      - Set the vector table entries with the exceptions ISR address
 ;*                      - Configure the system clock
 ;*                      - Branches to __main in the C library (which eventually
 ;*                        calls main()).
 ;*                      After Reset the CortexM0 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;* <<< Use Configuration Wizard in Context Menu >>>
 ;*******************************************************************************
 ;  @attention
+;
 ;  Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 ;  You may not use this file except in compliance with the License.
 ;  You may obtain a copy of the License at:
+;
 ;         http://www.st.com/software_license_agreement_liberty_v2
+;
 ;  Unless required by applicable law or agreed to in writing, software
 ;  distributed under the License is distributed on an "AS IS" BASIS,
 ;  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 ;  See the License for the specific language governing permissions and
 ;  limitations under the License.
+;
 ;*******************************************************************************
+;
 ; Amount of memory (in bytes) allocated for Stack
 ; Tailor this value to your application needs
 ; <h> Stack Configuration
 ;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
 ; </h>
 Stack_Size      EQU     0x00000400
                 AREA    STACK, NOINIT, READWRITE, ALIGN=3
 Stack_Mem       SPACE   Stack_Size
 __initial_sp
 ; <h> Heap Configuration
 ;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
 ; </h>
 Heap_Size       EQU     0x00000200
                 AREA    HEAP, NOINIT, READWRITE, ALIGN=3
 __heap_base
 Heap_Mem        SPACE   Heap_Size
 __heap_limit
                 PRESERVE8
                 THUMB
 ; Vector Table Mapped to Address 0 at Reset
                 AREA    RESET, DATA, READONLY
                 EXPORT  __Vectors
                 EXPORT  __Vectors_End
                 EXPORT  __Vectors_Size
 __Vectors       DCD     __initial_sp                   ; Top of Stack
                         DCD     Reset_Handler                  ; Reset Handler
                         DCD     NMI_Handler                    ; NMI Handler
                         DCD     HardFault_Handler              ; Hard Fault Handler
                         DCD     0                              ; Reserved
                         DCD     0                              ; Reserved
                         DCD     0                              ; Reserved
                         DCD     0                              ; Reserved
                         DCD     0                              ; Reserved
                         DCD     0                              ; Reserved
                         DCD     0                              ; Reserved
                         DCD     SVC_Handler                    ; SVCall Handler
                         DCD     0                              ; Reserved
                         DCD     0                              ; Reserved
                         DCD     PendSV_Handler                 ; PendSV Handler
                         DCD     SysTick_Handler                ; SysTick Handler
                 ; External Interrupts
                 DCD     WWDG_IRQHandler                ; Window Watchdog
                 DCD     PVD_VDDIO2_IRQHandler          ; PVD and VDDIO2 through EXTI Line detect
                 DCD     RTC_IRQHandler                 ; RTC through EXTI Line
                 DCD     FLASH_IRQHandler               ; FLASH
                 DCD     RCC_CRS_IRQHandler             ; RCC and CRS
                 DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
                 DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
                 DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
                 DCD     TSC_IRQHandler                 ; TS
                 DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
                 DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
                 DCD     DMA1_Channel4_5_IRQHandler     ; DMA1 Channel 4, Channel 5
                 DCD     ADC1_IRQHandler                ; ADC1
                 DCD     TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
                 DCD     TIM1_CC_IRQHandler             ; TIM1 Capture Compare
                 DCD     TIM2_IRQHandler                ; TIM2
                 DCD     TIM3_IRQHandler                ; TIM3
                 DCD     0                              ; Reserved
                 DCD     0                              ; Reserved
                 DCD     TIM14_IRQHandler               ; TIM14
                 DCD     0                              ; Reserved
                 DCD     TIM16_IRQHandler               ; TIM16
                 DCD     TIM17_IRQHandler               ; TIM17
                 DCD     I2C1_IRQHandler                ; I2C1
                 DCD     0                              ; Reserved
                 DCD     SPI1_IRQHandler                ; SPI1
                 DCD     SPI2_IRQHandler                ; SPI2
                 DCD     USART1_IRQHandler              ; USART1
                 DCD     USART2_IRQHandler              ; USART2
                 DCD     0                              ; Reserved
                 DCD     CEC_CAN_IRQHandler             ; CEC and CAN
                 DCD     USB_IRQHandler                 ; USB
 __Vectors_End
 __Vectors_Size  EQU  __Vectors_End - __Vectors
                 AREA    |.text|, CODE, READONLY
 ; Reset handler routine
 Reset_Handler    PROC
                  EXPORT  Reset_Handler                 [WEAK]
         IMPORT  __main
         IMPORT  SystemInit
         LDR     R0, =__initial_sp          ; set stack pointer
         MSR     MSP, R0
 ;;Check if boot space corresponds to test memory
         LDR R0,=0x00000004
         LDR R1, [R0]
         LSRS R1, R1, #24
         LDR R2,=0x1F
         CMP R1, R2
         BNE ApplicationStart
 ;; SYSCFG clock enable
         LDR R0,=0x40021018
         LDR R1,=0x00000001
         STR R1, [R0]
 ;; Set CFGR1 register with flash memory remap at address 0
         LDR R0,=0x40010000
         LDR R1,=0x00000000
         STR R1, [R0]
 ApplicationStart
                  LDR     R0, =SystemInit
                  BLX     R0
                  LDR     R0, =__main
                  BX      R0
                  ENDP
 ; Dummy Exception Handlers (infinite loops which can be modified)
 NMI_Handler     PROC
                 EXPORT  NMI_Handler                    [WEAK]
                 B       .
                 ENDP
 HardFault_Handler\
                 PROC
                 EXPORT  HardFault_Handler              [WEAK]
                 B       .
                 ENDP
 SVC_Handler     PROC
                 EXPORT  SVC_Handler                    [WEAK]
                 B       .
                 ENDP
 PendSV_Handler  PROC
                 EXPORT  PendSV_Handler                 [WEAK]
                 B       .
                 ENDP
 SysTick_Handler PROC
                 EXPORT  SysTick_Handler                [WEAK]
                 B       .
                 ENDP
 Default_Handler PROC
                 EXPORT  WWDG_IRQHandler                [WEAK]
                 EXPORT  PVD_VDDIO2_IRQHandler          [WEAK]
                 EXPORT  RTC_IRQHandler                 [WEAK]
                 EXPORT  FLASH_IRQHandler               [WEAK]
                 EXPORT  RCC_CRS_IRQHandler             [WEAK]
                 EXPORT  EXTI0_1_IRQHandler             [WEAK]
                 EXPORT  EXTI2_3_IRQHandler             [WEAK]
                 EXPORT  EXTI4_15_IRQHandler            [WEAK]
                 EXPORT  TSC_IRQHandler                  [WEAK]
                 EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
                 EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
                 EXPORT  DMA1_Channel4_5_IRQHandler     [WEAK]
                 EXPORT  ADC1_IRQHandler                [WEAK]
                 EXPORT  TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
                 EXPORT  TIM1_CC_IRQHandler             [WEAK]
                 EXPORT  TIM2_IRQHandler                [WEAK]
                 EXPORT  TIM3_IRQHandler                [WEAK]
                 EXPORT  TIM14_IRQHandler               [WEAK]
                 EXPORT  TIM16_IRQHandler               [WEAK]
                 EXPORT  TIM17_IRQHandler               [WEAK]
                 EXPORT  I2C1_IRQHandler                [WEAK]
                 EXPORT  SPI1_IRQHandler                [WEAK]
                 EXPORT  SPI2_IRQHandler                [WEAK]
                 EXPORT  USART1_IRQHandler              [WEAK]
                 EXPORT  USART2_IRQHandler              [WEAK]
                 EXPORT  CEC_CAN_IRQHandler             [WEAK]
                 EXPORT  USB_IRQHandler                 [WEAK]
 WWDG_IRQHandler
 PVD_VDDIO2_IRQHandler
 RTC_IRQHandler
 FLASH_IRQHandler
 RCC_CRS_IRQHandler
 EXTI0_1_IRQHandler
 EXTI2_3_IRQHandler
 EXTI4_15_IRQHandler
 TSC_IRQHandler
 DMA1_Channel1_IRQHandler
 DMA1_Channel2_3_IRQHandler
 DMA1_Channel4_5_IRQHandler
 ADC1_IRQHandler
 TIM1_BRK_UP_TRG_COM_IRQHandler
 TIM1_CC_IRQHandler
 TIM2_IRQHandler
 TIM3_IRQHandler
 TIM14_IRQHandler
 TIM16_IRQHandler
 TIM17_IRQHandler
 I2C1_IRQHandler
 SPI1_IRQHandler
 SPI2_IRQHandler
 USART1_IRQHandler
 USART2_IRQHandler
 CEC_CAN_IRQHandler
 USB_IRQHandler
                 B       .
                 ENDP
                 ALIGN
 ;*******************************************************************************
 ; User Stack and Heap initialization
 ;*******************************************************************************
                  IF      :DEF:__MICROLIB
                  EXPORT  __initial_sp
                  EXPORT  __heap_base
                  EXPORT  __heap_limit
                  ELSE
                  IMPORT  __use_two_region_memory
                  EXPORT  __user_initial_stackheap
 __user_initial_stackheap
                  LDR     R0, =  Heap_Mem
                  LDR     R1, =(Stack_Mem + Stack_Size)
                  LDR     R2, = (Heap_Mem +  Heap_Size)
                  LDR     R3, = Stack_Mem
                  BX      LR
                  ALIGN
                  ENDIF
                  END
 ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f051.s

➞

Show inline comments

@@ new file 100644 @@
 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
 ;* File Name          : startup_stm32f051.s
 ;* Author             : MCD Application Team
 ;* Version            : V1.4.0
 ;* Date               : 24-July-2014
 ;* Description        : STM32F051 devices vector table for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
 ;*                      - Set the initial PC == Reset_Handler
 ;*                      - Set the vector table entries with the exceptions ISR address
 ;*                      - Configure the system clock
 ;*                      - Branches to __main in the C library (which eventually
 ;*                        calls main()).
 ;*                      After Reset the CortexM0 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;* <<< Use Configuration Wizard in Context Menu >>>
 ;*******************************************************************************
 ;  @attention
+;
 ;  Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 ;  You may not use this file except in compliance with the License.
 ;  You may obtain a copy of the License at:
+;
 ;         http://www.st.com/software_license_agreement_liberty_v2
+;
 ;  Unless required by applicable law or agreed to in writing, software
 ;  distributed under the License is distributed on an "AS IS" BASIS,
 ;  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 ;  See the License for the specific language governing permissions and
 ;  limitations under the License.
+;
 ;*******************************************************************************
+;
 ; Amount of memory (in bytes) allocated for Stack
 ; Tailor this value to your application needs
 ; <h> Stack Configuration
 ;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
 ; </h>
 Stack_Size      EQU     0x00000400
                 AREA    STACK, NOINIT, READWRITE, ALIGN=3
 Stack_Mem       SPACE   Stack_Size
 __initial_sp
 ; <h> Heap Configuration
 ;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
 ; </h>
 Heap_Size       EQU     0x00000200
                 AREA    HEAP, NOINIT, READWRITE, ALIGN=3
 __heap_base
 Heap_Mem        SPACE   Heap_Size
 __heap_limit
                 PRESERVE8
                 THUMB
 ; Vector Table Mapped to Address 0 at Reset
                 AREA    RESET, DATA, READONLY
                 EXPORT  __Vectors
                 EXPORT  __Vectors_End
                 EXPORT  __Vectors_Size
 __Vectors       DCD     __initial_sp                   ; Top of Stack
                 DCD     Reset_Handler                  ; Reset Handler
                 DCD     NMI_Handler                    ; NMI Handler
                 DCD     HardFault_Handler              ; Hard Fault Handler
                 DCD     0                              ; Reserved
                 DCD     0                              ; Reserved
                 DCD     0                              ; Reserved
                 DCD     0                              ; Reserved
                 DCD     0                              ; Reserved
                 DCD     0                              ; Reserved
                 DCD     0                              ; Reserved
                 DCD     SVC_Handler                    ; SVCall Handler
                 DCD     0                              ; Reserved
                 DCD     0                              ; Reserved
                 DCD     PendSV_Handler                 ; PendSV Handler
                 DCD     SysTick_Handler                ; SysTick Handler
                 ; External Interrupts
                 DCD     WWDG_IRQHandler                ; Window Watchdog
                 DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
                 DCD     RTC_IRQHandler                 ; RTC through EXTI Line
                 DCD     FLASH_IRQHandler               ; FLASH
                 DCD     RCC_IRQHandler                 ; RCC
                 DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
                 DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
                 DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
                 DCD     TS_IRQHandler                  ; TS
                 DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
                 DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
                 DCD     DMA1_Channel4_5_IRQHandler     ; DMA1 Channel 4 and Channel 5
                 DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2
                 DCD     TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
                 DCD     TIM1_CC_IRQHandler             ; TIM1 Capture Compare
                 DCD     TIM2_IRQHandler                ; TIM2
                 DCD     TIM3_IRQHandler                ; TIM3
                 DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
                 DCD     0                              ; Reserved
                 DCD     TIM14_IRQHandler               ; TIM14
                 DCD     TIM15_IRQHandler               ; TIM15
                 DCD     TIM16_IRQHandler               ; TIM16
                 DCD     TIM17_IRQHandler               ; TIM17
                 DCD     I2C1_IRQHandler                ; I2C1
                 DCD     I2C2_IRQHandler                ; I2C2
                 DCD     SPI1_IRQHandler                ; SPI1
                 DCD     SPI2_IRQHandler                ; SPI2
                 DCD     USART1_IRQHandler              ; USART1
                 DCD     USART2_IRQHandler              ; USART2
                 DCD     0                              ; Reserved
                 DCD     CEC_IRQHandler                 ; CEC
                 DCD     0                              ; Reserved
 __Vectors_End
 __Vectors_Size  EQU  __Vectors_End - __Vectors
                 AREA    |.text|, CODE, READONLY
 ; Reset handler routine
 Reset_Handler    PROC
                  EXPORT  Reset_Handler                 [WEAK]
         IMPORT  __main
         IMPORT  SystemInit
         LDR     R0, =__initial_sp          ; set stack pointer
         MSR     MSP, R0
 ;;Check if boot space corresponds to test memory
         LDR R0,=0x00000004
         LDR R1, [R0]
         LSRS R1, R1, #24
         LDR R2,=0x1F
         CMP R1, R2
         BNE ApplicationStart
 ;; SYSCFG clock enable
         LDR R0,=0x40021018
         LDR R1,=0x00000001
         STR R1, [R0]
 ;; Set CFGR1 register with flash memory remap at address 0
         LDR R0,=0x40010000
         LDR R1,=0x00000000
         STR R1, [R0]
 ApplicationStart
                  LDR     R0, =SystemInit
                  BLX     R0
                  LDR     R0, =__main
                  BX      R0
                  ENDP
 ; Dummy Exception Handlers (infinite loops which can be modified)
 NMI_Handler     PROC
                 EXPORT  NMI_Handler                    [WEAK]
                 B       .
                 ENDP
 HardFault_Handler\
                 PROC
                 EXPORT  HardFault_Handler              [WEAK]
                 B       .
                 ENDP
 SVC_Handler     PROC
                 EXPORT  SVC_Handler                    [WEAK]
                 B       .
                 ENDP
 PendSV_Handler  PROC
                 EXPORT  PendSV_Handler                 [WEAK]
                 B       .
                 ENDP
 SysTick_Handler PROC
                 EXPORT  SysTick_Handler                [WEAK]
                 B       .
                 ENDP
 Default_Handler PROC
                 EXPORT  WWDG_IRQHandler                [WEAK]
                 EXPORT  PVD_IRQHandler                 [WEAK]
                 EXPORT  RTC_IRQHandler                 [WEAK]
                 EXPORT  FLASH_IRQHandler               [WEAK]
                 EXPORT  RCC_IRQHandler                 [WEAK]
                 EXPORT  EXTI0_1_IRQHandler             [WEAK]
                 EXPORT  EXTI2_3_IRQHandler             [WEAK]
                 EXPORT  EXTI4_15_IRQHandler            [WEAK]
                 EXPORT  TS_IRQHandler                  [WEAK]
                 EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
                 EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
                 EXPORT  DMA1_Channel4_5_IRQHandler     [WEAK]
                 EXPORT  ADC1_COMP_IRQHandler           [WEAK]
                 EXPORT  TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
                 EXPORT  TIM1_CC_IRQHandler             [WEAK]
                 EXPORT  TIM2_IRQHandler                [WEAK]
                 EXPORT  TIM3_IRQHandler                [WEAK]
                 EXPORT  TIM6_DAC_IRQHandler            [WEAK]
                 EXPORT  TIM14_IRQHandler               [WEAK]
                 EXPORT  TIM15_IRQHandler               [WEAK]
                 EXPORT  TIM16_IRQHandler               [WEAK]
                 EXPORT  TIM17_IRQHandler               [WEAK]
                 EXPORT  I2C1_IRQHandler                [WEAK]
                 EXPORT  I2C2_IRQHandler                [WEAK]
                 EXPORT  SPI1_IRQHandler                [WEAK]
                 EXPORT  SPI2_IRQHandler                [WEAK]
                 EXPORT  USART1_IRQHandler              [WEAK]
                 EXPORT  USART2_IRQHandler              [WEAK]
                 EXPORT  CEC_IRQHandler                 [WEAK]
 WWDG_IRQHandler
 PVD_IRQHandler
 RTC_IRQHandler
 FLASH_IRQHandler
 RCC_IRQHandler
 EXTI0_1_IRQHandler
 EXTI2_3_IRQHandler
 EXTI4_15_IRQHandler
 TS_IRQHandler
 DMA1_Channel1_IRQHandler
 DMA1_Channel2_3_IRQHandler
 DMA1_Channel4_5_IRQHandler
 ADC1_COMP_IRQHandler
 TIM1_BRK_UP_TRG_COM_IRQHandler
 TIM1_CC_IRQHandler
 TIM2_IRQHandler
 TIM3_IRQHandler
 TIM6_DAC_IRQHandler
 TIM14_IRQHandler
 TIM15_IRQHandler
 TIM16_IRQHandler
 TIM17_IRQHandler
 I2C1_IRQHandler
 I2C2_IRQHandler
 SPI1_IRQHandler
 SPI2_IRQHandler
 USART1_IRQHandler
 USART2_IRQHandler
 CEC_IRQHandler
                 B       .
                 ENDP
                 ALIGN
 ;*******************************************************************************
 ; User Stack and Heap initialization
 ;*******************************************************************************
                  IF      :DEF:__MICROLIB
                  EXPORT  __initial_sp
                  EXPORT  __heap_base
                  EXPORT  __heap_limit
                  ELSE
                  IMPORT  __use_two_region_memory
                  EXPORT  __user_initial_stackheap
 __user_initial_stackheap
                  LDR     R0, =  Heap_Mem
                  LDR     R1, =(Stack_Mem + Stack_Size)
                  LDR     R2, = (Heap_Mem +  Heap_Size)
                  LDR     R3, = Stack_Mem
                  BX      LR
                  ALIGN
                  ENDIF
                  END
 ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f072.s

➞

Show inline comments

@@ new file 100644 @@
 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
 ;* File Name          : startup_stm32f072.s
 ;* Author             : MCD Application Team
 ;* Version            : V1.4.0
 ;* Date               : 24-July-2014
 ;* Description        : STM32F072 Devices vector table for
 ;*                      for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
 ;*                      - Set the initial PC == Reset_Handler
 ;*                      - Set the vector table entries with the exceptions ISR address
 ;*                      - Configure the system clock
 ;*                      - Branches to __main in the C library (which eventually
 ;*                        calls main()).
 ;*                      After Reset the CortexM0 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;* <<< Use Configuration Wizard in Context Menu >>>
 ;*******************************************************************************
 ;  @attention
+;
 ;  Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 ;  You may not use this file except in compliance with the License.
 ;  You may obtain a copy of the License at:
+;
 ;         http://www.st.com/software_license_agreement_liberty_v2
+;
 ;  Unless required by applicable law or agreed to in writing, software
 ;  distributed under the License is distributed on an "AS IS" BASIS,
 ;  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 ;  See the License for the specific language governing permissions and
 ;  limitations under the License.
+;
 ;*******************************************************************************
+;
 ; Amount of memory (in bytes) allocated for Stack
 ; Tailor this value to your application needs
 ; <h> Stack Configuration
 ;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
 ; </h>
 Stack_Size      EQU     0x00000400
                 AREA    STACK, NOINIT, READWRITE, ALIGN=3
 Stack_Mem       SPACE   Stack_Size
 __initial_sp
 ; <h> Heap Configuration
 ;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
 ; </h>
 Heap_Size       EQU     0x00000200
                 AREA    HEAP, NOINIT, READWRITE, ALIGN=3
 __heap_base
 Heap_Mem        SPACE   Heap_Size
 __heap_limit
                 PRESERVE8
                 THUMB
 ; Vector Table Mapped to Address 0 at Reset
                 AREA    RESET, DATA, READONLY
                 EXPORT  __Vectors
                 EXPORT  __Vectors_End
                 EXPORT  __Vectors_Size
 __Vectors       DCD     __initial_sp                   ; Top of Stack
                         DCD     Reset_Handler                  ; Reset Handler
                         DCD     NMI_Handler                    ; NMI Handler
                         DCD     HardFault_Handler              ; Hard Fault Handler
                         DCD     0                              ; Reserved
                         DCD     0                              ; Reserved
                         DCD     0                              ; Reserved
                         DCD     0                              ; Reserved
                         DCD     0                              ; Reserved
                         DCD     0                              ; Reserved
                         DCD     0                              ; Reserved
                         DCD     SVC_Handler                    ; SVCall Handler
                         DCD     0                              ; Reserved
                         DCD     0                              ; Reserved
                         DCD     PendSV_Handler                 ; PendSV Handler
                         DCD     SysTick_Handler                ; SysTick Handler
                 ; External Interrupts
                 DCD     WWDG_IRQHandler                ; Window Watchdog
                 DCD     PVD_VDDIO2_IRQHandler          ; PVD and VDDIO2 through EXTI Line detect
                 DCD     RTC_IRQHandler                 ; RTC through EXTI Line
                 DCD     FLASH_IRQHandler               ; FLASH
                 DCD     RCC_CRS_IRQHandler             ; RCC and CRS
                 DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
                 DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
                 DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
                 DCD     TSC_IRQHandler                  ; TS
                 DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
                 DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
                 DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
                 DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2
                 DCD     TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
                 DCD     TIM1_CC_IRQHandler             ; TIM1 Capture Compare
                 DCD     TIM2_IRQHandler                ; TIM2
                 DCD     TIM3_IRQHandler                ; TIM3
                 DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
                 DCD     TIM7_IRQHandler                ; TIM7
                 DCD     TIM14_IRQHandler               ; TIM14
                 DCD     TIM15_IRQHandler               ; TIM15
                 DCD     TIM16_IRQHandler               ; TIM16
                 DCD     TIM17_IRQHandler               ; TIM17
                 DCD     I2C1_IRQHandler                ; I2C1
                 DCD     I2C2_IRQHandler                ; I2C2
                 DCD     SPI1_IRQHandler                ; SPI1
                 DCD     SPI2_IRQHandler                ; SPI2
                 DCD     USART1_IRQHandler              ; USART1
                 DCD     USART2_IRQHandler              ; USART2
                 DCD     USART3_4_IRQHandler            ; USART3 and USART4
                 DCD     CEC_CAN_IRQHandler             ; CEC and CAN
                 DCD     USB_IRQHandler              ; USB
 __Vectors_End
 __Vectors_Size  EQU  __Vectors_End - __Vectors
                 AREA    |.text|, CODE, READONLY
 ; Reset handler routine
 Reset_Handler    PROC
                  EXPORT  Reset_Handler                 [WEAK]
         IMPORT  __main
         IMPORT  SystemInit
         LDR     R0, =__initial_sp          ; set stack pointer
         MSR     MSP, R0
 ;;Check if boot space corresponds to test memory
         LDR R0,=0x00000004
         LDR R1, [R0]
         LSRS R1, R1, #24
         LDR R2,=0x1F
         CMP R1, R2
         BNE ApplicationStart
 ;; SYSCFG clock enable
         LDR R0,=0x40021018
         LDR R1,=0x00000001
         STR R1, [R0]
 ;; Set CFGR1 register with flash memory remap at address 0
         LDR R0,=0x40010000
         LDR R1,=0x00000000
         STR R1, [R0]
 ApplicationStart
                  LDR     R0, =SystemInit
                  BLX     R0
                  LDR     R0, =__main
                  BX      R0
                  ENDP
 ; Dummy Exception Handlers (infinite loops which can be modified)
 NMI_Handler     PROC
                 EXPORT  NMI_Handler                    [WEAK]
                 B       .
                 ENDP
 HardFault_Handler\
                 PROC
                 EXPORT  HardFault_Handler              [WEAK]
                 B       .
                 ENDP
 SVC_Handler     PROC
                 EXPORT  SVC_Handler                    [WEAK]
                 B       .
                 ENDP
 PendSV_Handler  PROC
                 EXPORT  PendSV_Handler                 [WEAK]
                 B       .
                 ENDP
 SysTick_Handler PROC
                 EXPORT  SysTick_Handler                [WEAK]
                 B       .
                 ENDP
 Default_Handler PROC
                 EXPORT  WWDG_IRQHandler                [WEAK]
                 EXPORT  PVD_VDDIO2_IRQHandler          [WEAK]
                 EXPORT  RTC_IRQHandler                 [WEAK]
                 EXPORT  FLASH_IRQHandler               [WEAK]
                 EXPORT  RCC_CRS_IRQHandler             [WEAK]
                 EXPORT  EXTI0_1_IRQHandler             [WEAK]
                 EXPORT  EXTI2_3_IRQHandler             [WEAK]
                 EXPORT  EXTI4_15_IRQHandler            [WEAK]
                 EXPORT  TSC_IRQHandler                  [WEAK]
                 EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
                 EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
                 EXPORT  DMA1_Channel4_5_6_7_IRQHandler [WEAK]
                 EXPORT  ADC1_COMP_IRQHandler           [WEAK]
                 EXPORT  TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
                 EXPORT  TIM1_CC_IRQHandler             [WEAK]
                 EXPORT  TIM2_IRQHandler                [WEAK]
                 EXPORT  TIM3_IRQHandler                [WEAK]
                 EXPORT  TIM6_DAC_IRQHandler            [WEAK]
                 EXPORT  TIM7_IRQHandler                [WEAK]
                 EXPORT  TIM14_IRQHandler               [WEAK]
                 EXPORT  TIM15_IRQHandler               [WEAK]
                 EXPORT  TIM16_IRQHandler               [WEAK]
                 EXPORT  TIM17_IRQHandler               [WEAK]
                 EXPORT  I2C1_IRQHandler                [WEAK]
                 EXPORT  I2C2_IRQHandler                [WEAK]
                 EXPORT  SPI1_IRQHandler                [WEAK]
                 EXPORT  SPI2_IRQHandler                [WEAK]
                 EXPORT  USART1_IRQHandler              [WEAK]
                 EXPORT  USART2_IRQHandler              [WEAK]
                 EXPORT  USART3_4_IRQHandler            [WEAK]
                 EXPORT  CEC_CAN_IRQHandler             [WEAK]
                 EXPORT  USB_IRQHandler                 [WEAK]
 WWDG_IRQHandler
 PVD_VDDIO2_IRQHandler
 RTC_IRQHandler
 FLASH_IRQHandler
 RCC_CRS_IRQHandler
 EXTI0_1_IRQHandler
 EXTI2_3_IRQHandler
 EXTI4_15_IRQHandler
 TSC_IRQHandler
 DMA1_Channel1_IRQHandler
 DMA1_Channel2_3_IRQHandler
 DMA1_Channel4_5_6_7_IRQHandler
 ADC1_COMP_IRQHandler
 TIM1_BRK_UP_TRG_COM_IRQHandler
 TIM1_CC_IRQHandler
 TIM2_IRQHandler
 TIM3_IRQHandler
 TIM6_DAC_IRQHandler
 TIM7_IRQHandler
 TIM14_IRQHandler
 TIM15_IRQHandler
 TIM16_IRQHandler
 TIM17_IRQHandler
 I2C1_IRQHandler
 I2C2_IRQHandler
 SPI1_IRQHandler
 SPI2_IRQHandler
 USART1_IRQHandler
 USART2_IRQHandler
 USART3_4_IRQHandler
 CEC_CAN_IRQHandler
 USB_IRQHandler
                 B       .
                 ENDP
                 ALIGN
 ;*******************************************************************************
 ; User Stack and Heap initialization
 ;*******************************************************************************
                  IF      :DEF:__MICROLIB
                  EXPORT  __initial_sp
                  EXPORT  __heap_base
                  EXPORT  __heap_limit
                  ELSE
                  IMPORT  __use_two_region_memory
                  EXPORT  __user_initial_stackheap
 __user_initial_stackheap
                  LDR     R0, =  Heap_Mem
                  LDR     R1, =(Stack_Mem + Stack_Size)
                  LDR     R2, = (Heap_Mem +  Heap_Size)
                  LDR     R3, = Stack_Mem
                  BX      LR
                  ALIGN
                  ENDIF
                  END
 ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f091.s

➞

Show inline comments

@@ new file 100644 @@
 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
 ;* File Name          : startup_stm32f091.s
 ;* Author             : MCD Application Team
 ;* Version            : V1.4.0
 ;* Date               : 24-July-2014
 ;* Description        : STM32F091 Devices vector table for
 ;*                      for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
 ;*                      - Set the initial PC == Reset_Handler
 ;*                      - Set the vector table entries with the exceptions ISR address
 ;*                      - Configure the system clock
 ;*                      - Branches to __main in the C library (which eventually
 ;*                        calls main()).
 ;*                      After Reset the CortexM0 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;* <<< Use Configuration Wizard in Context Menu >>>
 ;*******************************************************************************
 ;  @attention
+;
 ;  Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 ;  You may not use this file except in compliance with the License.
 ;  You may obtain a copy of the License at:
+;
 ;         http://www.st.com/software_license_agreement_liberty_v2
+;
 ;  Unless required by applicable law or agreed to in writing, software
 ;  distributed under the License is distributed on an "AS IS" BASIS,
 ;  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 ;  See the License for the specific language governing permissions and
 ;  limitations under the License.
+;
 ;*******************************************************************************
+;
 ; Amount of memory (in bytes) allocated for Stack
 ; Tailor this value to your application needs
 ; <h> Stack Configuration
 ;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
 ; </h>
 Stack_Size      EQU     0x00000400
                 AREA    STACK, NOINIT, READWRITE, ALIGN=3
 Stack_Mem       SPACE   Stack_Size
 __initial_sp
 ; <h> Heap Configuration
 ;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
 ; </h>
 Heap_Size       EQU     0x00000200
                 AREA    HEAP, NOINIT, READWRITE, ALIGN=3
 __heap_base
 Heap_Mem        SPACE   Heap_Size
 __heap_limit
                 PRESERVE8
                 THUMB
 ; Vector Table Mapped to Address 0 at Reset
                 AREA    RESET, DATA, READONLY
                 EXPORT  __Vectors
                 EXPORT  __Vectors_End
                 EXPORT  __Vectors_Size
 __Vectors       DCD     __initial_sp                   ; Top of Stack
                         DCD     Reset_Handler                  ; Reset Handler
                         DCD     NMI_Handler                    ; NMI Handler
                         DCD     HardFault_Handler              ; Hard Fault Handler
                         DCD     0                              ; Reserved
                         DCD     0                              ; Reserved
                         DCD     0                              ; Reserved
                         DCD     0                              ; Reserved
                         DCD     0                              ; Reserved
                         DCD     0                              ; Reserved
                         DCD     0                              ; Reserved
                         DCD     SVC_Handler                    ; SVCall Handler
                         DCD     0                              ; Reserved
                         DCD     0                              ; Reserved
                         DCD     PendSV_Handler                 ; PendSV Handler
                         DCD     SysTick_Handler                ; SysTick Handler
                 ; External Interrupts
                 DCD     WWDG_IRQHandler                ; Window Watchdog
                 DCD     PVD_VDDIO2_IRQHandler          ; PVD and VDDIO2 through EXTI Line detect
                 DCD     RTC_IRQHandler                 ; RTC through EXTI Line
                 DCD     FLASH_IRQHandler               ; FLASH
                 DCD     RCC_CRS_IRQHandler             ; RCC and CRS
                 DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
                 DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
                 DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
                 DCD     TSC_IRQHandler                  ; TS
                 DCD     DMA1_Ch1_IRQHandler       		 ; DMA1 Channel 1
                 DCD     DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler ; DMA1 Channel 2 and 3 & DMA2 Channel 1 and 2
                 DCD     DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler ; DMA1 Channel 4 to 7 & DMA2 Channel 3 to 5
                 DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2
                 DCD     TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
                 DCD     TIM1_CC_IRQHandler             ; TIM1 Capture Compare
                 DCD     TIM2_IRQHandler                ; TIM2
                 DCD     TIM3_IRQHandler                ; TIM3
                 DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
                 DCD     TIM7_IRQHandler                ; TIM7
                 DCD     TIM14_IRQHandler               ; TIM14
                 DCD     TIM15_IRQHandler               ; TIM15
                 DCD     TIM16_IRQHandler               ; TIM16
                 DCD     TIM17_IRQHandler               ; TIM17
                 DCD     I2C1_IRQHandler                ; I2C1
                 DCD     I2C2_IRQHandler                ; I2C2
                 DCD     SPI1_IRQHandler                ; SPI1
                 DCD     SPI2_IRQHandler                ; SPI2
                 DCD     USART1_IRQHandler              ; USART1
                 DCD     USART2_IRQHandler              ; USART2
                 DCD     USART3_8_IRQHandler            ; USART3, USART4, USART5, USART6, USART7, USART8
                 DCD     CEC_CAN_IRQHandler             ; CEC and CAN
 __Vectors_End
 __Vectors_Size  EQU  __Vectors_End - __Vectors
                 AREA    |.text|, CODE, READONLY
 ; Reset handler routine
 Reset_Handler    PROC
                  EXPORT  Reset_Handler                 [WEAK]
         IMPORT  __main
         IMPORT  SystemInit
         LDR     R0, =__initial_sp          ; set stack pointer
         MSR     MSP, R0
 ;;Check if boot space corresponds to test memory
         LDR R0,=0x00000004
         LDR R1, [R0]
         LSRS R1, R1, #24
         LDR R2,=0x1F
         CMP R1, R2
         BNE ApplicationStart
 ;; SYSCFG clock enable
         LDR R0,=0x40021018
         LDR R1,=0x00000001
         STR R1, [R0]
 ;; Set CFGR1 register with flash memory remap at address 0
         LDR R0,=0x40010000
         LDR R1,=0x00000000
         STR R1, [R0]
 ApplicationStart
                  LDR     R0, =SystemInit
                  BLX     R0
                  LDR     R0, =__main
                  BX      R0
                  ENDP
 ; Dummy Exception Handlers (infinite loops which can be modified)
 NMI_Handler     PROC
                 EXPORT  NMI_Handler                    [WEAK]
                 B       .
                 ENDP
 HardFault_Handler\
                 PROC
                 EXPORT  HardFault_Handler              [WEAK]
                 B       .
                 ENDP
 SVC_Handler     PROC
                 EXPORT  SVC_Handler                    [WEAK]
                 B       .
                 ENDP
 PendSV_Handler  PROC
                 EXPORT  PendSV_Handler                 [WEAK]
                 B       .
                 ENDP
 SysTick_Handler PROC
                 EXPORT  SysTick_Handler                [WEAK]
                 B       .
                 ENDP
 Default_Handler PROC
                 EXPORT  WWDG_IRQHandler                [WEAK]
                 EXPORT  PVD_VDDIO2_IRQHandler          [WEAK]
                 EXPORT  RTC_IRQHandler                 [WEAK]
                 EXPORT  FLASH_IRQHandler               [WEAK]
                 EXPORT  RCC_CRS_IRQHandler             [WEAK]
                 EXPORT  EXTI0_1_IRQHandler             [WEAK]
                 EXPORT  EXTI2_3_IRQHandler             [WEAK]
                 EXPORT  EXTI4_15_IRQHandler            [WEAK]
                 EXPORT  TSC_IRQHandler                  [WEAK]
                 EXPORT  DMA1_Ch1_IRQHandler              [WEAK]
                 EXPORT  DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler [WEAK]
                 EXPORT  DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler [WEAK]
                 EXPORT  ADC1_COMP_IRQHandler             [WEAK]
                 EXPORT  TIM1_BRK_UP_TRG_COM_IRQHandler   [WEAK]
                 EXPORT  TIM1_CC_IRQHandler               [WEAK]
                 EXPORT  TIM2_IRQHandler                  [WEAK]
                 EXPORT  TIM3_IRQHandler                  [WEAK]
                 EXPORT  TIM6_DAC_IRQHandler              [WEAK]
                 EXPORT  TIM7_IRQHandler                  [WEAK]
                 EXPORT  TIM14_IRQHandler                 [WEAK]
                 EXPORT  TIM15_IRQHandler                 [WEAK]
                 EXPORT  TIM16_IRQHandler                 [WEAK]
                 EXPORT  TIM17_IRQHandler                 [WEAK]
                 EXPORT  I2C1_IRQHandler                  [WEAK]
                 EXPORT  I2C2_IRQHandler                  [WEAK]
                 EXPORT  SPI1_IRQHandler                [WEAK]
                 EXPORT  SPI2_IRQHandler                [WEAK]
                 EXPORT  USART1_IRQHandler              [WEAK]
                 EXPORT  USART2_IRQHandler              [WEAK]
                 EXPORT  USART3_8_IRQHandler            [WEAK]
                 EXPORT  CEC_CAN_IRQHandler             [WEAK]
 WWDG_IRQHandler
 PVD_VDDIO2_IRQHandler
 RTC_IRQHandler
 FLASH_IRQHandler
 RCC_CRS_IRQHandler
 EXTI0_1_IRQHandler
 EXTI2_3_IRQHandler
 EXTI4_15_IRQHandler
 TSC_IRQHandler
 DMA1_Ch1_IRQHandler
 DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
 DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
 ADC1_COMP_IRQHandler
 TIM1_BRK_UP_TRG_COM_IRQHandler
 TIM1_CC_IRQHandler
 TIM2_IRQHandler
 TIM3_IRQHandler
 TIM6_DAC_IRQHandler
 TIM7_IRQHandler
 TIM14_IRQHandler
 TIM15_IRQHandler
 TIM16_IRQHandler
 TIM17_IRQHandler
 I2C1_IRQHandler
 I2C2_IRQHandler
 SPI1_IRQHandler
 SPI2_IRQHandler
 USART1_IRQHandler
 USART2_IRQHandler
 USART3_8_IRQHandler
 CEC_CAN_IRQHandler
                 B       .
                 ENDP
                 ALIGN
 ;*******************************************************************************
 ; User Stack and Heap initialization
 ;*******************************************************************************
                  IF      :DEF:__MICROLIB
                  EXPORT  __initial_sp
                  EXPORT  __heap_base
                  EXPORT  __heap_limit
                  ELSE
                  IMPORT  __use_two_region_memory
                  EXPORT  __user_initial_stackheap
 __user_initial_stackheap
                  LDR     R0, =  Heap_Mem
                  LDR     R1, =(Stack_Mem + Stack_Size)
                  LDR     R2, = (Heap_Mem +  Heap_Size)
                  LDR     R3, = Stack_Mem
                  BX      LR
                  ALIGN
                  ENDIF
                  END
 ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f0xx.s

➞

Show inline comments

@@ new file 100644 @@
 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
 ;* File Name          : startup_stm32f0xx.s
 ;* Author             : MCD Application Team
 ;* Version            : V1.4.0
 ;* Date               : 24-July-2014
 ;* Description        : STM32F051 devices vector table for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
 ;*                      - Set the initial PC == Reset_Handler
 ;*                      - Set the vector table entries with the exceptions ISR address
 ;*                      - Configure the system clock
 ;*                      - Branches to __main in the C library (which eventually
 ;*                        calls main()).
 ;*                      After Reset the CortexM0 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;* <<< Use Configuration Wizard in Context Menu >>>
 ;*******************************************************************************
 ;  @attention
+;
 ;  Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 ;  You may not use this file except in compliance with the License.
 ;  You may obtain a copy of the License at:
+;
 ;         http://www.st.com/software_license_agreement_liberty_v2
+;
 ;  Unless required by applicable law or agreed to in writing, software
 ;  distributed under the License is distributed on an "AS IS" BASIS,
 ;  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 ;  See the License for the specific language governing permissions and
 ;  limitations under the License.
+;
 ;*******************************************************************************
+;
 ; Amount of memory (in bytes) allocated for Stack
 ; Tailor this value to your application needs
 ; <h> Stack Configuration
 ;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
 ; </h>
 Stack_Size      EQU     0x00000400
                 AREA    STACK, NOINIT, READWRITE, ALIGN=3
 Stack_Mem       SPACE   Stack_Size
 __initial_sp
 ; <h> Heap Configuration
 ;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
 ; </h>
 Heap_Size       EQU     0x00000200
                 AREA    HEAP, NOINIT, READWRITE, ALIGN=3
 __heap_base
 Heap_Mem        SPACE   Heap_Size
 __heap_limit
                 PRESERVE8
                 THUMB
 ; Vector Table Mapped to Address 0 at Reset
                 AREA    RESET, DATA, READONLY
                 EXPORT  __Vectors
                 EXPORT  __Vectors_End
                 EXPORT  __Vectors_Size
 __Vectors       DCD     __initial_sp                   ; Top of Stack
                 DCD     Reset_Handler                  ; Reset Handler
                 DCD     NMI_Handler                    ; NMI Handler
                 DCD     HardFault_Handler              ; Hard Fault Handler
                 DCD     0                              ; Reserved
                 DCD     0                              ; Reserved
                 DCD     0                              ; Reserved
                 DCD     0                              ; Reserved
                 DCD     0                              ; Reserved
                 DCD     0                              ; Reserved
                 DCD     0                              ; Reserved
                 DCD     SVC_Handler                    ; SVCall Handler
                 DCD     0                              ; Reserved
                 DCD     0                              ; Reserved
                 DCD     PendSV_Handler                 ; PendSV Handler
                 DCD     SysTick_Handler                ; SysTick Handler
                 ; External Interrupts
                 DCD     WWDG_IRQHandler                ; Window Watchdog
                 DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
                 DCD     RTC_IRQHandler                 ; RTC through EXTI Line
                 DCD     FLASH_IRQHandler               ; FLASH
                 DCD     RCC_IRQHandler                 ; RCC
                 DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
                 DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
                 DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
                 DCD     TS_IRQHandler                  ; TS
                 DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
                 DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
                 DCD     DMA1_Channel4_5_IRQHandler     ; DMA1 Channel 4 and Channel 5
                 DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2
                 DCD     TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
                 DCD     TIM1_CC_IRQHandler             ; TIM1 Capture Compare
                 DCD     TIM2_IRQHandler                ; TIM2
                 DCD     TIM3_IRQHandler                ; TIM3
                 DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
                 DCD     0                              ; Reserved
                 DCD     TIM14_IRQHandler               ; TIM14
                 DCD     TIM15_IRQHandler               ; TIM15
                 DCD     TIM16_IRQHandler               ; TIM16
                 DCD     TIM17_IRQHandler               ; TIM17
                 DCD     I2C1_IRQHandler                ; I2C1
                 DCD     I2C2_IRQHandler                ; I2C2
                 DCD     SPI1_IRQHandler                ; SPI1
                 DCD     SPI2_IRQHandler                ; SPI2
                 DCD     USART1_IRQHandler              ; USART1
                 DCD     USART2_IRQHandler              ; USART2
                 DCD     0                              ; Reserved
                 DCD     CEC_IRQHandler                 ; CEC
                 DCD     0                              ; Reserved
 __Vectors_End
 __Vectors_Size  EQU  __Vectors_End - __Vectors
                 AREA    |.text|, CODE, READONLY
 ; Reset handler routine
 Reset_Handler    PROC
                  EXPORT  Reset_Handler                 [WEAK]
         IMPORT  __main
         IMPORT  SystemInit
         LDR     R0, =__initial_sp          ; set stack pointer
         MSR     MSP, R0
 ;;Check if boot space corresponds to test memory
         LDR R0,=0x00000004
         LDR R1, [R0]
         LSRS R1, R1, #24
         LDR R2,=0x1F
         CMP R1, R2
         BNE ApplicationStart
 ;; SYSCFG clock enable
         LDR R0,=0x40021018
         LDR R1,=0x00000001
         STR R1, [R0]
 ;; Set CFGR1 register with flash memory remap at address 0
         LDR R0,=0x40010000
         LDR R1,=0x00000000
         STR R1, [R0]
 ApplicationStart
                  LDR     R0, =SystemInit
                  BLX     R0
                  LDR     R0, =__main
                  BX      R0
                  ENDP
 ; Dummy Exception Handlers (infinite loops which can be modified)
 NMI_Handler     PROC
                 EXPORT  NMI_Handler                    [WEAK]
                 B       .
                 ENDP
 HardFault_Handler\
                 PROC
                 EXPORT  HardFault_Handler              [WEAK]
                 B       .
                 ENDP
 SVC_Handler     PROC
                 EXPORT  SVC_Handler                    [WEAK]
                 B       .
                 ENDP
 PendSV_Handler  PROC
                 EXPORT  PendSV_Handler                 [WEAK]
                 B       .
                 ENDP
 SysTick_Handler PROC
                 EXPORT  SysTick_Handler                [WEAK]
                 B       .
                 ENDP
 Default_Handler PROC
                 EXPORT  WWDG_IRQHandler                [WEAK]
                 EXPORT  PVD_IRQHandler                 [WEAK]
                 EXPORT  RTC_IRQHandler                 [WEAK]
                 EXPORT  FLASH_IRQHandler               [WEAK]
                 EXPORT  RCC_IRQHandler                 [WEAK]
                 EXPORT  EXTI0_1_IRQHandler             [WEAK]
                 EXPORT  EXTI2_3_IRQHandler             [WEAK]
                 EXPORT  EXTI4_15_IRQHandler            [WEAK]
                 EXPORT  TS_IRQHandler                  [WEAK]
                 EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
                 EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
                 EXPORT  DMA1_Channel4_5_IRQHandler     [WEAK]
                 EXPORT  ADC1_COMP_IRQHandler           [WEAK]
                 EXPORT  TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
                 EXPORT  TIM1_CC_IRQHandler             [WEAK]
                 EXPORT  TIM2_IRQHandler                [WEAK]
                 EXPORT  TIM3_IRQHandler                [WEAK]
                 EXPORT  TIM6_DAC_IRQHandler            [WEAK]
                 EXPORT  TIM14_IRQHandler               [WEAK]
                 EXPORT  TIM15_IRQHandler               [WEAK]
                 EXPORT  TIM16_IRQHandler               [WEAK]
                 EXPORT  TIM17_IRQHandler               [WEAK]
                 EXPORT  I2C1_IRQHandler                [WEAK]
                 EXPORT  I2C2_IRQHandler                [WEAK]
                 EXPORT  SPI1_IRQHandler                [WEAK]
                 EXPORT  SPI2_IRQHandler                [WEAK]
                 EXPORT  USART1_IRQHandler              [WEAK]
                 EXPORT  USART2_IRQHandler              [WEAK]
                 EXPORT  CEC_IRQHandler                 [WEAK]
 WWDG_IRQHandler
 PVD_IRQHandler
 RTC_IRQHandler
 FLASH_IRQHandler
 RCC_IRQHandler
 EXTI0_1_IRQHandler
 EXTI2_3_IRQHandler
 EXTI4_15_IRQHandler
 TS_IRQHandler
 DMA1_Channel1_IRQHandler
 DMA1_Channel2_3_IRQHandler
 DMA1_Channel4_5_IRQHandler
 ADC1_COMP_IRQHandler
 TIM1_BRK_UP_TRG_COM_IRQHandler
 TIM1_CC_IRQHandler
 TIM2_IRQHandler
 TIM3_IRQHandler
 TIM6_DAC_IRQHandler
 TIM14_IRQHandler
 TIM15_IRQHandler
 TIM16_IRQHandler
 TIM17_IRQHandler
 I2C1_IRQHandler
 I2C2_IRQHandler
 SPI1_IRQHandler
 SPI2_IRQHandler
 USART1_IRQHandler
 USART2_IRQHandler
 CEC_IRQHandler
                 B       .
                 ENDP
                 ALIGN
 ;*******************************************************************************
 ; User Stack and Heap initialization
 ;*******************************************************************************
                  IF      :DEF:__MICROLIB
                  EXPORT  __initial_sp
                  EXPORT  __heap_base
                  EXPORT  __heap_limit
                  ELSE
                  IMPORT  __use_two_region_memory
                  EXPORT  __user_initial_stackheap
 __user_initial_stackheap
                  LDR     R0, =  Heap_Mem
                  LDR     R1, =(Stack_Mem + Stack_Size)
                  LDR     R2, = (Heap_Mem +  Heap_Size)
                  LDR     R3, = Stack_Mem
                  BX      LR
                  ALIGN
                  ENDIF
                  END
 ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f0xx_ld.s

➞

Show inline comments

@@ new file 100644 @@
 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
 ;* File Name          : startup_stm32f0xx_ld.s
 ;* Author             : MCD Application Team
 ;* Version            : V1.4.0
 ;* Date               : 24-July-2014
 ;* Description        : STM32F031 devices vector table for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
 ;*                      - Set the initial PC == Reset_Handler
 ;*                      - Set the vector table entries with the exceptions ISR address
 ;*                      - Configure the system clock
 ;*                      - Branches to __main in the C library (which eventually
 ;*                        calls main()).
 ;*                      After Reset the CortexM0 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;* <<< Use Configuration Wizard in Context Menu >>>
 ;*******************************************************************************
 ;  @attention
+;
 ;  Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 ;  You may not use this file except in compliance with the License.
 ;  You may obtain a copy of the License at:
+;
 ;         http://www.st.com/software_license_agreement_liberty_v2
+;
 ;  Unless required by applicable law or agreed to in writing, software
 ;  distributed under the License is distributed on an "AS IS" BASIS,
 ;  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 ;  See the License for the specific language governing permissions and
 ;  limitations under the License.
+;
 ;*******************************************************************************
+;
 ; Amount of memory (in bytes) allocated for Stack
 ; Tailor this value to your application needs
 ; <h> Stack Configuration
 ;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
 ; </h>
 Stack_Size      EQU     0x00000400
                 AREA    STACK, NOINIT, READWRITE, ALIGN=3
 Stack_Mem       SPACE   Stack_Size
 __initial_sp
 ; <h> Heap Configuration
 ;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
 ; </h>
 Heap_Size       EQU     0x00000200
                 AREA    HEAP, NOINIT, READWRITE, ALIGN=3
 __heap_base
 Heap_Mem        SPACE   Heap_Size
 __heap_limit
                 PRESERVE8
                 THUMB
 ; Vector Table Mapped to Address 0 at Reset
                 AREA    RESET, DATA, READONLY
                 EXPORT  __Vectors
                 EXPORT  __Vectors_End
                 EXPORT  __Vectors_Size
 __Vectors       DCD     __initial_sp                   ; Top of Stack
                 DCD     Reset_Handler                  ; Reset Handler
                 DCD     NMI_Handler                    ; NMI Handler
                 DCD     HardFault_Handler              ; Hard Fault Handler
                 DCD     0                              ; Reserved
                 DCD     0                              ; Reserved
                 DCD     0                              ; Reserved
                 DCD     0                              ; Reserved
                 DCD     0                              ; Reserved
                 DCD     0                              ; Reserved
                 DCD     0                              ; Reserved
                 DCD     SVC_Handler                    ; SVCall Handler
                 DCD     0                              ; Reserved
                 DCD     0                              ; Reserved
                 DCD     PendSV_Handler                 ; PendSV Handler
                 DCD     SysTick_Handler                ; SysTick Handler
                 ; External Interrupts
                 DCD     WWDG_IRQHandler                ; Window Watchdog
                 DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
                 DCD     RTC_IRQHandler                 ; RTC through EXTI Line
                 DCD     FLASH_IRQHandler               ; FLASH
                 DCD     RCC_IRQHandler                 ; RCC
                 DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
                 DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
                 DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
                 DCD     0                              ; Reserved
                 DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
                 DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
                 DCD     DMA1_Channel4_5_IRQHandler     ; DMA1 Channel 4 and Channel 5
                 DCD     ADC1_IRQHandler                ; ADC1
                 DCD     TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
                 DCD     TIM1_CC_IRQHandler             ; TIM1 Capture Compare
                 DCD     TIM2_IRQHandler                ; TIM2
                 DCD     TIM3_IRQHandler                ; TIM3
                 DCD     0                              ; Reserved
                 DCD     0                              ; Reserved
                 DCD     TIM14_IRQHandler               ; TIM14
                 DCD     0                              ; Reserved
                 DCD     TIM16_IRQHandler               ; TIM16
                 DCD     TIM17_IRQHandler               ; TIM17
                 DCD     I2C1_IRQHandler                ; I2C1
                 DCD     0                              ; Reserved
                 DCD     SPI1_IRQHandler                ; SPI1
                 DCD     0                              ; Reserved
                 DCD     USART1_IRQHandler              ; USART1
 __Vectors_End
 __Vectors_Size  EQU  __Vectors_End - __Vectors
                 AREA    |.text|, CODE, READONLY
 ; Reset handler routine
 Reset_Handler    PROC
                  EXPORT  Reset_Handler                 [WEAK]
         IMPORT  __main
         IMPORT  SystemInit
         LDR     R0, =__initial_sp          ; set stack pointer
         MSR     MSP, R0
 ;;Check if boot space corresponds to test memory
         LDR R0,=0x00000004
         LDR R1, [R0]
         LSRS R1, R1, #24
         LDR R2,=0x1F
         CMP R1, R2
         BNE ApplicationStart
 ;; SYSCFG clock enable
         LDR R0,=0x40021018
         LDR R1,=0x00000001
         STR R1, [R0]
 ;; Set CFGR1 register with flash memory remap at address 0
         LDR R0,=0x40010000
         LDR R1,=0x00000000
         STR R1, [R0]
 ApplicationStart
                  LDR     R0, =SystemInit
                  BLX     R0
                  LDR     R0, =__main
                  BX      R0
                  ENDP
 ; Dummy Exception Handlers (infinite loops which can be modified)
 NMI_Handler     PROC
                 EXPORT  NMI_Handler                    [WEAK]
                 B       .
                 ENDP
 HardFault_Handler\
                 PROC
                 EXPORT  HardFault_Handler              [WEAK]
                 B       .
                 ENDP
 SVC_Handler     PROC
                 EXPORT  SVC_Handler                    [WEAK]
                 B       .
                 ENDP
 PendSV_Handler  PROC
                 EXPORT  PendSV_Handler                 [WEAK]
                 B       .
                 ENDP
 SysTick_Handler PROC
                 EXPORT  SysTick_Handler                [WEAK]
                 B       .
                 ENDP
 Default_Handler PROC
                 EXPORT  WWDG_IRQHandler                [WEAK]
                 EXPORT  PVD_IRQHandler                 [WEAK]
                 EXPORT  RTC_IRQHandler                 [WEAK]
                 EXPORT  FLASH_IRQHandler               [WEAK]
                 EXPORT  RCC_IRQHandler                 [WEAK]
                 EXPORT  EXTI0_1_IRQHandler             [WEAK]
                 EXPORT  EXTI2_3_IRQHandler             [WEAK]
                 EXPORT  EXTI4_15_IRQHandler            [WEAK]
                 EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
                 EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
                 EXPORT  DMA1_Channel4_5_IRQHandler     [WEAK]
                 EXPORT  ADC1_IRQHandler                [WEAK]
                 EXPORT  TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
                 EXPORT  TIM1_CC_IRQHandler             [WEAK]
                 EXPORT  TIM2_IRQHandler                [WEAK]
                 EXPORT  TIM3_IRQHandler                [WEAK]
                 EXPORT  TIM14_IRQHandler               [WEAK]
                 EXPORT  TIM16_IRQHandler               [WEAK]
                 EXPORT  TIM17_IRQHandler               [WEAK]
                 EXPORT  I2C1_IRQHandler                [WEAK]
                 EXPORT  SPI1_IRQHandler                [WEAK]
                 EXPORT  USART1_IRQHandler              [WEAK]
 WWDG_IRQHandler
 PVD_IRQHandler
 RTC_IRQHandler
 FLASH_IRQHandler
 RCC_IRQHandler
 EXTI0_1_IRQHandler
 EXTI2_3_IRQHandler
 EXTI4_15_IRQHandler
 DMA1_Channel1_IRQHandler
 DMA1_Channel2_3_IRQHandler
 DMA1_Channel4_5_IRQHandler
 ADC1_IRQHandler
 TIM1_BRK_UP_TRG_COM_IRQHandler
 TIM1_CC_IRQHandler
 TIM2_IRQHandler
 TIM3_IRQHandler
 TIM14_IRQHandler
 TIM16_IRQHandler
 TIM17_IRQHandler
 I2C1_IRQHandler
 SPI1_IRQHandler
 USART1_IRQHandler
                 B       .
                 ENDP
                 ALIGN
 ;*******************************************************************************
 ; User Stack and Heap initialization
 ;*******************************************************************************
                  IF      :DEF:__MICROLIB
                  EXPORT  __initial_sp
                  EXPORT  __heap_base
                  EXPORT  __heap_limit
                  ELSE
                  IMPORT  __use_two_region_memory
                  EXPORT  __user_initial_stackheap
 __user_initial_stackheap
                  LDR     R0, =  Heap_Mem
                  LDR     R1, =(Stack_Mem + Stack_Size)
                  LDR     R2, = (Heap_Mem +  Heap_Size)
                  LDR     R3, = Stack_Mem
                  BX      LR
                  ALIGN
                  ENDIF
                  END
 ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f030.s

➞

Show inline comments

@@ new file 100644 @@
 /**
   ******************************************************************************
   * @file      startup_stm32f0xx.s
   * @author    MCD Application Team
   * @version   V1.4.0
   * @date      24-July-2014
   * @brief     STM32F030 Devices vector table for RIDE7 toolchain.
   *            This module performs:
   *                - Set the initial SP
   *                - Set the initial PC == Reset_Handler,
   *                - Set the vector table entries with the exceptions ISR address
   *                - Configure the system clock
   *                - Branches to main in the C library (which eventually
   *                  calls main()).
   *            After Reset the Cortex-M0 processor is in Thread mode,
   *            priority is Privileged, and the Stack is set to Main.
   ******************************************************************************
   * @attention
+  *
   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
   * You may not use this file except in compliance with the License.
   * You may obtain a copy of the License at:
+  *
   *        http://www.st.com/software_license_agreement_liberty_v2
+  *
   * Unless required by applicable law or agreed to in writing, software
   * distributed under the License is distributed on an "AS IS" BASIS,
   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
   * See the License for the specific language governing permissions and
   * limitations under the License.
+  *
   ******************************************************************************
   */
   .syntax unified
   .cpu cortex-m0
   .fpu softvfp
   .thumb
 .global g_pfnVectors
 .global Default_Handler
 /* start address for the initialization values of the .data section.
 defined in linker script */
 .word _sidata
 /* start address for the .data section. defined in linker script */
 .word _sdata
 /* end address for the .data section. defined in linker script */
 .word _edata
 /* start address for the .bss section. defined in linker script */
 .word _sbss
 /* end address for the .bss section. defined in linker script */
 .word _ebss
 .equ  BootRAM, 0xF108F85F
 /**
  * @brief  This is the code that gets called when the processor first
  *          starts execution following a reset event. Only the absolutely
  *          necessary set is performed, after which the application
  *          supplied main() routine is called.
  * @param  None
  * @retval : None
 */
   .section .text.Reset_Handler
   .weak Reset_Handler
   .type Reset_Handler, %function
 Reset_Handler:
   ldr   r0, =_estack
   mov   sp, r0          /* set stack pointer */
 /*Check if boot space corresponds to test memory*/
     LDR R0,=0x00000004
     LDR R1, [R0]
     LSRS R1, R1, #24
     LDR R2,=0x1F
     CMP R1, R2
     BNE ApplicationStart
  /*SYSCFG clock enable*/
     LDR R0,=0x40021018
     LDR R1,=0x00000001
     STR R1, [R0]
 /*Set CFGR1 register with flash memory remap at address 0*/
     LDR R0,=0x40010000
     LDR R1,=0x00000000
     STR R1, [R0]
 ApplicationStart:
 /* Copy the data segment initializers from flash to SRAM */
   movs r1, #0
   b LoopCopyDataInit
 CopyDataInit:
   ldr r3, =_sidata
   ldr r3, [r3, r1]
   str r3, [r0, r1]
   adds r1, r1, #4
 LoopCopyDataInit:
   ldr r0, =_sdata
   ldr r3, =_edata
   adds r2, r0, r1
   cmp r2, r3
   bcc CopyDataInit
   ldr r2, =_sbss
   b LoopFillZerobss
 /* Zero fill the bss segment. */
 FillZerobss:
   movs r3, #0
   str  r3, [r2]
   adds r2, r2, #4
 LoopFillZerobss:
   ldr r3, = _ebss
   cmp r2, r3
   bcc FillZerobss
 /* Call the clock system intitialization function.*/
     bl  SystemInit
 /* Call the application's entry point.*/
   bl main
 LoopForever:
     b LoopForever
 .size Reset_Handler, .-Reset_Handler
 /**
  * @brief  This is the code that gets called when the processor receives an
  *         unexpected interrupt.  This simply enters an infinite loop, preserving
  *         the system state for examination by a debugger.
+ *
  * @param  None
  * @retval : None
 */
     .section .text.Default_Handler,"ax",%progbits
 Default_Handler:
 Infinite_Loop:
   b Infinite_Loop
   .size Default_Handler, .-Default_Handler
 /******************************************************************************
+*
 * The minimal vector table for a Cortex M0.  Note that the proper constructs
 * must be placed on this to ensure that it ends up at physical address
 * 0x0000.0000.
+*
 ******************************************************************************/
    .section .isr_vector,"a",%progbits
   .type g_pfnVectors, %object
   .size g_pfnVectors, .-g_pfnVectors
 g_pfnVectors:
   .word _estack
   .word Reset_Handler
   .word NMI_Handler
   .word HardFault_Handler
   .word 0
   .word 0
   .word 0
   .word 0
   .word 0
   .word 0
   .word 0
   .word SVC_Handler
   .word 0
   .word 0
   .word PendSV_Handler
   .word SysTick_Handler
   .word WWDG_IRQHandler
   .word 0
   .word RTC_IRQHandler
   .word FLASH_IRQHandler
   .word RCC_IRQHandler
   .word EXTI0_1_IRQHandler
   .word EXTI2_3_IRQHandler
   .word EXTI4_15_IRQHandler
   .word 0
   .word DMA1_Channel1_IRQHandler
   .word DMA1_Channel2_3_IRQHandler
   .word DMA1_Channel4_5_IRQHandler
   .word ADC1_IRQHandler
   .word TIM1_BRK_UP_TRG_COM_IRQHandler
   .word TIM1_CC_IRQHandler
   .word 0
   .word TIM3_IRQHandler
   .word 0
   .word 0
   .word TIM14_IRQHandler
   .word TIM15_IRQHandler
   .word TIM16_IRQHandler
   .word TIM17_IRQHandler
   .word I2C1_IRQHandler
   .word I2C2_IRQHandler
   .word SPI1_IRQHandler
   .word SPI2_IRQHandler
   .word USART1_IRQHandler
   .word USART2_IRQHandler
   .word 0
   .word 0
   .word 0
   .word BootRAM          /* @0x108. This is for boot in RAM mode for
                             STM32F0xx devices. */
 /*******************************************************************************
+*
 * Provide weak aliases for each Exception handler to the Default_Handler.
 * As they are weak aliases, any function with the same name will override
 * this definition.
+*
 *******************************************************************************/
   .weak NMI_Handler
   .thumb_set NMI_Handler,Default_Handler
   .weak HardFault_Handler
   .thumb_set HardFault_Handler,Default_Handler
   .weak SVC_Handler
   .thumb_set SVC_Handler,Default_Handler
   .weak PendSV_Handler
   .thumb_set PendSV_Handler,Default_Handler
   .weak SysTick_Handler
   .thumb_set SysTick_Handler,Default_Handler
   .weak WWDG_IRQHandler
   .thumb_set WWDG_IRQHandler,Default_Handler
   .weak RTC_IRQHandler
   .thumb_set RTC_IRQHandler,Default_Handler
   .weak FLASH_IRQHandler
   .thumb_set FLASH_IRQHandler,Default_Handler
   .weak RCC_IRQHandler
   .thumb_set RCC_IRQHandler,Default_Handler
   .weak EXTI0_1_IRQHandler
   .thumb_set EXTI0_1_IRQHandler,Default_Handler
   .weak EXTI2_3_IRQHandler
   .thumb_set EXTI2_3_IRQHandler,Default_Handler
   .weak EXTI4_15_IRQHandler
   .thumb_set EXTI4_15_IRQHandler,Default_Handler
   .weak DMA1_Channel1_IRQHandler
   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
   .weak DMA1_Channel2_3_IRQHandler
   .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
   .weak DMA1_Channel4_5_IRQHandler
   .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
   .weak ADC1_IRQHandler
   .thumb_set ADC1_IRQHandler,Default_Handler
   .weak TIM1_BRK_UP_TRG_COM_IRQHandler
   .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
   .weak TIM1_CC_IRQHandler
   .thumb_set TIM1_CC_IRQHandler,Default_Handler
   .weak TIM3_IRQHandler
   .thumb_set TIM3_IRQHandler,Default_Handler
   .weak TIM14_IRQHandler
   .thumb_set TIM14_IRQHandler,Default_Handler
   .weak TIM15_IRQHandler
   .thumb_set TIM15_IRQHandler,Default_Handler
   .weak TIM16_IRQHandler
   .thumb_set TIM16_IRQHandler,Default_Handler
   .weak TIM17_IRQHandler
   .thumb_set TIM17_IRQHandler,Default_Handler
   .weak I2C1_IRQHandler
   .thumb_set I2C1_IRQHandler,Default_Handler
   .weak I2C2_IRQHandler
   .thumb_set I2C2_IRQHandler,Default_Handler
   .weak SPI1_IRQHandler
   .thumb_set SPI1_IRQHandler,Default_Handler
   .weak SPI2_IRQHandler
   .thumb_set SPI2_IRQHandler,Default_Handler
   .weak USART1_IRQHandler
   .thumb_set USART1_IRQHandler,Default_Handler
   .weak USART2_IRQHandler
   .thumb_set USART2_IRQHandler,Default_Handler
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f031.s

➞

Show inline comments

@@ new file 100644 @@
 /**
   ******************************************************************************
   * @file      startup_stm32f0xx.s
   * @author    MCD Application Team
   * @version   V1.4.0
   * @date      24-July-2014
   * @brief     STM32F031 Devices vector table for RIDE7 toolchain.
   *            This module performs:
   *                - Set the initial SP
   *                - Set the initial PC == Reset_Handler,
   *                - Set the vector table entries with the exceptions ISR address
   *                - Configure the system clock
   *                - Branches to main in the C library (which eventually
   *                  calls main()).
   *            After Reset the Cortex-M0 processor is in Thread mode,
   *            priority is Privileged, and the Stack is set to Main.
   ******************************************************************************
   * @attention
+  *
   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
   * You may not use this file except in compliance with the License.
   * You may obtain a copy of the License at:
+  *
   *        http://www.st.com/software_license_agreement_liberty_v2
+  *
   * Unless required by applicable law or agreed to in writing, software
   * distributed under the License is distributed on an "AS IS" BASIS,
   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
   * See the License for the specific language governing permissions and
   * limitations under the License.
+  *
   ******************************************************************************
   */
   .syntax unified
   .cpu cortex-m0
   .fpu softvfp
   .thumb
 .global g_pfnVectors
 .global Default_Handler
 /* start address for the initialization values of the .data section.
 defined in linker script */
 .word _sidata
 /* start address for the .data section. defined in linker script */
 .word _sdata
 /* end address for the .data section. defined in linker script */
 .word _edata
 /* start address for the .bss section. defined in linker script */
 .word _sbss
 /* end address for the .bss section. defined in linker script */
 .word _ebss
 .equ  BootRAM, 0xF108F85F
 /**
  * @brief  This is the code that gets called when the processor first
  *          starts execution following a reset event. Only the absolutely
  *          necessary set is performed, after which the application
  *          supplied main() routine is called.
  * @param  None
  * @retval : None
 */
   .section .text.Reset_Handler
   .weak Reset_Handler
   .type Reset_Handler, %function
 Reset_Handler:
   ldr   r0, =_estack
   mov   sp, r0          /* set stack pointer */
 /*Check if boot space corresponds to test memory*/
     LDR R0,=0x00000004
     LDR R1, [R0]
     LSRS R1, R1, #24
     LDR R2,=0x1F
     CMP R1, R2
     BNE ApplicationStart
  /*SYSCFG clock enable*/
     LDR R0,=0x40021018
     LDR R1,=0x00000001
     STR R1, [R0]
 /*Set CFGR1 register with flash memory remap at address 0*/
     LDR R0,=0x40010000
     LDR R1,=0x00000000
     STR R1, [R0]
 ApplicationStart:
 /* Copy the data segment initializers from flash to SRAM */
   movs r1, #0
   b LoopCopyDataInit
 CopyDataInit:
   ldr r3, =_sidata
   ldr r3, [r3, r1]
   str r3, [r0, r1]
   adds r1, r1, #4
 LoopCopyDataInit:
   ldr r0, =_sdata
   ldr r3, =_edata
   adds r2, r0, r1
   cmp r2, r3
   bcc CopyDataInit
   ldr r2, =_sbss
   b LoopFillZerobss
 /* Zero fill the bss segment. */
 FillZerobss:
   movs r3, #0
   str  r3, [r2]
   adds r2, r2, #4
 LoopFillZerobss:
   ldr r3, = _ebss
   cmp r2, r3
   bcc FillZerobss
 /* Call the clock system intitialization function.*/
     bl  SystemInit
 /* Call the application's entry point.*/
   bl main
 LoopForever:
     b LoopForever
 .size Reset_Handler, .-Reset_Handler
 /**
  * @brief  This is the code that gets called when the processor receives an
  *         unexpected interrupt.  This simply enters an infinite loop, preserving
  *         the system state for examination by a debugger.
+ *
  * @param  None
  * @retval : None
 */
     .section .text.Default_Handler,"ax",%progbits
 Default_Handler:
 Infinite_Loop:
   b Infinite_Loop
   .size Default_Handler, .-Default_Handler
 /******************************************************************************
+*
 * The minimal vector table for a Cortex M0.  Note that the proper constructs
 * must be placed on this to ensure that it ends up at physical address
 * 0x0000.0000.
+*
 ******************************************************************************/
    .section .isr_vector,"a",%progbits
   .type g_pfnVectors, %object
   .size g_pfnVectors, .-g_pfnVectors
 g_pfnVectors:
   .word _estack
   .word Reset_Handler
   .word NMI_Handler
   .word HardFault_Handler
   .word 0
   .word 0
   .word 0
   .word 0
   .word 0
   .word 0
   .word 0
   .word SVC_Handler
   .word 0
   .word 0
   .word PendSV_Handler
   .word SysTick_Handler
   .word WWDG_IRQHandler
   .word PVD_IRQHandler
   .word RTC_IRQHandler
   .word FLASH_IRQHandler
   .word RCC_IRQHandler
   .word EXTI0_1_IRQHandler
   .word EXTI2_3_IRQHandler
   .word EXTI4_15_IRQHandler
   .word 0
   .word DMA1_Channel1_IRQHandler
   .word DMA1_Channel2_3_IRQHandler
   .word DMA1_Channel4_5_IRQHandler
   .word ADC1_IRQHandler
   .word TIM1_BRK_UP_TRG_COM_IRQHandler
   .word TIM1_CC_IRQHandler
   .word TIM2_IRQHandler
   .word TIM3_IRQHandler
   .word 0
   .word 0
   .word TIM14_IRQHandler
   .word 0
   .word TIM16_IRQHandler
   .word TIM17_IRQHandler
   .word I2C1_IRQHandler
   .word 0
   .word SPI1_IRQHandler
   .word 0
   .word USART1_IRQHandler
   .word 0
   .word 0
   .word 0
   .word 0
   .word BootRAM          /* @0x108. This is for boot in RAM mode for
                             STM32F0xx devices. */
 /*******************************************************************************
+*
 * Provide weak aliases for each Exception handler to the Default_Handler.
 * As they are weak aliases, any function with the same name will override
 * this definition.
+*
 *******************************************************************************/
   .weak NMI_Handler
   .thumb_set NMI_Handler,Default_Handler
   .weak HardFault_Handler
   .thumb_set HardFault_Handler,Default_Handler
   .weak SVC_Handler
   .thumb_set SVC_Handler,Default_Handler
   .weak PendSV_Handler
   .thumb_set PendSV_Handler,Default_Handler
   .weak SysTick_Handler
   .thumb_set SysTick_Handler,Default_Handler
   .weak WWDG_IRQHandler
   .thumb_set WWDG_IRQHandler,Default_Handler
   .weak PVD_IRQHandler
   .thumb_set PVD_IRQHandler,Default_Handler
   .weak RTC_IRQHandler
   .thumb_set RTC_IRQHandler,Default_Handler
   .weak FLASH_IRQHandler
   .thumb_set FLASH_IRQHandler,Default_Handler
   .weak RCC_IRQHandler
   .thumb_set RCC_IRQHandler,Default_Handler
   .weak EXTI0_1_IRQHandler
   .thumb_set EXTI0_1_IRQHandler,Default_Handler
   .weak EXTI2_3_IRQHandler
   .thumb_set EXTI2_3_IRQHandler,Default_Handler
   .weak EXTI4_15_IRQHandler
   .thumb_set EXTI4_15_IRQHandler,Default_Handler
   .weak DMA1_Channel1_IRQHandler
   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
   .weak DMA1_Channel2_3_IRQHandler
   .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
   .weak DMA1_Channel4_5_IRQHandler
   .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
   .weak ADC1_IRQHandler
   .thumb_set ADC1_IRQHandler,Default_Handler
   .weak TIM1_BRK_UP_TRG_COM_IRQHandler
   .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
   .weak TIM1_CC_IRQHandler
   .thumb_set TIM1_CC_IRQHandler,Default_Handler
   .weak TIM2_IRQHandler
   .thumb_set TIM2_IRQHandler,Default_Handler
   .weak TIM3_IRQHandler
   .thumb_set TIM3_IRQHandler,Default_Handler
   .weak TIM14_IRQHandler
   .thumb_set TIM14_IRQHandler,Default_Handler
   .weak TIM16_IRQHandler
   .thumb_set TIM16_IRQHandler,Default_Handler
   .weak TIM17_IRQHandler
   .thumb_set TIM17_IRQHandler,Default_Handler
   .weak I2C1_IRQHandler
   .thumb_set I2C1_IRQHandler,Default_Handler
   .weak SPI1_IRQHandler
   .thumb_set SPI1_IRQHandler,Default_Handler
   .weak USART1_IRQHandler
   .thumb_set USART1_IRQHandler,Default_Handler
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f042.s

➞

Show inline comments

@@ new file 100644 @@
 /**
   ******************************************************************************
   * @file      startup_stm32f042.s
   * @author    MCD Application Team
   * @version   V1.4.0
   * @date      24-July-2014
   * @brief     STM32F042 Devices vector table for Atollic toolchain.
   *            This module performs:
   *                - Set the initial SP
   *                - Set the initial PC == Reset_Handler,
   *                - Set the vector table entries with the exceptions ISR address
   *                - Configure the system clock
   *                - Branches to main in the C library (which eventually
   *                  calls main()).
   *            After Reset the Cortex-M0 processor is in Thread mode,
   *            priority is Privileged, and the Stack is set to Main.
   ******************************************************************************
   * @attention
+  *
   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
   * You may not use this file except in compliance with the License.
   * You may obtain a copy of the License at:
+  *
   *        http://www.st.com/software_license_agreement_liberty_v2
+  *
   * Unless required by applicable law or agreed to in writing, software
   * distributed under the License is distributed on an "AS IS" BASIS,
   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
   * See the License for the specific language governing permissions and
   * limitations under the License.
+  *
   ******************************************************************************
   */
   .syntax unified
   .cpu cortex-m0
   .fpu softvfp
   .thumb
 .global g_pfnVectors
 .global Default_Handler
 /* start address for the initialization values of the .data section.
 defined in linker script */
 .word _sidata
 /* start address for the .data section. defined in linker script */
 .word _sdata
 /* end address for the .data section. defined in linker script */
 .word _edata
 /* start address for the .bss section. defined in linker script */
 .word _sbss
 /* end address for the .bss section. defined in linker script */
 .word _ebss
 .equ  BootRAM, 0xF108F85F
 /**
  * @brief  This is the code that gets called when the processor first
  *          starts execution following a reset event. Only the absolutely
  *          necessary set is performed, after which the application
  *          supplied main() routine is called.
  * @param  None
  * @retval : None
 */
   .section .text.Reset_Handler
   .weak Reset_Handler
   .type Reset_Handler, %function
 Reset_Handler:
   ldr   r0, =_estack
   mov   sp, r0          /* set stack pointer */
 /*Check if boot space corresponds to test memory*/
     LDR R0,=0x00000004
     LDR R1, [R0]
     LSRS R1, R1, #24
     LDR R2,=0x1F
     CMP R1, R2
     BNE ApplicationStart
  /*SYSCFG clock enable*/
     LDR R0,=0x40021018
     LDR R1,=0x00000001
     STR R1, [R0]
 /*Set CFGR1 register with flash memory remap at address 0*/
     LDR R0,=0x40010000
     LDR R1,=0x00000000
     STR R1, [R0]
 ApplicationStart:
 /* Copy the data segment initializers from flash to SRAM */
   movs r1, #0
   b LoopCopyDataInit
 CopyDataInit:
   ldr r3, =_sidata
   ldr r3, [r3, r1]
   str r3, [r0, r1]
   adds r1, r1, #4
 LoopCopyDataInit:
   ldr r0, =_sdata
   ldr r3, =_edata
   adds r2, r0, r1
   cmp r2, r3
   bcc CopyDataInit
   ldr r2, =_sbss
   b LoopFillZerobss
 /* Zero fill the bss segment. */
 FillZerobss:
   movs r3, #0
   str  r3, [r2]
   adds r2, r2, #4
 LoopFillZerobss:
   ldr r3, = _ebss
   cmp r2, r3
   bcc FillZerobss
 /* Call the clock system intitialization function.*/
     bl  SystemInit
 /* Call static constructors */
     bl __libc_init_array
 /* Call the application's entry point.*/
   bl main
 LoopForever:
     b LoopForever
 .size Reset_Handler, .-Reset_Handler
 /**
  * @brief  This is the code that gets called when the processor receives an
  *         unexpected interrupt.  This simply enters an infinite loop, preserving
  *         the system state for examination by a debugger.
+ *
  * @param  None
  * @retval : None
 */
     .section .text.Default_Handler,"ax",%progbits
 Default_Handler:
 Infinite_Loop:
   b Infinite_Loop
   .size Default_Handler, .-Default_Handler
 /******************************************************************************
+*
 * The minimal vector table for a Cortex M0.  Note that the proper constructs
 * must be placed on this to ensure that it ends up at physical address
 * 0x0000.0000.
+*
 ******************************************************************************/
    .section .isr_vector,"a",%progbits
   .type g_pfnVectors, %object
   .size g_pfnVectors, .-g_pfnVectors
 g_pfnVectors:
   .word _estack
   .word Reset_Handler
   .word NMI_Handler
   .word HardFault_Handler
   .word 0
   .word 0
   .word 0
   .word 0
   .word 0
   .word 0
   .word 0
   .word SVC_Handler
   .word 0
   .word 0
   .word PendSV_Handler
   .word SysTick_Handler
   .word WWDG_IRQHandler
   .word PVD_VDDIO2_IRQHandler
   .word RTC_IRQHandler
   .word FLASH_IRQHandler
   .word RCC_CRS_IRQHandler
   .word EXTI0_1_IRQHandler
   .word EXTI2_3_IRQHandler
   .word EXTI4_15_IRQHandler
   .word TSC_IRQHandler
   .word DMA1_Channel1_IRQHandler
   .word DMA1_Channel2_3_IRQHandler
   .word DMA1_Channel4_5_IRQHandler
   .word ADC1_IRQHandler
   .word TIM1_BRK_UP_TRG_COM_IRQHandler
   .word TIM1_CC_IRQHandler
   .word TIM2_IRQHandler
   .word TIM3_IRQHandler
   .word 0
   .word 0
   .word TIM14_IRQHandler
   .word 0
   .word TIM16_IRQHandler
   .word TIM17_IRQHandler
   .word I2C1_IRQHandler
   .word 0
   .word SPI1_IRQHandler
   .word SPI2_IRQHandler
   .word USART1_IRQHandler
   .word USART2_IRQHandler
   .word 0
   .word CEC_CAN_IRQHandler
   .word USB_IRQHandler
   .word BootRAM          /* @0x108. This is for boot in RAM mode for
                             STM32F0xx devices. */
 /*******************************************************************************
+*
 * Provide weak aliases for each Exception handler to the Default_Handler.
 * As they are weak aliases, any function with the same name will override
 * this definition.
+*
 *******************************************************************************/
   .weak NMI_Handler
   .thumb_set NMI_Handler,Default_Handler
   .weak HardFault_Handler
   .thumb_set HardFault_Handler,Default_Handler
   .weak SVC_Handler
   .thumb_set SVC_Handler,Default_Handler
   .weak PendSV_Handler
   .thumb_set PendSV_Handler,Default_Handler
   .weak SysTick_Handler
   .thumb_set SysTick_Handler,Default_Handler
   .weak WWDG_IRQHandler
   .thumb_set WWDG_IRQHandler,Default_Handler
   .weak PVD_VDDIO2_IRQHandler
   .thumb_set PVD_VDDIO2_IRQHandler,Default_Handler
   .weak RTC_IRQHandler
   .thumb_set RTC_IRQHandler,Default_Handler
   .weak FLASH_IRQHandler
   .thumb_set FLASH_IRQHandler,Default_Handler
   .weak RCC_CRS_IRQHandler
   .thumb_set RCC_CRS_IRQHandler,Default_Handler
   .weak EXTI0_1_IRQHandler
   .thumb_set EXTI0_1_IRQHandler,Default_Handler
   .weak EXTI2_3_IRQHandler
   .thumb_set EXTI2_3_IRQHandler,Default_Handler
   .weak EXTI4_15_IRQHandler
   .thumb_set EXTI4_15_IRQHandler,Default_Handler
   .weak TSC_IRQHandler
   .thumb_set TSC_IRQHandler,Default_Handler
   .weak DMA1_Channel1_IRQHandler
   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
   .weak DMA1_Channel2_3_IRQHandler
   .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
   .weak DMA1_Channel4_5_IRQHandler
   .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
   .weak ADC1_IRQHandler
   .thumb_set ADC1_IRQHandler,Default_Handler
   .weak TIM1_BRK_UP_TRG_COM_IRQHandler
   .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
   .weak TIM1_CC_IRQHandler
   .thumb_set TIM1_CC_IRQHandler,Default_Handler
   .weak TIM2_IRQHandler
   .thumb_set TIM2_IRQHandler,Default_Handler
   .weak TIM3_IRQHandler
   .thumb_set TIM3_IRQHandler,Default_Handler
   .weak TIM14_IRQHandler
   .thumb_set TIM14_IRQHandler,Default_Handler
   .weak TIM16_IRQHandler
   .thumb_set TIM16_IRQHandler,Default_Handler
   .weak TIM17_IRQHandler
   .thumb_set TIM17_IRQHandler,Default_Handler
   .weak I2C1_IRQHandler
   .thumb_set I2C1_IRQHandler,Default_Handler
   .weak SPI1_IRQHandler
   .thumb_set SPI1_IRQHandler,Default_Handler
   .weak SPI2_IRQHandler
   .thumb_set SPI2_IRQHandler,Default_Handler
   .weak USART1_IRQHandler
   .thumb_set USART1_IRQHandler,Default_Handler
   .weak USART2_IRQHandler
   .thumb_set USART2_IRQHandler,Default_Handler
   .weak CEC_CAN_IRQHandler
   .thumb_set CEC_CAN_IRQHandler,Default_Handler
   .weak USB_IRQHandler
   .thumb_set USB_IRQHandler,Default_Handler
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f051.s

➞

Show inline comments

@@ new file 100644 @@
 /**
   ******************************************************************************
   * @file      startup_stm32f0xx.s
   * @author    MCD Application Team
   * @version   V1.4.0
   * @date      24-July-2014
   * @brief     STM32F051 Devices vector table for RIDE7 toolchain.
   *            This module performs:
   *                - Set the initial SP
   *                - Set the initial PC == Reset_Handler,
   *                - Set the vector table entries with the exceptions ISR address
   *                - Configure the system clock
   *                - Branches to main in the C library (which eventually
   *                  calls main()).
   *            After Reset the Cortex-M0 processor is in Thread mode,
   *            priority is Privileged, and the Stack is set to Main.
   ******************************************************************************
   * @attention
+  *
   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
   * You may not use this file except in compliance with the License.
   * You may obtain a copy of the License at:
+  *
   *        http://www.st.com/software_license_agreement_liberty_v2
+  *
   * Unless required by applicable law or agreed to in writing, software
   * distributed under the License is distributed on an "AS IS" BASIS,
   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
   * See the License for the specific language governing permissions and
   * limitations under the License.
+  *
   ******************************************************************************
   */
   .syntax unified
   .cpu cortex-m0
   .fpu softvfp
   .thumb
 .global g_pfnVectors
 .global Default_Handler
 /* start address for the initialization values of the .data section.
 defined in linker script */
 .word _sidata
 /* start address for the .data section. defined in linker script */
 .word _sdata
 /* end address for the .data section. defined in linker script */
 .word _edata
 /* start address for the .bss section. defined in linker script */
 .word _sbss
 /* end address for the .bss section. defined in linker script */
 .word _ebss
 .equ  BootRAM, 0xF108F85F
 /**
  * @brief  This is the code that gets called when the processor first
  *          starts execution following a reset event. Only the absolutely
  *          necessary set is performed, after which the application
  *          supplied main() routine is called.
  * @param  None
  * @retval : None
 */
   .section .text.Reset_Handler
   .weak Reset_Handler
   .type Reset_Handler, %function
 Reset_Handler:
   ldr   r0, =_estack
   mov   sp, r0          /* set stack pointer */
 /*Check if boot space corresponds to test memory*/
     LDR R0,=0x00000004
     LDR R1, [R0]
     LSRS R1, R1, #24
     LDR R2,=0x1F
     CMP R1, R2
     BNE ApplicationStart
  /*SYSCFG clock enable*/
     LDR R0,=0x40021018
     LDR R1,=0x00000001
     STR R1, [R0]
 /*Set CFGR1 register with flash memory remap at address 0*/
     LDR R0,=0x40010000
     LDR R1,=0x00000000
     STR R1, [R0]
 ApplicationStart:
 /* Copy the data segment initializers from flash to SRAM */
   movs r1, #0
   b LoopCopyDataInit
 CopyDataInit:
   ldr r3, =_sidata
   ldr r3, [r3, r1]
   str r3, [r0, r1]
   adds r1, r1, #4
 LoopCopyDataInit:
   ldr r0, =_sdata
   ldr r3, =_edata
   adds r2, r0, r1
   cmp r2, r3
   bcc CopyDataInit
   ldr r2, =_sbss
   b LoopFillZerobss
 /* Zero fill the bss segment. */
 FillZerobss:
   movs r3, #0
   str  r3, [r2]
   adds r2, r2, #4
 LoopFillZerobss:
   ldr r3, = _ebss
   cmp r2, r3
   bcc FillZerobss
 /* Call the clock system intitialization function.*/
     bl  SystemInit
 /* Call the application's entry point.*/
   bl main
 LoopForever:
     b LoopForever
 .size Reset_Handler, .-Reset_Handler
 /**
  * @brief  This is the code that gets called when the processor receives an
  *         unexpected interrupt.  This simply enters an infinite loop, preserving
  *         the system state for examination by a debugger.
+ *
  * @param  None
  * @retval : None
 */
     .section .text.Default_Handler,"ax",%progbits
 Default_Handler:
 Infinite_Loop:
   b Infinite_Loop
   .size Default_Handler, .-Default_Handler
 /******************************************************************************
+*
 * The minimal vector table for a Cortex M0.  Note that the proper constructs
 * must be placed on this to ensure that it ends up at physical address
 * 0x0000.0000.
+*
 ******************************************************************************/
    .section .isr_vector,"a",%progbits
   .type g_pfnVectors, %object
   .size g_pfnVectors, .-g_pfnVectors
 g_pfnVectors:
   .word _estack
   .word Reset_Handler
   .word NMI_Handler
   .word HardFault_Handler
   .word 0
   .word 0
   .word 0
   .word 0
   .word 0
   .word 0
   .word 0
   .word SVC_Handler
   .word 0
   .word 0
   .word PendSV_Handler
   .word SysTick_Handler
   .word WWDG_IRQHandler
   .word PVD_IRQHandler
   .word RTC_IRQHandler
   .word FLASH_IRQHandler
   .word RCC_IRQHandler
   .word EXTI0_1_IRQHandler
   .word EXTI2_3_IRQHandler
   .word EXTI4_15_IRQHandler
   .word TS_IRQHandler
   .word DMA1_Channel1_IRQHandler
   .word DMA1_Channel2_3_IRQHandler
   .word DMA1_Channel4_5_IRQHandler
   .word ADC1_COMP_IRQHandler
   .word TIM1_BRK_UP_TRG_COM_IRQHandler
   .word TIM1_CC_IRQHandler
   .word TIM2_IRQHandler
   .word TIM3_IRQHandler
   .word TIM6_DAC_IRQHandler
   .word 0
   .word TIM14_IRQHandler
   .word TIM15_IRQHandler
   .word TIM16_IRQHandler
   .word TIM17_IRQHandler
   .word I2C1_IRQHandler
   .word I2C2_IRQHandler
   .word SPI1_IRQHandler
   .word SPI2_IRQHandler
   .word USART1_IRQHandler
   .word USART2_IRQHandler
   .word 0
   .word CEC_IRQHandler
   .word 0
   .word BootRAM          /* @0x108. This is for boot in RAM mode for
                             STM32F0xx devices. */
 /*******************************************************************************
+*
 * Provide weak aliases for each Exception handler to the Default_Handler.
 * As they are weak aliases, any function with the same name will override
 * this definition.
+*
 *******************************************************************************/
   .weak NMI_Handler
   .thumb_set NMI_Handler,Default_Handler
   .weak HardFault_Handler
   .thumb_set HardFault_Handler,Default_Handler
   .weak SVC_Handler
   .thumb_set SVC_Handler,Default_Handler
   .weak PendSV_Handler
   .thumb_set PendSV_Handler,Default_Handler
   .weak SysTick_Handler
   .thumb_set SysTick_Handler,Default_Handler
   .weak WWDG_IRQHandler
   .thumb_set WWDG_IRQHandler,Default_Handler
   .weak PVD_IRQHandler
   .thumb_set PVD_IRQHandler,Default_Handler
   .weak RTC_IRQHandler
   .thumb_set RTC_IRQHandler,Default_Handler
   .weak FLASH_IRQHandler
   .thumb_set FLASH_IRQHandler,Default_Handler
   .weak RCC_IRQHandler
   .thumb_set RCC_IRQHandler,Default_Handler
   .weak EXTI0_1_IRQHandler
   .thumb_set EXTI0_1_IRQHandler,Default_Handler
   .weak EXTI2_3_IRQHandler
   .thumb_set EXTI2_3_IRQHandler,Default_Handler
   .weak EXTI4_15_IRQHandler
   .thumb_set EXTI4_15_IRQHandler,Default_Handler
   .weak TS_IRQHandler
   .thumb_set TS_IRQHandler,Default_Handler
   .weak DMA1_Channel1_IRQHandler
   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
   .weak DMA1_Channel2_3_IRQHandler
   .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
   .weak DMA1_Channel4_5_IRQHandler
   .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
   .weak ADC1_COMP_IRQHandler
   .thumb_set ADC1_COMP_IRQHandler,Default_Handler
   .weak TIM1_BRK_UP_TRG_COM_IRQHandler
   .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
   .weak TIM1_CC_IRQHandler
   .thumb_set TIM1_CC_IRQHandler,Default_Handler
   .weak TIM2_IRQHandler
   .thumb_set TIM2_IRQHandler,Default_Handler
   .weak TIM3_IRQHandler
   .thumb_set TIM3_IRQHandler,Default_Handler
   .weak TIM6_DAC_IRQHandler
   .thumb_set TIM6_DAC_IRQHandler,Default_Handler
   .weak TIM14_IRQHandler
   .thumb_set TIM14_IRQHandler,Default_Handler
   .weak TIM15_IRQHandler
   .thumb_set TIM15_IRQHandler,Default_Handler
   .weak TIM16_IRQHandler
   .thumb_set TIM16_IRQHandler,Default_Handler
   .weak TIM17_IRQHandler
   .thumb_set TIM17_IRQHandler,Default_Handler
   .weak I2C1_IRQHandler
   .thumb_set I2C1_IRQHandler,Default_Handler
   .weak I2C2_IRQHandler
   .thumb_set I2C2_IRQHandler,Default_Handler
   .weak SPI1_IRQHandler
   .thumb_set SPI1_IRQHandler,Default_Handler
   .weak SPI2_IRQHandler
   .thumb_set SPI2_IRQHandler,Default_Handler
   .weak USART1_IRQHandler
   .thumb_set USART1_IRQHandler,Default_Handler
   .weak USART2_IRQHandler
   .thumb_set USART2_IRQHandler,Default_Handler
   .weak CEC_IRQHandler
   .thumb_set CEC_IRQHandler,Default_Handler
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f072.s

➞

Show inline comments

@@ new file 100644 @@
 /**
   ******************************************************************************
   * @file      startup_stm32f0xx.s
   * @author    MCD Application Team
   * @version   V1.4.0
   * @date      24-July-2014
   * @brief     STM32F072 Devices vector table for RIDE7 toolchain.
   *            This module performs:
   *                - Set the initial SP
   *                - Set the initial PC == Reset_Handler,
   *                - Set the vector table entries with the exceptions ISR address
   *                - Configure the system clock
   *                - Branches to main in the C library (which eventually
   *                  calls main()).
   *            After Reset the Cortex-M0 processor is in Thread mode,
   *            priority is Privileged, and the Stack is set to Main.
   ******************************************************************************
   * @attention
+  *
   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
   * You may not use this file except in compliance with the License.
   * You may obtain a copy of the License at:
+  *
   *        http://www.st.com/software_license_agreement_liberty_v2
+  *
   * Unless required by applicable law or agreed to in writing, software
   * distributed under the License is distributed on an "AS IS" BASIS,
   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
   * See the License for the specific language governing permissions and
   * limitations under the License.
+  *
   ******************************************************************************
   */
   .syntax unified
   .cpu cortex-m0
   .fpu softvfp
   .thumb
 .global g_pfnVectors
 .global Default_Handler
 /* start address for the initialization values of the .data section.
 defined in linker script */
 .word _sidata
 /* start address for the .data section. defined in linker script */
 .word _sdata
 /* end address for the .data section. defined in linker script */
 .word _edata
 /* start address for the .bss section. defined in linker script */
 .word _sbss
 /* end address for the .bss section. defined in linker script */
 .word _ebss
 .equ  BootRAM, 0xF108F85F
 /**
  * @brief  This is the code that gets called when the processor first
  *          starts execution following a reset event. Only the absolutely
  *          necessary set is performed, after which the application
  *          supplied main() routine is called.
  * @param  None
  * @retval : None
 */
   .section .text.Reset_Handler
   .weak Reset_Handler
   .type Reset_Handler, %function
 Reset_Handler:
   ldr   r0, =_estack
   mov   sp, r0          /* set stack pointer */
 /*Check if boot space corresponds to test memory*/
     LDR R0,=0x00000004
     LDR R1, [R0]
     LSRS R1, R1, #24
     LDR R2,=0x1F
     CMP R1, R2
     BNE ApplicationStart
  /*SYSCFG clock enable*/
     LDR R0,=0x40021018
     LDR R1,=0x00000001
     STR R1, [R0]
 /*Set CFGR1 register with flash memory remap at address 0*/
     LDR R0,=0x40010000
     LDR R1,=0x00000000
     STR R1, [R0]
 ApplicationStart:
 /* Copy the data segment initializers from flash to SRAM */
   movs r1, #0
   b LoopCopyDataInit
 CopyDataInit:
   ldr r3, =_sidata
   ldr r3, [r3, r1]
   str r3, [r0, r1]
   adds r1, r1, #4
 LoopCopyDataInit:
   ldr r0, =_sdata
   ldr r3, =_edata
   adds r2, r0, r1
   cmp r2, r3
   bcc CopyDataInit
   ldr r2, =_sbss
   b LoopFillZerobss
 /* Zero fill the bss segment. */
 FillZerobss:
   movs r3, #0
   str  r3, [r2]
   adds r2, r2, #4
 LoopFillZerobss:
   ldr r3, = _ebss
   cmp r2, r3
   bcc FillZerobss
 /* Call the clock system intitialization function.*/
     bl  SystemInit
 /* Call the application's entry point.*/
   bl main
 LoopForever:
     b LoopForever
 .size Reset_Handler, .-Reset_Handler
 /**
  * @brief  This is the code that gets called when the processor receives an
  *         unexpected interrupt.  This simply enters an infinite loop, preserving
  *         the system state for examination by a debugger.
+ *
  * @param  None
  * @retval : None
 */
     .section .text.Default_Handler,"ax",%progbits
 Default_Handler:
 Infinite_Loop:
   b Infinite_Loop
   .size Default_Handler, .-Default_Handler
 /******************************************************************************
+*
 * The minimal vector table for a Cortex M0.  Note that the proper constructs
 * must be placed on this to ensure that it ends up at physical address
 * 0x0000.0000.
+*
 ******************************************************************************/
    .section .isr_vector,"a",%progbits
   .type g_pfnVectors, %object
   .size g_pfnVectors, .-g_pfnVectors
 g_pfnVectors:
   .word _estack
   .word Reset_Handler
   .word NMI_Handler
   .word HardFault_Handler
   .word 0
   .word 0
   .word 0
   .word 0
   .word 0
   .word 0
   .word 0
   .word SVC_Handler
   .word 0
   .word 0
   .word PendSV_Handler
   .word SysTick_Handler
   .word WWDG_IRQHandler
   .word PVD_VDDIO2_IRQHandler
   .word RTC_IRQHandler
   .word FLASH_IRQHandler
   .word RCC_CRS_IRQHandler
   .word EXTI0_1_IRQHandler
   .word EXTI2_3_IRQHandler
   .word EXTI4_15_IRQHandler
   .word TSC_IRQHandler
   .word DMA1_Channel1_IRQHandler
   .word DMA1_Channel2_3_IRQHandler
   .word DMA1_Channel4_5_6_7_IRQHandler
   .word ADC1_COMP_IRQHandler
   .word TIM1_BRK_UP_TRG_COM_IRQHandler
   .word TIM1_CC_IRQHandler
   .word TIM2_IRQHandler
   .word TIM3_IRQHandler
   .word TIM6_DAC_IRQHandler
   .word TIM7_IRQHandler
   .word TIM14_IRQHandler
   .word TIM15_IRQHandler
   .word TIM16_IRQHandler
   .word TIM17_IRQHandler
   .word I2C1_IRQHandler
   .word I2C2_IRQHandler
   .word SPI1_IRQHandler
   .word SPI2_IRQHandler
   .word USART1_IRQHandler
   .word USART2_IRQHandler
   .word USART3_4_IRQHandler
   .word CEC_CAN_IRQHandler
   .word USB_IRQHandler
   .word BootRAM          /* @0x108. This is for boot in RAM mode for
                             STM32F0xx devices. */
 /*******************************************************************************
+*
 * Provide weak aliases for each Exception handler to the Default_Handler.
 * As they are weak aliases, any function with the same name will override
 * this definition.
+*
 *******************************************************************************/
   .weak NMI_Handler
   .thumb_set NMI_Handler,Default_Handler
   .weak HardFault_Handler
   .thumb_set HardFault_Handler,Default_Handler
   .weak SVC_Handler
   .thumb_set SVC_Handler,Default_Handler
   .weak PendSV_Handler
   .thumb_set PendSV_Handler,Default_Handler
   .weak SysTick_Handler
   .thumb_set SysTick_Handler,Default_Handler
   .weak WWDG_IRQHandler
   .thumb_set WWDG_IRQHandler,Default_Handler
   .weak PVD_VDDIO2_IRQHandler
   .thumb_set PVD_VDDIO2_IRQHandler,Default_Handler
   .weak RTC_IRQHandler
   .thumb_set RTC_IRQHandler,Default_Handler
   .weak FLASH_IRQHandler
   .thumb_set FLASH_IRQHandler,Default_Handler
   .weak RCC_CRS_IRQHandler
   .thumb_set RCC_CRS_IRQHandler,Default_Handler
   .weak EXTI0_1_IRQHandler
   .thumb_set EXTI0_1_IRQHandler,Default_Handler
   .weak EXTI2_3_IRQHandler
   .thumb_set EXTI2_3_IRQHandler,Default_Handler
   .weak EXTI4_15_IRQHandler
   .thumb_set EXTI4_15_IRQHandler,Default_Handler
   .weak TSC_IRQHandler
   .thumb_set TSC_IRQHandler,Default_Handler
   .weak DMA1_Channel1_IRQHandler
   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
   .weak DMA1_Channel2_3_IRQHandler
   .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
   .weak DMA1_Channel4_5_6_7_IRQHandler
   .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
   .weak ADC1_COMP_IRQHandler
   .thumb_set ADC1_COMP_IRQHandler,Default_Handler
   .weak TIM1_BRK_UP_TRG_COM_IRQHandler
   .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
   .weak TIM1_CC_IRQHandler
   .thumb_set TIM1_CC_IRQHandler,Default_Handler
   .weak TIM2_IRQHandler
   .thumb_set TIM2_IRQHandler,Default_Handler
   .weak TIM3_IRQHandler
   .thumb_set TIM3_IRQHandler,Default_Handler
   .weak TIM6_DAC_IRQHandler
   .thumb_set TIM6_DAC_IRQHandler,Default_Handler
   .weak TIM7_IRQHandler
   .thumb_set TIM7_IRQHandler,Default_Handler
   .weak TIM14_IRQHandler
   .thumb_set TIM14_IRQHandler,Default_Handler
   .weak TIM15_IRQHandler
   .thumb_set TIM15_IRQHandler,Default_Handler
   .weak TIM16_IRQHandler
   .thumb_set TIM16_IRQHandler,Default_Handler
   .weak TIM17_IRQHandler
   .thumb_set TIM17_IRQHandler,Default_Handler
   .weak I2C1_IRQHandler
   .thumb_set I2C1_IRQHandler,Default_Handler
   .weak I2C2_IRQHandler
   .thumb_set I2C2_IRQHandler,Default_Handler
   .weak SPI1_IRQHandler
   .thumb_set SPI1_IRQHandler,Default_Handler
   .weak SPI2_IRQHandler
   .thumb_set SPI2_IRQHandler,Default_Handler
   .weak USART1_IRQHandler
   .thumb_set USART1_IRQHandler,Default_Handler
   .weak USART2_IRQHandler
   .thumb_set USART2_IRQHandler,Default_Handler
   .weak USART3_4_IRQHandler
   .thumb_set USART3_4_IRQHandler,Default_Handler
   .weak CEC_CAN_IRQHandler
   .thumb_set CEC_CAN_IRQHandler,Default_Handler
   .weak USB_IRQHandler
   .thumb_set USB_IRQHandler,Default_Handler
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f0xx.s

➞

Show inline comments

@@ new file 100644 @@
 /**
   ******************************************************************************
   * @file      startup_stm32f0xx.s
   * @author    MCD Application Team
   * @version   V1.4.0
   * @date      24-July-2014
   * @brief     STM32F0xx Devices vector table for RIDE7 toolchain.
   *            This module performs:
   *                - Set the initial SP
   *                - Set the initial PC == Reset_Handler,
   *                - Set the vector table entries with the exceptions ISR address
   *                - Configure the system clock
   *                - Branches to main in the C library (which eventually
   *                  calls main()).
   *            After Reset the Cortex-M0 processor is in Thread mode,
   *            priority is Privileged, and the Stack is set to Main.
   ******************************************************************************
   * @attention
+  *
   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
   * You may not use this file except in compliance with the License.
   * You may obtain a copy of the License at:
+  *
   *        http://www.st.com/software_license_agreement_liberty_v2
+  *
   * Unless required by applicable law or agreed to in writing, software
   * distributed under the License is distributed on an "AS IS" BASIS,
   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
   * See the License for the specific language governing permissions and
   * limitations under the License.
+  *
   ******************************************************************************
   */
   .syntax unified
   .cpu cortex-m0
   .fpu softvfp
   .thumb
 .global g_pfnVectors
 .global Default_Handler
 /* start address for the initialization values of the .data section.
 defined in linker script */
 .word _sidata
 /* start address for the .data section. defined in linker script */
 .word _sdata
 /* end address for the .data section. defined in linker script */
 .word _edata
 /* start address for the .bss section. defined in linker script */
 .word _sbss
 /* end address for the .bss section. defined in linker script */
 .word _ebss
 .equ  BootRAM, 0xF108F85F
 /**
  * @brief  This is the code that gets called when the processor first
  *          starts execution following a reset event. Only the absolutely
  *          necessary set is performed, after which the application
  *          supplied main() routine is called.
  * @param  None
  * @retval : None
 */
   .section .text.Reset_Handler
   .weak Reset_Handler
   .type Reset_Handler, %function
 Reset_Handler:
   ldr   r0, =_estack
   mov   sp, r0          /* set stack pointer */
 /*Check if boot space corresponds to test memory*/
     LDR R0,=0x00000004
     LDR R1, [R0]
     LSRS R1, R1, #24
     LDR R2,=0x1F
     CMP R1, R2
     BNE ApplicationStart
  /*SYSCFG clock enable*/
     LDR R0,=0x40021018
     LDR R1,=0x00000001
     STR R1, [R0]
 /*Set CFGR1 register with flash memory remap at address 0*/
     LDR R0,=0x40010000
     LDR R1,=0x00000000
     STR R1, [R0]
 ApplicationStart:
 /* Copy the data segment initializers from flash to SRAM */
   movs r1, #0
   b LoopCopyDataInit
 CopyDataInit:
   ldr r3, =_sidata
   ldr r3, [r3, r1]
   str r3, [r0, r1]
   adds r1, r1, #4
 LoopCopyDataInit:
   ldr r0, =_sdata
   ldr r3, =_edata
   adds r2, r0, r1
   cmp r2, r3
   bcc CopyDataInit
   ldr r2, =_sbss
   b LoopFillZerobss
 /* Zero fill the bss segment. */
 FillZerobss:
   movs r3, #0
   str  r3, [r2]
   adds r2, r2, #4
 LoopFillZerobss:
   ldr r3, = _ebss
   cmp r2, r3
   bcc FillZerobss
 /* Call the clock system intitialization function.*/
     bl  SystemInit
 /* Call the application's entry point.*/
   bl main
 LoopForever:
     b LoopForever
 .size Reset_Handler, .-Reset_Handler
 /**
  * @brief  This is the code that gets called when the processor receives an
  *         unexpected interrupt.  This simply enters an infinite loop, preserving
  *         the system state for examination by a debugger.
+ *
  * @param  None
  * @retval : None
 */
     .section .text.Default_Handler,"ax",%progbits
 Default_Handler:
 Infinite_Loop:
   b Infinite_Loop
   .size Default_Handler, .-Default_Handler
 /******************************************************************************
+*
 * The minimal vector table for a Cortex M0.  Note that the proper constructs
 * must be placed on this to ensure that it ends up at physical address
 * 0x0000.0000.
+*
 ******************************************************************************/
    .section .isr_vector,"a",%progbits
   .type g_pfnVectors, %object
   .size g_pfnVectors, .-g_pfnVectors
 g_pfnVectors:
   .word _estack
   .word Reset_Handler
   .word NMI_Handler
   .word HardFault_Handler
   .word 0
   .word 0
   .word 0
   .word 0
   .word 0
   .word 0
   .word 0
   .word SVC_Handler
   .word 0
   .word 0
   .word PendSV_Handler
   .word SysTick_Handler
   .word WWDG_IRQHandler
   .word PVD_IRQHandler
   .word RTC_IRQHandler
   .word FLASH_IRQHandler
   .word RCC_IRQHandler
   .word EXTI0_1_IRQHandler
   .word EXTI2_3_IRQHandler
   .word EXTI4_15_IRQHandler
   .word TS_IRQHandler
   .word DMA1_Channel1_IRQHandler
   .word DMA1_Channel2_3_IRQHandler
   .word DMA1_Channel4_5_IRQHandler
   .word ADC1_COMP_IRQHandler
   .word TIM1_BRK_UP_TRG_COM_IRQHandler
   .word TIM1_CC_IRQHandler
   .word TIM2_IRQHandler
   .word TIM3_IRQHandler
   .word TIM6_DAC_IRQHandler
   .word 0
   .word TIM14_IRQHandler
   .word TIM15_IRQHandler
   .word TIM16_IRQHandler
   .word TIM17_IRQHandler
   .word I2C1_IRQHandler
   .word I2C2_IRQHandler
   .word SPI1_IRQHandler
   .word SPI2_IRQHandler
   .word USART1_IRQHandler
   .word USART2_IRQHandler
   .word 0
   .word CEC_IRQHandler
   .word 0
   .word BootRAM          /* @0x108. This is for boot in RAM mode for
                             STM32F0xx devices. */
 /*******************************************************************************
+*
 * Provide weak aliases for each Exception handler to the Default_Handler.
 * As they are weak aliases, any function with the same name will override
 * this definition.
+*
 *******************************************************************************/
   .weak NMI_Handler
   .thumb_set NMI_Handler,Default_Handler
   .weak HardFault_Handler
   .thumb_set HardFault_Handler,Default_Handler
   .weak SVC_Handler
   .thumb_set SVC_Handler,Default_Handler
   .weak PendSV_Handler
   .thumb_set PendSV_Handler,Default_Handler
   .weak SysTick_Handler
   .thumb_set SysTick_Handler,Default_Handler
   .weak WWDG_IRQHandler
   .thumb_set WWDG_IRQHandler,Default_Handler
   .weak PVD_IRQHandler
   .thumb_set PVD_IRQHandler,Default_Handler
   .weak RTC_IRQHandler
   .thumb_set RTC_IRQHandler,Default_Handler
   .weak FLASH_IRQHandler
   .thumb_set FLASH_IRQHandler,Default_Handler
   .weak RCC_IRQHandler
   .thumb_set RCC_IRQHandler,Default_Handler
   .weak EXTI0_1_IRQHandler
   .thumb_set EXTI0_1_IRQHandler,Default_Handler
   .weak EXTI2_3_IRQHandler
   .thumb_set EXTI2_3_IRQHandler,Default_Handler
   .weak EXTI4_15_IRQHandler
   .thumb_set EXTI4_15_IRQHandler,Default_Handler
   .weak TS_IRQHandler
   .thumb_set TS_IRQHandler,Default_Handler
   .weak DMA1_Channel1_IRQHandler
   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
   .weak DMA1_Channel2_3_IRQHandler
   .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
   .weak DMA1_Channel4_5_IRQHandler
   .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
   .weak ADC1_COMP_IRQHandler
   .thumb_set ADC1_COMP_IRQHandler,Default_Handler
   .weak TIM1_BRK_UP_TRG_COM_IRQHandler
   .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
   .weak TIM1_CC_IRQHandler
   .thumb_set TIM1_CC_IRQHandler,Default_Handler
   .weak TIM2_IRQHandler
   .thumb_set TIM2_IRQHandler,Default_Handler
   .weak TIM3_IRQHandler
   .thumb_set TIM3_IRQHandler,Default_Handler
   .weak TIM6_DAC_IRQHandler
   .thumb_set TIM6_DAC_IRQHandler,Default_Handler
   .weak TIM14_IRQHandler
   .thumb_set TIM14_IRQHandler,Default_Handler
   .weak TIM15_IRQHandler
   .thumb_set TIM15_IRQHandler,Default_Handler
   .weak TIM16_IRQHandler
   .thumb_set TIM16_IRQHandler,Default_Handler
   .weak TIM17_IRQHandler
   .thumb_set TIM17_IRQHandler,Default_Handler
   .weak I2C1_IRQHandler
   .thumb_set I2C1_IRQHandler,Default_Handler
   .weak I2C2_IRQHandler
   .thumb_set I2C2_IRQHandler,Default_Handler
   .weak SPI1_IRQHandler
   .thumb_set SPI1_IRQHandler,Default_Handler
   .weak SPI2_IRQHandler
   .thumb_set SPI2_IRQHandler,Default_Handler
   .weak USART1_IRQHandler
   .thumb_set USART1_IRQHandler,Default_Handler
   .weak USART2_IRQHandler
   .thumb_set USART2_IRQHandler,Default_Handler
   .weak CEC_IRQHandler
   .thumb_set CEC_IRQHandler,Default_Handler
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f030.s

➞

Show inline comments

@@ new file 100644 @@
 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
 ;* File Name          : startup_stm32f030.s
 ;* Author             : MCD Application Team
 ;* Version            : V1.4.0
 ;* Date               : 24-July-2014
 ;* Description        : STM32F030 devices vector table for EWARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
 ;*                      - Set the initial PC == iar_program_start,
 ;*                      - Set the vector table entries with the exceptions ISR
 ;*                        address
 ;*                      - Configure the system clock
 ;*                      - Branches to main in the C library (which eventually
 ;*                        calls main()).
 ;*                      After Reset the Cortex-M0 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;*******************************************************************************
 ;  @attention
+;
 ;  Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 ;  You may not use this file except in compliance with the License.
 ;  You may obtain a copy of the License at:
+;
 ;         http://www.st.com/software_license_agreement_liberty_v2
+;
 ;  Unless required by applicable law or agreed to in writing, software
 ;  distributed under the License is distributed on an "AS IS" BASIS,
 ;  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 ;  See the License for the specific language governing permissions and
 ;  limitations under the License.
+;
 ;*******************************************************************************
+;
+;
 ; The modules in this file are included in the libraries, and may be replaced
 ; by any user-defined modules that define the PUBLIC symbol _program_start or
 ; a user defined start symbol.
 ; To override the cstartup defined in the library, simply add your modified
 ; version to the workbench project.
+;
 ; The vector table is normally located at address 0.
 ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
 ; The name "__vector_table" has special meaning for C-SPY:
 ; it is where the SP start value is found, and the NVIC vector
 ; table register (VTOR) is initialized to this address if != 0.
+;
 ; Cortex-M version
+;
         MODULE  ?cstartup
         ;; Forward declaration of sections.
         SECTION CSTACK:DATA:NOROOT(3)
         SECTION .intvec:CODE:NOROOT(2)
         EXTERN  __iar_program_start
         EXTERN  SystemInit
         PUBLIC  __vector_table
         DATA
 __vector_table
         DCD     sfe(CSTACK)
         DCD     Reset_Handler                  ; Reset Handler
         DCD     NMI_Handler                    ; NMI Handler
         DCD     HardFault_Handler              ; Hard Fault Handler
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     SVC_Handler                    ; SVCall Handler
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     PendSV_Handler                 ; PendSV Handler
         DCD     SysTick_Handler                ; SysTick Handler
         ; External Interrupts
         DCD     WWDG_IRQHandler                ; Window Watchdog
         DCD     0                              ; Reserved
         DCD     RTC_IRQHandler                 ; RTC through EXTI Line
         DCD     FLASH_IRQHandler               ; FLASH
         DCD     RCC_IRQHandler                 ; RCC
         DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
         DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
         DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
         DCD     0                              ; Reserved
         DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
         DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
         DCD     DMA1_Channel4_5_IRQHandler     ; DMA1 Channel 4 and Channel 5
         DCD     ADC1_IRQHandler                ; ADC1
         DCD     TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
         DCD     TIM1_CC_IRQHandler             ; TIM1 Capture Compare
         DCD     0                              ; Reserved
         DCD     TIM3_IRQHandler                ; TIM3
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     TIM14_IRQHandler               ; TIM14
         DCD     TIM15_IRQHandler               ; TIM15
         DCD     TIM16_IRQHandler               ; TIM16
         DCD     TIM17_IRQHandler               ; TIM17
         DCD     I2C1_IRQHandler                ; I2C1
         DCD     I2C2_IRQHandler                ; I2C2
         DCD     SPI1_IRQHandler                ; SPI1
         DCD     SPI2_IRQHandler                ; SPI2
         DCD     USART1_IRQHandler              ; USART1
         DCD     USART2_IRQHandler              ; USART2
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;;
 ;; Default interrupt handlers.
 ;;
         THUMB
         PUBWEAK Reset_Handler
         SECTION .text:CODE:NOROOT:REORDER(2)
 Reset_Handler
         LDR     R0, =sfe(CSTACK)          ; set stack pointer
         MSR     MSP, R0
 ;;Check if boot space corresponds to test memory
         LDR R0,=0x00000004
         LDR R1, [R0]
         LSRS R1, R1, #24
         LDR R2,=0x1F
         CMP R1, R2
         BNE ApplicationStart
 ;; SYSCFG clock enable
         LDR R0,=0x40021018
         LDR R1,=0x00000001
         STR R1, [R0]
 ;; Set CFGR1 register with flash memory remap at address 0
         LDR R0,=0x40010000
         LDR R1,=0x00000000
         STR R1, [R0]
 ApplicationStart
         LDR     R0, =SystemInit
         BLX     R0
         LDR     R0, =__iar_program_start
         BX      R0
         PUBWEAK NMI_Handler
         SECTION .text:CODE:NOROOT:REORDER(1)
 NMI_Handler
         B NMI_Handler
         PUBWEAK HardFault_Handler
         SECTION .text:CODE:NOROOT:REORDER(1)
 HardFault_Handler
         B HardFault_Handler
         PUBWEAK SVC_Handler
         SECTION .text:CODE:NOROOT:REORDER(1)
 SVC_Handler
         B SVC_Handler
         PUBWEAK PendSV_Handler
         SECTION .text:CODE:NOROOT:REORDER(1)
 PendSV_Handler
         B PendSV_Handler
         PUBWEAK SysTick_Handler
         SECTION .text:CODE:NOROOT:REORDER(1)
 SysTick_Handler
         B SysTick_Handler
         PUBWEAK WWDG_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 WWDG_IRQHandler
         B WWDG_IRQHandler
         PUBWEAK RTC_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 RTC_IRQHandler
         B RTC_IRQHandler
         PUBWEAK FLASH_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 FLASH_IRQHandler
         B FLASH_IRQHandler
         PUBWEAK RCC_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 RCC_IRQHandler
         B RCC_IRQHandler
         PUBWEAK EXTI0_1_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 EXTI0_1_IRQHandler
         B EXTI0_1_IRQHandler
         PUBWEAK EXTI2_3_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 EXTI2_3_IRQHandler
         B EXTI2_3_IRQHandler
         PUBWEAK EXTI4_15_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 EXTI4_15_IRQHandler
         B EXTI4_15_IRQHandler
         PUBWEAK DMA1_Channel1_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 DMA1_Channel1_IRQHandler
         B DMA1_Channel1_IRQHandler
         PUBWEAK DMA1_Channel2_3_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 DMA1_Channel2_3_IRQHandler
         B DMA1_Channel2_3_IRQHandler
         PUBWEAK DMA1_Channel4_5_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 DMA1_Channel4_5_IRQHandler
         B DMA1_Channel4_5_IRQHandler
         PUBWEAK ADC1_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 ADC1_IRQHandler
         B ADC1_IRQHandler
         PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM1_BRK_UP_TRG_COM_IRQHandler
         B TIM1_BRK_UP_TRG_COM_IRQHandler
         PUBWEAK TIM1_CC_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM1_CC_IRQHandler
         B TIM1_CC_IRQHandler
         PUBWEAK TIM3_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM3_IRQHandler
         B TIM3_IRQHandler
         PUBWEAK TIM14_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM14_IRQHandler
         B TIM14_IRQHandler
         PUBWEAK TIM15_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM15_IRQHandler
         B TIM15_IRQHandler
         PUBWEAK TIM16_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM16_IRQHandler
         B TIM16_IRQHandler
         PUBWEAK TIM17_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM17_IRQHandler
         B TIM17_IRQHandler
         PUBWEAK I2C1_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 I2C1_IRQHandler
         B I2C1_IRQHandler
         PUBWEAK I2C2_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 I2C2_IRQHandler
         B I2C2_IRQHandler
         PUBWEAK SPI1_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 SPI1_IRQHandler
         B SPI1_IRQHandler
         PUBWEAK SPI2_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 SPI2_IRQHandler
         B SPI2_IRQHandler
         PUBWEAK USART1_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 USART1_IRQHandler
         B USART1_IRQHandler
         PUBWEAK USART2_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 USART2_IRQHandler
         B USART2_IRQHandler
         END
 ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f031.s

➞

Show inline comments

@@ new file 100644 @@
 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
 ;* File Name          : startup_stm32f031.s
 ;* Author             : MCD Application Team
 ;* Version            : V1.4.0
 ;* Date               : 24-July-2014
 ;* Description        : STM32F031 devices vector table for EWARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
 ;*                      - Set the initial PC == iar_program_start,
 ;*                      - Set the vector table entries with the exceptions ISR
 ;*                        address
 ;*                      - Configure the system clock
 ;*                      - Branches to main in the C library (which eventually
 ;*                        calls main()).
 ;*                      After Reset the Cortex-M0 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;*******************************************************************************
 ;  @attention
+;
 ;  Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 ;  You may not use this file except in compliance with the License.
 ;  You may obtain a copy of the License at:
+;
 ;         http://www.st.com/software_license_agreement_liberty_v2
+;
 ;  Unless required by applicable law or agreed to in writing, software
 ;  distributed under the License is distributed on an "AS IS" BASIS,
 ;  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 ;  See the License for the specific language governing permissions and
 ;  limitations under the License.
+;
 ;*******************************************************************************
+;
+;
 ; The modules in this file are included in the libraries, and may be replaced
 ; by any user-defined modules that define the PUBLIC symbol _program_start or
 ; a user defined start symbol.
 ; To override the cstartup defined in the library, simply add your modified
 ; version to the workbench project.
+;
 ; The vector table is normally located at address 0.
 ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
 ; The name "__vector_table" has special meaning for C-SPY:
 ; it is where the SP start value is found, and the NVIC vector
 ; table register (VTOR) is initialized to this address if != 0.
+;
 ; Cortex-M version
+;
         MODULE  ?cstartup
         ;; Forward declaration of sections.
         SECTION CSTACK:DATA:NOROOT(3)
         SECTION .intvec:CODE:NOROOT(2)
         EXTERN  __iar_program_start
         EXTERN  SystemInit
         PUBLIC  __vector_table
         DATA
 __vector_table
         DCD     sfe(CSTACK)
         DCD     Reset_Handler                  ; Reset Handler
         DCD     NMI_Handler                    ; NMI Handler
         DCD     HardFault_Handler              ; Hard Fault Handler
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     SVC_Handler                    ; SVCall Handler
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     PendSV_Handler                 ; PendSV Handler
         DCD     SysTick_Handler                ; SysTick Handler
         ; External Interrupts
         DCD     WWDG_IRQHandler                ; Window Watchdog
         DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
         DCD     RTC_IRQHandler                 ; RTC through EXTI Line
         DCD     FLASH_IRQHandler               ; FLASH
         DCD     RCC_IRQHandler                 ; RCC
         DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
         DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
         DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
         DCD     0                              ; Reserved
         DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
         DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
         DCD     DMA1_Channel4_5_IRQHandler     ; DMA1 Channel 4 and Channel 5
         DCD     ADC1_IRQHandler                ; ADC1
         DCD     TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
         DCD     TIM1_CC_IRQHandler             ; TIM1 Capture Compare
         DCD     TIM2_IRQHandler                ; TIM2
         DCD     TIM3_IRQHandler                ; TIM3
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     TIM14_IRQHandler               ; TIM14
         DCD     0                              ; Reserved
         DCD     TIM16_IRQHandler               ; TIM16
         DCD     TIM17_IRQHandler               ; TIM17
         DCD     I2C1_IRQHandler                ; I2C1
         DCD     0                              ; Reserved
         DCD     SPI1_IRQHandler                ; SPI1
         DCD     0                              ; Reserved
         DCD     USART1_IRQHandler              ; USART1
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;;
 ;; Default interrupt handlers.
 ;;
         THUMB
         PUBWEAK Reset_Handler
         SECTION .text:CODE:NOROOT:REORDER(2)
 Reset_Handler
         LDR     R0, =sfe(CSTACK)          ; set stack pointer
         MSR     MSP, R0
 ;;Check if boot space corresponds to test memory
         LDR R0,=0x00000004
         LDR R1, [R0]
         LSRS R1, R1, #24
         LDR R2,=0x1F
         CMP R1, R2
         BNE ApplicationStart
 ;; SYSCFG clock enable
         LDR R0,=0x40021018
         LDR R1,=0x00000001
         STR R1, [R0]
 ;; Set CFGR1 register with flash memory remap at address 0
         LDR R0,=0x40010000
         LDR R1,=0x00000000
         STR R1, [R0]
 ApplicationStart
         LDR     R0, =SystemInit
         BLX     R0
         LDR     R0, =__iar_program_start
         BX      R0
         PUBWEAK NMI_Handler
         SECTION .text:CODE:NOROOT:REORDER(1)
 NMI_Handler
         B NMI_Handler
         PUBWEAK HardFault_Handler
         SECTION .text:CODE:NOROOT:REORDER(1)
 HardFault_Handler
         B HardFault_Handler
         PUBWEAK SVC_Handler
         SECTION .text:CODE:NOROOT:REORDER(1)
 SVC_Handler
         B SVC_Handler
         PUBWEAK PendSV_Handler
         SECTION .text:CODE:NOROOT:REORDER(1)
 PendSV_Handler
         B PendSV_Handler
         PUBWEAK SysTick_Handler
         SECTION .text:CODE:NOROOT:REORDER(1)
 SysTick_Handler
         B SysTick_Handler
         PUBWEAK WWDG_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 WWDG_IRQHandler
         B WWDG_IRQHandler
         PUBWEAK PVD_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 PVD_IRQHandler
         B PVD_IRQHandler
         PUBWEAK RTC_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 RTC_IRQHandler
         B RTC_IRQHandler
         PUBWEAK FLASH_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 FLASH_IRQHandler
         B FLASH_IRQHandler
         PUBWEAK RCC_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 RCC_IRQHandler
         B RCC_IRQHandler
         PUBWEAK EXTI0_1_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 EXTI0_1_IRQHandler
         B EXTI0_1_IRQHandler
         PUBWEAK EXTI2_3_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 EXTI2_3_IRQHandler
         B EXTI2_3_IRQHandler
         PUBWEAK EXTI4_15_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 EXTI4_15_IRQHandler
         B EXTI4_15_IRQHandler
         PUBWEAK DMA1_Channel1_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 DMA1_Channel1_IRQHandler
         B DMA1_Channel1_IRQHandler
         PUBWEAK DMA1_Channel2_3_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 DMA1_Channel2_3_IRQHandler
         B DMA1_Channel2_3_IRQHandler
         PUBWEAK DMA1_Channel4_5_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 DMA1_Channel4_5_IRQHandler
         B DMA1_Channel4_5_IRQHandler
         PUBWEAK ADC1_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 ADC1_IRQHandler
         B ADC1_IRQHandler
         PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM1_BRK_UP_TRG_COM_IRQHandler
         B TIM1_BRK_UP_TRG_COM_IRQHandler
         PUBWEAK TIM1_CC_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM1_CC_IRQHandler
         B TIM1_CC_IRQHandler
         PUBWEAK TIM2_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM2_IRQHandler
         B TIM2_IRQHandler
         PUBWEAK TIM3_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM3_IRQHandler
         B TIM3_IRQHandler
         PUBWEAK TIM14_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM14_IRQHandler
         B TIM14_IRQHandler
         PUBWEAK TIM16_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM16_IRQHandler
         B TIM16_IRQHandler
         PUBWEAK TIM17_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM17_IRQHandler
         B TIM17_IRQHandler
         PUBWEAK I2C1_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 I2C1_IRQHandler
         B I2C1_IRQHandler
         PUBWEAK SPI1_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 SPI1_IRQHandler
         B SPI1_IRQHandler
         PUBWEAK USART1_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 USART1_IRQHandler
         B USART1_IRQHandler
         END
 ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f042.s

➞

Show inline comments

@@ new file 100644 @@
 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
 ;* File Name          : startup_stm32f042.s
 ;* Author             : MCD Appl&ication Team
 ;* Version            : V1.4.0
 ;* Date               : 24-July-2014
 ;* Description        : STM32F042 Devices Devices vector table for
 ;*                      EWARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
 ;*                      - Set the initial PC == iar_program_start,
 ;*                      - Set the vector table entries with the exceptions ISR
 ;*                        address.
 ;*                      After Reset the Cortex-M0 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;*******************************************************************************
 ;  @attention
+;
 ;  Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 ;  You may not use this file except in compliance with the License.
 ;  You may obtain a copy of the License at:
+;
 ;         http://www.st.com/software_license_agreement_liberty_v2
+;
 ;  Unless required by applicable law or agreed to in writing, software
 ;  distributed under the License is distributed on an "AS IS" BASIS,
 ;  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 ;  See the License for the specific language governing permissions and
 ;  limitations under the License.
+;
 ;*******************************************************************************
+;
+;
 ; The modules in this file are included in the libraries, and may be replaced
 ; by any user-defined modules that define the PUBLIC symbol _program_start or
 ; a user defined start symbol.
 ; To override the cstartup defined in the library, simply add your modified
 ; version to the workbench project.
+;
 ; The vector table is normally located at address 0.
 ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
 ; The name "__vector_table" has special meaning for C-SPY:
 ; it is where the SP start value is found, and the NVIC vector
 ; table register (VTOR) is initialized to this address if != 0.
+;
 ; Cortex-M version
+;
         MODULE  ?cstartup
         ;; Forward declaration of sections.
         SECTION CSTACK:DATA:NOROOT(3)
         SECTION .intvec:CODE:NOROOT(2)
         EXTERN  __iar_program_start
         EXTERN  SystemInit
         PUBLIC  __vector_table
         DATA
 __vector_table
         DCD     sfe(CSTACK)
         DCD     Reset_Handler                  ; Reset Handler
         DCD     NMI_Handler                    ; NMI Handler
         DCD     HardFault_Handler              ; Hard Fault Handler
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     SVC_Handler                    ; SVCall Handler
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     PendSV_Handler                 ; PendSV Handler
         DCD     SysTick_Handler                ; SysTick Handler
         ; External Interrupts
         DCD     WWDG_IRQHandler                ; Window Watchdog
         DCD     PVD_VDDIO2_IRQHandler          ; PVD and VDDIO2 through EXTI Line detect
         DCD     RTC_IRQHandler                 ; RTC through EXTI Line
         DCD     FLASH_IRQHandler               ; FLASH
         DCD     RCC_CRS_IRQHandler             ; RCC and CRS
         DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
         DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
         DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
         DCD     TSC_IRQHandler                  ; TS
         DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
         DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
         DCD     DMA1_Channel4_5_IRQHandler     ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
         DCD     ADC1_IRQHandler                ; ADC1
         DCD     TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
         DCD     TIM1_CC_IRQHandler             ; TIM1 Capture Compare
         DCD     TIM2_IRQHandler                ; TIM2
         DCD     TIM3_IRQHandler                ; TIM3
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     TIM14_IRQHandler               ; TIM14
         DCD     0                              ; Reserved
         DCD     TIM16_IRQHandler               ; TIM16
         DCD     TIM17_IRQHandler               ; TIM17
         DCD     I2C1_IRQHandler                ; I2C1
         DCD     0                              ; Reserved
         DCD     SPI1_IRQHandler                ; SPI1
         DCD     SPI2_IRQHandler                ; SPI2
         DCD     USART1_IRQHandler              ; USART1
         DCD     USART2_IRQHandler              ; USART2
         DCD     0                              ; Reserved
         DCD     CEC_CAN_IRQHandler             ; CEC and CAN
         DCD     USB_IRQHandler                 ; USB
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;;
 ;; Default interrupt handlers.
 ;;
         THUMB
         PUBWEAK Reset_Handler
         SECTION .text:CODE:NOROOT:REORDER(2)
 Reset_Handler
         LDR     R0, =sfe(CSTACK)          ; set stack pointer
         MSR     MSP, R0
 ;;Check if boot space corresponds to test memory
         LDR R0,=0x00000004
         LDR R1, [R0]
         LSRS R1, R1, #24
         LDR R2,=0x1F
         CMP R1, R2
         BNE ApplicationStart
 ;; SYSCFG clock enable
         LDR R0,=0x40021018
         LDR R1,=0x00000001
         STR R1, [R0]
 ;; Set CFGR1 register with flash memory remap at address 0
         LDR R0,=0x40010000
         LDR R1,=0x00000000
         STR R1, [R0]
 ApplicationStart
         LDR     R0, =SystemInit
         BLX     R0
         LDR     R0, =__iar_program_start
         BX      R0
         PUBWEAK NMI_Handler
         SECTION .text:CODE:NOROOT:REORDER(1)
 NMI_Handler
         B NMI_Handler
         PUBWEAK HardFault_Handler
         SECTION .text:CODE:NOROOT:REORDER(1)
 HardFault_Handler
         B HardFault_Handler
         PUBWEAK SVC_Handler
         SECTION .text:CODE:NOROOT:REORDER(1)
 SVC_Handler
         B SVC_Handler
         PUBWEAK PendSV_Handler
         SECTION .text:CODE:NOROOT:REORDER(1)
 PendSV_Handler
         B PendSV_Handler
         PUBWEAK SysTick_Handler
         SECTION .text:CODE:NOROOT:REORDER(1)
 SysTick_Handler
         B SysTick_Handler
         PUBWEAK WWDG_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 WWDG_IRQHandler
         B WWDG_IRQHandler
         PUBWEAK PVD_VDDIO2_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 PVD_VDDIO2_IRQHandler
         B PVD_VDDIO2_IRQHandler
         PUBWEAK RTC_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 RTC_IRQHandler
         B RTC_IRQHandler
         PUBWEAK FLASH_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 FLASH_IRQHandler
         B FLASH_IRQHandler
         PUBWEAK RCC_CRS_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 RCC_CRS_IRQHandler
         B RCC_CRS_IRQHandler
         PUBWEAK EXTI0_1_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 EXTI0_1_IRQHandler
         B EXTI0_1_IRQHandler
         PUBWEAK EXTI2_3_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 EXTI2_3_IRQHandler
         B EXTI2_3_IRQHandler
         PUBWEAK EXTI4_15_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 EXTI4_15_IRQHandler
         B EXTI4_15_IRQHandler
         PUBWEAK TSC_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TSC_IRQHandler
         B TSC_IRQHandler
         PUBWEAK DMA1_Channel1_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 DMA1_Channel1_IRQHandler
         B DMA1_Channel1_IRQHandler
         PUBWEAK DMA1_Channel2_3_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 DMA1_Channel2_3_IRQHandler
         B DMA1_Channel2_3_IRQHandler
         PUBWEAK DMA1_Channel4_5_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 DMA1_Channel4_5_IRQHandler
         B DMA1_Channel4_5_IRQHandler
         PUBWEAK ADC1_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 ADC1_IRQHandler
         B ADC1_IRQHandler
         PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM1_BRK_UP_TRG_COM_IRQHandler
         B TIM1_BRK_UP_TRG_COM_IRQHandler
         PUBWEAK TIM1_CC_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM1_CC_IRQHandler
         B TIM1_CC_IRQHandler
         PUBWEAK TIM2_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM2_IRQHandler
         B TIM2_IRQHandler
         PUBWEAK TIM3_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM3_IRQHandler
         B TIM3_IRQHandler
         PUBWEAK TIM14_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM14_IRQHandler
         B TIM14_IRQHandler
         PUBWEAK TIM16_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM16_IRQHandler
         B TIM16_IRQHandler
         PUBWEAK TIM17_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM17_IRQHandler
         B TIM17_IRQHandler
         PUBWEAK I2C1_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 I2C1_IRQHandler
         B I2C1_IRQHandler
         PUBWEAK SPI1_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 SPI1_IRQHandler
         B SPI1_IRQHandler
         PUBWEAK SPI2_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 SPI2_IRQHandler
         B SPI2_IRQHandler
         PUBWEAK USART1_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 USART1_IRQHandler
         B USART1_IRQHandler
         PUBWEAK USART2_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 USART2_IRQHandler
         B USART2_IRQHandler
         PUBWEAK CEC_CAN_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 CEC_CAN_IRQHandler
         B CEC_CAN_IRQHandler
         PUBWEAK USB_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 USB_IRQHandler
         B USB_IRQHandler
         END
 ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f051.s

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Show inline comments

@@ new file 100644 @@
 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
 ;* File Name          : startup_stm32f051.s
 ;* Author             : MCD Application Team
 ;* Version            : V1.4.0
 ;* Date               : 24-July-2014
 ;* Description        : STM32F051 devices vector table for EWARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
 ;*                      - Set the initial PC == iar_program_start,
 ;*                      - Set the vector table entries with the exceptions ISR
 ;*                        address
 ;*                      - Configure the system clock
 ;*                      - Branches to main in the C library (which eventually
 ;*                        calls main()).
 ;*                      After Reset the Cortex-M0 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;*******************************************************************************
 ;  @attention
+;
 ;  Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 ;  You may not use this file except in compliance with the License.
 ;  You may obtain a copy of the License at:
+;
 ;         http://www.st.com/software_license_agreement_liberty_v2
+;
 ;  Unless required by applicable law or agreed to in writing, software
 ;  distributed under the License is distributed on an "AS IS" BASIS,
 ;  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 ;  See the License for the specific language governing permissions and
 ;  limitations under the License.
+;
 ;*******************************************************************************
+;
+;
 ; The modules in this file are included in the libraries, and may be replaced
 ; by any user-defined modules that define the PUBLIC symbol _program_start or
 ; a user defined start symbol.
 ; To override the cstartup defined in the library, simply add your modified
 ; version to the workbench project.
+;
 ; The vector table is normally located at address 0.
 ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
 ; The name "__vector_table" has special meaning for C-SPY:
 ; it is where the SP start value is found, and the NVIC vector
 ; table register (VTOR) is initialized to this address if != 0.
+;
 ; Cortex-M version
+;
         MODULE  ?cstartup
         ;; Forward declaration of sections.
         SECTION CSTACK:DATA:NOROOT(3)
         SECTION .intvec:CODE:NOROOT(2)
         EXTERN  __iar_program_start
         EXTERN  SystemInit
         PUBLIC  __vector_table
         DATA
 __vector_table
         DCD     sfe(CSTACK)
         DCD     Reset_Handler                  ; Reset Handler
         DCD     NMI_Handler                    ; NMI Handler
         DCD     HardFault_Handler              ; Hard Fault Handler
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     SVC_Handler                    ; SVCall Handler
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     PendSV_Handler                 ; PendSV Handler
         DCD     SysTick_Handler                ; SysTick Handler
         ; External Interrupts
         DCD     WWDG_IRQHandler                ; Window Watchdog
         DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
         DCD     RTC_IRQHandler                 ; RTC through EXTI Line
         DCD     FLASH_IRQHandler               ; FLASH
         DCD     RCC_IRQHandler                 ; RCC
         DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
         DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
         DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
         DCD     TS_IRQHandler                  ; TS
         DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
         DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
         DCD     DMA1_Channel4_5_IRQHandler     ; DMA1 Channel 4 and Channel 5
         DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2
         DCD     TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
         DCD     TIM1_CC_IRQHandler             ; TIM1 Capture Compare
         DCD     TIM2_IRQHandler                ; TIM2
         DCD     TIM3_IRQHandler                ; TIM3
         DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
         DCD     0                              ; Reserved
         DCD     TIM14_IRQHandler               ; TIM14
         DCD     TIM15_IRQHandler               ; TIM15
         DCD     TIM16_IRQHandler               ; TIM16
         DCD     TIM17_IRQHandler               ; TIM17
         DCD     I2C1_IRQHandler                ; I2C1
         DCD     I2C2_IRQHandler                ; I2C2
         DCD     SPI1_IRQHandler                ; SPI1
         DCD     SPI2_IRQHandler                ; SPI2
         DCD     USART1_IRQHandler              ; USART1
         DCD     USART2_IRQHandler              ; USART2
         DCD     0                              ; Reserved
         DCD     CEC_IRQHandler                 ; CEC
         DCD     0                              ; Reserved
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;;
 ;; Default interrupt handlers.
 ;;
         THUMB
         PUBWEAK Reset_Handler
         SECTION .text:CODE:NOROOT:REORDER(2)
 Reset_Handler
         LDR     R0, =sfe(CSTACK)          ; set stack pointer
         MSR     MSP, R0
 ;;Check if boot space corresponds to test memory
         LDR R0,=0x00000004
         LDR R1, [R0]
         LSRS R1, R1, #24
         LDR R2,=0x1F
         CMP R1, R2
         BNE ApplicationStart
 ;; SYSCFG clock enable
         LDR R0,=0x40021018
         LDR R1,=0x00000001
         STR R1, [R0]
 ;; Set CFGR1 register with flash memory remap at address 0
         LDR R0,=0x40010000
         LDR R1,=0x00000000
         STR R1, [R0]
 ApplicationStart
         LDR     R0, =SystemInit
         BLX     R0
         LDR     R0, =__iar_program_start
         BX      R0
         PUBWEAK NMI_Handler
         SECTION .text:CODE:NOROOT:REORDER(1)
 NMI_Handler
         B NMI_Handler
         PUBWEAK HardFault_Handler
         SECTION .text:CODE:NOROOT:REORDER(1)
 HardFault_Handler
         B HardFault_Handler
         PUBWEAK SVC_Handler
         SECTION .text:CODE:NOROOT:REORDER(1)
 SVC_Handler
         B SVC_Handler
         PUBWEAK PendSV_Handler
         SECTION .text:CODE:NOROOT:REORDER(1)
 PendSV_Handler
         B PendSV_Handler
         PUBWEAK SysTick_Handler
         SECTION .text:CODE:NOROOT:REORDER(1)
 SysTick_Handler
         B SysTick_Handler
         PUBWEAK WWDG_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 WWDG_IRQHandler
         B WWDG_IRQHandler
         PUBWEAK PVD_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 PVD_IRQHandler
         B PVD_IRQHandler
         PUBWEAK RTC_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 RTC_IRQHandler
         B RTC_IRQHandler
         PUBWEAK FLASH_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 FLASH_IRQHandler
         B FLASH_IRQHandler
         PUBWEAK RCC_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 RCC_IRQHandler
         B RCC_IRQHandler
         PUBWEAK EXTI0_1_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 EXTI0_1_IRQHandler
         B EXTI0_1_IRQHandler
         PUBWEAK EXTI2_3_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 EXTI2_3_IRQHandler
         B EXTI2_3_IRQHandler
         PUBWEAK EXTI4_15_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 EXTI4_15_IRQHandler
         B EXTI4_15_IRQHandler
         PUBWEAK TS_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TS_IRQHandler
         B TS_IRQHandler
         PUBWEAK DMA1_Channel1_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 DMA1_Channel1_IRQHandler
         B DMA1_Channel1_IRQHandler
         PUBWEAK DMA1_Channel2_3_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 DMA1_Channel2_3_IRQHandler
         B DMA1_Channel2_3_IRQHandler
         PUBWEAK DMA1_Channel4_5_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 DMA1_Channel4_5_IRQHandler
         B DMA1_Channel4_5_IRQHandler
         PUBWEAK ADC1_COMP_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 ADC1_COMP_IRQHandler
         B ADC1_COMP_IRQHandler
         PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM1_BRK_UP_TRG_COM_IRQHandler
         B TIM1_BRK_UP_TRG_COM_IRQHandler
         PUBWEAK TIM1_CC_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM1_CC_IRQHandler
         B TIM1_CC_IRQHandler
         PUBWEAK TIM2_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM2_IRQHandler
         B TIM2_IRQHandler
         PUBWEAK TIM3_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM3_IRQHandler
         B TIM3_IRQHandler
         PUBWEAK TIM6_DAC_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM6_DAC_IRQHandler
         B TIM6_DAC_IRQHandler
         PUBWEAK TIM14_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM14_IRQHandler
         B TIM14_IRQHandler
         PUBWEAK TIM15_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM15_IRQHandler
         B TIM15_IRQHandler
         PUBWEAK TIM16_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM16_IRQHandler
         B TIM16_IRQHandler
         PUBWEAK TIM17_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM17_IRQHandler
         B TIM17_IRQHandler
         PUBWEAK I2C1_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 I2C1_IRQHandler
         B I2C1_IRQHandler
         PUBWEAK I2C2_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 I2C2_IRQHandler
         B I2C2_IRQHandler
         PUBWEAK SPI1_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 SPI1_IRQHandler
         B SPI1_IRQHandler
         PUBWEAK SPI2_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 SPI2_IRQHandler
         B SPI2_IRQHandler
         PUBWEAK USART1_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 USART1_IRQHandler
         B USART1_IRQHandler
         PUBWEAK USART2_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 USART2_IRQHandler
         B USART2_IRQHandler
         PUBWEAK CEC_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 CEC_IRQHandler
         B CEC_IRQHandler
         END
 ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f072.s

➞

Show inline comments

@@ new file 100644 @@
 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
 ;* File Name          : startup_stm32f072.s
 ;* Author             : MCD Appl&ication Team
 ;* Version            : V1.4.0
 ;* Date               : 24-July-2014
 ;* Description        : STM32F072 Devices Devices vector table for
 ;*                      EWARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
 ;*                      - Set the initial PC == iar_program_start,
 ;*                      - Set the vector table entries with the exceptions ISR
 ;*                        address.
 ;*                      After Reset the Cortex-M0 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;*******************************************************************************
 ;  @attention
+;
 ;  Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 ;  You may not use this file except in compliance with the License.
 ;  You may obtain a copy of the License at:
+;
 ;         http://www.st.com/software_license_agreement_liberty_v2
+;
 ;  Unless required by applicable law or agreed to in writing, software
 ;  distributed under the License is distributed on an "AS IS" BASIS,
 ;  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 ;  See the License for the specific language governing permissions and
 ;  limitations under the License.
+;
 ;*******************************************************************************
+;
+;
 ; The modules in this file are included in the libraries, and may be replaced
 ; by any user-defined modules that define the PUBLIC symbol _program_start or
 ; a user defined start symbol.
 ; To override the cstartup defined in the library, simply add your modified
 ; version to the workbench project.
+;
 ; The vector table is normally located at address 0.
 ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
 ; The name "__vector_table" has special meaning for C-SPY:
 ; it is where the SP start value is found, and the NVIC vector
 ; table register (VTOR) is initialized to this address if != 0.
+;
 ; Cortex-M version
+;
         MODULE  ?cstartup
         ;; Forward declaration of sections.
         SECTION CSTACK:DATA:NOROOT(3)
         SECTION .intvec:CODE:NOROOT(2)
         EXTERN  __iar_program_start
         EXTERN  SystemInit
         PUBLIC  __vector_table
         DATA
 __vector_table
         DCD     sfe(CSTACK)
         DCD     Reset_Handler                  ; Reset Handler
         DCD     NMI_Handler                    ; NMI Handler
         DCD     HardFault_Handler              ; Hard Fault Handler
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     SVC_Handler                    ; SVCall Handler
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     PendSV_Handler                 ; PendSV Handler
         DCD     SysTick_Handler                ; SysTick Handler
         ; External Interrupts
         DCD     WWDG_IRQHandler                ; Window Watchdog
         DCD     PVD_VDDIO2_IRQHandler          ; PVD and VDDIO2 through EXTI Line detect
         DCD     RTC_IRQHandler                 ; RTC through EXTI Line
         DCD     FLASH_IRQHandler               ; FLASH
         DCD     RCC_CRS_IRQHandler             ; RCC and CRS
         DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
         DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
         DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
         DCD     TSC_IRQHandler                  ; TS
         DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
         DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
         DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
         DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2
         DCD     TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
         DCD     TIM1_CC_IRQHandler             ; TIM1 Capture Compare
         DCD     TIM2_IRQHandler                ; TIM2
         DCD     TIM3_IRQHandler                ; TIM3
         DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
         DCD     TIM7_IRQHandler                ; TIM7
         DCD     TIM14_IRQHandler               ; TIM14
         DCD     TIM15_IRQHandler               ; TIM15
         DCD     TIM16_IRQHandler               ; TIM16
         DCD     TIM17_IRQHandler               ; TIM17
         DCD     I2C1_IRQHandler                ; I2C1
         DCD     I2C2_IRQHandler                ; I2C2
         DCD     SPI1_IRQHandler                ; SPI1
         DCD     SPI2_IRQHandler                ; SPI2
         DCD     USART1_IRQHandler              ; USART1
         DCD     USART2_IRQHandler              ; USART2
         DCD     USART3_4_IRQHandler            ; USART3 and USART4
         DCD     CEC_CAN_IRQHandler             ; CEC and CAN
         DCD     USB_IRQHandler                 ; USB
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;;
 ;; Default interrupt handlers.
 ;;
         THUMB
         PUBWEAK Reset_Handler
         SECTION .text:CODE:NOROOT:REORDER(2)
 Reset_Handler
         LDR     R0, =sfe(CSTACK)          ; set stack pointer
         MSR     MSP, R0
 ;;Check if boot space corresponds to test memory
         LDR R0,=0x00000004
         LDR R1, [R0]
         LSRS R1, R1, #24
         LDR R2,=0x1F
         CMP R1, R2
         BNE ApplicationStart
 ;; SYSCFG clock enable
         LDR R0,=0x40021018
         LDR R1,=0x00000001
         STR R1, [R0]
 ;; Set CFGR1 register with flash memory remap at address 0
         LDR R0,=0x40010000
         LDR R1,=0x00000000
         STR R1, [R0]
 ApplicationStart
         LDR     R0, =SystemInit
         BLX     R0
         LDR     R0, =__iar_program_start
         BX      R0
         PUBWEAK NMI_Handler
         SECTION .text:CODE:NOROOT:REORDER(1)
 NMI_Handler
         B NMI_Handler
         PUBWEAK HardFault_Handler
         SECTION .text:CODE:NOROOT:REORDER(1)
 HardFault_Handler
         B HardFault_Handler
         PUBWEAK SVC_Handler
         SECTION .text:CODE:NOROOT:REORDER(1)
 SVC_Handler
         B SVC_Handler
         PUBWEAK PendSV_Handler
         SECTION .text:CODE:NOROOT:REORDER(1)
 PendSV_Handler
         B PendSV_Handler
         PUBWEAK SysTick_Handler
         SECTION .text:CODE:NOROOT:REORDER(1)
 SysTick_Handler
         B SysTick_Handler
         PUBWEAK WWDG_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 WWDG_IRQHandler
         B WWDG_IRQHandler
         PUBWEAK PVD_VDDIO2_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 PVD_VDDIO2_IRQHandler
         B PVD_VDDIO2_IRQHandler
         PUBWEAK RTC_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 RTC_IRQHandler
         B RTC_IRQHandler
         PUBWEAK FLASH_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 FLASH_IRQHandler
         B FLASH_IRQHandler
         PUBWEAK RCC_CRS_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 RCC_CRS_IRQHandler
         B RCC_CRS_IRQHandler
         PUBWEAK EXTI0_1_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 EXTI0_1_IRQHandler
         B EXTI0_1_IRQHandler
         PUBWEAK EXTI2_3_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 EXTI2_3_IRQHandler
         B EXTI2_3_IRQHandler
         PUBWEAK EXTI4_15_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 EXTI4_15_IRQHandler
         B EXTI4_15_IRQHandler
         PUBWEAK TSC_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TSC_IRQHandler
         B TSC_IRQHandler
         PUBWEAK DMA1_Channel1_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 DMA1_Channel1_IRQHandler
         B DMA1_Channel1_IRQHandler
         PUBWEAK DMA1_Channel2_3_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 DMA1_Channel2_3_IRQHandler
         B DMA1_Channel2_3_IRQHandler
         PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 DMA1_Channel4_5_6_7_IRQHandler
         B DMA1_Channel4_5_6_7_IRQHandler
         PUBWEAK ADC1_COMP_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 ADC1_COMP_IRQHandler
         B ADC1_COMP_IRQHandler
         PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM1_BRK_UP_TRG_COM_IRQHandler
         B TIM1_BRK_UP_TRG_COM_IRQHandler
         PUBWEAK TIM1_CC_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM1_CC_IRQHandler
         B TIM1_CC_IRQHandler
         PUBWEAK TIM2_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM2_IRQHandler
         B TIM2_IRQHandler
         PUBWEAK TIM3_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM3_IRQHandler
         B TIM3_IRQHandler
         PUBWEAK TIM6_DAC_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM6_DAC_IRQHandler
         B TIM6_DAC_IRQHandler
         PUBWEAK TIM7_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM7_IRQHandler
         B TIM7_IRQHandler
         PUBWEAK TIM14_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM14_IRQHandler
         B TIM14_IRQHandler
         PUBWEAK TIM15_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM15_IRQHandler
         B TIM15_IRQHandler
         PUBWEAK TIM16_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM16_IRQHandler
         B TIM16_IRQHandler
         PUBWEAK TIM17_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM17_IRQHandler
         B TIM17_IRQHandler
         PUBWEAK I2C1_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 I2C1_IRQHandler
         B I2C1_IRQHandler
         PUBWEAK I2C2_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 I2C2_IRQHandler
         B I2C2_IRQHandler
         PUBWEAK SPI1_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 SPI1_IRQHandler
         B SPI1_IRQHandler
         PUBWEAK SPI2_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 SPI2_IRQHandler
         B SPI2_IRQHandler
         PUBWEAK USART1_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 USART1_IRQHandler
         B USART1_IRQHandler
         PUBWEAK USART2_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 USART2_IRQHandler
         B USART2_IRQHandler
         PUBWEAK USART3_4_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 USART3_4_IRQHandler
         B USART3_4_IRQHandler
         PUBWEAK CEC_CAN_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 CEC_CAN_IRQHandler
         B CEC_CAN_IRQHandler
         PUBWEAK USB_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 USB_IRQHandler
         B USB_IRQHandler
         END
 ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f091.s

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@@ new file 100644 @@
 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
 ;* File Name          : startup_stm32f091.s
 ;* Author             : MCD Application Team
 ;* Version            : V1.4.0
 ;* Date               : 24-July-2014
 ;* Description        : STM32F091xc devices vector table for EWARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
 ;*                      - Set the initial PC == __iar_program_start,
 ;*                      - Set the vector table entries with the exceptions ISR
 ;*                        address,
 ;*                      - Branches to main in the C library (which eventually
 ;*                        calls main()).
 ;*                      After Reset the Cortex-M0 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;*******************************************************************************
 ;*
 ;* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
 ;*
 ;* Redistribution and use in source and binary forms, with or without modification,
 ;* are permitted provided that the following conditions are met:
 ;*   1. Redistributions of source code must retain the above copyright notice,
 ;*      this list of conditions and the following disclaimer.
 ;*   2. Redistributions in binary form must reproduce the above copyright notice,
 ;*      this list of conditions and the following disclaimer in the documentation
 ;*      and/or other materials provided with the distribution.
 ;*   3. Neither the name of STMicroelectronics nor the names of its contributors
 ;*      may be used to endorse or promote products derived from this software
 ;*      without specific prior written permission.
 ;*
 ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 ;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 ;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 ;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 ;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 ;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 ;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 ;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 ;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 ;*
 ;*******************************************************************************
+;
+;
 ; The modules in this file are included in the libraries, and may be replaced
 ; by any user-defined modules that define the PUBLIC symbol _program_start or
 ; a user defined start symbol.
 ; To override the cstartup defined in the library, simply add your modified
 ; version to the workbench project.
+;
 ; The vector table is normally located at address 0.
 ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
 ; The name "__vector_table" has special meaning for C-SPY:
 ; it is where the SP start value is found, and the NVIC vector
 ; table register (VTOR) is initialized to this address if != 0.
+;
 ; Cortex-M version
+;
         MODULE  ?cstartup
         ;; Forward declaration of sections.
         SECTION CSTACK:DATA:NOROOT(3)
         SECTION .intvec:CODE:NOROOT(2)
         EXTERN  __iar_program_start
         EXTERN  SystemInit
         PUBLIC  __vector_table
         DATA
 __vector_table
         DCD     sfe(CSTACK)
         DCD     Reset_Handler                  ; Reset Handler
         DCD     NMI_Handler                    ; NMI Handler
         DCD     HardFault_Handler              ; Hard Fault Handler
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     SVC_Handler                    ; SVCall Handler
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     PendSV_Handler                 ; PendSV Handler
         DCD     SysTick_Handler                ; SysTick Handler
         ; External Interrupts
         DCD     WWDG_IRQHandler                ; Window Watchdog
         DCD     PVD_VDDIO2_IRQHandler          ; PVD and VDDIO2 through EXTI Line detect
         DCD     RTC_IRQHandler                 ; RTC through EXTI Line
         DCD     FLASH_IRQHandler               ; FLASH
         DCD     RCC_CRS_IRQHandler             ; RCC and CRS
         DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
         DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
         DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
         DCD     TSC_IRQHandler                 ; TS
         DCD     DMA1_Ch1_IRQHandler       		 ; DMA1 Channel 1
         DCD     DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler ; DMA1 Channel 2 and 3 & DMA2 Channel 1 and 2
         DCD     DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler ; DMA1 Channel 4 to 7 & DMA2 Channel 3 to 5
         DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2
         DCD     TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
         DCD     TIM1_CC_IRQHandler             ; TIM1 Capture Compare
         DCD     TIM2_IRQHandler                ; TIM2
         DCD     TIM3_IRQHandler                ; TIM3
         DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
         DCD     TIM7_IRQHandler                ; TIM7
         DCD     TIM14_IRQHandler               ; TIM14
         DCD     TIM15_IRQHandler               ; TIM15
         DCD     TIM16_IRQHandler               ; TIM16
         DCD     TIM17_IRQHandler               ; TIM17
         DCD     I2C1_IRQHandler                ; I2C1
         DCD     I2C2_IRQHandler                ; I2C2
         DCD     SPI1_IRQHandler                ; SPI1
         DCD     SPI2_IRQHandler                ; SPI2
         DCD     USART1_IRQHandler              ; USART1
         DCD     USART2_IRQHandler              ; USART2
         DCD     USART3_8_IRQHandler    				 ; USART3, USART4, USART5, USART6, USART7, USART8
         DCD     CEC_CAN_IRQHandler             ; CEC and CAN
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;;
 ;; Default interrupt handlers.
 ;;
         THUMB
         PUBWEAK Reset_Handler
         SECTION .text:CODE:NOROOT:REORDER(2)
 Reset_Handler
         LDR     R0, =SystemInit
         BLX     R0
         LDR     R0, =__iar_program_start
         BX      R0
         PUBWEAK NMI_Handler
         SECTION .text:CODE:NOROOT:REORDER(1)
 NMI_Handler
         B NMI_Handler
         PUBWEAK HardFault_Handler
         SECTION .text:CODE:NOROOT:REORDER(1)
 HardFault_Handler
         B HardFault_Handler
         PUBWEAK SVC_Handler
         SECTION .text:CODE:NOROOT:REORDER(1)
 SVC_Handler
         B SVC_Handler
         PUBWEAK PendSV_Handler
         SECTION .text:CODE:NOROOT:REORDER(1)
 PendSV_Handler
         B PendSV_Handler
         PUBWEAK SysTick_Handler
         SECTION .text:CODE:NOROOT:REORDER(1)
 SysTick_Handler
         B SysTick_Handler
         PUBWEAK WWDG_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 WWDG_IRQHandler
         B WWDG_IRQHandler
         PUBWEAK PVD_VDDIO2_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 PVD_VDDIO2_IRQHandler
         B PVD_VDDIO2_IRQHandler
         PUBWEAK RTC_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 RTC_IRQHandler
         B RTC_IRQHandler
         PUBWEAK FLASH_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 FLASH_IRQHandler
         B FLASH_IRQHandler
         PUBWEAK RCC_CRS_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 RCC_CRS_IRQHandler
         B RCC_CRS_IRQHandler
         PUBWEAK EXTI0_1_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 EXTI0_1_IRQHandler
         B EXTI0_1_IRQHandler
         PUBWEAK EXTI2_3_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 EXTI2_3_IRQHandler
         B EXTI2_3_IRQHandler
         PUBWEAK EXTI4_15_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 EXTI4_15_IRQHandler
         B EXTI4_15_IRQHandler
         PUBWEAK TSC_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TSC_IRQHandler
         B TSC_IRQHandler
         PUBWEAK DMA1_Ch1_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 DMA1_Ch1_IRQHandler
         B DMA1_Ch1_IRQHandler
         PUBWEAK DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
         B DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
         PUBWEAK DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
         B DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
         PUBWEAK ADC1_COMP_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 ADC1_COMP_IRQHandler
         B ADC1_COMP_IRQHandler
         PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM1_BRK_UP_TRG_COM_IRQHandler
         B TIM1_BRK_UP_TRG_COM_IRQHandler
         PUBWEAK TIM1_CC_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM1_CC_IRQHandler
         B TIM1_CC_IRQHandler
         PUBWEAK TIM2_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM2_IRQHandler
         B TIM2_IRQHandler
         PUBWEAK TIM3_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM3_IRQHandler
         B TIM3_IRQHandler
         PUBWEAK TIM6_DAC_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM6_DAC_IRQHandler
         B TIM6_DAC_IRQHandler
         PUBWEAK TIM7_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM7_IRQHandler
         B TIM7_IRQHandler
         PUBWEAK TIM14_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM14_IRQHandler
         B TIM14_IRQHandler
         PUBWEAK TIM15_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM15_IRQHandler
         B TIM15_IRQHandler
         PUBWEAK TIM16_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM16_IRQHandler
         B TIM16_IRQHandler
         PUBWEAK TIM17_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM17_IRQHandler
         B TIM17_IRQHandler
         PUBWEAK I2C1_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 I2C1_IRQHandler
         B I2C1_IRQHandler
         PUBWEAK I2C2_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 I2C2_IRQHandler
         B I2C2_IRQHandler
         PUBWEAK SPI1_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 SPI1_IRQHandler
         B SPI1_IRQHandler
         PUBWEAK SPI2_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 SPI2_IRQHandler
         B SPI2_IRQHandler
         PUBWEAK USART1_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 USART1_IRQHandler
         B USART1_IRQHandler
         PUBWEAK USART2_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 USART2_IRQHandler
         B USART2_IRQHandler
         PUBWEAK USART3_8_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 USART3_8_IRQHandler
         B USART3_8_IRQHandler
         PUBWEAK CEC_CAN_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 CEC_CAN_IRQHandler
         B CEC_CAN_IRQHandler
         END
 ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f0xx.s

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@@ new file 100644 @@
 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
 ;* File Name          : startup_stm32f0xx.s
 ;* Author             : MCD Application Team
 ;* Version            : V1.4.0
 ;* Date               : 24-July-2014
 ;* Description        : STM32F051 devices vector table for EWARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
 ;*                      - Set the initial PC == iar_program_start,
 ;*                      - Set the vector table entries with the exceptions ISR
 ;*                        address
 ;*                      - Configure the system clock
 ;*                      - Branches to main in the C library (which eventually
 ;*                        calls main()).
 ;*                      After Reset the Cortex-M0 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;*******************************************************************************
 ;  @attention
+;
 ;  Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 ;  You may not use this file except in compliance with the License.
 ;  You may obtain a copy of the License at:
+;
 ;         http://www.st.com/software_license_agreement_liberty_v2
+;
 ;  Unless required by applicable law or agreed to in writing, software
 ;  distributed under the License is distributed on an "AS IS" BASIS,
 ;  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 ;  See the License for the specific language governing permissions and
 ;  limitations under the License.
+;
 ;*******************************************************************************
+;
+;
 ; The modules in this file are included in the libraries, and may be replaced
 ; by any user-defined modules that define the PUBLIC symbol _program_start or
 ; a user defined start symbol.
 ; To override the cstartup defined in the library, simply add your modified
 ; version to the workbench project.
+;
 ; The vector table is normally located at address 0.
 ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
 ; The name "__vector_table" has special meaning for C-SPY:
 ; it is where the SP start value is found, and the NVIC vector
 ; table register (VTOR) is initialized to this address if != 0.
+;
 ; Cortex-M version
+;
         MODULE  ?cstartup
         ;; Forward declaration of sections.
         SECTION CSTACK:DATA:NOROOT(3)
         SECTION .intvec:CODE:NOROOT(2)
         EXTERN  __iar_program_start
         EXTERN  SystemInit
         PUBLIC  __vector_table
         DATA
 __vector_table
         DCD     sfe(CSTACK)
         DCD     Reset_Handler                  ; Reset Handler
         DCD     NMI_Handler                    ; NMI Handler
         DCD     HardFault_Handler              ; Hard Fault Handler
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     SVC_Handler                    ; SVCall Handler
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     PendSV_Handler                 ; PendSV Handler
         DCD     SysTick_Handler                ; SysTick Handler
         ; External Interrupts
         DCD     WWDG_IRQHandler                ; Window Watchdog
         DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
         DCD     RTC_IRQHandler                 ; RTC through EXTI Line
         DCD     FLASH_IRQHandler               ; FLASH
         DCD     RCC_IRQHandler                 ; RCC
         DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
         DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
         DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
         DCD     TS_IRQHandler                  ; TS
         DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
         DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
         DCD     DMA1_Channel4_5_IRQHandler     ; DMA1 Channel 4 and Channel 5
         DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2
         DCD     TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
         DCD     TIM1_CC_IRQHandler             ; TIM1 Capture Compare
         DCD     TIM2_IRQHandler                ; TIM2
         DCD     TIM3_IRQHandler                ; TIM3
         DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
         DCD     0                              ; Reserved
         DCD     TIM14_IRQHandler               ; TIM14
         DCD     TIM15_IRQHandler               ; TIM15
         DCD     TIM16_IRQHandler               ; TIM16
         DCD     TIM17_IRQHandler               ; TIM17
         DCD     I2C1_IRQHandler                ; I2C1
         DCD     I2C2_IRQHandler                ; I2C2
         DCD     SPI1_IRQHandler                ; SPI1
         DCD     SPI2_IRQHandler                ; SPI2
         DCD     USART1_IRQHandler              ; USART1
         DCD     USART2_IRQHandler              ; USART2
         DCD     0                              ; Reserved
         DCD     CEC_IRQHandler                 ; CEC
         DCD     0                              ; Reserved
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;;
 ;; Default interrupt handlers.
 ;;
         THUMB
         PUBWEAK Reset_Handler
         SECTION .text:CODE:NOROOT:REORDER(2)
 Reset_Handler
         LDR     R0, =sfe(CSTACK)          ; set stack pointer
         MSR     MSP, R0
 ;;Check if boot space corresponds to test memory
         LDR R0,=0x00000004
         LDR R1, [R0]
         LSRS R1, R1, #24
         LDR R2,=0x1F
         CMP R1, R2
         BNE ApplicationStart
 ;; SYSCFG clock enable
         LDR R0,=0x40021018
         LDR R1,=0x00000001
         STR R1, [R0]
 ;; Set CFGR1 register with flash memory remap at address 0
         LDR R0,=0x40010000
         LDR R1,=0x00000000
         STR R1, [R0]
 ApplicationStart
         LDR     R0, =SystemInit
         BLX     R0
         LDR     R0, =__iar_program_start
         BX      R0
         PUBWEAK NMI_Handler
         SECTION .text:CODE:NOROOT:REORDER(1)
 NMI_Handler
         B NMI_Handler
         PUBWEAK HardFault_Handler
         SECTION .text:CODE:NOROOT:REORDER(1)
 HardFault_Handler
         B HardFault_Handler
         PUBWEAK SVC_Handler
         SECTION .text:CODE:NOROOT:REORDER(1)
 SVC_Handler
         B SVC_Handler
         PUBWEAK PendSV_Handler
         SECTION .text:CODE:NOROOT:REORDER(1)
 PendSV_Handler
         B PendSV_Handler
         PUBWEAK SysTick_Handler
         SECTION .text:CODE:NOROOT:REORDER(1)
 SysTick_Handler
         B SysTick_Handler
         PUBWEAK WWDG_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 WWDG_IRQHandler
         B WWDG_IRQHandler
         PUBWEAK PVD_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 PVD_IRQHandler
         B PVD_IRQHandler
         PUBWEAK RTC_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 RTC_IRQHandler
         B RTC_IRQHandler
         PUBWEAK FLASH_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 FLASH_IRQHandler
         B FLASH_IRQHandler
         PUBWEAK RCC_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 RCC_IRQHandler
         B RCC_IRQHandler
         PUBWEAK EXTI0_1_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 EXTI0_1_IRQHandler
         B EXTI0_1_IRQHandler
         PUBWEAK EXTI2_3_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 EXTI2_3_IRQHandler
         B EXTI2_3_IRQHandler
         PUBWEAK EXTI4_15_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 EXTI4_15_IRQHandler
         B EXTI4_15_IRQHandler
         PUBWEAK TS_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TS_IRQHandler
         B TS_IRQHandler
         PUBWEAK DMA1_Channel1_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 DMA1_Channel1_IRQHandler
         B DMA1_Channel1_IRQHandler
         PUBWEAK DMA1_Channel2_3_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 DMA1_Channel2_3_IRQHandler
         B DMA1_Channel2_3_IRQHandler
         PUBWEAK DMA1_Channel4_5_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 DMA1_Channel4_5_IRQHandler
         B DMA1_Channel4_5_IRQHandler
         PUBWEAK ADC1_COMP_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 ADC1_COMP_IRQHandler
         B ADC1_COMP_IRQHandler
         PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM1_BRK_UP_TRG_COM_IRQHandler
         B TIM1_BRK_UP_TRG_COM_IRQHandler
         PUBWEAK TIM1_CC_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM1_CC_IRQHandler
         B TIM1_CC_IRQHandler
         PUBWEAK TIM2_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM2_IRQHandler
         B TIM2_IRQHandler
         PUBWEAK TIM3_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM3_IRQHandler
         B TIM3_IRQHandler
         PUBWEAK TIM6_DAC_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM6_DAC_IRQHandler
         B TIM6_DAC_IRQHandler
         PUBWEAK TIM14_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM14_IRQHandler
         B TIM14_IRQHandler
         PUBWEAK TIM15_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM15_IRQHandler
         B TIM15_IRQHandler
         PUBWEAK TIM16_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM16_IRQHandler
         B TIM16_IRQHandler
         PUBWEAK TIM17_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM17_IRQHandler
         B TIM17_IRQHandler
         PUBWEAK I2C1_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 I2C1_IRQHandler
         B I2C1_IRQHandler
         PUBWEAK I2C2_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 I2C2_IRQHandler
         B I2C2_IRQHandler
         PUBWEAK SPI1_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 SPI1_IRQHandler
         B SPI1_IRQHandler
         PUBWEAK SPI2_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 SPI2_IRQHandler
         B SPI2_IRQHandler
         PUBWEAK USART1_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 USART1_IRQHandler
         B USART1_IRQHandler
         PUBWEAK USART2_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 USART2_IRQHandler
         B USART2_IRQHandler
         PUBWEAK CEC_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 CEC_IRQHandler
         B CEC_IRQHandler
         END
 ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f0xx_ld.s

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@@ new file 100644 @@
 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
 ;* File Name          : startup_stm32f0xx_ld.s
 ;* Author             : MCD Application Team
 ;* Version            : V1.4.0
 ;* Date               : 24-July-2014
 ;* Description        : STM32F031 devices vector table for EWARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
 ;*                      - Set the initial PC == iar_program_start,
 ;*                      - Set the vector table entries with the exceptions ISR
 ;*                        address
 ;*                      - Configure the system clock
 ;*                      - Branches to main in the C library (which eventually
 ;*                        calls main()).
 ;*                      After Reset the Cortex-M0 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;*******************************************************************************
 ;  @attention
+;
 ;  Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 ;  You may not use this file except in compliance with the License.
 ;  You may obtain a copy of the License at:
+;
 ;         http://www.st.com/software_license_agreement_liberty_v2
+;
 ;  Unless required by applicable law or agreed to in writing, software
 ;  distributed under the License is distributed on an "AS IS" BASIS,
 ;  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 ;  See the License for the specific language governing permissions and
 ;  limitations under the License.
+;
 ;*******************************************************************************
+;
+;
 ; The modules in this file are included in the libraries, and may be replaced
 ; by any user-defined modules that define the PUBLIC symbol _program_start or
 ; a user defined start symbol.
 ; To override the cstartup defined in the library, simply add your modified
 ; version to the workbench project.
+;
 ; The vector table is normally located at address 0.
 ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
 ; The name "__vector_table" has special meaning for C-SPY:
 ; it is where the SP start value is found, and the NVIC vector
 ; table register (VTOR) is initialized to this address if != 0.
+;
 ; Cortex-M version
+;
         MODULE  ?cstartup
         ;; Forward declaration of sections.
         SECTION CSTACK:DATA:NOROOT(3)
         SECTION .intvec:CODE:NOROOT(2)
         EXTERN  __iar_program_start
         EXTERN  SystemInit
         PUBLIC  __vector_table
         DATA
 __vector_table
         DCD     sfe(CSTACK)
         DCD     Reset_Handler                  ; Reset Handler
         DCD     NMI_Handler                    ; NMI Handler
         DCD     HardFault_Handler              ; Hard Fault Handler
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     SVC_Handler                    ; SVCall Handler
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     PendSV_Handler                 ; PendSV Handler
         DCD     SysTick_Handler                ; SysTick Handler
         ; External Interrupts
         DCD     WWDG_IRQHandler                ; Window Watchdog
         DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
         DCD     RTC_IRQHandler                 ; RTC through EXTI Line
         DCD     FLASH_IRQHandler               ; FLASH
         DCD     RCC_IRQHandler                 ; RCC
         DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
         DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
         DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
         DCD     0                              ; Reserved
         DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
         DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
         DCD     DMA1_Channel4_5_IRQHandler     ; DMA1 Channel 4 and Channel 5
         DCD     ADC1_IRQHandler                ; ADC1
         DCD     TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
         DCD     TIM1_CC_IRQHandler             ; TIM1 Capture Compare
         DCD     TIM2_IRQHandler                ; TIM2
         DCD     TIM3_IRQHandler                ; TIM3
         DCD     0                              ; Reserved
         DCD     0                              ; Reserved
         DCD     TIM14_IRQHandler               ; TIM14
         DCD     0                              ; Reserved
         DCD     TIM16_IRQHandler               ; TIM16
         DCD     TIM17_IRQHandler               ; TIM17
         DCD     I2C1_IRQHandler                ; I2C1
         DCD     0                              ; Reserved
         DCD     SPI1_IRQHandler                ; SPI1
         DCD     0                              ; Reserved
         DCD     USART1_IRQHandler              ; USART1
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;;
 ;; Default interrupt handlers.
 ;;
         THUMB
         PUBWEAK Reset_Handler
         SECTION .text:CODE:NOROOT:REORDER(2)
 Reset_Handler
         LDR     R0, =sfe(CSTACK)          ; set stack pointer
         MSR     MSP, R0
 ;;Check if boot space corresponds to test memory
         LDR R0,=0x00000004
         LDR R1, [R0]
         LSRS R1, R1, #24
         LDR R2,=0x1F
         CMP R1, R2
         BNE ApplicationStart
 ;; SYSCFG clock enable
         LDR R0,=0x40021018
         LDR R1,=0x00000001
         STR R1, [R0]
 ;; Set CFGR1 register with flash memory remap at address 0
         LDR R0,=0x40010000
         LDR R1,=0x00000000
         STR R1, [R0]
 ApplicationStart
         LDR     R0, =SystemInit
         BLX     R0
         LDR     R0, =__iar_program_start
         BX      R0
         PUBWEAK NMI_Handler
         SECTION .text:CODE:NOROOT:REORDER(1)
 NMI_Handler
         B NMI_Handler
         PUBWEAK HardFault_Handler
         SECTION .text:CODE:NOROOT:REORDER(1)
 HardFault_Handler
         B HardFault_Handler
         PUBWEAK SVC_Handler
         SECTION .text:CODE:NOROOT:REORDER(1)
 SVC_Handler
         B SVC_Handler
         PUBWEAK PendSV_Handler
         SECTION .text:CODE:NOROOT:REORDER(1)
 PendSV_Handler
         B PendSV_Handler
         PUBWEAK SysTick_Handler
         SECTION .text:CODE:NOROOT:REORDER(1)
 SysTick_Handler
         B SysTick_Handler
         PUBWEAK WWDG_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 WWDG_IRQHandler
         B WWDG_IRQHandler
         PUBWEAK PVD_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 PVD_IRQHandler
         B PVD_IRQHandler
         PUBWEAK RTC_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 RTC_IRQHandler
         B RTC_IRQHandler
         PUBWEAK FLASH_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 FLASH_IRQHandler
         B FLASH_IRQHandler
         PUBWEAK RCC_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 RCC_IRQHandler
         B RCC_IRQHandler
         PUBWEAK EXTI0_1_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 EXTI0_1_IRQHandler
         B EXTI0_1_IRQHandler
         PUBWEAK EXTI2_3_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 EXTI2_3_IRQHandler
         B EXTI2_3_IRQHandler
         PUBWEAK EXTI4_15_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 EXTI4_15_IRQHandler
         B EXTI4_15_IRQHandler
         PUBWEAK DMA1_Channel1_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 DMA1_Channel1_IRQHandler
         B DMA1_Channel1_IRQHandler
         PUBWEAK DMA1_Channel2_3_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 DMA1_Channel2_3_IRQHandler
         B DMA1_Channel2_3_IRQHandler
         PUBWEAK DMA1_Channel4_5_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 DMA1_Channel4_5_IRQHandler
         B DMA1_Channel4_5_IRQHandler
         PUBWEAK ADC1_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 ADC1_IRQHandler
         B ADC1_IRQHandler
         PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM1_BRK_UP_TRG_COM_IRQHandler
         B TIM1_BRK_UP_TRG_COM_IRQHandler
         PUBWEAK TIM1_CC_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM1_CC_IRQHandler
         B TIM1_CC_IRQHandler
         PUBWEAK TIM2_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM2_IRQHandler
         B TIM2_IRQHandler
         PUBWEAK TIM3_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM3_IRQHandler
         B TIM3_IRQHandler
         PUBWEAK TIM14_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM14_IRQHandler
         B TIM14_IRQHandler
         PUBWEAK TIM16_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM16_IRQHandler
         B TIM16_IRQHandler
         PUBWEAK TIM17_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 TIM17_IRQHandler
         B TIM17_IRQHandler
         PUBWEAK I2C1_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 I2C1_IRQHandler
         B I2C1_IRQHandler
         PUBWEAK SPI1_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 SPI1_IRQHandler
         B SPI1_IRQHandler
         PUBWEAK USART1_IRQHandler
         SECTION .text:CODE:NOROOT:REORDER(1)
 USART1_IRQHandler
         B USART1_IRQHandler
         END
 ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/system_stm32f0xx.c

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 /**
   ******************************************************************************
   * @file    system_stm32f0xx.c
   * @author  MCD Application Team
   * @version V1.4.0
   * @date    24-July-2014
   * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
   *          This file contains the system clock configuration for STM32F0xx devices,
   *          and is generated by the clock configuration tool
   *          STM32F0xx_Clock_Configuration_V1.0.0.xls
+  *
   * 1.  This file provides two functions and one global variable to be called from
   *     user application:
   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
   *                      and Divider factors, AHB/APBx prescalers and Flash settings),
   *                      depending on the configuration made in the clock xls tool.
   *                      This function is called at startup just after reset and
   *                      before branch to main program. This call is made inside
   *                      the "startup_stm32f0xx.s" file.
+  *
   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
   *                                  by the user application to setup the SysTick
   *                                  timer or configure other parameters.
+  *
   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
   *                                 be called whenever the core clock is changed
   *                                 during program execution.
+  *
   * 2. After each device reset the HSI (8 MHz Range) is used as system clock source.
   *    Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
   *    configure the system clock before to branch to main program.
+  *
   * 3. If the system clock source selected by user fails to startup, the SystemInit()
   *    function will do nothing and HSI still used as system clock source. User can
   *    add some code to deal with this issue inside the SetSysClock() function.
+  *
   * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
   *    in "stm32f0xx.h" file. When HSE is used as system clock source, directly or
   *    through PLL, and you are using different crystal you have to adapt the HSE
   *    value to your own configuration.
+  *
   * 5. This file configures the system clock as follows:
   *=============================================================================
   *                         System Clock Configuration
   *=============================================================================
   *        System Clock source          | PLL(HSE)
   *-----------------------------------------------------------------------------
   *        SYSCLK                       | 48000000 Hz
   *-----------------------------------------------------------------------------
   *        HCLK                         | 48000000 Hz
   *-----------------------------------------------------------------------------
   *        AHB Prescaler                | 1
   *-----------------------------------------------------------------------------
   *        APB1 Prescaler               | 1
   *-----------------------------------------------------------------------------
   *        APB2 Prescaler               | 1
   *-----------------------------------------------------------------------------
   *        HSE Frequency                | 8000000 Hz
   *-----------------------------------------------------------------------------
   *        PLL MUL                      | 6
   *-----------------------------------------------------------------------------
   *        VDD                          | 3.3 V
   *-----------------------------------------------------------------------------
   *        Flash Latency                | 1 WS
   *-----------------------------------------------------------------------------
   *=============================================================================
   ******************************************************************************
   * @attention
+  *
   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
   * You may not use this file except in compliance with the License.
   * You may obtain a copy of the License at:
+  *
   *        http://www.st.com/software_license_agreement_liberty_v2
+  *
   * Unless required by applicable law or agreed to in writing, software
   * distributed under the License is distributed on an "AS IS" BASIS,
   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
   * See the License for the specific language governing permissions and
   * limitations under the License.
+  *
   ******************************************************************************
   */
 /** @addtogroup CMSIS
   * @{
   */
 /** @addtogroup stm32f0xx_system
   * @{
   */
 /** @addtogroup STM32F0xx_System_Private_Includes
   * @{
   */
 #include "stm32f0xx.h"
 /**
   * @}
   */
 /** @addtogroup STM32F0xx_System_Private_TypesDefinitions
   * @{
   */
 /**
   * @}
   */
 /** @addtogroup STM32F0xx_System_Private_Defines
   * @{
   */
 /**
   * @}
   */
 /** @addtogroup STM32F0xx_System_Private_Macros
   * @{
   */
 /**
   * @}
   */
 /** @addtogroup STM32F0xx_System_Private_Variables
   * @{
   */
 uint32_t SystemCoreClock    = 48000000;
 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 /**
   * @}
   */
 /** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
   * @{
   */
 static void SetSysClock(void);
 /**
   * @}
   */
 /** @addtogroup STM32F0xx_System_Private_Functions
   * @{
   */
 /**
   * @brief  Setup the microcontroller system.
   *         Initialize the Embedded Flash Interface, the PLL and update the
   *         SystemCoreClock variable.
   * @param  None
   * @retval None
   */
 void SystemInit (void)
+{
   /* Set HSION bit */
   RCC->CR |= (uint32_t)0x00000001;
 #if defined (STM32F031) || defined (STM32F072) || defined (STM32F042)
   /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
   RCC->CFGR &= (uint32_t)0xF8FFB80C;
 #else
   /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
   RCC->CFGR &= (uint32_t)0x08FFB80C;
 #endif /* STM32F031*/
   /* Reset HSEON, CSSON and PLLON bits */
   RCC->CR &= (uint32_t)0xFEF6FFFF;
   /* Reset HSEBYP bit */
   RCC->CR &= (uint32_t)0xFFFBFFFF;
   /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
   RCC->CFGR &= (uint32_t)0xFFC0FFFF;
   /* Reset PREDIV1[3:0] bits */
   RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
   /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */
   RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
   /* Reset HSI14 bit */
   RCC->CR2 &= (uint32_t)0xFFFFFFFE;
   /* Disable all interrupts */
   RCC->CIR = 0x00000000;
   /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
   SetSysClock();
+}
 /**
   * @brief  Update SystemCoreClock according to Clock Register Values
   *         The SystemCoreClock variable contains the core clock (HCLK), it can
   *         be used by the user application to setup the SysTick timer or configure
   *         other parameters.
+  *
   * @note   Each time the core clock (HCLK) changes, this function must be called
   *         to update SystemCoreClock variable value. Otherwise, any configuration
   *         based on this variable will be incorrect.
+  *
   * @note   - The system frequency computed by this function is not the real
   *           frequency in the chip. It is calculated based on the predefined
   *           constant and the selected clock source:
+  *
   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *
   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *
   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
   *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
   *         (*) HSI_VALUE is a constant defined in stm32f0xx.h file (default value
   *             8 MHz) but the real value may vary depending on the variations
   *             in voltage and temperature.
+  *
   *         (**) HSE_VALUE is a constant defined in stm32f0xx.h file (default value
   *              8 MHz), user has to ensure that HSE_VALUE is same as the real
   *              frequency of the crystal used. Otherwise, this function may
   *              have wrong result.
+  *
   *         - The result of this function could be not correct when using fractional
   *           value for HSE crystal.
   * @param  None
   * @retval None
   */
 void SystemCoreClockUpdate (void)
+{
   uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
   /* Get SYSCLK source -------------------------------------------------------*/
   tmp = RCC->CFGR & RCC_CFGR_SWS;
   switch (tmp)
+  {
     case 0x00:  /* HSI used as system clock */
       SystemCoreClock = HSI_VALUE;
       break;
     case 0x04:  /* HSE used as system clock */
       SystemCoreClock = HSE_VALUE;
       break;
     case 0x08:  /* PLL used as system clock */
       /* Get PLL clock source and multiplication factor ----------------------*/
       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
       pllmull = ( pllmull >> 18) + 2;
       if (pllsource == 0x00)
+      {
         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
       else
+      {
         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
         /* HSE oscillator clock selected as PREDIV1 clock entry */
         SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
+      }
       break;
     default: /* HSI used as system clock */
       SystemCoreClock = HSI_VALUE;
       break;
+  }
   /* Compute HCLK clock frequency ----------------*/
   /* Get HCLK prescaler */
   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
   /* HCLK clock frequency */
   SystemCoreClock >>= tmp;
+}
 /**
   * @brief  Configures the System clock frequency, AHB/APBx prescalers and Flash
   *         settings.
   * @note   This function should be called only once the RCC clock configuration
   *         is reset to the default reset state (done in SystemInit() function).
   * @param  None
   * @retval None
   */
 static void SetSysClock(void)
+{
   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
   /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/
   /* Enable HSE */
   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
   /* Wait till HSE is ready and if Time out is reached exit */
   do
+  {
     HSEStatus = RCC->CR & RCC_CR_HSERDY;
     StartUpCounter++;
   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
     HSEStatus = (uint32_t)0x01;
+  }
   else
+  {
     HSEStatus = (uint32_t)0x00;
+  }
   if (HSEStatus == (uint32_t)0x01)
+  {
     /* Enable Prefetch Buffer and set Flash Latency */
     FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;
     /* HCLK = SYSCLK */
     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
     /* PCLK = HCLK */
     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;
     /* PLL configuration = HSE * 6 = 48 MHz */
     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL6);
     /* Enable PLL */
     RCC->CR |= RCC_CR_PLLON;
     /* Wait till PLL is ready */
     while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
     /* Select PLL as system clock source */
     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
     /* Wait till PLL is used as system clock source */
     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
+    {
+    }
+  }
   else
   { /* If HSE fails to start-up, the application will have wrong clock
          configuration. User can add here some code to deal with this error */
+  }
+}
 /**
   * @}
   */
 /**
   * @}
   */
 /**
   * @}
   */
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

libraries/CMSIS/Include/arm_common_tables.h

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@@ new file 100644 @@
 /* ----------------------------------------------------------------------
 * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
 * $Date:        17. January 2013
 * $Revision:    V1.4.1
+*
 * Project:      CMSIS DSP Library
 * Title:        arm_common_tables.h
+*
 * Description:  This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
 * Target Processor: Cortex-M4/Cortex-M3
+*
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *   - Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *   - Redistributions in binary form must reproduce the above copyright
 *     notice, this list of conditions and the following disclaimer in
 *     the documentation and/or other materials provided with the
 *     distribution.
 *   - Neither the name of ARM LIMITED nor the names of its contributors
 *     may be used to endorse or promote products derived from this
 *     software without specific prior written permission.
+*
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 * -------------------------------------------------------------------- */
 #ifndef _ARM_COMMON_TABLES_H
 #define _ARM_COMMON_TABLES_H
 #include "arm_math.h"
 extern const uint16_t armBitRevTable[1024];
 extern const q15_t armRecipTableQ15[64];
 extern const q31_t armRecipTableQ31[64];
 extern const q31_t realCoefAQ31[1024];
 extern const q31_t realCoefBQ31[1024];
 extern const float32_t twiddleCoef_16[32];
 extern const float32_t twiddleCoef_32[64];
 extern const float32_t twiddleCoef_64[128];
 extern const float32_t twiddleCoef_128[256];
 extern const float32_t twiddleCoef_256[512];
 extern const float32_t twiddleCoef_512[1024];
 extern const float32_t twiddleCoef_1024[2048];
 extern const float32_t twiddleCoef_2048[4096];
 extern const float32_t twiddleCoef_4096[8192];
 #define twiddleCoef twiddleCoef_4096
 extern const q31_t twiddleCoefQ31[6144];
 extern const q15_t twiddleCoefQ15[6144];
 extern const float32_t twiddleCoef_rfft_32[32];
 extern const float32_t twiddleCoef_rfft_64[64];
 extern const float32_t twiddleCoef_rfft_128[128];
 extern const float32_t twiddleCoef_rfft_256[256];
 extern const float32_t twiddleCoef_rfft_512[512];
 extern const float32_t twiddleCoef_rfft_1024[1024];
 extern const float32_t twiddleCoef_rfft_2048[2048];
 extern const float32_t twiddleCoef_rfft_4096[4096];
 #define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )
 #define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )
 #define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )
 #define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
 #define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
 #define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
 #define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
 #define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
 #define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
 extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
 extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
 extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
 extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
 extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
 extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
 extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
 extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
 extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
 #endif /*  ARM_COMMON_TABLES_H */

libraries/CMSIS/Include/arm_const_structs.h

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@@ new file 100644 @@
 /* ----------------------------------------------------------------------
 * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
 * $Date:        17. January 2013
 * $Revision:    V1.4.1
+*
 * Project:      CMSIS DSP Library
 * Title:        arm_const_structs.h
+*
 * Description:  This file has constant structs that are initialized for
 *               user convenience.  For example, some can be given as
 *               arguments to the arm_cfft_f32() function.
+*
 * Target Processor: Cortex-M4/Cortex-M3
+*
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *   - Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *   - Redistributions in binary form must reproduce the above copyright
 *     notice, this list of conditions and the following disclaimer in
 *     the documentation and/or other materials provided with the
 *     distribution.
 *   - Neither the name of ARM LIMITED nor the names of its contributors
 *     may be used to endorse or promote products derived from this
 *     software without specific prior written permission.
+*
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 * -------------------------------------------------------------------- */
 #ifndef _ARM_CONST_STRUCTS_H
 #define _ARM_CONST_STRUCTS_H
 #include "arm_math.h"
 #include "arm_common_tables.h"
    const arm_cfft_instance_f32 arm_cfft_sR_f32_len16 = {
 , twiddleCoef_16, armBitRevIndexTable16, ARMBITREVINDEXTABLE__16_TABLE_LENGTH
    };
    const arm_cfft_instance_f32 arm_cfft_sR_f32_len32 = {
 , twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE__32_TABLE_LENGTH
    };
    const arm_cfft_instance_f32 arm_cfft_sR_f32_len64 = {
 , twiddleCoef_64, armBitRevIndexTable64, ARMBITREVINDEXTABLE__64_TABLE_LENGTH
    };
    const arm_cfft_instance_f32 arm_cfft_sR_f32_len128 = {
 , twiddleCoef_128, armBitRevIndexTable128, ARMBITREVINDEXTABLE_128_TABLE_LENGTH
    };
    const arm_cfft_instance_f32 arm_cfft_sR_f32_len256 = {
 , twiddleCoef_256, armBitRevIndexTable256, ARMBITREVINDEXTABLE_256_TABLE_LENGTH
    };
    const arm_cfft_instance_f32 arm_cfft_sR_f32_len512 = {
 , twiddleCoef_512, armBitRevIndexTable512, ARMBITREVINDEXTABLE_512_TABLE_LENGTH
    };
    const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024 = {
 , twiddleCoef_1024, armBitRevIndexTable1024, ARMBITREVINDEXTABLE1024_TABLE_LENGTH
    };
    const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048 = {
 , twiddleCoef_2048, armBitRevIndexTable2048, ARMBITREVINDEXTABLE2048_TABLE_LENGTH
    };
    const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096 = {
 , twiddleCoef_4096, armBitRevIndexTable4096, ARMBITREVINDEXTABLE4096_TABLE_LENGTH
    };
 #endif

libraries/CMSIS/Include/arm_math.h

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@@ new file 100644 @@
 /* ----------------------------------------------------------------------
 * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
 * $Date:        17. January 2013
 * $Revision:    V1.4.1
+*
 * Project:      CMSIS DSP Library
 * Title:        arm_math.h
+*
 * Description:  Public header file for CMSIS DSP Library
+*
 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *   - Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *   - Redistributions in binary form must reproduce the above copyright
 *     notice, this list of conditions and the following disclaimer in
 *     the documentation and/or other materials provided with the
 *     distribution.
 *   - Neither the name of ARM LIMITED nor the names of its contributors
 *     may be used to endorse or promote products derived from this
 *     software without specific prior written permission.
+*
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
  * -------------------------------------------------------------------- */
 /**
    \mainpage CMSIS DSP Software Library
+   *
    * <b>Introduction</b>
+   *
    * This user manual describes the CMSIS DSP software library,
    * a suite of common signal processing functions for use on Cortex-M processor based devices.
+   *
    * The library is divided into a number of functions each covering a specific category:
    * - Basic math functions
    * - Fast math functions
    * - Complex math functions
    * - Filters
    * - Matrix functions
    * - Transforms
    * - Motor control functions
    * - Statistical functions
    * - Support functions
    * - Interpolation functions
+   *
    * The library has separate functions for operating on 8-bit integers, 16-bit integers,
    * 32-bit integer and 32-bit floating-point values.
+   *
    * <b>Using the Library</b>
+   *
    * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
    * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
    * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
    * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
    * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
    * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
    * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
    * - arm_cortexM0l_math.lib (Little endian on Cortex-M0)
    * - arm_cortexM0b_math.lib (Big endian on Cortex-M3)
+   *
    * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
    * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
    * public header file <code> arm_math.h</code> for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
    * Define the appropriate pre processor MACRO ARM_MATH_CM4 or  ARM_MATH_CM3 or
    * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+   *
    * <b>Examples</b>
+   *
    * The library ships with a number of examples which demonstrate how to use the library functions.
+   *
    * <b>Toolchain Support</b>
+   *
    * The library has been developed and tested with MDK-ARM version 4.60.
    * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+   *
    * <b>Building the Library</b>
+   *
    * The library installer contains project files to re build libraries on MDK Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
    * - arm_cortexM0b_math.uvproj
    * - arm_cortexM0l_math.uvproj
    * - arm_cortexM3b_math.uvproj
    * - arm_cortexM3l_math.uvproj
    * - arm_cortexM4b_math.uvproj
    * - arm_cortexM4l_math.uvproj
    * - arm_cortexM4bf_math.uvproj
    * - arm_cortexM4lf_math.uvproj
+   *
+   *
    * The project can be built by opening the appropriate project in MDK-ARM 4.60 chain and defining the optional pre processor MACROs detailed above.
+   *
    * <b>Pre-processor Macros</b>
+   *
    * Each library project have differant pre-processor macros.
+   *
    * - UNALIGNED_SUPPORT_DISABLE:
+   *
    * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+   *
    * - ARM_MATH_BIG_ENDIAN:
+   *
    * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+   *
    * - ARM_MATH_MATRIX_CHECK:
+   *
    * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+   *
    * - ARM_MATH_ROUNDING:
+   *
    * Define macro ARM_MATH_ROUNDING for rounding on support functions
+   *
    * - ARM_MATH_CMx:
+   *
    * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
    * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target.
+   *
    * - __FPU_PRESENT:
+   *
    * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
+   *
    * <b>Copyright Notice</b>
+   *
    * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
    */
 /**
  * @defgroup groupMath Basic Math Functions
  */
 /**
  * @defgroup groupFastMath Fast Math Functions
  * This set of functions provides a fast approximation to sine, cosine, and square root.
  * As compared to most of the other functions in the CMSIS math library, the fast math functions
  * operate on individual values and not arrays.
  * There are separate functions for Q15, Q31, and floating-point data.
+ *
  */
 /**
  * @defgroup groupCmplxMath Complex Math Functions
  * This set of functions operates on complex data vectors.
  * The data in the complex arrays is stored in an interleaved fashion
  * (real, imag, real, imag, ...).
  * In the API functions, the number of samples in a complex array refers
  * to the number of complex values; the array contains twice this number of
  * real values.
  */
 /**
  * @defgroup groupFilters Filtering Functions
  */
 /**
  * @defgroup groupMatrix Matrix Functions
+ *
  * This set of functions provides basic matrix math operations.
  * The functions operate on matrix data structures.  For example,
  * the type
  * definition for the floating-point matrix structure is shown
  * below:
  * <pre>
  *     typedef struct
  *     {
  *       uint16_t numRows;     // number of rows of the matrix.
  *       uint16_t numCols;     // number of columns of the matrix.
  *       float32_t *pData;     // points to the data of the matrix.
  *     } arm_matrix_instance_f32;
  * </pre>
  * There are similar definitions for Q15 and Q31 data types.
+ *
  * The structure specifies the size of the matrix and then points to
  * an array of data.  The array is of size <code>numRows X numCols</code>
  * and the values are arranged in row order.  That is, the
  * matrix element (i, j) is stored at:
  * <pre>
  *     pData[i*numCols + j]
  * </pre>
+ *
  * \par Init Functions
  * There is an associated initialization function for each type of matrix
  * data structure.
  * The initialization function sets the values of the internal structure fields.
  * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
  * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.
+ *
  * \par
  * Use of the initialization function is optional. However, if initialization function is used
  * then the instance structure cannot be placed into a const data section.
  * To place the instance structure in a const data
  * section, manually initialize the data structure.  For example:
  * <pre>
  * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
  * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
  * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
  * </pre>
  * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
  * specifies the number of columns, and <code>pData</code> points to the
  * data array.
+ *
  * \par Size Checking
  * By default all of the matrix functions perform size checking on the input and
  * output matrices.  For example, the matrix addition function verifies that the
  * two input matrices and the output matrix all have the same number of rows and
  * columns.  If the size check fails the functions return:
  * <pre>
  *     ARM_MATH_SIZE_MISMATCH
  * </pre>
  * Otherwise the functions return
  * <pre>
  *     ARM_MATH_SUCCESS
  * </pre>
  * There is some overhead associated with this matrix size checking.
  * The matrix size checking is enabled via the \#define
  * <pre>
  *     ARM_MATH_MATRIX_CHECK
  * </pre>
  * within the library project settings.  By default this macro is defined
  * and size checking is enabled.  By changing the project settings and
  * undefining this macro size checking is eliminated and the functions
  * run a bit faster.  With size checking disabled the functions always
  * return <code>ARM_MATH_SUCCESS</code>.
  */
 /**
  * @defgroup groupTransforms Transform Functions
  */
 /**
  * @defgroup groupController Controller Functions
  */
 /**
  * @defgroup groupStats Statistics Functions
  */
 /**
  * @defgroup groupSupport Support Functions
  */
 /**
  * @defgroup groupInterpolation Interpolation Functions
  * These functions perform 1- and 2-dimensional interpolation of data.
  * Linear interpolation is used for 1-dimensional data and
  * bilinear interpolation is used for 2-dimensional data.
  */
 /**
  * @defgroup groupExamples Examples
  */
 #ifndef _ARM_MATH_H
 #define _ARM_MATH_H
 #define __CMSIS_GENERIC         /* disable NVIC and Systick functions */
 #if defined (ARM_MATH_CM4)
 #include "core_cm4.h"
 #elif defined (ARM_MATH_CM3)
 #include "core_cm3.h"
 #elif defined (ARM_MATH_CM0)
 #include "core_cm0.h"
 #define ARM_MATH_CM0_FAMILY
 #elif defined (ARM_MATH_CM0PLUS)
 #include "core_cm0plus.h"
 #define ARM_MATH_CM0_FAMILY
 #else
 #include "ARMCM4.h"
 #warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....."
 #endif
 #undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
 #include "string.h"
 #include "math.h"
 #ifdef	__cplusplus
 extern "C"
+{
 #endif
   /**
    * @brief Macros required for reciprocal calculation in Normalized LMS
    */
 #define DELTA_Q31 			(0x100)
 #define DELTA_Q15 			0x5
 #define INDEX_MASK 			0x0000003F
 #ifndef PI
 #define PI					3.14159265358979f
 #endif
   /**
    * @brief Macros required for SINE and COSINE Fast math approximations
    */
 #define TABLE_SIZE			256
 #define TABLE_SPACING_Q31	0x800000
 #define TABLE_SPACING_Q15	0x80
   /**
    * @brief Macros required for SINE and COSINE Controller functions
    */
   /* 1.31(q31) Fixed value of 2/360 */
   /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
 #define INPUT_SPACING			0xB60B61
   /**
    * @brief Macro for Unaligned Support
    */
 #ifndef UNALIGNED_SUPPORT_DISABLE
     #define ALIGN4
 #else
   #if defined  (__GNUC__)
     #define ALIGN4 __attribute__((aligned(4)))
   #else
     #define ALIGN4 __align(4)
   #endif
 #endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
   /**
    * @brief Error status returned by some functions in the library.
    */
   typedef enum
+  {
     ARM_MATH_SUCCESS = 0,                /**< No error */
     ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */
     ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */
     ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */
     ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */
     ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
     ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */
   } arm_status;
   /**
    * @brief 8-bit fractional data type in 1.7 format.
    */
   typedef int8_t q7_t;
   /**
    * @brief 16-bit fractional data type in 1.15 format.
    */
   typedef int16_t q15_t;
   /**
    * @brief 32-bit fractional data type in 1.31 format.
    */
   typedef int32_t q31_t;
   /**
    * @brief 64-bit fractional data type in 1.63 format.
    */
   typedef int64_t q63_t;
   /**
    * @brief 32-bit floating-point type definition.
    */
   typedef float float32_t;
   /**
    * @brief 64-bit floating-point type definition.
    */
   typedef double float64_t;
   /**
    * @brief definition to read/write two 16 bit values.
    */
 #if defined __CC_ARM
 #define __SIMD32_TYPE int32_t __packed
 #define CMSIS_UNUSED __attribute__((unused))
 #elif defined __ICCARM__
 #define CMSIS_UNUSED
 #define __SIMD32_TYPE int32_t __packed
 #elif defined __GNUC__
 #define __SIMD32_TYPE int32_t
 #define CMSIS_UNUSED __attribute__((unused))
 #else
 #error Unknown compiler
 #endif
 #define __SIMD32(addr)  (*(__SIMD32_TYPE **) & (addr))
 #define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))
 #define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))
 #define __SIMD64(addr)  (*(int64_t **) & (addr))
 #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
   /**
    * @brief definition to pack two 16 bit values.
    */
 #define __PKHBT(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0x0000FFFF) | \
                                          (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
 #define __PKHTB(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0xFFFF0000) | \
                                          (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )
 #endif
    /**
    * @brief definition to pack four 8 bit values.
    */
 #ifndef ARM_MATH_BIG_ENDIAN
 #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) |	\
                                 (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) |	\
 							    (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) |	\
 							    (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
 #else
 #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) |	\
                                 (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) |	\
 							    (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) |	\
 							    (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
 #endif
   /**
    * @brief Clips Q63 to Q31 values.
    */
   static __INLINE q31_t clip_q63_to_q31(
   q63_t x)
+  {
     return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
       ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+  }
   /**
    * @brief Clips Q63 to Q15 values.
    */
   static __INLINE q15_t clip_q63_to_q15(
   q63_t x)
+  {
     return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
       ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+  }
   /**
    * @brief Clips Q31 to Q7 values.
    */
   static __INLINE q7_t clip_q31_to_q7(
   q31_t x)
+  {
     return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
       ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+  }
   /**
    * @brief Clips Q31 to Q15 values.
    */
   static __INLINE q15_t clip_q31_to_q15(
   q31_t x)
+  {
     return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
       ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+  }
   /**
    * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
    */
   static __INLINE q63_t mult32x64(
   q63_t x,
   q31_t y)
+  {
     return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
             (((q63_t) (x >> 32) * y)));
+  }
 #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM   )
 #define __CLZ __clz
 #endif
 #if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) )
   static __INLINE uint32_t __CLZ(
   q31_t data);
   static __INLINE uint32_t __CLZ(
   q31_t data)
+  {
     uint32_t count = 0;
     uint32_t mask = 0x80000000;
     while((data & mask) == 0)
+    {
       count += 1u;
       mask = mask >> 1u;
+    }
     return (count);
+  }
 #endif
   /**
    * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
    */
   static __INLINE uint32_t arm_recip_q31(
   q31_t in,
   q31_t * dst,
   q31_t * pRecipTable)
+  {
     uint32_t out, tempVal;
     uint32_t index, i;
     uint32_t signBits;
     if(in > 0)
+    {
       signBits = __CLZ(in) - 1;
+    }
     else
+    {
       signBits = __CLZ(-in) - 1;
+    }
     /* Convert input sample to 1.31 format */
     in = in << signBits;
     /* calculation of index for initial approximated Val */
     index = (uint32_t) (in >> 24u);
     index = (index & INDEX_MASK);
     /* 1.31 with exp 1 */
     out = pRecipTable[index];
     /* calculation of reciprocal value */
     /* running approximation for two iterations */
     for (i = 0u; i < 2u; i++)
+    {
       tempVal = (q31_t) (((q63_t) in * out) >> 31u);
       tempVal = 0x7FFFFFFF - tempVal;
       /*      1.31 with exp 1 */
       //out = (q31_t) (((q63_t) out * tempVal) >> 30u);
       out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
+    }
     /* write output */
     *dst = out;
     /* return num of signbits of out = 1/in value */
     return (signBits + 1u);
+  }
   /**
    * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
    */
   static __INLINE uint32_t arm_recip_q15(
   q15_t in,
   q15_t * dst,
   q15_t * pRecipTable)
+  {
     uint32_t out = 0, tempVal = 0;
     uint32_t index = 0, i = 0;
     uint32_t signBits = 0;
     if(in > 0)
+    {
       signBits = __CLZ(in) - 17;
+    }
     else
+    {
       signBits = __CLZ(-in) - 17;
+    }
     /* Convert input sample to 1.15 format */
     in = in << signBits;
     /* calculation of index for initial approximated Val */
     index = in >> 8;
     index = (index & INDEX_MASK);
     /*      1.15 with exp 1  */
     out = pRecipTable[index];
     /* calculation of reciprocal value */
     /* running approximation for two iterations */
     for (i = 0; i < 2; i++)
+    {
       tempVal = (q15_t) (((q31_t) in * out) >> 15);
       tempVal = 0x7FFF - tempVal;
       /*      1.15 with exp 1 */
       out = (q15_t) (((q31_t) out * tempVal) >> 14);
+    }
     /* write output */
     *dst = out;
     /* return num of signbits of out = 1/in value */
     return (signBits + 1);
+  }
   /*
    * @brief C custom defined intrinisic function for only M0 processors
    */
 #if defined(ARM_MATH_CM0_FAMILY)
   static __INLINE q31_t __SSAT(
   q31_t x,
   uint32_t y)
+  {
     int32_t posMax, negMin;
     uint32_t i;
     posMax = 1;
     for (i = 0; i < (y - 1); i++)
+    {
       posMax = posMax * 2;
+    }
     if(x > 0)
+    {
       posMax = (posMax - 1);
       if(x > posMax)
+      {
         x = posMax;
+      }
+    }
     else
+    {
       negMin = -posMax;
       if(x < negMin)
+      {
         x = negMin;
+      }
+    }
     return (x);
+  }
 #endif /* end of ARM_MATH_CM0_FAMILY */
   /*
    * @brief C custom defined intrinsic function for M3 and M0 processors
    */
 #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
   /*
    * @brief C custom defined QADD8 for M3 and M0 processors
    */
   static __INLINE q31_t __QADD8(
   q31_t x,
   q31_t y)
+  {
     q31_t sum;
     q7_t r, s, t, u;
     r = (q7_t) x;
     s = (q7_t) y;
     r = __SSAT((q31_t) (r + s), 8);
     s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
     t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
     u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
     sum =
       (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
       (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
     return sum;
+  }
   /*
    * @brief C custom defined QSUB8 for M3 and M0 processors
    */
   static __INLINE q31_t __QSUB8(
   q31_t x,
   q31_t y)
+  {
     q31_t sum;
     q31_t r, s, t, u;
     r = (q7_t) x;
     s = (q7_t) y;
     r = __SSAT((r - s), 8);
     s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
     t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
     u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
     sum =
       (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r &
 x000000FF);
     return sum;
+  }
   /*
    * @brief C custom defined QADD16 for M3 and M0 processors
    */
   /*
    * @brief C custom defined QADD16 for M3 and M0 processors
    */
   static __INLINE q31_t __QADD16(
   q31_t x,
   q31_t y)
+  {
     q31_t sum;
     q31_t r, s;
     r = (short) x;
     s = (short) y;
     r = __SSAT(r + s, 16);
     s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
     sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
     return sum;
+  }
   /*
    * @brief C custom defined SHADD16 for M3 and M0 processors
    */
   static __INLINE q31_t __SHADD16(
   q31_t x,
   q31_t y)
+  {
     q31_t sum;
     q31_t r, s;
     r = (short) x;
     s = (short) y;
     r = ((r >> 1) + (s >> 1));
     s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
     sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
     return sum;
+  }
   /*
    * @brief C custom defined QSUB16 for M3 and M0 processors
    */
   static __INLINE q31_t __QSUB16(
   q31_t x,
   q31_t y)
+  {
     q31_t sum;
     q31_t r, s;
     r = (short) x;
     s = (short) y;
     r = __SSAT(r - s, 16);
     s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
     sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
     return sum;
+  }
   /*
    * @brief C custom defined SHSUB16 for M3 and M0 processors
    */
   static __INLINE q31_t __SHSUB16(
   q31_t x,
   q31_t y)
+  {
     q31_t diff;
     q31_t r, s;
     r = (short) x;
     s = (short) y;
     r = ((r >> 1) - (s >> 1));
     s = (((x >> 17) - (y >> 17)) << 16);
     diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
     return diff;
+  }
   /*
    * @brief C custom defined QASX for M3 and M0 processors
    */
   static __INLINE q31_t __QASX(
   q31_t x,
   q31_t y)
+  {
     q31_t sum = 0;
     sum =
       ((sum +
         clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) +
       clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16)));
     return sum;
+  }
   /*
    * @brief C custom defined SHASX for M3 and M0 processors
    */
   static __INLINE q31_t __SHASX(
   q31_t x,
   q31_t y)
+  {
     q31_t sum;
     q31_t r, s;
     r = (short) x;
     s = (short) y;
     r = ((r >> 1) - (y >> 17));
     s = (((x >> 17) + (s >> 1)) << 16);
     sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
     return sum;
+  }
   /*
    * @brief C custom defined QSAX for M3 and M0 processors
    */
   static __INLINE q31_t __QSAX(
   q31_t x,
   q31_t y)
+  {
     q31_t sum = 0;
     sum =
       ((sum +
         clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) +
       clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16)));
     return sum;
+  }
   /*
    * @brief C custom defined SHSAX for M3 and M0 processors
    */
   static __INLINE q31_t __SHSAX(
   q31_t x,
   q31_t y)
+  {
     q31_t sum;
     q31_t r, s;
     r = (short) x;
     s = (short) y;
     r = ((r >> 1) + (y >> 17));
     s = (((x >> 17) - (s >> 1)) << 16);
     sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
     return sum;
+  }
   /*
    * @brief C custom defined SMUSDX for M3 and M0 processors
    */
   static __INLINE q31_t __SMUSDX(
   q31_t x,
   q31_t y)
+  {
     return ((q31_t) (((short) x * (short) (y >> 16)) -
                      ((short) (x >> 16) * (short) y)));
+  }
   /*
    * @brief C custom defined SMUADX for M3 and M0 processors
    */
   static __INLINE q31_t __SMUADX(
   q31_t x,
   q31_t y)
+  {
     return ((q31_t) (((short) x * (short) (y >> 16)) +
                      ((short) (x >> 16) * (short) y)));
+  }
   /*
    * @brief C custom defined QADD for M3 and M0 processors
    */
   static __INLINE q31_t __QADD(
   q31_t x,
   q31_t y)
+  {
     return clip_q63_to_q31((q63_t) x + y);
+  }
   /*
    * @brief C custom defined QSUB for M3 and M0 processors
    */
   static __INLINE q31_t __QSUB(
   q31_t x,
   q31_t y)
+  {
     return clip_q63_to_q31((q63_t) x - y);
+  }
   /*
    * @brief C custom defined SMLAD for M3 and M0 processors
    */
   static __INLINE q31_t __SMLAD(
   q31_t x,
   q31_t y,
   q31_t sum)
+  {
     return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
             ((short) x * (short) y));
+  }
   /*
    * @brief C custom defined SMLADX for M3 and M0 processors
    */
   static __INLINE q31_t __SMLADX(
   q31_t x,
   q31_t y,
   q31_t sum)
+  {
     return (sum + ((short) (x >> 16) * (short) (y)) +
             ((short) x * (short) (y >> 16)));
+  }
   /*
    * @brief C custom defined SMLSDX for M3 and M0 processors
    */
   static __INLINE q31_t __SMLSDX(
   q31_t x,
   q31_t y,
   q31_t sum)
+  {
     return (sum - ((short) (x >> 16) * (short) (y)) +
             ((short) x * (short) (y >> 16)));
+  }
   /*
    * @brief C custom defined SMLALD for M3 and M0 processors
    */
   static __INLINE q63_t __SMLALD(
   q31_t x,
   q31_t y,
   q63_t sum)
+  {
     return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
             ((short) x * (short) y));
+  }
   /*
    * @brief C custom defined SMLALDX for M3 and M0 processors
    */
   static __INLINE q63_t __SMLALDX(
   q31_t x,
   q31_t y,
   q63_t sum)
+  {
     return (sum + ((short) (x >> 16) * (short) y)) +
       ((short) x * (short) (y >> 16));
+  }
   /*
    * @brief C custom defined SMUAD for M3 and M0 processors
    */
   static __INLINE q31_t __SMUAD(
   q31_t x,
   q31_t y)
+  {
     return (((x >> 16) * (y >> 16)) +
             (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
   /*
    * @brief C custom defined SMUSD for M3 and M0 processors
    */
   static __INLINE q31_t __SMUSD(
   q31_t x,
   q31_t y)
+  {
     return (-((x >> 16) * (y >> 16)) +
             (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
   /*
    * @brief C custom defined SXTB16 for M3 and M0 processors
    */
   static __INLINE q31_t __SXTB16(
   q31_t x)
+  {
     return ((((x << 24) >> 24) & 0x0000FFFF) |
             (((x << 8) >> 8) & 0xFFFF0000));
+  }
 #endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
   /**
    * @brief Instance structure for the Q7 FIR filter.
    */
   typedef struct
+  {
     uint16_t numTaps;        /**< number of filter coefficients in the filter. */
     q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
     q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
   } arm_fir_instance_q7;
   /**
    * @brief Instance structure for the Q15 FIR filter.
    */
   typedef struct
+  {
     uint16_t numTaps;         /**< number of filter coefficients in the filter. */
     q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
     q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
   } arm_fir_instance_q15;
   /**
    * @brief Instance structure for the Q31 FIR filter.
    */
   typedef struct
+  {
     uint16_t numTaps;         /**< number of filter coefficients in the filter. */
     q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
     q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
   } arm_fir_instance_q31;
   /**
    * @brief Instance structure for the floating-point FIR filter.
    */
   typedef struct
+  {
     uint16_t numTaps;     /**< number of filter coefficients in the filter. */
     float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
     float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
   } arm_fir_instance_f32;
   /**
    * @brief Processing function for the Q7 FIR filter.
    * @param[in] *S points to an instance of the Q7 FIR filter structure.
    * @param[in] *pSrc points to the block of input data.
    * @param[out] *pDst points to the block of output data.
    * @param[in] blockSize number of samples to process.
    * @return none.
    */
   void arm_fir_q7(
   const arm_fir_instance_q7 * S,
   q7_t * pSrc,
   q7_t * pDst,
   uint32_t blockSize);
   /**
    * @brief  Initialization function for the Q7 FIR filter.
    * @param[in,out] *S points to an instance of the Q7 FIR structure.
    * @param[in] numTaps  Number of filter coefficients in the filter.
    * @param[in] *pCoeffs points to the filter coefficients.
    * @param[in] *pState points to the state buffer.
    * @param[in] blockSize number of samples that are processed.
    * @return none
    */
   void arm_fir_init_q7(
   arm_fir_instance_q7 * S,
   uint16_t numTaps,
   q7_t * pCoeffs,
   q7_t * pState,
   uint32_t blockSize);
   /**
    * @brief Processing function for the Q15 FIR filter.
    * @param[in] *S points to an instance of the Q15 FIR structure.
    * @param[in] *pSrc points to the block of input data.
    * @param[out] *pDst points to the block of output data.
    * @param[in] blockSize number of samples to process.
    * @return none.
    */
   void arm_fir_q15(
   const arm_fir_instance_q15 * S,
   q15_t * pSrc,
   q15_t * pDst,
   uint32_t blockSize);
   /**
    * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
    * @param[in] *S points to an instance of the Q15 FIR filter structure.
    * @param[in] *pSrc points to the block of input data.
    * @param[out] *pDst points to the block of output data.
    * @param[in] blockSize number of samples to process.
    * @return none.
    */
   void arm_fir_fast_q15(
   const arm_fir_instance_q15 * S,
   q15_t * pSrc,
   q15_t * pDst,
   uint32_t blockSize);
   /**
    * @brief  Initialization function for the Q15 FIR filter.
    * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
    * @param[in] numTaps  Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
    * @param[in] *pCoeffs points to the filter coefficients.
    * @param[in] *pState points to the state buffer.
    * @param[in] blockSize number of samples that are processed at a time.
    * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
    * <code>numTaps</code> is not a supported value.
    */
   arm_status arm_fir_init_q15(
   arm_fir_instance_q15 * S,
   uint16_t numTaps,
   q15_t * pCoeffs,
   q15_t * pState,
   uint32_t blockSize);
   /**
    * @brief Processing function for the Q31 FIR filter.
    * @param[in] *S points to an instance of the Q31 FIR filter structure.
    * @param[in] *pSrc points to the block of input data.
    * @param[out] *pDst points to the block of output data.
    * @param[in] blockSize number of samples to process.
    * @return none.
    */
   void arm_fir_q31(
   const arm_fir_instance_q31 * S,
   q31_t * pSrc,
   q31_t * pDst,
   uint32_t blockSize);
   /**
    * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
    * @param[in] *S points to an instance of the Q31 FIR structure.
    * @param[in] *pSrc points to the block of input data.
    * @param[out] *pDst points to the block of output data.
    * @param[in] blockSize number of samples to process.
    * @return none.
    */
   void arm_fir_fast_q31(
   const arm_fir_instance_q31 * S,
   q31_t * pSrc,
   q31_t * pDst,
   uint32_t blockSize);
   /**
    * @brief  Initialization function for the Q31 FIR filter.
    * @param[in,out] *S points to an instance of the Q31 FIR structure.
    * @param[in] 	numTaps  Number of filter coefficients in the filter.
    * @param[in] 	*pCoeffs points to the filter coefficients.
    * @param[in] 	*pState points to the state buffer.
    * @param[in] 	blockSize number of samples that are processed at a time.
    * @return 		none.
    */
   void arm_fir_init_q31(
   arm_fir_instance_q31 * S,
   uint16_t numTaps,
   q31_t * pCoeffs,
   q31_t * pState,
   uint32_t blockSize);
   /**
    * @brief Processing function for the floating-point FIR filter.
    * @param[in] *S points to an instance of the floating-point FIR structure.
    * @param[in] *pSrc points to the block of input data.
    * @param[out] *pDst points to the block of output data.
    * @param[in] blockSize number of samples to process.
    * @return none.
    */
   void arm_fir_f32(
   const arm_fir_instance_f32 * S,
   float32_t * pSrc,
   float32_t * pDst,
   uint32_t blockSize);
   /**
    * @brief  Initialization function for the floating-point FIR filter.
    * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
    * @param[in] 	numTaps  Number of filter coefficients in the filter.
    * @param[in] 	*pCoeffs points to the filter coefficients.
    * @param[in] 	*pState points to the state buffer.
    * @param[in] 	blockSize number of samples that are processed at a time.
    * @return    	none.
    */
   void arm_fir_init_f32(
   arm_fir_instance_f32 * S,
   uint16_t numTaps,
   float32_t * pCoeffs,
   float32_t * pState,
   uint32_t blockSize);
   /**
    * @brief Instance structure for the Q15 Biquad cascade filter.
    */
   typedef struct
+  {
     int8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
     q15_t *pState;            /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
     q15_t *pCoeffs;           /**< Points to the array of coefficients.  The array is of length 5*numStages. */
     int8_t postShift;         /**< Additional shift, in bits, applied to each output sample. */
   } arm_biquad_casd_df1_inst_q15;
   /**
    * @brief Instance structure for the Q31 Biquad cascade filter.
    */
   typedef struct
+  {
     uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
     q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
     q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
     uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
   } arm_biquad_casd_df1_inst_q31;
   /**
    * @brief Instance structure for the floating-point Biquad cascade filter.
    */
   typedef struct
+  {
     uint32_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
     float32_t *pState;          /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
     float32_t *pCoeffs;         /**< Points to the array of coefficients.  The array is of length 5*numStages. */
   } arm_biquad_casd_df1_inst_f32;
   /**
    * @brief Processing function for the Q15 Biquad cascade filter.
    * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
    * @param[in]  *pSrc points to the block of input data.
    * @param[out] *pDst points to the block of output data.
    * @param[in]  blockSize number of samples to process.
    * @return     none.
    */
   void arm_biquad_cascade_df1_q15(
   const arm_biquad_casd_df1_inst_q15 * S,
   q15_t * pSrc,
   q15_t * pDst,
   uint32_t blockSize);
   /**
    * @brief  Initialization function for the Q15 Biquad cascade filter.
    * @param[in,out] *S           points to an instance of the Q15 Biquad cascade structure.
    * @param[in]     numStages    number of 2nd order stages in the filter.
    * @param[in]     *pCoeffs     points to the filter coefficients.
    * @param[in]     *pState      points to the state buffer.
    * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
    * @return        none
    */
   void arm_biquad_cascade_df1_init_q15(
   arm_biquad_casd_df1_inst_q15 * S,
   uint8_t numStages,
   q15_t * pCoeffs,
   q15_t * pState,
   int8_t postShift);
   /**
    * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
    * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
    * @param[in]  *pSrc points to the block of input data.
    * @param[out] *pDst points to the block of output data.
    * @param[in]  blockSize number of samples to process.
    * @return     none.
    */
   void arm_biquad_cascade_df1_fast_q15(
   const arm_biquad_casd_df1_inst_q15 * S,
   q15_t * pSrc,
   q15_t * pDst,
   uint32_t blockSize);
   /**
    * @brief Processing function for the Q31 Biquad cascade filter
    * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
    * @param[in]  *pSrc      points to the block of input data.
    * @param[out] *pDst      points to the block of output data.
    * @param[in]  blockSize  number of samples to process.
    * @return     none.
    */
   void arm_biquad_cascade_df1_q31(
   const arm_biquad_casd_df1_inst_q31 * S,
   q31_t * pSrc,
   q31_t * pDst,
   uint32_t blockSize);
   /**
    * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
    * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
    * @param[in]  *pSrc      points to the block of input data.
    * @param[out] *pDst      points to the block of output data.
    * @param[in]  blockSize  number of samples to process.
    * @return     none.
    */
   void arm_biquad_cascade_df1_fast_q31(
   const arm_biquad_casd_df1_inst_q31 * S,
   q31_t * pSrc,
   q31_t * pDst,
   uint32_t blockSize);
   /**
    * @brief  Initialization function for the Q31 Biquad cascade filter.
    * @param[in,out] *S           points to an instance of the Q31 Biquad cascade structure.
    * @param[in]     numStages      number of 2nd order stages in the filter.
    * @param[in]     *pCoeffs     points to the filter coefficients.
    * @param[in]     *pState      points to the state buffer.
    * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
    * @return        none
    */
   void arm_biquad_cascade_df1_init_q31(
   arm_biquad_casd_df1_inst_q31 * S,
   uint8_t numStages,
   q31_t * pCoeffs,
   q31_t * pState,
   int8_t postShift);
   /**
    * @brief Processing function for the floating-point Biquad cascade filter.
    * @param[in]  *S         points to an instance of the floating-point Biquad cascade structure.
    * @param[in]  *pSrc      points to the block of input data.
    * @param[out] *pDst      points to the block of output data.
    * @param[in]  blockSize  number of samples to process.
    * @return     none.
    */
   void arm_biquad_cascade_df1_f32(
   const arm_biquad_casd_df1_inst_f32 * S,
   float32_t * pSrc,
   float32_t * pDst,
   uint32_t blockSize);
   /**
    * @brief  Initialization function for the floating-point Biquad cascade filter.
    * @param[in,out] *S           points to an instance of the floating-point Biquad cascade structure.
    * @param[in]     numStages    number of 2nd order stages in the filter.
    * @param[in]     *pCoeffs     points to the filter coefficients.
    * @param[in]     *pState      points to the state buffer.
    * @return        none
    */
   void arm_biquad_cascade_df1_init_f32(
   arm_biquad_casd_df1_inst_f32 * S,
   uint8_t numStages,
   float32_t * pCoeffs,
   float32_t * pState);
   /**
    * @brief Instance structure for the floating-point matrix structure.
    */
   typedef struct
+  {
     uint16_t numRows;     /**< number of rows of the matrix.     */
     uint16_t numCols;     /**< number of columns of the matrix.  */
     float32_t *pData;     /**< points to the data of the matrix. */
   } arm_matrix_instance_f32;
   /**
    * @brief Instance structure for the Q15 matrix structure.
    */
   typedef struct
+  {
     uint16_t numRows;     /**< number of rows of the matrix.     */
     uint16_t numCols;     /**< number of columns of the matrix.  */
     q15_t *pData;         /**< points to the data of the matrix. */
   } arm_matrix_instance_q15;
   /**
    * @brief Instance structure for the Q31 matrix structure.
    */
   typedef struct
+  {
     uint16_t numRows;     /**< number of rows of the matrix.     */
     uint16_t numCols;     /**< number of columns of the matrix.  */
     q31_t *pData;         /**< points to the data of the matrix. */
   } arm_matrix_instance_q31;
   /**
    * @brief Floating-point matrix addition.
    * @param[in]       *pSrcA points to the first input matrix structure
    * @param[in]       *pSrcB points to the second input matrix structure
    * @param[out]      *pDst points to output matrix structure
    * @return     The function returns either
    * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
    */
   arm_status arm_mat_add_f32(
   const arm_matrix_instance_f32 * pSrcA,
   const arm_matrix_instance_f32 * pSrcB,
   arm_matrix_instance_f32 * pDst);
   /**
    * @brief Q15 matrix addition.
    * @param[in]       *pSrcA points to the first input matrix structure
    * @param[in]       *pSrcB points to the second input matrix structure
    * @param[out]      *pDst points to output matrix structure
    * @return     The function returns either
    * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
    */
   arm_status arm_mat_add_q15(
   const arm_matrix_instance_q15 * pSrcA,
   const arm_matrix_instance_q15 * pSrcB,
   arm_matrix_instance_q15 * pDst);
   /**
    * @brief Q31 matrix addition.
    * @param[in]       *pSrcA points to the first input matrix structure
    * @param[in]       *pSrcB points to the second input matrix structure
    * @param[out]      *pDst points to output matrix structure
    * @return     The function returns either
    * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
    */
   arm_status arm_mat_add_q31(
   const arm_matrix_instance_q31 * pSrcA,
   const arm_matrix_instance_q31 * pSrcB,
   arm_matrix_instance_q31 * pDst);
   /**
    * @brief Floating-point matrix transpose.
    * @param[in]  *pSrc points to the input matrix
    * @param[out] *pDst points to the output matrix
    * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
    * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
    */
   arm_status arm_mat_trans_f32(
   const arm_matrix_instance_f32 * pSrc,
   arm_matrix_instance_f32 * pDst);
   /**
    * @brief Q15 matrix transpose.
    * @param[in]  *pSrc points to the input matrix
    * @param[out] *pDst points to the output matrix
    * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
    * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
    */
   arm_status arm_mat_trans_q15(
   const arm_matrix_instance_q15 * pSrc,
   arm_matrix_instance_q15 * pDst);
   /**
    * @brief Q31 matrix transpose.
    * @param[in]  *pSrc points to the input matrix
    * @param[out] *pDst points to the output matrix
    * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
    * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
    */
   arm_status arm_mat_trans_q31(
   const arm_matrix_instance_q31 * pSrc,
   arm_matrix_instance_q31 * pDst);
   /**
    * @brief Floating-point matrix multiplication
    * @param[in]       *pSrcA points to the first input matrix structure
    * @param[in]       *pSrcB points to the second input matrix structure
    * @param[out]      *pDst points to output matrix structure
    * @return     The function returns either
    * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
    */
   arm_status arm_mat_mult_f32(
   const arm_matrix_instance_f32 * pSrcA,
   const arm_matrix_instance_f32 * pSrcB,
   arm_matrix_instance_f32 * pDst);
   /**
    * @brief Q15 matrix multiplication
    * @param[in]       *pSrcA points to the first input matrix structure
    * @param[in]       *pSrcB points to the second input matrix structure
    * @param[out]      *pDst points to output matrix structure
    * @param[in]		  *pState points to the array for storing intermediate results
    * @return     The function returns either
    * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
    */
   arm_status arm_mat_mult_q15(
   const arm_matrix_instance_q15 * pSrcA,
   const arm_matrix_instance_q15 * pSrcB,
   arm_matrix_instance_q15 * pDst,
   q15_t * pState);
   /**
    * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
    * @param[in]       *pSrcA  points to the first input matrix structure
    * @param[in]       *pSrcB  points to the second input matrix structure
    * @param[out]      *pDst   points to output matrix structure
    * @param[in]		  *pState points to the array for storing intermediate results
    * @return     The function returns either
    * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
    */
   arm_status arm_mat_mult_fast_q15(
   const arm_matrix_instance_q15 * pSrcA,
   const arm_matrix_instance_q15 * pSrcB,
   arm_matrix_instance_q15 * pDst,
   q15_t * pState);
   /**
    * @brief Q31 matrix multiplication
    * @param[in]       *pSrcA points to the first input matrix structure
    * @param[in]       *pSrcB points to the second input matrix structure
    * @param[out]      *pDst points to output matrix structure
    * @return     The function returns either
    * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
    */
   arm_status arm_mat_mult_q31(
   const arm_matrix_instance_q31 * pSrcA,
   const arm_matrix_instance_q31 * pSrcB,
   arm_matrix_instance_q31 * pDst);
   /**
    * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
    * @param[in]       *pSrcA points to the first input matrix structure
    * @param[in]       *pSrcB points to the second input matrix structure
    * @param[out]      *pDst points to output matrix structure
    * @return     The function returns either
    * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
    */
   arm_status arm_mat_mult_fast_q31(
   const arm_matrix_instance_q31 * pSrcA,
   const arm_matrix_instance_q31 * pSrcB,
   arm_matrix_instance_q31 * pDst);
   /**
    * @brief Floating-point matrix subtraction
    * @param[in]       *pSrcA points to the first input matrix structure
    * @param[in]       *pSrcB points to the second input matrix structure
    * @param[out]      *pDst points to output matrix structure
    * @return     The function returns either
    * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
    */
   arm_status arm_mat_sub_f32(
   const arm_matrix_instance_f32 * pSrcA,
   const arm_matrix_instance_f32 * pSrcB,
   arm_matrix_instance_f32 * pDst);
   /**
    * @brief Q15 matrix subtraction
    * @param[in]       *pSrcA points to the first input matrix structure
    * @param[in]       *pSrcB points to the second input matrix structure
    * @param[out]      *pDst points to output matrix structure
    * @return     The function returns either
    * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
    */
   arm_status arm_mat_sub_q15(
   const arm_matrix_instance_q15 * pSrcA,
   const arm_matrix_instance_q15 * pSrcB,
   arm_matrix_instance_q15 * pDst);
   /**
    * @brief Q31 matrix subtraction
    * @param[in]       *pSrcA points to the first input matrix structure
    * @param[in]       *pSrcB points to the second input matrix structure
    * @param[out]      *pDst points to output matrix structure
    * @return     The function returns either
    * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
    */
   arm_status arm_mat_sub_q31(
   const arm_matrix_instance_q31 * pSrcA,
   const arm_matrix_instance_q31 * pSrcB,
   arm_matrix_instance_q31 * pDst);
   /**
    * @brief Floating-point matrix scaling.
    * @param[in]  *pSrc points to the input matrix
    * @param[in]  scale scale factor
    * @param[out] *pDst points to the output matrix
    * @return     The function returns either
    * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
    */
   arm_status arm_mat_scale_f32(
   const arm_matrix_instance_f32 * pSrc,
   float32_t scale,
   arm_matrix_instance_f32 * pDst);
   /**
    * @brief Q15 matrix scaling.
    * @param[in]       *pSrc points to input matrix
    * @param[in]       scaleFract fractional portion of the scale factor
    * @param[in]       shift number of bits to shift the result by
    * @param[out]      *pDst points to output matrix
    * @return     The function returns either
    * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
    */
   arm_status arm_mat_scale_q15(
   const arm_matrix_instance_q15 * pSrc,
   q15_t scaleFract,
   int32_t shift,
   arm_matrix_instance_q15 * pDst);
   /**
    * @brief Q31 matrix scaling.
    * @param[in]       *pSrc points to input matrix
    * @param[in]       scaleFract fractional portion of the scale factor
    * @param[in]       shift number of bits to shift the result by
    * @param[out]      *pDst points to output matrix structure
    * @return     The function returns either
    * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
    */
   arm_status arm_mat_scale_q31(
   const arm_matrix_instance_q31 * pSrc,
   q31_t scaleFract,
   int32_t shift,
   arm_matrix_instance_q31 * pDst);
   /**
    * @brief  Q31 matrix initialization.
    * @param[in,out] *S             points to an instance of the floating-point matrix structure.
    * @param[in]     nRows          number of rows in the matrix.
    * @param[in]     nColumns       number of columns in the matrix.
    * @param[in]     *pData	       points to the matrix data array.
    * @return        none
    */
   void arm_mat_init_q31(
   arm_matrix_instance_q31 * S,
   uint16_t nRows,
   uint16_t nColumns,
   q31_t * pData);
   /**
    * @brief  Q15 matrix initialization.
    * @param[in,out] *S             points to an instance of the floating-point matrix structure.
    * @param[in]     nRows          number of rows in the matrix.
    * @param[in]     nColumns       number of columns in the matrix.
    * @param[in]     *pData	       points to the matrix data array.
    * @return        none
    */
   void arm_mat_init_q15(
   arm_matrix_instance_q15 * S,
   uint16_t nRows,
   uint16_t nColumns,
   q15_t * pData);
   /**
    * @brief  Floating-point matrix initialization.
    * @param[in,out] *S             points to an instance of the floating-point matrix structure.
    * @param[in]     nRows          number of rows in the matrix.
    * @param[in]     nColumns       number of columns in the matrix.
    * @param[in]     *pData	       points to the matrix data array.
    * @return        none
    */
   void arm_mat_init_f32(
   arm_matrix_instance_f32 * S,
   uint16_t nRows,
   uint16_t nColumns,
   float32_t * pData);
   /**
    * @brief Instance structure for the Q15 PID Control.
    */
   typedef struct
+  {
     q15_t A0;    /**< The derived gain, A0 = Kp + Ki + Kd . */
 #ifdef ARM_MATH_CM0_FAMILY
     q15_t A1;
     q15_t A2;
 #else
     q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
 #endif
     q15_t state[3];       /**< The state array of length 3. */
     q15_t Kp;           /**< The proportional gain. */
     q15_t Ki;           /**< The integral gain. */
     q15_t Kd;           /**< The derivative gain. */
   } arm_pid_instance_q15;
   /**
    * @brief Instance structure for the Q31 PID Control.
    */
   typedef struct
+  {
     q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
     q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
     q31_t A2;            /**< The derived gain, A2 = Kd . */
     q31_t state[3];      /**< The state array of length 3. */
     q31_t Kp;            /**< The proportional gain. */
     q31_t Ki;            /**< The integral gain. */
     q31_t Kd;            /**< The derivative gain. */
   } arm_pid_instance_q31;
   /**
    * @brief Instance structure for the floating-point PID Control.
    */
   typedef struct
+  {
     float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
     float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
     float32_t A2;          /**< The derived gain, A2 = Kd . */
     float32_t state[3];    /**< The state array of length 3. */
     float32_t Kp;               /**< The proportional gain. */
     float32_t Ki;               /**< The integral gain. */
     float32_t Kd;               /**< The derivative gain. */
   } arm_pid_instance_f32;
   /**
    * @brief  Initialization function for the floating-point PID Control.
    * @param[in,out] *S      points to an instance of the PID structure.
    * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
    * @return none.
    */
   void arm_pid_init_f32(
   arm_pid_instance_f32 * S,
   int32_t resetStateFlag);
   /**
    * @brief  Reset function for the floating-point PID Control.
    * @param[in,out] *S is an instance of the floating-point PID Control structure
    * @return none
    */
   void arm_pid_reset_f32(
   arm_pid_instance_f32 * S);
   /**
    * @brief  Initialization function for the Q31 PID Control.
    * @param[in,out] *S points to an instance of the Q15 PID structure.
    * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
    * @return none.
    */
   void arm_pid_init_q31(
   arm_pid_instance_q31 * S,
   int32_t resetStateFlag);
   /**
    * @brief  Reset function for the Q31 PID Control.
    * @param[in,out] *S points to an instance of the Q31 PID Control structure
    * @return none
    */
   void arm_pid_reset_q31(
   arm_pid_instance_q31 * S);
   /**
    * @brief  Initialization function for the Q15 PID Control.
    * @param[in,out] *S points to an instance of the Q15 PID structure.
    * @param[in] resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
    * @return none.
    */
   void arm_pid_init_q15(
   arm_pid_instance_q15 * S,
   int32_t resetStateFlag);
   /**
    * @brief  Reset function for the Q15 PID Control.
    * @param[in,out] *S points to an instance of the q15 PID Control structure
    * @return none
    */
   void arm_pid_reset_q15(
   arm_pid_instance_q15 * S);
   /**
    * @brief Instance structure for the floating-point Linear Interpolate function.
    */
   typedef struct
+  {
     uint32_t nValues;           /**< nValues */
     float32_t x1;               /**< x1 */
     float32_t xSpacing;         /**< xSpacing */
     float32_t *pYData;          /**< pointer to the table of Y values */
   } arm_linear_interp_instance_f32;
   /**
    * @brief Instance structure for the floating-point bilinear interpolation function.
    */
   typedef struct
+  {
     uint16_t numRows;   /**< number of rows in the data table. */
     uint16_t numCols;   /**< number of columns in the data table. */
     float32_t *pData;   /**< points to the data table. */
   } arm_bilinear_interp_instance_f32;
    /**
    * @brief Instance structure for the Q31 bilinear interpolation function.
    */
   typedef struct
+  {
     uint16_t numRows;   /**< number of rows in the data table. */
     uint16_t numCols;   /**< number of columns in the data table. */
     q31_t *pData;       /**< points to the data table. */
   } arm_bilinear_interp_instance_q31;
    /**
    * @brief Instance structure for the Q15 bilinear interpolation function.
    */
   typedef struct
+  {
     uint16_t numRows;   /**< number of rows in the data table. */
     uint16_t numCols;   /**< number of columns in the data table. */
     q15_t *pData;       /**< points to the data table. */
   } arm_bilinear_interp_instance_q15;
    /**
    * @brief Instance structure for the Q15 bilinear interpolation function.
    */
   typedef struct
+  {
     uint16_t numRows;   /**< number of rows in the data table. */
     uint16_t numCols;   /**< number of columns in the data table. */
     q7_t *pData;                /**< points to the data table. */
   } arm_bilinear_interp_instance_q7;
   /**
    * @brief Q7 vector multiplication.
    * @param[in]       *pSrcA points to the first input vector
    * @param[in]       *pSrcB points to the second input vector
    * @param[out]      *pDst  points to the output vector
    * @param[in]       blockSize number of samples in each vector
    * @return none.
    */
   void arm_mult_q7(
   q7_t * pSrcA,
   q7_t * pSrcB,
   q7_t * pDst,
   uint32_t blockSize);
   /**
    * @brief Q15 vector multiplication.
    * @param[in]       *pSrcA points to the first input vector
    * @param[in]       *pSrcB points to the second input vector
    * @param[out]      *pDst  points to the output vector
    * @param[in]       blockSize number of samples in each vector
    * @return none.
    */
   void arm_mult_q15(
   q15_t * pSrcA,
   q15_t * pSrcB,
   q15_t * pDst,
   uint32_t blockSize);
   /**
    * @brief Q31 vector multiplication.
    * @param[in]       *pSrcA points to the first input vector
    * @param[in]       *pSrcB points to the second input vector
    * @param[out]      *pDst points to the output vector
    * @param[in]       blockSize number of samples in each vector
    * @return none.
    */
   void arm_mult_q31(
   q31_t * pSrcA,
   q31_t * pSrcB,
   q31_t * pDst,
   uint32_t blockSize);
   /**
    * @brief Floating-point vector multiplication.
    * @param[in]       *pSrcA points to the first input vector
    * @param[in]       *pSrcB points to the second input vector
    * @param[out]      *pDst points to the output vector
    * @param[in]       blockSize number of samples in each vector
    * @return none.
    */
   void arm_mult_f32(
   float32_t * pSrcA,
   float32_t * pSrcB,
   float32_t * pDst,
   uint32_t blockSize);
   /**
    * @brief Instance structure for the Q15 CFFT/CIFFT function.
    */
   typedef struct
+  {
     uint16_t fftLen;                 /**< length of the FFT. */
     uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
     uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
     q15_t *pTwiddle;                     /**< points to the Sin twiddle factor table. */
     uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
     uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
     uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
   } arm_cfft_radix2_instance_q15;
   arm_status arm_cfft_radix2_init_q15(
   arm_cfft_radix2_instance_q15 * S,
   uint16_t fftLen,
   uint8_t ifftFlag,
   uint8_t bitReverseFlag);
   void arm_cfft_radix2_q15(
   const arm_cfft_radix2_instance_q15 * S,
   q15_t * pSrc);
   /**
    * @brief Instance structure for the Q15 CFFT/CIFFT function.
    */
   typedef struct
+  {
     uint16_t fftLen;                 /**< length of the FFT. */
     uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
     uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
     q15_t *pTwiddle;                 /**< points to the twiddle factor table. */
     uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
     uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
     uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
   } arm_cfft_radix4_instance_q15;
   arm_status arm_cfft_radix4_init_q15(
   arm_cfft_radix4_instance_q15 * S,
   uint16_t fftLen,
   uint8_t ifftFlag,
   uint8_t bitReverseFlag);
   void arm_cfft_radix4_q15(
   const arm_cfft_radix4_instance_q15 * S,
   q15_t * pSrc);
   /**
    * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
    */
   typedef struct
+  {
     uint16_t fftLen;                 /**< length of the FFT. */
     uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
     uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
     q31_t *pTwiddle;                     /**< points to the Twiddle factor table. */
     uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
     uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
     uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
   } arm_cfft_radix2_instance_q31;
   arm_status arm_cfft_radix2_init_q31(
   arm_cfft_radix2_instance_q31 * S,
   uint16_t fftLen,
   uint8_t ifftFlag,
   uint8_t bitReverseFlag);
   void arm_cfft_radix2_q31(
   const arm_cfft_radix2_instance_q31 * S,
   q31_t * pSrc);
   /**
    * @brief Instance structure for the Q31 CFFT/CIFFT function.
    */
   typedef struct
+  {
     uint16_t fftLen;                 /**< length of the FFT. */
     uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
     uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
     q31_t *pTwiddle;                 /**< points to the twiddle factor table. */
     uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
     uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
     uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
   } arm_cfft_radix4_instance_q31;
   void arm_cfft_radix4_q31(
   const arm_cfft_radix4_instance_q31 * S,
   q31_t * pSrc);
   arm_status arm_cfft_radix4_init_q31(
   arm_cfft_radix4_instance_q31 * S,
   uint16_t fftLen,
   uint8_t ifftFlag,
   uint8_t bitReverseFlag);
   /**
    * @brief Instance structure for the floating-point CFFT/CIFFT function.
    */
   typedef struct
+  {
     uint16_t fftLen;                   /**< length of the FFT. */
     uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
     uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
     float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
     uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
     uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
     uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
     float32_t onebyfftLen;                 /**< value of 1/fftLen. */
   } arm_cfft_radix2_instance_f32;
 /* Deprecated */
   arm_status arm_cfft_radix2_init_f32(
   arm_cfft_radix2_instance_f32 * S,
   uint16_t fftLen,
   uint8_t ifftFlag,
   uint8_t bitReverseFlag);
 /* Deprecated */
   void arm_cfft_radix2_f32(
   const arm_cfft_radix2_instance_f32 * S,
   float32_t * pSrc);
   /**
    * @brief Instance structure for the floating-point CFFT/CIFFT function.
    */
   typedef struct
+  {
     uint16_t fftLen;                   /**< length of the FFT. */
     uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
     uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
     float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
     uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
     uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
     uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
     float32_t onebyfftLen;                 /**< value of 1/fftLen. */
   } arm_cfft_radix4_instance_f32;
 /* Deprecated */
   arm_status arm_cfft_radix4_init_f32(
   arm_cfft_radix4_instance_f32 * S,
   uint16_t fftLen,
   uint8_t ifftFlag,
   uint8_t bitReverseFlag);
 /* Deprecated */
   void arm_cfft_radix4_f32(
   const arm_cfft_radix4_instance_f32 * S,
   float32_t * pSrc);
   /**
    * @brief Instance structure for the floating-point CFFT/CIFFT function.
    */
   typedef struct
+  {
     uint16_t fftLen;                   /**< length of the FFT. */
     const float32_t *pTwiddle;         /**< points to the Twiddle factor table. */
     const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
     uint16_t bitRevLength;             /**< bit reversal table length. */
   } arm_cfft_instance_f32;
   void arm_cfft_f32(
   const arm_cfft_instance_f32 * S,
   float32_t * p1,
   uint8_t ifftFlag,
   uint8_t bitReverseFlag);
   /**
    * @brief Instance structure for the Q15 RFFT/RIFFT function.
    */
   typedef struct
+  {
     uint32_t fftLenReal;                      /**< length of the real FFT. */
     uint32_t fftLenBy2;                       /**< length of the complex FFT. */
     uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
     uint8_t bitReverseFlagR;                      /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
     uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
     q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */
     q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */
     arm_cfft_radix4_instance_q15 *pCfft;          /**< points to the complex FFT instance. */
   } arm_rfft_instance_q15;
   arm_status arm_rfft_init_q15(
   arm_rfft_instance_q15 * S,
   arm_cfft_radix4_instance_q15 * S_CFFT,
   uint32_t fftLenReal,
   uint32_t ifftFlagR,
   uint32_t bitReverseFlag);
   void arm_rfft_q15(
   const arm_rfft_instance_q15 * S,
   q15_t * pSrc,
   q15_t * pDst);
   /**
    * @brief Instance structure for the Q31 RFFT/RIFFT function.
    */
   typedef struct
+  {
     uint32_t fftLenReal;                        /**< length of the real FFT. */
     uint32_t fftLenBy2;                         /**< length of the complex FFT. */
     uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
     uint8_t bitReverseFlagR;                        /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
     uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
     q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */
     q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */
     arm_cfft_radix4_instance_q31 *pCfft;        /**< points to the complex FFT instance. */
   } arm_rfft_instance_q31;
   arm_status arm_rfft_init_q31(
   arm_rfft_instance_q31 * S,
   arm_cfft_radix4_instance_q31 * S_CFFT,
   uint32_t fftLenReal,
   uint32_t ifftFlagR,
   uint32_t bitReverseFlag);
   void arm_rfft_q31(
   const arm_rfft_instance_q31 * S,
   q31_t * pSrc,
   q31_t * pDst);
   /**
    * @brief Instance structure for the floating-point RFFT/RIFFT function.
    */
   typedef struct
+  {
     uint32_t fftLenReal;                        /**< length of the real FFT. */
     uint16_t fftLenBy2;                         /**< length of the complex FFT. */
     uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
     uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
     uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
     float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */
     float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
     arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */
   } arm_rfft_instance_f32;
   arm_status arm_rfft_init_f32(
   arm_rfft_instance_f32 * S,
   arm_cfft_radix4_instance_f32 * S_CFFT,
   uint32_t fftLenReal,
   uint32_t ifftFlagR,
   uint32_t bitReverseFlag);
   void arm_rfft_f32(
   const arm_rfft_instance_f32 * S,
   float32_t * pSrc,
   float32_t * pDst);
   /**
    * @brief Instance structure for the floating-point RFFT/RIFFT function.
    */
 typedef struct
+  {
     arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */
     uint16_t fftLenRFFT;                        /**< length of the real sequence */
 	float32_t * pTwiddleRFFT;					/**< Twiddle factors real stage  */
   } arm_rfft_fast_instance_f32 ;
 arm_status arm_rfft_fast_init_f32 (
 	arm_rfft_fast_instance_f32 * S,
 	uint16_t fftLen);
 void arm_rfft_fast_f32(
   arm_rfft_fast_instance_f32 * S,
   float32_t * p, float32_t * pOut,
   uint8_t ifftFlag);
   /**
    * @brief Instance structure for the floating-point DCT4/IDCT4 function.
    */
   typedef struct
+  {
     uint16_t N;                         /**< length of the DCT4. */
     uint16_t Nby2;                      /**< half of the length of the DCT4. */
     float32_t normalize;                /**< normalizing factor. */
     float32_t *pTwiddle;                /**< points to the twiddle factor table. */
     float32_t *pCosFactor;              /**< points to the cosFactor table. */
     arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */
     arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
   } arm_dct4_instance_f32;
   /**
    * @brief  Initialization function for the floating-point DCT4/IDCT4.
    * @param[in,out] *S         points to an instance of floating-point DCT4/IDCT4 structure.
    * @param[in]     *S_RFFT    points to an instance of floating-point RFFT/RIFFT structure.
    * @param[in]     *S_CFFT    points to an instance of floating-point CFFT/CIFFT structure.
    * @param[in]     N          length of the DCT4.
    * @param[in]     Nby2       half of the length of the DCT4.
    * @param[in]     normalize  normalizing factor.
    * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
    */
   arm_status arm_dct4_init_f32(
   arm_dct4_instance_f32 * S,
   arm_rfft_instance_f32 * S_RFFT,
   arm_cfft_radix4_instance_f32 * S_CFFT,
   uint16_t N,
   uint16_t Nby2,
   float32_t normalize);
   /**
    * @brief Processing function for the floating-point DCT4/IDCT4.
    * @param[in]       *S             points to an instance of the floating-point DCT4/IDCT4 structure.
    * @param[in]       *pState        points to state buffer.
    * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
    * @return none.
    */
   void arm_dct4_f32(
   const arm_dct4_instance_f32 * S,
   float32_t * pState,
   float32_t * pInlineBuffer);
   /**
    * @brief Instance structure for the Q31 DCT4/IDCT4 function.
    */
   typedef struct
+  {
     uint16_t N;                         /**< length of the DCT4. */
     uint16_t Nby2;                      /**< half of the length of the DCT4. */
     q31_t normalize;                    /**< normalizing factor. */
     q31_t *pTwiddle;                    /**< points to the twiddle factor table. */
     q31_t *pCosFactor;                  /**< points to the cosFactor table. */
     arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */
     arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
   } arm_dct4_instance_q31;
   /**
    * @brief  Initialization function for the Q31 DCT4/IDCT4.
    * @param[in,out] *S         points to an instance of Q31 DCT4/IDCT4 structure.
    * @param[in]     *S_RFFT    points to an instance of Q31 RFFT/RIFFT structure
    * @param[in]     *S_CFFT    points to an instance of Q31 CFFT/CIFFT structure
    * @param[in]     N          length of the DCT4.
    * @param[in]     Nby2       half of the length of the DCT4.
    * @param[in]     normalize  normalizing factor.
    * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
    */
   arm_status arm_dct4_init_q31(
   arm_dct4_instance_q31 * S,
   arm_rfft_instance_q31 * S_RFFT,
   arm_cfft_radix4_instance_q31 * S_CFFT,
   uint16_t N,
   uint16_t Nby2,
   q31_t normalize);
   /**
    * @brief Processing function for the Q31 DCT4/IDCT4.
    * @param[in]       *S             points to an instance of the Q31 DCT4 structure.
    * @param[in]       *pState        points to state buffer.
    * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
    * @return none.
    */
   void arm_dct4_q31(
   const arm_dct4_instance_q31 * S,
   q31_t * pState,
   q31_t * pInlineBuffer);
   /**
    * @brief Instance structure for the Q15 DCT4/IDCT4 function.
    */
   typedef struct
+  {
     uint16_t N;                         /**< length of the DCT4. */
     uint16_t Nby2;                      /**< half of the length of the DCT4. */
     q15_t normalize;                    /**< normalizing factor. */
     q15_t *pTwiddle;                    /**< points to the twiddle factor table. */
     q15_t *pCosFactor;                  /**< points to the cosFactor table. */
     arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */
     arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
   } arm_dct4_instance_q15;
   /**
    * @brief  Initialization function for the Q15 DCT4/IDCT4.
    * @param[in,out] *S         points to an instance of Q15 DCT4/IDCT4 structure.
    * @param[in]     *S_RFFT    points to an instance of Q15 RFFT/RIFFT structure.
    * @param[in]     *S_CFFT    points to an instance of Q15 CFFT/CIFFT structure.
    * @param[in]     N          length of the DCT4.
    * @param[in]     Nby2       half of the length of the DCT4.
    * @param[in]     normalize  normalizing factor.
    * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
    */
   arm_status arm_dct4_init_q15(
   arm_dct4_instance_q15 * S,
   arm_rfft_instance_q15 * S_RFFT,
   arm_cfft_radix4_instance_q15 * S_CFFT,
   uint16_t N,
   uint16_t Nby2,
   q15_t normalize);
   /**
    * @brief Processing function for the Q15 DCT4/IDCT4.
    * @param[in]       *S             points to an instance of the Q15 DCT4 structure.
    * @param[in]       *pState        points to state buffer.
    * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
    * @return none.
    */
   void arm_dct4_q15(
   const arm_dct4_instance_q15 * S,
   q15_t * pState,
   q15_t * pInlineBuffer);
   /**
    * @brief Floating-point vector addition.
    * @param[in]       *pSrcA points to the first input vector
    * @param[in]       *pSrcB points to the second input vector
    * @param[out]      *pDst points to the output vector
    * @param[in]       blockSize number of samples in each vector
    * @return none.
    */
   void arm_add_f32(
   float32_t * pSrcA,
   float32_t * pSrcB,
   float32_t * pDst,
   uint32_t blockSize);
   /**
    * @brief Q7 vector addition.
    * @param[in]       *pSrcA points to the first input vector
    * @param[in]       *pSrcB points to the second input vector
    * @param[out]      *pDst points to the output vector
    * @param[in]       blockSize number of samples in each vector
    * @return none.
    */
   void arm_add_q7(
   q7_t * pSrcA,
   q7_t * pSrcB,
   q7_t * pDst,
   uint32_t blockSize);
   /**
    * @brief Q15 vector addition.
    * @param[in]       *pSrcA points to the first input vector
    * @param[in]       *pSrcB points to the second input vector
    * @param[out]      *pDst points to the output vector
    * @param[in]       blockSize number of samples in each vector
    * @return none.
    */
   void arm_add_q15(
   q15_t * pSrcA,
   q15_t * pSrcB,
   q15_t * pDst,
   uint32_t blockSize);
   /**
    * @brief Q31 vector addition.
    * @param[in]       *pSrcA points to the first input vector
    * @param[in]       *pSrcB points to the second input vector
    * @param[out]      *pDst points to the output vector
    * @param[in]       blockSize number of samples in each vector
    * @return none.
    */
   void arm_add_q31(
   q31_t * pSrcA,
   q31_t * pSrcB,
   q31_t * pDst,
   uint32_t blockSize);
   /**
    * @brief Floating-point vector subtraction.
    * @param[in]       *pSrcA points to the first input vector
    * @param[in]       *pSrcB points to the second input vector
    * @param[out]      *pDst points to the output vector
    * @param[in]       blockSize number of samples in each vector
    * @return none.
    */
   void arm_sub_f32(
   float32_t * pSrcA,
   float32_t * pSrcB,
   float32_t * pDst,
   uint32_t blockSize);
   /**
    * @brief Q7 vector subtraction.
    * @param[in]       *pSrcA points to the first input vector
    * @param[in]       *pSrcB points to the second input vector
    * @param[out]      *pDst points to the output vector
    * @param[in]       blockSize number of samples in each vector
    * @return none.
    */
   void arm_sub_q7(
   q7_t * pSrcA,
   q7_t * pSrcB,
   q7_t * pDst,
   uint32_t blockSize);
   /**
    * @brief Q15 vector subtraction.
    * @param[in]       *pSrcA points to the first input vector
    * @param[in]       *pSrcB points to the second input vector
    * @param[out]      *pDst points to the output vector
    * @param[in]       blockSize number of samples in each vector
    * @return none.
    */
   void arm_sub_q15(
   q15_t * pSrcA,
   q15_t * pSrcB,
   q15_t * pDst,
   uint32_t blockSize);
   /**
    * @brief Q31 vector subtraction.
    * @param[in]       *pSrcA points to the first input vector
    * @param[in]       *pSrcB points to the second input vector
    * @param[out]      *pDst points to the output vector
    * @param[in]       blockSize number of samples in each vector
    * @return none.
    */
   void arm_sub_q31(
   q31_t * pSrcA,
   q31_t * pSrcB,
   q31_t * pDst,
   uint32_t blockSize);
   /**
    * @brief Multiplies a floating-point vector by a scalar.
    * @param[in]       *pSrc points to the input vector
    * @param[in]       scale scale factor to be applied
    * @param[out]      *pDst points to the output vector
    * @param[in]       blockSize number of samples in the vector
    * @return none.
    */
   void arm_scale_f32(
   float32_t * pSrc,
   float32_t scale,
   float32_t * pDst,
   uint32_t blockSize);
   /**
    * @brief Multiplies a Q7 vector by a scalar.
    * @param[in]       *pSrc points to the input vector
    * @param[in]       scaleFract fractional portion of the scale value
    * @param[in]       shift number of bits to shift the result by
    * @param[out]      *pDst points to the output vector
    * @param[in]       blockSize number of samples in the vector
    * @return none.
    */
   void arm_scale_q7(
   q7_t * pSrc,
   q7_t scaleFract,
   int8_t shift,
   q7_t * pDst,
   uint32_t blockSize);
   /**
    * @brief Multiplies a Q15 vector by a scalar.
    * @param[in]       *pSrc points to the input vector
    * @param[in]       scaleFract fractional portion of the scale value
    * @param[in]       shift number of bits to shift the result by
    * @param[out]      *pDst points to the output vector
    * @param[in]       blockSize number of samples in the vector
    * @return none.
    */
   void arm_scale_q15(
   q15_t * pSrc,
   q15_t scaleFract,
   int8_t shift,
   q15_t * pDst,
   uint32_t blockSize);
   /**
    * @brief Multiplies a Q31 vector by a scalar.
    * @param[in]       *pSrc points to the input vector
    * @param[in]       scaleFract fractional portion of the scale value
    * @param[in]       shift number of bits to shift the result by
    * @param[out]      *pDst points to the output vector
    * @param[in]       blockSize number of samples in the vector
    * @return none.
    */
   void arm_scale_q31(
   q31_t * pSrc,
   q31_t scaleFract,
   int8_t shift,
   q31_t * pDst,
   uint32_t blockSize);
   /**
    * @brief Q7 vector absolute value.
    * @param[in]       *pSrc points to the input buffer
    * @param[out]      *pDst points to the output buffer
    * @param[in]       blockSize number of samples in each vector
    * @return none.
    */
   void arm_abs_q7(
   q7_t * pSrc,
   q7_t * pDst,
   uint32_t blockSize);
   /**
    * @brief Floating-point vector absolute value.
    * @param[in]       *pSrc points to the input buffer
    * @param[out]      *pDst points to the output buffer
    * @param[in]       blockSize number of samples in each vector
    * @return none.
    */
   void arm_abs_f32(
   float32_t * pSrc,
   float32_t * pDst,
   uint32_t blockSize);
   /**
    * @brief Q15 vector absolute value.
    * @param[in]       *pSrc points to the input buffer
    * @param[out]      *pDst points to the output buffer
    * @param[in]       blockSize number of samples in each vector
    * @return none.
    */
   void arm_abs_q15(
   q15_t * pSrc,
   q15_t * pDst,
   uint32_t blockSize);
   /**
    * @brief Q31 vector absolute value.
    * @param[in]       *pSrc points to the input buffer
    * @param[out]      *pDst points to the output buffer
    * @param[in]       blockSize number of samples in each vector
    * @return none.
    */
   void arm_abs_q31(
   q31_t * pSrc,
   q31_t * pDst,
   uint32_t blockSize);
   /**
    * @brief Dot product of floating-point vectors.
    * @param[in]       *pSrcA points to the first input vector
    * @param[in]       *pSrcB points to the second input vector
    * @param[in]       blockSize number of samples in each vector
    * @param[out]      *result output result returned here
    * @return none.
    */
   void arm_dot_prod_f32(
   float32_t * pSrcA,
   float32_t * pSrcB,
   uint32_t blockSize,
   float32_t * result);
   /**
    * @brief Dot product of Q7 vectors.
    * @param[in]       *pSrcA points to the first input vector
    * @param[in]       *pSrcB points to the second input vector
    * @param[in]       blockSize number of samples in each vector
    * @param[out]      *result output result returned here
    * @return none.
    */
   void arm_dot_prod_q7(
   q7_t * pSrcA,
   q7_t * pSrcB,
   uint32_t blockSize,
   q31_t * result);
   /**
    * @brief Dot product of Q15 vectors.
    * @param[in]       *pSrcA points to the first input vector
    * @param[in]       *pSrcB points to the second input vector
    * @param[in]       blockSize number of samples in each vector
    * @param[out]      *result output result returned here
    * @return none.
    */
   void arm_dot_prod_q15(
   q15_t * pSrcA,
   q15_t * pSrcB,
   uint32_t blockSize,
   q63_t * result);
   /**
    * @brief Dot product of Q31 vectors.
    * @param[in]       *pSrcA points to the first input vector
    * @param[in]       *pSrcB points to the second input vector
    * @param[in]       blockSize number of samples in each vector
    * @param[out]      *result output result returned here
    * @return none.
    */
   void arm_dot_prod_q31(
   q31_t * pSrcA,
   q31_t * pSrcB,
   uint32_t blockSize,
   q63_t * result);
   /**
    * @brief  Shifts the elements of a Q7 vector a specified number of bits.
    * @param[in]  *pSrc points to the input vector
    * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
    * @param[out]  *pDst points to the output vector
    * @param[in]  blockSize number of samples in the vector
    * @return none.
    */
   void arm_shift_q7(
   q7_t * pSrc,
   int8_t shiftBits,
   q7_t * pDst,
   uint32_t blockSize);
   /**
    * @brief  Shifts the elements of a Q15 vector a specified number of bits.
    * @param[in]  *pSrc points to the input vector
    * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
    * @param[out]  *pDst points to the output vector
    * @param[in]  blockSize number of samples in the vector
    * @return none.
    */
   void arm_shift_q15(
   q15_t * pSrc,
   int8_t shiftBits,
   q15_t * pDst,
   uint32_t blockSize);
   /**
    * @brief  Shifts the elements of a Q31 vector a specified number of bits.
    * @param[in]  *pSrc points to the input vector
    * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
    * @param[out]  *pDst points to the output vector
    * @param[in]  blockSize number of samples in the vector
    * @return none.
    */
   void arm_shift_q31(
   q31_t * pSrc,
   int8_t shiftBits,
   q31_t * pDst,
   uint32_t blockSize);
   /**
    * @brief  Adds a constant offset to a floating-point vector.
    * @param[in]  *pSrc points to the input vector
    * @param[in]  offset is the offset to be added
    * @param[out]  *pDst points to the output vector
    * @param[in]  blockSize number of samples in the vector
    * @return none.
    */
   void arm_offset_f32(
   float32_t * pSrc,
   float32_t offset,
   float32_t * pDst,
   uint32_t blockSize);
   /**
    * @brief  Adds a constant offset to a Q7 vector.
    * @param[in]  *pSrc points to the input vector
    * @param[in]  offset is the offset to be added
    * @param[out]  *pDst points to the output vector
    * @param[in]  blockSize number of samples in the vector
    * @return none.
    */
   void arm_offset_q7(
   q7_t * pSrc,
   q7_t offset,
   q7_t * pDst,
   uint32_t blockSize);
   /**
    * @brief  Adds a constant offset to a Q15 vector.
    * @param[in]  *pSrc points to the input vector
    * @param[in]  offset is the offset to be added
    * @param[out]  *pDst points to the output vector
    * @param[in]  blockSize number of samples in the vector
    * @return none.
    */
   void arm_offset_q15(
   q15_t * pSrc,
   q15_t offset,
   q15_t * pDst,
   uint32_t blockSize);
   /**
    * @brief  Adds a constant offset to a Q31 vector.
    * @param[in]  *pSrc points to the input vector
    * @param[in]  offset is the offset to be added
    * @param[out]  *pDst points to the output vector
    * @param[in]  blockSize number of samples in the vector
    * @return none.
    */
   void arm_offset_q31(
   q31_t * pSrc,
   q31_t offset,
   q31_t * pDst,
   uint32_t blockSize);
   /**
    * @brief  Negates the elements of a floating-point vector.
    * @param[in]  *pSrc points to the input vector
    * @param[out]  *pDst points to the output vector
    * @param[in]  blockSize number of samples in the vector
    * @return none.
    */
   void arm_negate_f32(
   float32_t * pSrc,
   float32_t * pDst,
   uint32_t blockSize);
   /**
    * @brief  Negates the elements of a Q7 vector.
    * @param[in]  *pSrc points to the input vector
    * @param[out]  *pDst points to the output vector
    * @param[in]  blockSize number of samples in the vector
    * @return none.
    */
   void arm_negate_q7(
   q7_t * pSrc,
   q7_t * pDst,
   uint32_t blockSize);
   /**
    * @brief  Negates the elements of a Q15 vector.
    * @param[in]  *pSrc points to the input vector
    * @param[out]  *pDst points to the output vector
    * @param[in]  blockSize number of samples in the vector
    * @return none.
    */
   void arm_negate_q15(
   q15_t * pSrc,
   q15_t * pDst,
   uint32_t blockSize);
   /**
    * @brief  Negates the elements of a Q31 vector.
    * @param[in]  *pSrc points to the input vector
    * @param[out]  *pDst points to the output vector
    * @param[in]  blockSize number of samples in the vector
    * @return none.
    */
   void arm_negate_q31(
   q31_t * pSrc,
   q31_t * pDst,
   uint32_t blockSize);
   /**
    * @brief  Copies the elements of a floating-point vector.
    * @param[in]  *pSrc input pointer
    * @param[out]  *pDst output pointer
    * @param[in]  blockSize number of samples to process
    * @return none.
    */
   void arm_copy_f32(
   float32_t * pSrc,
   float32_t * pDst,
   uint32_t blockSize);
   /**
    * @brief  Copies the elements of a Q7 vector.
    * @param[in]  *pSrc input pointer
    * @param[out]  *pDst output pointer
    * @param[in]  blockSize number of samples to process
    * @return none.
    */
   void arm_copy_q7(
   q7_t * pSrc,
   q7_t * pDst,
   uint32_t blockSize);
   /**
    * @brief  Copies the elements of a Q15 vector.
    * @param[in]  *pSrc input pointer
    * @param[out]  *pDst output pointer
    * @param[in]  blockSize number of samples to process
    * @return none.
    */
   void arm_copy_q15(
   q15_t * pSrc,
   q15_t * pDst,
   uint32_t blockSize);
   /**
    * @brief  Copies the elements of a Q31 vector.
    * @param[in]  *pSrc input pointer
    * @param[out]  *pDst output pointer
    * @param[in]  blockSize number of samples to process
    * @return none.
    */
   void arm_copy_q31(
   q31_t * pSrc,
   q31_t * pDst,
   uint32_t blockSize);
   /**
    * @brief  Fills a constant value into a floating-point vector.
    * @param[in]  value input value to be filled
    * @param[out]  *pDst output pointer
    * @param[in]  blockSize number of samples to process
    * @return none.
    */
   void arm_fill_f32(
   float32_t value,
   float32_t * pDst,
   uint32_t blockSize);
   /**
    * @brief  Fills a constant value into a Q7 vector.
    * @param[in]  value input value to be filled
    * @param[out]  *pDst output pointer
    * @param[in]  blockSize number of samples to process
    * @return none.
    */
   void arm_fill_q7(
   q7_t value,
   q7_t * pDst,
   uint32_t blockSize);
   /**
    * @brief  Fills a constant value into a Q15 vector.
    * @param[in]  value input value to be filled
    * @param[out]  *pDst output pointer
    * @param[in]  blockSize number of samples to process
    * @return none.
    */
   void arm_fill_q15(
   q15_t value,
   q15_t * pDst,
   uint32_t blockSize);
   /**
    * @brief  Fills a constant value into a Q31 vector.
    * @param[in]  value input value to be filled
    * @param[out]  *pDst output pointer
    * @param[in]  blockSize number of samples to process
    * @return none.
    */
   void arm_fill_q31(
   q31_t value,
   q31_t * pDst,
   uint32_t blockSize);
 /**
  * @brief Convolution of floating-point sequences.
  * @param[in] *pSrcA points to the first input sequence.
  * @param[in] srcALen length of the first input sequence.
  * @param[in] *pSrcB points to the second input sequence.
  * @param[in] srcBLen length of the second input sequence.
  * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
  * @return none.
  */
   void arm_conv_f32(
   float32_t * pSrcA,
   uint32_t srcALen,
   float32_t * pSrcB,
   uint32_t srcBLen,
   float32_t * pDst);
   /**
    * @brief Convolution of Q15 sequences.
    * @param[in] *pSrcA points to the first input sequence.
    * @param[in] srcALen length of the first input sequence.
    * @param[in] *pSrcB points to the second input sequence.
    * @param[in] srcBLen length of the second input sequence.
    * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
    * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
    * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
    * @return none.
    */
   void arm_conv_opt_q15(
   q15_t * pSrcA,
   uint32_t srcALen,
   q15_t * pSrcB,
   uint32_t srcBLen,
   q15_t * pDst,
   q15_t * pScratch1,
   q15_t * pScratch2);
 /**
  * @brief Convolution of Q15 sequences.
  * @param[in] *pSrcA points to the first input sequence.
  * @param[in] srcALen length of the first input sequence.
  * @param[in] *pSrcB points to the second input sequence.
  * @param[in] srcBLen length of the second input sequence.
  * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
  * @return none.
  */
   void arm_conv_q15(
   q15_t * pSrcA,
   uint32_t srcALen,
   q15_t * pSrcB,
   uint32_t srcBLen,
   q15_t * pDst);
   /**
    * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
    * @param[in] *pSrcA points to the first input sequence.
    * @param[in] srcALen length of the first input sequence.
    * @param[in] *pSrcB points to the second input sequence.
    * @param[in] srcBLen length of the second input sequence.
    * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
    * @return none.
    */
   void arm_conv_fast_q15(
 			  q15_t * pSrcA,
 			 uint32_t srcALen,
 			  q15_t * pSrcB,
 			 uint32_t srcBLen,
 			 q15_t * pDst);
   /**
    * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
    * @param[in] *pSrcA points to the first input sequence.
    * @param[in] srcALen length of the first input sequence.
    * @param[in] *pSrcB points to the second input sequence.
    * @param[in] srcBLen length of the second input sequence.
    * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
    * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
    * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
    * @return none.
    */
   void arm_conv_fast_opt_q15(
   q15_t * pSrcA,
   uint32_t srcALen,
   q15_t * pSrcB,
   uint32_t srcBLen,
   q15_t * pDst,
   q15_t * pScratch1,
   q15_t * pScratch2);
   /**
    * @brief Convolution of Q31 sequences.
    * @param[in] *pSrcA points to the first input sequence.
    * @param[in] srcALen length of the first input sequence.
    * @param[in] *pSrcB points to the second input sequence.
    * @param[in] srcBLen length of the second input sequence.
    * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
    * @return none.
    */
   void arm_conv_q31(
   q31_t * pSrcA,
   uint32_t srcALen,
   q31_t * pSrcB,
   uint32_t srcBLen,
   q31_t * pDst);
   /**
    * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
    * @param[in] *pSrcA points to the first input sequence.
    * @param[in] srcALen length of the first input sequence.
    * @param[in] *pSrcB points to the second input sequence.
    * @param[in] srcBLen length of the second input sequence.
    * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
    * @return none.
    */
   void arm_conv_fast_q31(
   q31_t * pSrcA,
   uint32_t srcALen,
   q31_t * pSrcB,
   uint32_t srcBLen,
   q31_t * pDst);
     /**
    * @brief Convolution of Q7 sequences.
    * @param[in] *pSrcA points to the first input sequence.
    * @param[in] srcALen length of the first input sequence.
    * @param[in] *pSrcB points to the second input sequence.
    * @param[in] srcBLen length of the second input sequence.
    * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
    * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
    * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
    * @return none.
    */
   void arm_conv_opt_q7(
   q7_t * pSrcA,
   uint32_t srcALen,
   q7_t * pSrcB,
   uint32_t srcBLen,
   q7_t * pDst,
   q15_t * pScratch1,
   q15_t * pScratch2);
   /**
    * @brief Convolution of Q7 sequences.
    * @param[in] *pSrcA points to the first input sequence.
    * @param[in] srcALen length of the first input sequence.
    * @param[in] *pSrcB points to the second input sequence.
    * @param[in] srcBLen length of the second input sequence.
    * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
    * @return none.
    */
   void arm_conv_q7(
   q7_t * pSrcA,
   uint32_t srcALen,
   q7_t * pSrcB,
   uint32_t srcBLen,
   q7_t * pDst);
   /**
    * @brief Partial convolution of floating-point sequences.
    * @param[in]       *pSrcA points to the first input sequence.
    * @param[in]       srcALen length of the first input sequence.
    * @param[in]       *pSrcB points to the second input sequence.
    * @param[in]       srcBLen length of the second input sequence.
    * @param[out]      *pDst points to the block of output data
    * @param[in]       firstIndex is the first output sample to start with.
    * @param[in]       numPoints is the number of output points to be computed.
    * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
    */
   arm_status arm_conv_partial_f32(
   float32_t * pSrcA,
   uint32_t srcALen,
   float32_t * pSrcB,
   uint32_t srcBLen,
   float32_t * pDst,
   uint32_t firstIndex,
   uint32_t numPoints);
     /**
    * @brief Partial convolution of Q15 sequences.
    * @param[in]       *pSrcA points to the first input sequence.
    * @param[in]       srcALen length of the first input sequence.
    * @param[in]       *pSrcB points to the second input sequence.
    * @param[in]       srcBLen length of the second input sequence.
    * @param[out]      *pDst points to the block of output data
    * @param[in]       firstIndex is the first output sample to start with.
    * @param[in]       numPoints is the number of output points to be computed.
    * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
    * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
    * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
    */
   arm_status arm_conv_partial_opt_q15(
   q15_t * pSrcA,
   uint32_t srcALen,
   q15_t * pSrcB,
   uint32_t srcBLen,
   q15_t * pDst,
   uint32_t firstIndex,
   uint32_t numPoints,
   q15_t * pScratch1,
   q15_t * pScratch2);
 /**
    * @brief Partial convolution of Q15 sequences.
    * @param[in]       *pSrcA points to the first input sequence.
    * @param[in]       srcALen length of the first input sequence.
    * @param[in]       *pSrcB points to the second input sequence.
    * @param[in]       srcBLen length of the second input sequence.
    * @param[out]      *pDst points to the block of output data
    * @param[in]       firstIndex is the first output sample to start with.
    * @param[in]       numPoints is the number of output points to be computed.
    * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
    */
   arm_status arm_conv_partial_q15(
   q15_t * pSrcA,
   uint32_t srcALen,
   q15_t * pSrcB,
   uint32_t srcBLen,
   q15_t * pDst,
   uint32_t firstIndex,
   uint32_t numPoints);
   /**
    * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
    * @param[in]       *pSrcA points to the first input sequence.
    * @param[in]       srcALen length of the first input sequence.
    * @param[in]       *pSrcB points to the second input sequence.
    * @param[in]       srcBLen length of the second input sequence.
    * @param[out]      *pDst points to the block of output data
    * @param[in]       firstIndex is the first output sample to start with.
    * @param[in]       numPoints is the number of output points to be computed.
    * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
    */
   arm_status arm_conv_partial_fast_q15(
 				        q15_t * pSrcA,
 				       uint32_t srcALen,
 				        q15_t * pSrcB,
 				       uint32_t srcBLen,
 				       q15_t * pDst,
 				       uint32_t firstIndex,
 				       uint32_t numPoints);
   /**
    * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
    * @param[in]       *pSrcA points to the first input sequence.
    * @param[in]       srcALen length of the first input sequence.
    * @param[in]       *pSrcB points to the second input sequence.
    * @param[in]       srcBLen length of the second input sequence.
    * @param[out]      *pDst points to the block of output data
    * @param[in]       firstIndex is the first output sample to start with.
    * @param[in]       numPoints is the number of output points to be computed.
    * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
    * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
    * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
    */
   arm_status arm_conv_partial_fast_opt_q15(
   q15_t * pSrcA,
   uint32_t srcALen,
   q15_t * pSrcB,
   uint32_t srcBLen,
   q15_t * pDst,
   uint32_t firstIndex,
   uint32_t numPoints,
   q15_t * pScratch1,
   q15_t * pScratch2);
   /**
    * @brief Partial convolution of Q31 sequences.
    * @param[in]       *pSrcA points to the first input sequence.
    * @param[in]       srcALen length of the first input sequence.
    * @param[in]       *pSrcB points to the second input sequence.
    * @param[in]       srcBLen length of the second input sequence.
    * @param[out]      *pDst points to the block of output data
    * @param[in]       firstIndex is the first output sample to start with.
    * @param[in]       numPoints is the number of output points to be computed.
    * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
    */
   arm_status arm_conv_partial_q31(
   q31_t * pSrcA,
   uint32_t srcALen,
   q31_t * pSrcB,
   uint32_t srcBLen,
   q31_t * pDst,
   uint32_t firstIndex,
   uint32_t numPoints);
   /**
    * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
    * @param[in]       *pSrcA points to the first input sequence.
    * @param[in]       srcALen length of the first input sequence.
    * @param[in]       *pSrcB points to the second input sequence.
    * @param[in]       srcBLen length of the second input sequence.
    * @param[out]      *pDst points to the block of output data
    * @param[in]       firstIndex is the first output sample to start with.
    * @param[in]       numPoints is the number of output points to be computed.
    * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
    */
   arm_status arm_conv_partial_fast_q31(
   q31_t * pSrcA,
   uint32_t srcALen,
   q31_t * pSrcB,
   uint32_t srcBLen,
   q31_t * pDst,
   uint32_t firstIndex,
   uint32_t numPoints);
   /**
    * @brief Partial convolution of Q7 sequences
    * @param[in]       *pSrcA points to the first input sequence.
    * @param[in]       srcALen length of the first input sequence.
    * @param[in]       *pSrcB points to the second input sequence.
    * @param[in]       srcBLen length of the second input sequence.
    * @param[out]      *pDst points to the block of output data
    * @param[in]       firstIndex is the first output sample to start with.
    * @param[in]       numPoints is the number of output points to be computed.
    * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
    * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
    * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
    */
   arm_status arm_conv_partial_opt_q7(
   q7_t * pSrcA,
   uint32_t srcALen,
   q7_t * pSrcB,
   uint32_t srcBLen,
   q7_t * pDst,
   uint32_t firstIndex,
   uint32_t numPoints,
   q15_t * pScratch1,
   q15_t * pScratch2);
 /**
    * @brief Partial convolution of Q7 sequences.
    * @param[in]       *pSrcA points to the first input sequence.
    * @param[in]       srcALen length of the first input sequence.
    * @param[in]       *pSrcB points to the second input sequence.
    * @param[in]       srcBLen length of the second input sequence.
    * @param[out]      *pDst points to the block of output data
    * @param[in]       firstIndex is the first output sample to start with.
    * @param[in]       numPoints is the number of output points to be computed.
    * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
    */
   arm_status arm_conv_partial_q7(
   q7_t * pSrcA,
   uint32_t srcALen,
   q7_t * pSrcB,
   uint32_t srcBLen,
   q7_t * pDst,
   uint32_t firstIndex,
   uint32_t numPoints);
   /**
    * @brief Instance structure for the Q15 FIR decimator.
    */
   typedef struct
+  {
     uint8_t M;                      /**< decimation factor. */
     uint16_t numTaps;               /**< number of coefficients in the filter. */
     q15_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
     q15_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
   } arm_fir_decimate_instance_q15;
   /**
    * @brief Instance structure for the Q31 FIR decimator.
    */
   typedef struct
+  {
     uint8_t M;                  /**< decimation factor. */
     uint16_t numTaps;           /**< number of coefficients in the filter. */
     q31_t *pCoeffs;              /**< points to the coefficient array. The array is of length numTaps.*/
     q31_t *pState;               /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
   } arm_fir_decimate_instance_q31;
   /**
    * @brief Instance structure for the floating-point FIR decimator.
    */
   typedef struct
+  {
     uint8_t M;                          /**< decimation factor. */
     uint16_t numTaps;                   /**< number of coefficients in the filter. */
     float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
     float32_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
   } arm_fir_decimate_instance_f32;
   /**
    * @brief Processing function for the floating-point FIR decimator.
    * @param[in] *S points to an instance of the floating-point FIR decimator structure.
    * @param[in] *pSrc points to the block of input data.
    * @param[out] *pDst points to the block of output data
    * @param[in] blockSize number of input samples to process per call.
    * @return none
    */
   void arm_fir_decimate_f32(
   const arm_fir_decimate_instance_f32 * S,
   float32_t * pSrc,
   float32_t * pDst,
   uint32_t blockSize);
   /**
    * @brief  Initialization function for the floating-point FIR decimator.
    * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
    * @param[in] numTaps  number of coefficients in the filter.
    * @param[in] M  decimation factor.
    * @param[in] *pCoeffs points to the filter coefficients.
    * @param[in] *pState points to the state buffer.
    * @param[in] blockSize number of input samples to process per call.
    * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
    * <code>blockSize</code> is not a multiple of <code>M</code>.
    */
   arm_status arm_fir_decimate_init_f32(
   arm_fir_decimate_instance_f32 * S,
   uint16_t numTaps,
   uint8_t M,
   float32_t * pCoeffs,
   float32_t * pState,
   uint32_t blockSize);
   /**
    * @brief Processing function for the Q15 FIR decimator.
    * @param[in] *S points to an instance of the Q15 FIR decimator structure.
    * @param[in] *pSrc points to the block of input data.
    * @param[out] *pDst points to the block of output data
    * @param[in] blockSize number of input samples to process per call.
    * @return none
    */
   void arm_fir_decimate_q15(
   const arm_fir_decimate_instance_q15 * S,
   q15_t * pSrc,
   q15_t * pDst,
   uint32_t blockSize);
   /**
    * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
    * @param[in] *S points to an instance of the Q15 FIR decimator structure.
    * @param[in] *pSrc points to the block of input data.
    * @param[out] *pDst points to the block of output data
    * @param[in] blockSize number of input samples to process per call.
    * @return none
    */
   void arm_fir_decimate_fast_q15(
   const arm_fir_decimate_instance_q15 * S,
   q15_t * pSrc,
   q15_t * pDst,
   uint32_t blockSize);
   /**
    * @brief  Initialization function for the Q15 FIR decimator.
    * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
    * @param[in] numTaps  number of coefficients in the filter.
    * @param[in] M  decimation factor.
    * @param[in] *pCoeffs points to the filter coefficients.
    * @param[in] *pState points to the state buffer.
    * @param[in] blockSize number of input samples to process per call.
    * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
    * <code>blockSize</code> is not a multiple of <code>M</code>.
    */
   arm_status arm_fir_decimate_init_q15(
   arm_fir_decimate_instance_q15 * S,
   uint16_t numTaps,
   uint8_t M,
   q15_t * pCoeffs,
   q15_t * pState,
   uint32_t blockSize);
   /**
    * @brief Processing function for the Q31 FIR decimator.
    * @param[in] *S points to an instance of the Q31 FIR decimator structure.
    * @param[in] *pSrc points to the block of input data.
    * @param[out] *pDst points to the block of output data
    * @param[in] blockSize number of input samples to process per call.
    * @return none
    */
   void arm_fir_decimate_q31(
   const arm_fir_decimate_instance_q31 * S,
   q31_t * pSrc,
   q31_t * pDst,
   uint32_t blockSize);
   /**
    * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
    * @param[in] *S points to an instance of the Q31 FIR decimator structure.
    * @param[in] *pSrc points to the block of input data.
    * @param[out] *pDst points to the block of output data
    * @param[in] blockSize number of input samples to process per call.
    * @return none
    */
   void arm_fir_decimate_fast_q31(
   arm_fir_decimate_instance_q31 * S,
   q31_t * pSrc,
   q31_t * pDst,
   uint32_t blockSize);
   /**
    * @brief  Initialization function for the Q31 FIR decimator.
    * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
    * @param[in] numTaps  number of coefficients in the filter.
    * @param[in] M  decimation factor.
    * @param[in] *pCoeffs points to the filter coefficients.
    * @param[in] *pState points to the state buffer.
    * @param[in] blockSize number of input samples to process per call.
    * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
    * <code>blockSize</code> is not a multiple of <code>M</code>.
    */
   arm_status arm_fir_decimate_init_q31(
   arm_fir_decimate_instance_q31 * S,
   uint16_t numTaps,
   uint8_t M,
   q31_t * pCoeffs,
   q31_t * pState,
   uint32_t blockSize);
   /**
    * @brief Instance structure for the Q15 FIR interpolator.
    */
   typedef struct
+  {
     uint8_t L;                      /**< upsample factor. */
     uint16_t phaseLength;           /**< length of each polyphase filter component. */
     q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
     q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
   } arm_fir_interpolate_instance_q15;
   /**
    * @brief Instance structure for the Q31 FIR interpolator.
    */
   typedef struct
+  {
     uint8_t L;                      /**< upsample factor. */
     uint16_t phaseLength;           /**< length of each polyphase filter component. */
     q31_t *pCoeffs;                  /**< points to the coefficient array. The array is of length L*phaseLength. */
     q31_t *pState;                   /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
   } arm_fir_interpolate_instance_q31;
   /**
    * @brief Instance structure for the floating-point FIR interpolator.
    */
   typedef struct
+  {
     uint8_t L;                     /**< upsample factor. */
     uint16_t phaseLength;          /**< length of each polyphase filter component. */
     float32_t *pCoeffs;             /**< points to the coefficient array. The array is of length L*phaseLength. */
     float32_t *pState;              /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
   } arm_fir_interpolate_instance_f32;
   /**
    * @brief Processing function for the Q15 FIR interpolator.
    * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
    * @param[in] *pSrc     points to the block of input data.
    * @param[out] *pDst    points to the block of output data.
    * @param[in] blockSize number of input samples to process per call.
    * @return none.
    */
   void arm_fir_interpolate_q15(
   const arm_fir_interpolate_instance_q15 * S,
   q15_t * pSrc,
   q15_t * pDst,
   uint32_t blockSize);
   /**
    * @brief  Initialization function for the Q15 FIR interpolator.
    * @param[in,out] *S        points to an instance of the Q15 FIR interpolator structure.
    * @param[in]     L         upsample factor.
    * @param[in]     numTaps   number of filter coefficients in the filter.
    * @param[in]     *pCoeffs  points to the filter coefficient buffer.
    * @param[in]     *pState   points to the state buffer.
    * @param[in]     blockSize number of input samples to process per call.
    * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
    * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
    */
   arm_status arm_fir_interpolate_init_q15(
   arm_fir_interpolate_instance_q15 * S,
   uint8_t L,
   uint16_t numTaps,
   q15_t * pCoeffs,
   q15_t * pState,
   uint32_t blockSize);
   /**
    * @brief Processing function for the Q31 FIR interpolator.
    * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
    * @param[in] *pSrc     points to the block of input data.
    * @param[out] *pDst    points to the block of output data.
    * @param[in] blockSize number of input samples to process per call.
    * @return none.
    */
   void arm_fir_interpolate_q31(
   const arm_fir_interpolate_instance_q31 * S,
   q31_t * pSrc,
   q31_t * pDst,
   uint32_t blockSize);
   /**
    * @brief  Initialization function for the Q31 FIR interpolator.
    * @param[in,out] *S        points to an instance of the Q31 FIR interpolator structure.
    * @param[in]     L         upsample factor.
    * @param[in]     numTaps   number of filter coefficients in the filter.
    * @param[in]     *pCoeffs  points to the filter coefficient buffer.
    * @param[in]     *pState   points to the state buffer.
    * @param[in]     blockSize number of input samples to process per call.
    * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
    * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
    */
   arm_status arm_fir_interpolate_init_q31(
   arm_fir_interpolate_instance_q31 * S,
   uint8_t L,
   uint16_t numTaps,
   q31_t * pCoeffs,
   q31_t * pState,
   uint32_t blockSize);
   /**
    * @brief Processing function for the floating-point FIR interpolator.
    * @param[in] *S        points to an instance of the floating-point FIR interpolator structure.
    * @param[in] *pSrc     points to the block of input data.
    * @param[out] *pDst    points to the block of output data.
    * @param[in] blockSize number of input samples to process per call.
    * @return none.
    */
   void arm_fir_interpolate_f32(
   const arm_fir_interpolate_instance_f32 * S,
   float32_t * pSrc,
   float32_t * pDst,
   uint32_t blockSize);
   /**
    * @brief  Initialization function for the floating-point FIR interpolator.
    * @param[in,out] *S        points to an instance of the floating-point FIR interpolator structure.
    * @param[in]     L         upsample factor.
    * @param[in]     numTaps   number of filter coefficients in the filter.
    * @param[in]     *pCoeffs  points to the filter coefficient buffer.
    * @param[in]     *pState   points to the state buffer.
    * @param[in]     blockSize number of input samples to process per call.
    * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
    * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
    */
   arm_status arm_fir_interpolate_init_f32(
   arm_fir_interpolate_instance_f32 * S,
   uint8_t L,
   uint16_t numTaps,
   float32_t * pCoeffs,
   float32_t * pState,
   uint32_t blockSize);
   /**
    * @brief Instance structure for the high precision Q31 Biquad cascade filter.
    */
   typedef struct
+  {
     uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
     q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
     q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
     uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
   } arm_biquad_cas_df1_32x64_ins_q31;
   /**
    * @param[in]  *S        points to an instance of the high precision Q31 Biquad cascade filter structure.
    * @param[in]  *pSrc     points to the block of input data.
    * @param[out] *pDst     points to the block of output data
    * @param[in]  blockSize number of samples to process.
    * @return none.
    */
   void arm_biquad_cas_df1_32x64_q31(
   const arm_biquad_cas_df1_32x64_ins_q31 * S,
   q31_t * pSrc,
   q31_t * pDst,
   uint32_t blockSize);
   /**
    * @param[in,out] *S           points to an instance of the high precision Q31 Biquad cascade filter structure.
    * @param[in]     numStages    number of 2nd order stages in the filter.
    * @param[in]     *pCoeffs     points to the filter coefficients.
    * @param[in]     *pState      points to the state buffer.
    * @param[in]     postShift    shift to be applied to the output. Varies according to the coefficients format
    * @return        none
    */
   void arm_biquad_cas_df1_32x64_init_q31(
   arm_biquad_cas_df1_32x64_ins_q31 * S,
   uint8_t numStages,
   q31_t * pCoeffs,
   q63_t * pState,
   uint8_t postShift);
   /**
    * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
    */
   typedef struct
+  {
     uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
     float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
     float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
   } arm_biquad_cascade_df2T_instance_f32;
   /**
    * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
    * @param[in]  *S        points to an instance of the filter data structure.
    * @param[in]  *pSrc     points to the block of input data.
    * @param[out] *pDst     points to the block of output data
    * @param[in]  blockSize number of samples to process.
    * @return none.
    */
   void arm_biquad_cascade_df2T_f32(
   const arm_biquad_cascade_df2T_instance_f32 * S,
   float32_t * pSrc,
   float32_t * pDst,
   uint32_t blockSize);
   /**
    * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
    * @param[in,out] *S           points to an instance of the filter data structure.
    * @param[in]     numStages    number of 2nd order stages in the filter.
    * @param[in]     *pCoeffs     points to the filter coefficients.
    * @param[in]     *pState      points to the state buffer.
    * @return        none
    */
   void arm_biquad_cascade_df2T_init_f32(
   arm_biquad_cascade_df2T_instance_f32 * S,
   uint8_t numStages,
   float32_t * pCoeffs,
   float32_t * pState);
   /**
    * @brief Instance structure for the Q15 FIR lattice filter.
    */
   typedef struct
+  {
     uint16_t numStages;                          /**< number of filter stages. */
     q15_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
     q15_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
   } arm_fir_lattice_instance_q15;
   /**
    * @brief Instance structure for the Q31 FIR lattice filter.
    */
   typedef struct
+  {
     uint16_t numStages;                          /**< number of filter stages. */
     q31_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
     q31_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
   } arm_fir_lattice_instance_q31;
   /**
    * @brief Instance structure for the floating-point FIR lattice filter.
    */
   typedef struct
+  {
     uint16_t numStages;                  /**< number of filter stages. */
     float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */
     float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
   } arm_fir_lattice_instance_f32;
   /**
    * @brief Initialization function for the Q15 FIR lattice filter.
    * @param[in] *S points to an instance of the Q15 FIR lattice structure.
    * @param[in] numStages  number of filter stages.
    * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
    * @param[in] *pState points to the state buffer.  The array is of length numStages.
    * @return none.
    */
   void arm_fir_lattice_init_q15(
   arm_fir_lattice_instance_q15 * S,
   uint16_t numStages,
   q15_t * pCoeffs,
   q15_t * pState);
   /**
    * @brief Processing function for the Q15 FIR lattice filter.
    * @param[in] *S points to an instance of the Q15 FIR lattice structure.
    * @param[in] *pSrc points to the block of input data.
    * @param[out] *pDst points to the block of output data.
    * @param[in] blockSize number of samples to process.
    * @return none.
    */
   void arm_fir_lattice_q15(
   const arm_fir_lattice_instance_q15 * S,
   q15_t * pSrc,
   q15_t * pDst,
   uint32_t blockSize);
   /**
    * @brief Initialization function for the Q31 FIR lattice filter.
    * @param[in] *S points to an instance of the Q31 FIR lattice structure.
    * @param[in] numStages  number of filter stages.
    * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
    * @param[in] *pState points to the state buffer.   The array is of length numStages.
    * @return none.
    */
   void arm_fir_lattice_init_q31(
   arm_fir_lattice_instance_q31 * S,
   uint16_t numStages,
   q31_t * pCoeffs,
   q31_t * pState);
   /**
    * @brief Processing function for the Q31 FIR lattice filter.
    * @param[in]  *S        points to an instance of the Q31 FIR lattice structure.
    * @param[in]  *pSrc     points to the block of input data.
    * @param[out] *pDst     points to the block of output data
    * @param[in]  blockSize number of samples to process.
    * @return none.
    */
   void arm_fir_lattice_q31(
   const arm_fir_lattice_instance_q31 * S,
   q31_t * pSrc,
   q31_t * pDst,
   uint32_t blockSize);
 /**
  * @brief Initialization function for the floating-point FIR lattice filter.
  * @param[in] *S points to an instance of the floating-point FIR lattice structure.
  * @param[in] numStages  number of filter stages.
  * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
  * @param[in] *pState points to the state buffer.  The array is of length numStages.
  * @return none.
  */
   void arm_fir_lattice_init_f32(
   arm_fir_lattice_instance_f32 * S,
   uint16_t numStages,
   float32_t * pCoeffs,
   float32_t * pState);
   /**
    * @brief Processing function for the floating-point FIR lattice filter.
    * @param[in]  *S        points to an instance of the floating-point FIR lattice structure.
    * @param[in]  *pSrc     points to the block of input data.
    * @param[out] *pDst     points to the block of output data
    * @param[in]  blockSize number of samples to process.
    * @return none.
    */
   void arm_fir_lattice_f32(
   const arm_fir_lattice_instance_f32 * S,
   float32_t * pSrc,
   float32_t * pDst,
   uint32_t blockSize);
   /**
    * @brief Instance structure for the Q15 IIR lattice filter.
    */
   typedef struct
+  {
     uint16_t numStages;                         /**< number of stages in the filter. */
     q15_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
     q15_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
     q15_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
   } arm_iir_lattice_instance_q15;
   /**
    * @brief Instance structure for the Q31 IIR lattice filter.
    */
   typedef struct
+  {
     uint16_t numStages;                         /**< number of stages in the filter. */
     q31_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
     q31_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
     q31_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
   } arm_iir_lattice_instance_q31;
   /**
    * @brief Instance structure for the floating-point IIR lattice filter.
    */
   typedef struct
+  {
     uint16_t numStages;                         /**< number of stages in the filter. */
     float32_t *pState;                          /**< points to the state variable array. The array is of length numStages+blockSize. */
     float32_t *pkCoeffs;                        /**< points to the reflection coefficient array. The array is of length numStages. */
     float32_t *pvCoeffs;                        /**< points to the ladder coefficient array. The array is of length numStages+1. */
   } arm_iir_lattice_instance_f32;
   /**
    * @brief Processing function for the floating-point IIR lattice filter.
    * @param[in] *S points to an instance of the floating-point IIR lattice structure.
    * @param[in] *pSrc points to the block of input data.
    * @param[out] *pDst points to the block of output data.
    * @param[in] blockSize number of samples to process.
    * @return none.
    */
   void arm_iir_lattice_f32(
   const arm_iir_lattice_instance_f32 * S,
   float32_t * pSrc,
   float32_t * pDst,
   uint32_t blockSize);
   /**
    * @brief Initialization function for the floating-point IIR lattice filter.
    * @param[in] *S points to an instance of the floating-point IIR lattice structure.
    * @param[in] numStages number of stages in the filter.
    * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
    * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
    * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize-1.
    * @param[in] blockSize number of samples to process.
    * @return none.
    */
   void arm_iir_lattice_init_f32(
   arm_iir_lattice_instance_f32 * S,
   uint16_t numStages,
   float32_t * pkCoeffs,
   float32_t * pvCoeffs,
   float32_t * pState,
   uint32_t blockSize);
   /**
    * @brief Processing function for the Q31 IIR lattice filter.
    * @param[in] *S points to an instance of the Q31 IIR lattice structure.
    * @param[in] *pSrc points to the block of input data.
    * @param[out] *pDst points to the block of output data.
    * @param[in] blockSize number of samples to process.
    * @return none.
    */
   void arm_iir_lattice_q31(
   const arm_iir_lattice_instance_q31 * S,
   q31_t * pSrc,
   q31_t * pDst,
   uint32_t blockSize);
   /**
    * @brief Initialization function for the Q31 IIR lattice filter.
    * @param[in] *S points to an instance of the Q31 IIR lattice structure.
    * @param[in] numStages number of stages in the filter.
    * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
    * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
    * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.
    * @param[in] blockSize number of samples to process.
    * @return none.
    */
   void arm_iir_lattice_init_q31(
   arm_iir_lattice_instance_q31 * S,
   uint16_t numStages,
   q31_t * pkCoeffs,
   q31_t * pvCoeffs,
   q31_t * pState,
   uint32_t blockSize);
   /**
    * @brief Processing function for the Q15 IIR lattice filter.
    * @param[in] *S points to an instance of the Q15 IIR lattice structure.
    * @param[in] *pSrc points to the block of input data.
    * @param[out] *pDst points to the block of output data.
    * @param[in] blockSize number of samples to process.
    * @return none.
    */
   void arm_iir_lattice_q15(
   const arm_iir_lattice_instance_q15 * S,
   q15_t * pSrc,
   q15_t * pDst,
   uint32_t blockSize);
 /**
  * @brief Initialization function for the Q15 IIR lattice filter.
  * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
  * @param[in] numStages  number of stages in the filter.
  * @param[in] *pkCoeffs points to reflection coefficient buffer.  The array is of length numStages.
  * @param[in] *pvCoeffs points to ladder coefficient buffer.  The array is of length numStages+1.
  * @param[in] *pState points to state buffer.  The array is of length numStages+blockSize.
  * @param[in] blockSize number of samples to process per call.
  * @return none.
  */
   void arm_iir_lattice_init_q15(
   arm_iir_lattice_instance_q15 * S,
   uint16_t numStages,
   q15_t * pkCoeffs,
   q15_t * pvCoeffs,
   q15_t * pState,
   uint32_t blockSize);
   /**
    * @brief Instance structure for the floating-point LMS filter.
    */
   typedef struct
+  {
     uint16_t numTaps;    /**< number of coefficients in the filter. */
     float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
     float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
     float32_t mu;        /**< step size that controls filter coefficient updates. */
   } arm_lms_instance_f32;
   /**
    * @brief Processing function for floating-point LMS filter.
    * @param[in]  *S points to an instance of the floating-point LMS filter structure.
    * @param[in]  *pSrc points to the block of input data.
    * @param[in]  *pRef points to the block of reference data.
    * @param[out] *pOut points to the block of output data.
    * @param[out] *pErr points to the block of error data.
    * @param[in]  blockSize number of samples to process.
    * @return     none.
    */
   void arm_lms_f32(
   const arm_lms_instance_f32 * S,
   float32_t * pSrc,
   float32_t * pRef,
   float32_t * pOut,
   float32_t * pErr,
   uint32_t blockSize);
   /**
    * @brief Initialization function for floating-point LMS filter.
    * @param[in] *S points to an instance of the floating-point LMS filter structure.
    * @param[in] numTaps  number of filter coefficients.
    * @param[in] *pCoeffs points to the coefficient buffer.
    * @param[in] *pState points to state buffer.
    * @param[in] mu step size that controls filter coefficient updates.
    * @param[in] blockSize number of samples to process.
    * @return none.
    */
   void arm_lms_init_f32(
   arm_lms_instance_f32 * S,
   uint16_t numTaps,
   float32_t * pCoeffs,
   float32_t * pState,
   float32_t mu,
   uint32_t blockSize);
   /**
    * @brief Instance structure for the Q15 LMS filter.
    */
   typedef struct
+  {
     uint16_t numTaps;    /**< number of coefficients in the filter. */
     q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
     q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
     q15_t mu;            /**< step size that controls filter coefficient updates. */
     uint32_t postShift;  /**< bit shift applied to coefficients. */
   } arm_lms_instance_q15;
   /**
    * @brief Initialization function for the Q15 LMS filter.
    * @param[in] *S points to an instance of the Q15 LMS filter structure.
    * @param[in] numTaps  number of filter coefficients.
    * @param[in] *pCoeffs points to the coefficient buffer.
    * @param[in] *pState points to the state buffer.
    * @param[in] mu step size that controls filter coefficient updates.
    * @param[in] blockSize number of samples to process.
    * @param[in] postShift bit shift applied to coefficients.
    * @return    none.
    */
   void arm_lms_init_q15(
   arm_lms_instance_q15 * S,
   uint16_t numTaps,
   q15_t * pCoeffs,
   q15_t * pState,
   q15_t mu,
   uint32_t blockSize,
   uint32_t postShift);
   /**
    * @brief Processing function for Q15 LMS filter.
    * @param[in] *S points to an instance of the Q15 LMS filter structure.
    * @param[in] *pSrc points to the block of input data.
    * @param[in] *pRef points to the block of reference data.
    * @param[out] *pOut points to the block of output data.
    * @param[out] *pErr points to the block of error data.
    * @param[in] blockSize number of samples to process.
    * @return none.
    */
   void arm_lms_q15(
   const arm_lms_instance_q15 * S,
   q15_t * pSrc,
   q15_t * pRef,
   q15_t * pOut,
   q15_t * pErr,
   uint32_t blockSize);
   /**
    * @brief Instance structure for the Q31 LMS filter.
    */
   typedef struct
+  {
     uint16_t numTaps;    /**< number of coefficients in the filter. */
     q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
     q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
     q31_t mu;            /**< step size that controls filter coefficient updates. */
     uint32_t postShift;  /**< bit shift applied to coefficients. */
   } arm_lms_instance_q31;
   /**
    * @brief Processing function for Q31 LMS filter.
    * @param[in]  *S points to an instance of the Q15 LMS filter structure.
    * @param[in]  *pSrc points to the block of input data.
    * @param[in]  *pRef points to the block of reference data.
    * @param[out] *pOut points to the block of output data.
    * @param[out] *pErr points to the block of error data.
    * @param[in]  blockSize number of samples to process.
    * @return     none.
    */
   void arm_lms_q31(
   const arm_lms_instance_q31 * S,
   q31_t * pSrc,
   q31_t * pRef,
   q31_t * pOut,
   q31_t * pErr,
   uint32_t blockSize);
   /**
    * @brief Initialization function for Q31 LMS filter.
    * @param[in] *S points to an instance of the Q31 LMS filter structure.
    * @param[in] numTaps  number of filter coefficients.
    * @param[in] *pCoeffs points to coefficient buffer.
    * @param[in] *pState points to state buffer.
    * @param[in] mu step size that controls filter coefficient updates.
    * @param[in] blockSize number of samples to process.
    * @param[in] postShift bit shift applied to coefficients.
    * @return none.
    */
   void arm_lms_init_q31(
   arm_lms_instance_q31 * S,
   uint16_t numTaps,
   q31_t * pCoeffs,
   q31_t * pState,
   q31_t mu,
   uint32_t blockSize,
   uint32_t postShift);
   /**
    * @brief Instance structure for the floating-point normalized LMS filter.
    */
   typedef struct
+  {
     uint16_t numTaps;     /**< number of coefficients in the filter. */
     float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
     float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
     float32_t mu;        /**< step size that control filter coefficient updates. */
     float32_t energy;    /**< saves previous frame energy. */
     float32_t x0;        /**< saves previous input sample. */
   } arm_lms_norm_instance_f32;
   /**
    * @brief Processing function for floating-point normalized LMS filter.
    * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
    * @param[in] *pSrc points to the block of input data.
    * @param[in] *pRef points to the block of reference data.
    * @param[out] *pOut points to the block of output data.
    * @param[out] *pErr points to the block of error data.
    * @param[in] blockSize number of samples to process.
    * @return none.
    */
   void arm_lms_norm_f32(
   arm_lms_norm_instance_f32 * S,
   float32_t * pSrc,
   float32_t * pRef,
   float32_t * pOut,
   float32_t * pErr,
   uint32_t blockSize);
   /**
    * @brief Initialization function for floating-point normalized LMS filter.
    * @param[in] *S points to an instance of the floating-point LMS filter structure.
    * @param[in] numTaps  number of filter coefficients.
    * @param[in] *pCoeffs points to coefficient buffer.
    * @param[in] *pState points to state buffer.
    * @param[in] mu step size that controls filter coefficient updates.
    * @param[in] blockSize number of samples to process.
    * @return none.
    */
   void arm_lms_norm_init_f32(
   arm_lms_norm_instance_f32 * S,
   uint16_t numTaps,
   float32_t * pCoeffs,
   float32_t * pState,
   float32_t mu,
   uint32_t blockSize);
   /**
    * @brief Instance structure for the Q31 normalized LMS filter.
    */
   typedef struct
+  {
     uint16_t numTaps;     /**< number of coefficients in the filter. */
     q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
     q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
     q31_t mu;             /**< step size that controls filter coefficient updates. */
     uint8_t postShift;    /**< bit shift applied to coefficients. */
     q31_t *recipTable;    /**< points to the reciprocal initial value table. */
     q31_t energy;         /**< saves previous frame energy. */
     q31_t x0;             /**< saves previous input sample. */
   } arm_lms_norm_instance_q31;
   /**
    * @brief Processing function for Q31 normalized LMS filter.
    * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
    * @param[in] *pSrc points to the block of input data.
    * @param[in] *pRef points to the block of reference data.
    * @param[out] *pOut points to the block of output data.
    * @param[out] *pErr points to the block of error data.
    * @param[in] blockSize number of samples to process.
    * @return none.
    */
   void arm_lms_norm_q31(
   arm_lms_norm_instance_q31 * S,
   q31_t * pSrc,
   q31_t * pRef,
   q31_t * pOut,
   q31_t * pErr,
   uint32_t blockSize);
   /**
    * @brief Initialization function for Q31 normalized LMS filter.
    * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
    * @param[in] numTaps  number of filter coefficients.
    * @param[in] *pCoeffs points to coefficient buffer.
    * @param[in] *pState points to state buffer.
    * @param[in] mu step size that controls filter coefficient updates.
    * @param[in] blockSize number of samples to process.
    * @param[in] postShift bit shift applied to coefficients.
    * @return none.
    */
   void arm_lms_norm_init_q31(
   arm_lms_norm_instance_q31 * S,
   uint16_t numTaps,
   q31_t * pCoeffs,
   q31_t * pState,
   q31_t mu,
   uint32_t blockSize,
   uint8_t postShift);
   /**
    * @brief Instance structure for the Q15 normalized LMS filter.
    */
   typedef struct
+  {
     uint16_t numTaps;    /**< Number of coefficients in the filter. */
     q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
     q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
     q15_t mu;            /**< step size that controls filter coefficient updates. */
     uint8_t postShift;   /**< bit shift applied to coefficients. */
     q15_t *recipTable;   /**< Points to the reciprocal initial value table. */
     q15_t energy;        /**< saves previous frame energy. */
     q15_t x0;            /**< saves previous input sample. */
   } arm_lms_norm_instance_q15;
   /**
    * @brief Processing function for Q15 normalized LMS filter.
    * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
    * @param[in] *pSrc points to the block of input data.
    * @param[in] *pRef points to the block of reference data.
    * @param[out] *pOut points to the block of output data.
    * @param[out] *pErr points to the block of error data.
    * @param[in] blockSize number of samples to process.
    * @return none.
    */
   void arm_lms_norm_q15(
   arm_lms_norm_instance_q15 * S,
   q15_t * pSrc,
   q15_t * pRef,
   q15_t * pOut,
   q15_t * pErr,
   uint32_t blockSize);
   /**
    * @brief Initialization function for Q15 normalized LMS filter.
    * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
    * @param[in] numTaps  number of filter coefficients.
    * @param[in] *pCoeffs points to coefficient buffer.
    * @param[in] *pState points to state buffer.
    * @param[in] mu step size that controls filter coefficient updates.
    * @param[in] blockSize number of samples to process.
    * @param[in] postShift bit shift applied to coefficients.
    * @return none.
    */
   void arm_lms_norm_init_q15(
   arm_lms_norm_instance_q15 * S,
   uint16_t numTaps,
   q15_t * pCoeffs,
   q15_t * pState,
   q15_t mu,
   uint32_t blockSize,
   uint8_t postShift);
   /**
    * @brief Correlation of floating-point sequences.
    * @param[in] *pSrcA points to the first input sequence.
    * @param[in] srcALen length of the first input sequence.
    * @param[in] *pSrcB points to the second input sequence.
    * @param[in] srcBLen length of the second input sequence.
    * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
    * @return none.
    */
   void arm_correlate_f32(
   float32_t * pSrcA,
   uint32_t srcALen,
   float32_t * pSrcB,
   uint32_t srcBLen,
   float32_t * pDst);
    /**
    * @brief Correlation of Q15 sequences
    * @param[in] *pSrcA points to the first input sequence.
    * @param[in] srcALen length of the first input sequence.
    * @param[in] *pSrcB points to the second input sequence.
    * @param[in] srcBLen length of the second input sequence.
    * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
    * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
    * @return none.
    */
   void arm_correlate_opt_q15(
   q15_t * pSrcA,
   uint32_t srcALen,
   q15_t * pSrcB,
   uint32_t srcBLen,
   q15_t * pDst,
   q15_t * pScratch);
   /**
    * @brief Correlation of Q15 sequences.
    * @param[in] *pSrcA points to the first input sequence.
    * @param[in] srcALen length of the first input sequence.
    * @param[in] *pSrcB points to the second input sequence.
    * @param[in] srcBLen length of the second input sequence.
    * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
    * @return none.
    */
   void arm_correlate_q15(
   q15_t * pSrcA,
   uint32_t srcALen,
   q15_t * pSrcB,
   uint32_t srcBLen,
   q15_t * pDst);
   /**
    * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
    * @param[in] *pSrcA points to the first input sequence.
    * @param[in] srcALen length of the first input sequence.
    * @param[in] *pSrcB points to the second input sequence.
    * @param[in] srcBLen length of the second input sequence.
    * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
    * @return none.
    */
   void arm_correlate_fast_q15(
 			       q15_t * pSrcA,
 			      uint32_t srcALen,
 			       q15_t * pSrcB,
 			      uint32_t srcBLen,
 			      q15_t * pDst);
   /**
    * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
    * @param[in] *pSrcA points to the first input sequence.
    * @param[in] srcALen length of the first input sequence.
    * @param[in] *pSrcB points to the second input sequence.
    * @param[in] srcBLen length of the second input sequence.
    * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
    * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
    * @return none.
    */
   void arm_correlate_fast_opt_q15(
   q15_t * pSrcA,
   uint32_t srcALen,
   q15_t * pSrcB,
   uint32_t srcBLen,
   q15_t * pDst,
   q15_t * pScratch);
   /**
    * @brief Correlation of Q31 sequences.
    * @param[in] *pSrcA points to the first input sequence.
    * @param[in] srcALen length of the first input sequence.
    * @param[in] *pSrcB points to the second input sequence.
    * @param[in] srcBLen length of the second input sequence.
    * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
    * @return none.
    */
   void arm_correlate_q31(
   q31_t * pSrcA,
   uint32_t srcALen,
   q31_t * pSrcB,
   uint32_t srcBLen,
   q31_t * pDst);
   /**
    * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
    * @param[in] *pSrcA points to the first input sequence.
    * @param[in] srcALen length of the first input sequence.
    * @param[in] *pSrcB points to the second input sequence.
    * @param[in] srcBLen length of the second input sequence.
    * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
    * @return none.
    */
   void arm_correlate_fast_q31(
   q31_t * pSrcA,
   uint32_t srcALen,
   q31_t * pSrcB,
   uint32_t srcBLen,
   q31_t * pDst);
  /**
    * @brief Correlation of Q7 sequences.
    * @param[in] *pSrcA points to the first input sequence.
    * @param[in] srcALen length of the first input sequence.
    * @param[in] *pSrcB points to the second input sequence.
    * @param[in] srcBLen length of the second input sequence.
    * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
    * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
    * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
    * @return none.
    */
   void arm_correlate_opt_q7(
   q7_t * pSrcA,
   uint32_t srcALen,
   q7_t * pSrcB,
   uint32_t srcBLen,
   q7_t * pDst,
   q15_t * pScratch1,
   q15_t * pScratch2);
   /**
    * @brief Correlation of Q7 sequences.
    * @param[in] *pSrcA points to the first input sequence.
    * @param[in] srcALen length of the first input sequence.
    * @param[in] *pSrcB points to the second input sequence.
    * @param[in] srcBLen length of the second input sequence.
    * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
    * @return none.
    */
   void arm_correlate_q7(
   q7_t * pSrcA,
   uint32_t srcALen,
   q7_t * pSrcB,
   uint32_t srcBLen,
   q7_t * pDst);
   /**
    * @brief Instance structure for the floating-point sparse FIR filter.
    */
   typedef struct
+  {
     uint16_t numTaps;             /**< number of coefficients in the filter. */
     uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
     float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
     float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
     uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
     int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
   } arm_fir_sparse_instance_f32;
   /**
    * @brief Instance structure for the Q31 sparse FIR filter.
    */
   typedef struct
+  {
     uint16_t numTaps;             /**< number of coefficients in the filter. */
     uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
     q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
     q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
     uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
     int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
   } arm_fir_sparse_instance_q31;
   /**
    * @brief Instance structure for the Q15 sparse FIR filter.
    */
   typedef struct
+  {
     uint16_t numTaps;             /**< number of coefficients in the filter. */
     uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
     q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
     q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
     uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
     int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
   } arm_fir_sparse_instance_q15;
   /**
    * @brief Instance structure for the Q7 sparse FIR filter.
    */
   typedef struct
+  {
     uint16_t numTaps;             /**< number of coefficients in the filter. */
     uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
     q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
     q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
     uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
     int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
   } arm_fir_sparse_instance_q7;
   /**
    * @brief Processing function for the floating-point sparse FIR filter.
    * @param[in]  *S          points to an instance of the floating-point sparse FIR structure.
    * @param[in]  *pSrc       points to the block of input data.
    * @param[out] *pDst       points to the block of output data
    * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
    * @param[in]  blockSize   number of input samples to process per call.
    * @return none.
    */
   void arm_fir_sparse_f32(
   arm_fir_sparse_instance_f32 * S,
   float32_t * pSrc,
   float32_t * pDst,
   float32_t * pScratchIn,
   uint32_t blockSize);
   /**
    * @brief  Initialization function for the floating-point sparse FIR filter.
    * @param[in,out] *S         points to an instance of the floating-point sparse FIR structure.
    * @param[in]     numTaps    number of nonzero coefficients in the filter.
    * @param[in]     *pCoeffs   points to the array of filter coefficients.
    * @param[in]     *pState    points to the state buffer.
    * @param[in]     *pTapDelay points to the array of offset times.
    * @param[in]     maxDelay   maximum offset time supported.
    * @param[in]     blockSize  number of samples that will be processed per block.
    * @return none
    */
   void arm_fir_sparse_init_f32(
   arm_fir_sparse_instance_f32 * S,
   uint16_t numTaps,
   float32_t * pCoeffs,
   float32_t * pState,
   int32_t * pTapDelay,
   uint16_t maxDelay,
   uint32_t blockSize);
   /**
    * @brief Processing function for the Q31 sparse FIR filter.
    * @param[in]  *S          points to an instance of the Q31 sparse FIR structure.
    * @param[in]  *pSrc       points to the block of input data.
    * @param[out] *pDst       points to the block of output data
    * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
    * @param[in]  blockSize   number of input samples to process per call.
    * @return none.
    */
   void arm_fir_sparse_q31(
   arm_fir_sparse_instance_q31 * S,
   q31_t * pSrc,
   q31_t * pDst,
   q31_t * pScratchIn,
   uint32_t blockSize);
   /**
    * @brief  Initialization function for the Q31 sparse FIR filter.
    * @param[in,out] *S         points to an instance of the Q31 sparse FIR structure.
    * @param[in]     numTaps    number of nonzero coefficients in the filter.
    * @param[in]     *pCoeffs   points to the array of filter coefficients.
    * @param[in]     *pState    points to the state buffer.
    * @param[in]     *pTapDelay points to the array of offset times.
    * @param[in]     maxDelay   maximum offset time supported.
    * @param[in]     blockSize  number of samples that will be processed per block.
    * @return none
    */
   void arm_fir_sparse_init_q31(
   arm_fir_sparse_instance_q31 * S,
   uint16_t numTaps,
   q31_t * pCoeffs,
   q31_t * pState,
   int32_t * pTapDelay,
   uint16_t maxDelay,
   uint32_t blockSize);
   /**
    * @brief Processing function for the Q15 sparse FIR filter.
    * @param[in]  *S           points to an instance of the Q15 sparse FIR structure.
    * @param[in]  *pSrc        points to the block of input data.
    * @param[out] *pDst        points to the block of output data
    * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
    * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
    * @param[in]  blockSize    number of input samples to process per call.
    * @return none.
    */
   void arm_fir_sparse_q15(
   arm_fir_sparse_instance_q15 * S,
   q15_t * pSrc,
   q15_t * pDst,
   q15_t * pScratchIn,
   q31_t * pScratchOut,
   uint32_t blockSize);
   /**
    * @brief  Initialization function for the Q15 sparse FIR filter.
    * @param[in,out] *S         points to an instance of the Q15 sparse FIR structure.
    * @param[in]     numTaps    number of nonzero coefficients in the filter.
    * @param[in]     *pCoeffs   points to the array of filter coefficients.
    * @param[in]     *pState    points to the state buffer.
    * @param[in]     *pTapDelay points to the array of offset times.
    * @param[in]     maxDelay   maximum offset time supported.
    * @param[in]     blockSize  number of samples that will be processed per block.
    * @return none
    */
   void arm_fir_sparse_init_q15(
   arm_fir_sparse_instance_q15 * S,
   uint16_t numTaps,
   q15_t * pCoeffs,
   q15_t * pState,
   int32_t * pTapDelay,
   uint16_t maxDelay,
   uint32_t blockSize);
   /**
    * @brief Processing function for the Q7 sparse FIR filter.
    * @param[in]  *S           points to an instance of the Q7 sparse FIR structure.
    * @param[in]  *pSrc        points to the block of input data.
    * @param[out] *pDst        points to the block of output data
    * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
    * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
    * @param[in]  blockSize    number of input samples to process per call.
    * @return none.
    */
   void arm_fir_sparse_q7(
   arm_fir_sparse_instance_q7 * S,
   q7_t * pSrc,
   q7_t * pDst,
   q7_t * pScratchIn,
   q31_t * pScratchOut,
   uint32_t blockSize);
   /**
    * @brief  Initialization function for the Q7 sparse FIR filter.
    * @param[in,out] *S         points to an instance of the Q7 sparse FIR structure.
    * @param[in]     numTaps    number of nonzero coefficients in the filter.
    * @param[in]     *pCoeffs   points to the array of filter coefficients.
    * @param[in]     *pState    points to the state buffer.
    * @param[in]     *pTapDelay points to the array of offset times.
    * @param[in]     maxDelay   maximum offset time supported.
    * @param[in]     blockSize  number of samples that will be processed per block.
    * @return none
    */
   void arm_fir_sparse_init_q7(
   arm_fir_sparse_instance_q7 * S,
   uint16_t numTaps,
   q7_t * pCoeffs,
   q7_t * pState,
   int32_t * pTapDelay,
   uint16_t maxDelay,
   uint32_t blockSize);
   /*
    * @brief  Floating-point sin_cos function.
    * @param[in]  theta    input value in degrees
    * @param[out] *pSinVal points to the processed sine output.
    * @param[out] *pCosVal points to the processed cos output.
    * @return none.
    */
   void arm_sin_cos_f32(
   float32_t theta,
   float32_t * pSinVal,
   float32_t * pCcosVal);
   /*
    * @brief  Q31 sin_cos function.
    * @param[in]  theta    scaled input value in degrees
    * @param[out] *pSinVal points to the processed sine output.
    * @param[out] *pCosVal points to the processed cosine output.
    * @return none.
    */
   void arm_sin_cos_q31(
   q31_t theta,
   q31_t * pSinVal,
   q31_t * pCosVal);
   /**
    * @brief  Floating-point complex conjugate.
    * @param[in]  *pSrc points to the input vector
    * @param[out]  *pDst points to the output vector
    * @param[in]  numSamples number of complex samples in each vector
    * @return none.
    */
   void arm_cmplx_conj_f32(
   float32_t * pSrc,
   float32_t * pDst,
   uint32_t numSamples);
   /**
    * @brief  Q31 complex conjugate.
    * @param[in]  *pSrc points to the input vector
    * @param[out]  *pDst points to the output vector
    * @param[in]  numSamples number of complex samples in each vector
    * @return none.
    */
   void arm_cmplx_conj_q31(
   q31_t * pSrc,
   q31_t * pDst,
   uint32_t numSamples);
   /**
    * @brief  Q15 complex conjugate.
    * @param[in]  *pSrc points to the input vector
    * @param[out]  *pDst points to the output vector
    * @param[in]  numSamples number of complex samples in each vector
    * @return none.
    */
   void arm_cmplx_conj_q15(
   q15_t * pSrc,
   q15_t * pDst,
   uint32_t numSamples);
   /**
    * @brief  Floating-point complex magnitude squared
    * @param[in]  *pSrc points to the complex input vector
    * @param[out]  *pDst points to the real output vector
    * @param[in]  numSamples number of complex samples in the input vector
    * @return none.
    */
   void arm_cmplx_mag_squared_f32(
   float32_t * pSrc,
   float32_t * pDst,
   uint32_t numSamples);
   /**
    * @brief  Q31 complex magnitude squared
    * @param[in]  *pSrc points to the complex input vector
    * @param[out]  *pDst points to the real output vector
    * @param[in]  numSamples number of complex samples in the input vector
    * @return none.
    */
   void arm_cmplx_mag_squared_q31(
   q31_t * pSrc,
   q31_t * pDst,
   uint32_t numSamples);
   /**
    * @brief  Q15 complex magnitude squared
    * @param[in]  *pSrc points to the complex input vector
    * @param[out]  *pDst points to the real output vector
    * @param[in]  numSamples number of complex samples in the input vector
    * @return none.
    */
   void arm_cmplx_mag_squared_q15(
   q15_t * pSrc,
   q15_t * pDst,
   uint32_t numSamples);
  /**
    * @ingroup groupController
    */
   /**
    * @defgroup PID PID Motor Control
+   *
    * A Proportional Integral Derivative (PID) controller is a generic feedback control
    * loop mechanism widely used in industrial control systems.
    * A PID controller is the most commonly used type of feedback controller.
+   *
    * This set of functions implements (PID) controllers
    * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
    * of data and each call to the function returns a single processed value.
    * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>
    * is the input sample value. The functions return the output value.
+   *
    * \par Algorithm:
    * <pre>
    *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
    *    A0 = Kp + Ki + Kd
    *    A1 = (-Kp ) - (2 * Kd )
    *    A2 = Kd  </pre>
+   *
    * \par
    * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+   *
    * \par
    * \image html PID.gif "Proportional Integral Derivative Controller"
+   *
    * \par
    * The PID controller calculates an "error" value as the difference between
    * the measured output and the reference input.
    * The controller attempts to minimize the error by adjusting the process control inputs.
    * The proportional value determines the reaction to the current error,
    * the integral value determines the reaction based on the sum of recent errors,
    * and the derivative value determines the reaction based on the rate at which the error has been changing.
+   *
    * \par Instance Structure
    * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
    * A separate instance structure must be defined for each PID Controller.
    * There are separate instance structure declarations for each of the 3 supported data types.
+   *
    * \par Reset Functions
    * There is also an associated reset function for each data type which clears the state array.
+   *
    * \par Initialization Functions
    * There is also an associated initialization function for each data type.
    * The initialization function performs the following operations:
    * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
    * - Zeros out the values in the state buffer.
+   *
    * \par
    * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+   *
    * \par Fixed-Point Behavior
    * Care must be taken when using the fixed-point versions of the PID Controller functions.
    * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
    * Refer to the function specific documentation below for usage guidelines.
    */
   /**
    * @addtogroup PID
    * @{
    */
   /**
    * @brief  Process function for the floating-point PID Control.
    * @param[in,out] *S is an instance of the floating-point PID Control structure
    * @param[in] in input sample to process
    * @return out processed output sample.
    */
   static __INLINE float32_t arm_pid_f32(
   arm_pid_instance_f32 * S,
   float32_t in)
+  {
     float32_t out;
     /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
     out = (S->A0 * in) +
       (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
     /* Update state */
     S->state[1] = S->state[0];
     S->state[0] = in;
     S->state[2] = out;
     /* return to application */
     return (out);
+  }
   /**
    * @brief  Process function for the Q31 PID Control.
    * @param[in,out] *S points to an instance of the Q31 PID Control structure
    * @param[in] in input sample to process
    * @return out processed output sample.
+   *
    * <b>Scaling and Overflow Behavior:</b>
    * \par
    * The function is implemented using an internal 64-bit accumulator.
    * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
    * Thus, if the accumulator result overflows it wraps around rather than clip.
    * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
    * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
    */
   static __INLINE q31_t arm_pid_q31(
   arm_pid_instance_q31 * S,
   q31_t in)
+  {
     q63_t acc;
     q31_t out;
     /* acc = A0 * x[n]  */
     acc = (q63_t) S->A0 * in;
     /* acc += A1 * x[n-1] */
     acc += (q63_t) S->A1 * S->state[0];
     /* acc += A2 * x[n-2]  */
     acc += (q63_t) S->A2 * S->state[1];
     /* convert output to 1.31 format to add y[n-1] */
     out = (q31_t) (acc >> 31u);
     /* out += y[n-1] */
     out += S->state[2];
     /* Update state */
     S->state[1] = S->state[0];
     S->state[0] = in;
     S->state[2] = out;
     /* return to application */
     return (out);
+  }
   /**
    * @brief  Process function for the Q15 PID Control.
    * @param[in,out] *S points to an instance of the Q15 PID Control structure
    * @param[in] in input sample to process
    * @return out processed output sample.
+   *
    * <b>Scaling and Overflow Behavior:</b>
    * \par
    * The function is implemented using a 64-bit internal accumulator.
    * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
    * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
    * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
    * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
    * Lastly, the accumulator is saturated to yield a result in 1.15 format.
    */
   static __INLINE q15_t arm_pid_q15(
   arm_pid_instance_q15 * S,
   q15_t in)
+  {
     q63_t acc;
     q15_t out;
 #ifndef ARM_MATH_CM0_FAMILY
     __SIMD32_TYPE *vstate;
     /* Implementation of PID controller */
     /* acc = A0 * x[n]  */
     acc = (q31_t) __SMUAD(S->A0, in);
     /* acc += A1 * x[n-1] + A2 * x[n-2]  */
     vstate = __SIMD32_CONST(S->state);
     acc = __SMLALD(S->A1, (q31_t) *vstate, acc);
 #else
     /* acc = A0 * x[n]  */
     acc = ((q31_t) S->A0) * in;
     /* acc += A1 * x[n-1] + A2 * x[n-2]  */
     acc += (q31_t) S->A1 * S->state[0];
     acc += (q31_t) S->A2 * S->state[1];
 #endif
     /* acc += y[n-1] */
     acc += (q31_t) S->state[2] << 15;
     /* saturate the output */
     out = (q15_t) (__SSAT((acc >> 15), 16));
     /* Update state */
     S->state[1] = S->state[0];
     S->state[0] = in;
     S->state[2] = out;
     /* return to application */
     return (out);
+  }
   /**
    * @} end of PID group
    */
   /**
    * @brief Floating-point matrix inverse.
    * @param[in]  *src points to the instance of the input floating-point matrix structure.
    * @param[out] *dst points to the instance of the output floating-point matrix structure.
    * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
    * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
    */
   arm_status arm_mat_inverse_f32(
   const arm_matrix_instance_f32 * src,
   arm_matrix_instance_f32 * dst);
   /**
    * @ingroup groupController
    */
   /**
    * @defgroup clarke Vector Clarke Transform
    * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
    * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
    * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
    * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
    * \image html clarke.gif Stator current space vector and its components in (a,b).
    * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
    * can be calculated using only <code>Ia</code> and <code>Ib</code>.
+   *
    * The function operates on a single sample of data and each call to the function returns the processed output.
    * The library provides separate functions for Q31 and floating-point data types.
    * \par Algorithm
    * \image html clarkeFormula.gif
    * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
    * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
    * \par Fixed-Point Behavior
    * Care must be taken when using the Q31 version of the Clarke transform.
    * In particular, the overflow and saturation behavior of the accumulator used must be considered.
    * Refer to the function specific documentation below for usage guidelines.
    */
   /**
    * @addtogroup clarke
    * @{
    */
   /**
+   *
    * @brief  Floating-point Clarke transform
    * @param[in]       Ia       input three-phase coordinate <code>a</code>
    * @param[in]       Ib       input three-phase coordinate <code>b</code>
    * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
    * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
    * @return none.
    */
   static __INLINE void arm_clarke_f32(
   float32_t Ia,
   float32_t Ib,
   float32_t * pIalpha,
   float32_t * pIbeta)
+  {
     /* Calculate pIalpha using the equation, pIalpha = Ia */
     *pIalpha = Ia;
     /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
     *pIbeta =
       ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+  }
   /**
    * @brief  Clarke transform for Q31 version
    * @param[in]       Ia       input three-phase coordinate <code>a</code>
    * @param[in]       Ib       input three-phase coordinate <code>b</code>
    * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
    * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
    * @return none.
+   *
    * <b>Scaling and Overflow Behavior:</b>
    * \par
    * The function is implemented using an internal 32-bit accumulator.
    * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
    * There is saturation on the addition, hence there is no risk of overflow.
    */
   static __INLINE void arm_clarke_q31(
   q31_t Ia,
   q31_t Ib,
   q31_t * pIalpha,
   q31_t * pIbeta)
+  {
     q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
     /* Calculating pIalpha from Ia by equation pIalpha = Ia */
     *pIalpha = Ia;
     /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
     product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
     /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
     product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
     /* pIbeta is calculated by adding the intermediate products */
     *pIbeta = __QADD(product1, product2);
+  }
   /**
    * @} end of clarke group
    */
   /**
    * @brief  Converts the elements of the Q7 vector to Q31 vector.
    * @param[in]  *pSrc     input pointer
    * @param[out]  *pDst    output pointer
    * @param[in]  blockSize number of samples to process
    * @return none.
    */
   void arm_q7_to_q31(
   q7_t * pSrc,
   q31_t * pDst,
   uint32_t blockSize);
   /**
    * @ingroup groupController
    */
   /**
    * @defgroup inv_clarke Vector Inverse Clarke Transform
    * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+   *
    * The function operates on a single sample of data and each call to the function returns the processed output.
    * The library provides separate functions for Q31 and floating-point data types.
    * \par Algorithm
    * \image html clarkeInvFormula.gif
    * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
    * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
    * \par Fixed-Point Behavior
    * Care must be taken when using the Q31 version of the Clarke transform.
    * In particular, the overflow and saturation behavior of the accumulator used must be considered.
    * Refer to the function specific documentation below for usage guidelines.
    */
   /**
    * @addtogroup inv_clarke
    * @{
    */
    /**
    * @brief  Floating-point Inverse Clarke transform
    * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
    * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
    * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
    * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
    * @return none.
    */
   static __INLINE void arm_inv_clarke_f32(
   float32_t Ialpha,
   float32_t Ibeta,
   float32_t * pIa,
   float32_t * pIb)
+  {
     /* Calculating pIa from Ialpha by equation pIa = Ialpha */
     *pIa = Ialpha;
     /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
     *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;
+  }
   /**
    * @brief  Inverse Clarke transform for Q31 version
    * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
    * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
    * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
    * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
    * @return none.
+   *
    * <b>Scaling and Overflow Behavior:</b>
    * \par
    * The function is implemented using an internal 32-bit accumulator.
    * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
    * There is saturation on the subtraction, hence there is no risk of overflow.
    */
   static __INLINE void arm_inv_clarke_q31(
   q31_t Ialpha,
   q31_t Ibeta,
   q31_t * pIa,
   q31_t * pIb)
+  {
     q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
     /* Calculating pIa from Ialpha by equation pIa = Ialpha */
     *pIa = Ialpha;
     /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
     product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
     /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
     product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
     /* pIb is calculated by subtracting the products */
     *pIb = __QSUB(product2, product1);
+  }
   /**
    * @} end of inv_clarke group
    */
   /**
    * @brief  Converts the elements of the Q7 vector to Q15 vector.
    * @param[in]  *pSrc     input pointer
    * @param[out] *pDst     output pointer
    * @param[in]  blockSize number of samples to process
    * @return none.
    */
   void arm_q7_to_q15(
   q7_t * pSrc,
   q15_t * pDst,
   uint32_t blockSize);
   /**
    * @ingroup groupController
    */
   /**
    * @defgroup park Vector Park Transform
+   *
    * Forward Park transform converts the input two-coordinate vector to flux and torque components.
    * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
    * from the stationary to the moving reference frame and control the spatial relationship between
    * the stator vector current and rotor flux vector.
    * If we consider the d axis aligned with the rotor flux, the diagram below shows the
    * current vector and the relationship from the two reference frames:
    * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+   *
    * The function operates on a single sample of data and each call to the function returns the processed output.
    * The library provides separate functions for Q31 and floating-point data types.
    * \par Algorithm
    * \image html parkFormula.gif
    * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
    * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
    * cosine and sine values of theta (rotor flux position).
    * \par Fixed-Point Behavior
    * Care must be taken when using the Q31 version of the Park transform.
    * In particular, the overflow and saturation behavior of the accumulator used must be considered.
    * Refer to the function specific documentation below for usage guidelines.
    */
   /**
    * @addtogroup park
    * @{
    */
   /**
    * @brief Floating-point Park transform
    * @param[in]       Ialpha input two-phase vector coordinate alpha
    * @param[in]       Ibeta  input two-phase vector coordinate beta
    * @param[out]      *pId   points to output	rotor reference frame d
    * @param[out]      *pIq   points to output	rotor reference frame q
    * @param[in]       sinVal sine value of rotation angle theta
    * @param[in]       cosVal cosine value of rotation angle theta
    * @return none.
+   *
    * The function implements the forward Park transform.
+   *
    */
   static __INLINE void arm_park_f32(
   float32_t Ialpha,
   float32_t Ibeta,
   float32_t * pId,
   float32_t * pIq,
   float32_t sinVal,
   float32_t cosVal)
+  {
     /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
     *pId = Ialpha * cosVal + Ibeta * sinVal;
     /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
     *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+  }
   /**
    * @brief  Park transform for Q31 version
    * @param[in]       Ialpha input two-phase vector coordinate alpha
    * @param[in]       Ibeta  input two-phase vector coordinate beta
    * @param[out]      *pId   points to output rotor reference frame d
    * @param[out]      *pIq   points to output rotor reference frame q
    * @param[in]       sinVal sine value of rotation angle theta
    * @param[in]       cosVal cosine value of rotation angle theta
    * @return none.
+   *
    * <b>Scaling and Overflow Behavior:</b>
    * \par
    * The function is implemented using an internal 32-bit accumulator.
    * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
    * There is saturation on the addition and subtraction, hence there is no risk of overflow.
    */
   static __INLINE void arm_park_q31(
   q31_t Ialpha,
   q31_t Ibeta,
   q31_t * pId,
   q31_t * pIq,
   q31_t sinVal,
   q31_t cosVal)
+  {
     q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
     q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
     /* Intermediate product is calculated by (Ialpha * cosVal) */
     product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
     /* Intermediate product is calculated by (Ibeta * sinVal) */
     product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
     /* Intermediate product is calculated by (Ialpha * sinVal) */
     product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
     /* Intermediate product is calculated by (Ibeta * cosVal) */
     product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
     /* Calculate pId by adding the two intermediate products 1 and 2 */
     *pId = __QADD(product1, product2);
     /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
     *pIq = __QSUB(product4, product3);
+  }
   /**
    * @} end of park group
    */
   /**
    * @brief  Converts the elements of the Q7 vector to floating-point vector.
    * @param[in]  *pSrc is input pointer
    * @param[out]  *pDst is output pointer
    * @param[in]  blockSize is the number of samples to process
    * @return none.
    */
   void arm_q7_to_float(
   q7_t * pSrc,
   float32_t * pDst,
   uint32_t blockSize);
   /**
    * @ingroup groupController
    */
   /**
    * @defgroup inv_park Vector Inverse Park transform
    * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+   *
    * The function operates on a single sample of data and each call to the function returns the processed output.
    * The library provides separate functions for Q31 and floating-point data types.
    * \par Algorithm
    * \image html parkInvFormula.gif
    * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
    * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
    * cosine and sine values of theta (rotor flux position).
    * \par Fixed-Point Behavior
    * Care must be taken when using the Q31 version of the Park transform.
    * In particular, the overflow and saturation behavior of the accumulator used must be considered.
    * Refer to the function specific documentation below for usage guidelines.
    */
   /**
    * @addtogroup inv_park
    * @{
    */
    /**
    * @brief  Floating-point Inverse Park transform
    * @param[in]       Id        input coordinate of rotor reference frame d
    * @param[in]       Iq        input coordinate of rotor reference frame q
    * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
    * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
    * @param[in]       sinVal    sine value of rotation angle theta
    * @param[in]       cosVal    cosine value of rotation angle theta
    * @return none.
    */
   static __INLINE void arm_inv_park_f32(
   float32_t Id,
   float32_t Iq,
   float32_t * pIalpha,
   float32_t * pIbeta,
   float32_t sinVal,
   float32_t cosVal)
+  {
     /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
     *pIalpha = Id * cosVal - Iq * sinVal;
     /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
     *pIbeta = Id * sinVal + Iq * cosVal;
+  }
   /**
    * @brief  Inverse Park transform for	Q31 version
    * @param[in]       Id        input coordinate of rotor reference frame d
    * @param[in]       Iq        input coordinate of rotor reference frame q
    * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
    * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
    * @param[in]       sinVal    sine value of rotation angle theta
    * @param[in]       cosVal    cosine value of rotation angle theta
    * @return none.
+   *
    * <b>Scaling and Overflow Behavior:</b>
    * \par
    * The function is implemented using an internal 32-bit accumulator.
    * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
    * There is saturation on the addition, hence there is no risk of overflow.
    */
   static __INLINE void arm_inv_park_q31(
   q31_t Id,
   q31_t Iq,
   q31_t * pIalpha,
   q31_t * pIbeta,
   q31_t sinVal,
   q31_t cosVal)
+  {
     q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
     q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
     /* Intermediate product is calculated by (Id * cosVal) */
     product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
     /* Intermediate product is calculated by (Iq * sinVal) */
     product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
     /* Intermediate product is calculated by (Id * sinVal) */
     product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
     /* Intermediate product is calculated by (Iq * cosVal) */
     product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
     /* Calculate pIalpha by using the two intermediate products 1 and 2 */
     *pIalpha = __QSUB(product1, product2);
     /* Calculate pIbeta by using the two intermediate products 3 and 4 */
     *pIbeta = __QADD(product4, product3);
+  }
   /**
    * @} end of Inverse park group
    */
   /**
    * @brief  Converts the elements of the Q31 vector to floating-point vector.
    * @param[in]  *pSrc is input pointer
    * @param[out]  *pDst is output pointer
    * @param[in]  blockSize is the number of samples to process
    * @return none.
    */
   void arm_q31_to_float(
   q31_t * pSrc,
   float32_t * pDst,
   uint32_t blockSize);
   /**
    * @ingroup groupInterpolation
    */
   /**
    * @defgroup LinearInterpolate Linear Interpolation
+   *
    * Linear interpolation is a method of curve fitting using linear polynomials.
    * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+   *
    * \par
    * \image html LinearInterp.gif "Linear interpolation"
+   *
    * \par
    * A  Linear Interpolate function calculates an output value(y), for the input(x)
    * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+   *
    * \par Algorithm:
    * <pre>
    *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
    *       where x0, x1 are nearest values of input x
    *             y0, y1 are nearest values to output y
    * </pre>
+   *
    * \par
    * This set of functions implements Linear interpolation process
    * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
    * sample of data and each call to the function returns a single processed value.
    * <code>S</code> points to an instance of the Linear Interpolate function data structure.
    * <code>x</code> is the input sample value. The functions returns the output value.
+   *
    * \par
    * if x is outside of the table boundary, Linear interpolation returns first value of the table
    * if x is below input range and returns last value of table if x is above range.
    */
   /**
    * @addtogroup LinearInterpolate
    * @{
    */
   /**
    * @brief  Process function for the floating-point Linear Interpolation Function.
    * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
    * @param[in] x input sample to process
    * @return y processed output sample.
+   *
    */
   static __INLINE float32_t arm_linear_interp_f32(
   arm_linear_interp_instance_f32 * S,
   float32_t x)
+  {
     float32_t y;
     float32_t x0, x1;                            /* Nearest input values */
     float32_t y0, y1;                            /* Nearest output values */
     float32_t xSpacing = S->xSpacing;            /* spacing between input values */
     int32_t i;                                   /* Index variable */
     float32_t *pYData = S->pYData;               /* pointer to output table */
     /* Calculation of index */
     i = (int32_t) ((x - S->x1) / xSpacing);
     if(i < 0)
+    {
       /* Iniatilize output for below specified range as least output value of table */
       y = pYData[0];
+    }
     else if((uint32_t)i >= S->nValues)
+    {
       /* Iniatilize output for above specified range as last output value of table */
       y = pYData[S->nValues - 1];
+    }
     else
+    {
       /* Calculation of nearest input values */
       x0 = S->x1 + i * xSpacing;
       x1 = S->x1 + (i + 1) * xSpacing;
       /* Read of nearest output values */
       y0 = pYData[i];
       y1 = pYData[i + 1];
       /* Calculation of output */
       y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+    }
     /* returns output value */
     return (y);
+  }
    /**
+   *
    * @brief  Process function for the Q31 Linear Interpolation Function.
    * @param[in] *pYData  pointer to Q31 Linear Interpolation table
    * @param[in] x input sample to process
    * @param[in] nValues number of table values
    * @return y processed output sample.
+   *
    * \par
    * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
    * This function can support maximum of table size 2^12.
+   *
    */
   static __INLINE q31_t arm_linear_interp_q31(
   q31_t * pYData,
   q31_t x,
   uint32_t nValues)
+  {
     q31_t y;                                     /* output */
     q31_t y0, y1;                                /* Nearest output values */
     q31_t fract;                                 /* fractional part */
     int32_t index;                               /* Index to read nearest output values */
     /* Input is in 12.20 format */
     /* 12 bits for the table index */
     /* Index value calculation */
     index = ((x & 0xFFF00000) >> 20);
     if(index >= (int32_t)(nValues - 1))
+    {
       return (pYData[nValues - 1]);
+    }
     else if(index < 0)
+    {
       return (pYData[0]);
+    }
     else
+    {
       /* 20 bits for the fractional part */
       /* shift left by 11 to keep fract in 1.31 format */
       fract = (x & 0x000FFFFF) << 11;
       /* Read two nearest output values from the index in 1.31(q31) format */
       y0 = pYData[index];
       y1 = pYData[index + 1u];
       /* Calculation of y0 * (1-fract) and y is in 2.30 format */
       y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
       /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
       y += ((q31_t) (((q63_t) y1 * fract) >> 32));
       /* Convert y to 1.31 format */
       return (y << 1u);
+    }
+  }
   /**
+   *
    * @brief  Process function for the Q15 Linear Interpolation Function.
    * @param[in] *pYData  pointer to Q15 Linear Interpolation table
    * @param[in] x input sample to process
    * @param[in] nValues number of table values
    * @return y processed output sample.
+   *
    * \par
    * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
    * This function can support maximum of table size 2^12.
+   *
    */
   static __INLINE q15_t arm_linear_interp_q15(
   q15_t * pYData,
   q31_t x,
   uint32_t nValues)
+  {
     q63_t y;                                     /* output */
     q15_t y0, y1;                                /* Nearest output values */
     q31_t fract;                                 /* fractional part */
     int32_t index;                               /* Index to read nearest output values */
     /* Input is in 12.20 format */
     /* 12 bits for the table index */
     /* Index value calculation */
     index = ((x & 0xFFF00000) >> 20u);
     if(index >= (int32_t)(nValues - 1))
+    {
       return (pYData[nValues - 1]);
+    }
     else if(index < 0)
+    {
       return (pYData[0]);
+    }
     else
+    {
       /* 20 bits for the fractional part */
       /* fract is in 12.20 format */
       fract = (x & 0x000FFFFF);
       /* Read two nearest output values from the index */
       y0 = pYData[index];
       y1 = pYData[index + 1u];
       /* Calculation of y0 * (1-fract) and y is in 13.35 format */
       y = ((q63_t) y0 * (0xFFFFF - fract));
       /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
       y += ((q63_t) y1 * (fract));
       /* convert y to 1.15 format */
       return (y >> 20);
+    }
+  }
   /**
+   *
    * @brief  Process function for the Q7 Linear Interpolation Function.
    * @param[in] *pYData  pointer to Q7 Linear Interpolation table
    * @param[in] x input sample to process
    * @param[in] nValues number of table values
    * @return y processed output sample.
+   *
    * \par
    * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
    * This function can support maximum of table size 2^12.
    */
   static __INLINE q7_t arm_linear_interp_q7(
   q7_t * pYData,
   q31_t x,
   uint32_t nValues)
+  {
     q31_t y;                                     /* output */
     q7_t y0, y1;                                 /* Nearest output values */
     q31_t fract;                                 /* fractional part */
     uint32_t index;                              /* Index to read nearest output values */
     /* Input is in 12.20 format */
     /* 12 bits for the table index */
     /* Index value calculation */
     if (x < 0)
+    {
       return (pYData[0]);
+    }
     index = (x >> 20) & 0xfff;
     if(index >= (nValues - 1))
+    {
       return (pYData[nValues - 1]);
+    }
     else
+    {
       /* 20 bits for the fractional part */
       /* fract is in 12.20 format */
       fract = (x & 0x000FFFFF);
       /* Read two nearest output values from the index and are in 1.7(q7) format */
       y0 = pYData[index];
       y1 = pYData[index + 1u];
       /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
       y = ((y0 * (0xFFFFF - fract)));
       /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
       y += (y1 * fract);
       /* convert y to 1.7(q7) format */
       return (y >> 20u);
+    }
+  }
   /**
    * @} end of LinearInterpolate group
    */
   /**
    * @brief  Fast approximation to the trigonometric sine function for floating-point data.
    * @param[in] x input value in radians.
    * @return  sin(x).
    */
   float32_t arm_sin_f32(
   float32_t x);
   /**
    * @brief  Fast approximation to the trigonometric sine function for Q31 data.
    * @param[in] x Scaled input value in radians.
    * @return  sin(x).
    */
   q31_t arm_sin_q31(
   q31_t x);
   /**
    * @brief  Fast approximation to the trigonometric sine function for Q15 data.
    * @param[in] x Scaled input value in radians.
    * @return  sin(x).
    */
   q15_t arm_sin_q15(
   q15_t x);
   /**
    * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
    * @param[in] x input value in radians.
    * @return  cos(x).
    */
   float32_t arm_cos_f32(
   float32_t x);
   /**
    * @brief Fast approximation to the trigonometric cosine function for Q31 data.
    * @param[in] x Scaled input value in radians.
    * @return  cos(x).
    */
   q31_t arm_cos_q31(
   q31_t x);
   /**
    * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
    * @param[in] x Scaled input value in radians.
    * @return  cos(x).
    */
   q15_t arm_cos_q15(
   q15_t x);
   /**
    * @ingroup groupFastMath
    */
   /**
    * @defgroup SQRT Square Root
+   *
    * Computes the square root of a number.
    * There are separate functions for Q15, Q31, and floating-point data types.
    * The square root function is computed using the Newton-Raphson algorithm.
    * This is an iterative algorithm of the form:
    * <pre>
    *      x1 = x0 - f(x0)/f'(x0)
    * </pre>
    * where <code>x1</code> is the current estimate,
    * <code>x0</code> is the previous estimate, and
    * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
    * For the square root function, the algorithm reduces to:
    * <pre>
    *     x0 = in/2                         [initial guess]
    *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
    * </pre>
    */
   /**
    * @addtogroup SQRT
    * @{
    */
   /**
    * @brief  Floating-point square root function.
    * @param[in]  in     input value.
    * @param[out] *pOut  square root of input value.
    * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
    * <code>in</code> is negative value and returns zero output for negative values.
    */
   static __INLINE arm_status arm_sqrt_f32(
   float32_t in,
   float32_t * pOut)
+  {
     if(in > 0)
+    {
 //      #if __FPU_USED
 #if (__FPU_USED == 1) && defined ( __CC_ARM   )
       *pOut = __sqrtf(in);
 #else
       *pOut = sqrtf(in);
 #endif
       return (ARM_MATH_SUCCESS);
+    }
     else
+    {
       *pOut = 0.0f;
       return (ARM_MATH_ARGUMENT_ERROR);
+    }
+  }
   /**
    * @brief Q31 square root function.
    * @param[in]   in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
    * @param[out]  *pOut square root of input value.
    * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
    * <code>in</code> is negative value and returns zero output for negative values.
    */
   arm_status arm_sqrt_q31(
   q31_t in,
   q31_t * pOut);
   /**
    * @brief  Q15 square root function.
    * @param[in]   in     input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
    * @param[out]  *pOut  square root of input value.
    * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
    * <code>in</code> is negative value and returns zero output for negative values.
    */
   arm_status arm_sqrt_q15(
   q15_t in,
   q15_t * pOut);
   /**
    * @} end of SQRT group
    */
   /**
    * @brief floating-point Circular write function.
    */
   static __INLINE void arm_circularWrite_f32(
   int32_t * circBuffer,
   int32_t L,
   uint16_t * writeOffset,
   int32_t bufferInc,
   const int32_t * src,
   int32_t srcInc,
   uint32_t blockSize)
+  {
     uint32_t i = 0u;
     int32_t wOffset;
     /* Copy the value of Index pointer that points
      * to the current location where the input samples to be copied */
     wOffset = *writeOffset;
     /* Loop over the blockSize */
     i = blockSize;
     while(i > 0u)
+    {
       /* copy the input sample to the circular buffer */
       circBuffer[wOffset] = *src;
       /* Update the input pointer */
       src += srcInc;
       /* Circularly update wOffset.  Watch out for positive and negative value */
       wOffset += bufferInc;
       if(wOffset >= L)
         wOffset -= L;
       /* Decrement the loop counter */
       i--;
+    }
     /* Update the index pointer */
     *writeOffset = wOffset;
+  }
   /**
    * @brief floating-point Circular Read function.
    */
   static __INLINE void arm_circularRead_f32(
   int32_t * circBuffer,
   int32_t L,
   int32_t * readOffset,
   int32_t bufferInc,
   int32_t * dst,
   int32_t * dst_base,
   int32_t dst_length,
   int32_t dstInc,
   uint32_t blockSize)
+  {
     uint32_t i = 0u;
     int32_t rOffset, dst_end;
     /* Copy the value of Index pointer that points
      * to the current location from where the input samples to be read */
     rOffset = *readOffset;
     dst_end = (int32_t) (dst_base + dst_length);
     /* Loop over the blockSize */
     i = blockSize;
     while(i > 0u)
+    {
       /* copy the sample from the circular buffer to the destination buffer */
       *dst = circBuffer[rOffset];
       /* Update the input pointer */
       dst += dstInc;
       if(dst == (int32_t *) dst_end)
+      {
         dst = dst_base;
+      }
       /* Circularly update rOffset.  Watch out for positive and negative value  */
       rOffset += bufferInc;
       if(rOffset >= L)
+      {
         rOffset -= L;
+      }
       /* Decrement the loop counter */
       i--;
+    }
     /* Update the index pointer */
     *readOffset = rOffset;
+  }
   /**
    * @brief Q15 Circular write function.
    */
   static __INLINE void arm_circularWrite_q15(
   q15_t * circBuffer,
   int32_t L,
   uint16_t * writeOffset,
   int32_t bufferInc,
   const q15_t * src,
   int32_t srcInc,
   uint32_t blockSize)
+  {
     uint32_t i = 0u;
     int32_t wOffset;
     /* Copy the value of Index pointer that points
      * to the current location where the input samples to be copied */
     wOffset = *writeOffset;
     /* Loop over the blockSize */
     i = blockSize;
     while(i > 0u)
+    {
       /* copy the input sample to the circular buffer */
       circBuffer[wOffset] = *src;
       /* Update the input pointer */
       src += srcInc;
       /* Circularly update wOffset.  Watch out for positive and negative value */
       wOffset += bufferInc;
       if(wOffset >= L)
         wOffset -= L;
       /* Decrement the loop counter */
       i--;
+    }
     /* Update the index pointer */
     *writeOffset = wOffset;
+  }
   /**
    * @brief Q15 Circular Read function.
    */
   static __INLINE void arm_circularRead_q15(
   q15_t * circBuffer,
   int32_t L,
   int32_t * readOffset,
   int32_t bufferInc,
   q15_t * dst,
   q15_t * dst_base,
   int32_t dst_length,
   int32_t dstInc,
   uint32_t blockSize)
+  {
     uint32_t i = 0;
     int32_t rOffset, dst_end;
     /* Copy the value of Index pointer that points
      * to the current location from where the input samples to be read */
     rOffset = *readOffset;
     dst_end = (int32_t) (dst_base + dst_length);
     /* Loop over the blockSize */
     i = blockSize;
     while(i > 0u)
+    {
       /* copy the sample from the circular buffer to the destination buffer */
       *dst = circBuffer[rOffset];
       /* Update the input pointer */
       dst += dstInc;
       if(dst == (q15_t *) dst_end)
+      {
         dst = dst_base;
+      }
       /* Circularly update wOffset.  Watch out for positive and negative value */
       rOffset += bufferInc;
       if(rOffset >= L)
+      {
         rOffset -= L;
+      }
       /* Decrement the loop counter */
       i--;
+    }
     /* Update the index pointer */
     *readOffset = rOffset;
+  }
   /**
    * @brief Q7 Circular write function.
    */
   static __INLINE void arm_circularWrite_q7(
   q7_t * circBuffer,
   int32_t L,
   uint16_t * writeOffset,
   int32_t bufferInc,
   const q7_t * src,
   int32_t srcInc,
   uint32_t blockSize)
+  {
     uint32_t i = 0u;
     int32_t wOffset;
     /* Copy the value of Index pointer that points
      * to the current location where the input samples to be copied */
     wOffset = *writeOffset;
     /* Loop over the blockSize */
     i = blockSize;
     while(i > 0u)
+    {
       /* copy the input sample to the circular buffer */
       circBuffer[wOffset] = *src;
       /* Update the input pointer */
       src += srcInc;
       /* Circularly update wOffset.  Watch out for positive and negative value */
       wOffset += bufferInc;
       if(wOffset >= L)
         wOffset -= L;
       /* Decrement the loop counter */
       i--;
+    }
     /* Update the index pointer */
     *writeOffset = wOffset;
+  }
   /**
    * @brief Q7 Circular Read function.
    */
   static __INLINE void arm_circularRead_q7(
   q7_t * circBuffer,
   int32_t L,
   int32_t * readOffset,
   int32_t bufferInc,
   q7_t * dst,
   q7_t * dst_base,
   int32_t dst_length,
   int32_t dstInc,
   uint32_t blockSize)
+  {
     uint32_t i = 0;
     int32_t rOffset, dst_end;
     /* Copy the value of Index pointer that points
      * to the current location from where the input samples to be read */
     rOffset = *readOffset;
     dst_end = (int32_t) (dst_base + dst_length);
     /* Loop over the blockSize */
     i = blockSize;
     while(i > 0u)
+    {
       /* copy the sample from the circular buffer to the destination buffer */
       *dst = circBuffer[rOffset];
       /* Update the input pointer */
       dst += dstInc;
       if(dst == (q7_t *) dst_end)
+      {
         dst = dst_base;
+      }
       /* Circularly update rOffset.  Watch out for positive and negative value */
       rOffset += bufferInc;
       if(rOffset >= L)
+      {
         rOffset -= L;
+      }
       /* Decrement the loop counter */
       i--;
+    }
     /* Update the index pointer */
     *readOffset = rOffset;
+  }
   /**
    * @brief  Sum of the squares of the elements of a Q31 vector.
    * @param[in]  *pSrc is input pointer
    * @param[in]  blockSize is the number of samples to process
    * @param[out]  *pResult is output value.
    * @return none.
    */
   void arm_power_q31(
   q31_t * pSrc,
   uint32_t blockSize,
   q63_t * pResult);
   /**
    * @brief  Sum of the squares of the elements of a floating-point vector.
    * @param[in]  *pSrc is input pointer
    * @param[in]  blockSize is the number of samples to process
    * @param[out]  *pResult is output value.
    * @return none.
    */
   void arm_power_f32(
   float32_t * pSrc,
   uint32_t blockSize,
   float32_t * pResult);
   /**
    * @brief  Sum of the squares of the elements of a Q15 vector.
    * @param[in]  *pSrc is input pointer
    * @param[in]  blockSize is the number of samples to process
    * @param[out]  *pResult is output value.
    * @return none.
    */
   void arm_power_q15(
   q15_t * pSrc,
   uint32_t blockSize,
   q63_t * pResult);
   /**
    * @brief  Sum of the squares of the elements of a Q7 vector.
    * @param[in]  *pSrc is input pointer
    * @param[in]  blockSize is the number of samples to process
    * @param[out]  *pResult is output value.
    * @return none.
    */
   void arm_power_q7(
   q7_t * pSrc,
   uint32_t blockSize,
   q31_t * pResult);
   /**
    * @brief  Mean value of a Q7 vector.
    * @param[in]  *pSrc is input pointer
    * @param[in]  blockSize is the number of samples to process
    * @param[out]  *pResult is output value.
    * @return none.
    */
   void arm_mean_q7(
   q7_t * pSrc,
   uint32_t blockSize,
   q7_t * pResult);
   /**
    * @brief  Mean value of a Q15 vector.
    * @param[in]  *pSrc is input pointer
    * @param[in]  blockSize is the number of samples to process
    * @param[out]  *pResult is output value.
    * @return none.
    */
   void arm_mean_q15(
   q15_t * pSrc,
   uint32_t blockSize,
   q15_t * pResult);
   /**
    * @brief  Mean value of a Q31 vector.
    * @param[in]  *pSrc is input pointer
    * @param[in]  blockSize is the number of samples to process
    * @param[out]  *pResult is output value.
    * @return none.
    */
   void arm_mean_q31(
   q31_t * pSrc,
   uint32_t blockSize,
   q31_t * pResult);
   /**
    * @brief  Mean value of a floating-point vector.
    * @param[in]  *pSrc is input pointer
    * @param[in]  blockSize is the number of samples to process
    * @param[out]  *pResult is output value.
    * @return none.
    */
   void arm_mean_f32(
   float32_t * pSrc,
   uint32_t blockSize,
   float32_t * pResult);
   /**
    * @brief  Variance of the elements of a floating-point vector.
    * @param[in]  *pSrc is input pointer
    * @param[in]  blockSize is the number of samples to process
    * @param[out]  *pResult is output value.
    * @return none.
    */
   void arm_var_f32(
   float32_t * pSrc,
   uint32_t blockSize,
   float32_t * pResult);
   /**
    * @brief  Variance of the elements of a Q31 vector.
    * @param[in]  *pSrc is input pointer
    * @param[in]  blockSize is the number of samples to process
    * @param[out]  *pResult is output value.
    * @return none.
    */
   void arm_var_q31(
   q31_t * pSrc,
   uint32_t blockSize,
   q63_t * pResult);
   /**
    * @brief  Variance of the elements of a Q15 vector.
    * @param[in]  *pSrc is input pointer
    * @param[in]  blockSize is the number of samples to process
    * @param[out]  *pResult is output value.
    * @return none.
    */
   void arm_var_q15(
   q15_t * pSrc,
   uint32_t blockSize,
   q31_t * pResult);
   /**
    * @brief  Root Mean Square of the elements of a floating-point vector.
    * @param[in]  *pSrc is input pointer
    * @param[in]  blockSize is the number of samples to process
    * @param[out]  *pResult is output value.
    * @return none.
    */
   void arm_rms_f32(
   float32_t * pSrc,
   uint32_t blockSize,
   float32_t * pResult);
   /**
    * @brief  Root Mean Square of the elements of a Q31 vector.
    * @param[in]  *pSrc is input pointer
    * @param[in]  blockSize is the number of samples to process
    * @param[out]  *pResult is output value.
    * @return none.
    */
   void arm_rms_q31(
   q31_t * pSrc,
   uint32_t blockSize,
   q31_t * pResult);
   /**
    * @brief  Root Mean Square of the elements of a Q15 vector.
    * @param[in]  *pSrc is input pointer
    * @param[in]  blockSize is the number of samples to process
    * @param[out]  *pResult is output value.
    * @return none.
    */
   void arm_rms_q15(
   q15_t * pSrc,
   uint32_t blockSize,
   q15_t * pResult);
   /**
    * @brief  Standard deviation of the elements of a floating-point vector.
    * @param[in]  *pSrc is input pointer
    * @param[in]  blockSize is the number of samples to process
    * @param[out]  *pResult is output value.
    * @return none.
    */
   void arm_std_f32(
   float32_t * pSrc,
   uint32_t blockSize,
   float32_t * pResult);
   /**
    * @brief  Standard deviation of the elements of a Q31 vector.
    * @param[in]  *pSrc is input pointer
    * @param[in]  blockSize is the number of samples to process
    * @param[out]  *pResult is output value.
    * @return none.
    */
   void arm_std_q31(
   q31_t * pSrc,
   uint32_t blockSize,
   q31_t * pResult);
   /**
    * @brief  Standard deviation of the elements of a Q15 vector.
    * @param[in]  *pSrc is input pointer
    * @param[in]  blockSize is the number of samples to process
    * @param[out]  *pResult is output value.
    * @return none.
    */
   void arm_std_q15(
   q15_t * pSrc,
   uint32_t blockSize,
   q15_t * pResult);
   /**
    * @brief  Floating-point complex magnitude
    * @param[in]  *pSrc points to the complex input vector
    * @param[out]  *pDst points to the real output vector
    * @param[in]  numSamples number of complex samples in the input vector
    * @return none.
    */
   void arm_cmplx_mag_f32(
   float32_t * pSrc,
   float32_t * pDst,
   uint32_t numSamples);
   /**
    * @brief  Q31 complex magnitude
    * @param[in]  *pSrc points to the complex input vector
    * @param[out]  *pDst points to the real output vector
    * @param[in]  numSamples number of complex samples in the input vector
    * @return none.
    */
   void arm_cmplx_mag_q31(
   q31_t * pSrc,
   q31_t * pDst,
   uint32_t numSamples);
   /**
    * @brief  Q15 complex magnitude
    * @param[in]  *pSrc points to the complex input vector
    * @param[out]  *pDst points to the real output vector
    * @param[in]  numSamples number of complex samples in the input vector
    * @return none.
    */
   void arm_cmplx_mag_q15(
   q15_t * pSrc,
   q15_t * pDst,
   uint32_t numSamples);
   /**
    * @brief  Q15 complex dot product
    * @param[in]  *pSrcA points to the first input vector
    * @param[in]  *pSrcB points to the second input vector
    * @param[in]  numSamples number of complex samples in each vector
    * @param[out]  *realResult real part of the result returned here
    * @param[out]  *imagResult imaginary part of the result returned here
    * @return none.
    */
   void arm_cmplx_dot_prod_q15(
   q15_t * pSrcA,
   q15_t * pSrcB,
   uint32_t numSamples,
   q31_t * realResult,
   q31_t * imagResult);
   /**
    * @brief  Q31 complex dot product
    * @param[in]  *pSrcA points to the first input vector
    * @param[in]  *pSrcB points to the second input vector
    * @param[in]  numSamples number of complex samples in each vector
    * @param[out]  *realResult real part of the result returned here
    * @param[out]  *imagResult imaginary part of the result returned here
    * @return none.
    */
   void arm_cmplx_dot_prod_q31(
   q31_t * pSrcA,
   q31_t * pSrcB,
   uint32_t numSamples,
   q63_t * realResult,
   q63_t * imagResult);
   /**
    * @brief  Floating-point complex dot product
    * @param[in]  *pSrcA points to the first input vector
    * @param[in]  *pSrcB points to the second input vector
    * @param[in]  numSamples number of complex samples in each vector
    * @param[out]  *realResult real part of the result returned here
    * @param[out]  *imagResult imaginary part of the result returned here
    * @return none.
    */
   void arm_cmplx_dot_prod_f32(
   float32_t * pSrcA,
   float32_t * pSrcB,
   uint32_t numSamples,
   float32_t * realResult,
   float32_t * imagResult);
   /**
    * @brief  Q15 complex-by-real multiplication
    * @param[in]  *pSrcCmplx points to the complex input vector
    * @param[in]  *pSrcReal points to the real input vector
    * @param[out]  *pCmplxDst points to the complex output vector
    * @param[in]  numSamples number of samples in each vector
    * @return none.
    */
   void arm_cmplx_mult_real_q15(
   q15_t * pSrcCmplx,
   q15_t * pSrcReal,
   q15_t * pCmplxDst,
   uint32_t numSamples);
   /**
    * @brief  Q31 complex-by-real multiplication
    * @param[in]  *pSrcCmplx points to the complex input vector
    * @param[in]  *pSrcReal points to the real input vector
    * @param[out]  *pCmplxDst points to the complex output vector
    * @param[in]  numSamples number of samples in each vector
    * @return none.
    */
   void arm_cmplx_mult_real_q31(
   q31_t * pSrcCmplx,
   q31_t * pSrcReal,
   q31_t * pCmplxDst,
   uint32_t numSamples);
   /**
    * @brief  Floating-point complex-by-real multiplication
    * @param[in]  *pSrcCmplx points to the complex input vector
    * @param[in]  *pSrcReal points to the real input vector
    * @param[out]  *pCmplxDst points to the complex output vector
    * @param[in]  numSamples number of samples in each vector
    * @return none.
    */
   void arm_cmplx_mult_real_f32(
   float32_t * pSrcCmplx,
   float32_t * pSrcReal,
   float32_t * pCmplxDst,
   uint32_t numSamples);
   /**
    * @brief  Minimum value of a Q7 vector.
    * @param[in]  *pSrc is input pointer
    * @param[in]  blockSize is the number of samples to process
    * @param[out]  *result is output pointer
    * @param[in]  index is the array index of the minimum value in the input buffer.
    * @return none.
    */
   void arm_min_q7(
   q7_t * pSrc,
   uint32_t blockSize,
   q7_t * result,
   uint32_t * index);
   /**
    * @brief  Minimum value of a Q15 vector.
    * @param[in]  *pSrc is input pointer
    * @param[in]  blockSize is the number of samples to process
    * @param[out]  *pResult is output pointer
    * @param[in]  *pIndex is the array index of the minimum value in the input buffer.
    * @return none.
    */
   void arm_min_q15(
   q15_t * pSrc,
   uint32_t blockSize,
   q15_t * pResult,
   uint32_t * pIndex);
   /**
    * @brief  Minimum value of a Q31 vector.
    * @param[in]  *pSrc is input pointer
    * @param[in]  blockSize is the number of samples to process
    * @param[out]  *pResult is output pointer
    * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
    * @return none.
    */
   void arm_min_q31(
   q31_t * pSrc,
   uint32_t blockSize,
   q31_t * pResult,
   uint32_t * pIndex);
   /**
    * @brief  Minimum value of a floating-point vector.
    * @param[in]  *pSrc is input pointer
    * @param[in]  blockSize is the number of samples to process
    * @param[out]  *pResult is output pointer
    * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
    * @return none.
    */
   void arm_min_f32(
   float32_t * pSrc,
   uint32_t blockSize,
   float32_t * pResult,
   uint32_t * pIndex);
 /**
  * @brief Maximum value of a Q7 vector.
  * @param[in]       *pSrc points to the input buffer
  * @param[in]       blockSize length of the input vector
  * @param[out]      *pResult maximum value returned here
  * @param[out]      *pIndex index of maximum value returned here
  * @return none.
  */
   void arm_max_q7(
   q7_t * pSrc,
   uint32_t blockSize,
   q7_t * pResult,
   uint32_t * pIndex);
 /**
  * @brief Maximum value of a Q15 vector.
  * @param[in]       *pSrc points to the input buffer
  * @param[in]       blockSize length of the input vector
  * @param[out]      *pResult maximum value returned here
  * @param[out]      *pIndex index of maximum value returned here
  * @return none.
  */
   void arm_max_q15(
   q15_t * pSrc,
   uint32_t blockSize,
   q15_t * pResult,
   uint32_t * pIndex);
 /**
  * @brief Maximum value of a Q31 vector.
  * @param[in]       *pSrc points to the input buffer
  * @param[in]       blockSize length of the input vector
  * @param[out]      *pResult maximum value returned here
  * @param[out]      *pIndex index of maximum value returned here
  * @return none.
  */
   void arm_max_q31(
   q31_t * pSrc,
   uint32_t blockSize,
   q31_t * pResult,
   uint32_t * pIndex);
 /**
  * @brief Maximum value of a floating-point vector.
  * @param[in]       *pSrc points to the input buffer
  * @param[in]       blockSize length of the input vector
  * @param[out]      *pResult maximum value returned here
  * @param[out]      *pIndex index of maximum value returned here
  * @return none.
  */
   void arm_max_f32(
   float32_t * pSrc,
   uint32_t blockSize,
   float32_t * pResult,
   uint32_t * pIndex);
   /**
    * @brief  Q15 complex-by-complex multiplication
    * @param[in]  *pSrcA points to the first input vector
    * @param[in]  *pSrcB points to the second input vector
    * @param[out]  *pDst  points to the output vector
    * @param[in]  numSamples number of complex samples in each vector
    * @return none.
    */
   void arm_cmplx_mult_cmplx_q15(
   q15_t * pSrcA,
   q15_t * pSrcB,
   q15_t * pDst,
   uint32_t numSamples);
   /**
    * @brief  Q31 complex-by-complex multiplication
    * @param[in]  *pSrcA points to the first input vector
    * @param[in]  *pSrcB points to the second input vector
    * @param[out]  *pDst  points to the output vector
    * @param[in]  numSamples number of complex samples in each vector
    * @return none.
    */
   void arm_cmplx_mult_cmplx_q31(
   q31_t * pSrcA,
   q31_t * pSrcB,
   q31_t * pDst,
   uint32_t numSamples);
   /**
    * @brief  Floating-point complex-by-complex multiplication
    * @param[in]  *pSrcA points to the first input vector
    * @param[in]  *pSrcB points to the second input vector
    * @param[out]  *pDst  points to the output vector
    * @param[in]  numSamples number of complex samples in each vector
    * @return none.
    */
   void arm_cmplx_mult_cmplx_f32(
   float32_t * pSrcA,
   float32_t * pSrcB,
   float32_t * pDst,
   uint32_t numSamples);
   /**
    * @brief Converts the elements of the floating-point vector to Q31 vector.
    * @param[in]       *pSrc points to the floating-point input vector
    * @param[out]      *pDst points to the Q31 output vector
    * @param[in]       blockSize length of the input vector
    * @return none.
    */
   void arm_float_to_q31(
   float32_t * pSrc,
   q31_t * pDst,
   uint32_t blockSize);
   /**
    * @brief Converts the elements of the floating-point vector to Q15 vector.
    * @param[in]       *pSrc points to the floating-point input vector
    * @param[out]      *pDst points to the Q15 output vector
    * @param[in]       blockSize length of the input vector
    * @return          none
    */
   void arm_float_to_q15(
   float32_t * pSrc,
   q15_t * pDst,
   uint32_t blockSize);
   /**
    * @brief Converts the elements of the floating-point vector to Q7 vector.
    * @param[in]       *pSrc points to the floating-point input vector
    * @param[out]      *pDst points to the Q7 output vector
    * @param[in]       blockSize length of the input vector
    * @return          none
    */
   void arm_float_to_q7(
   float32_t * pSrc,
   q7_t * pDst,
   uint32_t blockSize);
   /**
    * @brief  Converts the elements of the Q31 vector to Q15 vector.
    * @param[in]  *pSrc is input pointer
    * @param[out]  *pDst is output pointer
    * @param[in]  blockSize is the number of samples to process
    * @return none.
    */
   void arm_q31_to_q15(
   q31_t * pSrc,
   q15_t * pDst,
   uint32_t blockSize);
   /**
    * @brief  Converts the elements of the Q31 vector to Q7 vector.
    * @param[in]  *pSrc is input pointer
    * @param[out]  *pDst is output pointer
    * @param[in]  blockSize is the number of samples to process
    * @return none.
    */
   void arm_q31_to_q7(
   q31_t * pSrc,
   q7_t * pDst,
   uint32_t blockSize);
   /**
    * @brief  Converts the elements of the Q15 vector to floating-point vector.
    * @param[in]  *pSrc is input pointer
    * @param[out]  *pDst is output pointer
    * @param[in]  blockSize is the number of samples to process
    * @return none.
    */
   void arm_q15_to_float(
   q15_t * pSrc,
   float32_t * pDst,
   uint32_t blockSize);
   /**
    * @brief  Converts the elements of the Q15 vector to Q31 vector.
    * @param[in]  *pSrc is input pointer
    * @param[out]  *pDst is output pointer
    * @param[in]  blockSize is the number of samples to process
    * @return none.
    */
   void arm_q15_to_q31(
   q15_t * pSrc,
   q31_t * pDst,
   uint32_t blockSize);
   /**
    * @brief  Converts the elements of the Q15 vector to Q7 vector.
    * @param[in]  *pSrc is input pointer
    * @param[out]  *pDst is output pointer
    * @param[in]  blockSize is the number of samples to process
    * @return none.
    */
   void arm_q15_to_q7(
   q15_t * pSrc,
   q7_t * pDst,
   uint32_t blockSize);
   /**
    * @ingroup groupInterpolation
    */
   /**
    * @defgroup BilinearInterpolate Bilinear Interpolation
+   *
    * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
    * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
    * determines values between the grid points.
    * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
    * Bilinear interpolation is often used in image processing to rescale images.
    * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+   *
    * <b>Algorithm</b>
    * \par
    * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
    * For floating-point, the instance structure is defined as:
    * <pre>
    *   typedef struct
    *   {
    *     uint16_t numRows;
    *     uint16_t numCols;
    *     float32_t *pData;
    * } arm_bilinear_interp_instance_f32;
    * </pre>
+   *
    * \par
    * where <code>numRows</code> specifies the number of rows in the table;
    * <code>numCols</code> specifies the number of columns in the table;
    * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
    * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
    * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
+   *
    * \par
    * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:
    * <pre>
    *     XF = floor(x)
    *     YF = floor(y)
    * </pre>
    * \par
    * The interpolated output point is computed as:
    * <pre>
    *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
    *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
    *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
    *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
    * </pre>
    * Note that the coordinates (x, y) contain integer and fractional components.
    * The integer components specify which portion of the table to use while the
    * fractional components control the interpolation processor.
+   *
    * \par
    * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
    */
   /**
    * @addtogroup BilinearInterpolate
    * @{
    */
   /**
+  *
   * @brief  Floating-point bilinear interpolation.
   * @param[in,out] *S points to an instance of the interpolation structure.
   * @param[in] X interpolation coordinate.
   * @param[in] Y interpolation coordinate.
   * @return out interpolated value.
   */
   static __INLINE float32_t arm_bilinear_interp_f32(
   const arm_bilinear_interp_instance_f32 * S,
   float32_t X,
   float32_t Y)
+  {
     float32_t out;
     float32_t f00, f01, f10, f11;
     float32_t *pData = S->pData;
     int32_t xIndex, yIndex, index;
     float32_t xdiff, ydiff;
     float32_t b1, b2, b3, b4;
     xIndex = (int32_t) X;
     yIndex = (int32_t) Y;
     /* Care taken for table outside boundary */
     /* Returns zero output when values are outside table boundary */
     if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0
        || yIndex > (S->numCols - 1))
+    {
       return (0);
+    }
     /* Calculation of index for two nearest points in X-direction */
     index = (xIndex - 1) + (yIndex - 1) * S->numCols;
     /* Read two nearest points in X-direction */
     f00 = pData[index];
     f01 = pData[index + 1];
     /* Calculation of index for two nearest points in Y-direction */
     index = (xIndex - 1) + (yIndex) * S->numCols;
     /* Read two nearest points in Y-direction */
     f10 = pData[index];
     f11 = pData[index + 1];
     /* Calculation of intermediate values */
     b1 = f00;
     b2 = f01 - f00;
     b3 = f10 - f00;
     b4 = f00 - f01 - f10 + f11;
     /* Calculation of fractional part in X */
     xdiff = X - xIndex;
     /* Calculation of fractional part in Y */
     ydiff = Y - yIndex;
     /* Calculation of bi-linear interpolated output */
     out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
     /* return to application */
     return (out);
+  }
   /**
+  *
   * @brief  Q31 bilinear interpolation.
   * @param[in,out] *S points to an instance of the interpolation structure.
   * @param[in] X interpolation coordinate in 12.20 format.
   * @param[in] Y interpolation coordinate in 12.20 format.
   * @return out interpolated value.
   */
   static __INLINE q31_t arm_bilinear_interp_q31(
   arm_bilinear_interp_instance_q31 * S,
   q31_t X,
   q31_t Y)
+  {
     q31_t out;                                   /* Temporary output */
     q31_t acc = 0;                               /* output */
     q31_t xfract, yfract;                        /* X, Y fractional parts */
     q31_t x1, x2, y1, y2;                        /* Nearest output values */
     int32_t rI, cI;                              /* Row and column indices */
     q31_t *pYData = S->pData;                    /* pointer to output table values */
     uint32_t nCols = S->numCols;                 /* num of rows */
     /* Input is in 12.20 format */
     /* 12 bits for the table index */
     /* Index value calculation */
     rI = ((X & 0xFFF00000) >> 20u);
     /* Input is in 12.20 format */
     /* 12 bits for the table index */
     /* Index value calculation */
     cI = ((Y & 0xFFF00000) >> 20u);
     /* Care taken for table outside boundary */
     /* Returns zero output when values are outside table boundary */
     if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
       return (0);
+    }
     /* 20 bits for the fractional part */
     /* shift left xfract by 11 to keep 1.31 format */
     xfract = (X & 0x000FFFFF) << 11u;
     /* Read two nearest output values from the index */
     x1 = pYData[(rI) + nCols * (cI)];
     x2 = pYData[(rI) + nCols * (cI) + 1u];
     /* 20 bits for the fractional part */
     /* shift left yfract by 11 to keep 1.31 format */
     yfract = (Y & 0x000FFFFF) << 11u;
     /* Read two nearest output values from the index */
     y1 = pYData[(rI) + nCols * (cI + 1)];
     y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
     /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
     out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
     acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
     /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
     out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
     acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
     /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
     out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
     acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
     /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
     out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
     acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
     /* Convert acc to 1.31(q31) format */
     return (acc << 2u);
+  }
   /**
   * @brief  Q15 bilinear interpolation.
   * @param[in,out] *S points to an instance of the interpolation structure.
   * @param[in] X interpolation coordinate in 12.20 format.
   * @param[in] Y interpolation coordinate in 12.20 format.
   * @return out interpolated value.
   */
   static __INLINE q15_t arm_bilinear_interp_q15(
   arm_bilinear_interp_instance_q15 * S,
   q31_t X,
   q31_t Y)
+  {
     q63_t acc = 0;                               /* output */
     q31_t out;                                   /* Temporary output */
     q15_t x1, x2, y1, y2;                        /* Nearest output values */
     q31_t xfract, yfract;                        /* X, Y fractional parts */
     int32_t rI, cI;                              /* Row and column indices */
     q15_t *pYData = S->pData;                    /* pointer to output table values */
     uint32_t nCols = S->numCols;                 /* num of rows */
     /* Input is in 12.20 format */
     /* 12 bits for the table index */
     /* Index value calculation */
     rI = ((X & 0xFFF00000) >> 20);
     /* Input is in 12.20 format */
     /* 12 bits for the table index */
     /* Index value calculation */
     cI = ((Y & 0xFFF00000) >> 20);
     /* Care taken for table outside boundary */
     /* Returns zero output when values are outside table boundary */
     if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
       return (0);
+    }
     /* 20 bits for the fractional part */
     /* xfract should be in 12.20 format */
     xfract = (X & 0x000FFFFF);
     /* Read two nearest output values from the index */
     x1 = pYData[(rI) + nCols * (cI)];
     x2 = pYData[(rI) + nCols * (cI) + 1u];
     /* 20 bits for the fractional part */
     /* yfract should be in 12.20 format */
     yfract = (Y & 0x000FFFFF);
     /* Read two nearest output values from the index */
     y1 = pYData[(rI) + nCols * (cI + 1)];
     y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
     /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
     /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
     /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
     out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
     acc = ((q63_t) out * (0xFFFFF - yfract));
     /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
     out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
     acc += ((q63_t) out * (xfract));
     /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
     out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
     acc += ((q63_t) out * (yfract));
     /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
     out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
     acc += ((q63_t) out * (yfract));
     /* acc is in 13.51 format and down shift acc by 36 times */
     /* Convert out to 1.15 format */
     return (acc >> 36);
+  }
   /**
   * @brief  Q7 bilinear interpolation.
   * @param[in,out] *S points to an instance of the interpolation structure.
   * @param[in] X interpolation coordinate in 12.20 format.
   * @param[in] Y interpolation coordinate in 12.20 format.
   * @return out interpolated value.
   */
   static __INLINE q7_t arm_bilinear_interp_q7(
   arm_bilinear_interp_instance_q7 * S,
   q31_t X,
   q31_t Y)
+  {
     q63_t acc = 0;                               /* output */
     q31_t out;                                   /* Temporary output */
     q31_t xfract, yfract;                        /* X, Y fractional parts */
     q7_t x1, x2, y1, y2;                         /* Nearest output values */
     int32_t rI, cI;                              /* Row and column indices */
     q7_t *pYData = S->pData;                     /* pointer to output table values */
     uint32_t nCols = S->numCols;                 /* num of rows */
     /* Input is in 12.20 format */
     /* 12 bits for the table index */
     /* Index value calculation */
     rI = ((X & 0xFFF00000) >> 20);
     /* Input is in 12.20 format */
     /* 12 bits for the table index */
     /* Index value calculation */
     cI = ((Y & 0xFFF00000) >> 20);
     /* Care taken for table outside boundary */
     /* Returns zero output when values are outside table boundary */
     if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
       return (0);
+    }
     /* 20 bits for the fractional part */
     /* xfract should be in 12.20 format */
     xfract = (X & 0x000FFFFF);
     /* Read two nearest output values from the index */
     x1 = pYData[(rI) + nCols * (cI)];
     x2 = pYData[(rI) + nCols * (cI) + 1u];
     /* 20 bits for the fractional part */
     /* yfract should be in 12.20 format */
     yfract = (Y & 0x000FFFFF);
     /* Read two nearest output values from the index */
     y1 = pYData[(rI) + nCols * (cI + 1)];
     y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
     /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
     out = ((x1 * (0xFFFFF - xfract)));
     acc = (((q63_t) out * (0xFFFFF - yfract)));
     /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
     out = ((x2 * (0xFFFFF - yfract)));
     acc += (((q63_t) out * (xfract)));
     /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
     out = ((y1 * (0xFFFFF - xfract)));
     acc += (((q63_t) out * (yfract)));
     /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
     out = ((y2 * (yfract)));
     acc += (((q63_t) out * (xfract)));
     /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
     return (acc >> 40);
+  }
   /**
    * @} end of BilinearInterpolate group
    */
 #if   defined ( __CC_ARM ) //Keil
 //SMMLAR
   #define multAcc_32x32_keep32_R(a, x, y) \
   a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
 //SMMLSR
   #define multSub_32x32_keep32_R(a, x, y) \
   a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
 //SMMULR
   #define mult_32x32_keep32_R(a, x, y) \
   a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
 //Enter low optimization region - place directly above function definition
   #define LOW_OPTIMIZATION_ENTER \
      _Pragma ("push")         \
      _Pragma ("O1")
 //Exit low optimization region - place directly after end of function definition
   #define LOW_OPTIMIZATION_EXIT \
      _Pragma ("pop")
 //Enter low optimization region - place directly above function definition
   #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
 //Exit low optimization region - place directly after end of function definition
   #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
 #elif defined(__ICCARM__) //IAR
  //SMMLA
   #define multAcc_32x32_keep32_R(a, x, y) \
   a += (q31_t) (((q63_t) x * y) >> 32)
  //SMMLS
   #define multSub_32x32_keep32_R(a, x, y) \
   a -= (q31_t) (((q63_t) x * y) >> 32)
 //SMMUL
   #define mult_32x32_keep32_R(a, x, y) \
   a = (q31_t) (((q63_t) x * y ) >> 32)
 //Enter low optimization region - place directly above function definition
   #define LOW_OPTIMIZATION_ENTER \
      _Pragma ("optimize=low")
 //Exit low optimization region - place directly after end of function definition
   #define LOW_OPTIMIZATION_EXIT
 //Enter low optimization region - place directly above function definition
   #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
      _Pragma ("optimize=low")
 //Exit low optimization region - place directly after end of function definition
   #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
 #elif defined(__GNUC__)
  //SMMLA
   #define multAcc_32x32_keep32_R(a, x, y) \
   a += (q31_t) (((q63_t) x * y) >> 32)
  //SMMLS
   #define multSub_32x32_keep32_R(a, x, y) \
   a -= (q31_t) (((q63_t) x * y) >> 32)
 //SMMUL
   #define mult_32x32_keep32_R(a, x, y) \
   a = (q31_t) (((q63_t) x * y ) >> 32)
   #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))
   #define LOW_OPTIMIZATION_EXIT
   #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
   #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
 #endif
 #ifdef	__cplusplus
+}
 #endif
 #endif /* _ARM_MATH_H */
 /**
+ *
  * End of file.
  */

libraries/CMSIS/Include/core_cm0.h

➞

Show inline comments

@@ new file 100644 @@
 /**************************************************************************//**
  * @file     core_cm0.h
  * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
  * @version  V3.20
  * @date     25. February 2013
+ *
  * @note
+ *
  ******************************************************************************/
 /* Copyright (c) 2009 - 2013 ARM LIMITED
    All rights reserved.
    Redistribution and use in source and binary forms, with or without
    modification, are permitted provided that the following conditions are met:
    - Redistributions of source code must retain the above copyright
      notice, this list of conditions and the following disclaimer.
    - Redistributions in binary form must reproduce the above copyright
      notice, this list of conditions and the following disclaimer in the
      documentation and/or other materials provided with the distribution.
    - Neither the name of ARM nor the names of its contributors may be used
      to endorse or promote products derived from this software without
      specific prior written permission.
+   *
    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
    IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
    ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
    LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
    INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
    CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
    POSSIBILITY OF SUCH DAMAGE.
    ---------------------------------------------------------------------------*/
 #if defined ( __ICCARM__ )
  #pragma system_include  /* treat file as system include file for MISRA check */
 #endif
 #ifdef __cplusplus
  extern "C" {
 #endif
 #ifndef __CORE_CM0_H_GENERIC
 #define __CORE_CM0_H_GENERIC
 /** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
   CMSIS violates the following MISRA-C:2004 rules:
    \li Required Rule 8.5, object/function definition in header file.<br>
      Function definitions in header files are used to allow 'inlining'.
    \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
      Unions are used for effective representation of core registers.
    \li Advisory Rule 19.7, Function-like macro defined.<br>
      Function-like macros are used to allow more efficient code.
  */
 /*******************************************************************************
  *                 CMSIS definitions
  ******************************************************************************/
 /** \ingroup Cortex_M0
   @{
  */
 /*  CMSIS CM0 definitions */
 #define __CM0_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
 #define __CM0_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version    */
 #define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | \
                                     __CM0_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
 #define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
 #if   defined ( __CC_ARM )
   #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
   #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
   #define __STATIC_INLINE  static __inline
 #elif defined ( __ICCARM__ )
   #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
   #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
   #define __STATIC_INLINE  static inline
 #elif defined ( __GNUC__ )
   #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
   #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
   #define __STATIC_INLINE  static inline
 #elif defined ( __TASKING__ )
   #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
   #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
   #define __STATIC_INLINE  static inline
 #endif
 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
 */
 #define __FPU_USED       0
 #if defined ( __CC_ARM )
   #if defined __TARGET_FPU_VFP
     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 #elif defined ( __ICCARM__ )
   #if defined __ARMVFP__
     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 #elif defined ( __GNUC__ )
   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 #elif defined ( __TASKING__ )
   #if defined __FPU_VFP__
     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 #endif
 #include <stdint.h>                      /* standard types definitions                      */
 #include <core_cmInstr.h>                /* Core Instruction Access                         */
 #include <core_cmFunc.h>                 /* Core Function Access                            */
 #endif /* __CORE_CM0_H_GENERIC */
 #ifndef __CMSIS_GENERIC
 #ifndef __CORE_CM0_H_DEPENDANT
 #define __CORE_CM0_H_DEPENDANT
 /* check device defines and use defaults */
 #if defined __CHECK_DEVICE_DEFINES
   #ifndef __CM0_REV
     #define __CM0_REV               0x0000
     #warning "__CM0_REV not defined in device header file; using default!"
   #endif
   #ifndef __NVIC_PRIO_BITS
     #define __NVIC_PRIO_BITS          2
     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
   #endif
   #ifndef __Vendor_SysTickConfig
     #define __Vendor_SysTickConfig    0
     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
   #endif
 #endif
 /* IO definitions (access restrictions to peripheral registers) */
 /**
     \defgroup CMSIS_glob_defs CMSIS Global Defines
     <strong>IO Type Qualifiers</strong> are used
     \li to specify the access to peripheral variables.
     \li for automatic generation of peripheral register debug information.
 */
 #ifdef __cplusplus
   #define   __I     volatile             /*!< Defines 'read only' permissions                 */
 #else
   #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
 #endif
 #define     __O     volatile             /*!< Defines 'write only' permissions                */
 #define     __IO    volatile             /*!< Defines 'read / write' permissions              */
 /*@} end of group Cortex_M0 */
 /*******************************************************************************
  *                 Register Abstraction
   Core Register contain:
   - Core Register
   - Core NVIC Register
   - Core SCB Register
   - Core SysTick Register
  ******************************************************************************/
 /** \defgroup CMSIS_core_register Defines and Type Definitions
     \brief Type definitions and defines for Cortex-M processor based devices.
 */
 /** \ingroup    CMSIS_core_register
     \defgroup   CMSIS_CORE  Status and Control Registers
     \brief  Core Register type definitions.
   @{
  */
 /** \brief  Union type to access the Application Program Status Register (APSR).
  */
 typedef union
+{
   struct
+  {
 #if (__CORTEX_M != 0x04)
     uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
 #else
     uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
     uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
 #endif
     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
   } b;                                   /*!< Structure used for bit  access                  */
   uint32_t w;                            /*!< Type      used for word access                  */
 } APSR_Type;
 /** \brief  Union type to access the Interrupt Program Status Register (IPSR).
  */
 typedef union
+{
   struct
+  {
     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
     uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
   } b;                                   /*!< Structure used for bit  access                  */
   uint32_t w;                            /*!< Type      used for word access                  */
 } IPSR_Type;
 /** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
  */
 typedef union
+{
   struct
+  {
     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
 #if (__CORTEX_M != 0x04)
     uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
 #else
     uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
     uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
 #endif
     uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
     uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
   } b;                                   /*!< Structure used for bit  access                  */
   uint32_t w;                            /*!< Type      used for word access                  */
 } xPSR_Type;
 /** \brief  Union type to access the Control Registers (CONTROL).
  */
 typedef union
+{
   struct
+  {
     uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
     uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
     uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
     uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
   } b;                                   /*!< Structure used for bit  access                  */
   uint32_t w;                            /*!< Type      used for word access                  */
 } CONTROL_Type;
 /*@} end of group CMSIS_CORE */
 /** \ingroup    CMSIS_core_register
     \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
     \brief      Type definitions for the NVIC Registers
   @{
  */
 /** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
  */
 typedef struct
+{
   __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
        uint32_t RESERVED0[31];
   __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
        uint32_t RSERVED1[31];
   __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
        uint32_t RESERVED2[31];
   __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
        uint32_t RESERVED3[31];
        uint32_t RESERVED4[64];
   __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
 }  NVIC_Type;
 /*@} end of group CMSIS_NVIC */
 /** \ingroup  CMSIS_core_register
     \defgroup CMSIS_SCB     System Control Block (SCB)
     \brief      Type definitions for the System Control Block Registers
   @{
  */
 /** \brief  Structure type to access the System Control Block (SCB).
  */
 typedef struct
+{
   __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
   __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
        uint32_t RESERVED0;
   __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
   __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
   __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
        uint32_t RESERVED1;
   __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
   __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
 } SCB_Type;
 /* SCB CPUID Register Definitions */
 #define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
 #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
 #define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
 #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
 #define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
 #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
 #define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
 #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
 #define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
 #define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
 /* SCB Interrupt Control State Register Definitions */
 #define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
 #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
 #define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
 #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
 #define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
 #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
 #define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
 #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
 #define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
 #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
 #define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
 #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
 #define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
 #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
 #define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
 #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
 #define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
 #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
 /* SCB Application Interrupt and Reset Control Register Definitions */
 #define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
 #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
 #define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
 #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
 #define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
 #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
 #define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
 #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
 #define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
 #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
 /* SCB System Control Register Definitions */
 #define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
 #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
 #define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
 #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
 #define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
 #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
 /* SCB Configuration Control Register Definitions */
 #define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
 #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
 #define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
 #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
 /* SCB System Handler Control and State Register Definitions */
 #define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
 #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
 /*@} end of group CMSIS_SCB */
 /** \ingroup  CMSIS_core_register
     \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
     \brief      Type definitions for the System Timer Registers.
   @{
  */
 /** \brief  Structure type to access the System Timer (SysTick).
  */
 typedef struct
+{
   __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
   __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
   __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
   __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
 } SysTick_Type;
 /* SysTick Control / Status Register Definitions */
 #define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
 #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
 #define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
 #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
 #define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
 #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
 #define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
 #define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
 /* SysTick Reload Register Definitions */
 #define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
 #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
 /* SysTick Current Register Definitions */
 #define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
 #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
 /* SysTick Calibration Register Definitions */
 #define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
 #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
 #define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
 #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
 #define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
 #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
 /*@} end of group CMSIS_SysTick */
 /** \ingroup  CMSIS_core_register
     \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
     \brief      Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
                 are only accessible over DAP and not via processor. Therefore
                 they are not covered by the Cortex-M0 header file.
   @{
  */
 /*@} end of group CMSIS_CoreDebug */
 /** \ingroup    CMSIS_core_register
     \defgroup   CMSIS_core_base     Core Definitions
     \brief      Definitions for base addresses, unions, and structures.
   @{
  */
 /* Memory mapping of Cortex-M0 Hardware */
 #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
 #define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
 #define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
 #define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
 #define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
 #define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
 #define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
 /*@} */
 /*******************************************************************************
  *                Hardware Abstraction Layer
   Core Function Interface contains:
   - Core NVIC Functions
   - Core SysTick Functions
   - Core Register Access Functions
  ******************************************************************************/
 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
 */
 /* ##########################   NVIC functions  #################################### */
 /** \ingroup  CMSIS_Core_FunctionInterface
     \defgroup CMSIS_Core_NVICFunctions NVIC Functions
     \brief      Functions that manage interrupts and exceptions via the NVIC.
     @{
  */
 /* Interrupt Priorities are WORD accessible only under ARMv6M                   */
 /* The following MACROS handle generation of the register offset and byte masks */
 #define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
 #define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
 #define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
 /** \brief  Enable External Interrupt
     The function enables a device-specific interrupt in the NVIC interrupt controller.
     \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
   NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
 /** \brief  Disable External Interrupt
     The function disables a device-specific interrupt in the NVIC interrupt controller.
     \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
   NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
 /** \brief  Get Pending Interrupt
     The function reads the pending register in the NVIC and returns the pending bit
     for the specified interrupt.
     \param [in]      IRQn  Interrupt number.
     \return             0  Interrupt status is not pending.
     \return             1  Interrupt status is pending.
  */
 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
   return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
 /** \brief  Set Pending Interrupt
     The function sets the pending bit of an external interrupt.
     \param [in]      IRQn  Interrupt number. Value cannot be negative.
  */
 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
   NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
 /** \brief  Clear Pending Interrupt
     The function clears the pending bit of an external interrupt.
     \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
   NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
 /** \brief  Set Interrupt Priority
     The function sets the priority of an interrupt.
     \note The priority cannot be set for every core interrupt.
     \param [in]      IRQn  Interrupt number.
     \param [in]  priority  Priority to set.
  */
 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
   if(IRQn < 0) {
     SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
         (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
   else {
     NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
         (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
 /** \brief  Get Interrupt Priority
     The function reads the priority of an interrupt. The interrupt
     number can be positive to specify an external (device specific)
     interrupt, or negative to specify an internal (core) interrupt.
     \param [in]   IRQn  Interrupt number.
     \return             Interrupt Priority. Value is aligned automatically to the implemented
                         priority bits of the microcontroller.
  */
 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
   if(IRQn < 0) {
     return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
   else {
     return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
 /** \brief  System Reset
     The function initiates a system reset request to reset the MCU.
  */
 __STATIC_INLINE void NVIC_SystemReset(void)
+{
   __DSB();                                                     /* Ensure all outstanding memory accesses included
                                                                   buffered write are completed before reset */
   SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
                  SCB_AIRCR_SYSRESETREQ_Msk);
   __DSB();                                                     /* Ensure completion of memory access */
   while(1);                                                    /* wait until reset */
+}
 /*@} end of CMSIS_Core_NVICFunctions */
 /* ##################################    SysTick function  ############################################ */
 /** \ingroup  CMSIS_Core_FunctionInterface
     \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
     \brief      Functions that configure the System.
   @{
  */
 #if (__Vendor_SysTickConfig == 0)
 /** \brief  System Tick Configuration
     The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
     Counter is in free running mode to generate periodic interrupts.
     \param [in]  ticks  Number of ticks between two interrupts.
     \return          0  Function succeeded.
     \return          1  Function failed.
     \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
     function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
     must contain a vendor-specific implementation of this function.
  */
 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
   if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
   SysTick->LOAD  = ticks - 1;                                  /* set reload register */
   NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
   SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
                    SysTick_CTRL_TICKINT_Msk   |
                    SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
   return (0);                                                  /* Function successful */
+}
 #endif
 /*@} end of CMSIS_Core_SysTickFunctions */
 #endif /* __CORE_CM0_H_DEPENDANT */
 #endif /* __CMSIS_GENERIC */
 #ifdef __cplusplus
+}
 #endif

libraries/CMSIS/Include/core_cm0plus.h

➞

Show inline comments

@@ new file 100644 @@
 /**************************************************************************//**
  * @file     core_cm0plus.h
  * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
  * @version  V3.20
  * @date     25. February 2013
+ *
  * @note
+ *
  ******************************************************************************/
 /* Copyright (c) 2009 - 2013 ARM LIMITED
    All rights reserved.
    Redistribution and use in source and binary forms, with or without
    modification, are permitted provided that the following conditions are met:
    - Redistributions of source code must retain the above copyright
      notice, this list of conditions and the following disclaimer.
    - Redistributions in binary form must reproduce the above copyright
      notice, this list of conditions and the following disclaimer in the
      documentation and/or other materials provided with the distribution.
    - Neither the name of ARM nor the names of its contributors may be used
      to endorse or promote products derived from this software without
      specific prior written permission.
+   *
    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
    IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
    ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
    LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
    INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
    CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
    POSSIBILITY OF SUCH DAMAGE.
    ---------------------------------------------------------------------------*/
 #if defined ( __ICCARM__ )
  #pragma system_include  /* treat file as system include file for MISRA check */
 #endif
 #ifdef __cplusplus
  extern "C" {
 #endif
 #ifndef __CORE_CM0PLUS_H_GENERIC
 #define __CORE_CM0PLUS_H_GENERIC
 /** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
   CMSIS violates the following MISRA-C:2004 rules:
    \li Required Rule 8.5, object/function definition in header file.<br>
      Function definitions in header files are used to allow 'inlining'.
    \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
      Unions are used for effective representation of core registers.
    \li Advisory Rule 19.7, Function-like macro defined.<br>
      Function-like macros are used to allow more efficient code.
  */
 /*******************************************************************************
  *                 CMSIS definitions
  ******************************************************************************/
 /** \ingroup Cortex-M0+
   @{
  */
 /*  CMSIS CM0P definitions */
 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x03)                                /*!< [31:16] CMSIS HAL main version   */
 #define __CM0PLUS_CMSIS_VERSION_SUB  (0x20)                                /*!< [15:0]  CMSIS HAL sub version    */
 #define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
                                        __CM0PLUS_CMSIS_VERSION_SUB)        /*!< CMSIS HAL version number         */
 #define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
 #if   defined ( __CC_ARM )
   #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
   #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
   #define __STATIC_INLINE  static __inline
 #elif defined ( __ICCARM__ )
   #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
   #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
   #define __STATIC_INLINE  static inline
 #elif defined ( __GNUC__ )
   #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
   #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
   #define __STATIC_INLINE  static inline
 #elif defined ( __TASKING__ )
   #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
   #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
   #define __STATIC_INLINE  static inline
 #endif
 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
 */
 #define __FPU_USED       0
 #if defined ( __CC_ARM )
   #if defined __TARGET_FPU_VFP
     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 #elif defined ( __ICCARM__ )
   #if defined __ARMVFP__
     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 #elif defined ( __GNUC__ )
   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 #elif defined ( __TASKING__ )
   #if defined __FPU_VFP__
     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 #endif
 #include <stdint.h>                      /* standard types definitions                      */
 #include <core_cmInstr.h>                /* Core Instruction Access                         */
 #include <core_cmFunc.h>                 /* Core Function Access                            */
 #endif /* __CORE_CM0PLUS_H_GENERIC */
 #ifndef __CMSIS_GENERIC
 #ifndef __CORE_CM0PLUS_H_DEPENDANT
 #define __CORE_CM0PLUS_H_DEPENDANT
 /* check device defines and use defaults */
 #if defined __CHECK_DEVICE_DEFINES
   #ifndef __CM0PLUS_REV
     #define __CM0PLUS_REV             0x0000
     #warning "__CM0PLUS_REV not defined in device header file; using default!"
   #endif
   #ifndef __MPU_PRESENT
     #define __MPU_PRESENT             0
     #warning "__MPU_PRESENT not defined in device header file; using default!"
   #endif
   #ifndef __VTOR_PRESENT
     #define __VTOR_PRESENT            0
     #warning "__VTOR_PRESENT not defined in device header file; using default!"
   #endif
   #ifndef __NVIC_PRIO_BITS
     #define __NVIC_PRIO_BITS          2
     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
   #endif
   #ifndef __Vendor_SysTickConfig
     #define __Vendor_SysTickConfig    0
     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
   #endif
 #endif
 /* IO definitions (access restrictions to peripheral registers) */
 /**
     \defgroup CMSIS_glob_defs CMSIS Global Defines
     <strong>IO Type Qualifiers</strong> are used
     \li to specify the access to peripheral variables.
     \li for automatic generation of peripheral register debug information.
 */
 #ifdef __cplusplus
   #define   __I     volatile             /*!< Defines 'read only' permissions                 */
 #else
   #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
 #endif
 #define     __O     volatile             /*!< Defines 'write only' permissions                */
 #define     __IO    volatile             /*!< Defines 'read / write' permissions              */
 /*@} end of group Cortex-M0+ */
 /*******************************************************************************
  *                 Register Abstraction
   Core Register contain:
   - Core Register
   - Core NVIC Register
   - Core SCB Register
   - Core SysTick Register
   - Core MPU Register
  ******************************************************************************/
 /** \defgroup CMSIS_core_register Defines and Type Definitions
     \brief Type definitions and defines for Cortex-M processor based devices.
 */
 /** \ingroup    CMSIS_core_register
     \defgroup   CMSIS_CORE  Status and Control Registers
     \brief  Core Register type definitions.
   @{
  */
 /** \brief  Union type to access the Application Program Status Register (APSR).
  */
 typedef union
+{
   struct
+  {
 #if (__CORTEX_M != 0x04)
     uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
 #else
     uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
     uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
 #endif
     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
   } b;                                   /*!< Structure used for bit  access                  */
   uint32_t w;                            /*!< Type      used for word access                  */
 } APSR_Type;
 /** \brief  Union type to access the Interrupt Program Status Register (IPSR).
  */
 typedef union
+{
   struct
+  {
     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
     uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
   } b;                                   /*!< Structure used for bit  access                  */
   uint32_t w;                            /*!< Type      used for word access                  */
 } IPSR_Type;
 /** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
  */
 typedef union
+{
   struct
+  {
     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
 #if (__CORTEX_M != 0x04)
     uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
 #else
     uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
     uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
 #endif
     uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
     uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
   } b;                                   /*!< Structure used for bit  access                  */
   uint32_t w;                            /*!< Type      used for word access                  */
 } xPSR_Type;
 /** \brief  Union type to access the Control Registers (CONTROL).
  */
 typedef union
+{
   struct
+  {
     uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
     uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
     uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
     uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
   } b;                                   /*!< Structure used for bit  access                  */
   uint32_t w;                            /*!< Type      used for word access                  */
 } CONTROL_Type;
 /*@} end of group CMSIS_CORE */
 /** \ingroup    CMSIS_core_register
     \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
     \brief      Type definitions for the NVIC Registers
   @{
  */
 /** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
  */
 typedef struct
+{
   __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
        uint32_t RESERVED0[31];
   __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
        uint32_t RSERVED1[31];
   __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
        uint32_t RESERVED2[31];
   __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
        uint32_t RESERVED3[31];
        uint32_t RESERVED4[64];
   __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
 }  NVIC_Type;
 /*@} end of group CMSIS_NVIC */
 /** \ingroup  CMSIS_core_register
     \defgroup CMSIS_SCB     System Control Block (SCB)
     \brief      Type definitions for the System Control Block Registers
   @{
  */
 /** \brief  Structure type to access the System Control Block (SCB).
  */
 typedef struct
+{
   __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
   __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
 #if (__VTOR_PRESENT == 1)
   __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
 #else
        uint32_t RESERVED0;
 #endif
   __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
   __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
   __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
        uint32_t RESERVED1;
   __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
   __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
 } SCB_Type;
 /* SCB CPUID Register Definitions */
 #define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
 #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
 #define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
 #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
 #define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
 #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
 #define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
 #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
 #define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
 #define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
 /* SCB Interrupt Control State Register Definitions */
 #define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
 #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
 #define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
 #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
 #define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
 #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
 #define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
 #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
 #define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
 #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
 #define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
 #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
 #define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
 #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
 #define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
 #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
 #define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
 #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
 #if (__VTOR_PRESENT == 1)
 /* SCB Interrupt Control State Register Definitions */
 #define SCB_VTOR_TBLOFF_Pos                 8                                             /*!< SCB VTOR: TBLOFF Position */
 #define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
 #endif
 /* SCB Application Interrupt and Reset Control Register Definitions */
 #define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
 #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
 #define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
 #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
 #define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
 #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
 #define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
 #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
 #define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
 #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
 /* SCB System Control Register Definitions */
 #define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
 #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
 #define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
 #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
 #define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
 #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
 /* SCB Configuration Control Register Definitions */
 #define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
 #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
 #define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
 #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
 /* SCB System Handler Control and State Register Definitions */
 #define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
 #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
 /*@} end of group CMSIS_SCB */
 /** \ingroup  CMSIS_core_register
     \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
     \brief      Type definitions for the System Timer Registers.
   @{
  */
 /** \brief  Structure type to access the System Timer (SysTick).
  */
 typedef struct
+{
   __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
   __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
   __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
   __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
 } SysTick_Type;
 /* SysTick Control / Status Register Definitions */
 #define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
 #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
 #define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
 #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
 #define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
 #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
 #define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
 #define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
 /* SysTick Reload Register Definitions */
 #define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
 #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
 /* SysTick Current Register Definitions */
 #define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
 #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
 /* SysTick Calibration Register Definitions */
 #define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
 #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
 #define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
 #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
 #define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
 #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
 /*@} end of group CMSIS_SysTick */
 #if (__MPU_PRESENT == 1)
 /** \ingroup  CMSIS_core_register
     \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
     \brief      Type definitions for the Memory Protection Unit (MPU)
   @{
  */
 /** \brief  Structure type to access the Memory Protection Unit (MPU).
  */
 typedef struct
+{
   __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
   __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
   __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
   __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
   __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
 } MPU_Type;
 /* MPU Type Register */
 #define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
 #define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
 #define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
 #define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
 #define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
 #define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
 /* MPU Control Register */
 #define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
 #define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
 #define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
 #define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
 #define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
 #define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
 /* MPU Region Number Register */
 #define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
 #define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
 /* MPU Region Base Address Register */
 #define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
 #define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
 #define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
 #define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
 #define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
 #define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
 /* MPU Region Attribute and Size Register */
 #define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
 #define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
 #define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
 #define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
 #define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
 #define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
 #define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
 #define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
 #define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
 #define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
 #define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
 #define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
 #define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
 #define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
 #define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
 #define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
 #define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
 #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
 #define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
 #define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
 /*@} end of group CMSIS_MPU */
 #endif
 /** \ingroup  CMSIS_core_register
     \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
     \brief      Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
                 are only accessible over DAP and not via processor. Therefore
                 they are not covered by the Cortex-M0 header file.
   @{
  */
 /*@} end of group CMSIS_CoreDebug */
 /** \ingroup    CMSIS_core_register
     \defgroup   CMSIS_core_base     Core Definitions
     \brief      Definitions for base addresses, unions, and structures.
   @{
  */
 /* Memory mapping of Cortex-M0+ Hardware */
 #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
 #define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
 #define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
 #define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
 #define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
 #define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
 #define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
 #if (__MPU_PRESENT == 1)
   #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
   #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
 #endif
 /*@} */
 /*******************************************************************************
  *                Hardware Abstraction Layer
   Core Function Interface contains:
   - Core NVIC Functions
   - Core SysTick Functions
   - Core Register Access Functions
  ******************************************************************************/
 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
 */
 /* ##########################   NVIC functions  #################################### */
 /** \ingroup  CMSIS_Core_FunctionInterface
     \defgroup CMSIS_Core_NVICFunctions NVIC Functions
     \brief      Functions that manage interrupts and exceptions via the NVIC.
     @{
  */
 /* Interrupt Priorities are WORD accessible only under ARMv6M                   */
 /* The following MACROS handle generation of the register offset and byte masks */
 #define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
 #define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
 #define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
 /** \brief  Enable External Interrupt
     The function enables a device-specific interrupt in the NVIC interrupt controller.
     \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
   NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
 /** \brief  Disable External Interrupt
     The function disables a device-specific interrupt in the NVIC interrupt controller.
     \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
   NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
 /** \brief  Get Pending Interrupt
     The function reads the pending register in the NVIC and returns the pending bit
     for the specified interrupt.
     \param [in]      IRQn  Interrupt number.
     \return             0  Interrupt status is not pending.
     \return             1  Interrupt status is pending.
  */
 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
   return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
 /** \brief  Set Pending Interrupt
     The function sets the pending bit of an external interrupt.
     \param [in]      IRQn  Interrupt number. Value cannot be negative.
  */
 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
   NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
 /** \brief  Clear Pending Interrupt
     The function clears the pending bit of an external interrupt.
     \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
   NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
 /** \brief  Set Interrupt Priority
     The function sets the priority of an interrupt.
     \note The priority cannot be set for every core interrupt.
     \param [in]      IRQn  Interrupt number.
     \param [in]  priority  Priority to set.
  */
 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
   if(IRQn < 0) {
     SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
         (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
   else {
     NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
         (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
 /** \brief  Get Interrupt Priority
     The function reads the priority of an interrupt. The interrupt
     number can be positive to specify an external (device specific)
     interrupt, or negative to specify an internal (core) interrupt.
     \param [in]   IRQn  Interrupt number.
     \return             Interrupt Priority. Value is aligned automatically to the implemented
                         priority bits of the microcontroller.
  */
 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
   if(IRQn < 0) {
     return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
   else {
     return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
 /** \brief  System Reset
     The function initiates a system reset request to reset the MCU.
  */
 __STATIC_INLINE void NVIC_SystemReset(void)
+{
   __DSB();                                                     /* Ensure all outstanding memory accesses included
                                                                   buffered write are completed before reset */
   SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
                  SCB_AIRCR_SYSRESETREQ_Msk);
   __DSB();                                                     /* Ensure completion of memory access */
   while(1);                                                    /* wait until reset */
+}
 /*@} end of CMSIS_Core_NVICFunctions */
 /* ##################################    SysTick function  ############################################ */
 /** \ingroup  CMSIS_Core_FunctionInterface
     \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
     \brief      Functions that configure the System.
   @{
  */
 #if (__Vendor_SysTickConfig == 0)
 /** \brief  System Tick Configuration
     The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
     Counter is in free running mode to generate periodic interrupts.
     \param [in]  ticks  Number of ticks between two interrupts.
     \return          0  Function succeeded.
     \return          1  Function failed.
     \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
     function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
     must contain a vendor-specific implementation of this function.
  */
 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
   if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
   SysTick->LOAD  = ticks - 1;                                  /* set reload register */
   NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
   SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
                    SysTick_CTRL_TICKINT_Msk   |
                    SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
   return (0);                                                  /* Function successful */
+}
 #endif
 /*@} end of CMSIS_Core_SysTickFunctions */
 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
 #endif /* __CMSIS_GENERIC */
 #ifdef __cplusplus
+}
 #endif

libraries/CMSIS/Include/core_cm3.h

➞

Show inline comments

@@ new file 100644 @@
 /**************************************************************************//**
  * @file     core_cm3.h
  * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
  * @version  V3.20
  * @date     25. February 2013
+ *
  * @note
+ *
  ******************************************************************************/
 /* Copyright (c) 2009 - 2013 ARM LIMITED
    All rights reserved.
    Redistribution and use in source and binary forms, with or without
    modification, are permitted provided that the following conditions are met:
    - Redistributions of source code must retain the above copyright
      notice, this list of conditions and the following disclaimer.
    - Redistributions in binary form must reproduce the above copyright
      notice, this list of conditions and the following disclaimer in the
      documentation and/or other materials provided with the distribution.
    - Neither the name of ARM nor the names of its contributors may be used
      to endorse or promote products derived from this software without
      specific prior written permission.
+   *
    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
    IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
    ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
    LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
    INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
    CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
    POSSIBILITY OF SUCH DAMAGE.
    ---------------------------------------------------------------------------*/
 #if defined ( __ICCARM__ )
  #pragma system_include  /* treat file as system include file for MISRA check */
 #endif
 #ifdef __cplusplus
  extern "C" {
 #endif
 #ifndef __CORE_CM3_H_GENERIC
 #define __CORE_CM3_H_GENERIC
 /** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
   CMSIS violates the following MISRA-C:2004 rules:
    \li Required Rule 8.5, object/function definition in header file.<br>
      Function definitions in header files are used to allow 'inlining'.
    \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
      Unions are used for effective representation of core registers.
    \li Advisory Rule 19.7, Function-like macro defined.<br>
      Function-like macros are used to allow more efficient code.
  */
 /*******************************************************************************
  *                 CMSIS definitions
  ******************************************************************************/
 /** \ingroup Cortex_M3
   @{
  */
 /*  CMSIS CM3 definitions */
 #define __CM3_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
 #define __CM3_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version    */
 #define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | \
                                     __CM3_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
 #define __CORTEX_M                (0x03)                                   /*!< Cortex-M Core                    */
 #if   defined ( __CC_ARM )
   #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
   #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
   #define __STATIC_INLINE  static __inline
 #elif defined ( __ICCARM__ )
   #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
   #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
   #define __STATIC_INLINE  static inline
 #elif defined ( __TMS470__ )
   #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
   #define __STATIC_INLINE  static inline
 #elif defined ( __GNUC__ )
   #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
   #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
   #define __STATIC_INLINE  static inline
 #elif defined ( __TASKING__ )
   #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
   #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
   #define __STATIC_INLINE  static inline
 #endif
 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
 */
 #define __FPU_USED       0
 #if defined ( __CC_ARM )
   #if defined __TARGET_FPU_VFP
     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 #elif defined ( __ICCARM__ )
   #if defined __ARMVFP__
     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 #elif defined ( __TMS470__ )
   #if defined __TI__VFP_SUPPORT____
     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 #elif defined ( __GNUC__ )
   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 #elif defined ( __TASKING__ )
   #if defined __FPU_VFP__
     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 #endif
 #include <stdint.h>                      /* standard types definitions                      */
 #include <core_cmInstr.h>                /* Core Instruction Access                         */
 #include <core_cmFunc.h>                 /* Core Function Access                            */
 #endif /* __CORE_CM3_H_GENERIC */
 #ifndef __CMSIS_GENERIC
 #ifndef __CORE_CM3_H_DEPENDANT
 #define __CORE_CM3_H_DEPENDANT
 /* check device defines and use defaults */
 #if defined __CHECK_DEVICE_DEFINES
   #ifndef __CM3_REV
     #define __CM3_REV               0x0200
     #warning "__CM3_REV not defined in device header file; using default!"
   #endif
   #ifndef __MPU_PRESENT
     #define __MPU_PRESENT             0
     #warning "__MPU_PRESENT not defined in device header file; using default!"
   #endif
   #ifndef __NVIC_PRIO_BITS
     #define __NVIC_PRIO_BITS          4
     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
   #endif
   #ifndef __Vendor_SysTickConfig
     #define __Vendor_SysTickConfig    0
     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
   #endif
 #endif
 /* IO definitions (access restrictions to peripheral registers) */
 /**
     \defgroup CMSIS_glob_defs CMSIS Global Defines
     <strong>IO Type Qualifiers</strong> are used
     \li to specify the access to peripheral variables.
     \li for automatic generation of peripheral register debug information.
 */
 #ifdef __cplusplus
   #define   __I     volatile             /*!< Defines 'read only' permissions                 */
 #else
   #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
 #endif
 #define     __O     volatile             /*!< Defines 'write only' permissions                */
 #define     __IO    volatile             /*!< Defines 'read / write' permissions              */
 /*@} end of group Cortex_M3 */
 /*******************************************************************************
  *                 Register Abstraction
   Core Register contain:
   - Core Register
   - Core NVIC Register
   - Core SCB Register
   - Core SysTick Register
   - Core Debug Register
   - Core MPU Register
  ******************************************************************************/
 /** \defgroup CMSIS_core_register Defines and Type Definitions
     \brief Type definitions and defines for Cortex-M processor based devices.
 */
 /** \ingroup    CMSIS_core_register
     \defgroup   CMSIS_CORE  Status and Control Registers
     \brief  Core Register type definitions.
   @{
  */
 /** \brief  Union type to access the Application Program Status Register (APSR).
  */
 typedef union
+{
   struct
+  {
 #if (__CORTEX_M != 0x04)
     uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
 #else
     uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
     uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
 #endif
     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
   } b;                                   /*!< Structure used for bit  access                  */
   uint32_t w;                            /*!< Type      used for word access                  */
 } APSR_Type;
 /** \brief  Union type to access the Interrupt Program Status Register (IPSR).
  */
 typedef union
+{
   struct
+  {
     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
     uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
   } b;                                   /*!< Structure used for bit  access                  */
   uint32_t w;                            /*!< Type      used for word access                  */
 } IPSR_Type;
 /** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
  */
 typedef union
+{
   struct
+  {
     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
 #if (__CORTEX_M != 0x04)
     uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
 #else
     uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
     uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
 #endif
     uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
     uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
   } b;                                   /*!< Structure used for bit  access                  */
   uint32_t w;                            /*!< Type      used for word access                  */
 } xPSR_Type;
 /** \brief  Union type to access the Control Registers (CONTROL).
  */
 typedef union
+{
   struct
+  {
     uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
     uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
     uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
     uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
   } b;                                   /*!< Structure used for bit  access                  */
   uint32_t w;                            /*!< Type      used for word access                  */
 } CONTROL_Type;
 /*@} end of group CMSIS_CORE */
 /** \ingroup    CMSIS_core_register
     \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
     \brief      Type definitions for the NVIC Registers
   @{
  */
 /** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
  */
 typedef struct
+{
   __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
        uint32_t RESERVED0[24];
   __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
        uint32_t RSERVED1[24];
   __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
        uint32_t RESERVED2[24];
   __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
        uint32_t RESERVED3[24];
   __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
        uint32_t RESERVED4[56];
   __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
        uint32_t RESERVED5[644];
   __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
 }  NVIC_Type;
 /* Software Triggered Interrupt Register Definitions */
 #define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
 #define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
 /*@} end of group CMSIS_NVIC */
 /** \ingroup  CMSIS_core_register
     \defgroup CMSIS_SCB     System Control Block (SCB)
     \brief      Type definitions for the System Control Block Registers
   @{
  */
 /** \brief  Structure type to access the System Control Block (SCB).
  */
 typedef struct
+{
   __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
   __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
   __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
   __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
   __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
   __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
   __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
   __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
   __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
   __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
   __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
   __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
   __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
   __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
   __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
   __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
   __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
   __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
   __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
        uint32_t RESERVED0[5];
   __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
 } SCB_Type;
 /* SCB CPUID Register Definitions */
 #define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
 #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
 #define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
 #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
 #define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
 #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
 #define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
 #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
 #define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
 #define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
 /* SCB Interrupt Control State Register Definitions */
 #define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
 #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
 #define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
 #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
 #define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
 #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
 #define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
 #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
 #define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
 #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
 #define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
 #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
 #define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
 #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
 #define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
 #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
 #define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
 #define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
 #define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
 #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
 /* SCB Vector Table Offset Register Definitions */
 #if (__CM3_REV < 0x0201)                   /* core r2p1 */
 #define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
 #define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
 #define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
 #define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
 #else
 #define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
 #define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
 #endif
 /* SCB Application Interrupt and Reset Control Register Definitions */
 #define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
 #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
 #define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
 #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
 #define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
 #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
 #define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
 #define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
 #define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
 #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
 #define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
 #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
 #define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
 #define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
 /* SCB System Control Register Definitions */
 #define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
 #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
 #define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
 #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
 #define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
 #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
 /* SCB Configuration Control Register Definitions */
 #define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
 #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
 #define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
 #define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
 #define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
 #define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
 #define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
 #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
 #define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
 #define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
 #define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
 #define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
 /* SCB System Handler Control and State Register Definitions */
 #define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
 #define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
 #define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
 #define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
 #define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
 #define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
 #define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
 #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
 #define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
 #define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
 #define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
 #define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
 #define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
 #define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
 #define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
 #define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
 #define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
 #define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
 #define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
 #define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
 #define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
 #define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
 #define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
 #define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
 #define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
 #define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
 #define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
 #define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
 /* SCB Configurable Fault Status Registers Definitions */
 #define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
 #define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
 #define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
 #define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
 #define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
 #define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
 /* SCB Hard Fault Status Registers Definitions */
 #define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
 #define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
 #define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
 #define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
 #define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
 #define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
 /* SCB Debug Fault Status Register Definitions */
 #define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
 #define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
 #define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
 #define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
 #define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
 #define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
 #define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
 #define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
 #define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
 #define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
 /*@} end of group CMSIS_SCB */
 /** \ingroup  CMSIS_core_register
     \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
     \brief      Type definitions for the System Control and ID Register not in the SCB
   @{
  */
 /** \brief  Structure type to access the System Control and ID Register not in the SCB.
  */
 typedef struct
+{
        uint32_t RESERVED0[1];
   __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
   __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
 #else
        uint32_t RESERVED1[1];
 #endif
 } SCnSCB_Type;
 /* Interrupt Controller Type Register Definitions */
 #define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
 #define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
 /* Auxiliary Control Register Definitions */
 #define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
 #define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
 #define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
 #define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
 #define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
 #define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
 /*@} end of group CMSIS_SCnotSCB */
 /** \ingroup  CMSIS_core_register
     \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
     \brief      Type definitions for the System Timer Registers.
   @{
  */
 /** \brief  Structure type to access the System Timer (SysTick).
  */
 typedef struct
+{
   __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
   __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
   __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
   __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
 } SysTick_Type;
 /* SysTick Control / Status Register Definitions */
 #define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
 #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
 #define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
 #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
 #define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
 #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
 #define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
 #define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
 /* SysTick Reload Register Definitions */
 #define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
 #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
 /* SysTick Current Register Definitions */
 #define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
 #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
 /* SysTick Calibration Register Definitions */
 #define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
 #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
 #define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
 #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
 #define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
 #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
 /*@} end of group CMSIS_SysTick */
 /** \ingroup  CMSIS_core_register
     \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
     \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
   @{
  */
 /** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
  */
 typedef struct
+{
   __O  union
+  {
     __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
     __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
     __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
   }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
        uint32_t RESERVED0[864];
   __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
        uint32_t RESERVED1[15];
   __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
        uint32_t RESERVED2[15];
   __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
        uint32_t RESERVED3[29];
   __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
   __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
   __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
        uint32_t RESERVED4[43];
   __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
   __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
        uint32_t RESERVED5[6];
   __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
   __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
   __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
   __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
   __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
   __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
   __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
   __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
   __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
   __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
   __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
   __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
 } ITM_Type;
 /* ITM Trace Privilege Register Definitions */
 #define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
 #define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
 /* ITM Trace Control Register Definitions */
 #define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
 #define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
 #define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
 #define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
 #define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
 #define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
 #define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
 #define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
 #define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
 #define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
 #define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
 #define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
 #define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
 #define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
 #define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
 #define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
 #define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
 #define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
 /* ITM Integration Write Register Definitions */
 #define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
 #define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
 /* ITM Integration Read Register Definitions */
 #define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
 #define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
 /* ITM Integration Mode Control Register Definitions */
 #define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
 #define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
 /* ITM Lock Status Register Definitions */
 #define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
 #define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
 #define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
 #define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
 #define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
 #define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
 /*@}*/ /* end of group CMSIS_ITM */
 /** \ingroup  CMSIS_core_register
     \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
     \brief      Type definitions for the Data Watchpoint and Trace (DWT)
   @{
  */
 /** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
  */
 typedef struct
+{
   __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
   __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
   __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
   __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
   __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
   __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
   __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
   __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
   __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
   __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
   __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
        uint32_t RESERVED0[1];
   __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
   __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
   __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
        uint32_t RESERVED1[1];
   __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
   __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
   __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
        uint32_t RESERVED2[1];
   __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
   __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
   __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
 } DWT_Type;
 /* DWT Control Register Definitions */
 #define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
 #define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
 #define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
 #define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
 #define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
 #define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
 #define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
 #define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
 #define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
 #define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
 #define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
 #define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
 #define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
 #define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
 #define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
 #define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
 #define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
 #define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
 #define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
 #define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
 #define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
 #define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
 #define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
 #define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
 #define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
 #define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
 #define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
 #define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
 #define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
 #define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
 #define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
 #define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
 #define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
 #define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
 #define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
 #define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
 /* DWT CPI Count Register Definitions */
 #define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
 #define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
 /* DWT Exception Overhead Count Register Definitions */
 #define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
 #define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
 /* DWT Sleep Count Register Definitions */
 #define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
 #define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
 /* DWT LSU Count Register Definitions */
 #define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
 #define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
 /* DWT Folded-instruction Count Register Definitions */
 #define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
 #define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
 /* DWT Comparator Mask Register Definitions */
 #define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
 #define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
 /* DWT Comparator Function Register Definitions */
 #define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
 #define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
 #define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
 #define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
 #define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
 #define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
 #define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
 #define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
 #define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
 #define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
 #define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
 #define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
 #define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
 #define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
 #define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
 #define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
 #define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
 #define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
 /*@}*/ /* end of group CMSIS_DWT */
 /** \ingroup  CMSIS_core_register
     \defgroup CMSIS_TPI     Trace Port Interface (TPI)
     \brief      Type definitions for the Trace Port Interface (TPI)
   @{
  */
 /** \brief  Structure type to access the Trace Port Interface Register (TPI).
  */
 typedef struct
+{
   __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
   __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
        uint32_t RESERVED0[2];
   __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
        uint32_t RESERVED1[55];
   __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
        uint32_t RESERVED2[131];
   __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
   __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
   __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
        uint32_t RESERVED3[759];
   __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
   __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
   __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
        uint32_t RESERVED4[1];
   __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
   __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
   __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
        uint32_t RESERVED5[39];
   __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
   __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
        uint32_t RESERVED7[8];
   __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
   __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
 } TPI_Type;
 /* TPI Asynchronous Clock Prescaler Register Definitions */
 #define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
 #define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
 /* TPI Selected Pin Protocol Register Definitions */
 #define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
 #define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
 /* TPI Formatter and Flush Status Register Definitions */
 #define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
 #define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
 #define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
 #define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
 #define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
 #define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
 #define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
 #define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
 /* TPI Formatter and Flush Control Register Definitions */
 #define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
 #define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
 #define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
 #define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
 /* TPI TRIGGER Register Definitions */
 #define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
 #define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
 /* TPI Integration ETM Data Register Definitions (FIFO0) */
 #define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
 #define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
 #define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
 #define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
 #define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
 #define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
 #define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
 #define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
 #define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
 #define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
 #define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
 #define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
 #define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
 #define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
 /* TPI ITATBCTR2 Register Definitions */
 #define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
 #define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
 /* TPI Integration ITM Data Register Definitions (FIFO1) */
 #define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
 #define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
 #define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
 #define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
 #define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
 #define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
 #define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
 #define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
 #define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
 #define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
 #define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
 #define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
 #define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
 #define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
 /* TPI ITATBCTR0 Register Definitions */
 #define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
 #define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
 /* TPI Integration Mode Control Register Definitions */
 #define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
 #define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
 /* TPI DEVID Register Definitions */
 #define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
 #define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
 #define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
 #define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
 #define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
 #define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
 #define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
 #define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
 #define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
 #define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
 #define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
 #define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
 /* TPI DEVTYPE Register Definitions */
 #define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
 #define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
 #define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
 #define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
 /*@}*/ /* end of group CMSIS_TPI */
 #if (__MPU_PRESENT == 1)
 /** \ingroup  CMSIS_core_register
     \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
     \brief      Type definitions for the Memory Protection Unit (MPU)
   @{
  */
 /** \brief  Structure type to access the Memory Protection Unit (MPU).
  */
 typedef struct
+{
   __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
   __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
   __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
   __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
   __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
   __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
   __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
   __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
   __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
   __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
   __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
 } MPU_Type;
 /* MPU Type Register */
 #define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
 #define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
 #define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
 #define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
 #define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
 #define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
 /* MPU Control Register */
 #define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
 #define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
 #define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
 #define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
 #define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
 #define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
 /* MPU Region Number Register */
 #define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
 #define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
 /* MPU Region Base Address Register */
 #define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
 #define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
 #define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
 #define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
 #define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
 #define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
 /* MPU Region Attribute and Size Register */
 #define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
 #define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
 #define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
 #define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
 #define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
 #define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
 #define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
 #define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
 #define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
 #define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
 #define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
 #define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
 #define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
 #define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
 #define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
 #define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
 #define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
 #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
 #define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
 #define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
 /*@} end of group CMSIS_MPU */
 #endif
 /** \ingroup  CMSIS_core_register
     \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
     \brief      Type definitions for the Core Debug Registers
   @{
  */
 /** \brief  Structure type to access the Core Debug Register (CoreDebug).
  */
 typedef struct
+{
   __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
   __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
   __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
   __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
 } CoreDebug_Type;
 /* Debug Halting Control and Status Register */
 #define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
 #define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
 #define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
 #define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
 #define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
 #define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
 #define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
 #define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
 #define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
 #define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
 #define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
 #define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
 #define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
 #define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
 #define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
 #define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
 #define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
 #define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
 #define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
 #define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
 /* Debug Core Register Selector Register */
 #define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
 #define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
 #define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
 #define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
 /* Debug Exception and Monitor Control Register */
 #define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
 #define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
 #define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
 #define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
 #define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
 #define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
 #define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
 #define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
 #define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
 #define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
 #define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
 #define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
 #define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
 #define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
 #define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
 #define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
 #define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
 #define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
 #define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
 #define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
 #define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
 #define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
 #define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
 #define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
 #define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
 #define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
 /*@} end of group CMSIS_CoreDebug */
 /** \ingroup    CMSIS_core_register
     \defgroup   CMSIS_core_base     Core Definitions
     \brief      Definitions for base addresses, unions, and structures.
   @{
  */
 /* Memory mapping of Cortex-M3 Hardware */
 #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
 #define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
 #define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
 #define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
 #define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
 #define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
 #define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
 #define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
 #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
 #define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
 #define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
 #define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
 #define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
 #define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
 #define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
 #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
 #if (__MPU_PRESENT == 1)
   #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
   #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
 #endif
 /*@} */
 /*******************************************************************************
  *                Hardware Abstraction Layer
   Core Function Interface contains:
   - Core NVIC Functions
   - Core SysTick Functions
   - Core Debug Functions
   - Core Register Access Functions
  ******************************************************************************/
 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
 */
 /* ##########################   NVIC functions  #################################### */
 /** \ingroup  CMSIS_Core_FunctionInterface
     \defgroup CMSIS_Core_NVICFunctions NVIC Functions
     \brief      Functions that manage interrupts and exceptions via the NVIC.
     @{
  */
 /** \brief  Set Priority Grouping
   The function sets the priority grouping field using the required unlock sequence.
   The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
   Only values from 0..7 are used.
   In case of a conflict between priority grouping and available
   priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
     \param [in]      PriorityGroup  Priority grouping field.
  */
 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
   uint32_t reg_value;
   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
   reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
   reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
   reg_value  =  (reg_value                                 |
                 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
                 (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
   SCB->AIRCR =  reg_value;
+}
 /** \brief  Get Priority Grouping
   The function reads the priority grouping field from the NVIC Interrupt Controller.
     \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
  */
 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
   return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
 /** \brief  Enable External Interrupt
     The function enables a device-specific interrupt in the NVIC interrupt controller.
     \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
   NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
 /** \brief  Disable External Interrupt
     The function disables a device-specific interrupt in the NVIC interrupt controller.
     \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
   NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
 /** \brief  Get Pending Interrupt
     The function reads the pending register in the NVIC and returns the pending bit
     for the specified interrupt.
     \param [in]      IRQn  Interrupt number.
     \return             0  Interrupt status is not pending.
     \return             1  Interrupt status is pending.
  */
 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
   return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
 /** \brief  Set Pending Interrupt
     The function sets the pending bit of an external interrupt.
     \param [in]      IRQn  Interrupt number. Value cannot be negative.
  */
 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
   NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
 /** \brief  Clear Pending Interrupt
     The function clears the pending bit of an external interrupt.
     \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
   NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
 /** \brief  Get Active Interrupt
     The function reads the active register in NVIC and returns the active bit.
     \param [in]      IRQn  Interrupt number.
     \return             0  Interrupt status is not active.
     \return             1  Interrupt status is active.
  */
 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
   return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
 /** \brief  Set Interrupt Priority
     The function sets the priority of an interrupt.
     \note The priority cannot be set for every core interrupt.
     \param [in]      IRQn  Interrupt number.
     \param [in]  priority  Priority to set.
  */
 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
   if(IRQn < 0) {
     SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
   else {
     NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
 /** \brief  Get Interrupt Priority
     The function reads the priority of an interrupt. The interrupt
     number can be positive to specify an external (device specific)
     interrupt, or negative to specify an internal (core) interrupt.
     \param [in]   IRQn  Interrupt number.
     \return             Interrupt Priority. Value is aligned automatically to the implemented
                         priority bits of the microcontroller.
  */
 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
   if(IRQn < 0) {
     return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
   else {
     return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
 /** \brief  Encode Priority
     The function encodes the priority for an interrupt with the given priority group,
     preemptive priority value, and subpriority value.
     In case of a conflict between priority grouping and available
     priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
     \param [in]     PriorityGroup  Used priority group.
     \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
     \param [in]       SubPriority  Subpriority value (starting from 0).
     \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
  */
 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
   uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
   uint32_t PreemptPriorityBits;
   uint32_t SubPriorityBits;
   PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
   SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
   return (
            ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
            ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
          );
+}
 /** \brief  Decode Priority
     The function decodes an interrupt priority value with a given priority group to
     preemptive priority value and subpriority value.
     In case of a conflict between priority grouping and available
     priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
     \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
     \param [in]     PriorityGroup  Used priority group.
     \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
     \param [out]     pSubPriority  Subpriority value (starting from 0).
  */
 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
   uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
   uint32_t PreemptPriorityBits;
   uint32_t SubPriorityBits;
   PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
   SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
   *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
   *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
 /** \brief  System Reset
     The function initiates a system reset request to reset the MCU.
  */
 __STATIC_INLINE void NVIC_SystemReset(void)
+{
   __DSB();                                                     /* Ensure all outstanding memory accesses included
                                                                   buffered write are completed before reset */
   SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
                  (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
                  SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
   __DSB();                                                     /* Ensure completion of memory access */
   while(1);                                                    /* wait until reset */
+}
 /*@} end of CMSIS_Core_NVICFunctions */
 /* ##################################    SysTick function  ############################################ */
 /** \ingroup  CMSIS_Core_FunctionInterface
     \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
     \brief      Functions that configure the System.
   @{
  */
 #if (__Vendor_SysTickConfig == 0)
 /** \brief  System Tick Configuration
     The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
     Counter is in free running mode to generate periodic interrupts.
     \param [in]  ticks  Number of ticks between two interrupts.
     \return          0  Function succeeded.
     \return          1  Function failed.
     \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
     function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
     must contain a vendor-specific implementation of this function.
  */
 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
   if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
   SysTick->LOAD  = ticks - 1;                                  /* set reload register */
   NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
   SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
                    SysTick_CTRL_TICKINT_Msk   |
                    SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
   return (0);                                                  /* Function successful */
+}
 #endif
 /*@} end of CMSIS_Core_SysTickFunctions */
 /* ##################################### Debug In/Output function ########################################### */
 /** \ingroup  CMSIS_Core_FunctionInterface
     \defgroup CMSIS_core_DebugFunctions ITM Functions
     \brief   Functions that access the ITM debug interface.
   @{
  */
 extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
 #define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
 /** \brief  ITM Send Character
     The function transmits a character via the ITM channel 0, and
     \li Just returns when no debugger is connected that has booked the output.
     \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
     \param [in]     ch  Character to transmit.
     \returns            Character to transmit.
  */
 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
   if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
       (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
     while (ITM->PORT[0].u32 == 0);
     ITM->PORT[0].u8 = (uint8_t) ch;
+  }
   return (ch);
+}
 /** \brief  ITM Receive Character
     The function inputs a character via the external variable \ref ITM_RxBuffer.
     \return             Received character.
     \return         -1  No character pending.
  */
 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
   int32_t ch = -1;                           /* no character available */
   if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
     ch = ITM_RxBuffer;
     ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
   return (ch);
+}
 /** \brief  ITM Check Character
     The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
     \return          0  No character available.
     \return          1  Character available.
  */
 __STATIC_INLINE int32_t ITM_CheckChar (void) {
   if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
     return (0);                                 /* no character available */
   } else {
     return (1);                                 /*    character available */
+  }
+}
 /*@} end of CMSIS_core_DebugFunctions */
 #endif /* __CORE_CM3_H_DEPENDANT */
 #endif /* __CMSIS_GENERIC */
 #ifdef __cplusplus
+}
 #endif

libraries/CMSIS/Include/core_cm4.h

➞

Show inline comments

@@ new file 100644 @@
 /**************************************************************************//**
  * @file     core_cm4.h
  * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
  * @version  V3.20
  * @date     25. February 2013
+ *
  * @note
+ *
  ******************************************************************************/
 /* Copyright (c) 2009 - 2013 ARM LIMITED
    All rights reserved.
    Redistribution and use in source and binary forms, with or without
    modification, are permitted provided that the following conditions are met:
    - Redistributions of source code must retain the above copyright
      notice, this list of conditions and the following disclaimer.
    - Redistributions in binary form must reproduce the above copyright
      notice, this list of conditions and the following disclaimer in the
      documentation and/or other materials provided with the distribution.
    - Neither the name of ARM nor the names of its contributors may be used
      to endorse or promote products derived from this software without
      specific prior written permission.
+   *
    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
    IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
    ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
    LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
    INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
    CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
    POSSIBILITY OF SUCH DAMAGE.
    ---------------------------------------------------------------------------*/
 #if defined ( __ICCARM__ )
  #pragma system_include  /* treat file as system include file for MISRA check */
 #endif
 #ifdef __cplusplus
  extern "C" {
 #endif
 #ifndef __CORE_CM4_H_GENERIC
 #define __CORE_CM4_H_GENERIC
 /** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
   CMSIS violates the following MISRA-C:2004 rules:
    \li Required Rule 8.5, object/function definition in header file.<br>
      Function definitions in header files are used to allow 'inlining'.
    \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
      Unions are used for effective representation of core registers.
    \li Advisory Rule 19.7, Function-like macro defined.<br>
      Function-like macros are used to allow more efficient code.
  */
 /*******************************************************************************
  *                 CMSIS definitions
  ******************************************************************************/
 /** \ingroup Cortex_M4
   @{
  */
 /*  CMSIS CM4 definitions */
 #define __CM4_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
 #define __CM4_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version    */
 #define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | \
                                     __CM4_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
 #define __CORTEX_M                (0x04)                                   /*!< Cortex-M Core                    */
 #if   defined ( __CC_ARM )
   #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
   #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
   #define __STATIC_INLINE  static __inline
 #elif defined ( __ICCARM__ )
   #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
   #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
   #define __STATIC_INLINE  static inline
 #elif defined ( __TMS470__ )
   #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
   #define __STATIC_INLINE  static inline
 #elif defined ( __GNUC__ )
   #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
   #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
   #define __STATIC_INLINE  static inline
 #elif defined ( __TASKING__ )
   #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
   #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
   #define __STATIC_INLINE  static inline
 #endif
 /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
 */
 #if defined ( __CC_ARM )
   #if defined __TARGET_FPU_VFP
     #if (__FPU_PRESENT == 1)
       #define __FPU_USED       1
     #else
       #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
       #define __FPU_USED       0
     #endif
   #else
     #define __FPU_USED         0
   #endif
 #elif defined ( __ICCARM__ )
   #if defined __ARMVFP__
     #if (__FPU_PRESENT == 1)
       #define __FPU_USED       1
     #else
       #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
       #define __FPU_USED       0
     #endif
   #else
     #define __FPU_USED         0
   #endif
 #elif defined ( __TMS470__ )
   #if defined __TI_VFP_SUPPORT__
     #if (__FPU_PRESENT == 1)
       #define __FPU_USED       1
     #else
       #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
       #define __FPU_USED       0
     #endif
   #else
     #define __FPU_USED         0
   #endif
 #elif defined ( __GNUC__ )
   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
     #if (__FPU_PRESENT == 1)
       #define __FPU_USED       1
     #else
       #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
       #define __FPU_USED       0
     #endif
   #else
     #define __FPU_USED         0
   #endif
 #elif defined ( __TASKING__ )
   #if defined __FPU_VFP__
     #if (__FPU_PRESENT == 1)
       #define __FPU_USED       1
     #else
       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
       #define __FPU_USED       0
     #endif
   #else
     #define __FPU_USED         0
   #endif
 #endif
 #include <stdint.h>                      /* standard types definitions                      */
 #include <core_cmInstr.h>                /* Core Instruction Access                         */
 #include <core_cmFunc.h>                 /* Core Function Access                            */
 #include <core_cm4_simd.h>               /* Compiler specific SIMD Intrinsics               */
 #endif /* __CORE_CM4_H_GENERIC */
 #ifndef __CMSIS_GENERIC
 #ifndef __CORE_CM4_H_DEPENDANT
 #define __CORE_CM4_H_DEPENDANT
 /* check device defines and use defaults */
 #if defined __CHECK_DEVICE_DEFINES
   #ifndef __CM4_REV
     #define __CM4_REV               0x0000
     #warning "__CM4_REV not defined in device header file; using default!"
   #endif
   #ifndef __FPU_PRESENT
     #define __FPU_PRESENT             0
     #warning "__FPU_PRESENT not defined in device header file; using default!"
   #endif
   #ifndef __MPU_PRESENT
     #define __MPU_PRESENT             0
     #warning "__MPU_PRESENT not defined in device header file; using default!"
   #endif
   #ifndef __NVIC_PRIO_BITS
     #define __NVIC_PRIO_BITS          4
     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
   #endif
   #ifndef __Vendor_SysTickConfig
     #define __Vendor_SysTickConfig    0
     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
   #endif
 #endif
 /* IO definitions (access restrictions to peripheral registers) */
 /**
     \defgroup CMSIS_glob_defs CMSIS Global Defines
     <strong>IO Type Qualifiers</strong> are used
     \li to specify the access to peripheral variables.
     \li for automatic generation of peripheral register debug information.
 */
 #ifdef __cplusplus
   #define   __I     volatile             /*!< Defines 'read only' permissions                 */
 #else
   #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
 #endif
 #define     __O     volatile             /*!< Defines 'write only' permissions                */
 #define     __IO    volatile             /*!< Defines 'read / write' permissions              */
 /*@} end of group Cortex_M4 */
 /*******************************************************************************
  *                 Register Abstraction
   Core Register contain:
   - Core Register
   - Core NVIC Register
   - Core SCB Register
   - Core SysTick Register
   - Core Debug Register
   - Core MPU Register
   - Core FPU Register
  ******************************************************************************/
 /** \defgroup CMSIS_core_register Defines and Type Definitions
     \brief Type definitions and defines for Cortex-M processor based devices.
 */
 /** \ingroup    CMSIS_core_register
     \defgroup   CMSIS_CORE  Status and Control Registers
     \brief  Core Register type definitions.
   @{
  */
 /** \brief  Union type to access the Application Program Status Register (APSR).
  */
 typedef union
+{
   struct
+  {
 #if (__CORTEX_M != 0x04)
     uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
 #else
     uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
     uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
 #endif
     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
   } b;                                   /*!< Structure used for bit  access                  */
   uint32_t w;                            /*!< Type      used for word access                  */
 } APSR_Type;
 /** \brief  Union type to access the Interrupt Program Status Register (IPSR).
  */
 typedef union
+{
   struct
+  {
     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
     uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
   } b;                                   /*!< Structure used for bit  access                  */
   uint32_t w;                            /*!< Type      used for word access                  */
 } IPSR_Type;
 /** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
  */
 typedef union
+{
   struct
+  {
     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
 #if (__CORTEX_M != 0x04)
     uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
 #else
     uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
     uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
 #endif
     uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
     uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
   } b;                                   /*!< Structure used for bit  access                  */
   uint32_t w;                            /*!< Type      used for word access                  */
 } xPSR_Type;
 /** \brief  Union type to access the Control Registers (CONTROL).
  */
 typedef union
+{
   struct
+  {
     uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
     uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
     uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
     uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
   } b;                                   /*!< Structure used for bit  access                  */
   uint32_t w;                            /*!< Type      used for word access                  */
 } CONTROL_Type;
 /*@} end of group CMSIS_CORE */
 /** \ingroup    CMSIS_core_register
     \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
     \brief      Type definitions for the NVIC Registers
   @{
  */
 /** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
  */
 typedef struct
+{
   __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
        uint32_t RESERVED0[24];
   __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
        uint32_t RSERVED1[24];
   __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
        uint32_t RESERVED2[24];
   __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
        uint32_t RESERVED3[24];
   __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
        uint32_t RESERVED4[56];
   __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
        uint32_t RESERVED5[644];
   __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
 }  NVIC_Type;
 /* Software Triggered Interrupt Register Definitions */
 #define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
 #define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
 /*@} end of group CMSIS_NVIC */
 /** \ingroup  CMSIS_core_register
     \defgroup CMSIS_SCB     System Control Block (SCB)
     \brief      Type definitions for the System Control Block Registers
   @{
  */
 /** \brief  Structure type to access the System Control Block (SCB).
  */
 typedef struct
+{
   __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
   __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
   __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
   __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
   __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
   __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
   __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
   __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
   __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
   __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
   __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
   __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
   __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
   __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
   __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
   __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
   __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
   __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
   __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
        uint32_t RESERVED0[5];
   __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
 } SCB_Type;
 /* SCB CPUID Register Definitions */
 #define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
 #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
 #define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
 #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
 #define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
 #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
 #define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
 #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
 #define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
 #define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
 /* SCB Interrupt Control State Register Definitions */
 #define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
 #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
 #define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
 #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
 #define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
 #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
 #define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
 #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
 #define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
 #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
 #define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
 #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
 #define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
 #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
 #define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
 #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
 #define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
 #define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
 #define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
 #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
 /* SCB Vector Table Offset Register Definitions */
 #define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
 #define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
 /* SCB Application Interrupt and Reset Control Register Definitions */
 #define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
 #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
 #define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
 #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
 #define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
 #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
 #define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
 #define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
 #define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
 #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
 #define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
 #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
 #define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
 #define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
 /* SCB System Control Register Definitions */
 #define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
 #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
 #define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
 #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
 #define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
 #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
 /* SCB Configuration Control Register Definitions */
 #define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
 #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
 #define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
 #define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
 #define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
 #define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
 #define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
 #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
 #define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
 #define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
 #define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
 #define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
 /* SCB System Handler Control and State Register Definitions */
 #define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
 #define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
 #define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
 #define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
 #define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
 #define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
 #define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
 #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
 #define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
 #define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
 #define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
 #define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
 #define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
 #define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
 #define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
 #define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
 #define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
 #define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
 #define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
 #define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
 #define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
 #define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
 #define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
 #define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
 #define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
 #define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
 #define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
 #define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
 /* SCB Configurable Fault Status Registers Definitions */
 #define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
 #define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
 #define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
 #define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
 #define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
 #define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
 /* SCB Hard Fault Status Registers Definitions */
 #define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
 #define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
 #define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
 #define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
 #define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
 #define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
 /* SCB Debug Fault Status Register Definitions */
 #define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
 #define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
 #define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
 #define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
 #define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
 #define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
 #define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
 #define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
 #define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
 #define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
 /*@} end of group CMSIS_SCB */
 /** \ingroup  CMSIS_core_register
     \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
     \brief      Type definitions for the System Control and ID Register not in the SCB
   @{
  */
 /** \brief  Structure type to access the System Control and ID Register not in the SCB.
  */
 typedef struct
+{
        uint32_t RESERVED0[1];
   __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
   __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
 } SCnSCB_Type;
 /* Interrupt Controller Type Register Definitions */
 #define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
 #define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
 /* Auxiliary Control Register Definitions */
 #define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */
 #define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
 #define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */
 #define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
 #define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
 #define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
 #define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
 #define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
 #define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
 #define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
 /*@} end of group CMSIS_SCnotSCB */
 /** \ingroup  CMSIS_core_register
     \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
     \brief      Type definitions for the System Timer Registers.
   @{
  */
 /** \brief  Structure type to access the System Timer (SysTick).
  */
 typedef struct
+{
   __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
   __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
   __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
   __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
 } SysTick_Type;
 /* SysTick Control / Status Register Definitions */
 #define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
 #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
 #define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
 #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
 #define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
 #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
 #define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
 #define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
 /* SysTick Reload Register Definitions */
 #define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
 #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
 /* SysTick Current Register Definitions */
 #define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
 #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
 /* SysTick Calibration Register Definitions */
 #define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
 #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
 #define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
 #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
 #define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
 #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
 /*@} end of group CMSIS_SysTick */
 /** \ingroup  CMSIS_core_register
     \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
     \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
   @{
  */
 /** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
  */
 typedef struct
+{
   __O  union
+  {
     __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
     __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
     __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
   }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
        uint32_t RESERVED0[864];
   __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
        uint32_t RESERVED1[15];
   __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
        uint32_t RESERVED2[15];
   __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
        uint32_t RESERVED3[29];
   __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
   __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
   __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
        uint32_t RESERVED4[43];
   __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
   __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
        uint32_t RESERVED5[6];
   __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
   __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
   __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
   __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
   __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
   __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
   __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
   __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
   __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
   __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
   __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
   __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
 } ITM_Type;
 /* ITM Trace Privilege Register Definitions */
 #define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
 #define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
 /* ITM Trace Control Register Definitions */
 #define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
 #define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
 #define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
 #define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
 #define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
 #define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
 #define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
 #define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
 #define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
 #define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
 #define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
 #define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
 #define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
 #define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
 #define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
 #define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
 #define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
 #define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
 /* ITM Integration Write Register Definitions */
 #define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
 #define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
 /* ITM Integration Read Register Definitions */
 #define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
 #define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
 /* ITM Integration Mode Control Register Definitions */
 #define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
 #define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
 /* ITM Lock Status Register Definitions */
 #define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
 #define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
 #define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
 #define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
 #define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
 #define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
 /*@}*/ /* end of group CMSIS_ITM */
 /** \ingroup  CMSIS_core_register
     \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
     \brief      Type definitions for the Data Watchpoint and Trace (DWT)
   @{
  */
 /** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
  */
 typedef struct
+{
   __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
   __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
   __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
   __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
   __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
   __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
   __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
   __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
   __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
   __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
   __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
        uint32_t RESERVED0[1];
   __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
   __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
   __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
        uint32_t RESERVED1[1];
   __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
   __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
   __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
        uint32_t RESERVED2[1];
   __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
   __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
   __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
 } DWT_Type;
 /* DWT Control Register Definitions */
 #define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
 #define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
 #define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
 #define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
 #define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
 #define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
 #define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
 #define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
 #define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
 #define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
 #define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
 #define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
 #define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
 #define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
 #define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
 #define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
 #define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
 #define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
 #define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
 #define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
 #define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
 #define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
 #define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
 #define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
 #define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
 #define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
 #define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
 #define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
 #define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
 #define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
 #define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
 #define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
 #define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
 #define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
 #define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
 #define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
 /* DWT CPI Count Register Definitions */
 #define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
 #define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
 /* DWT Exception Overhead Count Register Definitions */
 #define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
 #define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
 /* DWT Sleep Count Register Definitions */
 #define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
 #define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
 /* DWT LSU Count Register Definitions */
 #define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
 #define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
 /* DWT Folded-instruction Count Register Definitions */
 #define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
 #define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
 /* DWT Comparator Mask Register Definitions */
 #define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
 #define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
 /* DWT Comparator Function Register Definitions */
 #define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
 #define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
 #define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
 #define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
 #define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
 #define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
 #define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
 #define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
 #define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
 #define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
 #define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
 #define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
 #define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
 #define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
 #define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
 #define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
 #define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
 #define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
 /*@}*/ /* end of group CMSIS_DWT */
 /** \ingroup  CMSIS_core_register
     \defgroup CMSIS_TPI     Trace Port Interface (TPI)
     \brief      Type definitions for the Trace Port Interface (TPI)
   @{
  */
 /** \brief  Structure type to access the Trace Port Interface Register (TPI).
  */
 typedef struct
+{
   __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
   __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
        uint32_t RESERVED0[2];
   __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
        uint32_t RESERVED1[55];
   __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
        uint32_t RESERVED2[131];
   __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
   __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
   __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
        uint32_t RESERVED3[759];
   __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
   __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
   __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
        uint32_t RESERVED4[1];
   __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
   __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
   __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
        uint32_t RESERVED5[39];
   __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
   __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
        uint32_t RESERVED7[8];
   __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
   __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
 } TPI_Type;
 /* TPI Asynchronous Clock Prescaler Register Definitions */
 #define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
 #define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
 /* TPI Selected Pin Protocol Register Definitions */
 #define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
 #define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
 /* TPI Formatter and Flush Status Register Definitions */
 #define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
 #define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
 #define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
 #define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
 #define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
 #define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
 #define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
 #define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
 /* TPI Formatter and Flush Control Register Definitions */
 #define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
 #define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
 #define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
 #define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
 /* TPI TRIGGER Register Definitions */
 #define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
 #define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
 /* TPI Integration ETM Data Register Definitions (FIFO0) */
 #define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
 #define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
 #define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
 #define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
 #define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
 #define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
 #define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
 #define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
 #define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
 #define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
 #define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
 #define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
 #define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
 #define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
 /* TPI ITATBCTR2 Register Definitions */
 #define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
 #define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
 /* TPI Integration ITM Data Register Definitions (FIFO1) */
 #define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
 #define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
 #define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
 #define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
 #define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
 #define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
 #define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
 #define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
 #define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
 #define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
 #define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
 #define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
 #define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
 #define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
 /* TPI ITATBCTR0 Register Definitions */
 #define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
 #define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
 /* TPI Integration Mode Control Register Definitions */
 #define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
 #define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
 /* TPI DEVID Register Definitions */
 #define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
 #define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
 #define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
 #define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
 #define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
 #define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
 #define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
 #define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
 #define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
 #define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
 #define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
 #define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
 /* TPI DEVTYPE Register Definitions */
 #define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
 #define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
 #define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
 #define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
 /*@}*/ /* end of group CMSIS_TPI */
 #if (__MPU_PRESENT == 1)
 /** \ingroup  CMSIS_core_register
     \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
     \brief      Type definitions for the Memory Protection Unit (MPU)
   @{
  */
 /** \brief  Structure type to access the Memory Protection Unit (MPU).
  */
 typedef struct
+{
   __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
   __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
   __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
   __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
   __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
   __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
   __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
   __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
   __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
   __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
   __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
 } MPU_Type;
 /* MPU Type Register */
 #define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
 #define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
 #define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
 #define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
 #define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
 #define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
 /* MPU Control Register */
 #define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
 #define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
 #define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
 #define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
 #define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
 #define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
 /* MPU Region Number Register */
 #define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
 #define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
 /* MPU Region Base Address Register */
 #define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
 #define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
 #define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
 #define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
 #define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
 #define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
 /* MPU Region Attribute and Size Register */
 #define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
 #define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
 #define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
 #define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
 #define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
 #define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
 #define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
 #define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
 #define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
 #define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
 #define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
 #define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
 #define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
 #define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
 #define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
 #define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
 #define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
 #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
 #define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
 #define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
 /*@} end of group CMSIS_MPU */
 #endif
 #if (__FPU_PRESENT == 1)
 /** \ingroup  CMSIS_core_register
     \defgroup CMSIS_FPU     Floating Point Unit (FPU)
     \brief      Type definitions for the Floating Point Unit (FPU)
   @{
  */
 /** \brief  Structure type to access the Floating Point Unit (FPU).
  */
 typedef struct
+{
        uint32_t RESERVED0[1];
   __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
   __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
   __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
   __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
   __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
 } FPU_Type;
 /* Floating-Point Context Control Register */
 #define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
 #define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
 #define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
 #define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
 #define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
 #define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
 #define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
 #define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
 #define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
 #define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
 #define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
 #define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
 #define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
 #define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
 #define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
 #define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
 #define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
 #define FPU_FPCCR_LSPACT_Msk               (1UL << FPU_FPCCR_LSPACT_Pos)                  /*!< FPCCR: Lazy state preservation active bit Mask */
 /* Floating-Point Context Address Register */
 #define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
 #define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
 /* Floating-Point Default Status Control Register */
 #define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
 #define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
 #define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
 #define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
 #define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
 #define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
 #define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
 #define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
 /* Media and FP Feature Register 0 */
 #define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
 #define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
 #define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
 #define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
 #define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
 #define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
 #define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
 #define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
 #define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
 #define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
 #define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
 #define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
 #define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
 #define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
 #define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
 #define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)      /*!< MVFR0: A_SIMD registers bits Mask */
 /* Media and FP Feature Register 1 */
 #define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
 #define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
 #define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
 #define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
 #define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
 #define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
 #define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
 #define FPU_MVFR1_FtZ_mode_Msk             (0xFUL << FPU_MVFR1_FtZ_mode_Pos)              /*!< MVFR1: FtZ mode bits Mask */
 /*@} end of group CMSIS_FPU */
 #endif
 /** \ingroup  CMSIS_core_register
     \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
     \brief      Type definitions for the Core Debug Registers
   @{
  */
 /** \brief  Structure type to access the Core Debug Register (CoreDebug).
  */
 typedef struct
+{
   __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
   __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
   __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
   __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
 } CoreDebug_Type;
 /* Debug Halting Control and Status Register */
 #define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
 #define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
 #define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
 #define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
 #define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
 #define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
 #define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
 #define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
 #define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
 #define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
 #define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
 #define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
 #define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
 #define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
 #define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
 #define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
 #define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
 #define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
 #define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
 #define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
 /* Debug Core Register Selector Register */
 #define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
 #define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
 #define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
 #define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
 /* Debug Exception and Monitor Control Register */
 #define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
 #define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
 #define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
 #define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
 #define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
 #define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
 #define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
 #define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
 #define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
 #define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
 #define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
 #define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
 #define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
 #define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
 #define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
 #define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
 #define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
 #define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
 #define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
 #define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
 #define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
 #define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
 #define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
 #define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
 #define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
 #define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
 /*@} end of group CMSIS_CoreDebug */
 /** \ingroup    CMSIS_core_register
     \defgroup   CMSIS_core_base     Core Definitions
     \brief      Definitions for base addresses, unions, and structures.
   @{
  */
 /* Memory mapping of Cortex-M4 Hardware */
 #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
 #define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
 #define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
 #define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
 #define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
 #define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
 #define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
 #define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
 #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
 #define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
 #define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
 #define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
 #define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
 #define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
 #define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
 #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
 #if (__MPU_PRESENT == 1)
   #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
   #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
 #endif
 #if (__FPU_PRESENT == 1)
   #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
   #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
 #endif
 /*@} */
 /*******************************************************************************
  *                Hardware Abstraction Layer
   Core Function Interface contains:
   - Core NVIC Functions
   - Core SysTick Functions
   - Core Debug Functions
   - Core Register Access Functions
  ******************************************************************************/
 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
 */
 /* ##########################   NVIC functions  #################################### */
 /** \ingroup  CMSIS_Core_FunctionInterface
     \defgroup CMSIS_Core_NVICFunctions NVIC Functions
     \brief      Functions that manage interrupts and exceptions via the NVIC.
     @{
  */
 /** \brief  Set Priority Grouping
   The function sets the priority grouping field using the required unlock sequence.
   The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
   Only values from 0..7 are used.
   In case of a conflict between priority grouping and available
   priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
     \param [in]      PriorityGroup  Priority grouping field.
  */
 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
   uint32_t reg_value;
   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
   reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
   reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
   reg_value  =  (reg_value                                 |
                 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
                 (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
   SCB->AIRCR =  reg_value;
+}
 /** \brief  Get Priority Grouping
   The function reads the priority grouping field from the NVIC Interrupt Controller.
     \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
  */
 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
   return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
 /** \brief  Enable External Interrupt
     The function enables a device-specific interrupt in the NVIC interrupt controller.
     \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
 /*  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  enable interrupt */
   NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+}
 /** \brief  Disable External Interrupt
     The function disables a device-specific interrupt in the NVIC interrupt controller.
     \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
   NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
 /** \brief  Get Pending Interrupt
     The function reads the pending register in the NVIC and returns the pending bit
     for the specified interrupt.
     \param [in]      IRQn  Interrupt number.
     \return             0  Interrupt status is not pending.
     \return             1  Interrupt status is pending.
  */
 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
   return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
 /** \brief  Set Pending Interrupt
     The function sets the pending bit of an external interrupt.
     \param [in]      IRQn  Interrupt number. Value cannot be negative.
  */
 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
   NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
 /** \brief  Clear Pending Interrupt
     The function clears the pending bit of an external interrupt.
     \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
   NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
 /** \brief  Get Active Interrupt
     The function reads the active register in NVIC and returns the active bit.
     \param [in]      IRQn  Interrupt number.
     \return             0  Interrupt status is not active.
     \return             1  Interrupt status is active.
  */
 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
   return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
 /** \brief  Set Interrupt Priority
     The function sets the priority of an interrupt.
     \note The priority cannot be set for every core interrupt.
     \param [in]      IRQn  Interrupt number.
     \param [in]  priority  Priority to set.
  */
 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
   if(IRQn < 0) {
     SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
   else {
     NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
 /** \brief  Get Interrupt Priority
     The function reads the priority of an interrupt. The interrupt
     number can be positive to specify an external (device specific)
     interrupt, or negative to specify an internal (core) interrupt.
     \param [in]   IRQn  Interrupt number.
     \return             Interrupt Priority. Value is aligned automatically to the implemented
                         priority bits of the microcontroller.
  */
 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
   if(IRQn < 0) {
     return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
   else {
     return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
 /** \brief  Encode Priority
     The function encodes the priority for an interrupt with the given priority group,
     preemptive priority value, and subpriority value.
     In case of a conflict between priority grouping and available
     priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
     \param [in]     PriorityGroup  Used priority group.
     \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
     \param [in]       SubPriority  Subpriority value (starting from 0).
     \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
  */
 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
   uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
   uint32_t PreemptPriorityBits;
   uint32_t SubPriorityBits;
   PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
   SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
   return (
            ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
            ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
          );
+}
 /** \brief  Decode Priority
     The function decodes an interrupt priority value with a given priority group to
     preemptive priority value and subpriority value.
     In case of a conflict between priority grouping and available
     priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
     \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
     \param [in]     PriorityGroup  Used priority group.
     \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
     \param [out]     pSubPriority  Subpriority value (starting from 0).
  */
 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
   uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
   uint32_t PreemptPriorityBits;
   uint32_t SubPriorityBits;
   PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
   SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
   *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
   *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
 /** \brief  System Reset
     The function initiates a system reset request to reset the MCU.
  */
 __STATIC_INLINE void NVIC_SystemReset(void)
+{
   __DSB();                                                     /* Ensure all outstanding memory accesses included
                                                                   buffered write are completed before reset */
   SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
                  (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
                  SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
   __DSB();                                                     /* Ensure completion of memory access */
   while(1);                                                    /* wait until reset */
+}
 /*@} end of CMSIS_Core_NVICFunctions */
 /* ##################################    SysTick function  ############################################ */
 /** \ingroup  CMSIS_Core_FunctionInterface
     \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
     \brief      Functions that configure the System.
   @{
  */
 #if (__Vendor_SysTickConfig == 0)
 /** \brief  System Tick Configuration
     The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
     Counter is in free running mode to generate periodic interrupts.
     \param [in]  ticks  Number of ticks between two interrupts.
     \return          0  Function succeeded.
     \return          1  Function failed.
     \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
     function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
     must contain a vendor-specific implementation of this function.
  */
 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
   if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
   SysTick->LOAD  = ticks - 1;                                  /* set reload register */
   NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
   SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
                    SysTick_CTRL_TICKINT_Msk   |
                    SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
   return (0);                                                  /* Function successful */
+}
 #endif
 /*@} end of CMSIS_Core_SysTickFunctions */
 /* ##################################### Debug In/Output function ########################################### */
 /** \ingroup  CMSIS_Core_FunctionInterface
     \defgroup CMSIS_core_DebugFunctions ITM Functions
     \brief   Functions that access the ITM debug interface.
   @{
  */
 extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
 #define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
 /** \brief  ITM Send Character
     The function transmits a character via the ITM channel 0, and
     \li Just returns when no debugger is connected that has booked the output.
     \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
     \param [in]     ch  Character to transmit.
     \returns            Character to transmit.
  */
 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
   if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
       (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
     while (ITM->PORT[0].u32 == 0);
     ITM->PORT[0].u8 = (uint8_t) ch;
+  }
   return (ch);
+}
 /** \brief  ITM Receive Character
     The function inputs a character via the external variable \ref ITM_RxBuffer.
     \return             Received character.
     \return         -1  No character pending.
  */
 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
   int32_t ch = -1;                           /* no character available */
   if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
     ch = ITM_RxBuffer;
     ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
   return (ch);
+}
 /** \brief  ITM Check Character
     The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
     \return          0  No character available.
     \return          1  Character available.
  */
 __STATIC_INLINE int32_t ITM_CheckChar (void) {
   if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
     return (0);                                 /* no character available */
   } else {
     return (1);                                 /*    character available */
+  }
+}
 /*@} end of CMSIS_core_DebugFunctions */
 #endif /* __CORE_CM4_H_DEPENDANT */
 #endif /* __CMSIS_GENERIC */
 #ifdef __cplusplus
+}
 #endif

libraries/CMSIS/Include/core_cm4_simd.h

➞

Show inline comments

@@ new file 100644 @@
 /**************************************************************************//**
  * @file     core_cm4_simd.h
  * @brief    CMSIS Cortex-M4 SIMD Header File
  * @version  V3.20
  * @date     25. February 2013
+ *
  * @note
+ *
  ******************************************************************************/
 /* Copyright (c) 2009 - 2013 ARM LIMITED
    All rights reserved.
    Redistribution and use in source and binary forms, with or without
    modification, are permitted provided that the following conditions are met:
    - Redistributions of source code must retain the above copyright
      notice, this list of conditions and the following disclaimer.
    - Redistributions in binary form must reproduce the above copyright
      notice, this list of conditions and the following disclaimer in the
      documentation and/or other materials provided with the distribution.
    - Neither the name of ARM nor the names of its contributors may be used
      to endorse or promote products derived from this software without
      specific prior written permission.
+   *
    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
    IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
    ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
    LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
    INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
    CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
    POSSIBILITY OF SUCH DAMAGE.
    ---------------------------------------------------------------------------*/
 #ifdef __cplusplus
  extern "C" {
 #endif
 #ifndef __CORE_CM4_SIMD_H
 #define __CORE_CM4_SIMD_H
 /*******************************************************************************
  *                Hardware Abstraction Layer
  ******************************************************************************/
 /* ###################  Compiler specific Intrinsics  ########################### */
 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
   Access to dedicated SIMD instructions
   @{
 */
 #if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
 /* ARM armcc specific functions */
 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
 #define __SADD8                           __sadd8
 #define __QADD8                           __qadd8
 #define __SHADD8                          __shadd8
 #define __UADD8                           __uadd8
 #define __UQADD8                          __uqadd8
 #define __UHADD8                          __uhadd8
 #define __SSUB8                           __ssub8
 #define __QSUB8                           __qsub8
 #define __SHSUB8                          __shsub8
 #define __USUB8                           __usub8
 #define __UQSUB8                          __uqsub8
 #define __UHSUB8                          __uhsub8
 #define __SADD16                          __sadd16
 #define __QADD16                          __qadd16
 #define __SHADD16                         __shadd16
 #define __UADD16                          __uadd16
 #define __UQADD16                         __uqadd16
 #define __UHADD16                         __uhadd16
 #define __SSUB16                          __ssub16
 #define __QSUB16                          __qsub16
 #define __SHSUB16                         __shsub16
 #define __USUB16                          __usub16
 #define __UQSUB16                         __uqsub16
 #define __UHSUB16                         __uhsub16
 #define __SASX                            __sasx
 #define __QASX                            __qasx
 #define __SHASX                           __shasx
 #define __UASX                            __uasx
 #define __UQASX                           __uqasx
 #define __UHASX                           __uhasx
 #define __SSAX                            __ssax
 #define __QSAX                            __qsax
 #define __SHSAX                           __shsax
 #define __USAX                            __usax
 #define __UQSAX                           __uqsax
 #define __UHSAX                           __uhsax
 #define __USAD8                           __usad8
 #define __USADA8                          __usada8
 #define __SSAT16                          __ssat16
 #define __USAT16                          __usat16
 #define __UXTB16                          __uxtb16
 #define __UXTAB16                         __uxtab16
 #define __SXTB16                          __sxtb16
 #define __SXTAB16                         __sxtab16
 #define __SMUAD                           __smuad
 #define __SMUADX                          __smuadx
 #define __SMLAD                           __smlad
 #define __SMLADX                          __smladx
 #define __SMLALD                          __smlald
 #define __SMLALDX                         __smlaldx
 #define __SMUSD                           __smusd
 #define __SMUSDX                          __smusdx
 #define __SMLSD                           __smlsd
 #define __SMLSDX                          __smlsdx
 #define __SMLSLD                          __smlsld
 #define __SMLSLDX                         __smlsldx
 #define __SEL                             __sel
 #define __QADD                            __qadd
 #define __QSUB                            __qsub
 #define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
                                            ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
 #define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
                                            ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
 #define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
                                                       ((int64_t)(ARG3) << 32)      ) >> 32))
 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
 /* IAR iccarm specific functions */
 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
 #include <cmsis_iar.h>
 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
 /* TI CCS specific functions */
 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
 #include <cmsis_ccs.h>
 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
 /* GNU gcc specific functions */
 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
   uint32_t result;
   __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
   return(result);
+}
 #define __SSAT16(ARG1,ARG2) \
 ({                          \
   uint32_t __RES, __ARG1 = (ARG1); \
   __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
   __RES; \
  })
 #define __USAT16(ARG1,ARG2) \
 ({                          \
   uint32_t __RES, __ARG1 = (ARG1); \
   __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
   __RES; \
  })
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
   uint32_t result;
   __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
   uint32_t result;
   __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
   uint32_t result;
   __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
   uint32_t result;
   __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
   return(result);
+}
 #define __SMLALD(ARG1,ARG2,ARG3) \
 ({ \
   uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
   __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
   (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
  })
 #define __SMLALDX(ARG1,ARG2,ARG3) \
 ({ \
   uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
   __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
   (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
  })
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
   uint32_t result;
   __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
   uint32_t result;
   __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
   return(result);
+}
 #define __SMLSLD(ARG1,ARG2,ARG3) \
 ({ \
   uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
   __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
   (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
  })
 #define __SMLSLDX(ARG1,ARG2,ARG3) \
 ({ \
   uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
   __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
   (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
  })
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
   uint32_t result;
   __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
   return(result);
+}
 #define __PKHBT(ARG1,ARG2,ARG3) \
 ({                          \
   uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
   __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
   __RES; \
  })
 #define __PKHTB(ARG1,ARG2,ARG3) \
 ({                          \
   uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
   if (ARG3 == 0) \
     __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
   else \
     __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
   __RES; \
  })
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
  int32_t result;
  __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
  return(result);
+}
 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
 /* TASKING carm specific functions */
 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
 /* not yet supported */
 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
 #endif
 /*@} end of group CMSIS_SIMD_intrinsics */
 #endif /* __CORE_CM4_SIMD_H */
 #ifdef __cplusplus
+}
 #endif

libraries/CMSIS/Include/core_cmFunc.h

➞

Show inline comments

@@ new file 100644 @@
 /**************************************************************************//**
  * @file     core_cmFunc.h
  * @brief    CMSIS Cortex-M Core Function Access Header File
  * @version  V3.20
  * @date     25. February 2013
+ *
  * @note
+ *
  ******************************************************************************/
 /* Copyright (c) 2009 - 2013 ARM LIMITED
    All rights reserved.
    Redistribution and use in source and binary forms, with or without
    modification, are permitted provided that the following conditions are met:
    - Redistributions of source code must retain the above copyright
      notice, this list of conditions and the following disclaimer.
    - Redistributions in binary form must reproduce the above copyright
      notice, this list of conditions and the following disclaimer in the
      documentation and/or other materials provided with the distribution.
    - Neither the name of ARM nor the names of its contributors may be used
      to endorse or promote products derived from this software without
      specific prior written permission.
+   *
    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
    IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
    ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
    LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
    INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
    CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
    POSSIBILITY OF SUCH DAMAGE.
    ---------------------------------------------------------------------------*/
 #ifndef __CORE_CMFUNC_H
 #define __CORE_CMFUNC_H
 /* ###########################  Core Function Access  ########################### */
 /** \ingroup  CMSIS_Core_FunctionInterface
     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
   @{
  */
 #if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
 /* ARM armcc specific functions */
 #if (__ARMCC_VERSION < 400677)
   #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
 #endif
 /* intrinsic void __enable_irq();     */
 /* intrinsic void __disable_irq();    */
 /** \brief  Get Control Register
     This function returns the content of the Control Register.
     \return               Control Register value
  */
 __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
   register uint32_t __regControl         __ASM("control");
   return(__regControl);
+}
 /** \brief  Set Control Register
     This function writes the given value to the Control Register.
     \param [in]    control  Control Register value to set
  */
 __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
   register uint32_t __regControl         __ASM("control");
   __regControl = control;
+}
 /** \brief  Get IPSR Register
     This function returns the content of the IPSR Register.
     \return               IPSR Register value
  */
 __STATIC_INLINE uint32_t __get_IPSR(void)
+{
   register uint32_t __regIPSR          __ASM("ipsr");
   return(__regIPSR);
+}
 /** \brief  Get APSR Register
     This function returns the content of the APSR Register.
     \return               APSR Register value
  */
 __STATIC_INLINE uint32_t __get_APSR(void)
+{
   register uint32_t __regAPSR          __ASM("apsr");
   return(__regAPSR);
+}
 /** \brief  Get xPSR Register
     This function returns the content of the xPSR Register.
     \return               xPSR Register value
  */
 __STATIC_INLINE uint32_t __get_xPSR(void)
+{
   register uint32_t __regXPSR          __ASM("xpsr");
   return(__regXPSR);
+}
 /** \brief  Get Process Stack Pointer
     This function returns the current value of the Process Stack Pointer (PSP).
     \return               PSP Register value
  */
 __STATIC_INLINE uint32_t __get_PSP(void)
+{
   register uint32_t __regProcessStackPointer  __ASM("psp");
   return(__regProcessStackPointer);
+}
 /** \brief  Set Process Stack Pointer
     This function assigns the given value to the Process Stack Pointer (PSP).
     \param [in]    topOfProcStack  Process Stack Pointer value to set
  */
 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
   register uint32_t __regProcessStackPointer  __ASM("psp");
   __regProcessStackPointer = topOfProcStack;
+}
 /** \brief  Get Main Stack Pointer
     This function returns the current value of the Main Stack Pointer (MSP).
     \return               MSP Register value
  */
 __STATIC_INLINE uint32_t __get_MSP(void)
+{
   register uint32_t __regMainStackPointer     __ASM("msp");
   return(__regMainStackPointer);
+}
 /** \brief  Set Main Stack Pointer
     This function assigns the given value to the Main Stack Pointer (MSP).
     \param [in]    topOfMainStack  Main Stack Pointer value to set
  */
 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
   register uint32_t __regMainStackPointer     __ASM("msp");
   __regMainStackPointer = topOfMainStack;
+}
 /** \brief  Get Priority Mask
     This function returns the current state of the priority mask bit from the Priority Mask Register.
     \return               Priority Mask value
  */
 __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
   register uint32_t __regPriMask         __ASM("primask");
   return(__regPriMask);
+}
 /** \brief  Set Priority Mask
     This function assigns the given value to the Priority Mask Register.
     \param [in]    priMask  Priority Mask
  */
 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
   register uint32_t __regPriMask         __ASM("primask");
   __regPriMask = (priMask);
+}
 #if       (__CORTEX_M >= 0x03)
 /** \brief  Enable FIQ
     This function enables FIQ interrupts by clearing the F-bit in the CPSR.
     Can only be executed in Privileged modes.
  */
 #define __enable_fault_irq                __enable_fiq
 /** \brief  Disable FIQ
     This function disables FIQ interrupts by setting the F-bit in the CPSR.
     Can only be executed in Privileged modes.
  */
 #define __disable_fault_irq               __disable_fiq
 /** \brief  Get Base Priority
     This function returns the current value of the Base Priority register.
     \return               Base Priority register value
  */
 __STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
   register uint32_t __regBasePri         __ASM("basepri");
   return(__regBasePri);
+}
 /** \brief  Set Base Priority
     This function assigns the given value to the Base Priority register.
     \param [in]    basePri  Base Priority value to set
  */
 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
   register uint32_t __regBasePri         __ASM("basepri");
   __regBasePri = (basePri & 0xff);
+}
 /** \brief  Get Fault Mask
     This function returns the current value of the Fault Mask register.
     \return               Fault Mask register value
  */
 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
   register uint32_t __regFaultMask       __ASM("faultmask");
   return(__regFaultMask);
+}
 /** \brief  Set Fault Mask
     This function assigns the given value to the Fault Mask register.
     \param [in]    faultMask  Fault Mask value to set
  */
 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
   register uint32_t __regFaultMask       __ASM("faultmask");
   __regFaultMask = (faultMask & (uint32_t)1);
+}
 #endif /* (__CORTEX_M >= 0x03) */
 #if       (__CORTEX_M == 0x04)
 /** \brief  Get FPSCR
     This function returns the current value of the Floating Point Status/Control register.
     \return               Floating Point Status/Control register value
  */
 __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
   register uint32_t __regfpscr         __ASM("fpscr");
   return(__regfpscr);
 #else
    return(0);
 #endif
+}
 /** \brief  Set FPSCR
     This function assigns the given value to the Floating Point Status/Control register.
     \param [in]    fpscr  Floating Point Status/Control value to set
  */
 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
   register uint32_t __regfpscr         __ASM("fpscr");
   __regfpscr = (fpscr);
 #endif
+}
 #endif /* (__CORTEX_M == 0x04) */
 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
 /* IAR iccarm specific functions */
 #include <cmsis_iar.h>
 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
 /* TI CCS specific functions */
 #include <cmsis_ccs.h>
 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
 /* GNU gcc specific functions */
 /** \brief  Enable IRQ Interrupts
   This function enables IRQ interrupts by clearing the I-bit in the CPSR.
   Can only be executed in Privileged modes.
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
   __ASM volatile ("cpsie i" : : : "memory");
+}
 /** \brief  Disable IRQ Interrupts
   This function disables IRQ interrupts by setting the I-bit in the CPSR.
   Can only be executed in Privileged modes.
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
   __ASM volatile ("cpsid i" : : : "memory");
+}
 /** \brief  Get Control Register
     This function returns the content of the Control Register.
     \return               Control Register value
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
   uint32_t result;
   __ASM volatile ("MRS %0, control" : "=r" (result) );
   return(result);
+}
 /** \brief  Set Control Register
     This function writes the given value to the Control Register.
     \param [in]    control  Control Register value to set
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
   __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
 /** \brief  Get IPSR Register
     This function returns the content of the IPSR Register.
     \return               IPSR Register value
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
   uint32_t result;
   __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
   return(result);
+}
 /** \brief  Get APSR Register
     This function returns the content of the APSR Register.
     \return               APSR Register value
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
   uint32_t result;
   __ASM volatile ("MRS %0, apsr" : "=r" (result) );
   return(result);
+}
 /** \brief  Get xPSR Register
     This function returns the content of the xPSR Register.
     \return               xPSR Register value
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
   uint32_t result;
   __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
   return(result);
+}
 /** \brief  Get Process Stack Pointer
     This function returns the current value of the Process Stack Pointer (PSP).
     \return               PSP Register value
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
   register uint32_t result;
   __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
   return(result);
+}
 /** \brief  Set Process Stack Pointer
     This function assigns the given value to the Process Stack Pointer (PSP).
     \param [in]    topOfProcStack  Process Stack Pointer value to set
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
   __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
 /** \brief  Get Main Stack Pointer
     This function returns the current value of the Main Stack Pointer (MSP).
     \return               MSP Register value
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
   register uint32_t result;
   __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
   return(result);
+}
 /** \brief  Set Main Stack Pointer
     This function assigns the given value to the Main Stack Pointer (MSP).
     \param [in]    topOfMainStack  Main Stack Pointer value to set
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
   __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
 /** \brief  Get Priority Mask
     This function returns the current state of the priority mask bit from the Priority Mask Register.
     \return               Priority Mask value
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
   uint32_t result;
   __ASM volatile ("MRS %0, primask" : "=r" (result) );
   return(result);
+}
 /** \brief  Set Priority Mask
     This function assigns the given value to the Priority Mask Register.
     \param [in]    priMask  Priority Mask
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
   __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
 #if       (__CORTEX_M >= 0x03)
 /** \brief  Enable FIQ
     This function enables FIQ interrupts by clearing the F-bit in the CPSR.
     Can only be executed in Privileged modes.
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
   __ASM volatile ("cpsie f" : : : "memory");
+}
 /** \brief  Disable FIQ
     This function disables FIQ interrupts by setting the F-bit in the CPSR.
     Can only be executed in Privileged modes.
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
   __ASM volatile ("cpsid f" : : : "memory");
+}
 /** \brief  Get Base Priority
     This function returns the current value of the Base Priority register.
     \return               Base Priority register value
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
   uint32_t result;
   __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
   return(result);
+}
 /** \brief  Set Base Priority
     This function assigns the given value to the Base Priority register.
     \param [in]    basePri  Base Priority value to set
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
   __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
 /** \brief  Get Fault Mask
     This function returns the current value of the Fault Mask register.
     \return               Fault Mask register value
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
   uint32_t result;
   __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
   return(result);
+}
 /** \brief  Set Fault Mask
     This function assigns the given value to the Fault Mask register.
     \param [in]    faultMask  Fault Mask value to set
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
   __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
 #endif /* (__CORTEX_M >= 0x03) */
 #if       (__CORTEX_M == 0x04)
 /** \brief  Get FPSCR
     This function returns the current value of the Floating Point Status/Control register.
     \return               Floating Point Status/Control register value
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
   uint32_t result;
   /* Empty asm statement works as a scheduling barrier */
   __ASM volatile ("");
   __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
   __ASM volatile ("");
   return(result);
 #else
    return(0);
 #endif
+}
 /** \brief  Set FPSCR
     This function assigns the given value to the Floating Point Status/Control register.
     \param [in]    fpscr  Floating Point Status/Control value to set
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
   /* Empty asm statement works as a scheduling barrier */
   __ASM volatile ("");
   __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
   __ASM volatile ("");
 #endif
+}
 #endif /* (__CORTEX_M == 0x04) */
 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
 /* TASKING carm specific functions */
 /*
  * The CMSIS functions have been implemented as intrinsics in the compiler.
  * Please use "carm -?i" to get an up to date list of all instrinsics,
  * Including the CMSIS ones.
  */
 #endif
 /*@} end of CMSIS_Core_RegAccFunctions */
 #endif /* __CORE_CMFUNC_H */

libraries/CMSIS/Include/core_cmInstr.h

➞

Show inline comments

@@ new file 100644 @@
 /**************************************************************************//**
  * @file     core_cmInstr.h
  * @brief    CMSIS Cortex-M Core Instruction Access Header File
  * @version  V3.20
  * @date     05. March 2013
+ *
  * @note
+ *
  ******************************************************************************/
 /* Copyright (c) 2009 - 2013 ARM LIMITED
    All rights reserved.
    Redistribution and use in source and binary forms, with or without
    modification, are permitted provided that the following conditions are met:
    - Redistributions of source code must retain the above copyright
      notice, this list of conditions and the following disclaimer.
    - Redistributions in binary form must reproduce the above copyright
      notice, this list of conditions and the following disclaimer in the
      documentation and/or other materials provided with the distribution.
    - Neither the name of ARM nor the names of its contributors may be used
      to endorse or promote products derived from this software without
      specific prior written permission.
+   *
    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
    IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
    ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
    LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
    INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
    CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
    POSSIBILITY OF SUCH DAMAGE.
    ---------------------------------------------------------------------------*/
 #ifndef __CORE_CMINSTR_H
 #define __CORE_CMINSTR_H
 /* ##########################  Core Instruction Access  ######################### */
 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
   Access to dedicated instructions
   @{
 */
 #if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
 /* ARM armcc specific functions */
 #if (__ARMCC_VERSION < 400677)
   #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
 #endif
 /** \brief  No Operation
     No Operation does nothing. This instruction can be used for code alignment purposes.
  */
 #define __NOP                             __nop
 /** \brief  Wait For Interrupt
     Wait For Interrupt is a hint instruction that suspends execution
     until one of a number of events occurs.
  */
 #define __WFI                             __wfi
 /** \brief  Wait For Event
     Wait For Event is a hint instruction that permits the processor to enter
     a low-power state until one of a number of events occurs.
  */
 #define __WFE                             __wfe
 /** \brief  Send Event
     Send Event is a hint instruction. It causes an event to be signaled to the CPU.
  */
 #define __SEV                             __sev
 /** \brief  Instruction Synchronization Barrier
     Instruction Synchronization Barrier flushes the pipeline in the processor,
     so that all instructions following the ISB are fetched from cache or
     memory, after the instruction has been completed.
  */
 #define __ISB()                           __isb(0xF)
 /** \brief  Data Synchronization Barrier
     This function acts as a special kind of Data Memory Barrier.
     It completes when all explicit memory accesses before this instruction complete.
  */
 #define __DSB()                           __dsb(0xF)
 /** \brief  Data Memory Barrier
     This function ensures the apparent order of the explicit memory operations before
     and after the instruction, without ensuring their completion.
  */
 #define __DMB()                           __dmb(0xF)
 /** \brief  Reverse byte order (32 bit)
     This function reverses the byte order in integer value.
     \param [in]    value  Value to reverse
     \return               Reversed value
  */
 #define __REV                             __rev
 /** \brief  Reverse byte order (16 bit)
     This function reverses the byte order in two unsigned short values.
     \param [in]    value  Value to reverse
     \return               Reversed value
  */
 #ifndef __NO_EMBEDDED_ASM
 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
   rev16 r0, r0
   bx lr
+}
 #endif
 /** \brief  Reverse byte order in signed short value
     This function reverses the byte order in a signed short value with sign extension to integer.
     \param [in]    value  Value to reverse
     \return               Reversed value
  */
 #ifndef __NO_EMBEDDED_ASM
 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
   revsh r0, r0
   bx lr
+}
 #endif
 /** \brief  Rotate Right in unsigned value (32 bit)
     This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
     \param [in]    value  Value to rotate
     \param [in]    value  Number of Bits to rotate
     \return               Rotated value
  */
 #define __ROR                             __ror
 /** \brief  Breakpoint
     This function causes the processor to enter Debug state.
     Debug tools can use this to investigate system state when the instruction at a particular address is reached.
     \param [in]    value  is ignored by the processor.
                    If required, a debugger can use it to store additional information about the breakpoint.
  */
 #define __BKPT(value)                       __breakpoint(value)
 #if       (__CORTEX_M >= 0x03)
 /** \brief  Reverse bit order of value
     This function reverses the bit order of the given value.
     \param [in]    value  Value to reverse
     \return               Reversed value
  */
 #define __RBIT                            __rbit
 /** \brief  LDR Exclusive (8 bit)
     This function performs a exclusive LDR command for 8 bit value.
     \param [in]    ptr  Pointer to data
     \return             value of type uint8_t at (*ptr)
  */
 #define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
 /** \brief  LDR Exclusive (16 bit)
     This function performs a exclusive LDR command for 16 bit values.
     \param [in]    ptr  Pointer to data
     \return        value of type uint16_t at (*ptr)
  */
 #define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
 /** \brief  LDR Exclusive (32 bit)
     This function performs a exclusive LDR command for 32 bit values.
     \param [in]    ptr  Pointer to data
     \return        value of type uint32_t at (*ptr)
  */
 #define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
 /** \brief  STR Exclusive (8 bit)
     This function performs a exclusive STR command for 8 bit values.
     \param [in]  value  Value to store
     \param [in]    ptr  Pointer to location
     \return          0  Function succeeded
     \return          1  Function failed
  */
 #define __STREXB(value, ptr)              __strex(value, ptr)
 /** \brief  STR Exclusive (16 bit)
     This function performs a exclusive STR command for 16 bit values.
     \param [in]  value  Value to store
     \param [in]    ptr  Pointer to location
     \return          0  Function succeeded
     \return          1  Function failed
  */
 #define __STREXH(value, ptr)              __strex(value, ptr)
 /** \brief  STR Exclusive (32 bit)
     This function performs a exclusive STR command for 32 bit values.
     \param [in]  value  Value to store
     \param [in]    ptr  Pointer to location
     \return          0  Function succeeded
     \return          1  Function failed
  */
 #define __STREXW(value, ptr)              __strex(value, ptr)
 /** \brief  Remove the exclusive lock
     This function removes the exclusive lock which is created by LDREX.
  */
 #define __CLREX                           __clrex
 /** \brief  Signed Saturate
     This function saturates a signed value.
     \param [in]  value  Value to be saturated
     \param [in]    sat  Bit position to saturate to (1..32)
     \return             Saturated value
  */
 #define __SSAT                            __ssat
 /** \brief  Unsigned Saturate
     This function saturates an unsigned value.
     \param [in]  value  Value to be saturated
     \param [in]    sat  Bit position to saturate to (0..31)
     \return             Saturated value
  */
 #define __USAT                            __usat
 /** \brief  Count leading zeros
     This function counts the number of leading zeros of a data value.
     \param [in]  value  Value to count the leading zeros
     \return             number of leading zeros in value
  */
 #define __CLZ                             __clz
 #endif /* (__CORTEX_M >= 0x03) */
 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
 /* IAR iccarm specific functions */
 #include <cmsis_iar.h>
 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
 /* TI CCS specific functions */
 #include <cmsis_ccs.h>
 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
 /* GNU gcc specific functions */
 /* Define macros for porting to both thumb1 and thumb2.
  * For thumb1, use low register (r0-r7), specified by constrant "l"
  * Otherwise, use general registers, specified by constrant "r" */
 #if defined (__thumb__) && !defined (__thumb2__)
 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
 #define __CMSIS_GCC_USE_REG(r) "l" (r)
 #else
 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
 #define __CMSIS_GCC_USE_REG(r) "r" (r)
 #endif
 /** \brief  No Operation
     No Operation does nothing. This instruction can be used for code alignment purposes.
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
   __ASM volatile ("nop");
+}
 /** \brief  Wait For Interrupt
     Wait For Interrupt is a hint instruction that suspends execution
     until one of a number of events occurs.
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
   __ASM volatile ("wfi");
+}
 /** \brief  Wait For Event
     Wait For Event is a hint instruction that permits the processor to enter
     a low-power state until one of a number of events occurs.
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
   __ASM volatile ("wfe");
+}
 /** \brief  Send Event
     Send Event is a hint instruction. It causes an event to be signaled to the CPU.
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
   __ASM volatile ("sev");
+}
 /** \brief  Instruction Synchronization Barrier
     Instruction Synchronization Barrier flushes the pipeline in the processor,
     so that all instructions following the ISB are fetched from cache or
     memory, after the instruction has been completed.
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
   __ASM volatile ("isb");
+}
 /** \brief  Data Synchronization Barrier
     This function acts as a special kind of Data Memory Barrier.
     It completes when all explicit memory accesses before this instruction complete.
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
   __ASM volatile ("dsb");
+}
 /** \brief  Data Memory Barrier
     This function ensures the apparent order of the explicit memory operations before
     and after the instruction, without ensuring their completion.
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
   __ASM volatile ("dmb");
+}
 /** \brief  Reverse byte order (32 bit)
     This function reverses the byte order in integer value.
     \param [in]    value  Value to reverse
     \return               Reversed value
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
   return __builtin_bswap32(value);
 #else
   uint32_t result;
   __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
   return(result);
 #endif
+}
 /** \brief  Reverse byte order (16 bit)
     This function reverses the byte order in two unsigned short values.
     \param [in]    value  Value to reverse
     \return               Reversed value
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
   uint32_t result;
   __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
   return(result);
+}
 /** \brief  Reverse byte order in signed short value
     This function reverses the byte order in a signed short value with sign extension to integer.
     \param [in]    value  Value to reverse
     \return               Reversed value
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
   return (short)__builtin_bswap16(value);
 #else
   uint32_t result;
   __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
   return(result);
 #endif
+}
 /** \brief  Rotate Right in unsigned value (32 bit)
     This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
     \param [in]    value  Value to rotate
     \param [in]    value  Number of Bits to rotate
     \return               Rotated value
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
   return (op1 >> op2) | (op1 << (32 - op2));
+}
 /** \brief  Breakpoint
     This function causes the processor to enter Debug state.
     Debug tools can use this to investigate system state when the instruction at a particular address is reached.
     \param [in]    value  is ignored by the processor.
                    If required, a debugger can use it to store additional information about the breakpoint.
  */
 #define __BKPT(value)                       __ASM volatile ("bkpt "#value)
 #if       (__CORTEX_M >= 0x03)
 /** \brief  Reverse bit order of value
     This function reverses the bit order of the given value.
     \param [in]    value  Value to reverse
     \return               Reversed value
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
   uint32_t result;
    __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
    return(result);
+}
 /** \brief  LDR Exclusive (8 bit)
     This function performs a exclusive LDR command for 8 bit value.
     \param [in]    ptr  Pointer to data
     \return             value of type uint8_t at (*ptr)
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
     uint32_t result;
 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
    __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
 #else
     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
        accepted by assembler. So has to use following less efficient pattern.
     */
    __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
 #endif
    return(result);
+}
 /** \brief  LDR Exclusive (16 bit)
     This function performs a exclusive LDR command for 16 bit values.
     \param [in]    ptr  Pointer to data
     \return        value of type uint16_t at (*ptr)
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
     uint32_t result;
 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
    __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
 #else
     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
        accepted by assembler. So has to use following less efficient pattern.
     */
    __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
 #endif
    return(result);
+}
 /** \brief  LDR Exclusive (32 bit)
     This function performs a exclusive LDR command for 32 bit values.
     \param [in]    ptr  Pointer to data
     \return        value of type uint32_t at (*ptr)
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
     uint32_t result;
    __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
    return(result);
+}
 /** \brief  STR Exclusive (8 bit)
     This function performs a exclusive STR command for 8 bit values.
     \param [in]  value  Value to store
     \param [in]    ptr  Pointer to location
     \return          0  Function succeeded
     \return          1  Function failed
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
    uint32_t result;
    __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
    return(result);
+}
 /** \brief  STR Exclusive (16 bit)
     This function performs a exclusive STR command for 16 bit values.
     \param [in]  value  Value to store
     \param [in]    ptr  Pointer to location
     \return          0  Function succeeded
     \return          1  Function failed
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
    uint32_t result;
    __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
    return(result);
+}
 /** \brief  STR Exclusive (32 bit)
     This function performs a exclusive STR command for 32 bit values.
     \param [in]  value  Value to store
     \param [in]    ptr  Pointer to location
     \return          0  Function succeeded
     \return          1  Function failed
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
    uint32_t result;
    __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
    return(result);
+}
 /** \brief  Remove the exclusive lock
     This function removes the exclusive lock which is created by LDREX.
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
   __ASM volatile ("clrex" ::: "memory");
+}
 /** \brief  Signed Saturate
     This function saturates a signed value.
     \param [in]  value  Value to be saturated
     \param [in]    sat  Bit position to saturate to (1..32)
     \return             Saturated value
  */
 #define __SSAT(ARG1,ARG2) \
 ({                          \
   uint32_t __RES, __ARG1 = (ARG1); \
   __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
   __RES; \
  })
 /** \brief  Unsigned Saturate
     This function saturates an unsigned value.
     \param [in]  value  Value to be saturated
     \param [in]    sat  Bit position to saturate to (0..31)
     \return             Saturated value
  */
 #define __USAT(ARG1,ARG2) \
 ({                          \
   uint32_t __RES, __ARG1 = (ARG1); \
   __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
   __RES; \
  })
 /** \brief  Count leading zeros
     This function counts the number of leading zeros of a data value.
     \param [in]  value  Value to count the leading zeros
     \return             number of leading zeros in value
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
    uint32_t result;
   __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
   return(result);
+}
 #endif /* (__CORTEX_M >= 0x03) */
 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
 /* TASKING carm specific functions */
 /*
  * The CMSIS functions have been implemented as intrinsics in the compiler.
  * Please use "carm -?i" to get an up to date list of all intrinsics,
  * Including the CMSIS ones.
  */
 #endif
 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
 #endif /* __CORE_CMINSTR_H */

libraries/CMSIS/Include/core_sc000.h

➞

Show inline comments

@@ new file 100644 @@
 /**************************************************************************//**
  * @file     core_sc000.h
  * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
  * @version  V3.20
  * @date     25. February 2013
+ *
  * @note
+ *
  ******************************************************************************/
 /* Copyright (c) 2009 - 2013 ARM LIMITED
    All rights reserved.
    Redistribution and use in source and binary forms, with or without
    modification, are permitted provided that the following conditions are met:
    - Redistributions of source code must retain the above copyright
      notice, this list of conditions and the following disclaimer.
    - Redistributions in binary form must reproduce the above copyright
      notice, this list of conditions and the following disclaimer in the
      documentation and/or other materials provided with the distribution.
    - Neither the name of ARM nor the names of its contributors may be used
      to endorse or promote products derived from this software without
      specific prior written permission.
+   *
    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
    IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
    ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
    LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
    INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
    CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
    POSSIBILITY OF SUCH DAMAGE.
    ---------------------------------------------------------------------------*/
 #if defined ( __ICCARM__ )
  #pragma system_include  /* treat file as system include file for MISRA check */
 #endif
 #ifdef __cplusplus
  extern "C" {
 #endif
 #ifndef __CORE_SC000_H_GENERIC
 #define __CORE_SC000_H_GENERIC
 /** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
   CMSIS violates the following MISRA-C:2004 rules:
    \li Required Rule 8.5, object/function definition in header file.<br>
      Function definitions in header files are used to allow 'inlining'.
    \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
      Unions are used for effective representation of core registers.
    \li Advisory Rule 19.7, Function-like macro defined.<br>
      Function-like macros are used to allow more efficient code.
  */
 /*******************************************************************************
  *                 CMSIS definitions
  ******************************************************************************/
 /** \ingroup SC000
   @{
  */
 /*  CMSIS SC000 definitions */
 #define __SC000_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version */
 #define __SC000_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version  */
 #define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16) | \
                                       __SC000_CMSIS_VERSION_SUB          )   /*!< CMSIS HAL version number       */
 #define __CORTEX_SC                (0)                                       /*!< Cortex secure core             */
 #if   defined ( __CC_ARM )
   #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
   #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
   #define __STATIC_INLINE  static __inline
 #elif defined ( __ICCARM__ )
   #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
   #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
   #define __STATIC_INLINE  static inline
 #elif defined ( __GNUC__ )
   #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
   #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
   #define __STATIC_INLINE  static inline
 #elif defined ( __TASKING__ )
   #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
   #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
   #define __STATIC_INLINE  static inline
 #endif
 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
 */
 #define __FPU_USED       0
 #if defined ( __CC_ARM )
   #if defined __TARGET_FPU_VFP
     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 #elif defined ( __ICCARM__ )
   #if defined __ARMVFP__
     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 #elif defined ( __GNUC__ )
   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 #elif defined ( __TASKING__ )
   #if defined __FPU_VFP__
     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 #endif
 #include <stdint.h>                      /* standard types definitions                      */
 #include <core_cmInstr.h>                /* Core Instruction Access                         */
 #include <core_cmFunc.h>                 /* Core Function Access                            */
 #endif /* __CORE_SC000_H_GENERIC */
 #ifndef __CMSIS_GENERIC
 #ifndef __CORE_SC000_H_DEPENDANT
 #define __CORE_SC000_H_DEPENDANT
 /* check device defines and use defaults */
 #if defined __CHECK_DEVICE_DEFINES
   #ifndef __SC000_REV
     #define __SC000_REV             0x0000
     #warning "__SC000_REV not defined in device header file; using default!"
   #endif
   #ifndef __MPU_PRESENT
     #define __MPU_PRESENT             0
     #warning "__MPU_PRESENT not defined in device header file; using default!"
   #endif
   #ifndef __NVIC_PRIO_BITS
     #define __NVIC_PRIO_BITS          2
     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
   #endif
   #ifndef __Vendor_SysTickConfig
     #define __Vendor_SysTickConfig    0
     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
   #endif
 #endif
 /* IO definitions (access restrictions to peripheral registers) */
 /**
     \defgroup CMSIS_glob_defs CMSIS Global Defines
     <strong>IO Type Qualifiers</strong> are used
     \li to specify the access to peripheral variables.
     \li for automatic generation of peripheral register debug information.
 */
 #ifdef __cplusplus
   #define   __I     volatile             /*!< Defines 'read only' permissions                 */
 #else
   #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
 #endif
 #define     __O     volatile             /*!< Defines 'write only' permissions                */
 #define     __IO    volatile             /*!< Defines 'read / write' permissions              */
 /*@} end of group SC000 */
 /*******************************************************************************
  *                 Register Abstraction
   Core Register contain:
   - Core Register
   - Core NVIC Register
   - Core SCB Register
   - Core SysTick Register
   - Core MPU Register
  ******************************************************************************/
 /** \defgroup CMSIS_core_register Defines and Type Definitions
     \brief Type definitions and defines for Cortex-M processor based devices.
 */
 /** \ingroup    CMSIS_core_register
     \defgroup   CMSIS_CORE  Status and Control Registers
     \brief  Core Register type definitions.
   @{
  */
 /** \brief  Union type to access the Application Program Status Register (APSR).
  */
 typedef union
+{
   struct
+  {
 #if (__CORTEX_M != 0x04)
     uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
 #else
     uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
     uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
 #endif
     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
   } b;                                   /*!< Structure used for bit  access                  */
   uint32_t w;                            /*!< Type      used for word access                  */
 } APSR_Type;
 /** \brief  Union type to access the Interrupt Program Status Register (IPSR).
  */
 typedef union
+{
   struct
+  {
     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
     uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
   } b;                                   /*!< Structure used for bit  access                  */
   uint32_t w;                            /*!< Type      used for word access                  */
 } IPSR_Type;
 /** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
  */
 typedef union
+{
   struct
+  {
     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
 #if (__CORTEX_M != 0x04)
     uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
 #else
     uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
     uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
 #endif
     uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
     uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
   } b;                                   /*!< Structure used for bit  access                  */
   uint32_t w;                            /*!< Type      used for word access                  */
 } xPSR_Type;
 /** \brief  Union type to access the Control Registers (CONTROL).
  */
 typedef union
+{
   struct
+  {
     uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
     uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
     uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
     uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
   } b;                                   /*!< Structure used for bit  access                  */
   uint32_t w;                            /*!< Type      used for word access                  */
 } CONTROL_Type;
 /*@} end of group CMSIS_CORE */
 /** \ingroup    CMSIS_core_register
     \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
     \brief      Type definitions for the NVIC Registers
   @{
  */
 /** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
  */
 typedef struct
+{
   __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
        uint32_t RESERVED0[31];
   __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
        uint32_t RSERVED1[31];
   __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
        uint32_t RESERVED2[31];
   __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
        uint32_t RESERVED3[31];
        uint32_t RESERVED4[64];
   __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
 }  NVIC_Type;
 /*@} end of group CMSIS_NVIC */
 /** \ingroup  CMSIS_core_register
     \defgroup CMSIS_SCB     System Control Block (SCB)
     \brief      Type definitions for the System Control Block Registers
   @{
  */
 /** \brief  Structure type to access the System Control Block (SCB).
  */
 typedef struct
+{
   __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
   __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
   __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
   __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
   __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
   __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
        uint32_t RESERVED0[1];
   __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
   __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
        uint32_t RESERVED1[154];
   __IO uint32_t SFCR;                    /*!< Offset: 0x290 (R/W)  Security Features Register                            */
 } SCB_Type;
 /* SCB CPUID Register Definitions */
 #define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
 #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
 #define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
 #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
 #define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
 #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
 #define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
 #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
 #define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
 #define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
 /* SCB Interrupt Control State Register Definitions */
 #define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
 #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
 #define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
 #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
 #define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
 #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
 #define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
 #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
 #define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
 #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
 #define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
 #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
 #define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
 #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
 #define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
 #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
 #define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
 #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
 /* SCB Interrupt Control State Register Definitions */
 #define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
 #define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
 /* SCB Application Interrupt and Reset Control Register Definitions */
 #define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
 #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
 #define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
 #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
 #define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
 #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
 #define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
 #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
 #define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
 #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
 /* SCB System Control Register Definitions */
 #define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
 #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
 #define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
 #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
 #define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
 #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
 /* SCB Configuration Control Register Definitions */
 #define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
 #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
 #define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
 #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
 /* SCB System Handler Control and State Register Definitions */
 #define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
 #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
 /* SCB Security Features Register Definitions */
 #define SCB_SFCR_UNIBRTIMING_Pos            0                                             /*!< SCB SFCR: UNIBRTIMING Position */
 #define SCB_SFCR_UNIBRTIMING_Msk           (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SFCR: UNIBRTIMING Mask */
 #define SCB_SFCR_SECKEY_Pos                16                                             /*!< SCB SFCR: SECKEY Position */
 #define SCB_SFCR_SECKEY_Msk               (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos)        /*!< SCB SFCR: SECKEY Mask */
 /*@} end of group CMSIS_SCB */
 /** \ingroup  CMSIS_core_register
     \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
     \brief      Type definitions for the System Control and ID Register not in the SCB
   @{
  */
 /** \brief  Structure type to access the System Control and ID Register not in the SCB.
  */
 typedef struct
+{
        uint32_t RESERVED0[2];
   __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
 } SCnSCB_Type;
 /* Auxiliary Control Register Definitions */
 #define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
 #define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
 /*@} end of group CMSIS_SCnotSCB */
 /** \ingroup  CMSIS_core_register
     \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
     \brief      Type definitions for the System Timer Registers.
   @{
  */
 /** \brief  Structure type to access the System Timer (SysTick).
  */
 typedef struct
+{
   __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
   __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
   __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
   __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
 } SysTick_Type;
 /* SysTick Control / Status Register Definitions */
 #define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
 #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
 #define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
 #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
 #define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
 #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
 #define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
 #define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
 /* SysTick Reload Register Definitions */
 #define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
 #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
 /* SysTick Current Register Definitions */
 #define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
 #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
 /* SysTick Calibration Register Definitions */
 #define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
 #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
 #define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
 #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
 #define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
 #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
 /*@} end of group CMSIS_SysTick */
 #if (__MPU_PRESENT == 1)
 /** \ingroup  CMSIS_core_register
     \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
     \brief      Type definitions for the Memory Protection Unit (MPU)
   @{
  */
 /** \brief  Structure type to access the Memory Protection Unit (MPU).
  */
 typedef struct
+{
   __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
   __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
   __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
   __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
   __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
 } MPU_Type;
 /* MPU Type Register */
 #define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
 #define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
 #define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
 #define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
 #define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
 #define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
 /* MPU Control Register */
 #define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
 #define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
 #define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
 #define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
 #define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
 #define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
 /* MPU Region Number Register */
 #define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
 #define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
 /* MPU Region Base Address Register */
 #define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
 #define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
 #define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
 #define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
 #define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
 #define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
 /* MPU Region Attribute and Size Register */
 #define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
 #define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
 #define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
 #define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
 #define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
 #define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
 #define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
 #define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
 #define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
 #define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
 #define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
 #define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
 #define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
 #define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
 #define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
 #define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
 #define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
 #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
 #define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
 #define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
 /*@} end of group CMSIS_MPU */
 #endif
 /** \ingroup  CMSIS_core_register
     \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
     \brief      SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)
                 are only accessible over DAP and not via processor. Therefore
                 they are not covered by the Cortex-M0 header file.
   @{
  */
 /*@} end of group CMSIS_CoreDebug */
 /** \ingroup    CMSIS_core_register
     \defgroup   CMSIS_core_base     Core Definitions
     \brief      Definitions for base addresses, unions, and structures.
   @{
  */
 /* Memory mapping of SC000 Hardware */
 #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
 #define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
 #define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
 #define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
 #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
 #define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
 #define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
 #define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
 #if (__MPU_PRESENT == 1)
   #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
   #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
 #endif
 /*@} */
 /*******************************************************************************
  *                Hardware Abstraction Layer
   Core Function Interface contains:
   - Core NVIC Functions
   - Core SysTick Functions
   - Core Register Access Functions
  ******************************************************************************/
 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
 */
 /* ##########################   NVIC functions  #################################### */
 /** \ingroup  CMSIS_Core_FunctionInterface
     \defgroup CMSIS_Core_NVICFunctions NVIC Functions
     \brief      Functions that manage interrupts and exceptions via the NVIC.
     @{
  */
 /* Interrupt Priorities are WORD accessible only under ARMv6M                   */
 /* The following MACROS handle generation of the register offset and byte masks */
 #define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
 #define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
 #define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
 /** \brief  Enable External Interrupt
     The function enables a device-specific interrupt in the NVIC interrupt controller.
     \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
   NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
 /** \brief  Disable External Interrupt
     The function disables a device-specific interrupt in the NVIC interrupt controller.
     \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
   NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
 /** \brief  Get Pending Interrupt
     The function reads the pending register in the NVIC and returns the pending bit
     for the specified interrupt.
     \param [in]      IRQn  Interrupt number.
     \return             0  Interrupt status is not pending.
     \return             1  Interrupt status is pending.
  */
 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
   return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
 /** \brief  Set Pending Interrupt
     The function sets the pending bit of an external interrupt.
     \param [in]      IRQn  Interrupt number. Value cannot be negative.
  */
 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
   NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
 /** \brief  Clear Pending Interrupt
     The function clears the pending bit of an external interrupt.
     \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
   NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
 /** \brief  Set Interrupt Priority
     The function sets the priority of an interrupt.
     \note The priority cannot be set for every core interrupt.
     \param [in]      IRQn  Interrupt number.
     \param [in]  priority  Priority to set.
  */
 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
   if(IRQn < 0) {
     SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
         (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
   else {
     NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
         (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
 /** \brief  Get Interrupt Priority
     The function reads the priority of an interrupt. The interrupt
     number can be positive to specify an external (device specific)
     interrupt, or negative to specify an internal (core) interrupt.
     \param [in]   IRQn  Interrupt number.
     \return             Interrupt Priority. Value is aligned automatically to the implemented
                         priority bits of the microcontroller.
  */
 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
   if(IRQn < 0) {
     return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
   else {
     return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
 /** \brief  System Reset
     The function initiates a system reset request to reset the MCU.
  */
 __STATIC_INLINE void NVIC_SystemReset(void)
+{
   __DSB();                                                     /* Ensure all outstanding memory accesses included
                                                                   buffered write are completed before reset */
   SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
                  SCB_AIRCR_SYSRESETREQ_Msk);
   __DSB();                                                     /* Ensure completion of memory access */
   while(1);                                                    /* wait until reset */
+}
 /*@} end of CMSIS_Core_NVICFunctions */
 /* ##################################    SysTick function  ############################################ */
 /** \ingroup  CMSIS_Core_FunctionInterface
     \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
     \brief      Functions that configure the System.
   @{
  */
 #if (__Vendor_SysTickConfig == 0)
 /** \brief  System Tick Configuration
     The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
     Counter is in free running mode to generate periodic interrupts.
     \param [in]  ticks  Number of ticks between two interrupts.
     \return          0  Function succeeded.
     \return          1  Function failed.
     \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
     function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
     must contain a vendor-specific implementation of this function.
  */
 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
   if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
   SysTick->LOAD  = ticks - 1;                                  /* set reload register */
   NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
   SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
                    SysTick_CTRL_TICKINT_Msk   |
                    SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
   return (0);                                                  /* Function successful */
+}
 #endif
 /*@} end of CMSIS_Core_SysTickFunctions */
 #endif /* __CORE_SC000_H_DEPENDANT */
 #endif /* __CMSIS_GENERIC */
 #ifdef __cplusplus
+}
 #endif

libraries/CMSIS/Include/core_sc300.h

➞

Show inline comments

@@ new file 100644 @@
 /**************************************************************************//**
  * @file     core_sc300.h
  * @brief    CMSIS SC300 Core Peripheral Access Layer Header File
  * @version  V3.20
  * @date     25. February 2013
+ *
  * @note
+ *
  ******************************************************************************/
 /* Copyright (c) 2009 - 2013 ARM LIMITED
    All rights reserved.
    Redistribution and use in source and binary forms, with or without
    modification, are permitted provided that the following conditions are met:
    - Redistributions of source code must retain the above copyright
      notice, this list of conditions and the following disclaimer.
    - Redistributions in binary form must reproduce the above copyright
      notice, this list of conditions and the following disclaimer in the
      documentation and/or other materials provided with the distribution.
    - Neither the name of ARM nor the names of its contributors may be used
      to endorse or promote products derived from this software without
      specific prior written permission.
+   *
    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
    IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
    ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
    LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
    INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
    CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
    POSSIBILITY OF SUCH DAMAGE.
    ---------------------------------------------------------------------------*/
 #if defined ( __ICCARM__ )
  #pragma system_include  /* treat file as system include file for MISRA check */
 #endif
 #ifdef __cplusplus
  extern "C" {
 #endif
 #ifndef __CORE_SC300_H_GENERIC
 #define __CORE_SC300_H_GENERIC
 /** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
   CMSIS violates the following MISRA-C:2004 rules:
    \li Required Rule 8.5, object/function definition in header file.<br>
      Function definitions in header files are used to allow 'inlining'.
    \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
      Unions are used for effective representation of core registers.
    \li Advisory Rule 19.7, Function-like macro defined.<br>
      Function-like macros are used to allow more efficient code.
  */
 /*******************************************************************************
  *                 CMSIS definitions
  ******************************************************************************/
 /** \ingroup SC3000
   @{
  */
 /*  CMSIS SC300 definitions */
 #define __SC300_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version */
 #define __SC300_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version  */
 #define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16) | \
                                       __SC300_CMSIS_VERSION_SUB          )   /*!< CMSIS HAL version number       */
 #define __CORTEX_SC                (300)                                     /*!< Cortex secure core             */
 #if   defined ( __CC_ARM )
   #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
   #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
   #define __STATIC_INLINE  static __inline
 #elif defined ( __ICCARM__ )
   #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
   #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
   #define __STATIC_INLINE  static inline
 #elif defined ( __GNUC__ )
   #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
   #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
   #define __STATIC_INLINE  static inline
 #elif defined ( __TASKING__ )
   #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
   #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
   #define __STATIC_INLINE  static inline
 #endif
 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
 */
 #define __FPU_USED       0
 #if defined ( __CC_ARM )
   #if defined __TARGET_FPU_VFP
     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 #elif defined ( __ICCARM__ )
   #if defined __ARMVFP__
     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 #elif defined ( __GNUC__ )
   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 #elif defined ( __TASKING__ )
   #if defined __FPU_VFP__
     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 #endif
 #include <stdint.h>                      /* standard types definitions                      */
 #include <core_cmInstr.h>                /* Core Instruction Access                         */
 #include <core_cmFunc.h>                 /* Core Function Access                            */
 #endif /* __CORE_SC300_H_GENERIC */
 #ifndef __CMSIS_GENERIC
 #ifndef __CORE_SC300_H_DEPENDANT
 #define __CORE_SC300_H_DEPENDANT
 /* check device defines and use defaults */
 #if defined __CHECK_DEVICE_DEFINES
   #ifndef __SC300_REV
     #define __SC300_REV               0x0000
     #warning "__SC300_REV not defined in device header file; using default!"
   #endif
   #ifndef __MPU_PRESENT
     #define __MPU_PRESENT             0
     #warning "__MPU_PRESENT not defined in device header file; using default!"
   #endif
   #ifndef __NVIC_PRIO_BITS
     #define __NVIC_PRIO_BITS          4
     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
   #endif
   #ifndef __Vendor_SysTickConfig
     #define __Vendor_SysTickConfig    0
     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
   #endif
 #endif
 /* IO definitions (access restrictions to peripheral registers) */
 /**
     \defgroup CMSIS_glob_defs CMSIS Global Defines
     <strong>IO Type Qualifiers</strong> are used
     \li to specify the access to peripheral variables.
     \li for automatic generation of peripheral register debug information.
 */
 #ifdef __cplusplus
   #define   __I     volatile             /*!< Defines 'read only' permissions                 */
 #else
   #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
 #endif
 #define     __O     volatile             /*!< Defines 'write only' permissions                */
 #define     __IO    volatile             /*!< Defines 'read / write' permissions              */
 /*@} end of group SC300 */
 /*******************************************************************************
  *                 Register Abstraction
   Core Register contain:
   - Core Register
   - Core NVIC Register
   - Core SCB Register
   - Core SysTick Register
   - Core Debug Register
   - Core MPU Register
  ******************************************************************************/
 /** \defgroup CMSIS_core_register Defines and Type Definitions
     \brief Type definitions and defines for Cortex-M processor based devices.
 */
 /** \ingroup    CMSIS_core_register
     \defgroup   CMSIS_CORE  Status and Control Registers
     \brief  Core Register type definitions.
   @{
  */
 /** \brief  Union type to access the Application Program Status Register (APSR).
  */
 typedef union
+{
   struct
+  {
 #if (__CORTEX_M != 0x04)
     uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
 #else
     uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
     uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
 #endif
     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
   } b;                                   /*!< Structure used for bit  access                  */
   uint32_t w;                            /*!< Type      used for word access                  */
 } APSR_Type;
 /** \brief  Union type to access the Interrupt Program Status Register (IPSR).
  */
 typedef union
+{
   struct
+  {
     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
     uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
   } b;                                   /*!< Structure used for bit  access                  */
   uint32_t w;                            /*!< Type      used for word access                  */
 } IPSR_Type;
 /** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
  */
 typedef union
+{
   struct
+  {
     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
 #if (__CORTEX_M != 0x04)
     uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
 #else
     uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
     uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
 #endif
     uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
     uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
   } b;                                   /*!< Structure used for bit  access                  */
   uint32_t w;                            /*!< Type      used for word access                  */
 } xPSR_Type;
 /** \brief  Union type to access the Control Registers (CONTROL).
  */
 typedef union
+{
   struct
+  {
     uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
     uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
     uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
     uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
   } b;                                   /*!< Structure used for bit  access                  */
   uint32_t w;                            /*!< Type      used for word access                  */
 } CONTROL_Type;
 /*@} end of group CMSIS_CORE */
 /** \ingroup    CMSIS_core_register
     \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
     \brief      Type definitions for the NVIC Registers
   @{
  */
 /** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
  */
 typedef struct
+{
   __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
        uint32_t RESERVED0[24];
   __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
        uint32_t RSERVED1[24];
   __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
        uint32_t RESERVED2[24];
   __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
        uint32_t RESERVED3[24];
   __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
        uint32_t RESERVED4[56];
   __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
        uint32_t RESERVED5[644];
   __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
 }  NVIC_Type;
 /* Software Triggered Interrupt Register Definitions */
 #define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
 #define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
 /*@} end of group CMSIS_NVIC */
 /** \ingroup  CMSIS_core_register
     \defgroup CMSIS_SCB     System Control Block (SCB)
     \brief      Type definitions for the System Control Block Registers
   @{
  */
 /** \brief  Structure type to access the System Control Block (SCB).
  */
 typedef struct
+{
   __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
   __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
   __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
   __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
   __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
   __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
   __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
   __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
   __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
   __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
   __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
   __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
   __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
   __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
   __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
   __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
   __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
   __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
   __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
        uint32_t RESERVED0[5];
   __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
 } SCB_Type;
 /* SCB CPUID Register Definitions */
 #define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
 #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
 #define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
 #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
 #define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
 #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
 #define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
 #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
 #define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
 #define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
 /* SCB Interrupt Control State Register Definitions */
 #define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
 #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
 #define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
 #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
 #define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
 #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
 #define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
 #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
 #define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
 #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
 #define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
 #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
 #define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
 #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
 #define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
 #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
 #define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
 #define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
 #define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
 #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
 /* SCB Vector Table Offset Register Definitions */
 #define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
 #define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
 #define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
 #define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
 /* SCB Application Interrupt and Reset Control Register Definitions */
 #define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
 #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
 #define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
 #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
 #define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
 #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
 #define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
 #define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
 #define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
 #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
 #define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
 #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
 #define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
 #define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
 /* SCB System Control Register Definitions */
 #define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
 #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
 #define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
 #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
 #define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
 #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
 /* SCB Configuration Control Register Definitions */
 #define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
 #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
 #define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
 #define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
 #define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
 #define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
 #define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
 #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
 #define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
 #define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
 #define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
 #define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
 /* SCB System Handler Control and State Register Definitions */
 #define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
 #define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
 #define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
 #define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
 #define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
 #define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
 #define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
 #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
 #define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
 #define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
 #define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
 #define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
 #define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
 #define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
 #define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
 #define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
 #define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
 #define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
 #define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
 #define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
 #define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
 #define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
 #define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
 #define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
 #define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
 #define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
 #define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
 #define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
 /* SCB Configurable Fault Status Registers Definitions */
 #define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
 #define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
 #define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
 #define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
 #define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
 #define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
 /* SCB Hard Fault Status Registers Definitions */
 #define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
 #define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
 #define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
 #define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
 #define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
 #define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
 /* SCB Debug Fault Status Register Definitions */
 #define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
 #define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
 #define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
 #define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
 #define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
 #define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
 #define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
 #define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
 #define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
 #define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
 /*@} end of group CMSIS_SCB */
 /** \ingroup  CMSIS_core_register
     \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
     \brief      Type definitions for the System Control and ID Register not in the SCB
   @{
  */
 /** \brief  Structure type to access the System Control and ID Register not in the SCB.
  */
 typedef struct
+{
        uint32_t RESERVED0[1];
   __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
        uint32_t RESERVED1[1];
 } SCnSCB_Type;
 /* Interrupt Controller Type Register Definitions */
 #define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
 #define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
 /*@} end of group CMSIS_SCnotSCB */
 /** \ingroup  CMSIS_core_register
     \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
     \brief      Type definitions for the System Timer Registers.
   @{
  */
 /** \brief  Structure type to access the System Timer (SysTick).
  */
 typedef struct
+{
   __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
   __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
   __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
   __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
 } SysTick_Type;
 /* SysTick Control / Status Register Definitions */
 #define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
 #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
 #define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
 #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
 #define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
 #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
 #define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
 #define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
 /* SysTick Reload Register Definitions */
 #define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
 #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
 /* SysTick Current Register Definitions */
 #define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
 #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
 /* SysTick Calibration Register Definitions */
 #define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
 #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
 #define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
 #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
 #define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
 #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
 /*@} end of group CMSIS_SysTick */
 /** \ingroup  CMSIS_core_register
     \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
     \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
   @{
  */
 /** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
  */
 typedef struct
+{
   __O  union
+  {
     __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
     __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
     __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
   }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
        uint32_t RESERVED0[864];
   __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
        uint32_t RESERVED1[15];
   __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
        uint32_t RESERVED2[15];
   __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
        uint32_t RESERVED3[29];
   __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
   __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
   __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
        uint32_t RESERVED4[43];
   __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
   __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
        uint32_t RESERVED5[6];
   __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
   __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
   __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
   __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
   __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
   __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
   __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
   __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
   __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
   __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
   __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
   __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
 } ITM_Type;
 /* ITM Trace Privilege Register Definitions */
 #define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
 #define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
 /* ITM Trace Control Register Definitions */
 #define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
 #define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
 #define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
 #define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
 #define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
 #define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
 #define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
 #define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
 #define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
 #define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
 #define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
 #define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
 #define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
 #define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
 #define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
 #define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
 #define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
 #define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
 /* ITM Integration Write Register Definitions */
 #define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
 #define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
 /* ITM Integration Read Register Definitions */
 #define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
 #define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
 /* ITM Integration Mode Control Register Definitions */
 #define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
 #define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
 /* ITM Lock Status Register Definitions */
 #define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
 #define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
 #define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
 #define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
 #define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
 #define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
 /*@}*/ /* end of group CMSIS_ITM */
 /** \ingroup  CMSIS_core_register
     \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
     \brief      Type definitions for the Data Watchpoint and Trace (DWT)
   @{
  */
 /** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
  */
 typedef struct
+{
   __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
   __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
   __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
   __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
   __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
   __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
   __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
   __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
   __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
   __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
   __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
        uint32_t RESERVED0[1];
   __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
   __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
   __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
        uint32_t RESERVED1[1];
   __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
   __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
   __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
        uint32_t RESERVED2[1];
   __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
   __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
   __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
 } DWT_Type;
 /* DWT Control Register Definitions */
 #define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
 #define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
 #define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
 #define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
 #define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
 #define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
 #define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
 #define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
 #define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
 #define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
 #define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
 #define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
 #define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
 #define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
 #define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
 #define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
 #define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
 #define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
 #define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
 #define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
 #define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
 #define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
 #define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
 #define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
 #define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
 #define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
 #define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
 #define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
 #define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
 #define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
 #define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
 #define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
 #define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
 #define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
 #define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
 #define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
 /* DWT CPI Count Register Definitions */
 #define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
 #define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
 /* DWT Exception Overhead Count Register Definitions */
 #define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
 #define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
 /* DWT Sleep Count Register Definitions */
 #define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
 #define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
 /* DWT LSU Count Register Definitions */
 #define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
 #define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
 /* DWT Folded-instruction Count Register Definitions */
 #define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
 #define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
 /* DWT Comparator Mask Register Definitions */
 #define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
 #define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
 /* DWT Comparator Function Register Definitions */
 #define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
 #define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
 #define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
 #define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
 #define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
 #define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
 #define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
 #define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
 #define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
 #define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
 #define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
 #define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
 #define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
 #define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
 #define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
 #define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
 #define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
 #define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
 /*@}*/ /* end of group CMSIS_DWT */
 /** \ingroup  CMSIS_core_register
     \defgroup CMSIS_TPI     Trace Port Interface (TPI)
     \brief      Type definitions for the Trace Port Interface (TPI)
   @{
  */
 /** \brief  Structure type to access the Trace Port Interface Register (TPI).
  */
 typedef struct
+{
   __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
   __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
        uint32_t RESERVED0[2];
   __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
        uint32_t RESERVED1[55];
   __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
        uint32_t RESERVED2[131];
   __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
   __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
   __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
        uint32_t RESERVED3[759];
   __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
   __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
   __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
        uint32_t RESERVED4[1];
   __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
   __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
   __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
        uint32_t RESERVED5[39];
   __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
   __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
        uint32_t RESERVED7[8];
   __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
   __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
 } TPI_Type;
 /* TPI Asynchronous Clock Prescaler Register Definitions */
 #define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
 #define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
 /* TPI Selected Pin Protocol Register Definitions */
 #define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
 #define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
 /* TPI Formatter and Flush Status Register Definitions */
 #define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
 #define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
 #define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
 #define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
 #define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
 #define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
 #define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
 #define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
 /* TPI Formatter and Flush Control Register Definitions */
 #define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
 #define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
 #define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
 #define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
 /* TPI TRIGGER Register Definitions */
 #define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
 #define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
 /* TPI Integration ETM Data Register Definitions (FIFO0) */
 #define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
 #define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
 #define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
 #define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
 #define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
 #define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
 #define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
 #define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
 #define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
 #define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
 #define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
 #define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
 #define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
 #define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
 /* TPI ITATBCTR2 Register Definitions */
 #define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
 #define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
 /* TPI Integration ITM Data Register Definitions (FIFO1) */
 #define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
 #define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
 #define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
 #define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
 #define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
 #define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
 #define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
 #define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
 #define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
 #define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
 #define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
 #define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
 #define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
 #define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
 /* TPI ITATBCTR0 Register Definitions */
 #define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
 #define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
 /* TPI Integration Mode Control Register Definitions */
 #define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
 #define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
 /* TPI DEVID Register Definitions */
 #define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
 #define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
 #define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
 #define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
 #define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
 #define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
 #define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
 #define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
 #define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
 #define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
 #define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
 #define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
 /* TPI DEVTYPE Register Definitions */
 #define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
 #define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
 #define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
 #define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
 /*@}*/ /* end of group CMSIS_TPI */
 #if (__MPU_PRESENT == 1)
 /** \ingroup  CMSIS_core_register
     \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
     \brief      Type definitions for the Memory Protection Unit (MPU)
   @{
  */
 /** \brief  Structure type to access the Memory Protection Unit (MPU).
  */
 typedef struct
+{
   __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
   __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
   __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
   __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
   __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
   __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
   __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
   __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
   __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
   __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
   __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
 } MPU_Type;
 /* MPU Type Register */
 #define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
 #define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
 #define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
 #define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
 #define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
 #define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
 /* MPU Control Register */
 #define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
 #define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
 #define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
 #define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
 #define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
 #define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
 /* MPU Region Number Register */
 #define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
 #define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
 /* MPU Region Base Address Register */
 #define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
 #define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
 #define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
 #define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
 #define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
 #define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
 /* MPU Region Attribute and Size Register */
 #define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
 #define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
 #define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
 #define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
 #define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
 #define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
 #define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
 #define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
 #define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
 #define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
 #define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
 #define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
 #define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
 #define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
 #define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
 #define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
 #define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
 #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
 #define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
 #define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
 /*@} end of group CMSIS_MPU */
 #endif
 /** \ingroup  CMSIS_core_register
     \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
     \brief      Type definitions for the Core Debug Registers
   @{
  */
 /** \brief  Structure type to access the Core Debug Register (CoreDebug).
  */
 typedef struct
+{
   __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
   __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
   __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
   __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
 } CoreDebug_Type;
 /* Debug Halting Control and Status Register */
 #define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
 #define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
 #define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
 #define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
 #define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
 #define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
 #define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
 #define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
 #define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
 #define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
 #define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
 #define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
 #define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
 #define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
 #define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
 #define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
 #define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
 #define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
 #define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
 #define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
 /* Debug Core Register Selector Register */
 #define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
 #define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
 #define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
 #define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
 /* Debug Exception and Monitor Control Register */
 #define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
 #define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
 #define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
 #define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
 #define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
 #define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
 #define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
 #define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
 #define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
 #define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
 #define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
 #define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
 #define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
 #define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
 #define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
 #define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
 #define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
 #define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
 #define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
 #define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
 #define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
 #define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
 #define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
 #define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
 #define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
 #define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
 /*@} end of group CMSIS_CoreDebug */
 /** \ingroup    CMSIS_core_register
     \defgroup   CMSIS_core_base     Core Definitions
     \brief      Definitions for base addresses, unions, and structures.
   @{
  */
 /* Memory mapping of Cortex-M3 Hardware */
 #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
 #define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
 #define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
 #define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
 #define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
 #define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
 #define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
 #define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
 #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
 #define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
 #define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
 #define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
 #define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
 #define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
 #define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
 #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
 #if (__MPU_PRESENT == 1)
   #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
   #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
 #endif
 /*@} */
 /*******************************************************************************
  *                Hardware Abstraction Layer
   Core Function Interface contains:
   - Core NVIC Functions
   - Core SysTick Functions
   - Core Debug Functions
   - Core Register Access Functions
  ******************************************************************************/
 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
 */
 /* ##########################   NVIC functions  #################################### */
 /** \ingroup  CMSIS_Core_FunctionInterface
     \defgroup CMSIS_Core_NVICFunctions NVIC Functions
     \brief      Functions that manage interrupts and exceptions via the NVIC.
     @{
  */
 /** \brief  Set Priority Grouping
   The function sets the priority grouping field using the required unlock sequence.
   The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
   Only values from 0..7 are used.
   In case of a conflict between priority grouping and available
   priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
     \param [in]      PriorityGroup  Priority grouping field.
  */
 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
   uint32_t reg_value;
   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
   reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
   reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
   reg_value  =  (reg_value                                 |
                 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
                 (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
   SCB->AIRCR =  reg_value;
+}
 /** \brief  Get Priority Grouping
   The function reads the priority grouping field from the NVIC Interrupt Controller.
     \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
  */
 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
   return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
 /** \brief  Enable External Interrupt
     The function enables a device-specific interrupt in the NVIC interrupt controller.
     \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
   NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
 /** \brief  Disable External Interrupt
     The function disables a device-specific interrupt in the NVIC interrupt controller.
     \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
   NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
 /** \brief  Get Pending Interrupt
     The function reads the pending register in the NVIC and returns the pending bit
     for the specified interrupt.
     \param [in]      IRQn  Interrupt number.
     \return             0  Interrupt status is not pending.
     \return             1  Interrupt status is pending.
  */
 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
   return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
 /** \brief  Set Pending Interrupt
     The function sets the pending bit of an external interrupt.
     \param [in]      IRQn  Interrupt number. Value cannot be negative.
  */
 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
   NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
 /** \brief  Clear Pending Interrupt
     The function clears the pending bit of an external interrupt.
     \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
   NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
 /** \brief  Get Active Interrupt
     The function reads the active register in NVIC and returns the active bit.
     \param [in]      IRQn  Interrupt number.
     \return             0  Interrupt status is not active.
     \return             1  Interrupt status is active.
  */
 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
   return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
 /** \brief  Set Interrupt Priority
     The function sets the priority of an interrupt.
     \note The priority cannot be set for every core interrupt.
     \param [in]      IRQn  Interrupt number.
     \param [in]  priority  Priority to set.
  */
 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
   if(IRQn < 0) {
     SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
   else {
     NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
 /** \brief  Get Interrupt Priority
     The function reads the priority of an interrupt. The interrupt
     number can be positive to specify an external (device specific)
     interrupt, or negative to specify an internal (core) interrupt.
     \param [in]   IRQn  Interrupt number.
     \return             Interrupt Priority. Value is aligned automatically to the implemented
                         priority bits of the microcontroller.
  */
 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
   if(IRQn < 0) {
     return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
   else {
     return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
 /** \brief  Encode Priority
     The function encodes the priority for an interrupt with the given priority group,
     preemptive priority value, and subpriority value.
     In case of a conflict between priority grouping and available
     priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
     \param [in]     PriorityGroup  Used priority group.
     \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
     \param [in]       SubPriority  Subpriority value (starting from 0).
     \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
  */
 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
   uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
   uint32_t PreemptPriorityBits;
   uint32_t SubPriorityBits;
   PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
   SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
   return (
            ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
            ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
          );
+}
 /** \brief  Decode Priority
     The function decodes an interrupt priority value with a given priority group to
     preemptive priority value and subpriority value.
     In case of a conflict between priority grouping and available
     priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
     \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
     \param [in]     PriorityGroup  Used priority group.
     \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
     \param [out]     pSubPriority  Subpriority value (starting from 0).
  */
 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
   uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
   uint32_t PreemptPriorityBits;
   uint32_t SubPriorityBits;
   PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
   SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
   *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
   *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
 /** \brief  System Reset
     The function initiates a system reset request to reset the MCU.
  */
 __STATIC_INLINE void NVIC_SystemReset(void)
+{
   __DSB();                                                     /* Ensure all outstanding memory accesses included
                                                                   buffered write are completed before reset */
   SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
                  (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
                  SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
   __DSB();                                                     /* Ensure completion of memory access */
   while(1);                                                    /* wait until reset */
+}
 /*@} end of CMSIS_Core_NVICFunctions */
 /* ##################################    SysTick function  ############################################ */
 /** \ingroup  CMSIS_Core_FunctionInterface
     \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
     \brief      Functions that configure the System.
   @{
  */
 #if (__Vendor_SysTickConfig == 0)
 /** \brief  System Tick Configuration
     The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
     Counter is in free running mode to generate periodic interrupts.
     \param [in]  ticks  Number of ticks between two interrupts.
     \return          0  Function succeeded.
     \return          1  Function failed.
     \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
     function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
     must contain a vendor-specific implementation of this function.
  */
 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
   if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
   SysTick->LOAD  = ticks - 1;                                  /* set reload register */
   NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
   SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
                    SysTick_CTRL_TICKINT_Msk   |
                    SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
   return (0);                                                  /* Function successful */
+}
 #endif
 /*@} end of CMSIS_Core_SysTickFunctions */
 /* ##################################### Debug In/Output function ########################################### */
 /** \ingroup  CMSIS_Core_FunctionInterface
     \defgroup CMSIS_core_DebugFunctions ITM Functions
     \brief   Functions that access the ITM debug interface.
   @{
  */
 extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
 #define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
 /** \brief  ITM Send Character
     The function transmits a character via the ITM channel 0, and
     \li Just returns when no debugger is connected that has booked the output.
     \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
     \param [in]     ch  Character to transmit.
     \returns            Character to transmit.
  */
 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
   if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
       (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
     while (ITM->PORT[0].u32 == 0);
     ITM->PORT[0].u8 = (uint8_t) ch;
+  }
   return (ch);
+}
 /** \brief  ITM Receive Character
     The function inputs a character via the external variable \ref ITM_RxBuffer.
     \return             Received character.
     \return         -1  No character pending.
  */
 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
   int32_t ch = -1;                           /* no character available */
   if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
     ch = ITM_RxBuffer;
     ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
   return (ch);
+}
 /** \brief  ITM Check Character
     The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
     \return          0  No character available.
     \return          1  Character available.
  */
 __STATIC_INLINE int32_t ITM_CheckChar (void) {
   if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
     return (0);                                 /* no character available */
   } else {
     return (1);                                 /*    character available */
+  }
+}
 /*@} end of CMSIS_core_DebugFunctions */
 #endif /* __CORE_SC300_H_DEPENDANT */
 #endif /* __CMSIS_GENERIC */
 #ifdef __cplusplus
+}
 #endif

libraries/CMSIS/README.txt

➞

Show inline comments

@@ new file 100644 @@
 * -------------------------------------------------------------------
 * Copyright (C) 2011-2013 ARM Limited. All rights reserved.
+*
 * Date:        18 March 2013
 * Revision:    V3.20
+*
 * Project:     Cortex Microcontroller Software Interface Standard (CMSIS)
 * Title:       Release Note for CMSIS
+*
 * -------------------------------------------------------------------
 NOTE - Open the index.html file to access CMSIS documentation
 The Cortex Microcontroller Software Interface Standard (CMSIS) provides a single standard across all
 Cortex-Mx processor series vendors. It enables code re-use and code sharing across software projects
 and reduces time-to-market for new embedded applications.
 CMSIS is released under the terms of the end user license agreement ("CMSIS END USER LICENCE AGREEMENT.pdf").
 Any user of the software package is bound to the terms and conditions of the end user license agreement.
 You will find the following sub-directories:
 Documentation           - Contains CMSIS documentation.
 DSP_Lib                 - MDK project files, Examples and source files etc.. to build the
                           CMSIS DSP Software Library for Cortex-M0, Cortex-M3, Cortex-M4 processors.
 Include                 - CMSIS Core Support and CMSIS DSP Include Files.
 Lib                     - CMSIS DSP Libraries.
 RTOS                    - CMSIS RTOS API template header file.
 SVD                     - CMSIS SVD Schema files and Conversion Utility.

libraries/CMSIS/RTOS/cmsis_os.h

➞

Show inline comments

@@ new file 100644 @@
 /* ----------------------------------------------------------------------
  * $Date:        5. February 2013
  * $Revision:    V1.02
+ *
  * Project:      CMSIS-RTOS API
  * Title:        cmsis_os.h template header file
+ *
  * Version 0.02
  *    Initial Proposal Phase
  * Version 0.03
  *    osKernelStart added, optional feature: main started as thread
  *    osSemaphores have standard behavior
  *    osTimerCreate does not start the timer, added osTimerStart
  *    osThreadPass is renamed to osThreadYield
  * Version 1.01
  *    Support for C++ interface
  *     - const attribute removed from the osXxxxDef_t typedef's
  *     - const attribute added to the osXxxxDef macros
  *    Added: osTimerDelete, osMutexDelete, osSemaphoreDelete
  *    Added: osKernelInitialize
  * Version 1.02
  *    Control functions for short timeouts in microsecond resolution:
  *    Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec
  *    Removed: osSignalGet
  *----------------------------------------------------------------------------
+ *
  * Copyright (c) 2013 ARM LIMITED
  * All rights reserved.
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
  *  - Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  *  - Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  *  - Neither the name of ARM  nor the names of its contributors may be used
  *    to endorse or promote products derived from this software without
  *    specific prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  *---------------------------------------------------------------------------*/
 /**
 \page cmsis_os_h Header File Template: cmsis_os.h
 The file \b cmsis_os.h is a template header file for a CMSIS-RTOS compliant Real-Time Operating System (RTOS).
 Each RTOS that is compliant with CMSIS-RTOS shall provide a specific \b cmsis_os.h header file that represents
 its implementation.
 The file cmsis_os.h contains:
  - CMSIS-RTOS API function definitions
  - struct definitions for parameters and return types
  - status and priority values used by CMSIS-RTOS API functions
  - macros for defining threads and other kernel objects
 <b>Name conventions and header file modifications</b>
 All definitions are prefixed with \b os to give an unique name space for CMSIS-RTOS functions.
 Definitions that are prefixed \b os_ are not used in the application code but local to this header file.
 All definitions and functions that belong to a module are grouped and have a common prefix, i.e. \b osThread.
 Definitions that are marked with <b>CAN BE CHANGED</b> can be adapted towards the needs of the actual CMSIS-RTOS implementation.
 These definitions can be specific to the underlying RTOS kernel.
 Definitions that are marked with <b>MUST REMAIN UNCHANGED</b> cannot be altered. Otherwise the CMSIS-RTOS implementation is no longer
 compliant to the standard. Note that some functions are optional and need not to be provided by every CMSIS-RTOS implementation.
 <b>Function calls from interrupt service routines</b>
 The following CMSIS-RTOS functions can be called from threads and interrupt service routines (ISR):
   - \ref osSignalSet
   - \ref osSemaphoreRelease
   - \ref osPoolAlloc, \ref osPoolCAlloc, \ref osPoolFree
   - \ref osMessagePut, \ref osMessageGet
   - \ref osMailAlloc, \ref osMailCAlloc, \ref osMailGet, \ref osMailPut, \ref osMailFree
 Functions that cannot be called from an ISR are verifying the interrupt status and return in case that they are called
 from an ISR context the status code \b osErrorISR. In some implementations this condition might be caught using the HARD FAULT vector.
 Some CMSIS-RTOS implementations support CMSIS-RTOS function calls from multiple ISR at the same time.
 If this is impossible, the CMSIS-RTOS rejects calls by nested ISR functions with the status code \b osErrorISRRecursive.
 <b>Define and reference object definitions</b>
 With <b>\#define osObjectsExternal</b> objects are defined as external symbols. This allows to create a consistent header file
 that is used throughout a project as shown below:
 <i>Header File</i>
 \code
 #include <cmsis_os.h>                                         // CMSIS RTOS header file
 // Thread definition
 extern void thread_sample (void const *argument);             // function prototype
 osThreadDef (thread_sample, osPriorityBelowNormal, 1, 100);
 // Pool definition
 osPoolDef(MyPool, 10, long);
 \endcode
 This header file defines all objects when included in a C/C++ source file. When <b>\#define osObjectsExternal</b> is
 present before the header file, the objects are defined as external symbols. A single consistent header file can therefore be
 used throughout the whole project.
 <i>Example</i>
 \code
 #include "osObjects.h"     // Definition of the CMSIS-RTOS objects
 \endcode
 \code
 #define osObjectExternal   // Objects will be defined as external symbols
 #include "osObjects.h"     // Reference to the CMSIS-RTOS objects
 \endcode
 */
 #ifndef _CMSIS_OS_H
 #define _CMSIS_OS_H
 /// \note MUST REMAIN UNCHANGED: \b osCMSIS identifies the CMSIS-RTOS API version.
 #define osCMSIS           0x10002      ///< API version (main [31:16] .sub [15:0])
 /// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlying RTOS kernel and version number.
 #define osCMSIS_KERNEL    0x10000	   ///< RTOS identification and version (main [31:16] .sub [15:0])
 /// \note MUST REMAIN UNCHANGED: \b osKernelSystemId shall be consistent in every CMSIS-RTOS.
 #define osKernelSystemId "KERNEL V1.00"   ///< RTOS identification string
 /// \note MUST REMAIN UNCHANGED: \b osFeature_xxx shall be consistent in every CMSIS-RTOS.
 #define osFeature_MainThread   1       ///< main thread      1=main can be thread, 0=not available
 #define osFeature_Pool         1       ///< Memory Pools:    1=available, 0=not available
 #define osFeature_MailQ        1       ///< Mail Queues:     1=available, 0=not available
 #define osFeature_MessageQ     1       ///< Message Queues:  1=available, 0=not available
 #define osFeature_Signals      8       ///< maximum number of Signal Flags available per thread
 #define osFeature_Semaphore    30      ///< maximum count for \ref osSemaphoreCreate function
 #define osFeature_Wait         1       ///< osWait function: 1=available, 0=not available
 #define osFeature_SysTick      1       ///< osKernelSysTick functions: 1=available, 0=not available
 #include <stdint.h>
 #include <stddef.h>
 #ifdef  __cplusplus
 extern "C"
+{
 #endif
 // ==== Enumeration, structures, defines ====
 /// Priority used for thread control.
 /// \note MUST REMAIN UNCHANGED: \b osPriority shall be consistent in every CMSIS-RTOS.
 typedef enum  {
   osPriorityIdle          = -3,          ///< priority: idle (lowest)
   osPriorityLow           = -2,          ///< priority: low
   osPriorityBelowNormal   = -1,          ///< priority: below normal
   osPriorityNormal        =  0,          ///< priority: normal (default)
   osPriorityAboveNormal   = +1,          ///< priority: above normal
   osPriorityHigh          = +2,          ///< priority: high
   osPriorityRealtime      = +3,          ///< priority: realtime (highest)
   osPriorityError         =  0x84        ///< system cannot determine priority or thread has illegal priority
 } osPriority;
 /// Timeout value.
 /// \note MUST REMAIN UNCHANGED: \b osWaitForever shall be consistent in every CMSIS-RTOS.
 #define osWaitForever     0xFFFFFFFF     ///< wait forever timeout value
 /// Status code values returned by CMSIS-RTOS functions.
 /// \note MUST REMAIN UNCHANGED: \b osStatus shall be consistent in every CMSIS-RTOS.
 typedef enum  {
   osOK                    =     0,       ///< function completed; no error or event occurred.
   osEventSignal           =  0x08,       ///< function completed; signal event occurred.
   osEventMessage          =  0x10,       ///< function completed; message event occurred.
   osEventMail             =  0x20,       ///< function completed; mail event occurred.
   osEventTimeout          =  0x40,       ///< function completed; timeout occurred.
   osErrorParameter        =  0x80,       ///< parameter error: a mandatory parameter was missing or specified an incorrect object.
   osErrorResource         =  0x81,       ///< resource not available: a specified resource was not available.
   osErrorTimeoutResource  =  0xC1,       ///< resource not available within given time: a specified resource was not available within the timeout period.
   osErrorISR              =  0x82,       ///< not allowed in ISR context: the function cannot be called from interrupt service routines.
   osErrorISRRecursive     =  0x83,       ///< function called multiple times from ISR with same object.
   osErrorPriority         =  0x84,       ///< system cannot determine priority or thread has illegal priority.
   osErrorNoMemory         =  0x85,       ///< system is out of memory: it was impossible to allocate or reserve memory for the operation.
   osErrorValue            =  0x86,       ///< value of a parameter is out of range.
   osErrorOS               =  0xFF,       ///< unspecified RTOS error: run-time error but no other error message fits.
   os_status_reserved      =  0x7FFFFFFF  ///< prevent from enum down-size compiler optimization.
 } osStatus;
 /// Timer type value for the timer definition.
 /// \note MUST REMAIN UNCHANGED: \b os_timer_type shall be consistent in every CMSIS-RTOS.
 typedef enum  {
   osTimerOnce             =     0,       ///< one-shot timer
   osTimerPeriodic         =     1        ///< repeating timer
 } os_timer_type;
 /// Entry point of a thread.
 /// \note MUST REMAIN UNCHANGED: \b os_pthread shall be consistent in every CMSIS-RTOS.
 typedef void (*os_pthread) (void const *argument);
 /// Entry point of a timer call back function.
 /// \note MUST REMAIN UNCHANGED: \b os_ptimer shall be consistent in every CMSIS-RTOS.
 typedef void (*os_ptimer) (void const *argument);
 // >>> the following data type definitions may shall adapted towards a specific RTOS
 /// Thread ID identifies the thread (pointer to a thread control block).
 /// \note CAN BE CHANGED: \b os_thread_cb is implementation specific in every CMSIS-RTOS.
 typedef struct os_thread_cb *osThreadId;
 /// Timer ID identifies the timer (pointer to a timer control block).
 /// \note CAN BE CHANGED: \b os_timer_cb is implementation specific in every CMSIS-RTOS.
 typedef struct os_timer_cb *osTimerId;
 /// Mutex ID identifies the mutex (pointer to a mutex control block).
 /// \note CAN BE CHANGED: \b os_mutex_cb is implementation specific in every CMSIS-RTOS.
 typedef struct os_mutex_cb *osMutexId;
 /// Semaphore ID identifies the semaphore (pointer to a semaphore control block).
 /// \note CAN BE CHANGED: \b os_semaphore_cb is implementation specific in every CMSIS-RTOS.
 typedef struct os_semaphore_cb *osSemaphoreId;
 /// Pool ID identifies the memory pool (pointer to a memory pool control block).
 /// \note CAN BE CHANGED: \b os_pool_cb is implementation specific in every CMSIS-RTOS.
 typedef struct os_pool_cb *osPoolId;
 /// Message ID identifies the message queue (pointer to a message queue control block).
 /// \note CAN BE CHANGED: \b os_messageQ_cb is implementation specific in every CMSIS-RTOS.
 typedef struct os_messageQ_cb *osMessageQId;
 /// Mail ID identifies the mail queue (pointer to a mail queue control block).
 /// \note CAN BE CHANGED: \b os_mailQ_cb is implementation specific in every CMSIS-RTOS.
 typedef struct os_mailQ_cb *osMailQId;
 /// Thread Definition structure contains startup information of a thread.
 /// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS.
 typedef struct os_thread_def  {
   os_pthread               pthread;    ///< start address of thread function
   osPriority             tpriority;    ///< initial thread priority
   uint32_t               instances;    ///< maximum number of instances of that thread function
   uint32_t               stacksize;    ///< stack size requirements in bytes; 0 is default stack size
 } osThreadDef_t;
 /// Timer Definition structure contains timer parameters.
 /// \note CAN BE CHANGED: \b os_timer_def is implementation specific in every CMSIS-RTOS.
 typedef struct os_timer_def  {
   os_ptimer                 ptimer;    ///< start address of a timer function
 } osTimerDef_t;
 /// Mutex Definition structure contains setup information for a mutex.
 /// \note CAN BE CHANGED: \b os_mutex_def is implementation specific in every CMSIS-RTOS.
 typedef struct os_mutex_def  {
   uint32_t                   dummy;    ///< dummy value.
 } osMutexDef_t;
 /// Semaphore Definition structure contains setup information for a semaphore.
 /// \note CAN BE CHANGED: \b os_semaphore_def is implementation specific in every CMSIS-RTOS.
 typedef struct os_semaphore_def  {
   uint32_t                   dummy;    ///< dummy value.
 } osSemaphoreDef_t;
 /// Definition structure for memory block allocation.
 /// \note CAN BE CHANGED: \b os_pool_def is implementation specific in every CMSIS-RTOS.
 typedef struct os_pool_def  {
   uint32_t                 pool_sz;    ///< number of items (elements) in the pool
   uint32_t                 item_sz;    ///< size of an item
   void                       *pool;    ///< pointer to memory for pool
 } osPoolDef_t;
 /// Definition structure for message queue.
 /// \note CAN BE CHANGED: \b os_messageQ_def is implementation specific in every CMSIS-RTOS.
 typedef struct os_messageQ_def  {
   uint32_t                queue_sz;    ///< number of elements in the queue
   uint32_t                 item_sz;    ///< size of an item
   void                       *pool;    ///< memory array for messages
 } osMessageQDef_t;
 /// Definition structure for mail queue.
 /// \note CAN BE CHANGED: \b os_mailQ_def is implementation specific in every CMSIS-RTOS.
 typedef struct os_mailQ_def  {
   uint32_t                queue_sz;    ///< number of elements in the queue
   uint32_t                 item_sz;    ///< size of an item
   void                       *pool;    ///< memory array for mail
 } osMailQDef_t;
 /// Event structure contains detailed information about an event.
 /// \note MUST REMAIN UNCHANGED: \b os_event shall be consistent in every CMSIS-RTOS.
 ///       However the struct may be extended at the end.
 typedef struct  {
   osStatus                 status;     ///< status code: event or error information
   union  {
     uint32_t                    v;     ///< message as 32-bit value
     void                       *p;     ///< message or mail as void pointer
     int32_t               signals;     ///< signal flags
   } value;                             ///< event value
   union  {
     osMailQId             mail_id;     ///< mail id obtained by \ref osMailCreate
     osMessageQId       message_id;     ///< message id obtained by \ref osMessageCreate
   } def;                               ///< event definition
 } osEvent;
 //  ==== Kernel Control Functions ====
 /// Initialize the RTOS Kernel for creating objects.
 /// \return status code that indicates the execution status of the function.
 /// \note MUST REMAIN UNCHANGED: \b osKernelInitialize shall be consistent in every CMSIS-RTOS.
 osStatus osKernelInitialize (void);
 /// Start the RTOS Kernel.
 /// \return status code that indicates the execution status of the function.
 /// \note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS.
 osStatus osKernelStart (void);
 /// Check if the RTOS kernel is already started.
 /// \note MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS.
 /// \return 0 RTOS is not started, 1 RTOS is started.
 int32_t osKernelRunning(void);
 #if (defined (osFeature_SysTick)  &&  (osFeature_SysTick != 0))     // System Timer available
 /// Get the RTOS kernel system timer counter
 /// \note MUST REMAIN UNCHANGED: \b osKernelSysTick shall be consistent in every CMSIS-RTOS.
 /// \return RTOS kernel system timer as 32-bit value
 uint32_t osKernelSysTick (void);
 /// The RTOS kernel system timer frequency in Hz
 /// \note Reflects the system timer setting and is typically defined in a configuration file.
 #define osKernelSysTickFrequency 100000000
 /// Convert a microseconds value to a RTOS kernel system timer value.
 /// \param         microsec     time value in microseconds.
 /// \return time value normalized to the \ref osKernelSysTickFrequency
 #define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000)
 #endif    // System Timer available
 //  ==== Thread Management ====
 /// Create a Thread Definition with function, priority, and stack requirements.
 /// \param         name         name of the thread function.
 /// \param         priority     initial priority of the thread function.
 /// \param         instances    number of possible thread instances.
 /// \param         stacksz      stack size (in bytes) requirements for the thread function.
 /// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the
 ///       macro body is implementation specific in every CMSIS-RTOS.
 #if defined (osObjectsExternal)  // object is external
 #define osThreadDef(name, priority, instances, stacksz)  \
 extern const osThreadDef_t os_thread_def_##name
 #else                            // define the object
 #define osThreadDef(name, priority, instances, stacksz)  \
 const osThreadDef_t os_thread_def_##name = \
 { (name), (priority), (instances), (stacksz)  }
 #endif
 /// Access a Thread definition.
 /// \param         name          name of the thread definition object.
 /// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the
 ///       macro body is implementation specific in every CMSIS-RTOS.
 #define osThread(name)  \
 &os_thread_def_##name
 /// Create a thread and add it to Active Threads and set it to state READY.
 /// \param[in]     thread_def    thread definition referenced with \ref osThread.
 /// \param[in]     argument      pointer that is passed to the thread function as start argument.
 /// \return thread ID for reference by other functions or NULL in case of error.
 /// \note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS.
 osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument);
 /// Return the thread ID of the current running thread.
 /// \return thread ID for reference by other functions or NULL in case of error.
 /// \note MUST REMAIN UNCHANGED: \b osThreadGetId shall be consistent in every CMSIS-RTOS.
 osThreadId osThreadGetId (void);
 /// Terminate execution of a thread and remove it from Active Threads.
 /// \param[in]     thread_id   thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
 /// \return status code that indicates the execution status of the function.
 /// \note MUST REMAIN UNCHANGED: \b osThreadTerminate shall be consistent in every CMSIS-RTOS.
 osStatus osThreadTerminate (osThreadId thread_id);
 /// Pass control to next thread that is in state \b READY.
 /// \return status code that indicates the execution status of the function.
 /// \note MUST REMAIN UNCHANGED: \b osThreadYield shall be consistent in every CMSIS-RTOS.
 osStatus osThreadYield (void);
 /// Change priority of an active thread.
 /// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
 /// \param[in]     priority      new priority value for the thread function.
 /// \return status code that indicates the execution status of the function.
 /// \note MUST REMAIN UNCHANGED: \b osThreadSetPriority shall be consistent in every CMSIS-RTOS.
 osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority);
 /// Get current priority of an active thread.
 /// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
 /// \return current priority value of the thread function.
 /// \note MUST REMAIN UNCHANGED: \b osThreadGetPriority shall be consistent in every CMSIS-RTOS.
 osPriority osThreadGetPriority (osThreadId thread_id);
 //  ==== Generic Wait Functions ====
 /// Wait for Timeout (Time Delay).
 /// \param[in]     millisec      time delay value
 /// \return status code that indicates the execution status of the function.
 osStatus osDelay (uint32_t millisec);
 #if (defined (osFeature_Wait)  &&  (osFeature_Wait != 0))     // Generic Wait available
 /// Wait for Signal, Message, Mail, or Timeout.
 /// \param[in] millisec          timeout value or 0 in case of no time-out
 /// \return event that contains signal, message, or mail information or error code.
 /// \note MUST REMAIN UNCHANGED: \b osWait shall be consistent in every CMSIS-RTOS.
 osEvent osWait (uint32_t millisec);
 #endif  // Generic Wait available
 //  ==== Timer Management Functions ====
 /// Define a Timer object.
 /// \param         name          name of the timer object.
 /// \param         function      name of the timer call back function.
 /// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the
 ///       macro body is implementation specific in every CMSIS-RTOS.
 #if defined (osObjectsExternal)  // object is external
 #define osTimerDef(name, function)  \
 extern const osTimerDef_t os_timer_def_##name
 #else                            // define the object
 #define osTimerDef(name, function)  \
 const osTimerDef_t os_timer_def_##name = \
 { (function) }
 #endif
 /// Access a Timer definition.
 /// \param         name          name of the timer object.
 /// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the
 ///       macro body is implementation specific in every CMSIS-RTOS.
 #define osTimer(name) \
 &os_timer_def_##name
 /// Create a timer.
 /// \param[in]     timer_def     timer object referenced with \ref osTimer.
 /// \param[in]     type          osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.
 /// \param[in]     argument      argument to the timer call back function.
 /// \return timer ID for reference by other functions or NULL in case of error.
 /// \note MUST REMAIN UNCHANGED: \b osTimerCreate shall be consistent in every CMSIS-RTOS.
 osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument);
 /// Start or restart a timer.
 /// \param[in]     timer_id      timer ID obtained by \ref osTimerCreate.
 /// \param[in]     millisec      time delay value of the timer.
 /// \return status code that indicates the execution status of the function.
 /// \note MUST REMAIN UNCHANGED: \b osTimerStart shall be consistent in every CMSIS-RTOS.
 osStatus osTimerStart (osTimerId timer_id, uint32_t millisec);
 /// Stop the timer.
 /// \param[in]     timer_id      timer ID obtained by \ref osTimerCreate.
 /// \return status code that indicates the execution status of the function.
 /// \note MUST REMAIN UNCHANGED: \b osTimerStop shall be consistent in every CMSIS-RTOS.
 osStatus osTimerStop (osTimerId timer_id);
 /// Delete a timer that was created by \ref osTimerCreate.
 /// \param[in]     timer_id      timer ID obtained by \ref osTimerCreate.
 /// \return status code that indicates the execution status of the function.
 /// \note MUST REMAIN UNCHANGED: \b osTimerDelete shall be consistent in every CMSIS-RTOS.
 osStatus osTimerDelete (osTimerId timer_id);
 //  ==== Signal Management ====
 /// Set the specified Signal Flags of an active thread.
 /// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
 /// \param[in]     signals       specifies the signal flags of the thread that should be set.
 /// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
 /// \note MUST REMAIN UNCHANGED: \b osSignalSet shall be consistent in every CMSIS-RTOS.
 int32_t osSignalSet (osThreadId thread_id, int32_t signals);
 /// Clear the specified Signal Flags of an active thread.
 /// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
 /// \param[in]     signals       specifies the signal flags of the thread that shall be cleared.
 /// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
 /// \note MUST REMAIN UNCHANGED: \b osSignalClear shall be consistent in every CMSIS-RTOS.
 int32_t osSignalClear (osThreadId thread_id, int32_t signals);
 /// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread.
 /// \param[in]     signals       wait until all specified signal flags set or 0 for any single signal flag.
 /// \param[in]     millisec      timeout value or 0 in case of no time-out.
 /// \return event flag information or error code.
 /// \note MUST REMAIN UNCHANGED: \b osSignalWait shall be consistent in every CMSIS-RTOS.
 osEvent osSignalWait (int32_t signals, uint32_t millisec);
 //  ==== Mutex Management ====
 /// Define a Mutex.
 /// \param         name          name of the mutex object.
 /// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the
 ///       macro body is implementation specific in every CMSIS-RTOS.
 #if defined (osObjectsExternal)  // object is external
 #define osMutexDef(name)  \
 extern const osMutexDef_t os_mutex_def_##name
 #else                            // define the object
 #define osMutexDef(name)  \
 const osMutexDef_t os_mutex_def_##name = { 0 }
 #endif
 /// Access a Mutex definition.
 /// \param         name          name of the mutex object.
 /// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the
 ///       macro body is implementation specific in every CMSIS-RTOS.
 #define osMutex(name)  \
 &os_mutex_def_##name
 /// Create and Initialize a Mutex object.
 /// \param[in]     mutex_def     mutex definition referenced with \ref osMutex.
 /// \return mutex ID for reference by other functions or NULL in case of error.
 /// \note MUST REMAIN UNCHANGED: \b osMutexCreate shall be consistent in every CMSIS-RTOS.
 osMutexId osMutexCreate (const osMutexDef_t *mutex_def);
 /// Wait until a Mutex becomes available.
 /// \param[in]     mutex_id      mutex ID obtained by \ref osMutexCreate.
 /// \param[in]     millisec      timeout value or 0 in case of no time-out.
 /// \return status code that indicates the execution status of the function.
 /// \note MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS.
 osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec);
 /// Release a Mutex that was obtained by \ref osMutexWait.
 /// \param[in]     mutex_id      mutex ID obtained by \ref osMutexCreate.
 /// \return status code that indicates the execution status of the function.
 /// \note MUST REMAIN UNCHANGED: \b osMutexRelease shall be consistent in every CMSIS-RTOS.
 osStatus osMutexRelease (osMutexId mutex_id);
 /// Delete a Mutex that was created by \ref osMutexCreate.
 /// \param[in]     mutex_id      mutex ID obtained by \ref osMutexCreate.
 /// \return status code that indicates the execution status of the function.
 /// \note MUST REMAIN UNCHANGED: \b osMutexDelete shall be consistent in every CMSIS-RTOS.
 osStatus osMutexDelete (osMutexId mutex_id);
 //  ==== Semaphore Management Functions ====
 #if (defined (osFeature_Semaphore)  &&  (osFeature_Semaphore != 0))     // Semaphore available
 /// Define a Semaphore object.
 /// \param         name          name of the semaphore object.
 /// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the
 ///       macro body is implementation specific in every CMSIS-RTOS.
 #if defined (osObjectsExternal)  // object is external
 #define osSemaphoreDef(name)  \
 extern const osSemaphoreDef_t os_semaphore_def_##name
 #else                            // define the object
 #define osSemaphoreDef(name)  \
 const osSemaphoreDef_t os_semaphore_def_##name = { 0 }
 #endif
 /// Access a Semaphore definition.
 /// \param         name          name of the semaphore object.
 /// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the
 ///       macro body is implementation specific in every CMSIS-RTOS.
 #define osSemaphore(name)  \
 &os_semaphore_def_##name
 /// Create and Initialize a Semaphore object used for managing resources.
 /// \param[in]     semaphore_def semaphore definition referenced with \ref osSemaphore.
 /// \param[in]     count         number of available resources.
 /// \return semaphore ID for reference by other functions or NULL in case of error.
 /// \note MUST REMAIN UNCHANGED: \b osSemaphoreCreate shall be consistent in every CMSIS-RTOS.
 osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count);
 /// Wait until a Semaphore token becomes available.
 /// \param[in]     semaphore_id  semaphore object referenced with \ref osSemaphoreCreate.
 /// \param[in]     millisec      timeout value or 0 in case of no time-out.
 /// \return number of available tokens, or -1 in case of incorrect parameters.
 /// \note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS.
 int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec);
 /// Release a Semaphore token.
 /// \param[in]     semaphore_id  semaphore object referenced with \ref osSemaphoreCreate.
 /// \return status code that indicates the execution status of the function.
 /// \note MUST REMAIN UNCHANGED: \b osSemaphoreRelease shall be consistent in every CMSIS-RTOS.
 osStatus osSemaphoreRelease (osSemaphoreId semaphore_id);
 /// Delete a Semaphore that was created by \ref osSemaphoreCreate.
 /// \param[in]     semaphore_id  semaphore object referenced with \ref osSemaphoreCreate.
 /// \return status code that indicates the execution status of the function.
 /// \note MUST REMAIN UNCHANGED: \b osSemaphoreDelete shall be consistent in every CMSIS-RTOS.
 osStatus osSemaphoreDelete (osSemaphoreId semaphore_id);
 #endif     // Semaphore available
 //  ==== Memory Pool Management Functions ====
 #if (defined (osFeature_Pool)  &&  (osFeature_Pool != 0))  // Memory Pool Management available
 /// \brief Define a Memory Pool.
 /// \param         name          name of the memory pool.
 /// \param         no            maximum number of blocks (objects) in the memory pool.
 /// \param         type          data type of a single block (object).
 /// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the
 ///       macro body is implementation specific in every CMSIS-RTOS.
 #if defined (osObjectsExternal)  // object is external
 #define osPoolDef(name, no, type)   \
 extern const osPoolDef_t os_pool_def_##name
 #else                            // define the object
 #define osPoolDef(name, no, type)   \
 const osPoolDef_t os_pool_def_##name = \
 { (no), sizeof(type), NULL }
 #endif
 /// \brief Access a Memory Pool definition.
 /// \param         name          name of the memory pool
 /// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the
 ///       macro body is implementation specific in every CMSIS-RTOS.
 #define osPool(name) \
 &os_pool_def_##name
 /// Create and Initialize a memory pool.
 /// \param[in]     pool_def      memory pool definition referenced with \ref osPool.
 /// \return memory pool ID for reference by other functions or NULL in case of error.
 /// \note MUST REMAIN UNCHANGED: \b osPoolCreate shall be consistent in every CMSIS-RTOS.
 osPoolId osPoolCreate (const osPoolDef_t *pool_def);
 /// Allocate a memory block from a memory pool.
 /// \param[in]     pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
 /// \return address of the allocated memory block or NULL in case of no memory available.
 /// \note MUST REMAIN UNCHANGED: \b osPoolAlloc shall be consistent in every CMSIS-RTOS.
 void *osPoolAlloc (osPoolId pool_id);
 /// Allocate a memory block from a memory pool and set memory block to zero.
 /// \param[in]     pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
 /// \return address of the allocated memory block or NULL in case of no memory available.
 /// \note MUST REMAIN UNCHANGED: \b osPoolCAlloc shall be consistent in every CMSIS-RTOS.
 void *osPoolCAlloc (osPoolId pool_id);
 /// Return an allocated memory block back to a specific memory pool.
 /// \param[in]     pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
 /// \param[in]     block         address of the allocated memory block that is returned to the memory pool.
 /// \return status code that indicates the execution status of the function.
 /// \note MUST REMAIN UNCHANGED: \b osPoolFree shall be consistent in every CMSIS-RTOS.
 osStatus osPoolFree (osPoolId pool_id, void *block);
 #endif   // Memory Pool Management available
 //  ==== Message Queue Management Functions ====
 #if (defined (osFeature_MessageQ)  &&  (osFeature_MessageQ != 0))     // Message Queues available
 /// \brief Create a Message Queue Definition.
 /// \param         name          name of the queue.
 /// \param         queue_sz      maximum number of messages in the queue.
 /// \param         type          data type of a single message element (for debugger).
 /// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the
 ///       macro body is implementation specific in every CMSIS-RTOS.
 #if defined (osObjectsExternal)  // object is external
 #define osMessageQDef(name, queue_sz, type)   \
 extern const osMessageQDef_t os_messageQ_def_##name
 #else                            // define the object
 #define osMessageQDef(name, queue_sz, type)   \
 const osMessageQDef_t os_messageQ_def_##name = \
 { (queue_sz), sizeof (type)  }
 #endif
 /// \brief Access a Message Queue Definition.
 /// \param         name          name of the queue
 /// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the
 ///       macro body is implementation specific in every CMSIS-RTOS.
 #define osMessageQ(name) \
 &os_messageQ_def_##name
 /// Create and Initialize a Message Queue.
 /// \param[in]     queue_def     queue definition referenced with \ref osMessageQ.
 /// \param[in]     thread_id     thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
 /// \return message queue ID for reference by other functions or NULL in case of error.
 /// \note MUST REMAIN UNCHANGED: \b osMessageCreate shall be consistent in every CMSIS-RTOS.
 osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id);
 /// Put a Message to a Queue.
 /// \param[in]     queue_id      message queue ID obtained with \ref osMessageCreate.
 /// \param[in]     info          message information.
 /// \param[in]     millisec      timeout value or 0 in case of no time-out.
 /// \return status code that indicates the execution status of the function.
 /// \note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS.
 osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec);
 /// Get a Message or Wait for a Message from a Queue.
 /// \param[in]     queue_id      message queue ID obtained with \ref osMessageCreate.
 /// \param[in]     millisec      timeout value or 0 in case of no time-out.
 /// \return event information that includes status code.
 /// \note MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS.
 osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec);
 #endif     // Message Queues available
 //  ==== Mail Queue Management Functions ====
 #if (defined (osFeature_MailQ)  &&  (osFeature_MailQ != 0))     // Mail Queues available
 /// \brief Create a Mail Queue Definition.
 /// \param         name          name of the queue
 /// \param         queue_sz      maximum number of messages in queue
 /// \param         type          data type of a single message element
 /// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the
 ///       macro body is implementation specific in every CMSIS-RTOS.
 #if defined (osObjectsExternal)  // object is external
 #define osMailQDef(name, queue_sz, type) \
 extern const osMailQDef_t os_mailQ_def_##name
 #else                            // define the object
 #define osMailQDef(name, queue_sz, type) \
 const osMailQDef_t os_mailQ_def_##name =  \
 { (queue_sz), sizeof (type) }
 #endif
 /// \brief Access a Mail Queue Definition.
 /// \param         name          name of the queue
 /// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the
 ///       macro body is implementation specific in every CMSIS-RTOS.
 #define osMailQ(name)  \
 &os_mailQ_def_##name
 /// Create and Initialize mail queue.
 /// \param[in]     queue_def     reference to the mail queue definition obtain with \ref osMailQ
 /// \param[in]     thread_id     thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
 /// \return mail queue ID for reference by other functions or NULL in case of error.
 /// \note MUST REMAIN UNCHANGED: \b osMailCreate shall be consistent in every CMSIS-RTOS.
 osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id);
 /// Allocate a memory block from a mail.
 /// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
 /// \param[in]     millisec      timeout value or 0 in case of no time-out
 /// \return pointer to memory block that can be filled with mail or NULL in case of error.
 /// \note MUST REMAIN UNCHANGED: \b osMailAlloc shall be consistent in every CMSIS-RTOS.
 void *osMailAlloc (osMailQId queue_id, uint32_t millisec);
 /// Allocate a memory block from a mail and set memory block to zero.
 /// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
 /// \param[in]     millisec      timeout value or 0 in case of no time-out
 /// \return pointer to memory block that can be filled with mail or NULL in case of error.
 /// \note MUST REMAIN UNCHANGED: \b osMailCAlloc shall be consistent in every CMSIS-RTOS.
 void *osMailCAlloc (osMailQId queue_id, uint32_t millisec);
 /// Put a mail to a queue.
 /// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
 /// \param[in]     mail          memory block previously allocated with \ref osMailAlloc or \ref osMailCAlloc.
 /// \return status code that indicates the execution status of the function.
 /// \note MUST REMAIN UNCHANGED: \b osMailPut shall be consistent in every CMSIS-RTOS.
 osStatus osMailPut (osMailQId queue_id, void *mail);
 /// Get a mail from a queue.
 /// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
 /// \param[in]     millisec      timeout value or 0 in case of no time-out
 /// \return event that contains mail information or error code.
 /// \note MUST REMAIN UNCHANGED: \b osMailGet shall be consistent in every CMSIS-RTOS.
 osEvent osMailGet (osMailQId queue_id, uint32_t millisec);
 /// Free a memory block from a mail.
 /// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
 /// \param[in]     mail          pointer to the memory block that was obtained with \ref osMailGet.
 /// \return status code that indicates the execution status of the function.
 /// \note MUST REMAIN UNCHANGED: \b osMailFree shall be consistent in every CMSIS-RTOS.
 osStatus osMailFree (osMailQId queue_id, void *mail);
 #endif  // Mail Queues available
 #ifdef  __cplusplus
+}
 #endif
 #endif  // _CMSIS_OS_H

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