Files
@ af4bff132c45
Branch filter:
Location: therm/drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f031x6.h
af4bff132c45
228.6 KiB
text/plain
Remove old EEPROM r/w code
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685 2686 2687 2688 2689 2690 2691 2692 2693 2694 2695 2696 2697 2698 2699 2700 2701 2702 2703 2704 2705 2706 2707 2708 2709 2710 2711 2712 2713 2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731 2732 2733 2734 2735 2736 2737 2738 2739 2740 2741 2742 2743 2744 2745 2746 2747 2748 2749 2750 2751 2752 2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764 2765 2766 2767 2768 2769 2770 2771 2772 2773 2774 2775 2776 2777 2778 2779 2780 2781 2782 2783 2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809 2810 2811 2812 2813 2814 2815 2816 2817 2818 2819 2820 2821 2822 2823 2824 2825 2826 2827 2828 2829 2830 2831 2832 2833 2834 2835 2836 2837 2838 2839 2840 2841 2842 2843 2844 2845 2846 2847 2848 2849 2850 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861 2862 2863 2864 2865 2866 2867 2868 2869 2870 2871 2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 2886 2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899 2900 2901 2902 2903 2904 2905 2906 2907 2908 2909 2910 2911 2912 2913 2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924 2925 2926 2927 2928 2929 2930 2931 2932 2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943 2944 2945 2946 2947 2948 2949 2950 2951 2952 2953 2954 2955 2956 2957 2958 2959 2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970 2971 2972 2973 2974 2975 2976 2977 2978 2979 2980 2981 2982 2983 2984 2985 2986 2987 2988 2989 2990 2991 2992 2993 2994 2995 2996 2997 2998 2999 3000 3001 3002 3003 3004 3005 3006 3007 3008 3009 3010 3011 3012 3013 3014 3015 3016 3017 3018 3019 3020 3021 3022 3023 3024 3025 3026 3027 3028 3029 3030 3031 3032 3033 3034 3035 3036 3037 3038 3039 3040 3041 3042 3043 3044 3045 3046 3047 3048 3049 3050 3051 3052 3053 3054 3055 3056 3057 3058 3059 3060 3061 3062 3063 3064 3065 3066 3067 3068 3069 3070 3071 3072 3073 3074 3075 3076 3077 3078 3079 3080 3081 3082 3083 3084 3085 3086 3087 3088 3089 3090 3091 3092 3093 3094 3095 3096 3097 3098 3099 3100 3101 3102 3103 3104 3105 3106 3107 3108 3109 3110 3111 3112 3113 3114 3115 3116 3117 3118 3119 3120 3121 3122 3123 3124 3125 3126 3127 3128 3129 3130 3131 3132 3133 3134 3135 3136 3137 3138 3139 3140 3141 3142 3143 3144 3145 3146 3147 3148 3149 3150 3151 3152 3153 3154 3155 3156 3157 3158 3159 3160 3161 3162 3163 3164 3165 3166 3167 3168 3169 3170 3171 3172 3173 3174 3175 3176 3177 3178 3179 3180 3181 3182 3183 3184 3185 3186 3187 3188 3189 3190 3191 3192 3193 3194 3195 3196 3197 3198 3199 3200 3201 3202 3203 3204 3205 3206 3207 3208 3209 3210 3211 3212 3213 3214 3215 3216 3217 3218 3219 3220 3221 3222 3223 3224 3225 3226 3227 3228 3229 3230 3231 3232 3233 3234 3235 3236 3237 3238 3239 3240 3241 3242 3243 3244 3245 3246 3247 3248 3249 3250 3251 3252 3253 3254 3255 3256 3257 3258 3259 3260 | /**
******************************************************************************
* @file stm32f031x6.h
* @author MCD Application Team
* @version V2.1.0
* @date 03-Oct-2014
* @brief CMSIS STM32F031x4/STM32F031x6 devices Peripheral Access Layer Header File.
*
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
* - Macros to access peripheral’s registers hardware
*
******************************************************************************
* @attention
*
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/** @addtogroup CMSIS_Device
* @{
*/
/** @addtogroup stm32f031x6
* @{
*/
#ifndef __STM32F031x6_H
#define __STM32F031x6_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/** @addtogroup Configuration_section_for_CMSIS
* @{
*/
/**
* @brief Configuration of the Cortex-M0 Processor and Core Peripherals
*/
#define __CM0_REV 0 /*!< Core Revision r0p0 */
#define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */
#define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
/**
* @}
*/
/** @addtogroup Peripheral_interrupt_number_definition
* @{
*/
/**
* @brief STM32F031x4/STM32F031x6 device Interrupt Number Definition
*/
typedef enum
{
/****** Cortex-M0 Processor Exceptions Numbers **************************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
/****** STM32F031x4/STM32F031x6 specific Interrupt Numbers **************************************************/
WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
PVD_IRQn = 1, /*!< PVD Interrupts through EXTI Lines 16 */
RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */
FLASH_IRQn = 3, /*!< FLASH global Interrupt */
RCC_IRQn = 4, /*!< RCC global Interrupt */
EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */
ADC1_IRQn = 12, /*!< ADC1 global Interrupt */
TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
TIM2_IRQn = 15, /*!< TIM2 global Interrupt */
TIM3_IRQn = 16, /*!< TIM3 global Interrupt */
TIM14_IRQn = 19, /*!< TIM14 global Interrupt */
TIM16_IRQn = 21, /*!< TIM16 global Interrupt */
TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
SPI1_IRQn = 25, /*!< SPI1 global Interrupt */
USART1_IRQn = 27 /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
} IRQn_Type;
/**
* @}
*/
#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
#include "system_stm32f0xx.h" /* STM32F0xx System Header */
#include <stdint.h>
/** @addtogroup Peripheral_registers_structures
* @{
*/
/**
* @brief Analog to Digital Converter
*/
typedef struct
{
__IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
__IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
__IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
__IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
__IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
__IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
uint32_t RESERVED1; /*!< Reserved, 0x18 */
uint32_t RESERVED2; /*!< Reserved, 0x1C */
__IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
uint32_t RESERVED3; /*!< Reserved, 0x24 */
__IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
__IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
}ADC_TypeDef;
typedef struct
{
__IO uint32_t CCR;
}ADC_Common_TypeDef;
/**
* @brief CRC calculation unit
*/
typedef struct
{
__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
uint8_t RESERVED0; /*!< Reserved, 0x05 */
uint16_t RESERVED1; /*!< Reserved, 0x06 */
__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
uint32_t RESERVED2; /*!< Reserved, 0x0C */
__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
}CRC_TypeDef;
/**
* @brief Debug MCU
*/
typedef struct
{
__IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
__IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
__IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
__IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
}DBGMCU_TypeDef;
/**
* @brief DMA Controller
*/
typedef struct
{
__IO uint32_t CCR; /*!< DMA channel x configuration register */
__IO uint32_t CNDTR; /*!< DMA channel x number of data register */
__IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
__IO uint32_t CMAR; /*!< DMA channel x memory address register */
}DMA_Channel_TypeDef;
typedef struct
{
__IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
__IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
}DMA_TypeDef;
/**
* @brief External Interrupt/Event Controller
*/
typedef struct
{
__IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
__IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
__IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
__IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
__IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
__IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
}EXTI_TypeDef;
/**
* @brief FLASH Registers
*/
typedef struct
{
__IO uint32_t ACR; /*!<FLASH access control register, Address offset: 0x00 */
__IO uint32_t KEYR; /*!<FLASH key register, Address offset: 0x04 */
__IO uint32_t OPTKEYR; /*!<FLASH OPT key register, Address offset: 0x08 */
__IO uint32_t SR; /*!<FLASH status register, Address offset: 0x0C */
__IO uint32_t CR; /*!<FLASH control register, Address offset: 0x10 */
__IO uint32_t AR; /*!<FLASH address register, Address offset: 0x14 */
__IO uint32_t RESERVED; /*!< Reserved, 0x18 */
__IO uint32_t OBR; /*!<FLASH option bytes register, Address offset: 0x1C */
__IO uint32_t WRPR; /*!<FLASH option bytes register, Address offset: 0x20 */
}FLASH_TypeDef;
/**
* @brief Option Bytes Registers
*/
typedef struct
{
__IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */
__IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */
__IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
__IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
__IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */
__IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */
__IO uint16_t WRP2; /*!< FLASH option byte write protection 2, Address offset: 0x0C */
__IO uint16_t WRP3; /*!< FLASH option byte write protection 3, Address offset: 0x0E */
}OB_TypeDef;
/**
* @brief General Purpose I/O
*/
typedef struct
{
__IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
__IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
__IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
__IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
__IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
}GPIO_TypeDef;
/**
* @brief SysTem Configuration
*/
typedef struct
{
__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
uint32_t RESERVED; /*!< Reserved, 0x04 */
__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
}SYSCFG_TypeDef;
/**
* @brief Inter-integrated Circuit Interface
*/
typedef struct
{
__IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
__IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
__IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
__IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
__IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
__IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
__IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
__IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
__IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
__IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
}I2C_TypeDef;
/**
* @brief Independent WATCHDOG
*/
typedef struct
{
__IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
__IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
__IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
__IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
__IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
}IWDG_TypeDef;
/**
* @brief Power Control
*/
typedef struct
{
__IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
__IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
}PWR_TypeDef;
/**
* @brief Reset and Clock Control
*/
typedef struct
{
__IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
__IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
__IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
__IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
__IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
__IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
__IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
__IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
__IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
__IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
__IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
__IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
__IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
__IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */
}RCC_TypeDef;
/**
* @brief Real-Time Clock
*/
typedef struct
{
__IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
__IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
__IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
__IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
__IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */
__IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
uint32_t RESERVED3; /*!< Reserved, Address offset: 0x20 */
__IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
__IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
__IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
__IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
__IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
__IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
__IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
__IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
__IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
uint32_t RESERVED4; /*!< Reserved, Address offset: 0x48 */
uint32_t RESERVED5; /*!< Reserved, Address offset: 0x4C */
__IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
__IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
__IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
__IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
__IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
}RTC_TypeDef;
/**
* @brief Serial Peripheral Interface
*/
typedef struct
{
__IO uint16_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
uint16_t RESERVED0; /*!< Reserved, 0x02 */
__IO uint16_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
uint16_t RESERVED1; /*!< Reserved, 0x06 */
__IO uint16_t SR; /*!< SPI Status register, Address offset: 0x08 */
uint16_t RESERVED2; /*!< Reserved, 0x0A */
__IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */
uint16_t RESERVED3; /*!< Reserved, 0x0E */
__IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
uint16_t RESERVED4; /*!< Reserved, 0x12 */
__IO uint16_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
uint16_t RESERVED5; /*!< Reserved, 0x16 */
__IO uint16_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
uint16_t RESERVED6; /*!< Reserved, 0x1A */
__IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
uint16_t RESERVED7; /*!< Reserved, 0x1E */
__IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
uint16_t RESERVED8; /*!< Reserved, 0x22 */
}SPI_TypeDef;
/**
* @brief TIM
*/
typedef struct
{
__IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
__IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
__IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
__IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
__IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
__IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
__IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
__IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
__IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
__IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
__IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
__IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
__IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
__IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
__IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
__IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
__IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
__IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
__IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
__IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
}TIM_TypeDef;
/**
* @brief Universal Synchronous Asynchronous Receiver Transmitter
*/
typedef struct
{
__IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
__IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
__IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
__IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
__IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
__IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
__IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
__IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
__IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
uint16_t RESERVED1; /*!< Reserved, 0x26 */
__IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
uint16_t RESERVED2; /*!< Reserved, 0x2A */
}USART_TypeDef;
/**
* @brief Window WATCHDOG
*/
typedef struct
{
__IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
__IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
__IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
}WWDG_TypeDef;
/**
* @}
*/
/** @addtogroup Peripheral_memory_map
* @{
*/
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
/*!< Peripheral memory map */
#define APBPERIPH_BASE PERIPH_BASE
#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
#define TIM2_BASE (APBPERIPH_BASE + 0x00000000)
#define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
#define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
#define RTC_BASE (APBPERIPH_BASE + 0x00002800)
#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
#define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
#define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
#define PWR_BASE (APBPERIPH_BASE + 0x00007000)
#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
#define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
#define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
#define ADC_BASE (APBPERIPH_BASE + 0x00012708)
#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
#define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
#define USART1_BASE (APBPERIPH_BASE + 0x00013800)
#define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
#define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
#define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
#define OB_BASE ((uint32_t)0x1FFFF800) /*!< FLASH Option Bytes base address */
#define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
#define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
#define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
#define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
#define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
/**
* @}
*/
/** @addtogroup Peripheral_declaration
* @{
*/
#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
#define RTC ((RTC_TypeDef *) RTC_BASE)
#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
#define PWR ((PWR_TypeDef *) PWR_BASE)
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
#define USART1 ((USART_TypeDef *) USART1_BASE)
#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
#define OB ((OB_TypeDef *) OB_BASE)
#define RCC ((RCC_TypeDef *) RCC_BASE)
#define CRC ((CRC_TypeDef *) CRC_BASE)
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
/**
* @}
*/
/** @addtogroup Exported_constants
* @{
*/
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
/******************************************************************************/
/* Peripheral Registers Bits Definition */
/******************************************************************************/
/******************************************************************************/
/* */
/* Analog to Digital Converter (ADC) */
/* */
/******************************************************************************/
/******************** Bits definition for ADC_ISR register ******************/
#define ADC_ISR_AWD ((uint32_t)0x00000080) /*!< Analog watchdog flag */
#define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< Overrun flag */
#define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /*!< End of Sequence flag */
#define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< End of Conversion */
#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< End of sampling flag */
#define ADC_ISR_ADRDY ((uint32_t)0x00000001) /*!< ADC Ready */
/* Old EOSEQ bit definition, maintained for legacy purpose */
#define ADC_ISR_EOS ADC_ISR_EOSEQ
/******************** Bits definition for ADC_IER register ******************/
#define ADC_IER_AWDIE ((uint32_t)0x00000080) /*!< Analog Watchdog interrupt enable */
#define ADC_IER_OVRIE ((uint32_t)0x00000010) /*!< Overrun interrupt enable */
#define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /*!< End of Sequence of conversion interrupt enable */
#define ADC_IER_EOCIE ((uint32_t)0x00000004) /*!< End of Conversion interrupt enable */
#define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /*!< End of sampling interrupt enable */
#define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /*!< ADC Ready interrupt enable */
/* Old EOSEQIE bit definition, maintained for legacy purpose */
#define ADC_IER_EOSIE ADC_IER_EOSEQIE
/******************** Bits definition for ADC_CR register *******************/
#define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC calibration */
#define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC stop of conversion command */
#define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC start of conversion */
#define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC disable command */
#define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC enable control */
/******************* Bits definition for ADC_CFGR1 register *****************/
#define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
#define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /*!< Bit 0 */
#define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /*!< Bit 1 */
#define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /*!< Bit 2 */
#define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /*!< Bit 3 */
#define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /*!< Bit 4 */
#define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
#define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /*!< Enable the watchdog on a single channel or on all channels */
#define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /*!< Discontinuous mode on regular channels */
#define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /*!< ADC auto power off */
#define ADC_CFGR1_WAIT ((uint32_t)0x00004000) /*!< ADC wait conversion mode */
#define ADC_CFGR1_CONT ((uint32_t)0x00002000) /*!< Continuous Conversion */
#define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /*!< Overrun mode */
#define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
#define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /*!< Bit 0 */
#define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /*!< Bit 1 */
#define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
#define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /*!< Bit 0 */
#define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /*!< Bit 1 */
#define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /*!< Bit 2 */
#define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /*!< Data Alignment */
#define ADC_CFGR1_RES ((uint32_t)0x00000018) /*!< RES[1:0] bits (Resolution) */
#define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /*!< Bit 0 */
#define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /*!< Bit 1 */
#define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /*!< Sequence scan direction */
#define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /*!< Direct memory access configuration */
#define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /*!< Direct memory access enable */
/* Old WAIT bit definition, maintained for legacy purpose */
#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
/******************* Bits definition for ADC_CFGR2 register *****************/
#define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000) /*!< ADC clock mode */
#define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000) /*!< ADC clocked by PCLK div4 */
#define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000) /*!< ADC clocked by PCLK div2 */
/* Old bit definition, maintained for legacy purpose */
#define ADC_CFGR2_JITOFFDIV4 ADC_CFGR2_CKMODE_1 /*!< ADC clocked by PCLK div4 */
#define ADC_CFGR2_JITOFFDIV2 ADC_CFGR2_CKMODE_0 /*!< ADC clocked by PCLK div2 */
/****************** Bit definition for ADC_SMPR register ********************/
#define ADC_SMPR_SMP ((uint32_t)0x00000007) /*!< SMP[2:0] bits (Sampling time selection) */
#define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /*!< Bit 1 */
#define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /*!< Bit 2 */
/* Old bit definition, maintained for legacy purpose */
#define ADC_SMPR1_SMPR ADC_SMPR_SMP /*!< SMP[2:0] bits (Sampling time selection) */
#define ADC_SMPR1_SMPR_0 ADC_SMPR_SMP_0 /*!< Bit 0 */
#define ADC_SMPR1_SMPR_1 ADC_SMPR_SMP_1 /*!< Bit 1 */
#define ADC_SMPR1_SMPR_2 ADC_SMPR_SMP_2 /*!< Bit 2 */
/******************* Bit definition for ADC_TR register ********************/
#define ADC_TR_HT ((uint32_t)0x0FFF0000) /*!< Analog watchdog high threshold */
#define ADC_TR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
/* Old bit definition, maintained for legacy purpose */
#define ADC_HTR_HT ADC_TR_HT /*!< Analog watchdog high threshold */
#define ADC_LTR_LT ADC_TR_LT /*!< Analog watchdog low threshold */
/****************** Bit definition for ADC_CHSELR register ******************/
#define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /*!< Channel 18 selection */
#define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /*!< Channel 17 selection */
#define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /*!< Channel 16 selection */
#define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /*!< Channel 15 selection */
#define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /*!< Channel 14 selection */
#define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /*!< Channel 13 selection */
#define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /*!< Channel 12 selection */
#define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /*!< Channel 11 selection */
#define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /*!< Channel 10 selection */
#define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /*!< Channel 9 selection */
#define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /*!< Channel 8 selection */
#define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /*!< Channel 7 selection */
#define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /*!< Channel 6 selection */
#define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /*!< Channel 5 selection */
#define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /*!< Channel 4 selection */
#define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /*!< Channel 3 selection */
#define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /*!< Channel 2 selection */
#define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /*!< Channel 1 selection */
#define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /*!< Channel 0 selection */
/******************** Bit definition for ADC_DR register ********************/
#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
/******************* Bit definition for ADC_CCR register ********************/
#define ADC_CCR_VBATEN ((uint32_t)0x01000000) /*!< Voltage battery enable */
#define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Tempurature sensore enable */
#define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */
/******************************************************************************/
/* */
/* CRC calculation unit (CRC) */
/* */
/******************************************************************************/
/******************* Bit definition for CRC_DR register *********************/
#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
/******************* Bit definition for CRC_IDR register ********************/
#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
/******************** Bit definition for CRC_CR register ********************/
#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
#define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< REV_IN Bit 0 */
#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< REV_IN Bit 1 */
#define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
/******************* Bit definition for CRC_INIT register *******************/
#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
/******************************************************************************/
/* */
/* Debug MCU (DBGMCU) */
/* */
/******************************************************************************/
/**************** Bit definition for DBGMCU_IDCODE register *****************/
#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
/****************** Bit definition for DBGMCU_CR register *******************/
#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
/****************** Bit definition for DBGMCU_APB1_FZ register **************/
#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */
#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /*!< TIM3 counter stopped when core is halted */
#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) /*!< TIM14 counter stopped when core is halted */
#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Calendar frozen when core is halted */
#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */
#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */
#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
/****************** Bit definition for DBGMCU_APB2_FZ register **************/
#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000800) /*!< TIM1 counter stopped when core is halted */
#define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00020000) /*!< TIM16 counter stopped when core is halted */
#define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00040000) /*!< TIM17 counter stopped when core is halted */
/******************************************************************************/
/* */
/* DMA Controller (DMA) */
/* */
/******************************************************************************/
/******************* Bit definition for DMA_ISR register ********************/
#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
/******************* Bit definition for DMA_IFCR register *******************/
#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
/******************* Bit definition for DMA_CCR register ********************/
#define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
#define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
#define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
#define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
#define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
#define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
#define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
#define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
#define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
/****************** Bit definition for DMA_CNDTR register *******************/
#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
/****************** Bit definition for DMA_CPAR register ********************/
#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
/****************** Bit definition for DMA_CMAR register ********************/
#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
/******************************************************************************/
/* */
/* External Interrupt/Event Controller (EXTI) */
/* */
/******************************************************************************/
/******************* Bit definition for EXTI_IMR register *******************/
#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
#define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
/****************** Bit definition for EXTI_EMR register ********************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
#define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
/******************* Bit definition for EXTI_RTSR register ******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
/******************* Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
/******************* Bit definition for EXTI_SWIER register *******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
/****************** Bit definition for EXTI_PR register *********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
/******************************************************************************/
/* */
/* FLASH and Option Bytes Registers */
/* */
/******************************************************************************/
/******************* Bit definition for FLASH_ACR register ******************/
#define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< LATENCY bit (Latency) */
#define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
#define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
/****************** Bit definition for FLASH_KEYR register ******************/
#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
/***************** Bit definition for FLASH_OPTKEYR register ****************/
#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
/****************** FLASH Keys **********************************************/
#define FLASH_FKEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
#define FLASH_FKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
to unlock the write access to the FPEC. */
#define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */
#define FLASH_OPTKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash option key2: used with FLASH_OPTKEY1 to
unlock the write access to the option byte block */
/****************** Bit definition for FLASH_SR register *******************/
#define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
#define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
#define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /*!< Write Protection Error */
#define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
#define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /*!< Legacy of Write Protection Error */
/******************* Bit definition for FLASH_CR register *******************/
#define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
#define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
#define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
#define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
#define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
#define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
#define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
#define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
#define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
#define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
#define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< Option Bytes Loader Launch */
/******************* Bit definition for FLASH_AR register *******************/
#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
/****************** Bit definition for FLASH_OBR register *******************/
#define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
#define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
#define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */
#define FLASH_OBR_USER ((uint32_t)0x00003700) /*!< User Option Bytes */
#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA power supply supervisor */
/* Old BOOT1 bit definition, maintained for legacy purpose */
#define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
/* Old OBR_VDDA bit definition, maintained for legacy purpose */
#define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
/****************** Bit definition for FLASH_WRPR register ******************/
#define FLASH_WRPR_WRP ((uint32_t)0x0000FFFF) /*!< Write Protect */
/*----------------------------------------------------------------------------*/
/****************** Bit definition for OB_RDP register **********************/
#define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
#define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
/****************** Bit definition for OB_USER register *********************/
#define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
#define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
/****************** Bit definition for OB_WRP0 register *********************/
#define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
#define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
/****************** Bit definition for OB_WRP1 register *********************/
#define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
#define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
/******************************************************************************/
/* */
/* General Purpose IOs (GPIO) */
/* */
/******************************************************************************/
/******************* Bit definition for GPIO_MODER register *****************/
#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
/****************** Bit definition for GPIO_OTYPER register *****************/
#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
/**************** Bit definition for GPIO_OSPEEDR register ******************/
#define GPIO_OSPEEDR_OSPEEDR0 ((uint32_t)0x00000003)
#define GPIO_OSPEEDR_OSPEEDR0_0 ((uint32_t)0x00000001)
#define GPIO_OSPEEDR_OSPEEDR0_1 ((uint32_t)0x00000002)
#define GPIO_OSPEEDR_OSPEEDR1 ((uint32_t)0x0000000C)
#define GPIO_OSPEEDR_OSPEEDR1_0 ((uint32_t)0x00000004)
#define GPIO_OSPEEDR_OSPEEDR1_1 ((uint32_t)0x00000008)
#define GPIO_OSPEEDR_OSPEEDR2 ((uint32_t)0x00000030)
#define GPIO_OSPEEDR_OSPEEDR2_0 ((uint32_t)0x00000010)
#define GPIO_OSPEEDR_OSPEEDR2_1 ((uint32_t)0x00000020)
#define GPIO_OSPEEDR_OSPEEDR3 ((uint32_t)0x000000C0)
#define GPIO_OSPEEDR_OSPEEDR3_0 ((uint32_t)0x00000040)
#define GPIO_OSPEEDR_OSPEEDR3_1 ((uint32_t)0x00000080)
#define GPIO_OSPEEDR_OSPEEDR4 ((uint32_t)0x00000300)
#define GPIO_OSPEEDR_OSPEEDR4_0 ((uint32_t)0x00000100)
#define GPIO_OSPEEDR_OSPEEDR4_1 ((uint32_t)0x00000200)
#define GPIO_OSPEEDR_OSPEEDR5 ((uint32_t)0x00000C00)
#define GPIO_OSPEEDR_OSPEEDR5_0 ((uint32_t)0x00000400)
#define GPIO_OSPEEDR_OSPEEDR5_1 ((uint32_t)0x00000800)
#define GPIO_OSPEEDR_OSPEEDR6 ((uint32_t)0x00003000)
#define GPIO_OSPEEDR_OSPEEDR6_0 ((uint32_t)0x00001000)
#define GPIO_OSPEEDR_OSPEEDR6_1 ((uint32_t)0x00002000)
#define GPIO_OSPEEDR_OSPEEDR7 ((uint32_t)0x0000C000)
#define GPIO_OSPEEDR_OSPEEDR7_0 ((uint32_t)0x00004000)
#define GPIO_OSPEEDR_OSPEEDR7_1 ((uint32_t)0x00008000)
#define GPIO_OSPEEDR_OSPEEDR8 ((uint32_t)0x00030000)
#define GPIO_OSPEEDR_OSPEEDR8_0 ((uint32_t)0x00010000)
#define GPIO_OSPEEDR_OSPEEDR8_1 ((uint32_t)0x00020000)
#define GPIO_OSPEEDR_OSPEEDR9 ((uint32_t)0x000C0000)
#define GPIO_OSPEEDR_OSPEEDR9_0 ((uint32_t)0x00040000)
#define GPIO_OSPEEDR_OSPEEDR9_1 ((uint32_t)0x00080000)
#define GPIO_OSPEEDR_OSPEEDR10 ((uint32_t)0x00300000)
#define GPIO_OSPEEDR_OSPEEDR10_0 ((uint32_t)0x00100000)
#define GPIO_OSPEEDR_OSPEEDR10_1 ((uint32_t)0x00200000)
#define GPIO_OSPEEDR_OSPEEDR11 ((uint32_t)0x00C00000)
#define GPIO_OSPEEDR_OSPEEDR11_0 ((uint32_t)0x00400000)
#define GPIO_OSPEEDR_OSPEEDR11_1 ((uint32_t)0x00800000)
#define GPIO_OSPEEDR_OSPEEDR12 ((uint32_t)0x03000000)
#define GPIO_OSPEEDR_OSPEEDR12_0 ((uint32_t)0x01000000)
#define GPIO_OSPEEDR_OSPEEDR12_1 ((uint32_t)0x02000000)
#define GPIO_OSPEEDR_OSPEEDR13 ((uint32_t)0x0C000000)
#define GPIO_OSPEEDR_OSPEEDR13_0 ((uint32_t)0x04000000)
#define GPIO_OSPEEDR_OSPEEDR13_1 ((uint32_t)0x08000000)
#define GPIO_OSPEEDR_OSPEEDR14 ((uint32_t)0x30000000)
#define GPIO_OSPEEDR_OSPEEDR14_0 ((uint32_t)0x10000000)
#define GPIO_OSPEEDR_OSPEEDR14_1 ((uint32_t)0x20000000)
#define GPIO_OSPEEDR_OSPEEDR15 ((uint32_t)0xC0000000)
#define GPIO_OSPEEDR_OSPEEDR15_0 ((uint32_t)0x40000000)
#define GPIO_OSPEEDR_OSPEEDR15_1 ((uint32_t)0x80000000)
/* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
/******************* Bit definition for GPIO_PUPDR register ******************/
#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
/******************* Bit definition for GPIO_IDR register *******************/
#define GPIO_IDR_0 ((uint32_t)0x00000001)
#define GPIO_IDR_1 ((uint32_t)0x00000002)
#define GPIO_IDR_2 ((uint32_t)0x00000004)
#define GPIO_IDR_3 ((uint32_t)0x00000008)
#define GPIO_IDR_4 ((uint32_t)0x00000010)
#define GPIO_IDR_5 ((uint32_t)0x00000020)
#define GPIO_IDR_6 ((uint32_t)0x00000040)
#define GPIO_IDR_7 ((uint32_t)0x00000080)
#define GPIO_IDR_8 ((uint32_t)0x00000100)
#define GPIO_IDR_9 ((uint32_t)0x00000200)
#define GPIO_IDR_10 ((uint32_t)0x00000400)
#define GPIO_IDR_11 ((uint32_t)0x00000800)
#define GPIO_IDR_12 ((uint32_t)0x00001000)
#define GPIO_IDR_13 ((uint32_t)0x00002000)
#define GPIO_IDR_14 ((uint32_t)0x00004000)
#define GPIO_IDR_15 ((uint32_t)0x00008000)
/****************** Bit definition for GPIO_ODR register ********************/
#define GPIO_ODR_0 ((uint32_t)0x00000001)
#define GPIO_ODR_1 ((uint32_t)0x00000002)
#define GPIO_ODR_2 ((uint32_t)0x00000004)
#define GPIO_ODR_3 ((uint32_t)0x00000008)
#define GPIO_ODR_4 ((uint32_t)0x00000010)
#define GPIO_ODR_5 ((uint32_t)0x00000020)
#define GPIO_ODR_6 ((uint32_t)0x00000040)
#define GPIO_ODR_7 ((uint32_t)0x00000080)
#define GPIO_ODR_8 ((uint32_t)0x00000100)
#define GPIO_ODR_9 ((uint32_t)0x00000200)
#define GPIO_ODR_10 ((uint32_t)0x00000400)
#define GPIO_ODR_11 ((uint32_t)0x00000800)
#define GPIO_ODR_12 ((uint32_t)0x00001000)
#define GPIO_ODR_13 ((uint32_t)0x00002000)
#define GPIO_ODR_14 ((uint32_t)0x00004000)
#define GPIO_ODR_15 ((uint32_t)0x00008000)
/****************** Bit definition for GPIO_BSRR register ********************/
#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
/****************** Bit definition for GPIO_LCKR register ********************/
#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
/****************** Bit definition for GPIO_AFRL register ********************/
#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
/****************** Bit definition for GPIO_AFRH register ********************/
#define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
#define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
#define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
#define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
#define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
#define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
#define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
#define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
/****************** Bit definition for GPIO_BRR register *********************/
#define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
#define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
#define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
#define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
#define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
#define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
#define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
#define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
#define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
#define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
#define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
#define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
#define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
#define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
#define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
#define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
/******************************************************************************/
/* */
/* Inter-integrated Circuit Interface (I2C) */
/* */
/******************************************************************************/
/******************* Bit definition for I2C_CR1 register *******************/
#define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
#define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
#define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
#define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
#define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
#define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
#define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
#define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
#define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
#define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
/****************** Bit definition for I2C_CR2 register ********************/
#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
#define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
#define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
#define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
#define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
#define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
#define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
#define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
#define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
/******************* Bit definition for I2C_OAR1 register ******************/
#define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
/******************* Bit definition for I2C_OAR2 register ******************/
#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
/******************* Bit definition for I2C_TIMINGR register ****************/
#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
/******************* Bit definition for I2C_TIMEOUTR register ****************/
#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
/****************** Bit definition for I2C_ISR register ********************/
#define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
#define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
#define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
#define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
#define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
#define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
#define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
#define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
#define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
#define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
#define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
#define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
#define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
#define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
#define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
/****************** Bit definition for I2C_ICR register ********************/
#define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
#define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
#define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
#define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
#define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
#define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
#define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
#define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
/****************** Bit definition for I2C_PECR register *******************/
#define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
/****************** Bit definition for I2C_RXDR register *********************/
#define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
/****************** Bit definition for I2C_TXDR register *******************/
#define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
/*****************************************************************************/
/* */
/* Independent WATCHDOG (IWDG) */
/* */
/*****************************************************************************/
/******************* Bit definition for IWDG_KR register *******************/
#define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!< Key value (write only, read 0000h) */
/******************* Bit definition for IWDG_PR register *******************/
#define IWDG_PR_PR ((uint32_t)0x07) /*!< PR[2:0] (Prescaler divider) */
#define IWDG_PR_PR_0 ((uint32_t)0x01) /*!< Bit 0 */
#define IWDG_PR_PR_1 ((uint32_t)0x02) /*!< Bit 1 */
#define IWDG_PR_PR_2 ((uint32_t)0x04) /*!< Bit 2 */
/******************* Bit definition for IWDG_RLR register ******************/
#define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!< Watchdog counter reload value */
/******************* Bit definition for IWDG_SR register *******************/
#define IWDG_SR_PVU ((uint32_t)0x01) /*!< Watchdog prescaler value update */
#define IWDG_SR_RVU ((uint32_t)0x02) /*!< Watchdog counter reload value update */
#define IWDG_SR_WVU ((uint32_t)0x04) /*!< Watchdog counter window value update */
/******************* Bit definition for IWDG_KR register *******************/
#define IWDG_WINR_WIN ((uint32_t)0x0FFF) /*!< Watchdog counter window value */
/*****************************************************************************/
/* */
/* Power Control (PWR) */
/* */
/*****************************************************************************/
/******************** Bit definition for PWR_CR register *******************/
#define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-power Deepsleep */
#define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
#define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
#define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
#define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
#define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
/*!< PVD level configuration */
#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
/******************* Bit definition for PWR_CSR register *******************/
#define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
#define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
#define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
#define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /*!< Internal voltage reference (VREFINT) ready flag */
#define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
#define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
/*****************************************************************************/
/* */
/* Reset and Clock Control */
/* */
/*****************************************************************************/
/******************** Bit definition for RCC_CR register *******************/
#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) /*!<Bit 0 */
#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) /*!<Bit 1 */
#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) /*!<Bit 2 */
#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) /*!<Bit 3 */
#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) /*!<Bit 4 */
#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
/******************** Bit definition for RCC_CFGR register *****************/
/*!< SW configuration */
#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
/*!< SWS configuration */
#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
/*!< HPRE configuration */
#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
/*!< PPRE configuration */
#define RCC_CFGR_PPRE ((uint32_t)0x00000700) /*!< PRE[2:0] bits (APB prescaler) */
#define RCC_CFGR_PPRE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
#define RCC_CFGR_PPRE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
#define RCC_CFGR_PPRE_2 ((uint32_t)0x00000400) /*!< Bit 2 */
#define RCC_CFGR_PPRE_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
#define RCC_CFGR_PPRE_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
#define RCC_CFGR_PPRE_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
#define RCC_CFGR_PPRE_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
#define RCC_CFGR_PPRE_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
/*!< ADCPPRE configuration */
#define RCC_CFGR_ADCPRE ((uint32_t)0x00004000) /*!< ADCPRE bit (ADC prescaler) */
#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK divided by 2 */
#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK divided by 4 */
#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
#define RCC_CFGR_PLLSRC_HSI_DIV2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
#define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /*!< HSE/PREDIV clock selected as PLL entry clock source */
#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< HSE/PREDIV clock not divided for PLL entry */
#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 ((uint32_t)0x00020000) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
/*!< PLLMUL configuration */
#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
#define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
#define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
#define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
#define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
#define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
#define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
#define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
#define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
#define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
#define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
/*!< MCO configuration */
#define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */
#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
#define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */
#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
#define RCC_CFGR_MCO_HSI14 ((uint32_t)0x01000000) /*!< HSI14 clock selected as MCO source */
#define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */
#define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */
#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
#define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /*!< MCO prescaler */
#define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000) /*!< MCO is divided by 1 */
#define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000) /*!< MCO is divided by 2 */
#define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000) /*!< MCO is divided by 4 */
#define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000) /*!< MCO is divided by 8 */
#define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000) /*!< MCO is divided by 16 */
#define RCC_CFGR_MCOPRE_DIV32 ((uint32_t)0x50000000) /*!< MCO is divided by 32 */
#define RCC_CFGR_MCOPRE_DIV64 ((uint32_t)0x60000000) /*!< MCO is divided by 64 */
#define RCC_CFGR_MCOPRE_DIV128 ((uint32_t)0x70000000) /*!< MCO is divided by 128 */
#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */
/*!<****************** Bit definition for RCC_CIR register *****************/
#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
#define RCC_CIR_HSI14RDYF ((uint32_t)0x00000020) /*!< HSI14 Ready Interrupt flag */
#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
#define RCC_CIR_HSI14RDYIE ((uint32_t)0x00002000) /*!< HSI14 Ready Interrupt Enable */
#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
#define RCC_CIR_HSI14RDYC ((uint32_t)0x00200000) /*!< HSI14 Ready Interrupt Clear */
#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
/***************** Bit definition for RCC_APB2RSTR register ****************/
#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG clock reset */
#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200) /*!< ADC clock reset */
#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 clock reset */
#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 clock reset */
#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 clock reset */
#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 clock reset */
#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 clock reset */
#define RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) /*!< DBGMCU clock reset */
/*!< Old ADC1 clock reset bit definition maintained for legacy purpose */
#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
/***************** Bit definition for RCC_APB1RSTR register ****************/
#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 clock reset */
#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 clock reset */
#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< Timer 14 clock reset */
#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog clock reset */
#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 clock reset */
#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR clock reset */
/****************** Bit definition for RCC_AHBENR register *****************/
#define RCC_AHBENR_DMAEN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
#define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
#define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
#define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
#define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */
#define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */
#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
/* Old Bit definition maintained for legacy purpose */
#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
#define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */
/***************** Bit definition for RCC_APB2ENR register *****************/
#define RCC_APB2ENR_SYSCFGCOMPEN ((uint32_t)0x00000001) /*!< SYSCFG and comparator clock enable */
#define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200) /*!< ADC1 clock enable */
#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */
#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */
#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */
#define RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) /*!< DBGMCU clock enable */
/* Old Bit definition maintained for legacy purpose */
#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /*!< SYSCFG clock enable */
#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
/***************** Bit definition for RCC_APB1ENR register *****************/
#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< Timer 14 clock enable */
#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C1 clock enable */
#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
/******************* Bit definition for RCC_BDCR register ******************/
#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
#define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
#define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */
#define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */
#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
/*!< RTC configuration */
#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
/******************* Bit definition for RCC_CSR register *******************/
#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
#define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /*!< V1.8 power domain reset flag */
#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
/* Old Bit definition maintained for legacy purpose */
#define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
/******************* Bit definition for RCC_AHBRSTR register ***************/
#define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA clock reset */
#define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB clock reset */
#define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC clock reset */
#define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00100000) /*!< GPIOD clock reset */
#define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /*!< GPIOF clock reset */
/******************* Bit definition for RCC_CFGR2 register *****************/
/*!< PREDIV configuration */
#define RCC_CFGR2_PREDIV ((uint32_t)0x0000000F) /*!< PREDIV[3:0] bits */
#define RCC_CFGR2_PREDIV_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define RCC_CFGR2_PREDIV_1 ((uint32_t)0x00000002) /*!< Bit 1 */
#define RCC_CFGR2_PREDIV_2 ((uint32_t)0x00000004) /*!< Bit 2 */
#define RCC_CFGR2_PREDIV_3 ((uint32_t)0x00000008) /*!< Bit 3 */
#define RCC_CFGR2_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< PREDIV input clock not divided */
#define RCC_CFGR2_PREDIV_DIV2 ((uint32_t)0x00000001) /*!< PREDIV input clock divided by 2 */
#define RCC_CFGR2_PREDIV_DIV3 ((uint32_t)0x00000002) /*!< PREDIV input clock divided by 3 */
#define RCC_CFGR2_PREDIV_DIV4 ((uint32_t)0x00000003) /*!< PREDIV input clock divided by 4 */
#define RCC_CFGR2_PREDIV_DIV5 ((uint32_t)0x00000004) /*!< PREDIV input clock divided by 5 */
#define RCC_CFGR2_PREDIV_DIV6 ((uint32_t)0x00000005) /*!< PREDIV input clock divided by 6 */
#define RCC_CFGR2_PREDIV_DIV7 ((uint32_t)0x00000006) /*!< PREDIV input clock divided by 7 */
#define RCC_CFGR2_PREDIV_DIV8 ((uint32_t)0x00000007) /*!< PREDIV input clock divided by 8 */
#define RCC_CFGR2_PREDIV_DIV9 ((uint32_t)0x00000008) /*!< PREDIV input clock divided by 9 */
#define RCC_CFGR2_PREDIV_DIV10 ((uint32_t)0x00000009) /*!< PREDIV input clock divided by 10 */
#define RCC_CFGR2_PREDIV_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV input clock divided by 11 */
#define RCC_CFGR2_PREDIV_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV input clock divided by 12 */
#define RCC_CFGR2_PREDIV_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV input clock divided by 13 */
#define RCC_CFGR2_PREDIV_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV input clock divided by 14 */
#define RCC_CFGR2_PREDIV_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV input clock divided by 15 */
#define RCC_CFGR2_PREDIV_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV input clock divided by 16 */
/******************* Bit definition for RCC_CFGR3 register *****************/
/*!< USART1 Clock source selection */
#define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */
#define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
#define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART1 clock source */
#define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
#define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
#define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
/*!< I2C1 Clock source selection */
#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
#define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */
#define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
/******************* Bit definition for RCC_CR2 register *******************/
#define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /*!< Internal High Speed 14MHz clock enable */
#define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /*!< Internal High Speed 14MHz clock ready flag */
#define RCC_CR2_HSI14DIS ((uint32_t)0x00000004) /*!< Internal High Speed 14MHz clock disable */
#define RCC_CR2_HSI14TRIM ((uint32_t)0x000000F8) /*!< Internal High Speed 14MHz clock trimming */
#define RCC_CR2_HSI14CAL ((uint32_t)0x0000FF00) /*!< Internal High Speed 14MHz clock Calibration */
/*****************************************************************************/
/* */
/* Real-Time Clock (RTC) */
/* */
/*****************************************************************************/
/******************** Bits definition for RTC_TR register ******************/
#define RTC_TR_PM ((uint32_t)0x00400000)
#define RTC_TR_HT ((uint32_t)0x00300000)
#define RTC_TR_HT_0 ((uint32_t)0x00100000)
#define RTC_TR_HT_1 ((uint32_t)0x00200000)
#define RTC_TR_HU ((uint32_t)0x000F0000)
#define RTC_TR_HU_0 ((uint32_t)0x00010000)
#define RTC_TR_HU_1 ((uint32_t)0x00020000)
#define RTC_TR_HU_2 ((uint32_t)0x00040000)
#define RTC_TR_HU_3 ((uint32_t)0x00080000)
#define RTC_TR_MNT ((uint32_t)0x00007000)
#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
#define RTC_TR_MNU ((uint32_t)0x00000F00)
#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
#define RTC_TR_ST ((uint32_t)0x00000070)
#define RTC_TR_ST_0 ((uint32_t)0x00000010)
#define RTC_TR_ST_1 ((uint32_t)0x00000020)
#define RTC_TR_ST_2 ((uint32_t)0x00000040)
#define RTC_TR_SU ((uint32_t)0x0000000F)
#define RTC_TR_SU_0 ((uint32_t)0x00000001)
#define RTC_TR_SU_1 ((uint32_t)0x00000002)
#define RTC_TR_SU_2 ((uint32_t)0x00000004)
#define RTC_TR_SU_3 ((uint32_t)0x00000008)
/******************** Bits definition for RTC_DR register ******************/
#define RTC_DR_YT ((uint32_t)0x00F00000)
#define RTC_DR_YT_0 ((uint32_t)0x00100000)
#define RTC_DR_YT_1 ((uint32_t)0x00200000)
#define RTC_DR_YT_2 ((uint32_t)0x00400000)
#define RTC_DR_YT_3 ((uint32_t)0x00800000)
#define RTC_DR_YU ((uint32_t)0x000F0000)
#define RTC_DR_YU_0 ((uint32_t)0x00010000)
#define RTC_DR_YU_1 ((uint32_t)0x00020000)
#define RTC_DR_YU_2 ((uint32_t)0x00040000)
#define RTC_DR_YU_3 ((uint32_t)0x00080000)
#define RTC_DR_WDU ((uint32_t)0x0000E000)
#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
#define RTC_DR_MT ((uint32_t)0x00001000)
#define RTC_DR_MU ((uint32_t)0x00000F00)
#define RTC_DR_MU_0 ((uint32_t)0x00000100)
#define RTC_DR_MU_1 ((uint32_t)0x00000200)
#define RTC_DR_MU_2 ((uint32_t)0x00000400)
#define RTC_DR_MU_3 ((uint32_t)0x00000800)
#define RTC_DR_DT ((uint32_t)0x00000030)
#define RTC_DR_DT_0 ((uint32_t)0x00000010)
#define RTC_DR_DT_1 ((uint32_t)0x00000020)
#define RTC_DR_DU ((uint32_t)0x0000000F)
#define RTC_DR_DU_0 ((uint32_t)0x00000001)
#define RTC_DR_DU_1 ((uint32_t)0x00000002)
#define RTC_DR_DU_2 ((uint32_t)0x00000004)
#define RTC_DR_DU_3 ((uint32_t)0x00000008)
/******************** Bits definition for RTC_CR register ******************/
#define RTC_CR_COE ((uint32_t)0x00800000)
#define RTC_CR_OSEL ((uint32_t)0x00600000)
#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
#define RTC_CR_POL ((uint32_t)0x00100000)
#define RTC_CR_COSEL ((uint32_t)0x00080000)
#define RTC_CR_BCK ((uint32_t)0x00040000)
#define RTC_CR_SUB1H ((uint32_t)0x00020000)
#define RTC_CR_ADD1H ((uint32_t)0x00010000)
#define RTC_CR_TSIE ((uint32_t)0x00008000)
#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
#define RTC_CR_TSE ((uint32_t)0x00000800)
#define RTC_CR_ALRAE ((uint32_t)0x00000100)
#define RTC_CR_FMT ((uint32_t)0x00000040)
#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
#define RTC_CR_REFCKON ((uint32_t)0x00000010)
#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
/******************** Bits definition for RTC_ISR register *****************/
#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
#define RTC_ISR_TSF ((uint32_t)0x00000800)
#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
#define RTC_ISR_INIT ((uint32_t)0x00000080)
#define RTC_ISR_INITF ((uint32_t)0x00000040)
#define RTC_ISR_RSF ((uint32_t)0x00000020)
#define RTC_ISR_INITS ((uint32_t)0x00000010)
#define RTC_ISR_SHPF ((uint32_t)0x00000008)
#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
/******************** Bits definition for RTC_PRER register ****************/
#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
/******************** Bits definition for RTC_ALRMAR register **************/
#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
/******************** Bits definition for RTC_WPR register *****************/
#define RTC_WPR_KEY ((uint32_t)0x000000FF)
/******************** Bits definition for RTC_SSR register *****************/
#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
/******************** Bits definition for RTC_SHIFTR register **************/
#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
/******************** Bits definition for RTC_TSTR register ****************/
#define RTC_TSTR_PM ((uint32_t)0x00400000)
#define RTC_TSTR_HT ((uint32_t)0x00300000)
#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
#define RTC_TSTR_HU ((uint32_t)0x000F0000)
#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
#define RTC_TSTR_MNT ((uint32_t)0x00007000)
#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
#define RTC_TSTR_ST ((uint32_t)0x00000070)
#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
#define RTC_TSTR_SU ((uint32_t)0x0000000F)
#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
/******************** Bits definition for RTC_TSDR register ****************/
#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
#define RTC_TSDR_MT ((uint32_t)0x00001000)
#define RTC_TSDR_MU ((uint32_t)0x00000F00)
#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
#define RTC_TSDR_DT ((uint32_t)0x00000030)
#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
#define RTC_TSDR_DU ((uint32_t)0x0000000F)
#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
/******************** Bits definition for RTC_TSSSR register ***************/
#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
/******************** Bits definition for RTC_CALR register ****************/
#define RTC_CALR_CALP ((uint32_t)0x00008000)
#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
#define RTC_CALR_CALM ((uint32_t)0x000001FF)
#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
/******************** Bits definition for RTC_TAFCR register ***************/
#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
/******************** Bits definition for RTC_ALRMASSR register ************/
#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
/******************** Bits definition for RTC_BKP0R register ***************/
#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
/******************** Bits definition for RTC_BKP1R register ***************/
#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
/******************** Bits definition for RTC_BKP2R register ***************/
#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
/******************** Bits definition for RTC_BKP3R register ***************/
#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
/******************** Bits definition for RTC_BKP4R register ***************/
#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
/******************** Number of backup registers ******************************/
#define RTC_BKP_NUMBER ((uint32_t)0x00000005)
/*****************************************************************************/
/* */
/* Serial Peripheral Interface (SPI) */
/* */
/*****************************************************************************/
/******************* Bit definition for SPI_CR1 register *******************/
#define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
#define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
#define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
#define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
#define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
#define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
#define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
#define SPI_CR1_CRCL ((uint32_t)0x00000800) /*!< CRC Length */
#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
/******************* Bit definition for SPI_CR2 register *******************/
#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
#define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
#define SPI_CR2_NSSP ((uint32_t)0x00000008) /*!< NSS pulse management Enable */
#define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
#define SPI_CR2_DS ((uint32_t)0x00000F00) /*!< DS[3:0] Data Size */
#define SPI_CR2_DS_0 ((uint32_t)0x00000100) /*!< Bit 0 */
#define SPI_CR2_DS_1 ((uint32_t)0x00000200) /*!< Bit 1 */
#define SPI_CR2_DS_2 ((uint32_t)0x00000400) /*!< Bit 2 */
#define SPI_CR2_DS_3 ((uint32_t)0x00000800) /*!< Bit 3 */
#define SPI_CR2_FRXTH ((uint32_t)0x00001000) /*!< FIFO reception Threshold */
#define SPI_CR2_LDMARX ((uint32_t)0x00002000) /*!< Last DMA transfer for reception */
#define SPI_CR2_LDMATX ((uint32_t)0x00004000) /*!< Last DMA transfer for transmission */
/******************** Bit definition for SPI_SR register *******************/
#define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
#define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
#define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
#define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
#define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
#define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
#define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
#define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
#define SPI_SR_FRLVL ((uint32_t)0x00000600) /*!< FIFO Reception Level */
#define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
#define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
#define SPI_SR_FTLVL ((uint32_t)0x00001800) /*!< FIFO Transmission Level */
#define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /*!< Bit 0 */
#define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /*!< Bit 1 */
/******************** Bit definition for SPI_DR register *******************/
#define SPI_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data Register */
/******************* Bit definition for SPI_CRCPR register *****************/
#define SPI_CRCPR_CRCPOLY ((uint32_t)0xFFFFFFFF) /*!< CRC polynomial register */
/****************** Bit definition for SPI_RXCRCR register *****************/
#define SPI_RXCRCR_RXCRC ((uint32_t)0xFFFFFFFF) /*!< Rx CRC Register */
/****************** Bit definition for SPI_TXCRCR register *****************/
#define SPI_TXCRCR_TXCRC ((uint32_t)0xFFFFFFFF) /*!< Tx CRC Register */
/****************** Bit definition for SPI_I2SCFGR register ****************/
#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
/****************** Bit definition for SPI_I2SPR register ******************/
#define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
#define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
#define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
/*****************************************************************************/
/* */
/* System Configuration (SYSCFG) */
/* */
/*****************************************************************************/
/***************** Bit definition for SYSCFG_CFGR1 register ****************/
#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
#define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x00001F00) /*!< DMA remap mask */
#define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /*!< ADC DMA remap */
#define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
#define SYSCFG_CFGR1_USART1RX_DMA_RMP ((uint32_t)0x00000400) /*!< USART1 RX DMA remap */
#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
#define SYSCFG_CFGR1_I2C_FMP_PB6 ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
#define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
#define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
#define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
#define SYSCFG_CFGR1_I2C_FMP_I2C1 ((uint32_t)0x00100000) /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 */
#define SYSCFG_CFGR1_I2C_FMP_PA9 ((uint32_t)0x00400000) /*!< Enable Fast Mode Plus on PA9 */
#define SYSCFG_CFGR1_I2C_FMP_PA10 ((uint32_t)0x00800000) /*!< Enable Fast Mode Plus on PA10 */
/***************** Bit definition for SYSCFG_EXTICR1 register **************/
#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
/**
* @brief EXTI0 configuration
*/
#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */
/**
* @brief EXTI1 configuration
*/
#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */
/**
* @brief EXTI2 configuration
*/
#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */
/**
* @brief EXTI3 configuration
*/
#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register **************/
#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
/**
* @brief EXTI4 configuration
*/
#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */
/**
* @brief EXTI5 configuration
*/
#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */
/**
* @brief EXTI6 configuration
*/
#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */
/**
* @brief EXTI7 configuration
*/
#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */
/***************** Bit definition for SYSCFG_EXTICR3 register **************/
#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
/**
* @brief EXTI8 configuration
*/
#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */
/**
* @brief EXTI9 configuration
*/
#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */
/**
* @brief EXTI10 configuration
*/
#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */
/**
* @brief EXTI11 configuration
*/
#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */
/***************** Bit definition for SYSCFG_EXTICR4 register **************/
#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
/**
* @brief EXTI12 configuration
*/
#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */
/**
* @brief EXTI13 configuration
*/
#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */
/**
* @brief EXTI14 configuration
*/
#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */
/**
* @brief EXTI15 configuration
*/
#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */
/***************** Bit definition for SYSCFG_CFGR2 register ****************/
#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
#define SYSCFG_CFGR2_SRAM_PEF ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
#define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF /*!< SRAM Parity error flag (define maintained for legacy purpose) */
/*****************************************************************************/
/* */
/* Timers (TIM) */
/* */
/*****************************************************************************/
/******************* Bit definition for TIM_CR1 register *******************/
#define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
#define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
#define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
#define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
#define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
#define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
#define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
#define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
#define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
#define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
#define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
/******************* Bit definition for TIM_CR2 register *******************/
#define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
#define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
#define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
#define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
#define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
#define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
#define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
#define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
#define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
#define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
#define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
#define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
#define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
/******************* Bit definition for TIM_SMCR register ******************/
#define TIM_SMCR_SMS ((uint32_t)0x00000007) /*!<SMS[2:0] bits (Slave mode selection) */
#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
#define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
#define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
#define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
#define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
#define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
#define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
/******************* Bit definition for TIM_DIER register ******************/
#define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
#define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
#define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
#define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
#define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
#define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */
#define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
#define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */
#define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
#define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
#define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
#define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
#define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
#define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */
#define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
/******************** Bit definition for TIM_SR register *******************/
#define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
#define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
#define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
#define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
#define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
#define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
#define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
#define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
#define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
#define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
#define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
#define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
/******************* Bit definition for TIM_EGR register *******************/
#define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
#define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
#define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
#define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
#define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
#define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
#define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
#define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
/****************** Bit definition for TIM_CCMR1 register ******************/
#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
#define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
#define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
/*---------------------------------------------------------------------------*/
#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
/****************** Bit definition for TIM_CCMR2 register ******************/
#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
#define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
#define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
/*---------------------------------------------------------------------------*/
#define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
#define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
#define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
#define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
#define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
#define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
#define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
#define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
#define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
#define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
/******************* Bit definition for TIM_CCER register ******************/
#define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
#define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
#define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
#define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
#define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
#define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
#define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
#define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
/******************* Bit definition for TIM_CNT register *******************/
#define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
/******************* Bit definition for TIM_PSC register *******************/
#define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
/******************* Bit definition for TIM_ARR register *******************/
#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
/******************* Bit definition for TIM_RCR register *******************/
#define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
/******************* Bit definition for TIM_CCR1 register ******************/
#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
/******************* Bit definition for TIM_CCR2 register ******************/
#define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
/******************* Bit definition for TIM_CCR3 register ******************/
#define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
/******************* Bit definition for TIM_CCR4 register ******************/
#define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
/******************* Bit definition for TIM_BDTR register ******************/
#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
#define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable */
#define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity */
#define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
#define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
/******************* Bit definition for TIM_DCR register *******************/
#define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
#define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
#define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
#define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
#define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
/******************* Bit definition for TIM_DMAR register ******************/
#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
/******************* Bit definition for TIM14_OR register ********************/
#define TIM14_OR_TI1_RMP ((uint32_t)0x00000003) /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
#define TIM14_OR_TI1_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define TIM14_OR_TI1_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
/******************************************************************************/
/* */
/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
/* */
/******************************************************************************/
/****************** Bit definition for USART_CR1 register *******************/
#define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
#define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
#define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
#define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
#define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
#define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
#define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
#define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
#define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
#define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
#define USART_CR1_M0 ((uint32_t)0x00001000) /*!< Word length bit 0 */
#define USART_CR1_M ((uint32_t)0x00001000) /*!< SmartCard Length */
#define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
#define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
#define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
#define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
#define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
#define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
#define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
#define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
#define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
#define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
#define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
#define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
#define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
#define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
#define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
#define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
#define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
/****************** Bit definition for USART_CR2 register *******************/
#define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
#define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
#define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
#define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
#define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
#define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
#define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
#define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
#define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
#define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
#define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
#define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
#define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
#define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
#define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
#define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
#define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
#define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
/****************** Bit definition for USART_CR3 register *******************/
#define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
#define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
#define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
#define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
#define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
#define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
#define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
#define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
#define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
#define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
#define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
#define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
#define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
#define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
#define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
#define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
#define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
#define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
#define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
#define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
#define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
/****************** Bit definition for USART_BRR register *******************/
#define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
#define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
/****************** Bit definition for USART_GTPR register ******************/
#define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
#define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< GT[7:0] bits (Guard time value) */
/******************* Bit definition for USART_RTOR register *****************/
#define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
#define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
/******************* Bit definition for USART_RQR register ******************/
#define USART_RQR_ABRRQ ((uint32_t)0x00000001) /*!< Auto-Baud Rate Request */
#define USART_RQR_SBKRQ ((uint32_t)0x00000002) /*!< Send Break Request */
#define USART_RQR_MMRQ ((uint32_t)0x00000004) /*!< Mute Mode Request */
#define USART_RQR_RXFRQ ((uint32_t)0x00000008) /*!< Receive Data flush Request */
#define USART_RQR_TXFRQ ((uint32_t)0x00000010) /*!< Transmit data flush Request */
/******************* Bit definition for USART_ISR register ******************/
#define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
#define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
#define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
#define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
#define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
#define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
#define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
#define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
#define USART_ISR_LBDF ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
#define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
#define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
#define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
#define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
#define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
#define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
#define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
#define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
#define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
#define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
#define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
#define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
#define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
/******************* Bit definition for USART_ICR register ******************/
#define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
#define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
#define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
#define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
#define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
#define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
#define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
#define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
#define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
#define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
#define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
#define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
/******************* Bit definition for USART_RDR register ******************/
#define USART_RDR_RDR ((uint16_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */
/******************* Bit definition for USART_TDR register ******************/
#define USART_TDR_TDR ((uint16_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */
/******************************************************************************/
/* */
/* Window WATCHDOG (WWDG) */
/* */
/******************************************************************************/
/******************* Bit definition for WWDG_CR register ********************/
#define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
#define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
#define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
#define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
#define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
#define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
#define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
#define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
#define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
/******************* Bit definition for WWDG_CFR register *******************/
#define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
#define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
#define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
#define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
#define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
#define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
#define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
#define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
#define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
#define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
#define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
#define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
/******************* Bit definition for WWDG_SR register ********************/
#define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
/**
* @}
*/
/**
* @}
*/
/** @addtogroup Exported_macro
* @{
*/
/****************************** ADC Instances *********************************/
#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
/****************************** CRC Instances *********************************/
#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
/******************************* DMA Instances ******************************/
#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
((INSTANCE) == DMA1_Channel2) || \
((INSTANCE) == DMA1_Channel3) || \
((INSTANCE) == DMA1_Channel4) || \
((INSTANCE) == DMA1_Channel5))
/****************************** GPIO Instances ********************************/
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
((INSTANCE) == GPIOB) || \
((INSTANCE) == GPIOC) || \
((INSTANCE) == GPIOF))
/****************************** GPIO Lock Instances ****************************/
#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
((INSTANCE) == GPIOB))
/****************************** I2C Instances *********************************/
#define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
/****************************** I2S Instances *********************************/
#define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
/****************************** IWDG Instances ********************************/
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
/****************************** RTC Instances *********************************/
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
/****************************** SMBUS Instances *********************************/
#define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
/****************************** SPI Instances *********************************/
#define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
/****************************** TIM Instances *********************************/
#define IS_TIM_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM14) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
#define IS_TIM_CC1_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM14) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
#define IS_TIM_CC2_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3))
#define IS_TIM_CC3_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3))
#define IS_TIM_CC4_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3))
#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3))
#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3))
#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3))
#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3))
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3))
#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3))
#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1))
#define IS_TIM_XOR_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3))
#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3))
#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3))
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
((INSTANCE) == TIM2)
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
((((INSTANCE) == TIM1) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM2) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM3) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM14) && \
(((CHANNEL) == TIM_CHANNEL_1))) \
|| \
(((INSTANCE) == TIM16) && \
(((CHANNEL) == TIM_CHANNEL_1))) \
|| \
(((INSTANCE) == TIM17) && \
(((CHANNEL) == TIM_CHANNEL_1))))
#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
((((INSTANCE) == TIM1) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3))) \
|| \
(((INSTANCE) == TIM16) && \
((CHANNEL) == TIM_CHANNEL_1)) \
|| \
(((INSTANCE) == TIM17) && \
((CHANNEL) == TIM_CHANNEL_1)))
#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3))
#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM14) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
#define IS_TIM_DMA_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
#define IS_TIM_REMAP_INSTANCE(INSTANCE)\
((INSTANCE) == TIM14)
/*********************** UART Instances : IRDA mode ***************************/
#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1))
/********************* UART Instances : Smard card mode ***********************/
#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1))
/******************** USART Instances : Synchronous mode **********************/
#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1))
/******************** USART Instances : auto Baud rate detection **************/
#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1))
/******************** UART Instances : Asynchronous mode **********************/
#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1))
/******************** UART Instances : Half-Duplex mode **********************/
#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
/****************** UART Instances : Hardware Flow control ********************/
#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1))
/****************** UART Instances : LIN mode ********************/
#define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
/****************** UART Instances : wakeup from stop mode ********************/
#define IS_UART_WAKEUP_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
/****************** UART Instances : Auto Baud Rate detection ********************/
#define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1))
/****************** UART Instances : Driver enable detection ********************/
#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1))
/****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
/**
* @}
*/
/******************************************************************************/
/* For a painless codes migration between the STM32F0xx device product */
/* lines, the aliases defined below are put in place to overcome the */
/* differences in the interrupt handlers and IRQn definitions. */
/* No need to update developed interrupt code when moving across */
/* product lines within the same STM32F0 Family */
/******************************************************************************/
/* Aliases for __IRQn */
#define PVD_VDDIO2_IRQn PVD_IRQn
#define RCC_CRS_IRQn RCC_IRQn
#define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
#define ADC1_COMP_IRQn ADC1_IRQn
/* Aliases for __IRQHandler */
#define PVD_VDDIO2_IRQHandler PVD_IRQHandler
#define RCC_CRS_IRQHandler RCC_IRQHandler
#define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler
#define ADC1_COMP_IRQHandler ADC1_IRQHandler
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __STM32F031x6_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|